Summary for Variable clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53702 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
1886 | 
1 | 
 | 
 | 
T12 | 
6 | 
 | 
T18 | 
5 | 
 | 
T19 | 
47 | 
Summary for Variable clk_byp_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54814 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
774 | 
1 | 
 | 
 | 
T62 | 
10 | 
 | 
T63 | 
26 | 
 | 
T64 | 
19 | 
Summary for Variable count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53564 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
2024 | 
1 | 
 | 
 | 
T11 | 
10 | 
 | 
T13 | 
9 | 
 | 
T15 | 
5 | 
Summary for Variable count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53473 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
2115 | 
1 | 
 | 
 | 
T11 | 
9 | 
 | 
T13 | 
7 | 
 | 
T15 | 
5 | 
Summary for Variable count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53508 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
2080 | 
1 | 
 | 
 | 
T11 | 
5 | 
 | 
T13 | 
9 | 
 | 
T15 | 
6 | 
Summary for Variable err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
2 | 
0 | 
2 | 
100.00 | 
User Defined Bins for err_inj_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| err_inj | 
50842 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T11 | 
72 | 
 | 
T12 | 
74 | 
| no_err_inj | 
4746 | 
1 | 
 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
Summary for Variable flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53757 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
1831 | 
1 | 
 | 
 | 
T12 | 
4 | 
 | 
T18 | 
9 | 
 | 
T19 | 
46 | 
Summary for Variable flash_rma_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54861 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
727 | 
1 | 
 | 
 | 
T62 | 
9 | 
 | 
T63 | 
22 | 
 | 
T64 | 
11 | 
Summary for Variable jtag_csr_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for jtag_csr_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
38378 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T11 | 
72 | 
| auto[1] | 
17210 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
 | 
T15 | 
58 | 
Summary for Variable kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53517 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
2071 | 
1 | 
 | 
 | 
T11 | 
9 | 
 | 
T13 | 
10 | 
 | 
T15 | 
6 | 
Summary for Variable lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53546 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
2042 | 
1 | 
 | 
 | 
T11 | 
8 | 
 | 
T13 | 
7 | 
 | 
T15 | 
5 | 
Summary for Variable otp_lc_data_i_valid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53486 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
2102 | 
1 | 
 | 
 | 
T11 | 
10 | 
 | 
T13 | 
10 | 
 | 
T15 | 
14 | 
Summary for Variable otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_partition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53731 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
1857 | 
1 | 
 | 
 | 
T12 | 
10 | 
 | 
T18 | 
9 | 
 | 
T19 | 
51 | 
Summary for Variable otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_prog_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53125 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
2463 | 
1 | 
 | 
 | 
T54 | 
8 | 
 | 
T19 | 
55 | 
 | 
T61 | 
8 | 
Summary for Variable otp_rma_token_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54832 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
756 | 
1 | 
 | 
 | 
T62 | 
11 | 
 | 
T63 | 
15 | 
 | 
T64 | 
15 | 
Summary for Variable otp_secrets_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54871 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
717 | 
1 | 
 | 
 | 
T62 | 
12 | 
 | 
T63 | 
13 | 
 | 
T64 | 
10 | 
Summary for Variable otp_test_tokens_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54852 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
736 | 
1 | 
 | 
 | 
T62 | 
8 | 
 | 
T63 | 
20 | 
 | 
T64 | 
19 | 
Summary for Variable post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for post_trans_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53207 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
2381 | 
1 | 
 | 
 | 
T76 | 
12 | 
 | 
T18 | 
37 | 
 | 
T19 | 
113 | 
Summary for Variable security_escalation_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for security_escalation_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
51720 | 
1 | 
 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
| auto[1] | 
3868 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T51 | 
65 | 
 | 
T39 | 
100 | 
Summary for Variable state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53583 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
2005 | 
1 | 
 | 
 | 
T11 | 
9 | 
 | 
T13 | 
13 | 
 | 
T15 | 
5 | 
Summary for Variable state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53548 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
2040 | 
1 | 
 | 
 | 
T11 | 
6 | 
 | 
T13 | 
7 | 
 | 
T15 | 
4 | 
Summary for Variable state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53517 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
2071 | 
1 | 
 | 
 | 
T11 | 
6 | 
 | 
T13 | 
9 | 
 | 
T15 | 
8 | 
Summary for Variable token_invalid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_invalid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53672 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
1916 | 
1 | 
 | 
 | 
T12 | 
16 | 
 | 
T18 | 
6 | 
 | 
T19 | 
46 | 
Summary for Variable token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mismatch_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
49943 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
5645 | 
1 | 
 | 
 | 
T12 | 
13 | 
 | 
T18 | 
9 | 
 | 
T19 | 
50 | 
Summary for Variable token_mux_ctrl_redun_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
51961 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
3627 | 
1 | 
 | 
 | 
T27 | 
69 | 
 | 
T34 | 
60 | 
 | 
T35 | 
60 | 
Summary for Variable token_mux_digest_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
1 | 
1 | 
50.00  | 
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | 
0 | 
1 | 
1 | 
 | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
55588 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
Summary for Variable token_response_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_response_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53677 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
1911 | 
1 | 
 | 
 | 
T12 | 
7 | 
 | 
T18 | 
12 | 
 | 
T19 | 
33 | 
Summary for Variable transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53814 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
1774 | 
1 | 
 | 
 | 
T12 | 
8 | 
 | 
T18 | 
11 | 
 | 
T19 | 
38 | 
Summary for Variable transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53784 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[1] | 
1804 | 
1 | 
 | 
 | 
T12 | 
10 | 
 | 
T18 | 
7 | 
 | 
T19 | 
49 | 
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
| post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
err_inj | 
49643 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T11 | 
72 | 
 | 
T12 | 
74 | 
| auto[0] | 
no_err_inj | 
3564 | 
1 | 
 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
| auto[1] | 
err_inj | 
1199 | 
1 | 
 | 
 | 
T76 | 
5 | 
 | 
T18 | 
19 | 
 | 
T19 | 
53 | 
| auto[1] | 
no_err_inj | 
1182 | 
1 | 
 | 
 | 
T76 | 
7 | 
 | 
T18 | 
18 | 
 | 
T19 | 
60 | 
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
| post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
51297 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[0] | 
auto[1] | 
1910 | 
1 | 
 | 
 | 
T11 | 
6 | 
 | 
T13 | 
7 | 
 | 
T15 | 
4 | 
| auto[1] | 
auto[0] | 
2251 | 
1 | 
 | 
 | 
T76 | 
12 | 
 | 
T18 | 
32 | 
 | 
T19 | 
106 | 
| auto[1] | 
auto[1] | 
130 | 
1 | 
 | 
 | 
T18 | 
5 | 
 | 
T19 | 
7 | 
 | 
T40 | 
1 | 
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
| post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
51301 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[0] | 
auto[1] | 
1906 | 
1 | 
 | 
 | 
T11 | 
8 | 
 | 
T13 | 
7 | 
 | 
T15 | 
5 | 
| auto[1] | 
auto[0] | 
2245 | 
1 | 
 | 
 | 
T76 | 
11 | 
 | 
T18 | 
35 | 
 | 
T19 | 
110 | 
| auto[1] | 
auto[1] | 
136 | 
1 | 
 | 
 | 
T76 | 
1 | 
 | 
T18 | 
2 | 
 | 
T19 | 
3 | 
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
| post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
51271 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[0] | 
auto[1] | 
1936 | 
1 | 
 | 
 | 
T11 | 
6 | 
 | 
T13 | 
9 | 
 | 
T15 | 
8 | 
| auto[1] | 
auto[0] | 
2246 | 
1 | 
 | 
 | 
T76 | 
12 | 
 | 
T18 | 
34 | 
 | 
T19 | 
105 | 
| auto[1] | 
auto[1] | 
135 | 
1 | 
 | 
 | 
T18 | 
3 | 
 | 
T19 | 
8 | 
 | 
T40 | 
2 | 
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
| post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
51230 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[0] | 
auto[1] | 
1977 | 
1 | 
 | 
 | 
T11 | 
9 | 
 | 
T13 | 
7 | 
 | 
T15 | 
5 | 
| auto[1] | 
auto[0] | 
2243 | 
1 | 
 | 
 | 
T76 | 
11 | 
 | 
T18 | 
37 | 
 | 
T19 | 
107 | 
| auto[1] | 
auto[1] | 
138 | 
1 | 
 | 
 | 
T76 | 
1 | 
 | 
T19 | 
6 | 
 | 
T86 | 
1 | 
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
| post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
51265 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[0] | 
auto[1] | 
1942 | 
1 | 
 | 
 | 
T11 | 
5 | 
 | 
T13 | 
9 | 
 | 
T15 | 
6 | 
| auto[1] | 
auto[0] | 
2243 | 
1 | 
 | 
 | 
T76 | 
10 | 
 | 
T18 | 
34 | 
 | 
T19 | 
109 | 
| auto[1] | 
auto[1] | 
138 | 
1 | 
 | 
 | 
T76 | 
2 | 
 | 
T18 | 
3 | 
 | 
T19 | 
4 | 
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
| post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
51314 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T4 | 
4 | 
| auto[0] | 
auto[1] | 
1893 | 
1 | 
 | 
 | 
T11 | 
10 | 
 | 
T13 | 
9 | 
 | 
T15 | 
5 | 
| auto[1] | 
auto[0] | 
2250 | 
1 | 
 | 
 | 
T76 | 
11 | 
 | 
T18 | 
37 | 
 | 
T19 | 
107 | 
| auto[1] | 
auto[1] | 
131 | 
1 | 
 | 
 | 
T76 | 
1 | 
 | 
T19 | 
6 | 
 | 
T78 | 
1 | 
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
| jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37265 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T11 | 
72 | 
| auto[0] | 
auto[1] | 
1113 | 
1 | 
 | 
 | 
T12 | 
6 | 
 | 
T18 | 
5 | 
 | 
T19 | 
38 | 
| auto[1] | 
auto[0] | 
16437 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
 | 
T15 | 
58 | 
| auto[1] | 
auto[1] | 
773 | 
1 | 
 | 
 | 
T19 | 
9 | 
 | 
T44 | 
12 | 
 | 
T61 | 
14 | 
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
| jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37324 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T11 | 
72 | 
| auto[0] | 
auto[1] | 
1054 | 
1 | 
 | 
 | 
T12 | 
4 | 
 | 
T18 | 
9 | 
 | 
T19 | 
40 | 
| auto[1] | 
auto[0] | 
16433 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
 | 
T15 | 
58 | 
| auto[1] | 
auto[1] | 
777 | 
1 | 
 | 
 | 
T19 | 
6 | 
 | 
T44 | 
13 | 
 | 
T61 | 
9 | 
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
| jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
36885 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T11 | 
72 | 
| auto[0] | 
auto[1] | 
1493 | 
1 | 
 | 
 | 
T54 | 
8 | 
 | 
T19 | 
32 | 
 | 
T61 | 
1 | 
| auto[1] | 
auto[0] | 
16240 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
 | 
T15 | 
58 | 
| auto[1] | 
auto[1] | 
970 | 
1 | 
 | 
 | 
T19 | 
23 | 
 | 
T61 | 
7 | 
 | 
T216 | 
11 | 
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
| jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37292 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T11 | 
72 | 
| auto[0] | 
auto[1] | 
1086 | 
1 | 
 | 
 | 
T12 | 
10 | 
 | 
T18 | 
9 | 
 | 
T19 | 
38 | 
| auto[1] | 
auto[0] | 
16439 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
 | 
T15 | 
58 | 
| auto[1] | 
auto[1] | 
771 | 
1 | 
 | 
 | 
T19 | 
13 | 
 | 
T44 | 
13 | 
 | 
T61 | 
14 | 
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
| jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
33500 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T11 | 
72 | 
| auto[0] | 
auto[1] | 
4878 | 
1 | 
 | 
 | 
T12 | 
13 | 
 | 
T18 | 
9 | 
 | 
T19 | 
36 | 
| auto[1] | 
auto[0] | 
16443 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
 | 
T15 | 
58 | 
| auto[1] | 
auto[1] | 
767 | 
1 | 
 | 
 | 
T19 | 
14 | 
 | 
T44 | 
9 | 
 | 
T61 | 
12 | 
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
| jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37197 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T11 | 
66 | 
| auto[0] | 
auto[1] | 
1181 | 
1 | 
 | 
 | 
T11 | 
6 | 
 | 
T13 | 
7 | 
 | 
T18 | 
2 | 
| auto[1] | 
auto[0] | 
16351 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
 | 
T15 | 
54 | 
| auto[1] | 
auto[1] | 
859 | 
1 | 
 | 
 | 
T15 | 
4 | 
 | 
T18 | 
3 | 
 | 
T19 | 
34 | 
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
| jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37198 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T11 | 
63 | 
| auto[0] | 
auto[1] | 
1180 | 
1 | 
 | 
 | 
T11 | 
9 | 
 | 
T13 | 
13 | 
 | 
T18 | 
1 | 
| auto[1] | 
auto[0] | 
16385 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
 | 
T15 | 
53 | 
| auto[1] | 
auto[1] | 
825 | 
1 | 
 | 
 | 
T15 | 
5 | 
 | 
T19 | 
38 | 
 | 
T40 | 
8 | 
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37192 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T11 | 
64 | 
| auto[0] | 
auto[1] | 
1186 | 
1 | 
 | 
 | 
T11 | 
8 | 
 | 
T13 | 
7 | 
 | 
T76 | 
1 | 
| auto[1] | 
auto[0] | 
16354 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
 | 
T15 | 
53 | 
| auto[1] | 
auto[1] | 
856 | 
1 | 
 | 
 | 
T15 | 
5 | 
 | 
T18 | 
2 | 
 | 
T19 | 
33 | 
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37183 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T11 | 
63 | 
| auto[0] | 
auto[1] | 
1195 | 
1 | 
 | 
 | 
T11 | 
9 | 
 | 
T13 | 
10 | 
 | 
T18 | 
1 | 
| auto[1] | 
auto[0] | 
16334 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
 | 
T15 | 
52 | 
| auto[1] | 
auto[1] | 
876 | 
1 | 
 | 
 | 
T15 | 
6 | 
 | 
T18 | 
1 | 
 | 
T19 | 
27 | 
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
| jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37192 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T11 | 
63 | 
| auto[0] | 
auto[1] | 
1186 | 
1 | 
 | 
 | 
T11 | 
9 | 
 | 
T13 | 
7 | 
 | 
T76 | 
1 | 
| auto[1] | 
auto[0] | 
16281 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
 | 
T15 | 
53 | 
| auto[1] | 
auto[1] | 
929 | 
1 | 
 | 
 | 
T15 | 
5 | 
 | 
T19 | 
35 | 
 | 
T40 | 
4 | 
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
| jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37237 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T11 | 
62 | 
| auto[0] | 
auto[1] | 
1141 | 
1 | 
 | 
 | 
T11 | 
10 | 
 | 
T13 | 
9 | 
 | 
T76 | 
1 | 
| auto[1] | 
auto[0] | 
16327 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
 | 
T15 | 
53 | 
| auto[1] | 
auto[1] | 
883 | 
1 | 
 | 
 | 
T15 | 
5 | 
 | 
T19 | 
24 | 
 | 
T40 | 
9 | 
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
| jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37364 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T11 | 
72 | 
| auto[0] | 
auto[1] | 
1014 | 
1 | 
 | 
 | 
T12 | 
10 | 
 | 
T18 | 
7 | 
 | 
T19 | 
34 | 
| auto[1] | 
auto[0] | 
16420 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
 | 
T15 | 
58 | 
| auto[1] | 
auto[1] | 
790 | 
1 | 
 | 
 | 
T19 | 
15 | 
 | 
T44 | 
11 | 
 | 
T61 | 
21 | 
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
| jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37395 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T11 | 
72 | 
| auto[0] | 
auto[1] | 
983 | 
1 | 
 | 
 | 
T12 | 
8 | 
 | 
T18 | 
11 | 
 | 
T19 | 
23 | 
| auto[1] | 
auto[0] | 
16419 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
 | 
T15 | 
58 | 
| auto[1] | 
auto[1] | 
791 | 
1 | 
 | 
 | 
T19 | 
15 | 
 | 
T44 | 
11 | 
 | 
T61 | 
14 | 
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
| jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37064 | 
1 | 
 | 
 | 
T2 | 
92 | 
 | 
T3 | 
10 | 
 | 
T11 | 
72 | 
| auto[0] | 
auto[1] | 
1314 | 
1 | 
 | 
 | 
T76 | 
12 | 
 | 
T18 | 
22 | 
 | 
T19 | 
48 | 
| auto[1] | 
auto[0] | 
16143 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T5 | 
16 | 
 | 
T15 | 
58 | 
| auto[1] | 
auto[1] | 
1067 | 
1 | 
 | 
 | 
T18 | 
15 | 
 | 
T19 | 
65 | 
 | 
T40 | 
11 |