Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109338244

1

T1

5497

T2

39768

T3

34613

auto[1]

1468116

1

T2

13235

T11

2277

T12

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109307319

1

T1

5497

T2

41173

T3

34613

auto[1]

1499041

1

T2

11830

T11

3267

T12

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7819967	1			T1	72		T2	8163		T3	917
auto[IdleSt]	22339486	1			T1	5425		T2	9486		T3	1393
auto[ClkMuxSt]	35860	1			T2	79		T3	9		T4	4
auto[CntIncrSt]	35657	1			T2	79		T3	9		T4	4
auto[CntProgSt]	1936301	1			T2	6155		T3	18		T4	287
auto[TransCheckSt]	27607	1			T2	45		T3	9		T4	4
auto[TokenHashSt]	44308209	1			T2	9720		T3	31068		T4	40
auto[FlashRmaSt]	34763	1			T2	70		T3	34		T4	33
auto[TokenCheck0St]	12629	1			T2	31		T3	9		T4	4
auto[TokenCheck1St]	9380	1			T2	31		T3	9		T4	4
auto[TransProgSt]	502453	1			T2	244		T3	18		T4	302
auto[PostTransSt]	13125504	1			T2	8		T3	1077		T4	1724
auto[ScrapSt]	155557	1			T2	8		T3	43		T5	726
auto[EscalateSt]	7231655	1			T2	18884		T11	8034		T12	884
auto[InvalidSt]	13229209	1			T11	10109		T13	11289		T15	60879

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2123	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13229209	1			T11	10109		T13	11289		T15	60879
EscalateSt	7231655	1			T2	18884		T11	8034		T12	884
ScrapSt	155557	1			T2	8		T3	43		T5	726
PostTransSt	13125504	1			T2	8		T3	1077		T4	1724
TransProgSt	502453	1			T2	244		T3	18		T4	302
TokenCheck1St	9380	1			T2	31		T3	9		T4	4
TokenCheck0St	12629	1			T2	31		T3	9		T4	4
FlashRmaSt	34763	1			T2	70		T3	34		T4	33
TokenHashSt	44308209	1			T2	9720		T3	31068		T4	40
TransCheckSt	27607	1			T2	45		T3	9		T4	4
CntProgSt	1936301	1			T2	6155		T3	18		T4	287
CntIncrSt	35657	1			T2	79		T3	9		T4	4
ClkMuxSt	35860	1			T2	79		T3	9		T4	4
IdleSt	22339486	1			T1	5425		T2	9486		T3	1393
ResetSt	7819967	1			T1	72		T2	8163		T3	917
arcs[ResetSt=>IdleSt]	55650	1			T1	1		T2	88		T3	10
arcs[IdleSt=>ScrapSt]	316	1			T2	2		T3	1		T5	2
arcs[IdleSt=>ClkMuxSt]	35690	1			T2	79		T3	9		T4	4
arcs[ClkMuxSt=>CntIncrSt]	35657	1			T2	79		T3	9		T4	4
arcs[CntIncrSt=>PostTransSt]	1775	1			T12	8		T18	11		T19	38
arcs[CntIncrSt=>CntProgSt]	33827	1			T2	78		T3	9		T4	4
arcs[CntProgSt=>PostTransSt]	5075	1			T12	6		T54	8		T18	5
arcs[CntProgSt=>TransCheckSt]	27607	1			T2	45		T3	9		T4	4
arcs[TransCheckSt=>PostTransSt]	3628	1			T12	10		T27	32		T34	37
arcs[TransCheckSt=>TokenHashSt]	23863	1			T2	45		T3	9		T4	4
arcs[TokenHashSt=>PostTransSt]	10429	1			T12	36		T27	9		T34	7
arcs[TokenHashSt=>FlashRmaSt]	12671	1			T2	31		T3	9		T4	4
arcs[FlashRmaSt=>TokenCheck0St]	12629	1			T2	31		T3	9		T4	4
arcs[TokenCheck0St=>PostTransSt]	3187	1			T12	3		T27	17		T34	11
arcs[TokenCheck0St=>TokenCheck1St]	9380	1			T2	31		T3	9		T4	4
arcs[TokenCheck1St=>PostTransSt]	652	1			T12	1		T27	11		T34	5
arcs[TransProgSt=>PostTransSt]	7874	1			T2	2		T3	9		T4	4
arcs[IdleSt=>EscalateSt]	179	1			T2	6		T51	7		T52	6
arcs[ClkMuxSt=>EscalateSt]	33	1			T51	3		T52	2		T53	2
arcs[CntIncrSt=>EscalateSt]	55	1			T2	1		T39	4		T52	1
arcs[CntProgSt=>EscalateSt]	1145	1			T2	33		T51	15		T39	7
arcs[TransCheckSt=>EscalateSt]	116	1			T51	5		T39	5		T56	1
arcs[TokenHashSt=>EscalateSt]	763	1			T2	14		T51	16		T39	47
arcs[FlashRmaSt=>EscalateSt]	42	1			T39	2		T55	1		T56	1
arcs[TokenCheck0St=>EscalateSt]	62	1			T51	1		T39	3		T52	4
arcs[TokenCheck1St=>EscalateSt]	22	1			T55	2		T58	1		T53	1
arcs[TransProgSt=>EscalateSt]	832	1			T2	29		T51	9		T39	6
arcs[PostTransSt=>EscalateSt]	5401	1			T2	2		T12	6		T51	3
arcs[InvalidSt=>EscalateSt]	15104	1			T11	56		T13	62		T15	36

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7819789	1			T1	72		T2	8160		T3	917
auto[0]	auto[IdleSt]	22339355	1			T1	5425		T2	9481		T3	1393
auto[0]	auto[ClkMuxSt]	35842	1			T2	79		T3	9		T4	4
auto[0]	auto[CntIncrSt]	35624	1			T2	79		T3	9		T4	4
auto[0]	auto[CntProgSt]	1935545	1			T2	6136		T3	18		T4	287
auto[0]	auto[TransCheckSt]	27532	1			T2	45		T3	9		T4	4
auto[0]	auto[TokenHashSt]	44307707	1			T2	9708		T3	31068		T4	40
auto[0]	auto[FlashRmaSt]	34737	1			T2	70		T3	34		T4	33
auto[0]	auto[TokenCheck0St]	12588	1			T2	31		T3	9		T4	4
auto[0]	auto[TokenCheck1St]	9366	1			T2	31		T3	9		T4	4
auto[0]	auto[TransProgSt]	501895	1			T2	222		T3	18		T4	302
auto[0]	auto[PostTransSt]	13122795	1			T2	6		T3	1077		T4	1724
auto[0]	auto[ScrapSt]	155515	1			T2	6		T3	43		T5	726
auto[0]	auto[EscalateSt]	5776124	1			T2	5714		T11	5780		T12	590
auto[0]	auto[InvalidSt]	13221707	1			T11	10086		T13	11262		T15	60867
auto[1]	auto[ResetSt]	178	1			T2	3		T51	3		T39	3
auto[1]	auto[IdleSt]	131	1			T2	5		T51	6		T52	4
auto[1]	auto[ClkMuxSt]	18	1			T51	2		T52	1		T214	3
auto[1]	auto[CntIncrSt]	33	1			T39	3		T52	1		T59	1
auto[1]	auto[CntProgSt]	756	1			T2	19		T51	13		T39	4
auto[1]	auto[TransCheckSt]	75	1			T51	4		T39	4		T58	1
auto[1]	auto[TokenHashSt]	502	1			T2	12		T51	13		T39	32
auto[1]	auto[FlashRmaSt]	26	1			T39	2		T55	1		T56	1
auto[1]	auto[TokenCheck0St]	41	1			T51	1		T39	1		T52	4
auto[1]	auto[TokenCheck1St]	14	1			T55	1		T58	1		T215	1
auto[1]	auto[TransProgSt]	558	1			T2	22		T51	5		T39	4
auto[1]	auto[PostTransSt]	2709	1			T2	2		T12	3		T51	3
auto[1]	auto[ScrapSt]	42	1			T2	2		T39	2		T52	1
auto[1]	auto[EscalateSt]	1455531	1			T2	13170		T11	2254		T12	294
auto[1]	auto[InvalidSt]	7502	1			T11	23		T13	27		T15	12

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7819775	1			T1	72		T2	8159		T3	917
auto[0]	auto[IdleSt]	22339373	1			T1	5425		T2	9483		T3	1393
auto[0]	auto[ClkMuxSt]	35835	1			T2	79		T3	9		T4	4
auto[0]	auto[CntIncrSt]	35620	1			T2	78		T3	9		T4	4
auto[0]	auto[CntProgSt]	1935516	1			T2	6132		T3	18		T4	287
auto[0]	auto[TransCheckSt]	27530	1			T2	45		T3	9		T4	4
auto[0]	auto[TokenHashSt]	44307706	1			T2	9712		T3	31068		T4	40
auto[0]	auto[FlashRmaSt]	34734	1			T2	70		T3	34		T4	33
auto[0]	auto[TokenCheck0St]	12587	1			T2	31		T3	9		T4	4
auto[0]	auto[TokenCheck1St]	9366	1			T2	31		T3	9		T4	4
auto[0]	auto[TransProgSt]	501898	1			T2	228		T3	18		T4	302
auto[0]	auto[PostTransSt]	13122692	1			T2	8		T3	1077		T4	1724
auto[0]	auto[ScrapSt]	155508	1			T2	8		T3	43		T5	726
auto[0]	auto[EscalateSt]	5745449	1			T2	7109		T11	4800		T12	590
auto[0]	auto[InvalidSt]	13221607	1			T11	10076		T13	11254		T15	60855
auto[1]	auto[ResetSt]	192	1			T2	4		T51	5		T39	4
auto[1]	auto[IdleSt]	113	1			T2	3		T51	3		T52	6
auto[1]	auto[ClkMuxSt]	25	1			T51	2		T52	2		T53	2
auto[1]	auto[CntIncrSt]	37	1			T2	1		T39	2		T55	1
auto[1]	auto[CntProgSt]	785	1			T2	23		T51	10		T39	6
auto[1]	auto[TransCheckSt]	77	1			T51	5		T39	3		T56	1
auto[1]	auto[TokenHashSt]	503	1			T2	8		T51	12		T39	27
auto[1]	auto[FlashRmaSt]	29	1			T39	1		T58	1		T215	1
auto[1]	auto[TokenCheck0St]	42	1			T39	3		T52	2		T55	3
auto[1]	auto[TokenCheck1St]	14	1			T55	1		T53	1		T215	1
auto[1]	auto[TransProgSt]	555	1			T2	16		T51	5		T39	2
auto[1]	auto[PostTransSt]	2812	1			T12	3		T51	1		T39	13
auto[1]	auto[ScrapSt]	49	1			T51	1		T39	1		T55	1
auto[1]	auto[EscalateSt]	1486206	1			T2	11775		T11	3234		T12	294
auto[1]	auto[InvalidSt]	7602	1			T11	33		T13	35		T15	24