Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.79 97.99 95.32 93.40 97.67 98.55 98.51 96.11


Total test records in report: 1002
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T816 /workspace/coverage/default/18.lc_ctrl_state_failure.103530945 Aug 06 06:33:10 PM PDT 24 Aug 06 06:33:38 PM PDT 24 249136975 ps
T817 /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1776016937 Aug 06 06:31:08 PM PDT 24 Aug 06 06:31:21 PM PDT 24 366101507 ps
T818 /workspace/coverage/default/9.lc_ctrl_prog_failure.4138424280 Aug 06 06:32:01 PM PDT 24 Aug 06 06:32:04 PM PDT 24 204154462 ps
T819 /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3568584441 Aug 06 06:31:06 PM PDT 24 Aug 06 06:31:14 PM PDT 24 452108390 ps
T820 /workspace/coverage/default/47.lc_ctrl_alert_test.2808002976 Aug 06 06:36:48 PM PDT 24 Aug 06 06:36:49 PM PDT 24 79929249 ps
T821 /workspace/coverage/default/21.lc_ctrl_security_escalation.17184203 Aug 06 06:33:46 PM PDT 24 Aug 06 06:34:00 PM PDT 24 1524044478 ps
T822 /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2749978894 Aug 06 06:32:31 PM PDT 24 Aug 06 06:32:39 PM PDT 24 219079963 ps
T823 /workspace/coverage/default/19.lc_ctrl_sec_mubi.3296447351 Aug 06 06:33:30 PM PDT 24 Aug 06 06:33:42 PM PDT 24 467202550 ps
T824 /workspace/coverage/default/7.lc_ctrl_prog_failure.68635491 Aug 06 06:31:38 PM PDT 24 Aug 06 06:31:41 PM PDT 24 119179147 ps
T825 /workspace/coverage/default/44.lc_ctrl_alert_test.2654528327 Aug 06 06:36:08 PM PDT 24 Aug 06 06:36:09 PM PDT 24 34245706 ps
T826 /workspace/coverage/default/46.lc_ctrl_prog_failure.3134111616 Aug 06 06:36:20 PM PDT 24 Aug 06 06:36:23 PM PDT 24 966518162 ps
T827 /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2019820805 Aug 06 06:30:50 PM PDT 24 Aug 06 06:30:52 PM PDT 24 107776601 ps
T828 /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1274125353 Aug 06 06:31:37 PM PDT 24 Aug 06 06:31:47 PM PDT 24 359442378 ps
T829 /workspace/coverage/default/14.lc_ctrl_jtag_access.2712022255 Aug 06 06:32:37 PM PDT 24 Aug 06 06:32:49 PM PDT 24 748764873 ps
T830 /workspace/coverage/default/8.lc_ctrl_jtag_access.1333477312 Aug 06 06:31:37 PM PDT 24 Aug 06 06:31:45 PM PDT 24 1568990012 ps
T831 /workspace/coverage/default/49.lc_ctrl_smoke.2681836661 Aug 06 06:36:47 PM PDT 24 Aug 06 06:36:49 PM PDT 24 546148731 ps
T832 /workspace/coverage/default/44.lc_ctrl_prog_failure.3027287937 Aug 06 06:36:07 PM PDT 24 Aug 06 06:36:11 PM PDT 24 65618187 ps
T833 /workspace/coverage/default/13.lc_ctrl_alert_test.2802324947 Aug 06 06:32:31 PM PDT 24 Aug 06 06:32:32 PM PDT 24 35197603 ps
T834 /workspace/coverage/default/46.lc_ctrl_security_escalation.2013486478 Aug 06 06:36:19 PM PDT 24 Aug 06 06:36:26 PM PDT 24 1962963367 ps
T835 /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.3617214982 Aug 06 06:32:37 PM PDT 24 Aug 06 06:41:39 PM PDT 24 25209873323 ps
T836 /workspace/coverage/default/40.lc_ctrl_sec_mubi.1413540856 Aug 06 06:35:45 PM PDT 24 Aug 06 06:36:03 PM PDT 24 5098241156 ps
T837 /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.125988082 Aug 06 06:36:18 PM PDT 24 Aug 06 06:36:19 PM PDT 24 18678550 ps
T838 /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3927436095 Aug 06 06:31:05 PM PDT 24 Aug 06 06:31:15 PM PDT 24 367969502 ps
T839 /workspace/coverage/default/15.lc_ctrl_security_escalation.243583445 Aug 06 06:32:51 PM PDT 24 Aug 06 06:33:02 PM PDT 24 271802609 ps
T840 /workspace/coverage/default/37.lc_ctrl_state_post_trans.187533882 Aug 06 06:35:29 PM PDT 24 Aug 06 06:35:38 PM PDT 24 291594600 ps
T841 /workspace/coverage/default/44.lc_ctrl_jtag_access.444458335 Aug 06 06:36:03 PM PDT 24 Aug 06 06:36:08 PM PDT 24 1175090640 ps
T842 /workspace/coverage/default/17.lc_ctrl_jtag_smoke.4018505432 Aug 06 06:33:10 PM PDT 24 Aug 06 06:33:18 PM PDT 24 228764953 ps
T843 /workspace/coverage/default/48.lc_ctrl_state_post_trans.2502489330 Aug 06 06:36:46 PM PDT 24 Aug 06 06:36:54 PM PDT 24 283657124 ps
T844 /workspace/coverage/default/2.lc_ctrl_sec_mubi.2187618358 Aug 06 06:30:31 PM PDT 24 Aug 06 06:30:45 PM PDT 24 1122422131 ps
T845 /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2716615774 Aug 06 06:32:19 PM PDT 24 Aug 06 06:32:30 PM PDT 24 1423351747 ps
T846 /workspace/coverage/default/36.lc_ctrl_stress_all.3271216014 Aug 06 06:35:29 PM PDT 24 Aug 06 06:36:36 PM PDT 24 6959163683 ps
T73 /workspace/coverage/default/24.lc_ctrl_stress_all.3241487515 Aug 06 06:34:12 PM PDT 24 Aug 06 06:37:22 PM PDT 24 29726180639 ps
T847 /workspace/coverage/default/16.lc_ctrl_sec_mubi.961723388 Aug 06 06:33:09 PM PDT 24 Aug 06 06:33:17 PM PDT 24 212500208 ps
T848 /workspace/coverage/default/12.lc_ctrl_state_post_trans.4062849594 Aug 06 06:32:16 PM PDT 24 Aug 06 06:32:22 PM PDT 24 109738588 ps
T849 /workspace/coverage/default/12.lc_ctrl_errors.3074116612 Aug 06 06:32:20 PM PDT 24 Aug 06 06:32:45 PM PDT 24 2704091692 ps
T85 /workspace/coverage/default/2.lc_ctrl_sec_cm.3448999614 Aug 06 06:30:27 PM PDT 24 Aug 06 06:31:05 PM PDT 24 884543502 ps
T850 /workspace/coverage/default/9.lc_ctrl_sec_mubi.1443947910 Aug 06 06:32:00 PM PDT 24 Aug 06 06:32:14 PM PDT 24 1474969803 ps
T851 /workspace/coverage/default/16.lc_ctrl_state_post_trans.4124112771 Aug 06 06:33:09 PM PDT 24 Aug 06 06:33:17 PM PDT 24 280200593 ps
T852 /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2260400992 Aug 06 06:32:03 PM PDT 24 Aug 06 06:32:04 PM PDT 24 11333542 ps
T853 /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3610778101 Aug 06 06:31:58 PM PDT 24 Aug 06 06:32:21 PM PDT 24 3570299298 ps
T854 /workspace/coverage/default/1.lc_ctrl_regwen_during_op.925487478 Aug 06 06:30:11 PM PDT 24 Aug 06 06:30:22 PM PDT 24 289277073 ps
T855 /workspace/coverage/default/27.lc_ctrl_prog_failure.2804983273 Aug 06 06:34:37 PM PDT 24 Aug 06 06:34:40 PM PDT 24 53687046 ps
T856 /workspace/coverage/default/7.lc_ctrl_sec_token_digest.1764391552 Aug 06 06:31:43 PM PDT 24 Aug 06 06:32:05 PM PDT 24 1081338709 ps
T857 /workspace/coverage/default/12.lc_ctrl_alert_test.3654303806 Aug 06 06:32:19 PM PDT 24 Aug 06 06:32:20 PM PDT 24 54709688 ps
T858 /workspace/coverage/default/9.lc_ctrl_smoke.1525526625 Aug 06 06:31:58 PM PDT 24 Aug 06 06:31:59 PM PDT 24 15472933 ps
T859 /workspace/coverage/default/36.lc_ctrl_state_failure.2389673393 Aug 06 06:35:09 PM PDT 24 Aug 06 06:35:34 PM PDT 24 288281582 ps
T860 /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2075576192 Aug 06 06:30:31 PM PDT 24 Aug 06 06:30:38 PM PDT 24 955335403 ps
T861 /workspace/coverage/default/21.lc_ctrl_smoke.1248523664 Aug 06 06:33:31 PM PDT 24 Aug 06 06:33:33 PM PDT 24 38042067 ps
T862 /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1545160962 Aug 06 06:30:10 PM PDT 24 Aug 06 06:30:22 PM PDT 24 893783357 ps
T863 /workspace/coverage/default/14.lc_ctrl_stress_all.3472209800 Aug 06 06:32:31 PM PDT 24 Aug 06 06:34:06 PM PDT 24 3485117017 ps
T864 /workspace/coverage/default/26.lc_ctrl_smoke.1079665089 Aug 06 06:34:15 PM PDT 24 Aug 06 06:34:16 PM PDT 24 26371824 ps
T865 /workspace/coverage/default/28.lc_ctrl_sec_token_digest.598804175 Aug 06 06:34:36 PM PDT 24 Aug 06 06:34:52 PM PDT 24 821221428 ps
T866 /workspace/coverage/default/14.lc_ctrl_smoke.1874177487 Aug 06 06:32:30 PM PDT 24 Aug 06 06:32:32 PM PDT 24 16069597 ps
T867 /workspace/coverage/default/10.lc_ctrl_state_failure.1208795600 Aug 06 06:31:56 PM PDT 24 Aug 06 06:32:25 PM PDT 24 250687857 ps
T868 /workspace/coverage/default/2.lc_ctrl_alert_test.3484977220 Aug 06 06:30:27 PM PDT 24 Aug 06 06:30:28 PM PDT 24 61928723 ps
T869 /workspace/coverage/default/17.lc_ctrl_jtag_errors.1108503664 Aug 06 06:33:11 PM PDT 24 Aug 06 06:34:14 PM PDT 24 2204788353 ps
T870 /workspace/coverage/default/3.lc_ctrl_alert_test.1532455383 Aug 06 06:30:29 PM PDT 24 Aug 06 06:30:30 PM PDT 24 67948227 ps
T871 /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.959181313 Aug 06 06:34:33 PM PDT 24 Aug 06 06:34:35 PM PDT 24 23754876 ps
T872 /workspace/coverage/default/13.lc_ctrl_errors.3936965937 Aug 06 06:32:34 PM PDT 24 Aug 06 06:32:48 PM PDT 24 1858085668 ps
T873 /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3800952897 Aug 06 06:33:30 PM PDT 24 Aug 06 06:34:27 PM PDT 24 2653581611 ps
T874 /workspace/coverage/default/19.lc_ctrl_state_failure.1134963250 Aug 06 06:33:27 PM PDT 24 Aug 06 06:33:58 PM PDT 24 981207421 ps
T875 /workspace/coverage/default/26.lc_ctrl_jtag_access.2890245025 Aug 06 06:34:14 PM PDT 24 Aug 06 06:34:20 PM PDT 24 477245714 ps
T876 /workspace/coverage/default/49.lc_ctrl_stress_all.632785919 Aug 06 06:36:47 PM PDT 24 Aug 06 06:38:59 PM PDT 24 8564098628 ps
T877 /workspace/coverage/default/41.lc_ctrl_state_post_trans.2682644260 Aug 06 06:35:44 PM PDT 24 Aug 06 06:35:47 PM PDT 24 112002475 ps
T878 /workspace/coverage/default/3.lc_ctrl_sec_mubi.1591208952 Aug 06 06:30:27 PM PDT 24 Aug 06 06:30:43 PM PDT 24 606430452 ps
T879 /workspace/coverage/default/0.lc_ctrl_jtag_access.2331620321 Aug 06 06:30:10 PM PDT 24 Aug 06 06:30:22 PM PDT 24 6299744566 ps
T880 /workspace/coverage/default/4.lc_ctrl_prog_failure.1584251767 Aug 06 06:30:33 PM PDT 24 Aug 06 06:30:35 PM PDT 24 18006912 ps
T106 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1809863780 Aug 06 04:53:05 PM PDT 24 Aug 06 04:53:06 PM PDT 24 32984832 ps
T114 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1075821602 Aug 06 04:53:10 PM PDT 24 Aug 06 04:53:12 PM PDT 24 203229747 ps
T107 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3149027647 Aug 06 04:53:06 PM PDT 24 Aug 06 04:53:07 PM PDT 24 15206576 ps
T99 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.392179271 Aug 06 04:52:57 PM PDT 24 Aug 06 04:53:00 PM PDT 24 275217467 ps
T133 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4064122066 Aug 06 04:52:46 PM PDT 24 Aug 06 04:52:51 PM PDT 24 1606113586 ps
T108 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2765514311 Aug 06 04:53:05 PM PDT 24 Aug 06 04:53:09 PM PDT 24 264623124 ps
T100 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2353977536 Aug 06 04:53:03 PM PDT 24 Aug 06 04:53:09 PM PDT 24 1006319752 ps
T881 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1438790573 Aug 06 04:52:59 PM PDT 24 Aug 06 04:53:00 PM PDT 24 57793908 ps
T882 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.588262351 Aug 06 04:53:04 PM PDT 24 Aug 06 04:53:06 PM PDT 24 57805019 ps
T130 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2190180587 Aug 06 04:52:48 PM PDT 24 Aug 06 04:52:49 PM PDT 24 75435292 ps
T96 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2061686785 Aug 06 04:52:54 PM PDT 24 Aug 06 04:52:57 PM PDT 24 166301637 ps
T97 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.8508037 Aug 06 04:52:59 PM PDT 24 Aug 06 04:53:02 PM PDT 24 40412090 ps
T129 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2737389737 Aug 06 04:52:59 PM PDT 24 Aug 06 04:53:01 PM PDT 24 23956429 ps
T208 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.36902606 Aug 06 04:53:07 PM PDT 24 Aug 06 04:53:25 PM PDT 24 694639271 ps
T190 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2082886603 Aug 06 04:52:55 PM PDT 24 Aug 06 04:52:56 PM PDT 24 43472010 ps
T204 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3909230337 Aug 06 04:52:45 PM PDT 24 Aug 06 04:52:47 PM PDT 24 49447063 ps
T191 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3255470365 Aug 06 04:52:55 PM PDT 24 Aug 06 04:52:56 PM PDT 24 19255714 ps
T142 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1793125805 Aug 06 04:53:03 PM PDT 24 Aug 06 04:53:04 PM PDT 24 58610815 ps
T205 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3595767229 Aug 06 04:53:04 PM PDT 24 Aug 06 04:53:05 PM PDT 24 30273399 ps
T143 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1937869397 Aug 06 04:53:02 PM PDT 24 Aug 06 04:53:03 PM PDT 24 222318747 ps
T101 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3488677392 Aug 06 04:53:02 PM PDT 24 Aug 06 04:53:08 PM PDT 24 676622337 ps
T102 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2145944675 Aug 06 04:52:57 PM PDT 24 Aug 06 04:53:00 PM PDT 24 492797505 ps
T131 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2025919456 Aug 06 04:52:42 PM PDT 24 Aug 06 04:52:45 PM PDT 24 242949822 ps
T883 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1918460083 Aug 06 04:52:53 PM PDT 24 Aug 06 04:52:54 PM PDT 24 15895000 ps
T144 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.141414649 Aug 06 04:52:45 PM PDT 24 Aug 06 04:52:46 PM PDT 24 44802429 ps
T98 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3294904641 Aug 06 04:53:19 PM PDT 24 Aug 06 04:53:21 PM PDT 24 19125926 ps
T145 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2733326371 Aug 06 04:53:04 PM PDT 24 Aug 06 04:53:06 PM PDT 24 26643976 ps
T884 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.78470210 Aug 06 04:52:48 PM PDT 24 Aug 06 04:52:49 PM PDT 24 120602804 ps
T103 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.153765953 Aug 06 04:53:06 PM PDT 24 Aug 06 04:53:08 PM PDT 24 761365697 ps
T146 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.90661432 Aug 06 04:52:59 PM PDT 24 Aug 06 04:53:01 PM PDT 24 81753354 ps
T885 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3866894232 Aug 06 04:53:01 PM PDT 24 Aug 06 04:53:02 PM PDT 24 46522226 ps
T167 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2357767024 Aug 06 04:52:48 PM PDT 24 Aug 06 04:52:49 PM PDT 24 31483077 ps
T886 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2726891000 Aug 06 04:53:03 PM PDT 24 Aug 06 04:53:05 PM PDT 24 213756788 ps
T120 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2220036945 Aug 06 04:53:19 PM PDT 24 Aug 06 04:53:21 PM PDT 24 26693147 ps
T117 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1987260216 Aug 06 04:53:05 PM PDT 24 Aug 06 04:53:07 PM PDT 24 192651649 ps
T206 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2512873881 Aug 06 04:53:05 PM PDT 24 Aug 06 04:53:06 PM PDT 24 23112454 ps
T132 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2884906276 Aug 06 04:53:05 PM PDT 24 Aug 06 04:53:07 PM PDT 24 104837607 ps
T104 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.908376164 Aug 06 04:52:43 PM PDT 24 Aug 06 04:52:48 PM PDT 24 216026095 ps
T207 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1761748806 Aug 06 04:53:00 PM PDT 24 Aug 06 04:53:02 PM PDT 24 84868497 ps
T887 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.507544319 Aug 06 04:52:48 PM PDT 24 Aug 06 04:52:50 PM PDT 24 1436849865 ps
T105 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.182714281 Aug 06 04:53:22 PM PDT 24 Aug 06 04:53:25 PM PDT 24 960164402 ps
T126 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2636306882 Aug 06 04:53:01 PM PDT 24 Aug 06 04:53:04 PM PDT 24 826644549 ps
T888 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.752166852 Aug 06 04:53:03 PM PDT 24 Aug 06 04:53:04 PM PDT 24 17823570 ps
T889 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3393291715 Aug 06 04:52:46 PM PDT 24 Aug 06 04:52:47 PM PDT 24 115886618 ps
T890 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2066681648 Aug 06 04:53:00 PM PDT 24 Aug 06 04:53:01 PM PDT 24 29417943 ps
T891 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3680200666 Aug 06 04:52:59 PM PDT 24 Aug 06 04:53:01 PM PDT 24 25602638 ps
T892 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2079199678 Aug 06 04:52:58 PM PDT 24 Aug 06 04:53:00 PM PDT 24 143149736 ps
T119 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.610931964 Aug 06 04:52:58 PM PDT 24 Aug 06 04:53:01 PM PDT 24 168904094 ps
T893 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1746094178 Aug 06 04:53:04 PM PDT 24 Aug 06 04:53:13 PM PDT 24 2888837949 ps
T894 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2919469929 Aug 06 04:52:59 PM PDT 24 Aug 06 04:53:00 PM PDT 24 93188199 ps
T112 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.684998607 Aug 06 04:52:44 PM PDT 24 Aug 06 04:52:46 PM PDT 24 224557550 ps
T895 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2345433758 Aug 06 04:53:04 PM PDT 24 Aug 06 04:53:05 PM PDT 24 26908694 ps
T896 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1236051118 Aug 06 04:52:51 PM PDT 24 Aug 06 04:52:52 PM PDT 24 41264120 ps
T897 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.785323482 Aug 06 04:52:41 PM PDT 24 Aug 06 04:52:44 PM PDT 24 1106678219 ps
T898 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3742893297 Aug 06 04:52:59 PM PDT 24 Aug 06 04:53:01 PM PDT 24 25935281 ps
T899 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3535910555 Aug 06 04:53:02 PM PDT 24 Aug 06 04:53:07 PM PDT 24 551642873 ps
T900 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.4240153127 Aug 06 04:52:57 PM PDT 24 Aug 06 04:53:02 PM PDT 24 121358632 ps
T901 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.488237615 Aug 06 04:53:06 PM PDT 24 Aug 06 04:53:09 PM PDT 24 379554778 ps
T902 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1076171988 Aug 06 04:53:06 PM PDT 24 Aug 06 04:53:07 PM PDT 24 15878353 ps
T903 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.746715773 Aug 06 04:53:03 PM PDT 24 Aug 06 04:53:22 PM PDT 24 1391836246 ps
T192 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.696671226 Aug 06 04:52:42 PM PDT 24 Aug 06 04:52:44 PM PDT 24 61361068 ps
T193 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.913564483 Aug 06 04:52:51 PM PDT 24 Aug 06 04:52:52 PM PDT 24 41353517 ps
T904 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2424878235 Aug 06 04:53:23 PM PDT 24 Aug 06 04:53:25 PM PDT 24 115694499 ps
T113 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3263562615 Aug 06 04:53:05 PM PDT 24 Aug 06 04:53:09 PM PDT 24 103523701 ps
T905 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3535873868 Aug 06 04:53:04 PM PDT 24 Aug 06 04:53:05 PM PDT 24 48832587 ps
T906 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3636991554 Aug 06 04:53:04 PM PDT 24 Aug 06 04:53:05 PM PDT 24 120612724 ps
T907 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3433809727 Aug 06 04:53:04 PM PDT 24 Aug 06 04:53:07 PM PDT 24 2176870156 ps
T908 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1975343636 Aug 06 04:53:05 PM PDT 24 Aug 06 04:53:14 PM PDT 24 5115551237 ps
T909 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2544234940 Aug 06 04:53:08 PM PDT 24 Aug 06 04:53:09 PM PDT 24 441066631 ps
T910 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.142835941 Aug 06 04:52:59 PM PDT 24 Aug 06 04:53:01 PM PDT 24 290728722 ps
T911 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1894693486 Aug 06 04:53:07 PM PDT 24 Aug 06 04:53:08 PM PDT 24 16461712 ps
T912 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.591856565 Aug 06 04:53:05 PM PDT 24 Aug 06 04:53:06 PM PDT 24 60595261 ps
T913 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1987037234 Aug 06 04:52:44 PM PDT 24 Aug 06 04:52:46 PM PDT 24 53159174 ps
T914 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3571154168 Aug 06 04:53:06 PM PDT 24 Aug 06 04:53:08 PM PDT 24 72091182 ps
T915 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3167347093 Aug 06 04:53:00 PM PDT 24 Aug 06 04:53:05 PM PDT 24 823394433 ps
T194 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4180424895 Aug 06 04:52:58 PM PDT 24 Aug 06 04:53:00 PM PDT 24 21945786 ps
T916 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2758499962 Aug 06 04:53:02 PM PDT 24 Aug 06 04:53:04 PM PDT 24 85881618 ps
T917 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2097317096 Aug 06 04:53:07 PM PDT 24 Aug 06 04:53:09 PM PDT 24 100291259 ps
T918 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2923857015 Aug 06 04:52:50 PM PDT 24 Aug 06 04:52:51 PM PDT 24 20894702 ps
T919 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3295030252 Aug 06 04:53:05 PM PDT 24 Aug 06 04:53:16 PM PDT 24 971965435 ps
T920 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3422554667 Aug 06 04:53:06 PM PDT 24 Aug 06 04:53:07 PM PDT 24 23802620 ps
T921 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2542560238 Aug 06 04:53:07 PM PDT 24 Aug 06 04:53:10 PM PDT 24 132648992 ps
T922 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2141046090 Aug 06 04:53:07 PM PDT 24 Aug 06 04:53:11 PM PDT 24 592758294 ps
T923 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2020406373 Aug 06 04:53:03 PM PDT 24 Aug 06 04:53:11 PM PDT 24 299467673 ps
T924 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1745435919 Aug 06 04:52:54 PM PDT 24 Aug 06 04:52:57 PM PDT 24 160071211 ps
T925 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.516967767 Aug 06 04:53:08 PM PDT 24 Aug 06 04:53:09 PM PDT 24 95883616 ps
T127 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4257248665 Aug 06 04:53:04 PM PDT 24 Aug 06 04:53:06 PM PDT 24 153901338 ps
T128 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3038763490 Aug 06 04:53:00 PM PDT 24 Aug 06 04:53:03 PM PDT 24 411723996 ps
T926 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2949124056 Aug 06 04:52:41 PM PDT 24 Aug 06 04:52:45 PM PDT 24 1890411990 ps
T927 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.408791673 Aug 06 04:53:05 PM PDT 24 Aug 06 04:53:30 PM PDT 24 2430525389 ps
T928 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1930020296 Aug 06 04:52:55 PM PDT 24 Aug 06 04:53:05 PM PDT 24 371796678 ps
T929 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3122593038 Aug 06 04:52:48 PM PDT 24 Aug 06 04:52:50 PM PDT 24 189266095 ps
T930 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2954676287 Aug 06 04:52:48 PM PDT 24 Aug 06 04:52:49 PM PDT 24 199432512 ps
T931 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2069007501 Aug 06 04:52:45 PM PDT 24 Aug 06 04:52:46 PM PDT 24 76703874 ps
T932 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4251671018 Aug 06 04:53:03 PM PDT 24 Aug 06 04:53:04 PM PDT 24 65801214 ps
T933 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1839796153 Aug 06 04:52:59 PM PDT 24 Aug 06 04:53:01 PM PDT 24 87253103 ps
T934 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2514919329 Aug 06 04:53:05 PM PDT 24 Aug 06 04:53:07 PM PDT 24 28102416 ps
T935 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.771718606 Aug 06 04:53:00 PM PDT 24 Aug 06 04:53:01 PM PDT 24 21605830 ps
T936 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2057326984 Aug 06 04:52:41 PM PDT 24 Aug 06 04:52:42 PM PDT 24 40489964 ps
T937 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4058019446 Aug 06 04:52:43 PM PDT 24 Aug 06 04:52:44 PM PDT 24 1017977786 ps
T938 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1748133457 Aug 06 04:52:59 PM PDT 24 Aug 06 04:53:01 PM PDT 24 108252421 ps
T939 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3923377234 Aug 06 04:52:55 PM PDT 24 Aug 06 04:52:57 PM PDT 24 66441804 ps
T940 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3645053097 Aug 06 04:52:47 PM PDT 24 Aug 06 04:52:49 PM PDT 24 101492377 ps
T941 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.34981549 Aug 06 04:53:04 PM PDT 24 Aug 06 04:53:12 PM PDT 24 1321437495 ps
T195 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.4045823430 Aug 06 04:52:46 PM PDT 24 Aug 06 04:52:47 PM PDT 24 11357658 ps
T942 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2997720790 Aug 06 04:53:20 PM PDT 24 Aug 06 04:53:23 PM PDT 24 65810754 ps
T943 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.170441476 Aug 06 04:53:00 PM PDT 24 Aug 06 04:53:02 PM PDT 24 320545360 ps
T944 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.165633499 Aug 06 04:52:43 PM PDT 24 Aug 06 04:53:03 PM PDT 24 3115385351 ps
T945 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1256968283 Aug 06 04:52:57 PM PDT 24 Aug 06 04:53:37 PM PDT 24 1921841241 ps
T946 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.750637247 Aug 06 04:53:21 PM PDT 24 Aug 06 04:53:22 PM PDT 24 108081157 ps
T947 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3266610840 Aug 06 04:52:55 PM PDT 24 Aug 06 04:52:57 PM PDT 24 59299131 ps
T948 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3554635219 Aug 06 04:53:03 PM PDT 24 Aug 06 04:53:05 PM PDT 24 22682635 ps
T949 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2758715229 Aug 06 04:53:01 PM PDT 24 Aug 06 04:53:03 PM PDT 24 58787605 ps
T115 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1103259606 Aug 06 04:53:00 PM PDT 24 Aug 06 04:53:05 PM PDT 24 585209268 ps
T950 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2412982307 Aug 06 04:53:19 PM PDT 24 Aug 06 04:53:21 PM PDT 24 118923764 ps
T951 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.883585942 Aug 06 04:53:07 PM PDT 24 Aug 06 04:53:09 PM PDT 24 310832490 ps
T952 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.440544835 Aug 06 04:52:41 PM PDT 24 Aug 06 04:52:43 PM PDT 24 64720067 ps
T953 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2157609690 Aug 06 04:52:45 PM PDT 24 Aug 06 04:52:48 PM PDT 24 264278370 ps
T123 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4180690227 Aug 06 04:53:06 PM PDT 24 Aug 06 04:53:09 PM PDT 24 468725190 ps
T122 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.670122663 Aug 06 04:52:55 PM PDT 24 Aug 06 04:52:58 PM PDT 24 110329346 ps
T954 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2350319688 Aug 06 04:53:19 PM PDT 24 Aug 06 04:53:22 PM PDT 24 44538882 ps
T955 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2686557081 Aug 06 04:53:24 PM PDT 24 Aug 06 04:53:25 PM PDT 24 29797526 ps
T956 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1569603852 Aug 06 04:53:05 PM PDT 24 Aug 06 04:53:07 PM PDT 24 154226620 ps
T957 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2727342207 Aug 06 04:52:59 PM PDT 24 Aug 06 04:53:01 PM PDT 24 168797748 ps
T958 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.879645324 Aug 06 04:52:51 PM PDT 24 Aug 06 04:53:12 PM PDT 24 5494662858 ps
T959 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.683082128 Aug 06 04:53:07 PM PDT 24 Aug 06 04:53:17 PM PDT 24 2464474917 ps
T960 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2025473387 Aug 06 04:53:00 PM PDT 24 Aug 06 04:53:02 PM PDT 24 91014303 ps
T961 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.4016382377 Aug 06 04:53:03 PM PDT 24 Aug 06 04:53:05 PM PDT 24 20103221 ps
T196 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3254671146 Aug 06 04:53:00 PM PDT 24 Aug 06 04:53:02 PM PDT 24 54600967 ps
T110 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1326310396 Aug 06 04:52:57 PM PDT 24 Aug 06 04:53:00 PM PDT 24 60680432 ps
T962 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.22067000 Aug 06 04:53:07 PM PDT 24 Aug 06 04:53:11 PM PDT 24 108788169 ps
T963 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2386202421 Aug 06 04:53:04 PM PDT 24 Aug 06 04:53:05 PM PDT 24 23430201 ps
T964 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.786728400 Aug 06 04:53:07 PM PDT 24 Aug 06 04:53:08 PM PDT 24 18444103 ps
T965 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1294773595 Aug 06 04:52:44 PM PDT 24 Aug 06 04:52:46 PM PDT 24 113925472 ps
T111 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.928872753 Aug 06 04:53:07 PM PDT 24 Aug 06 04:53:11 PM PDT 24 861118516 ps
T966 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2839598931 Aug 06 04:52:57 PM PDT 24 Aug 06 04:53:00 PM PDT 24 1140321095 ps
T967 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3532099160 Aug 06 04:53:04 PM PDT 24 Aug 06 04:53:06 PM PDT 24 59894754 ps
T968 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2576079346 Aug 06 04:53:00 PM PDT 24 Aug 06 04:53:02 PM PDT 24 42803664 ps
T969 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3564873249 Aug 06 04:53:00 PM PDT 24 Aug 06 04:53:02 PM PDT 24 31607140 ps
T970 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.996397471 Aug 06 04:52:59 PM PDT 24 Aug 06 04:53:01 PM PDT 24 56673520 ps
T213 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.4168726711 Aug 06 04:53:06 PM PDT 24 Aug 06 04:53:09 PM PDT 24 66934937 ps
T197 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3767057532 Aug 06 04:53:01 PM PDT 24 Aug 06 04:53:02 PM PDT 24 19190893 ps
T971 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3427974254 Aug 06 04:52:54 PM PDT 24 Aug 06 04:52:56 PM PDT 24 34535341 ps
T972 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.4180075101 Aug 06 04:53:06 PM PDT 24 Aug 06 04:53:08 PM PDT 24 386578121 ps
T973 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.897382704 Aug 06 04:52:59 PM PDT 24 Aug 06 04:53:00 PM PDT 24 24177585 ps
T198 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.684892765 Aug 06 04:53:01 PM PDT 24 Aug 06 04:53:02 PM PDT 24 15996841 ps
T974 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.307512120 Aug 06 04:52:57 PM PDT 24 Aug 06 04:52:59 PM PDT 24 211296900 ps
T975 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2704319500 Aug 06 04:53:21 PM PDT 24 Aug 06 04:53:23 PM PDT 24 875605761 ps
T976 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.636969281 Aug 06 04:53:06 PM PDT 24 Aug 06 04:53:07 PM PDT 24 13330885 ps
T977 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1834538013 Aug 06 04:53:04 PM PDT 24 Aug 06 04:53:10 PM PDT 24 1207708390 ps
T199 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.583071800 Aug 06 04:53:07 PM PDT 24 Aug 06 04:53:08 PM PDT 24 14524753 ps
T125 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4141784886 Aug 06 04:53:02 PM PDT 24 Aug 06 04:53:05 PM PDT 24 88682298 ps
T118 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1488967387 Aug 06 04:52:52 PM PDT 24 Aug 06 04:52:56 PM PDT 24 101259089 ps
T202 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3524639799 Aug 06 04:53:19 PM PDT 24 Aug 06 04:53:20 PM PDT 24 15962880 ps
T978 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1270896353 Aug 06 04:53:19 PM PDT 24 Aug 06 04:53:21 PM PDT 24 112718341 ps
T979 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2256136663 Aug 06 04:53:02 PM PDT 24 Aug 06 04:53:03 PM PDT 24 24440233 ps
T980 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2083160968 Aug 06 04:52:41 PM PDT 24 Aug 06 04:52:51 PM PDT 24 1646916811 ps
T981 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2824657258 Aug 06 04:52:48 PM PDT 24 Aug 06 04:52:51 PM PDT 24 726473426 ps
T982 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3240295094 Aug 06 04:52:58 PM PDT 24 Aug 06 04:52:59 PM PDT 24 20783657 ps
T983 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.151934057 Aug 06 04:53:21 PM PDT 24 Aug 06 04:53:24 PM PDT 24 66275993 ps
T984 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1363526051 Aug 06 04:53:05 PM PDT 24 Aug 06 04:53:06 PM PDT 24 150879361 ps
T203 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2838494561 Aug 06 04:52:57 PM PDT 24 Aug 06 04:52:58 PM PDT 24 20472779 ps
T200 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1502453437 Aug 06 04:53:07 PM PDT 24 Aug 06 04:53:08 PM PDT 24 87385735 ps
T985 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1261469427 Aug 06 04:53:02 PM PDT 24 Aug 06 04:53:05 PM PDT 24 342066821 ps
T201 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2570730744 Aug 06 04:52:44 PM PDT 24 Aug 06 04:52:45 PM PDT 24 72731406 ps
T121 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.59736598 Aug 06 04:53:00 PM PDT 24 Aug 06 04:53:03 PM PDT 24 289825989 ps
T986 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1782504264 Aug 06 04:53:03 PM PDT 24 Aug 06 04:53:05 PM PDT 24 27268120 ps
T987 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.112433497 Aug 06 04:53:00 PM PDT 24 Aug 06 04:53:01 PM PDT 24 80398615 ps
T988 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.509055867 Aug 06 04:53:07 PM PDT 24 Aug 06 04:53:09 PM PDT 24 46481353 ps
T124 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3045148286 Aug 06 04:53:02 PM PDT 24 Aug 06 04:53:05 PM PDT 24 183655382 ps
T989 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2087598014 Aug 06 04:52:39 PM PDT 24 Aug 06 04:52:41 PM PDT 24 72968003 ps
T116 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1375706275 Aug 06 04:52:44 PM PDT 24 Aug 06 04:52:46 PM PDT 24 109327147 ps
T990 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2573923859 Aug 06 04:53:03 PM PDT 24 Aug 06 04:53:05 PM PDT 24 91827445 ps
T991 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1264520662 Aug 06 04:53:03 PM PDT 24 Aug 06 04:53:04 PM PDT 24 26635869 ps
T992 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1366461794 Aug 06 04:52:59 PM PDT 24 Aug 06 04:53:00 PM PDT 24 102211679 ps
T993 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3866138002 Aug 06 04:53:04 PM PDT 24 Aug 06 04:53:05 PM PDT 24 17447934 ps
T994 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2456007881 Aug 06 04:53:00 PM PDT 24 Aug 06 04:53:03 PM PDT 24 106607782 ps
T995 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1066870891 Aug 06 04:53:06 PM PDT 24 Aug 06 04:53:07 PM PDT 24 39420950 ps
T996 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1095091626 Aug 06 04:53:02 PM PDT 24 Aug 06 04:53:04 PM PDT 24 31262742 ps
T997 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3918122364 Aug 06 04:53:06 PM PDT 24 Aug 06 04:53:09 PM PDT 24 45094259 ps
T998 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2497196817 Aug 06 04:53:03 PM PDT 24 Aug 06 04:53:04 PM PDT 24 54047369 ps
T999 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1850898928 Aug 06 04:53:23 PM PDT 24 Aug 06 04:53:24 PM PDT 24 41487954 ps
T1000 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2566859164 Aug 06 04:53:07 PM PDT 24 Aug 06 04:53:08 PM PDT 24 90319085 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%