Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49249 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
55 |
auto[1] |
1600 |
1 |
|
|
T3 |
8 |
|
T37 |
4 |
|
T18 |
21 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50160 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
689 |
1 |
|
|
T38 |
11 |
|
T27 |
13 |
|
T66 |
9 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49058 |
1 |
|
|
T1 |
73 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
1791 |
1 |
|
|
T1 |
16 |
|
T5 |
7 |
|
T16 |
21 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49087 |
1 |
|
|
T1 |
79 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
1762 |
1 |
|
|
T1 |
10 |
|
T5 |
5 |
|
T16 |
25 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49028 |
1 |
|
|
T1 |
82 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
1821 |
1 |
|
|
T1 |
7 |
|
T10 |
1 |
|
T5 |
4 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
46191 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
63 |
no_err_inj |
4658 |
1 |
|
|
T10 |
8 |
|
T12 |
8 |
|
T15 |
7 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49240 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
57 |
auto[1] |
1609 |
1 |
|
|
T3 |
6 |
|
T37 |
5 |
|
T18 |
22 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50143 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
706 |
1 |
|
|
T38 |
10 |
|
T27 |
20 |
|
T66 |
8 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36063 |
1 |
|
|
T2 |
19 |
|
T3 |
63 |
|
T9 |
70 |
auto[1] |
14786 |
1 |
|
|
T1 |
89 |
|
T5 |
61 |
|
T13 |
17 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48995 |
1 |
|
|
T1 |
70 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
1854 |
1 |
|
|
T1 |
19 |
|
T5 |
10 |
|
T16 |
23 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49119 |
1 |
|
|
T1 |
80 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
1730 |
1 |
|
|
T1 |
9 |
|
T5 |
6 |
|
T41 |
2 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49053 |
1 |
|
|
T1 |
82 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
1796 |
1 |
|
|
T1 |
7 |
|
T5 |
7 |
|
T41 |
1 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49174 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
58 |
auto[1] |
1675 |
1 |
|
|
T3 |
5 |
|
T37 |
4 |
|
T18 |
29 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48783 |
1 |
|
|
T1 |
89 |
|
T3 |
63 |
|
T9 |
70 |
auto[1] |
2066 |
1 |
|
|
T2 |
19 |
|
T13 |
17 |
|
T14 |
1 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50159 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
690 |
1 |
|
|
T38 |
14 |
|
T27 |
15 |
|
T66 |
17 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50127 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
722 |
1 |
|
|
T38 |
12 |
|
T27 |
17 |
|
T66 |
18 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50123 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
726 |
1 |
|
|
T38 |
9 |
|
T27 |
18 |
|
T66 |
11 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48256 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
2593 |
1 |
|
|
T10 |
11 |
|
T41 |
14 |
|
T16 |
25 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47126 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
3723 |
1 |
|
|
T57 |
92 |
|
T54 |
79 |
|
T58 |
74 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49029 |
1 |
|
|
T1 |
77 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
1820 |
1 |
|
|
T1 |
12 |
|
T10 |
2 |
|
T5 |
9 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48938 |
1 |
|
|
T1 |
83 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
1911 |
1 |
|
|
T1 |
6 |
|
T5 |
7 |
|
T41 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49032 |
1 |
|
|
T1 |
86 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
1817 |
1 |
|
|
T1 |
3 |
|
T5 |
6 |
|
T16 |
12 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49220 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
55 |
auto[1] |
1629 |
1 |
|
|
T3 |
8 |
|
T37 |
6 |
|
T18 |
28 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
45425 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
55 |
auto[1] |
5424 |
1 |
|
|
T3 |
8 |
|
T37 |
7 |
|
T18 |
27 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47116 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
63 |
auto[1] |
3733 |
1 |
|
|
T9 |
70 |
|
T53 |
99 |
|
T65 |
83 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50849 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
63 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49274 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
55 |
auto[1] |
1575 |
1 |
|
|
T3 |
8 |
|
T37 |
3 |
|
T18 |
32 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49184 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
56 |
auto[1] |
1665 |
1 |
|
|
T3 |
7 |
|
T37 |
12 |
|
T18 |
31 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49192 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
50 |
auto[1] |
1657 |
1 |
|
|
T3 |
13 |
|
T37 |
10 |
|
T18 |
23 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
44872 |
1 |
|
|
T1 |
89 |
|
T2 |
19 |
|
T3 |
63 |
auto[0] |
no_err_inj |
3384 |
1 |
|
|
T12 |
8 |
|
T15 |
7 |
|
T16 |
15 |
auto[1] |
err_inj |
1319 |
1 |
|
|
T10 |
3 |
|
T41 |
7 |
|
T16 |
11 |
auto[1] |
no_err_inj |
1274 |
1 |
|
|
T10 |
8 |
|
T41 |
7 |
|
T16 |
14 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46501 |
1 |
|
|
T1 |
83 |
|
T2 |
19 |
|
T3 |
63 |
auto[0] |
auto[1] |
1755 |
1 |
|
|
T1 |
6 |
|
T5 |
7 |
|
T16 |
17 |
auto[1] |
auto[0] |
2437 |
1 |
|
|
T10 |
11 |
|
T41 |
13 |
|
T16 |
25 |
auto[1] |
auto[1] |
156 |
1 |
|
|
T41 |
1 |
|
T17 |
1 |
|
T19 |
3 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46661 |
1 |
|
|
T1 |
80 |
|
T2 |
19 |
|
T3 |
63 |
auto[0] |
auto[1] |
1595 |
1 |
|
|
T1 |
9 |
|
T5 |
6 |
|
T16 |
21 |
auto[1] |
auto[0] |
2458 |
1 |
|
|
T10 |
11 |
|
T41 |
12 |
|
T16 |
24 |
auto[1] |
auto[1] |
135 |
1 |
|
|
T41 |
2 |
|
T16 |
1 |
|
T184 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46584 |
1 |
|
|
T1 |
86 |
|
T2 |
19 |
|
T3 |
63 |
auto[0] |
auto[1] |
1672 |
1 |
|
|
T1 |
3 |
|
T5 |
6 |
|
T16 |
12 |
auto[1] |
auto[0] |
2448 |
1 |
|
|
T10 |
11 |
|
T41 |
14 |
|
T16 |
25 |
auto[1] |
auto[1] |
145 |
1 |
|
|
T17 |
3 |
|
T19 |
2 |
|
T218 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46632 |
1 |
|
|
T1 |
79 |
|
T2 |
19 |
|
T3 |
63 |
auto[0] |
auto[1] |
1624 |
1 |
|
|
T1 |
10 |
|
T5 |
5 |
|
T16 |
23 |
auto[1] |
auto[0] |
2455 |
1 |
|
|
T10 |
11 |
|
T41 |
14 |
|
T16 |
23 |
auto[1] |
auto[1] |
138 |
1 |
|
|
T16 |
2 |
|
T17 |
2 |
|
T103 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46583 |
1 |
|
|
T1 |
82 |
|
T2 |
19 |
|
T3 |
63 |
auto[0] |
auto[1] |
1673 |
1 |
|
|
T1 |
7 |
|
T5 |
4 |
|
T16 |
21 |
auto[1] |
auto[0] |
2445 |
1 |
|
|
T10 |
10 |
|
T41 |
14 |
|
T16 |
22 |
auto[1] |
auto[1] |
148 |
1 |
|
|
T10 |
1 |
|
T16 |
3 |
|
T219 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46603 |
1 |
|
|
T1 |
73 |
|
T2 |
19 |
|
T3 |
63 |
auto[0] |
auto[1] |
1653 |
1 |
|
|
T1 |
16 |
|
T5 |
7 |
|
T16 |
19 |
auto[1] |
auto[0] |
2455 |
1 |
|
|
T10 |
11 |
|
T41 |
14 |
|
T16 |
23 |
auto[1] |
auto[1] |
138 |
1 |
|
|
T16 |
2 |
|
T184 |
1 |
|
T220 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35074 |
1 |
|
|
T2 |
19 |
|
T3 |
55 |
|
T9 |
70 |
auto[0] |
auto[1] |
989 |
1 |
|
|
T3 |
8 |
|
T37 |
4 |
|
T18 |
17 |
auto[1] |
auto[0] |
14175 |
1 |
|
|
T1 |
89 |
|
T5 |
61 |
|
T13 |
17 |
auto[1] |
auto[1] |
611 |
1 |
|
|
T18 |
4 |
|
T32 |
6 |
|
T34 |
11 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35092 |
1 |
|
|
T2 |
19 |
|
T3 |
57 |
|
T9 |
70 |
auto[0] |
auto[1] |
971 |
1 |
|
|
T3 |
6 |
|
T37 |
5 |
|
T18 |
16 |
auto[1] |
auto[0] |
14148 |
1 |
|
|
T1 |
89 |
|
T5 |
61 |
|
T13 |
17 |
auto[1] |
auto[1] |
638 |
1 |
|
|
T18 |
6 |
|
T32 |
7 |
|
T34 |
7 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34964 |
1 |
|
|
T3 |
63 |
|
T9 |
70 |
|
T10 |
11 |
auto[0] |
auto[1] |
1099 |
1 |
|
|
T2 |
19 |
|
T14 |
1 |
|
T19 |
11 |
auto[1] |
auto[0] |
13819 |
1 |
|
|
T1 |
89 |
|
T5 |
61 |
|
T16 |
120 |
auto[1] |
auto[1] |
967 |
1 |
|
|
T13 |
17 |
|
T18 |
21 |
|
T96 |
1 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35073 |
1 |
|
|
T2 |
19 |
|
T3 |
58 |
|
T9 |
70 |
auto[0] |
auto[1] |
990 |
1 |
|
|
T3 |
5 |
|
T37 |
4 |
|
T18 |
19 |
auto[1] |
auto[0] |
14101 |
1 |
|
|
T1 |
89 |
|
T5 |
61 |
|
T13 |
17 |
auto[1] |
auto[1] |
685 |
1 |
|
|
T18 |
10 |
|
T32 |
4 |
|
T34 |
10 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31269 |
1 |
|
|
T2 |
19 |
|
T3 |
55 |
|
T9 |
70 |
auto[0] |
auto[1] |
4794 |
1 |
|
|
T3 |
8 |
|
T37 |
7 |
|
T18 |
21 |
auto[1] |
auto[0] |
14156 |
1 |
|
|
T1 |
89 |
|
T5 |
61 |
|
T13 |
17 |
auto[1] |
auto[1] |
630 |
1 |
|
|
T18 |
6 |
|
T32 |
11 |
|
T34 |
11 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34907 |
1 |
|
|
T2 |
19 |
|
T3 |
63 |
|
T9 |
70 |
auto[0] |
auto[1] |
1156 |
1 |
|
|
T41 |
1 |
|
T16 |
10 |
|
T18 |
7 |
auto[1] |
auto[0] |
14031 |
1 |
|
|
T1 |
83 |
|
T5 |
54 |
|
T13 |
17 |
auto[1] |
auto[1] |
755 |
1 |
|
|
T1 |
6 |
|
T5 |
7 |
|
T16 |
7 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35011 |
1 |
|
|
T2 |
19 |
|
T3 |
63 |
|
T9 |
70 |
auto[0] |
auto[1] |
1052 |
1 |
|
|
T10 |
2 |
|
T41 |
3 |
|
T16 |
9 |
auto[1] |
auto[0] |
14018 |
1 |
|
|
T1 |
77 |
|
T5 |
52 |
|
T13 |
17 |
auto[1] |
auto[1] |
768 |
1 |
|
|
T1 |
12 |
|
T5 |
9 |
|
T16 |
7 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35039 |
1 |
|
|
T2 |
19 |
|
T3 |
63 |
|
T9 |
70 |
auto[0] |
auto[1] |
1024 |
1 |
|
|
T41 |
2 |
|
T16 |
8 |
|
T18 |
3 |
auto[1] |
auto[0] |
14080 |
1 |
|
|
T1 |
80 |
|
T5 |
55 |
|
T13 |
17 |
auto[1] |
auto[1] |
706 |
1 |
|
|
T1 |
9 |
|
T5 |
6 |
|
T16 |
14 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35024 |
1 |
|
|
T2 |
19 |
|
T3 |
63 |
|
T9 |
70 |
auto[0] |
auto[1] |
1039 |
1 |
|
|
T16 |
9 |
|
T18 |
6 |
|
T28 |
9 |
auto[1] |
auto[0] |
13971 |
1 |
|
|
T1 |
70 |
|
T5 |
51 |
|
T13 |
17 |
auto[1] |
auto[1] |
815 |
1 |
|
|
T1 |
19 |
|
T5 |
10 |
|
T16 |
14 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35000 |
1 |
|
|
T2 |
19 |
|
T3 |
63 |
|
T9 |
70 |
auto[0] |
auto[1] |
1063 |
1 |
|
|
T16 |
11 |
|
T18 |
5 |
|
T28 |
1 |
auto[1] |
auto[0] |
14087 |
1 |
|
|
T1 |
79 |
|
T5 |
56 |
|
T13 |
17 |
auto[1] |
auto[1] |
699 |
1 |
|
|
T1 |
10 |
|
T5 |
5 |
|
T16 |
14 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35033 |
1 |
|
|
T2 |
19 |
|
T3 |
63 |
|
T9 |
70 |
auto[0] |
auto[1] |
1030 |
1 |
|
|
T16 |
11 |
|
T18 |
6 |
|
T28 |
6 |
auto[1] |
auto[0] |
14025 |
1 |
|
|
T1 |
73 |
|
T5 |
54 |
|
T13 |
17 |
auto[1] |
auto[1] |
761 |
1 |
|
|
T1 |
16 |
|
T5 |
7 |
|
T16 |
10 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35090 |
1 |
|
|
T2 |
19 |
|
T3 |
50 |
|
T9 |
70 |
auto[0] |
auto[1] |
973 |
1 |
|
|
T3 |
13 |
|
T37 |
10 |
|
T18 |
15 |
auto[1] |
auto[0] |
14102 |
1 |
|
|
T1 |
89 |
|
T5 |
61 |
|
T13 |
17 |
auto[1] |
auto[1] |
684 |
1 |
|
|
T18 |
8 |
|
T32 |
12 |
|
T34 |
13 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34998 |
1 |
|
|
T2 |
19 |
|
T3 |
56 |
|
T9 |
70 |
auto[0] |
auto[1] |
1065 |
1 |
|
|
T3 |
7 |
|
T37 |
12 |
|
T18 |
26 |
auto[1] |
auto[0] |
14186 |
1 |
|
|
T1 |
89 |
|
T5 |
61 |
|
T13 |
17 |
auto[1] |
auto[1] |
600 |
1 |
|
|
T18 |
5 |
|
T32 |
6 |
|
T34 |
11 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34519 |
1 |
|
|
T2 |
19 |
|
T3 |
63 |
|
T9 |
70 |
auto[0] |
auto[1] |
1544 |
1 |
|
|
T10 |
11 |
|
T41 |
14 |
|
T184 |
15 |
auto[1] |
auto[0] |
13737 |
1 |
|
|
T1 |
89 |
|
T5 |
61 |
|
T13 |
17 |
auto[1] |
auto[1] |
1049 |
1 |
|
|
T16 |
25 |
|
T17 |
11 |
|
T19 |
13 |