Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93963919

1

T1

149377

T2

8438

T3

37054

auto[1]

1326496

1

T1

4214

T2

990

T3

495

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93956541

1

T1

150063

T2

8537

T3

37252

auto[1]

1333874

1

T1

3528

T2

891

T3

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6866896	1			T1	17641		T2	1726		T3	5686
auto[IdleSt]	20067105	1			T1	8200		T2	2734		T3	2017
auto[ClkMuxSt]	33519	1			T2	19		T3	63		T9	70
auto[CntIncrSt]	33298	1			T2	19		T3	63		T9	70
auto[CntProgSt]	1593827	1			T2	724		T3	485		T9	25944
auto[TransCheckSt]	26114	1			T3	48		T9	70		T10	8
auto[TokenHashSt]	37598503	1			T3	19374		T9	889		T10	265
auto[FlashRmaSt]	34589	1			T3	35		T9	97		T10	8
auto[TokenCheck0St]	12181	1			T3	11		T9	31		T10	8
auto[TokenCheck1St]	9071	1			T3	5		T9	12		T10	8
auto[TransProgSt]	409653	1			T3	55		T10	764		T12	248
auto[PostTransSt]	11697858	1			T2	1461		T3	8713		T9	10717
auto[ScrapSt]	76143	1			T15	34		T18	899		T19	1044
auto[EscalateSt]	6287353	1			T1	31665		T2	2745		T3	994
auto[InvalidSt]	10542512	1			T1	96076		T10	210		T5	125359

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1793	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10542512	1			T1	96076		T10	210		T5	125359
EscalateSt	6287353	1			T1	31665		T2	2745		T3	994
ScrapSt	76143	1			T15	34		T18	899		T19	1044
PostTransSt	11697858	1			T2	1461		T3	8713		T9	10717
TransProgSt	409653	1			T3	55		T10	764		T12	248
TokenCheck1St	9071	1			T3	5		T9	12		T10	8
TokenCheck0St	12181	1			T3	11		T9	31		T10	8
FlashRmaSt	34589	1			T3	35		T9	97		T10	8
TokenHashSt	37598503	1			T3	19374		T9	889		T10	265
TransCheckSt	26114	1			T3	48		T9	70		T10	8
CntProgSt	1593827	1			T2	724		T3	485		T9	25944
CntIncrSt	33298	1			T2	19		T3	63		T9	70
ClkMuxSt	33519	1			T2	19		T3	63		T9	70
IdleSt	20067105	1			T1	8200		T2	2734		T3	2017
ResetSt	6866896	1			T1	17641		T2	1726		T3	5686
arcs[ResetSt=>IdleSt]	51087	1			T1	83		T2	20		T3	64
arcs[IdleSt=>ScrapSt]	245	1			T15	1		T18	2		T19	2
arcs[IdleSt=>ClkMuxSt]	33327	1			T2	19		T3	63		T9	70
arcs[ClkMuxSt=>CntIncrSt]	33298	1			T2	19		T3	63		T9	70
arcs[CntIncrSt=>PostTransSt]	1665	1			T3	7		T37	12		T18	31
arcs[CntIncrSt=>CntProgSt]	31566	1			T2	19		T3	56		T9	70
arcs[CntProgSt=>PostTransSt]	4317	1			T2	19		T3	8		T13	17
arcs[CntProgSt=>TransCheckSt]	26114	1			T3	48		T9	70		T10	8
arcs[TransCheckSt=>PostTransSt]	3512	1			T3	13		T9	29		T37	10
arcs[TransCheckSt=>TokenHashSt]	22511	1			T3	35		T9	41		T10	8
arcs[TokenHashSt=>PostTransSt]	9549	1			T3	24		T9	10		T37	16
arcs[TokenHashSt=>FlashRmaSt]	12226	1			T3	11		T9	31		T10	8
arcs[FlashRmaSt=>TokenCheck0St]	12181	1			T3	11		T9	31		T10	8
arcs[TokenCheck0St=>PostTransSt]	3058	1			T3	6		T9	19		T37	5
arcs[TokenCheck0St=>TokenCheck1St]	9071	1			T3	5		T9	12		T10	8
arcs[TokenCheck1St=>PostTransSt]	631	1			T9	12		T18	2		T27	1
arcs[TransProgSt=>PostTransSt]	7534	1			T3	5		T10	8		T12	8
arcs[IdleSt=>EscalateSt]	128	1			T57	8		T54	4		T58	5
arcs[ClkMuxSt=>EscalateSt]	29	1			T54	3		T55	2		T56	3
arcs[CntIncrSt=>EscalateSt]	67	1			T57	2		T54	1		T58	3
arcs[CntProgSt=>EscalateSt]	1135	1			T57	34		T54	27		T58	27
arcs[TransCheckSt=>EscalateSt]	91	1			T55	8		T59	1		T60	1
arcs[TokenHashSt=>EscalateSt]	736	1			T57	9		T54	18		T58	9
arcs[FlashRmaSt=>EscalateSt]	45	1			T55	1		T59	3		T60	1
arcs[TokenCheck0St=>EscalateSt]	52	1			T57	2		T54	1		T55	1
arcs[TokenCheck1St=>EscalateSt]	22	1			T59	1		T60	1		T62	1
arcs[TransProgSt=>EscalateSt]	884	1			T57	21		T54	17		T58	24
arcs[PostTransSt=>EscalateSt]	4599	1			T2	19		T3	8		T13	17
arcs[InvalidSt=>EscalateSt]	13425	1			T1	79		T10	3		T5	48

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6866736	1			T1	17641		T2	1726		T3	5686
auto[0]	auto[IdleSt]	20067013	1			T1	8200		T2	2734		T3	2017
auto[0]	auto[ClkMuxSt]	33499	1			T2	19		T3	63		T9	70
auto[0]	auto[CntIncrSt]	33255	1			T2	19		T3	63		T9	70
auto[0]	auto[CntProgSt]	1593104	1			T2	724		T3	485		T9	25944
auto[0]	auto[TransCheckSt]	26052	1			T3	48		T9	70		T10	8
auto[0]	auto[TokenHashSt]	37598028	1			T3	19374		T9	889		T10	265
auto[0]	auto[FlashRmaSt]	34560	1			T3	35		T9	97		T10	8
auto[0]	auto[TokenCheck0St]	12150	1			T3	11		T9	31		T10	8
auto[0]	auto[TokenCheck1St]	9057	1			T3	5		T9	12		T10	8
auto[0]	auto[TransProgSt]	409075	1			T3	55		T10	764		T12	248
auto[0]	auto[PostTransSt]	11695545	1			T2	1451		T3	8708		T9	10717
auto[0]	auto[ScrapSt]	76104	1			T15	34		T18	899		T19	1044
auto[0]	auto[EscalateSt]	4972211	1			T1	27494		T2	1765		T3	504
auto[0]	auto[InvalidSt]	10535737	1			T1	96033		T10	208		T5	125339
auto[1]	auto[ResetSt]	160	1			T57	5		T54	1		T58	2
auto[1]	auto[IdleSt]	92	1			T57	6		T54	3		T58	3
auto[1]	auto[ClkMuxSt]	20	1			T54	2		T55	1		T56	2
auto[1]	auto[CntIncrSt]	43	1			T57	1		T54	1		T58	3
auto[1]	auto[CntProgSt]	723	1			T57	22		T54	17		T58	19
auto[1]	auto[TransCheckSt]	62	1			T55	6		T216	8		T154	11
auto[1]	auto[TokenHashSt]	475	1			T57	6		T54	12		T58	7
auto[1]	auto[FlashRmaSt]	29	1			T55	1		T59	2		T60	1
auto[1]	auto[TokenCheck0St]	31	1			T57	1		T54	1		T55	1
auto[1]	auto[TokenCheck1St]	14	1			T59	1		T154	2		T217	1
auto[1]	auto[TransProgSt]	578	1			T57	14		T54	11		T58	13
auto[1]	auto[PostTransSt]	2313	1			T2	10		T3	5		T13	7
auto[1]	auto[ScrapSt]	39	1			T57	5		T54	3		T58	1
auto[1]	auto[EscalateSt]	1315142	1			T1	4171		T2	980		T3	490
auto[1]	auto[InvalidSt]	6775	1			T1	43		T10	2		T5	20

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6866747	1			T1	17641		T2	1726		T3	5686
auto[0]	auto[IdleSt]	20067022	1			T1	8200		T2	2734		T3	2017
auto[0]	auto[ClkMuxSt]	33503	1			T2	19		T3	63		T9	70
auto[0]	auto[CntIncrSt]	33247	1			T2	19		T3	63		T9	70
auto[0]	auto[CntProgSt]	1593058	1			T2	724		T3	485		T9	25944
auto[0]	auto[TransCheckSt]	26051	1			T3	48		T9	70		T10	8
auto[0]	auto[TokenHashSt]	37597992	1			T3	19374		T9	889		T10	265
auto[0]	auto[FlashRmaSt]	34557	1			T3	35		T9	97		T10	8
auto[0]	auto[TokenCheck0St]	12146	1			T3	11		T9	31		T10	8
auto[0]	auto[TokenCheck1St]	9057	1			T3	5		T9	12		T10	8
auto[0]	auto[TransProgSt]	409067	1			T3	55		T10	764		T12	248
auto[0]	auto[PostTransSt]	11695499	1			T2	1452		T3	8710		T9	10717
auto[0]	auto[ScrapSt]	76107	1			T15	34		T18	899		T19	1044
auto[0]	auto[EscalateSt]	4964833	1			T1	28173		T2	1863		T3	700
auto[0]	auto[InvalidSt]	10535862	1			T1	96040		T10	209		T5	125331
auto[1]	auto[ResetSt]	149	1			T57	3		T54	2		T58	1
auto[1]	auto[IdleSt]	83	1			T57	7		T54	3		T58	3
auto[1]	auto[ClkMuxSt]	16	1			T54	1		T55	1		T56	1
auto[1]	auto[CntIncrSt]	51	1			T57	2		T58	1		T55	1
auto[1]	auto[CntProgSt]	769	1			T57	22		T54	20		T58	16
auto[1]	auto[TransCheckSt]	63	1			T55	7		T59	1		T60	1
auto[1]	auto[TokenHashSt]	511	1			T57	7		T54	12		T58	6
auto[1]	auto[FlashRmaSt]	32	1			T59	2		T60	1		T154	2
auto[1]	auto[TokenCheck0St]	35	1			T57	2		T54	1		T55	1
auto[1]	auto[TokenCheck1St]	14	1			T59	1		T60	1		T62	1
auto[1]	auto[TransProgSt]	586	1			T57	15		T54	11		T58	15
auto[1]	auto[PostTransSt]	2359	1			T2	9		T3	3		T13	10
auto[1]	auto[ScrapSt]	36	1			T57	1		T54	4		T58	1
auto[1]	auto[EscalateSt]	1322520	1			T1	3492		T2	882		T3	294
auto[1]	auto[InvalidSt]	6650	1			T1	36		T10	1		T5	28