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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.27 97.99 96.13 93.40 100.00 98.55 98.51 96.29


Total test records in report: 999
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T815 /workspace/coverage/default/44.lc_ctrl_prog_failure.3738782150 Aug 07 06:15:58 PM PDT 24 Aug 07 06:15:59 PM PDT 24 16081878 ps
T816 /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1035893000 Aug 07 06:14:50 PM PDT 24 Aug 07 06:15:02 PM PDT 24 1332774232 ps
T817 /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3593758593 Aug 07 06:13:36 PM PDT 24 Aug 07 06:13:37 PM PDT 24 25768073 ps
T818 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2902967392 Aug 07 06:15:20 PM PDT 24 Aug 07 06:15:33 PM PDT 24 408061448 ps
T819 /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3113859993 Aug 07 06:15:08 PM PDT 24 Aug 07 06:15:16 PM PDT 24 402477200 ps
T820 /workspace/coverage/default/27.lc_ctrl_security_escalation.281731387 Aug 07 06:15:07 PM PDT 24 Aug 07 06:15:16 PM PDT 24 570462467 ps
T821 /workspace/coverage/default/27.lc_ctrl_smoke.1927398090 Aug 07 06:15:09 PM PDT 24 Aug 07 06:15:11 PM PDT 24 28803077 ps
T822 /workspace/coverage/default/24.lc_ctrl_sec_mubi.2528801072 Aug 07 06:14:56 PM PDT 24 Aug 07 06:15:09 PM PDT 24 388616611 ps
T823 /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2806448400 Aug 07 06:15:33 PM PDT 24 Aug 07 06:15:49 PM PDT 24 557200429 ps
T824 /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2335967308 Aug 07 06:13:27 PM PDT 24 Aug 07 06:13:29 PM PDT 24 102377352 ps
T825 /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2934108790 Aug 07 06:15:33 PM PDT 24 Aug 07 06:15:42 PM PDT 24 727830977 ps
T826 /workspace/coverage/default/36.lc_ctrl_alert_test.3917820043 Aug 07 06:15:33 PM PDT 24 Aug 07 06:15:35 PM PDT 24 19118786 ps
T827 /workspace/coverage/default/4.lc_ctrl_state_failure.3887217654 Aug 07 06:13:38 PM PDT 24 Aug 07 06:14:03 PM PDT 24 807586950 ps
T828 /workspace/coverage/default/44.lc_ctrl_state_failure.1790649215 Aug 07 06:15:58 PM PDT 24 Aug 07 06:16:22 PM PDT 24 171668419 ps
T829 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2935550668 Aug 07 06:15:40 PM PDT 24 Aug 07 06:15:47 PM PDT 24 233731359 ps
T830 /workspace/coverage/default/18.lc_ctrl_errors.1521074092 Aug 07 06:14:44 PM PDT 24 Aug 07 06:14:59 PM PDT 24 525377998 ps
T831 /workspace/coverage/default/13.lc_ctrl_smoke.2663586490 Aug 07 06:14:24 PM PDT 24 Aug 07 06:14:28 PM PDT 24 181574794 ps
T832 /workspace/coverage/default/15.lc_ctrl_errors.2192136370 Aug 07 06:14:37 PM PDT 24 Aug 07 06:14:53 PM PDT 24 1563724049 ps
T833 /workspace/coverage/default/28.lc_ctrl_stress_all.337766381 Aug 07 06:15:16 PM PDT 24 Aug 07 06:17:25 PM PDT 24 74506817875 ps
T834 /workspace/coverage/default/26.lc_ctrl_state_failure.3815071118 Aug 07 06:15:05 PM PDT 24 Aug 07 06:15:25 PM PDT 24 139489873 ps
T835 /workspace/coverage/default/14.lc_ctrl_jtag_access.4030305226 Aug 07 06:14:34 PM PDT 24 Aug 07 06:14:36 PM PDT 24 471370519 ps
T836 /workspace/coverage/default/31.lc_ctrl_smoke.3751269194 Aug 07 06:15:20 PM PDT 24 Aug 07 06:15:26 PM PDT 24 90263688 ps
T837 /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1162806528 Aug 07 06:16:14 PM PDT 24 Aug 07 06:16:28 PM PDT 24 600455470 ps
T838 /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1173646677 Aug 07 06:14:24 PM PDT 24 Aug 07 06:14:36 PM PDT 24 571107780 ps
T839 /workspace/coverage/default/9.lc_ctrl_alert_test.1915222342 Aug 07 06:14:08 PM PDT 24 Aug 07 06:14:09 PM PDT 24 83223855 ps
T840 /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2569691373 Aug 07 06:13:47 PM PDT 24 Aug 07 06:13:58 PM PDT 24 1369210470 ps
T841 /workspace/coverage/default/35.lc_ctrl_prog_failure.564862235 Aug 07 06:15:34 PM PDT 24 Aug 07 06:15:38 PM PDT 24 328001830 ps
T842 /workspace/coverage/default/6.lc_ctrl_jtag_priority.1033151938 Aug 07 06:13:54 PM PDT 24 Aug 07 06:14:10 PM PDT 24 1598167331 ps
T843 /workspace/coverage/default/2.lc_ctrl_jtag_smoke.4243763250 Aug 07 06:13:30 PM PDT 24 Aug 07 06:13:35 PM PDT 24 255909532 ps
T844 /workspace/coverage/default/48.lc_ctrl_security_escalation.2992069238 Aug 07 06:16:07 PM PDT 24 Aug 07 06:16:19 PM PDT 24 556579485 ps
T845 /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2001824016 Aug 07 06:15:39 PM PDT 24 Aug 07 06:15:40 PM PDT 24 36895796 ps
T846 /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3478288791 Aug 07 06:13:26 PM PDT 24 Aug 07 06:13:36 PM PDT 24 300960585 ps
T847 /workspace/coverage/default/19.lc_ctrl_stress_all.1262583037 Aug 07 06:14:51 PM PDT 24 Aug 07 06:16:42 PM PDT 24 2570560305 ps
T848 /workspace/coverage/default/29.lc_ctrl_stress_all.4064048432 Aug 07 06:15:16 PM PDT 24 Aug 07 06:16:47 PM PDT 24 3754451132 ps
T849 /workspace/coverage/default/14.lc_ctrl_state_failure.2629698608 Aug 07 06:14:26 PM PDT 24 Aug 07 06:14:52 PM PDT 24 223072657 ps
T850 /workspace/coverage/default/16.lc_ctrl_security_escalation.1153022433 Aug 07 06:14:36 PM PDT 24 Aug 07 06:14:47 PM PDT 24 1544739633 ps
T851 /workspace/coverage/default/32.lc_ctrl_sec_token_digest.4204946330 Aug 07 06:15:33 PM PDT 24 Aug 07 06:15:49 PM PDT 24 1573693648 ps
T852 /workspace/coverage/default/29.lc_ctrl_prog_failure.486004724 Aug 07 06:15:16 PM PDT 24 Aug 07 06:15:20 PM PDT 24 839541354 ps
T853 /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2302546690 Aug 07 06:14:48 PM PDT 24 Aug 07 06:14:56 PM PDT 24 433139457 ps
T854 /workspace/coverage/default/41.lc_ctrl_jtag_access.3075251773 Aug 07 06:15:49 PM PDT 24 Aug 07 06:15:51 PM PDT 24 515007633 ps
T855 /workspace/coverage/default/7.lc_ctrl_jtag_smoke.282265334 Aug 07 06:14:01 PM PDT 24 Aug 07 06:14:08 PM PDT 24 193928277 ps
T856 /workspace/coverage/default/33.lc_ctrl_alert_test.4213634878 Aug 07 06:15:31 PM PDT 24 Aug 07 06:15:32 PM PDT 24 53739332 ps
T857 /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2450705136 Aug 07 06:13:32 PM PDT 24 Aug 07 06:13:51 PM PDT 24 3235801109 ps
T858 /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2529307471 Aug 07 06:13:32 PM PDT 24 Aug 07 06:18:24 PM PDT 24 59212817731 ps
T859 /workspace/coverage/default/30.lc_ctrl_stress_all.236703648 Aug 07 06:15:19 PM PDT 24 Aug 07 06:15:54 PM PDT 24 5333538581 ps
T860 /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2101103882 Aug 07 06:13:29 PM PDT 24 Aug 07 06:13:38 PM PDT 24 553142146 ps
T861 /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1260975020 Aug 07 06:13:58 PM PDT 24 Aug 07 06:14:07 PM PDT 24 1544703149 ps
T862 /workspace/coverage/default/20.lc_ctrl_state_post_trans.1827657377 Aug 07 06:14:53 PM PDT 24 Aug 07 06:15:01 PM PDT 24 452378440 ps
T863 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1253863474 Aug 07 06:13:46 PM PDT 24 Aug 07 06:13:59 PM PDT 24 446512591 ps
T864 /workspace/coverage/default/15.lc_ctrl_sec_mubi.1888767325 Aug 07 06:14:34 PM PDT 24 Aug 07 06:14:47 PM PDT 24 685730979 ps
T865 /workspace/coverage/default/36.lc_ctrl_prog_failure.3147649373 Aug 07 06:15:33 PM PDT 24 Aug 07 06:15:36 PM PDT 24 57952840 ps
T866 /workspace/coverage/default/26.lc_ctrl_state_post_trans.626592369 Aug 07 06:15:05 PM PDT 24 Aug 07 06:15:12 PM PDT 24 196674404 ps
T867 /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.172390991 Aug 07 06:14:53 PM PDT 24 Aug 07 06:14:54 PM PDT 24 14985510 ps
T868 /workspace/coverage/default/47.lc_ctrl_state_failure.1642066299 Aug 07 06:16:04 PM PDT 24 Aug 07 06:16:28 PM PDT 24 585235690 ps
T869 /workspace/coverage/default/17.lc_ctrl_jtag_errors.2292319399 Aug 07 06:14:41 PM PDT 24 Aug 07 06:15:13 PM PDT 24 5100326821 ps
T214 /workspace/coverage/default/4.lc_ctrl_claim_transition_if.916204571 Aug 07 06:13:39 PM PDT 24 Aug 07 06:13:40 PM PDT 24 31097584 ps
T870 /workspace/coverage/default/8.lc_ctrl_errors.4019243330 Aug 07 06:14:02 PM PDT 24 Aug 07 06:14:13 PM PDT 24 398453825 ps
T871 /workspace/coverage/default/38.lc_ctrl_smoke.2705616899 Aug 07 06:15:42 PM PDT 24 Aug 07 06:15:43 PM PDT 24 67507197 ps
T872 /workspace/coverage/default/13.lc_ctrl_stress_all.14640788 Aug 07 06:14:24 PM PDT 24 Aug 07 06:14:44 PM PDT 24 718149892 ps
T873 /workspace/coverage/default/48.lc_ctrl_state_failure.922960167 Aug 07 06:16:08 PM PDT 24 Aug 07 06:16:38 PM PDT 24 4147303669 ps
T874 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2294230269 Aug 07 06:15:45 PM PDT 24 Aug 07 06:15:54 PM PDT 24 275529053 ps
T875 /workspace/coverage/default/32.lc_ctrl_jtag_access.4105160377 Aug 07 06:15:32 PM PDT 24 Aug 07 06:15:38 PM PDT 24 8130910885 ps
T876 /workspace/coverage/default/22.lc_ctrl_state_failure.4241741263 Aug 07 06:14:53 PM PDT 24 Aug 07 06:15:18 PM PDT 24 442539286 ps
T212 /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1982249109 Aug 07 06:14:04 PM PDT 24 Aug 07 06:14:05 PM PDT 24 14533871 ps
T107 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1205248753 Aug 07 04:46:42 PM PDT 24 Aug 07 04:46:44 PM PDT 24 47160373 ps
T115 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3575499850 Aug 07 04:46:36 PM PDT 24 Aug 07 04:46:38 PM PDT 24 44338497 ps
T120 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1782582823 Aug 07 04:46:34 PM PDT 24 Aug 07 04:46:36 PM PDT 24 54316063 ps
T189 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.387847991 Aug 07 04:46:28 PM PDT 24 Aug 07 04:46:29 PM PDT 24 26559279 ps
T110 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2210784078 Aug 07 04:46:26 PM PDT 24 Aug 07 04:46:30 PM PDT 24 90854420 ps
T141 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2253070024 Aug 07 04:46:34 PM PDT 24 Aug 07 04:46:35 PM PDT 24 13139780 ps
T190 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3698885780 Aug 07 04:46:27 PM PDT 24 Aug 07 04:46:28 PM PDT 24 98326007 ps
T108 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2444958201 Aug 07 04:46:34 PM PDT 24 Aug 07 04:46:37 PM PDT 24 95947766 ps
T112 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3138741959 Aug 07 04:46:28 PM PDT 24 Aug 07 04:46:30 PM PDT 24 234251128 ps
T164 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1540196352 Aug 07 04:46:36 PM PDT 24 Aug 07 04:46:37 PM PDT 24 33607131 ps
T191 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1776795560 Aug 07 04:46:19 PM PDT 24 Aug 07 04:46:21 PM PDT 24 19702970 ps
T140 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.88013938 Aug 07 04:46:27 PM PDT 24 Aug 07 04:46:39 PM PDT 24 706775229 ps
T877 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1907686734 Aug 07 04:46:29 PM PDT 24 Aug 07 04:46:31 PM PDT 24 49546138 ps
T202 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2864261286 Aug 07 04:46:41 PM PDT 24 Aug 07 04:46:42 PM PDT 24 14451577 ps
T156 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2938442842 Aug 07 04:46:46 PM PDT 24 Aug 07 04:46:47 PM PDT 24 28744669 ps
T157 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2822367381 Aug 07 04:46:24 PM PDT 24 Aug 07 04:46:26 PM PDT 24 375808313 ps
T109 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1376570602 Aug 07 04:46:46 PM PDT 24 Aug 07 04:46:48 PM PDT 24 73855810 ps
T113 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2267409965 Aug 07 04:46:45 PM PDT 24 Aug 07 04:46:47 PM PDT 24 29469025 ps
T878 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1605048103 Aug 07 04:46:18 PM PDT 24 Aug 07 04:46:20 PM PDT 24 20233580 ps
T207 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3037068855 Aug 07 04:46:28 PM PDT 24 Aug 07 04:46:33 PM PDT 24 7911754702 ps
T138 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2011879661 Aug 07 04:46:24 PM PDT 24 Aug 07 04:46:25 PM PDT 24 118846322 ps
T158 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2389954264 Aug 07 04:46:18 PM PDT 24 Aug 07 04:46:20 PM PDT 24 180840737 ps
T114 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1018585880 Aug 07 04:46:43 PM PDT 24 Aug 07 04:46:45 PM PDT 24 45980832 ps
T203 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2168083092 Aug 07 04:46:34 PM PDT 24 Aug 07 04:46:35 PM PDT 24 26375692 ps
T879 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.353754265 Aug 07 04:46:10 PM PDT 24 Aug 07 04:46:20 PM PDT 24 375615616 ps
T159 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1301925731 Aug 07 04:46:33 PM PDT 24 Aug 07 04:46:35 PM PDT 24 182517540 ps
T172 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4252921019 Aug 07 04:46:15 PM PDT 24 Aug 07 04:46:20 PM PDT 24 784330960 ps
T111 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.10537797 Aug 07 04:46:40 PM PDT 24 Aug 07 04:46:43 PM PDT 24 160559716 ps
T131 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4118206062 Aug 07 04:46:34 PM PDT 24 Aug 07 04:46:38 PM PDT 24 151558215 ps
T880 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.657274475 Aug 07 04:46:12 PM PDT 24 Aug 07 04:46:35 PM PDT 24 5795379811 ps
T881 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3984470049 Aug 07 04:46:13 PM PDT 24 Aug 07 04:46:16 PM PDT 24 61235405 ps
T204 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.645821911 Aug 07 04:46:32 PM PDT 24 Aug 07 04:46:33 PM PDT 24 19519390 ps
T882 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1280866800 Aug 07 04:46:37 PM PDT 24 Aug 07 04:46:44 PM PDT 24 2745608531 ps
T205 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2524333230 Aug 07 04:46:28 PM PDT 24 Aug 07 04:46:29 PM PDT 24 21874484 ps
T133 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1802128820 Aug 07 04:46:43 PM PDT 24 Aug 07 04:46:46 PM PDT 24 384872023 ps
T883 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.4224188656 Aug 07 04:46:34 PM PDT 24 Aug 07 04:46:35 PM PDT 24 34797498 ps
T139 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3120965810 Aug 07 04:46:20 PM PDT 24 Aug 07 04:46:22 PM PDT 24 237032285 ps
T884 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3671542685 Aug 07 04:46:23 PM PDT 24 Aug 07 04:46:24 PM PDT 24 15050151 ps
T160 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1703343960 Aug 07 04:46:14 PM PDT 24 Aug 07 04:46:16 PM PDT 24 41993270 ps
T116 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2588550282 Aug 07 04:46:34 PM PDT 24 Aug 07 04:46:41 PM PDT 24 269145856 ps
T161 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3009451084 Aug 07 04:46:34 PM PDT 24 Aug 07 04:46:35 PM PDT 24 17181654 ps
T885 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3741668172 Aug 07 04:46:30 PM PDT 24 Aug 07 04:46:32 PM PDT 24 56913015 ps
T886 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.710098630 Aug 07 04:46:24 PM PDT 24 Aug 07 04:46:25 PM PDT 24 42502027 ps
T887 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3156018911 Aug 07 04:46:22 PM PDT 24 Aug 07 04:46:26 PM PDT 24 494560919 ps
T888 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2830378394 Aug 07 04:46:13 PM PDT 24 Aug 07 04:46:15 PM PDT 24 93648982 ps
T889 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1939940790 Aug 07 04:46:33 PM PDT 24 Aug 07 04:46:34 PM PDT 24 26895894 ps
T215 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2249070781 Aug 07 04:46:45 PM PDT 24 Aug 07 04:46:48 PM PDT 24 62512301 ps
T890 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1559967364 Aug 07 04:46:56 PM PDT 24 Aug 07 04:46:57 PM PDT 24 36485664 ps
T891 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2899137301 Aug 07 04:46:28 PM PDT 24 Aug 07 04:46:30 PM PDT 24 27009343 ps
T892 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.616659012 Aug 07 04:46:27 PM PDT 24 Aug 07 04:46:28 PM PDT 24 83305413 ps
T893 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1391066815 Aug 07 04:46:25 PM PDT 24 Aug 07 04:46:26 PM PDT 24 27974364 ps
T894 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.120191911 Aug 07 04:46:40 PM PDT 24 Aug 07 04:46:42 PM PDT 24 22724222 ps
T136 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.277348695 Aug 07 04:46:34 PM PDT 24 Aug 07 04:46:36 PM PDT 24 65505669 ps
T117 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.4192206352 Aug 07 04:46:47 PM PDT 24 Aug 07 04:46:49 PM PDT 24 24746801 ps
T895 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.657459789 Aug 07 04:46:18 PM PDT 24 Aug 07 04:46:26 PM PDT 24 697723662 ps
T124 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2486880492 Aug 07 04:46:41 PM PDT 24 Aug 07 04:46:45 PM PDT 24 347533469 ps
T896 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1794093327 Aug 07 04:46:48 PM PDT 24 Aug 07 04:46:50 PM PDT 24 25890267 ps
T123 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3066297050 Aug 07 04:46:33 PM PDT 24 Aug 07 04:46:37 PM PDT 24 53602415 ps
T897 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.722249537 Aug 07 04:46:23 PM PDT 24 Aug 07 04:46:26 PM PDT 24 1070138649 ps
T898 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.324985745 Aug 07 04:46:28 PM PDT 24 Aug 07 04:46:29 PM PDT 24 19272555 ps
T192 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.170836055 Aug 07 04:46:36 PM PDT 24 Aug 07 04:46:37 PM PDT 24 13936739 ps
T899 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.414719039 Aug 07 04:46:38 PM PDT 24 Aug 07 04:46:40 PM PDT 24 34759258 ps
T900 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3518511125 Aug 07 04:46:54 PM PDT 24 Aug 07 04:46:55 PM PDT 24 18554919 ps
T121 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1763063456 Aug 07 04:46:44 PM PDT 24 Aug 07 04:46:47 PM PDT 24 77022147 ps
T901 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2224163354 Aug 07 04:46:33 PM PDT 24 Aug 07 04:46:35 PM PDT 24 268605536 ps
T902 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3207877688 Aug 07 04:46:27 PM PDT 24 Aug 07 04:46:29 PM PDT 24 328704969 ps
T126 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2204819929 Aug 07 04:46:21 PM PDT 24 Aug 07 04:46:23 PM PDT 24 131308810 ps
T903 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3085050152 Aug 07 04:46:32 PM PDT 24 Aug 07 04:46:33 PM PDT 24 138734596 ps
T122 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1248398210 Aug 07 04:46:23 PM PDT 24 Aug 07 04:46:26 PM PDT 24 457312562 ps
T904 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1893735704 Aug 07 04:46:41 PM PDT 24 Aug 07 04:46:42 PM PDT 24 94623601 ps
T129 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3481039343 Aug 07 04:46:37 PM PDT 24 Aug 07 04:46:41 PM PDT 24 457457220 ps
T127 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2250327408 Aug 07 04:46:33 PM PDT 24 Aug 07 04:46:37 PM PDT 24 80439676 ps
T905 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.808135745 Aug 07 04:46:33 PM PDT 24 Aug 07 04:46:35 PM PDT 24 85897329 ps
T906 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2385067250 Aug 07 04:46:42 PM PDT 24 Aug 07 04:46:43 PM PDT 24 86638453 ps
T130 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3852004620 Aug 07 04:46:39 PM PDT 24 Aug 07 04:46:43 PM PDT 24 458226233 ps
T907 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1282468582 Aug 07 04:46:40 PM PDT 24 Aug 07 04:46:45 PM PDT 24 224659675 ps
T908 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1656291221 Aug 07 04:46:34 PM PDT 24 Aug 07 04:46:41 PM PDT 24 4562034429 ps
T909 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2630237122 Aug 07 04:46:44 PM PDT 24 Aug 07 04:46:48 PM PDT 24 110097579 ps
T910 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3800484867 Aug 07 04:46:39 PM PDT 24 Aug 07 04:46:41 PM PDT 24 126581922 ps
T193 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.989391235 Aug 07 04:46:34 PM PDT 24 Aug 07 04:46:35 PM PDT 24 12129796 ps
T911 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3471234135 Aug 07 04:46:27 PM PDT 24 Aug 07 04:46:28 PM PDT 24 59583336 ps
T912 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.162538084 Aug 07 04:46:27 PM PDT 24 Aug 07 04:46:28 PM PDT 24 23044828 ps
T913 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2699569060 Aug 07 04:46:19 PM PDT 24 Aug 07 04:46:25 PM PDT 24 193009522 ps
T914 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3614687485 Aug 07 04:46:33 PM PDT 24 Aug 07 04:46:34 PM PDT 24 57484494 ps
T134 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1653334372 Aug 07 04:46:31 PM PDT 24 Aug 07 04:46:33 PM PDT 24 318280242 ps
T915 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3142073920 Aug 07 04:46:27 PM PDT 24 Aug 07 04:46:28 PM PDT 24 84585126 ps
T916 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.821605405 Aug 07 04:46:25 PM PDT 24 Aug 07 04:46:28 PM PDT 24 143910087 ps
T125 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3196144265 Aug 07 04:46:39 PM PDT 24 Aug 07 04:46:42 PM PDT 24 710732415 ps
T917 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1244666109 Aug 07 04:46:38 PM PDT 24 Aug 07 04:46:40 PM PDT 24 25010997 ps
T918 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.970112666 Aug 07 04:46:26 PM PDT 24 Aug 07 04:46:28 PM PDT 24 184432934 ps
T919 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2907452199 Aug 07 04:46:47 PM PDT 24 Aug 07 04:46:53 PM PDT 24 153911377 ps
T920 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2523143806 Aug 07 04:46:18 PM PDT 24 Aug 07 04:46:19 PM PDT 24 126030288 ps
T921 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.65661386 Aug 07 04:46:35 PM PDT 24 Aug 07 04:46:37 PM PDT 24 578746859 ps
T118 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4239775148 Aug 07 04:46:23 PM PDT 24 Aug 07 04:46:27 PM PDT 24 193509091 ps
T922 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2010640851 Aug 07 04:46:23 PM PDT 24 Aug 07 04:46:25 PM PDT 24 89527365 ps
T923 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1319959910 Aug 07 04:46:40 PM PDT 24 Aug 07 04:46:41 PM PDT 24 23247118 ps
T924 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2688482322 Aug 07 04:46:45 PM PDT 24 Aug 07 04:46:47 PM PDT 24 43527129 ps
T925 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3344936467 Aug 07 04:46:42 PM PDT 24 Aug 07 04:46:45 PM PDT 24 282953704 ps
T926 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2874913940 Aug 07 04:46:27 PM PDT 24 Aug 07 04:46:28 PM PDT 24 167495885 ps
T927 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3615102876 Aug 07 04:46:43 PM PDT 24 Aug 07 04:46:44 PM PDT 24 77428970 ps
T928 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1334584366 Aug 07 04:46:33 PM PDT 24 Aug 07 04:46:35 PM PDT 24 139152131 ps
T929 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3598269387 Aug 07 04:46:38 PM PDT 24 Aug 07 04:46:48 PM PDT 24 355403355 ps
T930 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1036602722 Aug 07 04:46:38 PM PDT 24 Aug 07 04:46:39 PM PDT 24 55079564 ps
T194 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4084012297 Aug 07 04:46:31 PM PDT 24 Aug 07 04:46:32 PM PDT 24 58812702 ps
T931 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.718188405 Aug 07 04:46:36 PM PDT 24 Aug 07 04:46:37 PM PDT 24 11577875 ps
T932 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3180492731 Aug 07 04:46:40 PM PDT 24 Aug 07 04:46:41 PM PDT 24 46478626 ps
T933 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.647123644 Aug 07 04:46:30 PM PDT 24 Aug 07 04:46:45 PM PDT 24 1478002481 ps
T934 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.973205251 Aug 07 04:46:52 PM PDT 24 Aug 07 04:46:53 PM PDT 24 72946168 ps
T935 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.922440278 Aug 07 04:46:22 PM PDT 24 Aug 07 04:46:23 PM PDT 24 62188146 ps
T195 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2804125971 Aug 07 04:46:22 PM PDT 24 Aug 07 04:46:24 PM PDT 24 92586417 ps
T128 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.384619609 Aug 07 04:46:38 PM PDT 24 Aug 07 04:46:42 PM PDT 24 143921786 ps
T936 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2770718289 Aug 07 04:46:46 PM PDT 24 Aug 07 04:46:48 PM PDT 24 24664610 ps
T937 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2670048044 Aug 07 04:46:18 PM PDT 24 Aug 07 04:46:19 PM PDT 24 20930039 ps
T196 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3459158611 Aug 07 04:46:30 PM PDT 24 Aug 07 04:46:31 PM PDT 24 48731899 ps
T197 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.977120042 Aug 07 04:46:22 PM PDT 24 Aug 07 04:46:23 PM PDT 24 42500915 ps
T938 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3677970620 Aug 07 04:46:20 PM PDT 24 Aug 07 04:46:21 PM PDT 24 29754941 ps
T939 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.216329931 Aug 07 04:46:32 PM PDT 24 Aug 07 04:46:37 PM PDT 24 758431580 ps
T940 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3413369514 Aug 07 04:46:40 PM PDT 24 Aug 07 04:46:43 PM PDT 24 759500953 ps
T941 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.111687764 Aug 07 04:46:33 PM PDT 24 Aug 07 04:46:35 PM PDT 24 585829923 ps
T942 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3513769200 Aug 07 04:46:33 PM PDT 24 Aug 07 04:46:34 PM PDT 24 18952999 ps
T943 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2535761375 Aug 07 04:46:18 PM PDT 24 Aug 07 04:46:19 PM PDT 24 32329253 ps
T944 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1038601737 Aug 07 04:46:38 PM PDT 24 Aug 07 04:46:41 PM PDT 24 56785156 ps
T945 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1663540978 Aug 07 04:46:30 PM PDT 24 Aug 07 04:46:32 PM PDT 24 248743851 ps
T198 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3408433971 Aug 07 04:46:38 PM PDT 24 Aug 07 04:46:39 PM PDT 24 29086505 ps
T946 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3619646799 Aug 07 04:46:33 PM PDT 24 Aug 07 04:46:36 PM PDT 24 160368720 ps
T947 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.14959172 Aug 07 04:46:17 PM PDT 24 Aug 07 04:46:19 PM PDT 24 264684552 ps
T948 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3144944087 Aug 07 04:46:29 PM PDT 24 Aug 07 04:46:30 PM PDT 24 20585473 ps
T949 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4043023907 Aug 07 04:46:38 PM PDT 24 Aug 07 04:46:40 PM PDT 24 50080720 ps
T950 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1922895557 Aug 07 04:46:20 PM PDT 24 Aug 07 04:46:21 PM PDT 24 59192815 ps
T951 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1083292473 Aug 07 04:46:20 PM PDT 24 Aug 07 04:46:58 PM PDT 24 1800369983 ps
T952 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2660794229 Aug 07 04:46:20 PM PDT 24 Aug 07 04:46:22 PM PDT 24 34522267 ps
T953 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1492306646 Aug 07 04:46:21 PM PDT 24 Aug 07 04:46:23 PM PDT 24 54083904 ps
T954 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3347838673 Aug 07 04:46:33 PM PDT 24 Aug 07 04:46:36 PM PDT 24 68361179 ps
T955 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3097729402 Aug 07 04:46:20 PM PDT 24 Aug 07 04:46:22 PM PDT 24 73898634 ps
T199 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.207871978 Aug 07 04:46:40 PM PDT 24 Aug 07 04:46:41 PM PDT 24 52011309 ps
T956 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3541681550 Aug 07 04:46:32 PM PDT 24 Aug 07 04:46:33 PM PDT 24 113984164 ps
T957 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2620249317 Aug 07 04:46:39 PM PDT 24 Aug 07 04:47:05 PM PDT 24 1110026625 ps
T958 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3119388562 Aug 07 04:46:25 PM PDT 24 Aug 07 04:46:28 PM PDT 24 826167440 ps
T959 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3581901623 Aug 07 04:46:39 PM PDT 24 Aug 07 04:46:40 PM PDT 24 27354816 ps
T119 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1238406615 Aug 07 04:46:43 PM PDT 24 Aug 07 04:46:46 PM PDT 24 1348894433 ps
T960 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1360961688 Aug 07 04:46:23 PM PDT 24 Aug 07 04:46:24 PM PDT 24 33211399 ps
T961 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1591921651 Aug 07 04:46:20 PM PDT 24 Aug 07 04:46:30 PM PDT 24 1699376774 ps
T962 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2539862994 Aug 07 04:46:34 PM PDT 24 Aug 07 04:46:40 PM PDT 24 1226484092 ps
T963 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.741127156 Aug 07 04:46:19 PM PDT 24 Aug 07 04:46:46 PM PDT 24 4569862413 ps
T964 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3927208542 Aug 07 04:46:19 PM PDT 24 Aug 07 04:46:32 PM PDT 24 8082224814 ps
T965 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3541272588 Aug 07 04:46:42 PM PDT 24 Aug 07 04:46:46 PM PDT 24 345932905 ps
T966 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2290565617 Aug 07 04:46:25 PM PDT 24 Aug 07 04:46:27 PM PDT 24 66995795 ps
T967 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3156700544 Aug 07 04:46:20 PM PDT 24 Aug 07 04:46:22 PM PDT 24 22044144 ps
T968 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2132273132 Aug 07 04:46:42 PM PDT 24 Aug 07 04:46:43 PM PDT 24 46675061 ps
T969 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3143476907 Aug 07 04:46:31 PM PDT 24 Aug 07 04:46:33 PM PDT 24 90479841 ps
T132 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2376768917 Aug 07 04:46:29 PM PDT 24 Aug 07 04:46:32 PM PDT 24 212888797 ps
T970 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3419397236 Aug 07 04:46:33 PM PDT 24 Aug 07 04:46:36 PM PDT 24 170359770 ps
T971 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.280400500 Aug 07 04:46:41 PM PDT 24 Aug 07 04:46:42 PM PDT 24 13670192 ps
T972 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4125052652 Aug 07 04:46:34 PM PDT 24 Aug 07 04:46:35 PM PDT 24 37229497 ps
T973 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3356039322 Aug 07 04:46:39 PM PDT 24 Aug 07 04:46:41 PM PDT 24 33057085 ps
T974 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2457285455 Aug 07 04:46:31 PM PDT 24 Aug 07 04:46:38 PM PDT 24 3988078848 ps
T975 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3216772489 Aug 07 04:46:30 PM PDT 24 Aug 07 04:46:31 PM PDT 24 239121284 ps
T976 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2817913734 Aug 07 04:46:37 PM PDT 24 Aug 07 04:46:42 PM PDT 24 290133111 ps
T977 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1972388406 Aug 07 04:46:31 PM PDT 24 Aug 07 04:46:32 PM PDT 24 71601284 ps
T978 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3421963052 Aug 07 04:46:40 PM PDT 24 Aug 07 04:46:42 PM PDT 24 16839069 ps
T979 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.553362419 Aug 07 04:46:19 PM PDT 24 Aug 07 04:46:20 PM PDT 24 109775592 ps
T200 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.541508243 Aug 07 04:46:45 PM PDT 24 Aug 07 04:46:46 PM PDT 24 13591929 ps
T980 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1869298843 Aug 07 04:46:38 PM PDT 24 Aug 07 04:46:39 PM PDT 24 117604996 ps
T135 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1544648970 Aug 07 04:46:40 PM PDT 24 Aug 07 04:46:43 PM PDT 24 268102073 ps
T981 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2237752573 Aug 07 04:46:39 PM PDT 24 Aug 07 04:46:42 PM PDT 24 91468932 ps
T982 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.876279782 Aug 07 04:46:30 PM PDT 24 Aug 07 04:46:33 PM PDT 24 326422811 ps
T137 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1342546986 Aug 07 04:46:34 PM PDT 24 Aug 07 04:46:38 PM PDT 24 190691928 ps
T983 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2042145491 Aug 07 04:46:26 PM PDT 24 Aug 07 04:46:27 PM PDT 24 129152558 ps
T984 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3428681087 Aug 07 04:46:42 PM PDT 24 Aug 07 04:46:43 PM PDT 24 45690087 ps
T985 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.154532594 Aug 07 04:46:40 PM PDT 24 Aug 07 04:46:42 PM PDT 24 43746367 ps
T201 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2224019100 Aug 07 04:46:19 PM PDT 24 Aug 07 04:46:20 PM PDT 24 31448212 ps
T986 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3336807005 Aug 07 04:46:42 PM PDT 24 Aug 07 04:46:43 PM PDT 24 57943762 ps
T987 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.126342359 Aug 07 04:46:15 PM PDT 24 Aug 07 04:46:18 PM PDT 24 40348026 ps
T988 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2257299396 Aug 07 04:46:23 PM PDT 24 Aug 07 04:46:24 PM PDT 24 12554872 ps
T989 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.316118910 Aug 07 04:46:40 PM PDT 24 Aug 07 04:46:41 PM PDT 24 15054957 ps
T990 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3017573794 Aug 07 04:46:27 PM PDT 24 Aug 07 04:46:50 PM PDT 24 6579931823 ps
T991 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.4179079587 Aug 07 04:46:12 PM PDT 24 Aug 07 04:46:14 PM PDT 24 476798966 ps
T992 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2081980246 Aug 07 04:46:20 PM PDT 24 Aug 07 04:46:24 PM PDT 24 103462328 ps
T993 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2143642908 Aug 07 04:46:34 PM PDT 24 Aug 07 04:46:35 PM PDT 24 73831766 ps
T994 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3414129388 Aug 07 04:46:43 PM PDT 24 Aug 07 04:46:44 PM PDT 24 52694635 ps
T995 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.156919380 Aug 07 04:46:28 PM PDT 24 Aug 07 04:46:34 PM PDT 24 793824264 ps
T996 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.644119245 Aug 07 04:46:20 PM PDT 24 Aug 07 04:46:23 PM PDT 24 49735936 ps
T997 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1162949934 Aug 07 04:46:35 PM PDT 24 Aug 07 04:46:49 PM PDT 24 1107459992 ps
T998 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1150143153 Aug 07 04:46:25 PM PDT 24 Aug 07 04:46:27 PM PDT 24 521549641 ps
T999 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2320100014 Aug 07 04:46:37 PM PDT 24 Aug 07 04:46:38 PM PDT 24 124815942 ps

Test location /workspace/coverage/default/11.lc_ctrl_errors.1399672598
Short name T3
Test name
Test status
Simulation time 2346924181 ps
CPU time 12.61 seconds
Started Aug 07 06:14:13 PM PDT 24
Finished Aug 07 06:14:25 PM PDT 24
Peak memory 218912 kb
Host smart-34313788-8091-48eb-9c83-88b150dc83e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399672598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1399672598
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1140094852
Short name T18
Test name
Test status
Simulation time 9258797095 ps
CPU time 180.08 seconds
Started Aug 07 06:15:36 PM PDT 24
Finished Aug 07 06:18:36 PM PDT 24
Peak memory 250880 kb
Host smart-3e724336-04c9-4ac2-9c02-bdcbbfe48511
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140094852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1140094852
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1840621922
Short name T55
Test name
Test status
Simulation time 416440009 ps
CPU time 10.47 seconds
Started Aug 07 06:15:26 PM PDT 24
Finished Aug 07 06:15:37 PM PDT 24
Peak memory 224928 kb
Host smart-ae114a1c-abd1-48a0-902e-dc33dd0db7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840621922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1840621922
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.3358657820
Short name T38
Test name
Test status
Simulation time 3045580955 ps
CPU time 13.28 seconds
Started Aug 07 06:15:27 PM PDT 24
Finished Aug 07 06:15:41 PM PDT 24
Peak memory 220024 kb
Host smart-bd09133d-31d0-449e-8f7f-716e10484022
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358657820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3358657820
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3712428726
Short name T45
Test name
Test status
Simulation time 19081611538 ps
CPU time 695.32 seconds
Started Aug 07 06:13:20 PM PDT 24
Finished Aug 07 06:24:56 PM PDT 24
Peak memory 513128 kb
Host smart-99c9bcee-5703-4078-bf63-74703d50e4bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3712428726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.3712428726
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2444958201
Short name T108
Test name
Test status
Simulation time 95947766 ps
CPU time 3.03 seconds
Started Aug 07 04:46:34 PM PDT 24
Finished Aug 07 04:46:37 PM PDT 24
Peak memory 222476 kb
Host smart-e5499b6a-d1b4-4435-b745-a36acaa02599
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444958201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2444958201
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2937441562
Short name T16
Test name
Test status
Simulation time 4881230692 ps
CPU time 112.95 seconds
Started Aug 07 06:15:59 PM PDT 24
Finished Aug 07 06:17:52 PM PDT 24
Peak memory 276272 kb
Host smart-e7f9dba5-5af9-4272-a60b-f47cff31f1b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937441562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2937441562
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.4168164908
Short name T11
Test name
Test status
Simulation time 14952321 ps
CPU time 1.01 seconds
Started Aug 07 06:15:21 PM PDT 24
Finished Aug 07 06:15:22 PM PDT 24
Peak memory 208936 kb
Host smart-b1471a00-ed8f-4d86-a169-0256b15b9484
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168164908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.4168164908
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3761957375
Short name T61
Test name
Test status
Simulation time 138132933 ps
CPU time 26.08 seconds
Started Aug 07 06:13:32 PM PDT 24
Finished Aug 07 06:13:58 PM PDT 24
Peak memory 269672 kb
Host smart-7cfbf4e7-5f95-43c2-84bc-0a6cb3111e89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761957375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3761957375
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2210784078
Short name T110
Test name
Test status
Simulation time 90854420 ps
CPU time 3.56 seconds
Started Aug 07 04:46:26 PM PDT 24
Finished Aug 07 04:46:30 PM PDT 24
Peak memory 222872 kb
Host smart-941b1dec-6074-42a6-bc00-77608f8b6725
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221078
4078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2210784078
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2737612476
Short name T217
Test name
Test status
Simulation time 345650938 ps
CPU time 9.18 seconds
Started Aug 07 06:15:32 PM PDT 24
Finished Aug 07 06:15:41 PM PDT 24
Peak memory 225996 kb
Host smart-20dfb9a2-f21c-45ef-a19b-b19dae5b0fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737612476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2737612476
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.658977598
Short name T94
Test name
Test status
Simulation time 32973494732 ps
CPU time 179.52 seconds
Started Aug 07 06:14:23 PM PDT 24
Finished Aug 07 06:17:23 PM PDT 24
Peak memory 258560 kb
Host smart-c65a70fb-25cf-4f21-8add-70c0f2cdb3b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658977598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.658977598
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2597531104
Short name T53
Test name
Test status
Simulation time 1356412151 ps
CPU time 14.01 seconds
Started Aug 07 06:14:01 PM PDT 24
Finished Aug 07 06:14:15 PM PDT 24
Peak memory 225396 kb
Host smart-af506363-49b1-45f0-80c0-d4870d45bea7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597531104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
597531104
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1017886919
Short name T163
Test name
Test status
Simulation time 366852160 ps
CPU time 11.87 seconds
Started Aug 07 06:14:14 PM PDT 24
Finished Aug 07 06:14:26 PM PDT 24
Peak memory 218048 kb
Host smart-a84810ae-9c33-4392-89b2-ecf46375fc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017886919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1017886919
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3205973521
Short name T90
Test name
Test status
Simulation time 16326688 ps
CPU time 0.92 seconds
Started Aug 07 06:15:50 PM PDT 24
Finished Aug 07 06:15:52 PM PDT 24
Peak memory 208848 kb
Host smart-d9b3534d-fb32-47ab-bd6e-2360c39bc600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205973521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3205973521
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2626549267
Short name T6
Test name
Test status
Simulation time 558127761 ps
CPU time 3.79 seconds
Started Aug 07 06:13:20 PM PDT 24
Finished Aug 07 06:13:24 PM PDT 24
Peak memory 217592 kb
Host smart-60934311-b5c4-46d5-bc44-160765de0ddb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626549267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2626549267
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2253070024
Short name T141
Test name
Test status
Simulation time 13139780 ps
CPU time 1.02 seconds
Started Aug 07 04:46:34 PM PDT 24
Finished Aug 07 04:46:35 PM PDT 24
Peak memory 209344 kb
Host smart-fa7735c5-4125-4f90-8320-ef191f5305a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253070024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2253070024
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3196144265
Short name T125
Test name
Test status
Simulation time 710732415 ps
CPU time 3.23 seconds
Started Aug 07 04:46:39 PM PDT 24
Finished Aug 07 04:46:42 PM PDT 24
Peak memory 221904 kb
Host smart-5f11fc74-b720-4304-b50e-bbb1ad76bfe4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196144265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3196144265
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2630237122
Short name T909
Test name
Test status
Simulation time 110097579 ps
CPU time 3.16 seconds
Started Aug 07 04:46:44 PM PDT 24
Finished Aug 07 04:46:48 PM PDT 24
Peak memory 217980 kb
Host smart-67e0a9c6-7c28-4e03-b41b-35ba18c98fa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630237122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2630237122
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1376570602
Short name T109
Test name
Test status
Simulation time 73855810 ps
CPU time 2.29 seconds
Started Aug 07 04:46:46 PM PDT 24
Finished Aug 07 04:46:48 PM PDT 24
Peak memory 222204 kb
Host smart-1a80a692-0b5a-43eb-a412-75b3b27923b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376570602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1376570602
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2250327408
Short name T127
Test name
Test status
Simulation time 80439676 ps
CPU time 3.63 seconds
Started Aug 07 04:46:33 PM PDT 24
Finished Aug 07 04:46:37 PM PDT 24
Peak memory 222388 kb
Host smart-47f082a0-472b-406e-82ad-63658d124b2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250327408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2250327408
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1818809634
Short name T27
Test name
Test status
Simulation time 734395954 ps
CPU time 16.84 seconds
Started Aug 07 06:15:52 PM PDT 24
Finished Aug 07 06:16:09 PM PDT 24
Peak memory 219912 kb
Host smart-f944b98e-f734-406c-a6c8-d4740225aa6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818809634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1818809634
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4239775148
Short name T118
Test name
Test status
Simulation time 193509091 ps
CPU time 3.58 seconds
Started Aug 07 04:46:23 PM PDT 24
Finished Aug 07 04:46:27 PM PDT 24
Peak memory 217616 kb
Host smart-01a92b7b-b069-445d-9ca7-f92183701259
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239775148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.4239775148
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1653334372
Short name T134
Test name
Test status
Simulation time 318280242 ps
CPU time 1.95 seconds
Started Aug 07 04:46:31 PM PDT 24
Finished Aug 07 04:46:33 PM PDT 24
Peak memory 222112 kb
Host smart-a430d6e1-4308-4bad-a5a1-25cb3e856402
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653334372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1653334372
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3837090679
Short name T19
Test name
Test status
Simulation time 2306513512 ps
CPU time 64.66 seconds
Started Aug 07 06:14:42 PM PDT 24
Finished Aug 07 06:15:47 PM PDT 24
Peak memory 250900 kb
Host smart-e9b03dfd-86bf-4c7e-828d-fe491da9c26c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837090679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3837090679
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2486880492
Short name T124
Test name
Test status
Simulation time 347533469 ps
CPU time 3.54 seconds
Started Aug 07 04:46:41 PM PDT 24
Finished Aug 07 04:46:45 PM PDT 24
Peak memory 222248 kb
Host smart-82d72d50-7e50-4140-8353-787cf1726423
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486880492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2486880492
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1839101428
Short name T210
Test name
Test status
Simulation time 12343505 ps
CPU time 0.98 seconds
Started Aug 07 06:13:32 PM PDT 24
Finished Aug 07 06:13:33 PM PDT 24
Peak memory 208768 kb
Host smart-f5b4fc18-5506-4502-9245-552147c019c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839101428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1839101428
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.916204571
Short name T214
Test name
Test status
Simulation time 31097584 ps
CPU time 0.92 seconds
Started Aug 07 06:13:39 PM PDT 24
Finished Aug 07 06:13:40 PM PDT 24
Peak memory 208724 kb
Host smart-e3e01a04-e809-4ee2-a142-55a09a7e9ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916204571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.916204571
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.4286564193
Short name T80
Test name
Test status
Simulation time 11699886 ps
CPU time 0.84 seconds
Started Aug 07 06:13:48 PM PDT 24
Finished Aug 07 06:13:49 PM PDT 24
Peak memory 208672 kb
Host smart-d9d1a425-51c3-4cd9-b430-6c935442d168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286564193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.4286564193
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1652980956
Short name T211
Test name
Test status
Simulation time 21106654 ps
CPU time 0.95 seconds
Started Aug 07 06:13:49 PM PDT 24
Finished Aug 07 06:13:50 PM PDT 24
Peak memory 208736 kb
Host smart-485accfd-c571-4cf5-930c-9e42820ffac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652980956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1652980956
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1677313628
Short name T13
Test name
Test status
Simulation time 646117696 ps
CPU time 9.2 seconds
Started Aug 07 06:13:19 PM PDT 24
Finished Aug 07 06:13:28 PM PDT 24
Peak memory 218136 kb
Host smart-412bbbc6-4695-4eec-9c49-229a6fa98e5b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677313628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1677313628
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3066297050
Short name T123
Test name
Test status
Simulation time 53602415 ps
CPU time 3.83 seconds
Started Aug 07 04:46:33 PM PDT 24
Finished Aug 07 04:46:37 PM PDT 24
Peak memory 217896 kb
Host smart-96fd90d4-f140-4acb-9480-cc6fd7d0e295
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066297050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3066297050
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.10537797
Short name T111
Test name
Test status
Simulation time 160559716 ps
CPU time 3.72 seconds
Started Aug 07 04:46:40 PM PDT 24
Finished Aug 07 04:46:43 PM PDT 24
Peak memory 217632 kb
Host smart-b1da12ab-790a-435c-ac25-7168369782fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10537797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_e
rr.10537797
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1802128820
Short name T133
Test name
Test status
Simulation time 384872023 ps
CPU time 2.67 seconds
Started Aug 07 04:46:43 PM PDT 24
Finished Aug 07 04:46:46 PM PDT 24
Peak memory 217656 kb
Host smart-a75d9942-4d80-4317-8075-aa29895c1b4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802128820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1802128820
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2376768917
Short name T132
Test name
Test status
Simulation time 212888797 ps
CPU time 2.61 seconds
Started Aug 07 04:46:29 PM PDT 24
Finished Aug 07 04:46:32 PM PDT 24
Peak memory 217568 kb
Host smart-935d010b-9ef4-4932-9274-9cf759917251
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376768917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2376768917
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.4041939681
Short name T52
Test name
Test status
Simulation time 4604714424 ps
CPU time 107.18 seconds
Started Aug 07 06:14:43 PM PDT 24
Finished Aug 07 06:16:30 PM PDT 24
Peak memory 270868 kb
Host smart-f98c5853-75d5-49b5-bd5c-576c719c919d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041939681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.4041939681
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3994278778
Short name T98
Test name
Test status
Simulation time 604204232 ps
CPU time 24.4 seconds
Started Aug 07 06:13:20 PM PDT 24
Finished Aug 07 06:13:45 PM PDT 24
Peak memory 267908 kb
Host smart-60067c3a-aeb8-433e-be89-3db429c445f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994278778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3994278778
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2804125971
Short name T195
Test name
Test status
Simulation time 92586417 ps
CPU time 1.38 seconds
Started Aug 07 04:46:22 PM PDT 24
Finished Aug 07 04:46:24 PM PDT 24
Peak memory 209364 kb
Host smart-413feafe-03ff-4adc-9aac-44d84253066e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804125971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2804125971
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1360961688
Short name T960
Test name
Test status
Simulation time 33211399 ps
CPU time 1.17 seconds
Started Aug 07 04:46:23 PM PDT 24
Finished Aug 07 04:46:24 PM PDT 24
Peak memory 209364 kb
Host smart-fc0315a6-37d0-4b87-a804-54bd6a0d1292
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360961688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1360961688
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.977120042
Short name T197
Test name
Test status
Simulation time 42500915 ps
CPU time 1.15 seconds
Started Aug 07 04:46:22 PM PDT 24
Finished Aug 07 04:46:23 PM PDT 24
Peak memory 218116 kb
Host smart-a75938a0-12b9-4931-a06d-c99982b44f49
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977120042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.977120042
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2670048044
Short name T937
Test name
Test status
Simulation time 20930039 ps
CPU time 1.37 seconds
Started Aug 07 04:46:18 PM PDT 24
Finished Aug 07 04:46:19 PM PDT 24
Peak memory 217828 kb
Host smart-df32be80-d64c-42b5-a213-5865f7500283
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670048044 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2670048044
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3518511125
Short name T900
Test name
Test status
Simulation time 18554919 ps
CPU time 0.9 seconds
Started Aug 07 04:46:54 PM PDT 24
Finished Aug 07 04:46:55 PM PDT 24
Peak memory 209364 kb
Host smart-5e01a474-63fa-46c3-9ac6-4df92df5799b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518511125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3518511125
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3984470049
Short name T881
Test name
Test status
Simulation time 61235405 ps
CPU time 2.19 seconds
Started Aug 07 04:46:13 PM PDT 24
Finished Aug 07 04:46:16 PM PDT 24
Peak memory 209356 kb
Host smart-fdeb1778-9572-400b-947c-62ca86f61064
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984470049 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3984470049
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.353754265
Short name T879
Test name
Test status
Simulation time 375615616 ps
CPU time 9.79 seconds
Started Aug 07 04:46:10 PM PDT 24
Finished Aug 07 04:46:20 PM PDT 24
Peak memory 208648 kb
Host smart-f006e61c-6fcf-43d0-b4b2-adcb5a5f69ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353754265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.353754265
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.657274475
Short name T880
Test name
Test status
Simulation time 5795379811 ps
CPU time 23.07 seconds
Started Aug 07 04:46:12 PM PDT 24
Finished Aug 07 04:46:35 PM PDT 24
Peak memory 208688 kb
Host smart-720afdf8-3176-4615-88ce-12df1cd08775
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657274475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.657274475
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.14959172
Short name T947
Test name
Test status
Simulation time 264684552 ps
CPU time 2.73 seconds
Started Aug 07 04:46:17 PM PDT 24
Finished Aug 07 04:46:19 PM PDT 24
Peak memory 210948 kb
Host smart-c5e206b0-79d2-4f0d-8eb6-d6e5da784432
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14959172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.14959172
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4252921019
Short name T172
Test name
Test status
Simulation time 784330960 ps
CPU time 5.39 seconds
Started Aug 07 04:46:15 PM PDT 24
Finished Aug 07 04:46:20 PM PDT 24
Peak memory 217988 kb
Host smart-f759b439-fc3d-4c30-a334-845ce1094c9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425292
1019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4252921019
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2830378394
Short name T888
Test name
Test status
Simulation time 93648982 ps
CPU time 1.64 seconds
Started Aug 07 04:46:13 PM PDT 24
Finished Aug 07 04:46:15 PM PDT 24
Peak memory 209336 kb
Host smart-689486aa-c409-4d67-88f0-3ecd6be48da6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830378394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2830378394
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1703343960
Short name T160
Test name
Test status
Simulation time 41993270 ps
CPU time 1.44 seconds
Started Aug 07 04:46:14 PM PDT 24
Finished Aug 07 04:46:16 PM PDT 24
Peak memory 217556 kb
Host smart-0b40d4cd-24f3-49a6-8d12-e8d0b7bb0b45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703343960 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1703343960
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1922895557
Short name T950
Test name
Test status
Simulation time 59192815 ps
CPU time 0.98 seconds
Started Aug 07 04:46:20 PM PDT 24
Finished Aug 07 04:46:21 PM PDT 24
Peak memory 209300 kb
Host smart-3295001d-7ad0-43cd-8c97-4f040cbf35b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922895557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1922895557
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.4179079587
Short name T991
Test name
Test status
Simulation time 476798966 ps
CPU time 1.75 seconds
Started Aug 07 04:46:12 PM PDT 24
Finished Aug 07 04:46:14 PM PDT 24
Peak memory 217648 kb
Host smart-ae3b1e47-eebe-4768-9753-d422617c11d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179079587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.4179079587
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.126342359
Short name T987
Test name
Test status
Simulation time 40348026 ps
CPU time 2.31 seconds
Started Aug 07 04:46:15 PM PDT 24
Finished Aug 07 04:46:18 PM PDT 24
Peak memory 217572 kb
Host smart-e05e345e-d484-45b5-b12e-ff171ec55bf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126342359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.126342359
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1776795560
Short name T191
Test name
Test status
Simulation time 19702970 ps
CPU time 1.41 seconds
Started Aug 07 04:46:19 PM PDT 24
Finished Aug 07 04:46:21 PM PDT 24
Peak memory 209420 kb
Host smart-4c1a88da-9000-4967-8a9e-a3125783ba9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776795560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1776795560
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2822367381
Short name T157
Test name
Test status
Simulation time 375808313 ps
CPU time 2.18 seconds
Started Aug 07 04:46:24 PM PDT 24
Finished Aug 07 04:46:26 PM PDT 24
Peak memory 209356 kb
Host smart-757e85d5-491e-4b88-bfa7-2552795b25f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822367381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2822367381
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3671542685
Short name T884
Test name
Test status
Simulation time 15050151 ps
CPU time 1.2 seconds
Started Aug 07 04:46:23 PM PDT 24
Finished Aug 07 04:46:24 PM PDT 24
Peak memory 209960 kb
Host smart-13c73539-648b-4da4-aa1e-d74f3c6847e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671542685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3671542685
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.553362419
Short name T979
Test name
Test status
Simulation time 109775592 ps
CPU time 1.63 seconds
Started Aug 07 04:46:19 PM PDT 24
Finished Aug 07 04:46:20 PM PDT 24
Peak memory 218208 kb
Host smart-148b6b73-50bd-4fdd-bff0-93d705d66160
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553362419 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.553362419
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2257299396
Short name T988
Test name
Test status
Simulation time 12554872 ps
CPU time 0.95 seconds
Started Aug 07 04:46:23 PM PDT 24
Finished Aug 07 04:46:24 PM PDT 24
Peak memory 209420 kb
Host smart-2ccd1955-d3f4-4216-9ae7-ed90b40af51e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257299396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2257299396
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.644119245
Short name T996
Test name
Test status
Simulation time 49735936 ps
CPU time 1.97 seconds
Started Aug 07 04:46:20 PM PDT 24
Finished Aug 07 04:46:23 PM PDT 24
Peak memory 209368 kb
Host smart-35e5c474-828e-409b-b47e-3274ed432e48
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644119245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.644119245
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1591921651
Short name T961
Test name
Test status
Simulation time 1699376774 ps
CPU time 9.95 seconds
Started Aug 07 04:46:20 PM PDT 24
Finished Aug 07 04:46:30 PM PDT 24
Peak memory 209300 kb
Host smart-b416477c-fbfb-43b9-9daa-77515baef72e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591921651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1591921651
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1083292473
Short name T951
Test name
Test status
Simulation time 1800369983 ps
CPU time 37.95 seconds
Started Aug 07 04:46:20 PM PDT 24
Finished Aug 07 04:46:58 PM PDT 24
Peak memory 209364 kb
Host smart-bea642fa-671e-46f0-a77e-7bf0849965f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083292473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1083292473
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1492306646
Short name T953
Test name
Test status
Simulation time 54083904 ps
CPU time 2.17 seconds
Started Aug 07 04:46:21 PM PDT 24
Finished Aug 07 04:46:23 PM PDT 24
Peak memory 211016 kb
Host smart-9794549d-8f48-46d7-be26-880250c59ff3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492306646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1492306646
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.216329931
Short name T939
Test name
Test status
Simulation time 758431580 ps
CPU time 5.3 seconds
Started Aug 07 04:46:32 PM PDT 24
Finished Aug 07 04:46:37 PM PDT 24
Peak memory 217616 kb
Host smart-401a54fb-abaa-410f-ad3c-00840078cd57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216329
931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.216329931
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2011879661
Short name T138
Test name
Test status
Simulation time 118846322 ps
CPU time 1.48 seconds
Started Aug 07 04:46:24 PM PDT 24
Finished Aug 07 04:46:25 PM PDT 24
Peak memory 209396 kb
Host smart-af2f27ec-7016-48e1-acc6-12ce30349789
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011879661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2011879661
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3677970620
Short name T938
Test name
Test status
Simulation time 29754941 ps
CPU time 1.25 seconds
Started Aug 07 04:46:20 PM PDT 24
Finished Aug 07 04:46:21 PM PDT 24
Peak memory 209392 kb
Host smart-8984d457-1451-4c08-a216-62c38b8f0501
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677970620 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3677970620
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2660794229
Short name T952
Test name
Test status
Simulation time 34522267 ps
CPU time 1.29 seconds
Started Aug 07 04:46:20 PM PDT 24
Finished Aug 07 04:46:22 PM PDT 24
Peak memory 217644 kb
Host smart-e3d1a401-1c53-4278-bd24-7fe7b3616abd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660794229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2660794229
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3097729402
Short name T955
Test name
Test status
Simulation time 73898634 ps
CPU time 1.74 seconds
Started Aug 07 04:46:20 PM PDT 24
Finished Aug 07 04:46:22 PM PDT 24
Peak memory 217652 kb
Host smart-9c6f9a7a-33bb-430e-9718-b44851ef169c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097729402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3097729402
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1036602722
Short name T930
Test name
Test status
Simulation time 55079564 ps
CPU time 1.11 seconds
Started Aug 07 04:46:38 PM PDT 24
Finished Aug 07 04:46:39 PM PDT 24
Peak memory 219744 kb
Host smart-c9c82082-7c9b-414c-81ea-128f616bccf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036602722 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1036602722
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3575499850
Short name T115
Test name
Test status
Simulation time 44338497 ps
CPU time 1.39 seconds
Started Aug 07 04:46:36 PM PDT 24
Finished Aug 07 04:46:38 PM PDT 24
Peak memory 209380 kb
Host smart-55cc07b9-19fb-49f6-9282-a759dfff647d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575499850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3575499850
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1205248753
Short name T107
Test name
Test status
Simulation time 47160373 ps
CPU time 1.97 seconds
Started Aug 07 04:46:42 PM PDT 24
Finished Aug 07 04:46:44 PM PDT 24
Peak memory 219832 kb
Host smart-8924ac56-ea87-45e6-bc02-ae4146662788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205248753 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1205248753
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.280400500
Short name T971
Test name
Test status
Simulation time 13670192 ps
CPU time 1.08 seconds
Started Aug 07 04:46:41 PM PDT 24
Finished Aug 07 04:46:42 PM PDT 24
Peak memory 209420 kb
Host smart-80232062-baec-4d07-ae66-12cfcccfe1a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280400500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.280400500
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.120191911
Short name T894
Test name
Test status
Simulation time 22724222 ps
CPU time 1.31 seconds
Started Aug 07 04:46:40 PM PDT 24
Finished Aug 07 04:46:42 PM PDT 24
Peak memory 209380 kb
Host smart-d93802aa-4681-4f7c-a4a5-1ee77dde1d5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120191911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.120191911
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3413369514
Short name T940
Test name
Test status
Simulation time 759500953 ps
CPU time 3.31 seconds
Started Aug 07 04:46:40 PM PDT 24
Finished Aug 07 04:46:43 PM PDT 24
Peak memory 217648 kb
Host smart-8f0e234a-16db-4f1c-879c-4fa0e30dc8c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413369514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3413369514
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3356039322
Short name T973
Test name
Test status
Simulation time 33057085 ps
CPU time 1.25 seconds
Started Aug 07 04:46:39 PM PDT 24
Finished Aug 07 04:46:41 PM PDT 24
Peak memory 219848 kb
Host smart-415b55a0-1291-4444-9c8f-18dd684d03ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356039322 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3356039322
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1319959910
Short name T923
Test name
Test status
Simulation time 23247118 ps
CPU time 0.96 seconds
Started Aug 07 04:46:40 PM PDT 24
Finished Aug 07 04:46:41 PM PDT 24
Peak memory 209036 kb
Host smart-d8e44202-7739-4999-8113-adcc3760b10d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319959910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1319959910
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3180492731
Short name T932
Test name
Test status
Simulation time 46478626 ps
CPU time 1.51 seconds
Started Aug 07 04:46:40 PM PDT 24
Finished Aug 07 04:46:41 PM PDT 24
Peak memory 211520 kb
Host smart-e4ac9b8d-d223-4e99-b4a8-08bde9ad4a92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180492731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3180492731
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3852004620
Short name T130
Test name
Test status
Simulation time 458226233 ps
CPU time 3.09 seconds
Started Aug 07 04:46:39 PM PDT 24
Finished Aug 07 04:46:43 PM PDT 24
Peak memory 217676 kb
Host smart-29bedc50-cdfa-47f1-a2bb-0ced04559e7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852004620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3852004620
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1893735704
Short name T904
Test name
Test status
Simulation time 94623601 ps
CPU time 1.64 seconds
Started Aug 07 04:46:41 PM PDT 24
Finished Aug 07 04:46:42 PM PDT 24
Peak memory 217784 kb
Host smart-1e0cd30b-4c10-4d6f-9607-09ddd52b30cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893735704 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1893735704
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3421963052
Short name T978
Test name
Test status
Simulation time 16839069 ps
CPU time 1.16 seconds
Started Aug 07 04:46:40 PM PDT 24
Finished Aug 07 04:46:42 PM PDT 24
Peak memory 217636 kb
Host smart-7af495cb-d5f4-43c7-9cf1-6448a1207186
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421963052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3421963052
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3428681087
Short name T984
Test name
Test status
Simulation time 45690087 ps
CPU time 1.58 seconds
Started Aug 07 04:46:42 PM PDT 24
Finished Aug 07 04:46:43 PM PDT 24
Peak memory 211948 kb
Host smart-97005a77-4491-4f9d-8f33-a9db9718a9aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428681087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3428681087
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2688482322
Short name T924
Test name
Test status
Simulation time 43527129 ps
CPU time 1.88 seconds
Started Aug 07 04:46:45 PM PDT 24
Finished Aug 07 04:46:47 PM PDT 24
Peak memory 222004 kb
Host smart-73b25885-ebac-4d66-ba31-2992c89dc13f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688482322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2688482322
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1018585880
Short name T114
Test name
Test status
Simulation time 45980832 ps
CPU time 1.75 seconds
Started Aug 07 04:46:43 PM PDT 24
Finished Aug 07 04:46:45 PM PDT 24
Peak memory 219708 kb
Host smart-b573e050-3804-4d76-b888-d055dacce043
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018585880 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1018585880
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.541508243
Short name T200
Test name
Test status
Simulation time 13591929 ps
CPU time 1.04 seconds
Started Aug 07 04:46:45 PM PDT 24
Finished Aug 07 04:46:46 PM PDT 24
Peak memory 209352 kb
Host smart-9328b2cb-3590-43d7-ad53-0914bc9dd1bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541508243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.541508243
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2132273132
Short name T968
Test name
Test status
Simulation time 46675061 ps
CPU time 1.06 seconds
Started Aug 07 04:46:42 PM PDT 24
Finished Aug 07 04:46:43 PM PDT 24
Peak memory 209420 kb
Host smart-f734d874-0cd9-4a4d-bf82-5474f1a364b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132273132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2132273132
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2267409965
Short name T113
Test name
Test status
Simulation time 29469025 ps
CPU time 2.29 seconds
Started Aug 07 04:46:45 PM PDT 24
Finished Aug 07 04:46:47 PM PDT 24
Peak memory 218524 kb
Host smart-219b6380-633b-416b-ac3d-621b25cc9e79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267409965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2267409965
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1763063456
Short name T121
Test name
Test status
Simulation time 77022147 ps
CPU time 2.92 seconds
Started Aug 07 04:46:44 PM PDT 24
Finished Aug 07 04:46:47 PM PDT 24
Peak memory 222656 kb
Host smart-3ea256af-2f36-4c36-9818-0ac976ac3291
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763063456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1763063456
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2938442842
Short name T156
Test name
Test status
Simulation time 28744669 ps
CPU time 1.21 seconds
Started Aug 07 04:46:46 PM PDT 24
Finished Aug 07 04:46:47 PM PDT 24
Peak memory 217564 kb
Host smart-4def8edf-9375-41b1-b122-2ce006b04817
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938442842 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2938442842
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.316118910
Short name T989
Test name
Test status
Simulation time 15054957 ps
CPU time 1.01 seconds
Started Aug 07 04:46:40 PM PDT 24
Finished Aug 07 04:46:41 PM PDT 24
Peak memory 209288 kb
Host smart-9643aad7-6b3d-485b-877f-80386b25e60b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316118910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.316118910
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.154532594
Short name T985
Test name
Test status
Simulation time 43746367 ps
CPU time 1.97 seconds
Started Aug 07 04:46:40 PM PDT 24
Finished Aug 07 04:46:42 PM PDT 24
Peak memory 209404 kb
Host smart-231dc5fe-35f4-44f1-91f6-55e756e8fe1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154532594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.154532594
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1282468582
Short name T907
Test name
Test status
Simulation time 224659675 ps
CPU time 4.73 seconds
Started Aug 07 04:46:40 PM PDT 24
Finished Aug 07 04:46:45 PM PDT 24
Peak memory 217676 kb
Host smart-72e96216-94c2-4f97-89b0-5df9850d6b43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282468582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1282468582
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3581901623
Short name T959
Test name
Test status
Simulation time 27354816 ps
CPU time 1.32 seconds
Started Aug 07 04:46:39 PM PDT 24
Finished Aug 07 04:46:40 PM PDT 24
Peak memory 221676 kb
Host smart-eaad6abd-b755-4cea-a293-642594bfec52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581901623 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3581901623
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3408433971
Short name T198
Test name
Test status
Simulation time 29086505 ps
CPU time 0.93 seconds
Started Aug 07 04:46:38 PM PDT 24
Finished Aug 07 04:46:39 PM PDT 24
Peak memory 209372 kb
Host smart-9b73e597-22cc-4358-aeec-84a69db8baef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408433971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3408433971
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2864261286
Short name T202
Test name
Test status
Simulation time 14451577 ps
CPU time 1.02 seconds
Started Aug 07 04:46:41 PM PDT 24
Finished Aug 07 04:46:42 PM PDT 24
Peak memory 209316 kb
Host smart-ae9b1889-98c1-480f-9f3c-044f1d1a4f5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864261286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2864261286
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3541272588
Short name T965
Test name
Test status
Simulation time 345932905 ps
CPU time 3.88 seconds
Started Aug 07 04:46:42 PM PDT 24
Finished Aug 07 04:46:46 PM PDT 24
Peak memory 217888 kb
Host smart-708db6db-491c-4948-9bf6-b6f849036aca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541272588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3541272588
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1238406615
Short name T119
Test name
Test status
Simulation time 1348894433 ps
CPU time 3 seconds
Started Aug 07 04:46:43 PM PDT 24
Finished Aug 07 04:46:46 PM PDT 24
Peak memory 222568 kb
Host smart-7567e170-9b47-425a-b299-7e9e1b63cbf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238406615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1238406615
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3615102876
Short name T927
Test name
Test status
Simulation time 77428970 ps
CPU time 1.76 seconds
Started Aug 07 04:46:43 PM PDT 24
Finished Aug 07 04:46:44 PM PDT 24
Peak memory 217712 kb
Host smart-8a58515f-bdbb-4c40-af6e-ab23220ff41f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615102876 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3615102876
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3414129388
Short name T994
Test name
Test status
Simulation time 52694635 ps
CPU time 0.88 seconds
Started Aug 07 04:46:43 PM PDT 24
Finished Aug 07 04:46:44 PM PDT 24
Peak memory 209368 kb
Host smart-7180d0f4-d78f-4d18-bfeb-a49614ee45f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414129388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3414129388
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2385067250
Short name T906
Test name
Test status
Simulation time 86638453 ps
CPU time 1.33 seconds
Started Aug 07 04:46:42 PM PDT 24
Finished Aug 07 04:46:43 PM PDT 24
Peak memory 209356 kb
Host smart-1443d5d6-1698-42e7-ab94-eb52c6e377ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385067250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2385067250
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3344936467
Short name T925
Test name
Test status
Simulation time 282953704 ps
CPU time 2.55 seconds
Started Aug 07 04:46:42 PM PDT 24
Finished Aug 07 04:46:45 PM PDT 24
Peak memory 217776 kb
Host smart-41b5cfd4-053f-4a6c-bac7-5e690debddeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344936467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3344936467
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1544648970
Short name T135
Test name
Test status
Simulation time 268102073 ps
CPU time 2.65 seconds
Started Aug 07 04:46:40 PM PDT 24
Finished Aug 07 04:46:43 PM PDT 24
Peak memory 217576 kb
Host smart-c142e2bf-1da8-4614-a6b7-796aab149660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544648970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1544648970
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2770718289
Short name T936
Test name
Test status
Simulation time 24664610 ps
CPU time 1.21 seconds
Started Aug 07 04:46:46 PM PDT 24
Finished Aug 07 04:46:48 PM PDT 24
Peak memory 217644 kb
Host smart-43c96e2a-656a-4790-98cb-58f6652631ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770718289 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2770718289
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.207871978
Short name T199
Test name
Test status
Simulation time 52011309 ps
CPU time 0.9 seconds
Started Aug 07 04:46:40 PM PDT 24
Finished Aug 07 04:46:41 PM PDT 24
Peak memory 209416 kb
Host smart-7b593ebb-ae6e-4a11-a74b-12a3416a1dd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207871978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.207871978
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3336807005
Short name T986
Test name
Test status
Simulation time 57943762 ps
CPU time 1.1 seconds
Started Aug 07 04:46:42 PM PDT 24
Finished Aug 07 04:46:43 PM PDT 24
Peak memory 209360 kb
Host smart-9ec06d94-a2a6-4f1a-b5c4-f595c172aaba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336807005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3336807005
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1038601737
Short name T944
Test name
Test status
Simulation time 56785156 ps
CPU time 2.18 seconds
Started Aug 07 04:46:38 PM PDT 24
Finished Aug 07 04:46:41 PM PDT 24
Peak memory 217628 kb
Host smart-0cb626de-8bdd-432c-8881-f5fc1fae0001
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038601737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1038601737
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.4192206352
Short name T117
Test name
Test status
Simulation time 24746801 ps
CPU time 1.53 seconds
Started Aug 07 04:46:47 PM PDT 24
Finished Aug 07 04:46:49 PM PDT 24
Peak memory 217780 kb
Host smart-f8e50ace-5e01-4b45-ac1c-e98b2781e659
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192206352 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.4192206352
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.973205251
Short name T934
Test name
Test status
Simulation time 72946168 ps
CPU time 0.95 seconds
Started Aug 07 04:46:52 PM PDT 24
Finished Aug 07 04:46:53 PM PDT 24
Peak memory 209360 kb
Host smart-15164818-9562-4f58-a547-78f32b17dd1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973205251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.973205251
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1794093327
Short name T896
Test name
Test status
Simulation time 25890267 ps
CPU time 1.38 seconds
Started Aug 07 04:46:48 PM PDT 24
Finished Aug 07 04:46:50 PM PDT 24
Peak memory 209492 kb
Host smart-a5694829-68fb-40cf-be41-ecf48b698185
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794093327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1794093327
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2907452199
Short name T919
Test name
Test status
Simulation time 153911377 ps
CPU time 5.64 seconds
Started Aug 07 04:46:47 PM PDT 24
Finished Aug 07 04:46:53 PM PDT 24
Peak memory 217576 kb
Host smart-f92fff74-aae8-491f-bfec-9f207f008f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907452199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2907452199
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2249070781
Short name T215
Test name
Test status
Simulation time 62512301 ps
CPU time 2.47 seconds
Started Aug 07 04:46:45 PM PDT 24
Finished Aug 07 04:46:48 PM PDT 24
Peak memory 217680 kb
Host smart-b8c4a293-2fdf-43a3-b5f8-23d313a6b2c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249070781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2249070781
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3156700544
Short name T967
Test name
Test status
Simulation time 22044144 ps
CPU time 1.01 seconds
Started Aug 07 04:46:20 PM PDT 24
Finished Aug 07 04:46:22 PM PDT 24
Peak memory 209356 kb
Host smart-4e6cac79-d444-42cf-8a8b-0b03751a4c79
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156700544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3156700544
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1605048103
Short name T878
Test name
Test status
Simulation time 20233580 ps
CPU time 1.22 seconds
Started Aug 07 04:46:18 PM PDT 24
Finished Aug 07 04:46:20 PM PDT 24
Peak memory 209320 kb
Host smart-c7a2c193-2d58-4ee1-a68c-89a05ed40cf3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605048103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1605048103
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.922440278
Short name T935
Test name
Test status
Simulation time 62188146 ps
CPU time 0.98 seconds
Started Aug 07 04:46:22 PM PDT 24
Finished Aug 07 04:46:23 PM PDT 24
Peak memory 209960 kb
Host smart-90a4131f-77ac-4556-8e8d-a6999b13ac27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922440278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.922440278
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.710098630
Short name T886
Test name
Test status
Simulation time 42502027 ps
CPU time 1.12 seconds
Started Aug 07 04:46:24 PM PDT 24
Finished Aug 07 04:46:25 PM PDT 24
Peak memory 217752 kb
Host smart-e796e534-66fa-44cb-a086-b7d796d212de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710098630 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.710098630
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2224019100
Short name T201
Test name
Test status
Simulation time 31448212 ps
CPU time 0.99 seconds
Started Aug 07 04:46:19 PM PDT 24
Finished Aug 07 04:46:20 PM PDT 24
Peak memory 209356 kb
Host smart-46fae44e-f4b8-4573-b8ea-d0b28351d327
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224019100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2224019100
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2535761375
Short name T943
Test name
Test status
Simulation time 32329253 ps
CPU time 0.99 seconds
Started Aug 07 04:46:18 PM PDT 24
Finished Aug 07 04:46:19 PM PDT 24
Peak memory 208000 kb
Host smart-3ebbba2a-355c-4b1a-a4ba-09b2ec0e679e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535761375 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2535761375
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3927208542
Short name T964
Test name
Test status
Simulation time 8082224814 ps
CPU time 12.33 seconds
Started Aug 07 04:46:19 PM PDT 24
Finished Aug 07 04:46:32 PM PDT 24
Peak memory 209376 kb
Host smart-c3d8e81a-229f-4c1a-b42c-ed270097761a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927208542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3927208542
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.657459789
Short name T895
Test name
Test status
Simulation time 697723662 ps
CPU time 8.27 seconds
Started Aug 07 04:46:18 PM PDT 24
Finished Aug 07 04:46:26 PM PDT 24
Peak memory 208584 kb
Host smart-a2fd405a-fe9c-4f0f-aaa8-aaad54378d88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657459789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.657459789
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.722249537
Short name T897
Test name
Test status
Simulation time 1070138649 ps
CPU time 2.88 seconds
Started Aug 07 04:46:23 PM PDT 24
Finished Aug 07 04:46:26 PM PDT 24
Peak memory 211032 kb
Host smart-08fd3279-a0f6-4d9f-b6dd-10b7d9e789a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722249537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.722249537
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2081980246
Short name T992
Test name
Test status
Simulation time 103462328 ps
CPU time 3.79 seconds
Started Aug 07 04:46:20 PM PDT 24
Finished Aug 07 04:46:24 PM PDT 24
Peak memory 218628 kb
Host smart-e06b3d40-7e8f-470e-92ea-9a4cdaa1e69e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208198
0246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2081980246
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3120965810
Short name T139
Test name
Test status
Simulation time 237032285 ps
CPU time 1.9 seconds
Started Aug 07 04:46:20 PM PDT 24
Finished Aug 07 04:46:22 PM PDT 24
Peak memory 209248 kb
Host smart-7e256118-4a73-44dd-9462-e7289f534a8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120965810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3120965810
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2389954264
Short name T158
Test name
Test status
Simulation time 180840737 ps
CPU time 1.48 seconds
Started Aug 07 04:46:18 PM PDT 24
Finished Aug 07 04:46:20 PM PDT 24
Peak memory 217704 kb
Host smart-ef4fcc11-1be2-47d2-a069-f33fb4ab41fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389954264 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2389954264
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2010640851
Short name T922
Test name
Test status
Simulation time 89527365 ps
CPU time 1.44 seconds
Started Aug 07 04:46:23 PM PDT 24
Finished Aug 07 04:46:25 PM PDT 24
Peak memory 209432 kb
Host smart-6463d31c-dca5-49a9-812b-641b1529d45a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010640851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2010640851
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2204819929
Short name T126
Test name
Test status
Simulation time 131308810 ps
CPU time 1.89 seconds
Started Aug 07 04:46:21 PM PDT 24
Finished Aug 07 04:46:23 PM PDT 24
Peak memory 217548 kb
Host smart-a2b7002e-695b-4454-b543-54b093666dac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204819929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2204819929
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1248398210
Short name T122
Test name
Test status
Simulation time 457312562 ps
CPU time 3.2 seconds
Started Aug 07 04:46:23 PM PDT 24
Finished Aug 07 04:46:26 PM PDT 24
Peak memory 222176 kb
Host smart-cf4983b0-8489-4f66-adfa-dba7d0c6a1ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248398210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1248398210
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.387847991
Short name T189
Test name
Test status
Simulation time 26559279 ps
CPU time 0.98 seconds
Started Aug 07 04:46:28 PM PDT 24
Finished Aug 07 04:46:29 PM PDT 24
Peak memory 209428 kb
Host smart-e1a24868-758b-4554-a78f-25578d354cde
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387847991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.387847991
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3741668172
Short name T885
Test name
Test status
Simulation time 56913015 ps
CPU time 1.82 seconds
Started Aug 07 04:46:30 PM PDT 24
Finished Aug 07 04:46:32 PM PDT 24
Peak memory 208204 kb
Host smart-e26b5ff5-b5aa-4c30-8754-448abac6d0dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741668172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3741668172
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.324985745
Short name T898
Test name
Test status
Simulation time 19272555 ps
CPU time 1.05 seconds
Started Aug 07 04:46:28 PM PDT 24
Finished Aug 07 04:46:29 PM PDT 24
Peak memory 218276 kb
Host smart-692e2a15-82b6-49eb-98a8-925fd79ec056
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324985745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.324985745
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.616659012
Short name T892
Test name
Test status
Simulation time 83305413 ps
CPU time 1.29 seconds
Started Aug 07 04:46:27 PM PDT 24
Finished Aug 07 04:46:28 PM PDT 24
Peak memory 220040 kb
Host smart-89789144-bd37-42bb-a21d-ab3985489878
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616659012 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.616659012
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1391066815
Short name T893
Test name
Test status
Simulation time 27974364 ps
CPU time 0.84 seconds
Started Aug 07 04:46:25 PM PDT 24
Finished Aug 07 04:46:26 PM PDT 24
Peak memory 208828 kb
Host smart-a01582e0-9cc5-4b53-92fd-18823894019c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391066815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1391066815
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2290565617
Short name T966
Test name
Test status
Simulation time 66995795 ps
CPU time 1.95 seconds
Started Aug 07 04:46:25 PM PDT 24
Finished Aug 07 04:46:27 PM PDT 24
Peak memory 209352 kb
Host smart-ae53e0f3-d550-4e9a-9fa0-18fea0381a21
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290565617 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2290565617
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2699569060
Short name T913
Test name
Test status
Simulation time 193009522 ps
CPU time 5.5 seconds
Started Aug 07 04:46:19 PM PDT 24
Finished Aug 07 04:46:25 PM PDT 24
Peak memory 209324 kb
Host smart-662ad750-2a14-4d69-9c00-48f356cdae2f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699569060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2699569060
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.741127156
Short name T963
Test name
Test status
Simulation time 4569862413 ps
CPU time 26.79 seconds
Started Aug 07 04:46:19 PM PDT 24
Finished Aug 07 04:46:46 PM PDT 24
Peak memory 209412 kb
Host smart-41e12a4c-d103-4c3e-91b8-3d284fbb8425
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741127156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.741127156
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3156018911
Short name T887
Test name
Test status
Simulation time 494560919 ps
CPU time 3.92 seconds
Started Aug 07 04:46:22 PM PDT 24
Finished Aug 07 04:46:26 PM PDT 24
Peak memory 211268 kb
Host smart-4c5cbd35-ebea-4897-a407-8cac29bda850
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156018911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3156018911
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3138741959
Short name T112
Test name
Test status
Simulation time 234251128 ps
CPU time 1.56 seconds
Started Aug 07 04:46:28 PM PDT 24
Finished Aug 07 04:46:30 PM PDT 24
Peak memory 219836 kb
Host smart-d78e3f68-3cb2-495f-9cd5-d814e6291feb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313874
1959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3138741959
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2523143806
Short name T920
Test name
Test status
Simulation time 126030288 ps
CPU time 1.04 seconds
Started Aug 07 04:46:18 PM PDT 24
Finished Aug 07 04:46:19 PM PDT 24
Peak memory 209344 kb
Host smart-4fa7e599-d258-46ac-ac97-254a09c6bc06
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523143806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2523143806
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2524333230
Short name T205
Test name
Test status
Simulation time 21874484 ps
CPU time 1.35 seconds
Started Aug 07 04:46:28 PM PDT 24
Finished Aug 07 04:46:29 PM PDT 24
Peak memory 209392 kb
Host smart-c9191e2a-fd3f-472e-b2b4-38e9cec9e63f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524333230 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2524333230
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.162538084
Short name T912
Test name
Test status
Simulation time 23044828 ps
CPU time 1.56 seconds
Started Aug 07 04:46:27 PM PDT 24
Finished Aug 07 04:46:28 PM PDT 24
Peak memory 209332 kb
Host smart-25065107-6334-444f-a821-d4014a741b0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162538084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.162538084
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1150143153
Short name T998
Test name
Test status
Simulation time 521549641 ps
CPU time 2.16 seconds
Started Aug 07 04:46:25 PM PDT 24
Finished Aug 07 04:46:27 PM PDT 24
Peak memory 217604 kb
Host smart-d68c353a-406c-49c0-9332-a2702bc92480
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150143153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1150143153
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3459158611
Short name T196
Test name
Test status
Simulation time 48731899 ps
CPU time 1.03 seconds
Started Aug 07 04:46:30 PM PDT 24
Finished Aug 07 04:46:31 PM PDT 24
Peak memory 209468 kb
Host smart-14b97574-43e9-4f8e-a6f2-7751e09b86cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459158611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.3459158611
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.970112666
Short name T918
Test name
Test status
Simulation time 184432934 ps
CPU time 1.38 seconds
Started Aug 07 04:46:26 PM PDT 24
Finished Aug 07 04:46:28 PM PDT 24
Peak memory 208612 kb
Host smart-027c4d91-c823-408a-aad0-9e88fd160053
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970112666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.970112666
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4084012297
Short name T194
Test name
Test status
Simulation time 58812702 ps
CPU time 0.91 seconds
Started Aug 07 04:46:31 PM PDT 24
Finished Aug 07 04:46:32 PM PDT 24
Peak memory 209560 kb
Host smart-763dbf89-d8d7-4ac1-bedf-a2dda8c44af8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084012297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.4084012297
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3144944087
Short name T948
Test name
Test status
Simulation time 20585473 ps
CPU time 1.38 seconds
Started Aug 07 04:46:29 PM PDT 24
Finished Aug 07 04:46:30 PM PDT 24
Peak memory 217656 kb
Host smart-b778949b-6401-4bdb-9ae7-85bfe0c08788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144944087 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3144944087
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3471234135
Short name T911
Test name
Test status
Simulation time 59583336 ps
CPU time 0.92 seconds
Started Aug 07 04:46:27 PM PDT 24
Finished Aug 07 04:46:28 PM PDT 24
Peak memory 209360 kb
Host smart-ad2f7d6e-4157-4a3e-9e60-20c1721d106c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471234135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3471234135
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2874913940
Short name T926
Test name
Test status
Simulation time 167495885 ps
CPU time 0.9 seconds
Started Aug 07 04:46:27 PM PDT 24
Finished Aug 07 04:46:28 PM PDT 24
Peak memory 209300 kb
Host smart-71aab138-999f-4c63-8be0-3df584ef8e82
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874913940 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2874913940
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3119388562
Short name T958
Test name
Test status
Simulation time 826167440 ps
CPU time 3.19 seconds
Started Aug 07 04:46:25 PM PDT 24
Finished Aug 07 04:46:28 PM PDT 24
Peak memory 208656 kb
Host smart-304d054c-284e-4179-8a41-fc7fc160a96f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119388562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3119388562
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2457285455
Short name T974
Test name
Test status
Simulation time 3988078848 ps
CPU time 6.64 seconds
Started Aug 07 04:46:31 PM PDT 24
Finished Aug 07 04:46:38 PM PDT 24
Peak memory 209420 kb
Host smart-ea4c2491-9be3-4eb1-946b-32648f4d6a3d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457285455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2457285455
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1663540978
Short name T945
Test name
Test status
Simulation time 248743851 ps
CPU time 2.4 seconds
Started Aug 07 04:46:30 PM PDT 24
Finished Aug 07 04:46:32 PM PDT 24
Peak memory 210992 kb
Host smart-ad919fcb-a8f9-45f6-87fc-fb5ef3a32a46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663540978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1663540978
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3541681550
Short name T956
Test name
Test status
Simulation time 113984164 ps
CPU time 1.76 seconds
Started Aug 07 04:46:32 PM PDT 24
Finished Aug 07 04:46:33 PM PDT 24
Peak memory 209400 kb
Host smart-543d2755-6218-4b02-b9d0-eaa69156ab9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541681550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3541681550
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2899137301
Short name T891
Test name
Test status
Simulation time 27009343 ps
CPU time 1.43 seconds
Started Aug 07 04:46:28 PM PDT 24
Finished Aug 07 04:46:30 PM PDT 24
Peak memory 209364 kb
Host smart-0a4394ce-9c48-4b94-934e-c0769f03cd16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899137301 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2899137301
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3143476907
Short name T969
Test name
Test status
Simulation time 90479841 ps
CPU time 1.96 seconds
Started Aug 07 04:46:31 PM PDT 24
Finished Aug 07 04:46:33 PM PDT 24
Peak memory 209364 kb
Host smart-8dffa5eb-9a50-44c5-8ccb-8450a9251602
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143476907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3143476907
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.876279782
Short name T982
Test name
Test status
Simulation time 326422811 ps
CPU time 3.21 seconds
Started Aug 07 04:46:30 PM PDT 24
Finished Aug 07 04:46:33 PM PDT 24
Peak memory 217728 kb
Host smart-5e81dfae-f2df-4e79-9e8d-ba870bc203ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876279782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.876279782
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1972388406
Short name T977
Test name
Test status
Simulation time 71601284 ps
CPU time 1.35 seconds
Started Aug 07 04:46:31 PM PDT 24
Finished Aug 07 04:46:32 PM PDT 24
Peak memory 217684 kb
Host smart-4210a996-4cb8-44fd-a504-b3a240345eed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972388406 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1972388406
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3698885780
Short name T190
Test name
Test status
Simulation time 98326007 ps
CPU time 1.03 seconds
Started Aug 07 04:46:27 PM PDT 24
Finished Aug 07 04:46:28 PM PDT 24
Peak memory 209232 kb
Host smart-6d275f3b-5791-4b61-ba3a-d5390ed22989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698885780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3698885780
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2042145491
Short name T983
Test name
Test status
Simulation time 129152558 ps
CPU time 0.88 seconds
Started Aug 07 04:46:26 PM PDT 24
Finished Aug 07 04:46:27 PM PDT 24
Peak memory 209308 kb
Host smart-1d707eb3-39f3-49f7-aa55-3b4109e36759
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042145491 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2042145491
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.88013938
Short name T140
Test name
Test status
Simulation time 706775229 ps
CPU time 12.04 seconds
Started Aug 07 04:46:27 PM PDT 24
Finished Aug 07 04:46:39 PM PDT 24
Peak memory 209304 kb
Host smart-7f405f9b-48da-49b2-9745-e21d31d9e4ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88013938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.lc_ctrl_jtag_csr_aliasing.88013938
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3037068855
Short name T207
Test name
Test status
Simulation time 7911754702 ps
CPU time 4.77 seconds
Started Aug 07 04:46:28 PM PDT 24
Finished Aug 07 04:46:33 PM PDT 24
Peak memory 209456 kb
Host smart-8d6f8026-7d03-43cf-a1ef-a2df90cd8c28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037068855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3037068855
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3216772489
Short name T975
Test name
Test status
Simulation time 239121284 ps
CPU time 1.32 seconds
Started Aug 07 04:46:30 PM PDT 24
Finished Aug 07 04:46:31 PM PDT 24
Peak memory 210816 kb
Host smart-0e998385-ce27-4a15-b7da-610c3030d122
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216772489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3216772489
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.156919380
Short name T995
Test name
Test status
Simulation time 793824264 ps
CPU time 5.46 seconds
Started Aug 07 04:46:28 PM PDT 24
Finished Aug 07 04:46:34 PM PDT 24
Peak memory 218924 kb
Host smart-4b602f46-f2ad-4da3-a31e-a17f1fa71976
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156919
380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.156919380
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3085050152
Short name T903
Test name
Test status
Simulation time 138734596 ps
CPU time 1.49 seconds
Started Aug 07 04:46:32 PM PDT 24
Finished Aug 07 04:46:33 PM PDT 24
Peak memory 209328 kb
Host smart-edd361ca-2e74-43db-b5fa-7b70557ee26c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085050152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3085050152
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3142073920
Short name T915
Test name
Test status
Simulation time 84585126 ps
CPU time 1.07 seconds
Started Aug 07 04:46:27 PM PDT 24
Finished Aug 07 04:46:28 PM PDT 24
Peak memory 209364 kb
Host smart-012b5743-d020-4777-aa25-e64573e04208
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142073920 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3142073920
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.645821911
Short name T204
Test name
Test status
Simulation time 19519390 ps
CPU time 1.17 seconds
Started Aug 07 04:46:32 PM PDT 24
Finished Aug 07 04:46:33 PM PDT 24
Peak memory 209500 kb
Host smart-013fdf68-90c8-4b27-930a-3133fdb7f90d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645821911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.645821911
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.821605405
Short name T916
Test name
Test status
Simulation time 143910087 ps
CPU time 2.37 seconds
Started Aug 07 04:46:25 PM PDT 24
Finished Aug 07 04:46:28 PM PDT 24
Peak memory 218704 kb
Host smart-87bb54e0-9e62-4e9a-af9a-feafecc453ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821605405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.821605405
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1540196352
Short name T164
Test name
Test status
Simulation time 33607131 ps
CPU time 1.46 seconds
Started Aug 07 04:46:36 PM PDT 24
Finished Aug 07 04:46:37 PM PDT 24
Peak memory 218740 kb
Host smart-ea7c6c11-ade9-4c9c-9636-28a10dda26a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540196352 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1540196352
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3009451084
Short name T161
Test name
Test status
Simulation time 17181654 ps
CPU time 1.09 seconds
Started Aug 07 04:46:34 PM PDT 24
Finished Aug 07 04:46:35 PM PDT 24
Peak memory 209364 kb
Host smart-b2fc4625-4961-41cd-844e-6026d1bc1052
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009451084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3009451084
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1869298843
Short name T980
Test name
Test status
Simulation time 117604996 ps
CPU time 1.6 seconds
Started Aug 07 04:46:38 PM PDT 24
Finished Aug 07 04:46:39 PM PDT 24
Peak memory 209448 kb
Host smart-035b9168-c3cc-4709-baab-d87384d34f05
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869298843 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1869298843
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.647123644
Short name T933
Test name
Test status
Simulation time 1478002481 ps
CPU time 14.68 seconds
Started Aug 07 04:46:30 PM PDT 24
Finished Aug 07 04:46:45 PM PDT 24
Peak memory 209228 kb
Host smart-e3973e07-75be-429f-9682-344200273c73
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647123644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.647123644
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3017573794
Short name T990
Test name
Test status
Simulation time 6579931823 ps
CPU time 22.84 seconds
Started Aug 07 04:46:27 PM PDT 24
Finished Aug 07 04:46:50 PM PDT 24
Peak memory 208724 kb
Host smart-d459f5f9-3917-420f-92fb-4f6199203825
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017573794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3017573794
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1907686734
Short name T877
Test name
Test status
Simulation time 49546138 ps
CPU time 1.97 seconds
Started Aug 07 04:46:29 PM PDT 24
Finished Aug 07 04:46:31 PM PDT 24
Peak memory 210884 kb
Host smart-cb8f61d8-a831-436e-8d4e-f954c865d8e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907686734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1907686734
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2588550282
Short name T116
Test name
Test status
Simulation time 269145856 ps
CPU time 6.84 seconds
Started Aug 07 04:46:34 PM PDT 24
Finished Aug 07 04:46:41 PM PDT 24
Peak memory 218700 kb
Host smart-9d92f21f-e93e-4a77-9ab7-73d4e2ed7de0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258855
0282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2588550282
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3207877688
Short name T902
Test name
Test status
Simulation time 328704969 ps
CPU time 1.61 seconds
Started Aug 07 04:46:27 PM PDT 24
Finished Aug 07 04:46:29 PM PDT 24
Peak memory 209288 kb
Host smart-c4478917-c2ba-42ca-ad48-42deacdf2b09
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207877688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3207877688
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2224163354
Short name T901
Test name
Test status
Simulation time 268605536 ps
CPU time 1.42 seconds
Started Aug 07 04:46:33 PM PDT 24
Finished Aug 07 04:46:35 PM PDT 24
Peak memory 209420 kb
Host smart-0006db1e-d2d5-4e12-99a2-75f380459185
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224163354 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2224163354
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1301925731
Short name T159
Test name
Test status
Simulation time 182517540 ps
CPU time 1.45 seconds
Started Aug 07 04:46:33 PM PDT 24
Finished Aug 07 04:46:35 PM PDT 24
Peak memory 209356 kb
Host smart-8a10102b-2b8d-40f5-baef-3e97d2b4e4cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301925731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1301925731
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2320100014
Short name T999
Test name
Test status
Simulation time 124815942 ps
CPU time 1.53 seconds
Started Aug 07 04:46:37 PM PDT 24
Finished Aug 07 04:46:38 PM PDT 24
Peak memory 218580 kb
Host smart-095f94bf-103b-4e7f-b6c9-5739cb890214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320100014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2320100014
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1342546986
Short name T137
Test name
Test status
Simulation time 190691928 ps
CPU time 3.99 seconds
Started Aug 07 04:46:34 PM PDT 24
Finished Aug 07 04:46:38 PM PDT 24
Peak memory 213564 kb
Host smart-ff234b1b-9599-4c91-8bec-ad9364f3862a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342546986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1342546986
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1782582823
Short name T120
Test name
Test status
Simulation time 54316063 ps
CPU time 0.96 seconds
Started Aug 07 04:46:34 PM PDT 24
Finished Aug 07 04:46:36 PM PDT 24
Peak memory 217724 kb
Host smart-093146d9-f2f1-4027-b549-0ee9db2c04c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782582823 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1782582823
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.170836055
Short name T192
Test name
Test status
Simulation time 13936739 ps
CPU time 0.86 seconds
Started Aug 07 04:46:36 PM PDT 24
Finished Aug 07 04:46:37 PM PDT 24
Peak memory 209224 kb
Host smart-6f219a55-c5dc-453c-b0f0-6a7e3208fbe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170836055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.170836055
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1244666109
Short name T917
Test name
Test status
Simulation time 25010997 ps
CPU time 1.34 seconds
Started Aug 07 04:46:38 PM PDT 24
Finished Aug 07 04:46:40 PM PDT 24
Peak memory 209484 kb
Host smart-266fe645-2ba9-4377-9a2e-21f173b901bf
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244666109 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1244666109
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1656291221
Short name T908
Test name
Test status
Simulation time 4562034429 ps
CPU time 6.32 seconds
Started Aug 07 04:46:34 PM PDT 24
Finished Aug 07 04:46:41 PM PDT 24
Peak memory 208264 kb
Host smart-08708dae-aa39-4d6a-a6a8-dc599de5bc45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656291221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1656291221
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1280866800
Short name T882
Test name
Test status
Simulation time 2745608531 ps
CPU time 6.84 seconds
Started Aug 07 04:46:37 PM PDT 24
Finished Aug 07 04:46:44 PM PDT 24
Peak memory 209408 kb
Host smart-93c9664c-065a-4a0b-85d4-51fbc9c01c06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280866800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1280866800
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2817913734
Short name T976
Test name
Test status
Simulation time 290133111 ps
CPU time 4.14 seconds
Started Aug 07 04:46:37 PM PDT 24
Finished Aug 07 04:46:42 PM PDT 24
Peak memory 211216 kb
Host smart-923e76a6-bb39-4798-9712-f8b721467a34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817913734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2817913734
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.808135745
Short name T905
Test name
Test status
Simulation time 85897329 ps
CPU time 1.96 seconds
Started Aug 07 04:46:33 PM PDT 24
Finished Aug 07 04:46:35 PM PDT 24
Peak memory 222060 kb
Host smart-0b22dd28-06f3-4735-8756-36f976d6f234
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808135
745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.808135745
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3800484867
Short name T910
Test name
Test status
Simulation time 126581922 ps
CPU time 2.24 seconds
Started Aug 07 04:46:39 PM PDT 24
Finished Aug 07 04:46:41 PM PDT 24
Peak memory 209348 kb
Host smart-d423bc21-0ed2-4c5f-bbf6-b1f9458f82c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800484867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3800484867
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1939940790
Short name T889
Test name
Test status
Simulation time 26895894 ps
CPU time 1.41 seconds
Started Aug 07 04:46:33 PM PDT 24
Finished Aug 07 04:46:34 PM PDT 24
Peak memory 209400 kb
Host smart-d493913c-a5dc-45db-865f-952c09d904af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939940790 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1939940790
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2143642908
Short name T993
Test name
Test status
Simulation time 73831766 ps
CPU time 1.4 seconds
Started Aug 07 04:46:34 PM PDT 24
Finished Aug 07 04:46:35 PM PDT 24
Peak memory 209500 kb
Host smart-f05d13a7-1cf3-47e8-beaa-8f9f0bdb1a5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143642908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2143642908
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3347838673
Short name T954
Test name
Test status
Simulation time 68361179 ps
CPU time 2.82 seconds
Started Aug 07 04:46:33 PM PDT 24
Finished Aug 07 04:46:36 PM PDT 24
Peak memory 217632 kb
Host smart-3008ec8d-b62b-4fd6-814e-4f06653b914f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347838673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3347838673
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.277348695
Short name T136
Test name
Test status
Simulation time 65505669 ps
CPU time 2.1 seconds
Started Aug 07 04:46:34 PM PDT 24
Finished Aug 07 04:46:36 PM PDT 24
Peak memory 221808 kb
Host smart-dda4a87c-6321-4e08-98d7-366a2ffcae65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277348695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.277348695
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1559967364
Short name T890
Test name
Test status
Simulation time 36485664 ps
CPU time 1.35 seconds
Started Aug 07 04:46:56 PM PDT 24
Finished Aug 07 04:46:57 PM PDT 24
Peak memory 221932 kb
Host smart-d77c5ba1-a729-4d34-a7da-4d47dd06eb19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559967364 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1559967364
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.989391235
Short name T193
Test name
Test status
Simulation time 12129796 ps
CPU time 1.07 seconds
Started Aug 07 04:46:34 PM PDT 24
Finished Aug 07 04:46:35 PM PDT 24
Peak memory 209260 kb
Host smart-485e85b0-2658-4546-b58c-e5b749886670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989391235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.989391235
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4043023907
Short name T949
Test name
Test status
Simulation time 50080720 ps
CPU time 1.79 seconds
Started Aug 07 04:46:38 PM PDT 24
Finished Aug 07 04:46:40 PM PDT 24
Peak memory 209348 kb
Host smart-2616c750-c997-4b6c-9b81-4aea9957348f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043023907 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.4043023907
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1162949934
Short name T997
Test name
Test status
Simulation time 1107459992 ps
CPU time 13.36 seconds
Started Aug 07 04:46:35 PM PDT 24
Finished Aug 07 04:46:49 PM PDT 24
Peak memory 209256 kb
Host smart-5b137ea4-e419-41fd-8021-2e40630fc0e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162949934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1162949934
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3598269387
Short name T929
Test name
Test status
Simulation time 355403355 ps
CPU time 9.65 seconds
Started Aug 07 04:46:38 PM PDT 24
Finished Aug 07 04:46:48 PM PDT 24
Peak memory 208684 kb
Host smart-8619e67d-3eed-49ed-b3d1-c215d3c4d844
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598269387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3598269387
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3619646799
Short name T946
Test name
Test status
Simulation time 160368720 ps
CPU time 2.72 seconds
Started Aug 07 04:46:33 PM PDT 24
Finished Aug 07 04:46:36 PM PDT 24
Peak memory 211108 kb
Host smart-4af277a6-8f18-4367-a903-1007128fdf37
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619646799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3619646799
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2237752573
Short name T981
Test name
Test status
Simulation time 91468932 ps
CPU time 3.8 seconds
Started Aug 07 04:46:39 PM PDT 24
Finished Aug 07 04:46:42 PM PDT 24
Peak memory 218972 kb
Host smart-6b422c15-c009-49e7-9ce2-0376d2f4bc49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223775
2573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2237752573
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.65661386
Short name T921
Test name
Test status
Simulation time 578746859 ps
CPU time 1.93 seconds
Started Aug 07 04:46:35 PM PDT 24
Finished Aug 07 04:46:37 PM PDT 24
Peak memory 209364 kb
Host smart-545e5924-1aaf-4569-b18b-daf690a6a717
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65661386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 8.lc_ctrl_jtag_csr_rw.65661386
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3614687485
Short name T914
Test name
Test status
Simulation time 57484494 ps
CPU time 1.17 seconds
Started Aug 07 04:46:33 PM PDT 24
Finished Aug 07 04:46:34 PM PDT 24
Peak memory 209412 kb
Host smart-a09611b7-67b0-4fe1-9ce4-9ee75e34ab21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614687485 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3614687485
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4125052652
Short name T972
Test name
Test status
Simulation time 37229497 ps
CPU time 1.3 seconds
Started Aug 07 04:46:34 PM PDT 24
Finished Aug 07 04:46:35 PM PDT 24
Peak memory 211596 kb
Host smart-b05eacbf-bf6e-4944-9138-336ba25e93a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125052652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.4125052652
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3481039343
Short name T129
Test name
Test status
Simulation time 457457220 ps
CPU time 3.96 seconds
Started Aug 07 04:46:37 PM PDT 24
Finished Aug 07 04:46:41 PM PDT 24
Peak memory 217560 kb
Host smart-336d025f-02b2-496a-8746-d78018a5db75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481039343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3481039343
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3513769200
Short name T942
Test name
Test status
Simulation time 18952999 ps
CPU time 1.15 seconds
Started Aug 07 04:46:33 PM PDT 24
Finished Aug 07 04:46:34 PM PDT 24
Peak memory 217728 kb
Host smart-e2500e39-44b3-4778-890f-39afefb71d49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513769200 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3513769200
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.718188405
Short name T931
Test name
Test status
Simulation time 11577875 ps
CPU time 1.06 seconds
Started Aug 07 04:46:36 PM PDT 24
Finished Aug 07 04:46:37 PM PDT 24
Peak memory 209040 kb
Host smart-506fd963-0ee7-435d-aa26-907ae14d670e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718188405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.718188405
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.4224188656
Short name T883
Test name
Test status
Simulation time 34797498 ps
CPU time 1.25 seconds
Started Aug 07 04:46:34 PM PDT 24
Finished Aug 07 04:46:35 PM PDT 24
Peak memory 209328 kb
Host smart-09f67fba-d42b-4f03-9e2e-c38d89b3e0ff
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224188656 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.4224188656
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2539862994
Short name T962
Test name
Test status
Simulation time 1226484092 ps
CPU time 5.93 seconds
Started Aug 07 04:46:34 PM PDT 24
Finished Aug 07 04:46:40 PM PDT 24
Peak memory 209392 kb
Host smart-b9bcafa8-e626-424d-a325-d5a52230bc57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539862994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2539862994
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2620249317
Short name T957
Test name
Test status
Simulation time 1110026625 ps
CPU time 26.16 seconds
Started Aug 07 04:46:39 PM PDT 24
Finished Aug 07 04:47:05 PM PDT 24
Peak memory 209396 kb
Host smart-e928bb99-ef99-44f8-9ba1-00446321aeaf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620249317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2620249317
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.111687764
Short name T941
Test name
Test status
Simulation time 585829923 ps
CPU time 1.71 seconds
Started Aug 07 04:46:33 PM PDT 24
Finished Aug 07 04:46:35 PM PDT 24
Peak memory 211064 kb
Host smart-cd4a154a-9e4f-44b4-bea1-e8632782a071
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111687764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.111687764
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4118206062
Short name T131
Test name
Test status
Simulation time 151558215 ps
CPU time 4.47 seconds
Started Aug 07 04:46:34 PM PDT 24
Finished Aug 07 04:46:38 PM PDT 24
Peak memory 218144 kb
Host smart-2a0df305-1896-4097-aef0-ca565d7f9687
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411820
6062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4118206062
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.414719039
Short name T899
Test name
Test status
Simulation time 34759258 ps
CPU time 1.55 seconds
Started Aug 07 04:46:38 PM PDT 24
Finished Aug 07 04:46:40 PM PDT 24
Peak memory 209428 kb
Host smart-e49819bf-da05-4347-8dfa-d54e4f33b08f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414719039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.414719039
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1334584366
Short name T928
Test name
Test status
Simulation time 139152131 ps
CPU time 1.85 seconds
Started Aug 07 04:46:33 PM PDT 24
Finished Aug 07 04:46:35 PM PDT 24
Peak memory 217672 kb
Host smart-19e0ae43-67a0-4cb7-aa55-f9eed8a5bdab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334584366 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1334584366
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2168083092
Short name T203
Test name
Test status
Simulation time 26375692 ps
CPU time 1.45 seconds
Started Aug 07 04:46:34 PM PDT 24
Finished Aug 07 04:46:35 PM PDT 24
Peak memory 209412 kb
Host smart-5a14b685-ed4f-4435-b101-202f707df4a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168083092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2168083092
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3419397236
Short name T970
Test name
Test status
Simulation time 170359770 ps
CPU time 2.88 seconds
Started Aug 07 04:46:33 PM PDT 24
Finished Aug 07 04:46:36 PM PDT 24
Peak memory 218588 kb
Host smart-e16fd2b2-79a7-4e16-a3b5-22aba4838a77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419397236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3419397236
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.384619609
Short name T128
Test name
Test status
Simulation time 143921786 ps
CPU time 3.51 seconds
Started Aug 07 04:46:38 PM PDT 24
Finished Aug 07 04:46:42 PM PDT 24
Peak memory 217612 kb
Host smart-78a1d2bc-251f-4976-b12e-d26ba9c8e796
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384619609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.384619609
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1996309047
Short name T367
Test name
Test status
Simulation time 39644030 ps
CPU time 0.85 seconds
Started Aug 07 06:13:16 PM PDT 24
Finished Aug 07 06:13:17 PM PDT 24
Peak memory 208728 kb
Host smart-eaf54799-ef1f-4ac3-ae4f-090280a1fd61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996309047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1996309047
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1933021215
Short name T711
Test name
Test status
Simulation time 73708144 ps
CPU time 0.83 seconds
Started Aug 07 06:13:20 PM PDT 24
Finished Aug 07 06:13:20 PM PDT 24
Peak memory 208948 kb
Host smart-a7827456-6cad-4b02-b096-4d34745f802b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933021215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1933021215
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1928708864
Short name T388
Test name
Test status
Simulation time 1376501187 ps
CPU time 13.46 seconds
Started Aug 07 06:13:17 PM PDT 24
Finished Aug 07 06:13:31 PM PDT 24
Peak memory 218236 kb
Host smart-97e47b6d-20ce-4429-b6f8-ad43bef7d2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928708864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1928708864
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3213428890
Short name T337
Test name
Test status
Simulation time 2952382721 ps
CPU time 28.35 seconds
Started Aug 07 06:13:17 PM PDT 24
Finished Aug 07 06:13:45 PM PDT 24
Peak memory 218944 kb
Host smart-8f7b5326-fc36-4461-848f-41d132c01c2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213428890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3213428890
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.4028778716
Short name T537
Test name
Test status
Simulation time 366962559 ps
CPU time 9.7 seconds
Started Aug 07 06:13:19 PM PDT 24
Finished Aug 07 06:13:29 PM PDT 24
Peak memory 217696 kb
Host smart-79e836df-fbda-4bfe-8b02-946a5f783814
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028778716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.4
028778716
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2142679282
Short name T698
Test name
Test status
Simulation time 1445693886 ps
CPU time 38.92 seconds
Started Aug 07 06:13:21 PM PDT 24
Finished Aug 07 06:14:00 PM PDT 24
Peak memory 217584 kb
Host smart-43dc088a-fe3f-4f2e-8cf3-70a2ed845ba8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142679282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2142679282
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2720012392
Short name T79
Test name
Test status
Simulation time 239089025 ps
CPU time 3.81 seconds
Started Aug 07 06:13:16 PM PDT 24
Finished Aug 07 06:13:20 PM PDT 24
Peak memory 217560 kb
Host smart-6e42f681-52cb-4789-9043-eacd20496a7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720012392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2720012392
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.4096059876
Short name T265
Test name
Test status
Simulation time 1088372023 ps
CPU time 32.05 seconds
Started Aug 07 06:13:21 PM PDT 24
Finished Aug 07 06:13:53 PM PDT 24
Peak memory 250816 kb
Host smart-8ad980c7-fc99-4e42-a588-50910edd0f0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096059876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.4096059876
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2915334491
Short name T478
Test name
Test status
Simulation time 1058766866 ps
CPU time 12.69 seconds
Started Aug 07 06:13:18 PM PDT 24
Finished Aug 07 06:13:31 PM PDT 24
Peak memory 250920 kb
Host smart-1dc6826f-b41f-4a96-935b-179b40d56d8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915334491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2915334491
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1453351970
Short name T455
Test name
Test status
Simulation time 18328729 ps
CPU time 1.49 seconds
Started Aug 07 06:13:20 PM PDT 24
Finished Aug 07 06:13:22 PM PDT 24
Peak memory 218192 kb
Host smart-d77c1225-d685-4636-97c1-5ffb042da325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453351970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1453351970
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1978865940
Short name T505
Test name
Test status
Simulation time 949691091 ps
CPU time 4.96 seconds
Started Aug 07 06:13:17 PM PDT 24
Finished Aug 07 06:13:22 PM PDT 24
Peak memory 213852 kb
Host smart-3dcffc87-a167-46e6-866e-af5b23e4f366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978865940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1978865940
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.4125493713
Short name T673
Test name
Test status
Simulation time 4916560747 ps
CPU time 16.53 seconds
Started Aug 07 06:13:19 PM PDT 24
Finished Aug 07 06:13:36 PM PDT 24
Peak memory 219516 kb
Host smart-de80566b-c12c-4f88-98f5-d26d9c1d24b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125493713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.4125493713
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2323696790
Short name T684
Test name
Test status
Simulation time 1362726559 ps
CPU time 7.87 seconds
Started Aug 07 06:13:21 PM PDT 24
Finished Aug 07 06:13:29 PM PDT 24
Peak memory 225984 kb
Host smart-b7ff0cf4-db16-4956-bee3-813464e8eb39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323696790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2323696790
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1036138388
Short name T407
Test name
Test status
Simulation time 1497752006 ps
CPU time 7.08 seconds
Started Aug 07 06:13:23 PM PDT 24
Finished Aug 07 06:13:30 PM PDT 24
Peak memory 218124 kb
Host smart-c5fae69c-ea2f-46d8-bca6-8358acb06842
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036138388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
036138388
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3545128729
Short name T475
Test name
Test status
Simulation time 1127361274 ps
CPU time 7.23 seconds
Started Aug 07 06:13:22 PM PDT 24
Finished Aug 07 06:13:29 PM PDT 24
Peak memory 223660 kb
Host smart-05ad163f-3c2c-4835-81a1-b2d90fd85d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545128729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3545128729
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3914768833
Short name T77
Test name
Test status
Simulation time 58082242 ps
CPU time 2.75 seconds
Started Aug 07 06:13:19 PM PDT 24
Finished Aug 07 06:13:22 PM PDT 24
Peak memory 214552 kb
Host smart-0a3fe5e3-07ff-484d-87b7-03aed9537599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914768833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3914768833
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1124881930
Short name T746
Test name
Test status
Simulation time 624817536 ps
CPU time 31.47 seconds
Started Aug 07 06:13:23 PM PDT 24
Finished Aug 07 06:13:55 PM PDT 24
Peak memory 250736 kb
Host smart-7f30cdf5-4f5d-49af-9244-63ef72bab94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124881930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1124881930
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2310247031
Short name T184
Test name
Test status
Simulation time 226122577 ps
CPU time 7.16 seconds
Started Aug 07 06:13:23 PM PDT 24
Finished Aug 07 06:13:30 PM PDT 24
Peak memory 250268 kb
Host smart-46f377ee-0a6f-4644-8473-20bd0f2dfc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310247031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2310247031
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3858278938
Short name T87
Test name
Test status
Simulation time 2207116668 ps
CPU time 80.67 seconds
Started Aug 07 06:13:20 PM PDT 24
Finished Aug 07 06:14:41 PM PDT 24
Peak memory 273488 kb
Host smart-d4c62905-3c2f-4180-9330-23b11c71382a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858278938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3858278938
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1749494576
Short name T591
Test name
Test status
Simulation time 13031065 ps
CPU time 0.81 seconds
Started Aug 07 06:13:19 PM PDT 24
Finished Aug 07 06:13:20 PM PDT 24
Peak memory 208864 kb
Host smart-f776d578-1af6-4db3-9020-c896224c8778
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749494576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1749494576
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1944085632
Short name T761
Test name
Test status
Simulation time 46578912 ps
CPU time 0.99 seconds
Started Aug 07 06:13:27 PM PDT 24
Finished Aug 07 06:13:28 PM PDT 24
Peak memory 208996 kb
Host smart-e3abcfa8-eaba-477f-82ee-f00d897d0159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944085632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1944085632
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.565884715
Short name T538
Test name
Test status
Simulation time 1182390112 ps
CPU time 13.69 seconds
Started Aug 07 06:13:26 PM PDT 24
Finished Aug 07 06:13:40 PM PDT 24
Peak memory 218204 kb
Host smart-c6ac102d-a6c4-4749-84a9-943d9d5c81a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565884715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.565884715
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.4223445479
Short name T414
Test name
Test status
Simulation time 691978506 ps
CPU time 8.58 seconds
Started Aug 07 06:13:29 PM PDT 24
Finished Aug 07 06:13:37 PM PDT 24
Peak memory 217108 kb
Host smart-5cb3d3bc-8ce1-460a-a8e0-158272d382fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223445479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.4223445479
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1371367572
Short name T32
Test name
Test status
Simulation time 14546549616 ps
CPU time 54.23 seconds
Started Aug 07 06:13:30 PM PDT 24
Finished Aug 07 06:14:24 PM PDT 24
Peak memory 218788 kb
Host smart-f12ecdf9-30aa-4faa-99db-0512c0eba931
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371367572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1371367572
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2464716218
Short name T376
Test name
Test status
Simulation time 1797664207 ps
CPU time 4.33 seconds
Started Aug 07 06:13:31 PM PDT 24
Finished Aug 07 06:13:35 PM PDT 24
Peak memory 217620 kb
Host smart-a9c4529b-770d-4fae-8b4b-7642fac2eee9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464716218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
464716218
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3180480074
Short name T394
Test name
Test status
Simulation time 207152862 ps
CPU time 4.26 seconds
Started Aug 07 06:13:27 PM PDT 24
Finished Aug 07 06:13:31 PM PDT 24
Peak memory 218264 kb
Host smart-1c3ef02b-3b91-4060-8724-f8c8e513a586
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180480074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3180480074
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.769284739
Short name T29
Test name
Test status
Simulation time 6358060957 ps
CPU time 23.92 seconds
Started Aug 07 06:13:25 PM PDT 24
Finished Aug 07 06:13:49 PM PDT 24
Peak memory 217596 kb
Host smart-d2f5b812-a71c-454b-ae7d-d983f1b9bd00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769284739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.769284739
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2335967308
Short name T824
Test name
Test status
Simulation time 102377352 ps
CPU time 2.14 seconds
Started Aug 07 06:13:27 PM PDT 24
Finished Aug 07 06:13:29 PM PDT 24
Peak memory 217576 kb
Host smart-24e3fbb0-1765-49b1-82c7-ad163c03efc0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335967308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2335967308
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.4143116401
Short name T330
Test name
Test status
Simulation time 6792254071 ps
CPU time 56.73 seconds
Started Aug 07 06:13:29 PM PDT 24
Finished Aug 07 06:14:25 PM PDT 24
Peak memory 275748 kb
Host smart-4a1e558b-9952-448e-850e-294e7f470846
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143116401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.4143116401
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1754223866
Short name T810
Test name
Test status
Simulation time 4424768913 ps
CPU time 35.97 seconds
Started Aug 07 06:13:28 PM PDT 24
Finished Aug 07 06:14:04 PM PDT 24
Peak memory 249016 kb
Host smart-e34ae056-5f54-4967-b3cc-b4019e80bb29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754223866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1754223866
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3145634779
Short name T341
Test name
Test status
Simulation time 111984312 ps
CPU time 2.26 seconds
Started Aug 07 06:13:30 PM PDT 24
Finished Aug 07 06:13:32 PM PDT 24
Peak memory 218212 kb
Host smart-061d7e15-5afb-4448-87e1-e3b0fa6d646a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145634779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3145634779
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1007257752
Short name T174
Test name
Test status
Simulation time 329035487 ps
CPU time 17.15 seconds
Started Aug 07 06:13:28 PM PDT 24
Finished Aug 07 06:13:45 PM PDT 24
Peak memory 217620 kb
Host smart-d9a8935a-637f-4ddb-998b-a176436d71dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007257752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1007257752
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.928689888
Short name T89
Test name
Test status
Simulation time 813967307 ps
CPU time 38.21 seconds
Started Aug 07 06:13:32 PM PDT 24
Finished Aug 07 06:14:10 PM PDT 24
Peak memory 283308 kb
Host smart-d82656c9-d097-464b-832f-c5e5af57363f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928689888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.928689888
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3750709615
Short name T441
Test name
Test status
Simulation time 584943017 ps
CPU time 25.42 seconds
Started Aug 07 06:13:25 PM PDT 24
Finished Aug 07 06:13:50 PM PDT 24
Peak memory 225832 kb
Host smart-8eb7d407-263b-405c-b8f6-2b01fd76edd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750709615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3750709615
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3478288791
Short name T846
Test name
Test status
Simulation time 300960585 ps
CPU time 9.22 seconds
Started Aug 07 06:13:26 PM PDT 24
Finished Aug 07 06:13:36 PM PDT 24
Peak memory 225940 kb
Host smart-c791217b-d0dc-4c62-b795-5da8361f41e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478288791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3478288791
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1651173863
Short name T774
Test name
Test status
Simulation time 518517655 ps
CPU time 11.61 seconds
Started Aug 07 06:13:29 PM PDT 24
Finished Aug 07 06:13:41 PM PDT 24
Peak memory 218164 kb
Host smart-896c4bb5-f9e7-485b-85e8-eb9be1063fe5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651173863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
651173863
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.647041145
Short name T154
Test name
Test status
Simulation time 1092552574 ps
CPU time 12.27 seconds
Started Aug 07 06:13:29 PM PDT 24
Finished Aug 07 06:13:42 PM PDT 24
Peak memory 218292 kb
Host smart-447976af-bdd6-4c21-85cc-42966aebd748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647041145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.647041145
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3508013645
Short name T617
Test name
Test status
Simulation time 42375942 ps
CPU time 2.96 seconds
Started Aug 07 06:13:18 PM PDT 24
Finished Aug 07 06:13:21 PM PDT 24
Peak memory 223860 kb
Host smart-aab1d743-3a89-4284-8011-cc1df136be7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508013645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3508013645
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1934341835
Short name T315
Test name
Test status
Simulation time 1303516776 ps
CPU time 24.22 seconds
Started Aug 07 06:13:26 PM PDT 24
Finished Aug 07 06:13:51 PM PDT 24
Peak memory 250856 kb
Host smart-a65251b1-9a98-433a-99e0-43ab32ae0743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934341835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1934341835
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.527012003
Short name T803
Test name
Test status
Simulation time 360148581 ps
CPU time 7.99 seconds
Started Aug 07 06:13:28 PM PDT 24
Finished Aug 07 06:13:37 PM PDT 24
Peak memory 250788 kb
Host smart-bc2e5568-3b44-4fe2-9718-e5d0f5522e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527012003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.527012003
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3647890506
Short name T630
Test name
Test status
Simulation time 187204557835 ps
CPU time 237.87 seconds
Started Aug 07 06:13:31 PM PDT 24
Finished Aug 07 06:17:29 PM PDT 24
Peak memory 283616 kb
Host smart-dd2d57ab-96ad-49f6-a614-eb276d8ffccf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647890506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3647890506
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2059595406
Short name T182
Test name
Test status
Simulation time 31557025900 ps
CPU time 1247.2 seconds
Started Aug 07 06:13:26 PM PDT 24
Finished Aug 07 06:34:13 PM PDT 24
Peak memory 513180 kb
Host smart-e46997d0-7543-4d3c-b3b0-1cd712689770
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2059595406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.2059595406
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2348761251
Short name T562
Test name
Test status
Simulation time 11223087 ps
CPU time 0.9 seconds
Started Aug 07 06:13:20 PM PDT 24
Finished Aug 07 06:13:21 PM PDT 24
Peak memory 208520 kb
Host smart-70683a26-2989-41a3-b964-089fd7ca1040
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348761251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2348761251
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.104046026
Short name T553
Test name
Test status
Simulation time 43163525 ps
CPU time 0.93 seconds
Started Aug 07 06:14:16 PM PDT 24
Finished Aug 07 06:14:17 PM PDT 24
Peak memory 208888 kb
Host smart-84381955-90a8-485e-8577-1691b0705d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104046026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.104046026
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1536548893
Short name T696
Test name
Test status
Simulation time 525222259 ps
CPU time 13.63 seconds
Started Aug 07 06:14:05 PM PDT 24
Finished Aug 07 06:14:19 PM PDT 24
Peak memory 218112 kb
Host smart-fa3c52c4-0284-417e-a372-2bc84d5faa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536548893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1536548893
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1401406262
Short name T7
Test name
Test status
Simulation time 61363252 ps
CPU time 1.45 seconds
Started Aug 07 06:14:04 PM PDT 24
Finished Aug 07 06:14:05 PM PDT 24
Peak memory 217096 kb
Host smart-70b40adb-8ec3-4a56-a2f1-2c31cf425e01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401406262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1401406262
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1194535575
Short name T619
Test name
Test status
Simulation time 10216143295 ps
CPU time 91.41 seconds
Started Aug 07 06:14:05 PM PDT 24
Finished Aug 07 06:15:36 PM PDT 24
Peak memory 219888 kb
Host smart-a90c6eee-4fd0-4f9a-9cf0-d86c5127bab9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194535575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1194535575
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1114101219
Short name T274
Test name
Test status
Simulation time 337852311 ps
CPU time 3.27 seconds
Started Aug 07 06:14:04 PM PDT 24
Finished Aug 07 06:14:08 PM PDT 24
Peak memory 221632 kb
Host smart-200a85d3-4c5a-4783-8a99-57ee5bb68db3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114101219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1114101219
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2000228639
Short name T244
Test name
Test status
Simulation time 277838398 ps
CPU time 1.79 seconds
Started Aug 07 06:14:04 PM PDT 24
Finished Aug 07 06:14:05 PM PDT 24
Peak memory 217592 kb
Host smart-d4ed1895-b086-4e38-9c55-387efa558272
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000228639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2000228639
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.144141053
Short name T461
Test name
Test status
Simulation time 21784975071 ps
CPU time 89.61 seconds
Started Aug 07 06:14:07 PM PDT 24
Finished Aug 07 06:15:37 PM PDT 24
Peak memory 276504 kb
Host smart-5cdb4532-8757-4854-b968-e12039c118c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144141053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.144141053
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3088933832
Short name T640
Test name
Test status
Simulation time 565510810 ps
CPU time 12.23 seconds
Started Aug 07 06:14:09 PM PDT 24
Finished Aug 07 06:14:21 PM PDT 24
Peak memory 226164 kb
Host smart-b16a96f7-b7b5-460e-9bbe-bb2e6c5db19b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088933832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3088933832
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.279736204
Short name T309
Test name
Test status
Simulation time 91236390 ps
CPU time 4.3 seconds
Started Aug 07 06:14:04 PM PDT 24
Finished Aug 07 06:14:08 PM PDT 24
Peak memory 218204 kb
Host smart-bfec4136-2dd6-4534-a703-6fedbf8a67a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279736204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.279736204
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.4011785855
Short name T234
Test name
Test status
Simulation time 1388289936 ps
CPU time 11.47 seconds
Started Aug 07 06:14:06 PM PDT 24
Finished Aug 07 06:14:18 PM PDT 24
Peak memory 226008 kb
Host smart-02ad76d8-8dd8-4d88-a6a7-e195ba1d3072
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011785855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.4011785855
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3048591144
Short name T400
Test name
Test status
Simulation time 1660971545 ps
CPU time 10.22 seconds
Started Aug 07 06:14:03 PM PDT 24
Finished Aug 07 06:14:14 PM PDT 24
Peak memory 225964 kb
Host smart-bf3cb006-5263-41c1-9dcc-e0a911745648
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048591144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3048591144
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3818347151
Short name T177
Test name
Test status
Simulation time 1461564173 ps
CPU time 12.72 seconds
Started Aug 07 06:14:03 PM PDT 24
Finished Aug 07 06:14:16 PM PDT 24
Peak memory 225904 kb
Host smart-a4d5ee49-1b0c-4f63-a8ab-f2a75c038c9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818347151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3818347151
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1763174961
Short name T550
Test name
Test status
Simulation time 2967157000 ps
CPU time 10.34 seconds
Started Aug 07 06:14:05 PM PDT 24
Finished Aug 07 06:14:15 PM PDT 24
Peak memory 226068 kb
Host smart-af332d2b-0f4f-497d-9435-cf31e2b1c323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763174961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1763174961
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1622375608
Short name T64
Test name
Test status
Simulation time 66827862 ps
CPU time 1.69 seconds
Started Aug 07 06:14:05 PM PDT 24
Finished Aug 07 06:14:07 PM PDT 24
Peak memory 223184 kb
Host smart-b7ef5276-c71a-4c45-aa1e-f554a7d0fd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622375608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1622375608
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2323899411
Short name T363
Test name
Test status
Simulation time 209519745 ps
CPU time 21.54 seconds
Started Aug 07 06:14:06 PM PDT 24
Finished Aug 07 06:14:27 PM PDT 24
Peak memory 250668 kb
Host smart-8719b316-0bad-4389-a63c-9ef454af6828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323899411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2323899411
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1697931795
Short name T571
Test name
Test status
Simulation time 157763765 ps
CPU time 7.77 seconds
Started Aug 07 06:14:08 PM PDT 24
Finished Aug 07 06:14:16 PM PDT 24
Peak memory 250836 kb
Host smart-fed8f943-d7af-4fcc-9e90-080d00c22415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697931795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1697931795
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2471828447
Short name T186
Test name
Test status
Simulation time 2119628553 ps
CPU time 86.61 seconds
Started Aug 07 06:14:04 PM PDT 24
Finished Aug 07 06:15:31 PM PDT 24
Peak memory 250872 kb
Host smart-9580f5d8-ecfb-4cf1-af59-391a985fc5c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471828447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2471828447
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.2109704160
Short name T183
Test name
Test status
Simulation time 49239895476 ps
CPU time 901.92 seconds
Started Aug 07 06:14:15 PM PDT 24
Finished Aug 07 06:29:18 PM PDT 24
Peak memory 513140 kb
Host smart-e6c61c37-8e07-4eea-baed-f0efe4b1d819
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2109704160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.2109704160
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.983667123
Short name T349
Test name
Test status
Simulation time 45382764 ps
CPU time 1.06 seconds
Started Aug 07 06:14:07 PM PDT 24
Finished Aug 07 06:14:09 PM PDT 24
Peak memory 211920 kb
Host smart-d1490215-8bf7-414c-b87f-1baa85cc9060
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983667123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.983667123
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.911157750
Short name T641
Test name
Test status
Simulation time 25328604 ps
CPU time 1.02 seconds
Started Aug 07 06:14:13 PM PDT 24
Finished Aug 07 06:14:14 PM PDT 24
Peak memory 208900 kb
Host smart-b91c3b1b-7dcd-4dc9-b2bd-9fdace1b2511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911157750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.911157750
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.4138338340
Short name T24
Test name
Test status
Simulation time 1375162768 ps
CPU time 3.87 seconds
Started Aug 07 06:14:15 PM PDT 24
Finished Aug 07 06:14:19 PM PDT 24
Peak memory 217096 kb
Host smart-2d4b2236-cae0-4518-a7c1-b89241c486b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138338340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.4138338340
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2662461766
Short name T46
Test name
Test status
Simulation time 10152315253 ps
CPU time 116.02 seconds
Started Aug 07 06:14:15 PM PDT 24
Finished Aug 07 06:16:12 PM PDT 24
Peak memory 219940 kb
Host smart-fd5ed105-7762-41bb-9620-25f40d3aa1f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662461766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2662461766
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.945763620
Short name T703
Test name
Test status
Simulation time 367725106 ps
CPU time 10.84 seconds
Started Aug 07 06:14:14 PM PDT 24
Finished Aug 07 06:14:25 PM PDT 24
Peak memory 223008 kb
Host smart-0206c78f-b1d8-4dc7-8171-f8a2c5b318eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945763620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.945763620
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3317355559
Short name T76
Test name
Test status
Simulation time 2371511737 ps
CPU time 14.92 seconds
Started Aug 07 06:14:15 PM PDT 24
Finished Aug 07 06:14:30 PM PDT 24
Peak memory 217696 kb
Host smart-11c53d13-d657-4984-b218-cefda4e6e1eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317355559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3317355559
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3378265092
Short name T662
Test name
Test status
Simulation time 3734758033 ps
CPU time 73.31 seconds
Started Aug 07 06:14:15 PM PDT 24
Finished Aug 07 06:15:28 PM PDT 24
Peak memory 275892 kb
Host smart-182e5d69-6155-42e4-8f13-1557fdae0972
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378265092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3378265092
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2863368744
Short name T17
Test name
Test status
Simulation time 1372770262 ps
CPU time 7.35 seconds
Started Aug 07 06:14:16 PM PDT 24
Finished Aug 07 06:14:24 PM PDT 24
Peak memory 218144 kb
Host smart-e2973d3b-2f50-48b3-801e-f808804f855e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863368744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2863368744
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.188083792
Short name T701
Test name
Test status
Simulation time 177157331 ps
CPU time 2.63 seconds
Started Aug 07 06:14:14 PM PDT 24
Finished Aug 07 06:14:17 PM PDT 24
Peak memory 218216 kb
Host smart-f7e4c945-d95d-420b-b6f2-63bf4c8ceb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188083792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.188083792
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.806667464
Short name T727
Test name
Test status
Simulation time 896692294 ps
CPU time 12.86 seconds
Started Aug 07 06:14:13 PM PDT 24
Finished Aug 07 06:14:27 PM PDT 24
Peak memory 225692 kb
Host smart-62f78ba0-95e4-4040-8ad0-43e6c3f6729c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806667464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.806667464
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1966033858
Short name T643
Test name
Test status
Simulation time 693497291 ps
CPU time 10.39 seconds
Started Aug 07 06:14:13 PM PDT 24
Finished Aug 07 06:14:24 PM PDT 24
Peak memory 225928 kb
Host smart-e4865c45-93d4-4aa6-8874-0072c1d21163
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966033858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1966033858
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.812493014
Short name T715
Test name
Test status
Simulation time 860216222 ps
CPU time 9.25 seconds
Started Aug 07 06:14:14 PM PDT 24
Finished Aug 07 06:14:24 PM PDT 24
Peak memory 225896 kb
Host smart-3249e47b-1862-40f1-af09-38a569cc93a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812493014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.812493014
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3549835072
Short name T637
Test name
Test status
Simulation time 389482784 ps
CPU time 9.02 seconds
Started Aug 07 06:14:13 PM PDT 24
Finished Aug 07 06:14:22 PM PDT 24
Peak memory 218280 kb
Host smart-caa4199a-2e1c-458d-a3bd-3c47bb950e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549835072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3549835072
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2501075833
Short name T753
Test name
Test status
Simulation time 53378572 ps
CPU time 3.03 seconds
Started Aug 07 06:14:13 PM PDT 24
Finished Aug 07 06:14:17 PM PDT 24
Peak memory 217664 kb
Host smart-be7f6f1a-07be-4e2b-9e77-d6d871598888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501075833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2501075833
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.154709963
Short name T150
Test name
Test status
Simulation time 441501233 ps
CPU time 24.83 seconds
Started Aug 07 06:14:11 PM PDT 24
Finished Aug 07 06:14:36 PM PDT 24
Peak memory 250928 kb
Host smart-1ed850f2-9526-4b14-921c-a70f93b76f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154709963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.154709963
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1806075080
Short name T404
Test name
Test status
Simulation time 244564870 ps
CPU time 9.17 seconds
Started Aug 07 06:14:16 PM PDT 24
Finished Aug 07 06:14:25 PM PDT 24
Peak memory 250752 kb
Host smart-60b6e6cc-8643-424b-9332-8e02cc6175a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806075080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1806075080
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1124130223
Short name T541
Test name
Test status
Simulation time 15180181706 ps
CPU time 113.49 seconds
Started Aug 07 06:14:12 PM PDT 24
Finished Aug 07 06:16:05 PM PDT 24
Peak memory 221160 kb
Host smart-2dd49801-cd62-442e-a6ef-85703d6ad263
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124130223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1124130223
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.940623996
Short name T470
Test name
Test status
Simulation time 17950515 ps
CPU time 0.75 seconds
Started Aug 07 06:14:15 PM PDT 24
Finished Aug 07 06:14:16 PM PDT 24
Peak memory 207392 kb
Host smart-0177d6a4-02a0-4fbf-ae5c-5c215c34a3fd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940623996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.940623996
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3873529661
Short name T706
Test name
Test status
Simulation time 110557303 ps
CPU time 1 seconds
Started Aug 07 06:14:23 PM PDT 24
Finished Aug 07 06:14:24 PM PDT 24
Peak memory 208832 kb
Host smart-bb926b4e-2450-40ba-957c-90f047e781b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873529661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3873529661
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2824049816
Short name T635
Test name
Test status
Simulation time 436088258 ps
CPU time 5.31 seconds
Started Aug 07 06:14:21 PM PDT 24
Finished Aug 07 06:14:27 PM PDT 24
Peak memory 217032 kb
Host smart-81790326-c234-413e-807b-6e1a16cdc276
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824049816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2824049816
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3645132315
Short name T457
Test name
Test status
Simulation time 1861030399 ps
CPU time 57.18 seconds
Started Aug 07 06:14:23 PM PDT 24
Finished Aug 07 06:15:20 PM PDT 24
Peak memory 218156 kb
Host smart-8c33560d-7548-4646-b8c2-73a150eff7ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645132315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3645132315
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.150665350
Short name T436
Test name
Test status
Simulation time 1026804011 ps
CPU time 15.29 seconds
Started Aug 07 06:14:23 PM PDT 24
Finished Aug 07 06:14:38 PM PDT 24
Peak memory 218156 kb
Host smart-845a2c13-93d6-43b8-94e4-9d6392afcbcd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150665350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.150665350
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.755119914
Short name T81
Test name
Test status
Simulation time 553870905 ps
CPU time 6.48 seconds
Started Aug 07 06:14:22 PM PDT 24
Finished Aug 07 06:14:29 PM PDT 24
Peak memory 217496 kb
Host smart-85bcc130-8cf4-4380-b725-5f976e01181e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755119914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
755119914
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2319150162
Short name T440
Test name
Test status
Simulation time 2016366676 ps
CPU time 49.07 seconds
Started Aug 07 06:14:25 PM PDT 24
Finished Aug 07 06:15:14 PM PDT 24
Peak memory 251620 kb
Host smart-1e6fa180-83bf-40b0-8d23-ac5f0931c5b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319150162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2319150162
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.910567101
Short name T546
Test name
Test status
Simulation time 1865126273 ps
CPU time 12.1 seconds
Started Aug 07 06:14:27 PM PDT 24
Finished Aug 07 06:14:39 PM PDT 24
Peak memory 250252 kb
Host smart-1262342a-2a81-448b-8cb1-6222892a639a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910567101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.910567101
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.408844690
Short name T723
Test name
Test status
Simulation time 100860720 ps
CPU time 2.12 seconds
Started Aug 07 06:14:11 PM PDT 24
Finished Aug 07 06:14:14 PM PDT 24
Peak memory 218192 kb
Host smart-b8efa31b-71d8-4aea-ab29-15723b8e098d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408844690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.408844690
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1983420703
Short name T305
Test name
Test status
Simulation time 652895027 ps
CPU time 9.43 seconds
Started Aug 07 06:14:22 PM PDT 24
Finished Aug 07 06:14:31 PM PDT 24
Peak memory 218852 kb
Host smart-8d7c72a4-6207-4da6-ac69-876cd43a47d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983420703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1983420703
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2641592219
Short name T531
Test name
Test status
Simulation time 1015380993 ps
CPU time 10.54 seconds
Started Aug 07 06:14:24 PM PDT 24
Finished Aug 07 06:14:35 PM PDT 24
Peak memory 225844 kb
Host smart-8e309a0b-c541-4ca6-a0cb-af403910566e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641592219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2641592219
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2254104519
Short name T584
Test name
Test status
Simulation time 1535106123 ps
CPU time 9.23 seconds
Started Aug 07 06:14:23 PM PDT 24
Finished Aug 07 06:14:33 PM PDT 24
Peak memory 225944 kb
Host smart-1227de1d-fc3a-4cf1-8c44-b8be538f12fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254104519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2254104519
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3869389715
Short name T385
Test name
Test status
Simulation time 4205572889 ps
CPU time 7.27 seconds
Started Aug 07 06:14:25 PM PDT 24
Finished Aug 07 06:14:32 PM PDT 24
Peak memory 218372 kb
Host smart-35b01873-f36b-41e3-b509-3cab44132e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869389715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3869389715
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3150197110
Short name T252
Test name
Test status
Simulation time 624011963 ps
CPU time 2.04 seconds
Started Aug 07 06:14:13 PM PDT 24
Finished Aug 07 06:14:16 PM PDT 24
Peak memory 214180 kb
Host smart-dd1e94de-0af7-4318-94ba-7c5292bb98a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150197110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3150197110
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1868027099
Short name T347
Test name
Test status
Simulation time 785352093 ps
CPU time 20.6 seconds
Started Aug 07 06:14:14 PM PDT 24
Finished Aug 07 06:14:35 PM PDT 24
Peak memory 245480 kb
Host smart-48d1398d-9e35-49f1-a643-cbf7f71cdc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868027099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1868027099
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3089098399
Short name T434
Test name
Test status
Simulation time 182048209 ps
CPU time 10.24 seconds
Started Aug 07 06:14:13 PM PDT 24
Finished Aug 07 06:14:23 PM PDT 24
Peak memory 244348 kb
Host smart-68be9a74-baa9-453c-bbe1-e95971c85f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089098399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3089098399
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4261228751
Short name T566
Test name
Test status
Simulation time 27764366 ps
CPU time 1.04 seconds
Started Aug 07 06:14:10 PM PDT 24
Finished Aug 07 06:14:11 PM PDT 24
Peak memory 211940 kb
Host smart-f8a4cb92-e5d5-4371-9ceb-1c8c70f1536b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261228751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.4261228751
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2291215645
Short name T551
Test name
Test status
Simulation time 33138281 ps
CPU time 1.16 seconds
Started Aug 07 06:14:26 PM PDT 24
Finished Aug 07 06:14:28 PM PDT 24
Peak memory 208988 kb
Host smart-f67fd442-33b3-463e-840d-c3f3ca307875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291215645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2291215645
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2733334983
Short name T719
Test name
Test status
Simulation time 824308125 ps
CPU time 23.79 seconds
Started Aug 07 06:14:27 PM PDT 24
Finished Aug 07 06:14:50 PM PDT 24
Peak memory 226008 kb
Host smart-ca49d224-f3cd-4d8a-a6e8-0d5591264d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733334983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2733334983
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3729857315
Short name T738
Test name
Test status
Simulation time 2745545975 ps
CPU time 8.65 seconds
Started Aug 07 06:14:26 PM PDT 24
Finished Aug 07 06:14:35 PM PDT 24
Peak memory 217532 kb
Host smart-57e68442-95f1-4ff0-b1de-ae2ebd66f10a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729857315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3729857315
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2402767082
Short name T683
Test name
Test status
Simulation time 3446725355 ps
CPU time 29.44 seconds
Started Aug 07 06:14:22 PM PDT 24
Finished Aug 07 06:14:52 PM PDT 24
Peak memory 218856 kb
Host smart-0cbc690d-5aed-4e89-b451-8104830d252b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402767082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2402767082
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1380669586
Short name T102
Test name
Test status
Simulation time 267530600 ps
CPU time 2.93 seconds
Started Aug 07 06:14:26 PM PDT 24
Finished Aug 07 06:14:29 PM PDT 24
Peak memory 218168 kb
Host smart-6d6ebfd4-99c7-459c-a494-b39d73c3a215
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380669586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1380669586
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3942060284
Short name T75
Test name
Test status
Simulation time 889954815 ps
CPU time 11.84 seconds
Started Aug 07 06:14:26 PM PDT 24
Finished Aug 07 06:14:38 PM PDT 24
Peak memory 217576 kb
Host smart-631897b8-e401-4f8b-83ec-1c6b0f4a9ca3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942060284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3942060284
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2985504583
Short name T579
Test name
Test status
Simulation time 4831002156 ps
CPU time 56.85 seconds
Started Aug 07 06:14:24 PM PDT 24
Finished Aug 07 06:15:21 PM PDT 24
Peak memory 268732 kb
Host smart-68d3aeb5-d49a-497f-82fa-7c3e3fe934d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985504583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2985504583
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3791055420
Short name T218
Test name
Test status
Simulation time 2106855781 ps
CPU time 17.51 seconds
Started Aug 07 06:14:23 PM PDT 24
Finished Aug 07 06:14:41 PM PDT 24
Peak memory 221956 kb
Host smart-432ec5e8-ff0c-4bcd-86d1-418ac709daff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791055420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3791055420
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2426735549
Short name T374
Test name
Test status
Simulation time 27409230 ps
CPU time 2.08 seconds
Started Aug 07 06:14:24 PM PDT 24
Finished Aug 07 06:14:26 PM PDT 24
Peak memory 222024 kb
Host smart-a617a0c9-5fe6-4ffd-9ef7-460e3118374f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426735549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2426735549
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3429572946
Short name T321
Test name
Test status
Simulation time 819903867 ps
CPU time 18.29 seconds
Started Aug 07 06:14:25 PM PDT 24
Finished Aug 07 06:14:44 PM PDT 24
Peak memory 226004 kb
Host smart-c1a3c92c-403b-4bd4-99a7-a552c2dbd55c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429572946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3429572946
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2702964998
Short name T255
Test name
Test status
Simulation time 11349053808 ps
CPU time 17.83 seconds
Started Aug 07 06:14:25 PM PDT 24
Finished Aug 07 06:14:43 PM PDT 24
Peak memory 226024 kb
Host smart-a28d43ba-ff50-4fe8-8c65-ad0985bb84fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702964998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2702964998
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1173646677
Short name T838
Test name
Test status
Simulation time 571107780 ps
CPU time 11.07 seconds
Started Aug 07 06:14:24 PM PDT 24
Finished Aug 07 06:14:36 PM PDT 24
Peak memory 225976 kb
Host smart-351353e5-8fc9-4bdc-b48f-7bb0ef4e9830
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173646677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1173646677
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2906409397
Short name T778
Test name
Test status
Simulation time 1146880588 ps
CPU time 9.44 seconds
Started Aug 07 06:14:26 PM PDT 24
Finished Aug 07 06:14:35 PM PDT 24
Peak memory 225980 kb
Host smart-e1c54dfd-043d-4b57-a4ea-e12489f1b88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906409397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2906409397
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2663586490
Short name T831
Test name
Test status
Simulation time 181574794 ps
CPU time 3.29 seconds
Started Aug 07 06:14:24 PM PDT 24
Finished Aug 07 06:14:28 PM PDT 24
Peak memory 217620 kb
Host smart-4a59fdfe-38d7-492e-b0c2-7483d1345abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663586490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2663586490
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3230871726
Short name T28
Test name
Test status
Simulation time 321495552 ps
CPU time 20.92 seconds
Started Aug 07 06:14:25 PM PDT 24
Finished Aug 07 06:14:46 PM PDT 24
Peak memory 250740 kb
Host smart-c972e193-830a-4186-87cd-a50fedb786da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230871726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3230871726
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3621676831
Short name T633
Test name
Test status
Simulation time 223345967 ps
CPU time 6.61 seconds
Started Aug 07 06:14:26 PM PDT 24
Finished Aug 07 06:14:32 PM PDT 24
Peak memory 250596 kb
Host smart-92d18b23-3485-4d70-aab0-6495ab39494b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621676831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3621676831
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.14640788
Short name T872
Test name
Test status
Simulation time 718149892 ps
CPU time 19.59 seconds
Started Aug 07 06:14:24 PM PDT 24
Finished Aug 07 06:14:44 PM PDT 24
Peak memory 250848 kb
Host smart-39b28203-3f07-4a4c-a2bc-d6f7af28c459
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14640788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.lc_ctrl_stress_all.14640788
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.484365399
Short name T661
Test name
Test status
Simulation time 43833723285 ps
CPU time 491.53 seconds
Started Aug 07 06:14:25 PM PDT 24
Finished Aug 07 06:22:36 PM PDT 24
Peak memory 263036 kb
Host smart-cb9a765d-b96c-4fad-bad3-b88c4e312e78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=484365399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.484365399
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2229344966
Short name T767
Test name
Test status
Simulation time 122406507 ps
CPU time 0.97 seconds
Started Aug 07 06:14:24 PM PDT 24
Finished Aug 07 06:14:25 PM PDT 24
Peak memory 217728 kb
Host smart-41b96a80-89cb-45c6-91ab-fc54a83a87c4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229344966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2229344966
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.994510442
Short name T567
Test name
Test status
Simulation time 65612889 ps
CPU time 1.02 seconds
Started Aug 07 06:14:33 PM PDT 24
Finished Aug 07 06:14:35 PM PDT 24
Peak memory 208840 kb
Host smart-963755d5-5da7-41f8-b3d0-41c3bcefd9ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994510442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.994510442
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1996179909
Short name T224
Test name
Test status
Simulation time 1673454998 ps
CPU time 13.14 seconds
Started Aug 07 06:14:25 PM PDT 24
Finished Aug 07 06:14:38 PM PDT 24
Peak memory 225952 kb
Host smart-dbfd86a9-c1cd-4d88-ac7f-36e4c97d5207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996179909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1996179909
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.4030305226
Short name T835
Test name
Test status
Simulation time 471370519 ps
CPU time 1.33 seconds
Started Aug 07 06:14:34 PM PDT 24
Finished Aug 07 06:14:36 PM PDT 24
Peak memory 216996 kb
Host smart-66386cd2-0472-4bcd-817a-8b3e85117d93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030305226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.4030305226
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2523174807
Short name T266
Test name
Test status
Simulation time 2466051148 ps
CPU time 39.91 seconds
Started Aug 07 06:14:36 PM PDT 24
Finished Aug 07 06:15:16 PM PDT 24
Peak memory 218196 kb
Host smart-8c361afc-9499-4244-9804-db2736b9b187
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523174807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2523174807
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3890274743
Short name T456
Test name
Test status
Simulation time 174030725 ps
CPU time 3.9 seconds
Started Aug 07 06:14:33 PM PDT 24
Finished Aug 07 06:14:38 PM PDT 24
Peak memory 218160 kb
Host smart-bd083557-7122-4b0d-a2a6-855c37c503a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890274743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3890274743
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1485159618
Short name T445
Test name
Test status
Simulation time 1125314470 ps
CPU time 6.89 seconds
Started Aug 07 06:14:33 PM PDT 24
Finished Aug 07 06:14:40 PM PDT 24
Peak memory 217580 kb
Host smart-4c7f6b9f-3520-4a2e-93e7-3410886ddbd9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485159618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1485159618
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2083153262
Short name T448
Test name
Test status
Simulation time 8059058080 ps
CPU time 61.23 seconds
Started Aug 07 06:14:36 PM PDT 24
Finished Aug 07 06:15:37 PM PDT 24
Peak memory 276096 kb
Host smart-cc432e9d-3620-40ce-8b62-d45b0e08df8d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083153262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2083153262
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2976025236
Short name T750
Test name
Test status
Simulation time 1274629949 ps
CPU time 17.55 seconds
Started Aug 07 06:14:35 PM PDT 24
Finished Aug 07 06:14:53 PM PDT 24
Peak memory 226168 kb
Host smart-b9bf8f01-307f-4a41-bfaa-adefa3319579
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976025236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2976025236
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1895817324
Short name T297
Test name
Test status
Simulation time 78232332 ps
CPU time 3.68 seconds
Started Aug 07 06:14:22 PM PDT 24
Finished Aug 07 06:14:26 PM PDT 24
Peak memory 218216 kb
Host smart-762732c2-9688-4269-9754-ad100b967056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895817324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1895817324
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3309366461
Short name T620
Test name
Test status
Simulation time 1165964162 ps
CPU time 12.32 seconds
Started Aug 07 06:14:35 PM PDT 24
Finished Aug 07 06:14:47 PM PDT 24
Peak memory 225996 kb
Host smart-6467dbf5-37a5-43c5-8916-502f41a10326
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309366461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3309366461
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.721809962
Short name T729
Test name
Test status
Simulation time 3222215956 ps
CPU time 19.45 seconds
Started Aug 07 06:14:37 PM PDT 24
Finished Aug 07 06:14:57 PM PDT 24
Peak memory 226000 kb
Host smart-1880176a-5e93-4245-a1ca-9ce02a4de0f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721809962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.721809962
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1537086750
Short name T520
Test name
Test status
Simulation time 1431639188 ps
CPU time 9.19 seconds
Started Aug 07 06:14:35 PM PDT 24
Finished Aug 07 06:14:44 PM PDT 24
Peak memory 225108 kb
Host smart-f4f34c55-2bd8-4a4b-bafb-2fddade5f547
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537086750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1537086750
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2898477532
Short name T771
Test name
Test status
Simulation time 340235174 ps
CPU time 13.48 seconds
Started Aug 07 06:14:36 PM PDT 24
Finished Aug 07 06:14:50 PM PDT 24
Peak memory 218252 kb
Host smart-2c094d27-c6cf-4edd-83c0-59d1db6be623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898477532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2898477532
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1431284600
Short name T646
Test name
Test status
Simulation time 49767379 ps
CPU time 3.69 seconds
Started Aug 07 06:14:23 PM PDT 24
Finished Aug 07 06:14:26 PM PDT 24
Peak memory 217636 kb
Host smart-90abd6cb-ade3-4b73-abed-8a5b257f467a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431284600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1431284600
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2629698608
Short name T849
Test name
Test status
Simulation time 223072657 ps
CPU time 25.65 seconds
Started Aug 07 06:14:26 PM PDT 24
Finished Aug 07 06:14:52 PM PDT 24
Peak memory 250876 kb
Host smart-a05cd569-d222-4324-8529-15750cf90ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629698608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2629698608
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.4098079925
Short name T373
Test name
Test status
Simulation time 67583278 ps
CPU time 6.84 seconds
Started Aug 07 06:14:24 PM PDT 24
Finished Aug 07 06:14:31 PM PDT 24
Peak memory 246548 kb
Host smart-43ddb740-a332-4136-930b-e848be2f7d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098079925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.4098079925
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2201117940
Short name T498
Test name
Test status
Simulation time 14648794971 ps
CPU time 174.8 seconds
Started Aug 07 06:14:34 PM PDT 24
Finished Aug 07 06:17:29 PM PDT 24
Peak memory 283668 kb
Host smart-51fe10c8-d6f2-476d-9ae8-b1625a2ea991
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201117940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2201117940
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1671745024
Short name T42
Test name
Test status
Simulation time 92168191 ps
CPU time 1.33 seconds
Started Aug 07 06:14:24 PM PDT 24
Finished Aug 07 06:14:25 PM PDT 24
Peak memory 217732 kb
Host smart-684c7b7a-74e7-4526-8bf2-b0daa0e1dd7b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671745024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1671745024
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1402114101
Short name T317
Test name
Test status
Simulation time 15572120 ps
CPU time 1.04 seconds
Started Aug 07 06:14:35 PM PDT 24
Finished Aug 07 06:14:36 PM PDT 24
Peak memory 208960 kb
Host smart-1d330fc5-0888-476d-a85d-8a5738e4c5a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402114101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1402114101
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2192136370
Short name T832
Test name
Test status
Simulation time 1563724049 ps
CPU time 16.52 seconds
Started Aug 07 06:14:37 PM PDT 24
Finished Aug 07 06:14:53 PM PDT 24
Peak memory 225996 kb
Host smart-ffb2e56f-e103-4882-b054-3d62b50e6d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192136370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2192136370
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.250418719
Short name T704
Test name
Test status
Simulation time 600658860 ps
CPU time 8.53 seconds
Started Aug 07 06:14:35 PM PDT 24
Finished Aug 07 06:14:43 PM PDT 24
Peak memory 217120 kb
Host smart-ace107ce-9cda-4231-a70e-c301db9fb50f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250418719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.250418719
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2845403729
Short name T418
Test name
Test status
Simulation time 51144448398 ps
CPU time 49.5 seconds
Started Aug 07 06:14:39 PM PDT 24
Finished Aug 07 06:15:28 PM PDT 24
Peak memory 218856 kb
Host smart-92388c57-b498-48b8-a1cc-f1b71d92673f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845403729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2845403729
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.892970258
Short name T422
Test name
Test status
Simulation time 609737618 ps
CPU time 9.31 seconds
Started Aug 07 06:14:35 PM PDT 24
Finished Aug 07 06:14:45 PM PDT 24
Peak memory 225220 kb
Host smart-a20e8b0e-1242-4da2-88e3-d1bba178af73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892970258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.892970258
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.956195920
Short name T249
Test name
Test status
Simulation time 336926717 ps
CPU time 2.07 seconds
Started Aug 07 06:14:32 PM PDT 24
Finished Aug 07 06:14:35 PM PDT 24
Peak memory 217704 kb
Host smart-60e9fdb4-7238-4189-849d-08af5dcd7ac6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956195920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
956195920
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.395427231
Short name T709
Test name
Test status
Simulation time 12595668753 ps
CPU time 66.39 seconds
Started Aug 07 06:14:35 PM PDT 24
Finished Aug 07 06:15:41 PM PDT 24
Peak memory 250868 kb
Host smart-de385394-bc4d-484b-8215-0cdea9e54db6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395427231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.395427231
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3109682144
Short name T655
Test name
Test status
Simulation time 1101931839 ps
CPU time 13.84 seconds
Started Aug 07 06:14:35 PM PDT 24
Finished Aug 07 06:14:49 PM PDT 24
Peak memory 250420 kb
Host smart-7e659d26-5fd6-467a-be6c-c931425efac9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109682144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3109682144
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3928020462
Short name T427
Test name
Test status
Simulation time 821937571 ps
CPU time 3.37 seconds
Started Aug 07 06:14:33 PM PDT 24
Finished Aug 07 06:14:37 PM PDT 24
Peak memory 218192 kb
Host smart-7afc3392-1015-40d8-b782-74eed9ef0d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928020462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3928020462
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1888767325
Short name T864
Test name
Test status
Simulation time 685730979 ps
CPU time 12.65 seconds
Started Aug 07 06:14:34 PM PDT 24
Finished Aug 07 06:14:47 PM PDT 24
Peak memory 218904 kb
Host smart-37021911-5664-42c2-91cc-907ed314d7c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888767325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1888767325
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3569949132
Short name T169
Test name
Test status
Simulation time 932791033 ps
CPU time 16.67 seconds
Started Aug 07 06:14:39 PM PDT 24
Finished Aug 07 06:14:55 PM PDT 24
Peak memory 225940 kb
Host smart-ddd03fa8-b8fe-4e87-abc0-082d7be76faa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569949132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3569949132
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.4039734420
Short name T166
Test name
Test status
Simulation time 399902584 ps
CPU time 9.67 seconds
Started Aug 07 06:14:35 PM PDT 24
Finished Aug 07 06:14:44 PM PDT 24
Peak memory 225384 kb
Host smart-7a1955c6-3b8a-4995-a7b5-c7331c8cd4e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039734420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
4039734420
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2487169290
Short name T59
Test name
Test status
Simulation time 1319941784 ps
CPU time 12.19 seconds
Started Aug 07 06:14:36 PM PDT 24
Finished Aug 07 06:14:48 PM PDT 24
Peak memory 224692 kb
Host smart-5b33e281-6d82-4c6f-ab2f-b1fb586cb447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487169290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2487169290
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3038950676
Short name T473
Test name
Test status
Simulation time 214505365 ps
CPU time 10.83 seconds
Started Aug 07 06:14:38 PM PDT 24
Finished Aug 07 06:14:49 PM PDT 24
Peak memory 217648 kb
Host smart-7c9ed295-51be-4ba1-b49b-ce4f287fa991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038950676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3038950676
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3276991308
Short name T486
Test name
Test status
Simulation time 287384435 ps
CPU time 19.41 seconds
Started Aug 07 06:14:35 PM PDT 24
Finished Aug 07 06:14:55 PM PDT 24
Peak memory 250852 kb
Host smart-16174b81-2e06-4dd1-905c-be2d96b059be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276991308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3276991308
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1335373851
Short name T493
Test name
Test status
Simulation time 137254713 ps
CPU time 3.2 seconds
Started Aug 07 06:14:35 PM PDT 24
Finished Aug 07 06:14:38 PM PDT 24
Peak memory 222224 kb
Host smart-1868693c-37b7-47b6-a671-6d6e53fc1326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335373851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1335373851
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.304921424
Short name T348
Test name
Test status
Simulation time 6658252440 ps
CPU time 29.56 seconds
Started Aug 07 06:14:34 PM PDT 24
Finished Aug 07 06:15:04 PM PDT 24
Peak memory 221236 kb
Host smart-6b0c8ebd-6458-4b81-82fa-e7ecfec0c183
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304921424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.304921424
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2738411046
Short name T148
Test name
Test status
Simulation time 105300836677 ps
CPU time 718.2 seconds
Started Aug 07 06:14:39 PM PDT 24
Finished Aug 07 06:26:37 PM PDT 24
Peak memory 480436 kb
Host smart-157b8a0c-6901-4e0f-a825-8f2774d79f9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2738411046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.2738411046
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.4073560956
Short name T594
Test name
Test status
Simulation time 36337825 ps
CPU time 0.81 seconds
Started Aug 07 06:14:34 PM PDT 24
Finished Aug 07 06:14:35 PM PDT 24
Peak memory 208736 kb
Host smart-a03bb543-43d7-4e7c-95c3-86d4f834f393
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073560956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.4073560956
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3223227827
Short name T634
Test name
Test status
Simulation time 25847242 ps
CPU time 0.94 seconds
Started Aug 07 06:14:42 PM PDT 24
Finished Aug 07 06:14:43 PM PDT 24
Peak memory 208824 kb
Host smart-58eddeec-b02f-477d-bf12-aade372b01fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223227827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3223227827
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2738277204
Short name T377
Test name
Test status
Simulation time 334475865 ps
CPU time 13.29 seconds
Started Aug 07 06:14:35 PM PDT 24
Finished Aug 07 06:14:49 PM PDT 24
Peak memory 218112 kb
Host smart-34b0ef68-39c6-4fd6-b5dc-f32affabdd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738277204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2738277204
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2504569243
Short name T22
Test name
Test status
Simulation time 750411927 ps
CPU time 8.26 seconds
Started Aug 07 06:14:36 PM PDT 24
Finished Aug 07 06:14:45 PM PDT 24
Peak memory 217088 kb
Host smart-c9333fe7-34db-4485-a587-ec59d78f1254
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504569243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2504569243
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3089355475
Short name T581
Test name
Test status
Simulation time 1473518837 ps
CPU time 23.7 seconds
Started Aug 07 06:14:35 PM PDT 24
Finished Aug 07 06:14:59 PM PDT 24
Peak memory 218184 kb
Host smart-0ed7358b-232a-437d-8640-47cb77f56256
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089355475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3089355475
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1866289130
Short name T226
Test name
Test status
Simulation time 723722510 ps
CPU time 12.09 seconds
Started Aug 07 06:14:33 PM PDT 24
Finished Aug 07 06:14:46 PM PDT 24
Peak memory 223168 kb
Host smart-ebccb28c-842f-4439-a76e-9e4ef5c0eaea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866289130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1866289130
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1750033039
Short name T756
Test name
Test status
Simulation time 455185439 ps
CPU time 5.03 seconds
Started Aug 07 06:14:37 PM PDT 24
Finished Aug 07 06:14:42 PM PDT 24
Peak memory 217620 kb
Host smart-53a7255a-f9be-4f52-abc5-9f7d39f8f1d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750033039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1750033039
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3140546020
Short name T30
Test name
Test status
Simulation time 1559692036 ps
CPU time 60.19 seconds
Started Aug 07 06:14:33 PM PDT 24
Finished Aug 07 06:15:33 PM PDT 24
Peak memory 267204 kb
Host smart-4aab3ff2-4c19-4ddc-a96d-6fb8925747f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140546020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3140546020
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3380629824
Short name T219
Test name
Test status
Simulation time 1621152087 ps
CPU time 12.68 seconds
Started Aug 07 06:14:35 PM PDT 24
Finished Aug 07 06:14:48 PM PDT 24
Peak memory 246452 kb
Host smart-02707202-9f82-4138-a475-d60de68c3671
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380629824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3380629824
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2439872834
Short name T293
Test name
Test status
Simulation time 30896885 ps
CPU time 1.86 seconds
Started Aug 07 06:14:34 PM PDT 24
Finished Aug 07 06:14:36 PM PDT 24
Peak memory 218212 kb
Host smart-90deb331-830e-44cf-8e2d-e19280964610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439872834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2439872834
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.311749766
Short name T527
Test name
Test status
Simulation time 3709852420 ps
CPU time 16.04 seconds
Started Aug 07 06:14:33 PM PDT 24
Finished Aug 07 06:14:50 PM PDT 24
Peak memory 226080 kb
Host smart-01859573-1795-4eb5-aa68-a6cc8b6cb499
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311749766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.311749766
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2166433924
Short name T264
Test name
Test status
Simulation time 857643481 ps
CPU time 11.94 seconds
Started Aug 07 06:14:37 PM PDT 24
Finished Aug 07 06:14:49 PM PDT 24
Peak memory 225940 kb
Host smart-c0a1fd6a-425e-4db0-a873-5376cf46f25c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166433924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2166433924
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3256733898
Short name T812
Test name
Test status
Simulation time 553085249 ps
CPU time 16.14 seconds
Started Aug 07 06:14:36 PM PDT 24
Finished Aug 07 06:14:52 PM PDT 24
Peak memory 217964 kb
Host smart-f465b20f-f9fd-469a-b71a-7bb153bbd1f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256733898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3256733898
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1153022433
Short name T850
Test name
Test status
Simulation time 1544739633 ps
CPU time 11.2 seconds
Started Aug 07 06:14:36 PM PDT 24
Finished Aug 07 06:14:47 PM PDT 24
Peak memory 225904 kb
Host smart-217de3c0-7992-4a50-8fd3-ef4c40319770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153022433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1153022433
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3333029329
Short name T70
Test name
Test status
Simulation time 59784673 ps
CPU time 3.25 seconds
Started Aug 07 06:14:36 PM PDT 24
Finished Aug 07 06:14:39 PM PDT 24
Peak memory 217376 kb
Host smart-591e9664-58b2-44f3-8b46-a0ccb7705d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333029329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3333029329
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2455878601
Short name T472
Test name
Test status
Simulation time 329577423 ps
CPU time 24.71 seconds
Started Aug 07 06:14:38 PM PDT 24
Finished Aug 07 06:15:03 PM PDT 24
Peak memory 250832 kb
Host smart-4250cbf4-6edc-4687-9acc-6225be9d08dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455878601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2455878601
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2064159905
Short name T41
Test name
Test status
Simulation time 288648352 ps
CPU time 9.8 seconds
Started Aug 07 06:14:34 PM PDT 24
Finished Aug 07 06:14:44 PM PDT 24
Peak memory 250980 kb
Host smart-df07d1b7-0ae9-44f4-9ec3-b5ba11779379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064159905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2064159905
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1235878198
Short name T735
Test name
Test status
Simulation time 13547736 ps
CPU time 1 seconds
Started Aug 07 06:14:33 PM PDT 24
Finished Aug 07 06:14:34 PM PDT 24
Peak memory 217880 kb
Host smart-44916bbb-4c34-4259-87df-c3c458e5ba21
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235878198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1235878198
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1345490373
Short name T178
Test name
Test status
Simulation time 31495821 ps
CPU time 1.06 seconds
Started Aug 07 06:14:46 PM PDT 24
Finished Aug 07 06:14:47 PM PDT 24
Peak memory 208972 kb
Host smart-66328e94-684c-448a-a819-58f3e908e3d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345490373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1345490373
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2208328086
Short name T281
Test name
Test status
Simulation time 1231141353 ps
CPU time 13.17 seconds
Started Aug 07 06:14:46 PM PDT 24
Finished Aug 07 06:15:00 PM PDT 24
Peak memory 218332 kb
Host smart-4a524c66-d355-42d2-8cc9-5027756c3735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208328086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2208328086
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1377996917
Short name T358
Test name
Test status
Simulation time 324615553 ps
CPU time 2.96 seconds
Started Aug 07 06:14:44 PM PDT 24
Finished Aug 07 06:14:47 PM PDT 24
Peak memory 217620 kb
Host smart-07d00d27-ebb7-448f-918a-186258df2f3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377996917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1377996917
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2292319399
Short name T869
Test name
Test status
Simulation time 5100326821 ps
CPU time 31.91 seconds
Started Aug 07 06:14:41 PM PDT 24
Finished Aug 07 06:15:13 PM PDT 24
Peak memory 218996 kb
Host smart-f31daed7-6c94-4694-95fa-8090386862c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292319399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2292319399
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2827005418
Short name T515
Test name
Test status
Simulation time 1845819715 ps
CPU time 7.11 seconds
Started Aug 07 06:14:44 PM PDT 24
Finished Aug 07 06:14:52 PM PDT 24
Peak memory 218304 kb
Host smart-d17eed9d-380c-401b-bd17-f10512f100c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827005418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2827005418
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1274806875
Short name T647
Test name
Test status
Simulation time 485341240 ps
CPU time 2.38 seconds
Started Aug 07 06:14:41 PM PDT 24
Finished Aug 07 06:14:44 PM PDT 24
Peak memory 217556 kb
Host smart-cf3d50fb-b0ed-4705-91b9-f809de70d413
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274806875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1274806875
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3017397459
Short name T783
Test name
Test status
Simulation time 5090114929 ps
CPU time 59.97 seconds
Started Aug 07 06:14:40 PM PDT 24
Finished Aug 07 06:15:40 PM PDT 24
Peak memory 275744 kb
Host smart-7efd5fcb-8530-41a7-ad53-3e07d9530dd8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017397459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3017397459
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1093808533
Short name T103
Test name
Test status
Simulation time 1161968937 ps
CPU time 10.04 seconds
Started Aug 07 06:14:48 PM PDT 24
Finished Aug 07 06:14:58 PM PDT 24
Peak memory 224128 kb
Host smart-b73ea76f-5ee6-4c06-935e-f0b182193329
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093808533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1093808533
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3384146150
Short name T736
Test name
Test status
Simulation time 24337592 ps
CPU time 1.9 seconds
Started Aug 07 06:14:44 PM PDT 24
Finished Aug 07 06:14:46 PM PDT 24
Peak memory 218212 kb
Host smart-207da037-4cb6-416b-b2c4-8535617cd78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384146150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3384146150
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2395835465
Short name T286
Test name
Test status
Simulation time 366717300 ps
CPU time 10.31 seconds
Started Aug 07 06:14:40 PM PDT 24
Finished Aug 07 06:14:51 PM PDT 24
Peak memory 225988 kb
Host smart-a14afee1-0243-4801-b924-412875544078
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395835465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2395835465
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1602189231
Short name T795
Test name
Test status
Simulation time 339385563 ps
CPU time 9.02 seconds
Started Aug 07 06:14:44 PM PDT 24
Finished Aug 07 06:14:54 PM PDT 24
Peak memory 225984 kb
Host smart-8ccd771b-856b-4853-b84d-cd31b8a46a79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602189231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1602189231
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.255727261
Short name T381
Test name
Test status
Simulation time 2595898294 ps
CPU time 13.49 seconds
Started Aug 07 06:14:40 PM PDT 24
Finished Aug 07 06:14:53 PM PDT 24
Peak memory 218236 kb
Host smart-31f58687-449f-4ac0-ad56-7ac888796070
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255727261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.255727261
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3611150460
Short name T737
Test name
Test status
Simulation time 416455542 ps
CPU time 6.15 seconds
Started Aug 07 06:14:43 PM PDT 24
Finished Aug 07 06:14:49 PM PDT 24
Peak memory 224656 kb
Host smart-9b3a799b-3469-47f5-a4fb-14b615ce253b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611150460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3611150460
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.938784262
Short name T369
Test name
Test status
Simulation time 67814918 ps
CPU time 2.37 seconds
Started Aug 07 06:14:41 PM PDT 24
Finished Aug 07 06:14:43 PM PDT 24
Peak memory 214368 kb
Host smart-6d934824-5931-4608-bb1f-27ffc9a47b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938784262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.938784262
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.4060371452
Short name T229
Test name
Test status
Simulation time 207234413 ps
CPU time 21.23 seconds
Started Aug 07 06:14:42 PM PDT 24
Finished Aug 07 06:15:04 PM PDT 24
Peak memory 250772 kb
Host smart-a91f07f8-6055-4c79-b513-dc694db4b486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060371452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.4060371452
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3356241907
Short name T598
Test name
Test status
Simulation time 145134289 ps
CPU time 8.17 seconds
Started Aug 07 06:14:43 PM PDT 24
Finished Aug 07 06:14:52 PM PDT 24
Peak memory 250860 kb
Host smart-06527095-aedb-4056-9934-01a12da2e311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356241907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3356241907
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2733431832
Short name T809
Test name
Test status
Simulation time 20117819545 ps
CPU time 156.37 seconds
Started Aug 07 06:14:43 PM PDT 24
Finished Aug 07 06:17:20 PM PDT 24
Peak memory 250888 kb
Host smart-d077265a-2c56-4b5b-b3e6-ad8e4ed2dfe9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733431832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2733431832
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3967014436
Short name T275
Test name
Test status
Simulation time 32755986 ps
CPU time 1.13 seconds
Started Aug 07 06:14:41 PM PDT 24
Finished Aug 07 06:14:42 PM PDT 24
Peak memory 211964 kb
Host smart-699f7ab1-5f5a-4539-b063-1f7559f31e9f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967014436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3967014436
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1524952831
Short name T671
Test name
Test status
Simulation time 50787043 ps
CPU time 1.15 seconds
Started Aug 07 06:14:47 PM PDT 24
Finished Aug 07 06:14:48 PM PDT 24
Peak memory 208864 kb
Host smart-45b824a3-6278-4cb6-bba4-6a303d21f867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524952831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1524952831
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1521074092
Short name T830
Test name
Test status
Simulation time 525377998 ps
CPU time 15.17 seconds
Started Aug 07 06:14:44 PM PDT 24
Finished Aug 07 06:14:59 PM PDT 24
Peak memory 218224 kb
Host smart-80cbe65c-e588-4a3f-87e2-d1a23e2ae183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521074092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1521074092
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.329525317
Short name T608
Test name
Test status
Simulation time 155297228 ps
CPU time 4.22 seconds
Started Aug 07 06:14:47 PM PDT 24
Finished Aug 07 06:14:52 PM PDT 24
Peak memory 216912 kb
Host smart-41457240-086e-4ca4-bced-e3774ccf845e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329525317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.329525317
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1830898054
Short name T340
Test name
Test status
Simulation time 5610402785 ps
CPU time 22.55 seconds
Started Aug 07 06:14:44 PM PDT 24
Finished Aug 07 06:15:07 PM PDT 24
Peak memory 218768 kb
Host smart-28553436-602d-40ae-b1bf-8e89e7922057
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830898054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1830898054
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.361476882
Short name T396
Test name
Test status
Simulation time 999241190 ps
CPU time 15.53 seconds
Started Aug 07 06:14:43 PM PDT 24
Finished Aug 07 06:14:59 PM PDT 24
Peak memory 225128 kb
Host smart-07b96d31-d049-46f0-8ae9-33e956b273ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361476882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.361476882
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2816048753
Short name T227
Test name
Test status
Simulation time 324413199 ps
CPU time 9.95 seconds
Started Aug 07 06:14:43 PM PDT 24
Finished Aug 07 06:14:53 PM PDT 24
Peak memory 217480 kb
Host smart-c9ec98b9-346e-4715-9733-98bf4d9b6350
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816048753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2816048753
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1464176567
Short name T326
Test name
Test status
Simulation time 4156253074 ps
CPU time 26.87 seconds
Started Aug 07 06:14:44 PM PDT 24
Finished Aug 07 06:15:12 PM PDT 24
Peak memory 267276 kb
Host smart-d9066681-e0c3-47e0-b58d-329154ff4248
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464176567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1464176567
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1887095664
Short name T690
Test name
Test status
Simulation time 354104095 ps
CPU time 7.06 seconds
Started Aug 07 06:14:43 PM PDT 24
Finished Aug 07 06:14:51 PM PDT 24
Peak memory 222552 kb
Host smart-f24bd469-8e8e-4424-be10-af54651266b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887095664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1887095664
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.650640351
Short name T576
Test name
Test status
Simulation time 364655501 ps
CPU time 3.95 seconds
Started Aug 07 06:14:42 PM PDT 24
Finished Aug 07 06:14:46 PM PDT 24
Peak memory 222348 kb
Host smart-060f72b3-ec0b-435e-ada8-0714a1c24f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650640351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.650640351
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.614442249
Short name T454
Test name
Test status
Simulation time 508105166 ps
CPU time 9.97 seconds
Started Aug 07 06:14:44 PM PDT 24
Finished Aug 07 06:14:54 PM PDT 24
Peak memory 218308 kb
Host smart-a5689651-4cd6-4493-959b-e2af53f5311a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614442249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.614442249
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1581999118
Short name T481
Test name
Test status
Simulation time 307459973 ps
CPU time 13.66 seconds
Started Aug 07 06:14:43 PM PDT 24
Finished Aug 07 06:14:56 PM PDT 24
Peak memory 225948 kb
Host smart-0c3b0aa6-dafe-4352-9211-49e2e5a30bbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581999118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1581999118
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2302546690
Short name T853
Test name
Test status
Simulation time 433139457 ps
CPU time 8.31 seconds
Started Aug 07 06:14:48 PM PDT 24
Finished Aug 07 06:14:56 PM PDT 24
Peak memory 224748 kb
Host smart-3b59d341-84bb-4432-a7fa-9c429dc3b55a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302546690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2302546690
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1370515712
Short name T287
Test name
Test status
Simulation time 272087252 ps
CPU time 11.87 seconds
Started Aug 07 06:14:47 PM PDT 24
Finished Aug 07 06:14:59 PM PDT 24
Peak memory 226064 kb
Host smart-6becd96a-ff69-4209-878b-267eaa03b73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370515712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1370515712
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3844095603
Short name T760
Test name
Test status
Simulation time 135514534 ps
CPU time 2.2 seconds
Started Aug 07 06:14:45 PM PDT 24
Finished Aug 07 06:14:47 PM PDT 24
Peak memory 214292 kb
Host smart-2fdaaaec-0eef-4f3f-a064-58eab312fdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844095603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3844095603
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3958781255
Short name T240
Test name
Test status
Simulation time 267118216 ps
CPU time 24.72 seconds
Started Aug 07 06:14:44 PM PDT 24
Finished Aug 07 06:15:09 PM PDT 24
Peak memory 250812 kb
Host smart-f935ce2c-f7da-4365-b950-3b86024da84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958781255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3958781255
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.4074944023
Short name T235
Test name
Test status
Simulation time 135477960 ps
CPU time 3.76 seconds
Started Aug 07 06:14:45 PM PDT 24
Finished Aug 07 06:14:49 PM PDT 24
Peak memory 226268 kb
Host smart-9050f911-df6c-4a1c-bc6f-60977b149160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074944023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.4074944023
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.4101860201
Short name T490
Test name
Test status
Simulation time 32119186 ps
CPU time 0.84 seconds
Started Aug 07 06:14:41 PM PDT 24
Finished Aug 07 06:14:41 PM PDT 24
Peak memory 208860 kb
Host smart-93709aa0-2182-4530-8db7-2746be278539
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101860201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.4101860201
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2554248939
Short name T489
Test name
Test status
Simulation time 21733026 ps
CPU time 1.02 seconds
Started Aug 07 06:14:51 PM PDT 24
Finished Aug 07 06:14:52 PM PDT 24
Peak memory 209052 kb
Host smart-52db79b6-9496-4e65-bf0f-f7b78c1146de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554248939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2554248939
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.911051133
Short name T484
Test name
Test status
Simulation time 2171869505 ps
CPU time 23.29 seconds
Started Aug 07 06:14:43 PM PDT 24
Finished Aug 07 06:15:06 PM PDT 24
Peak memory 218288 kb
Host smart-d8bab868-f534-4195-b606-a53119fb2bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911051133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.911051133
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3581475053
Short name T435
Test name
Test status
Simulation time 331825215 ps
CPU time 1.89 seconds
Started Aug 07 06:14:49 PM PDT 24
Finished Aug 07 06:14:51 PM PDT 24
Peak memory 216980 kb
Host smart-cd88f68a-5d87-444f-a93b-1b4aae133033
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581475053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3581475053
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.537052368
Short name T334
Test name
Test status
Simulation time 31956875385 ps
CPU time 79.73 seconds
Started Aug 07 06:14:50 PM PDT 24
Finished Aug 07 06:16:10 PM PDT 24
Peak memory 218860 kb
Host smart-06dc7265-5fa2-451a-9c64-8de1dee46ef4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537052368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.537052368
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1538680455
Short name T152
Test name
Test status
Simulation time 1744945505 ps
CPU time 7.27 seconds
Started Aug 07 06:14:49 PM PDT 24
Finished Aug 07 06:14:57 PM PDT 24
Peak memory 223156 kb
Host smart-60e48f24-4336-400e-97da-b02b819f2050
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538680455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1538680455
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2035658029
Short name T638
Test name
Test status
Simulation time 989235075 ps
CPU time 5.55 seconds
Started Aug 07 06:14:48 PM PDT 24
Finished Aug 07 06:14:54 PM PDT 24
Peak memory 217712 kb
Host smart-c6ea38f0-0d1d-4184-950b-93670dba8a21
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035658029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2035658029
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2149188001
Short name T1
Test name
Test status
Simulation time 1616722145 ps
CPU time 74.27 seconds
Started Aug 07 06:14:50 PM PDT 24
Finished Aug 07 06:16:04 PM PDT 24
Peak memory 267160 kb
Host smart-6c457409-97df-4336-9e4f-332558cbbc58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149188001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2149188001
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1218664180
Short name T689
Test name
Test status
Simulation time 3720609538 ps
CPU time 13.69 seconds
Started Aug 07 06:14:53 PM PDT 24
Finished Aug 07 06:15:06 PM PDT 24
Peak memory 250448 kb
Host smart-ef71931a-232f-4af8-99cb-8eae5252fab5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218664180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1218664180
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.370152158
Short name T424
Test name
Test status
Simulation time 272434827 ps
CPU time 2.5 seconds
Started Aug 07 06:14:47 PM PDT 24
Finished Aug 07 06:14:49 PM PDT 24
Peak memory 218204 kb
Host smart-0c8317f1-7d48-4c16-84c2-836ae104ac86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370152158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.370152158
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.307374543
Short name T482
Test name
Test status
Simulation time 306706687 ps
CPU time 13.24 seconds
Started Aug 07 06:14:52 PM PDT 24
Finished Aug 07 06:15:05 PM PDT 24
Peak memory 218832 kb
Host smart-4f9a708f-a594-4514-9e92-ecbfaa0a437a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307374543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.307374543
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1035893000
Short name T816
Test name
Test status
Simulation time 1332774232 ps
CPU time 11.84 seconds
Started Aug 07 06:14:50 PM PDT 24
Finished Aug 07 06:15:02 PM PDT 24
Peak memory 225944 kb
Host smart-298473e6-3d24-420d-8a03-6b0fe0a3dc2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035893000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1035893000
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3801330589
Short name T372
Test name
Test status
Simulation time 1167329234 ps
CPU time 8.77 seconds
Started Aug 07 06:14:51 PM PDT 24
Finished Aug 07 06:15:00 PM PDT 24
Peak memory 218124 kb
Host smart-9a035797-24d3-4e3c-941c-d164b5ebfe0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801330589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3801330589
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.4027213510
Short name T359
Test name
Test status
Simulation time 1161028104 ps
CPU time 11.65 seconds
Started Aug 07 06:14:44 PM PDT 24
Finished Aug 07 06:14:56 PM PDT 24
Peak memory 225916 kb
Host smart-3948e1e2-4723-4ed3-95cc-830e6537adff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027213510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.4027213510
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3357671716
Short name T82
Test name
Test status
Simulation time 88034158 ps
CPU time 2.32 seconds
Started Aug 07 06:14:47 PM PDT 24
Finished Aug 07 06:14:49 PM PDT 24
Peak memory 214200 kb
Host smart-63d9fd3f-8efa-4c4f-aa9d-13d2c6b20204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357671716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3357671716
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2580696670
Short name T716
Test name
Test status
Simulation time 1154907340 ps
CPU time 22.28 seconds
Started Aug 07 06:14:48 PM PDT 24
Finished Aug 07 06:15:10 PM PDT 24
Peak memory 250884 kb
Host smart-3caf6eeb-d896-46eb-88c8-f3dc42b4452d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580696670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2580696670
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3465548171
Short name T623
Test name
Test status
Simulation time 58357603 ps
CPU time 6.84 seconds
Started Aug 07 06:14:44 PM PDT 24
Finished Aug 07 06:14:51 PM PDT 24
Peak memory 250316 kb
Host smart-8ebe735b-d5bc-433c-8a0a-b8f989d9827c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465548171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3465548171
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1262583037
Short name T847
Test name
Test status
Simulation time 2570560305 ps
CPU time 111.01 seconds
Started Aug 07 06:14:51 PM PDT 24
Finished Aug 07 06:16:42 PM PDT 24
Peak memory 273752 kb
Host smart-dc369f40-60ef-4416-bdbb-5ad1af7d1957
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262583037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1262583037
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2205199911
Short name T144
Test name
Test status
Simulation time 149241696519 ps
CPU time 422.07 seconds
Started Aug 07 06:14:51 PM PDT 24
Finished Aug 07 06:21:54 PM PDT 24
Peak memory 251028 kb
Host smart-dcdf0abc-81ca-4e9b-8eef-40c381c20dc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2205199911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2205199911
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3446864422
Short name T238
Test name
Test status
Simulation time 76226869 ps
CPU time 1.05 seconds
Started Aug 07 06:14:40 PM PDT 24
Finished Aug 07 06:14:41 PM PDT 24
Peak memory 211976 kb
Host smart-63618bda-a1b8-4a1f-940c-498698153be9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446864422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3446864422
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2354176476
Short name T242
Test name
Test status
Simulation time 16648195 ps
CPU time 0.86 seconds
Started Aug 07 06:13:39 PM PDT 24
Finished Aug 07 06:13:40 PM PDT 24
Peak memory 208848 kb
Host smart-150fe2a9-fbaf-44ba-b796-c72ee5aa3bd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354176476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2354176476
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2918737988
Short name T477
Test name
Test status
Simulation time 17493599 ps
CPU time 0.92 seconds
Started Aug 07 06:13:28 PM PDT 24
Finished Aug 07 06:13:29 PM PDT 24
Peak memory 208764 kb
Host smart-13897d65-6f32-4b44-bcfe-9d8f238b070e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918737988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2918737988
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1138691632
Short name T51
Test name
Test status
Simulation time 2832472547 ps
CPU time 8.55 seconds
Started Aug 07 06:13:29 PM PDT 24
Finished Aug 07 06:13:37 PM PDT 24
Peak memory 226104 kb
Host smart-37b1ddec-1554-4c31-b5e9-4da35b5d3ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138691632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1138691632
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.228852485
Short name T580
Test name
Test status
Simulation time 299377530 ps
CPU time 4.24 seconds
Started Aug 07 06:13:31 PM PDT 24
Finished Aug 07 06:13:36 PM PDT 24
Peak memory 217136 kb
Host smart-6adf327f-e73c-4b25-9a60-de2ae9deca1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228852485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.228852485
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2993685439
Short name T34
Test name
Test status
Simulation time 2191563970 ps
CPU time 37.09 seconds
Started Aug 07 06:13:30 PM PDT 24
Finished Aug 07 06:14:07 PM PDT 24
Peak memory 218860 kb
Host smart-e94c0c15-16c9-48a0-83cc-615a249d610d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993685439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2993685439
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.878474642
Short name T4
Test name
Test status
Simulation time 5502935168 ps
CPU time 13.39 seconds
Started Aug 07 06:13:28 PM PDT 24
Finished Aug 07 06:13:41 PM PDT 24
Peak memory 217636 kb
Host smart-d87e488d-b284-463a-ae9c-a57028e924b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878474642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.878474642
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2101103882
Short name T860
Test name
Test status
Simulation time 553142146 ps
CPU time 8.64 seconds
Started Aug 07 06:13:29 PM PDT 24
Finished Aug 07 06:13:38 PM PDT 24
Peak memory 222912 kb
Host smart-b19ce1c2-5b41-4215-85ed-643e368662d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101103882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2101103882
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.4093193171
Short name T539
Test name
Test status
Simulation time 1560762730 ps
CPU time 13.82 seconds
Started Aug 07 06:13:27 PM PDT 24
Finished Aug 07 06:13:41 PM PDT 24
Peak memory 217584 kb
Host smart-767ac8ef-a67f-4d20-a340-7970ea08d72e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093193171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.4093193171
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.4243763250
Short name T843
Test name
Test status
Simulation time 255909532 ps
CPU time 5.18 seconds
Started Aug 07 06:13:30 PM PDT 24
Finished Aug 07 06:13:35 PM PDT 24
Peak memory 217580 kb
Host smart-8a95113d-da31-47c3-821e-be6617f5b7e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243763250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
4243763250
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.857397529
Short name T625
Test name
Test status
Simulation time 2669101142 ps
CPU time 66.4 seconds
Started Aug 07 06:13:32 PM PDT 24
Finished Aug 07 06:14:39 PM PDT 24
Peak memory 267256 kb
Host smart-56aa1952-0e44-45a7-a910-5d2a7035b6b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857397529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.857397529
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2450705136
Short name T857
Test name
Test status
Simulation time 3235801109 ps
CPU time 18.45 seconds
Started Aug 07 06:13:32 PM PDT 24
Finished Aug 07 06:13:51 PM PDT 24
Peak memory 247628 kb
Host smart-e7e2164c-93f0-4e61-a545-7d45021ad6e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450705136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2450705136
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3980346902
Short name T355
Test name
Test status
Simulation time 26022566 ps
CPU time 1.46 seconds
Started Aug 07 06:13:29 PM PDT 24
Finished Aug 07 06:13:31 PM PDT 24
Peak memory 221648 kb
Host smart-a7b2efca-cae3-4788-bf55-d47171ca97de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980346902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3980346902
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2728943619
Short name T529
Test name
Test status
Simulation time 1387579861 ps
CPU time 12.88 seconds
Started Aug 07 06:13:31 PM PDT 24
Finished Aug 07 06:13:44 PM PDT 24
Peak memory 214724 kb
Host smart-8be6ae49-c25f-43af-8936-ade8fee5b6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728943619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2728943619
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2842681351
Short name T239
Test name
Test status
Simulation time 515502919 ps
CPU time 10.5 seconds
Started Aug 07 06:13:31 PM PDT 24
Finished Aug 07 06:13:42 PM PDT 24
Peak memory 226032 kb
Host smart-501757c1-dd9f-4388-b2f1-16492441f596
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842681351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2842681351
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3513315258
Short name T39
Test name
Test status
Simulation time 334961632 ps
CPU time 12.26 seconds
Started Aug 07 06:13:31 PM PDT 24
Finished Aug 07 06:13:43 PM PDT 24
Peak memory 225952 kb
Host smart-ce7d4df7-176f-4004-a7be-6646a7ccbf13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513315258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3513315258
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1818072086
Short name T223
Test name
Test status
Simulation time 892641741 ps
CPU time 11.53 seconds
Started Aug 07 06:13:30 PM PDT 24
Finished Aug 07 06:13:41 PM PDT 24
Peak memory 225344 kb
Host smart-2c591fe8-8b3e-47e3-82c6-5a5889863e23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818072086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
818072086
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3450136907
Short name T60
Test name
Test status
Simulation time 248484126 ps
CPU time 7.85 seconds
Started Aug 07 06:13:30 PM PDT 24
Finished Aug 07 06:13:38 PM PDT 24
Peak memory 218296 kb
Host smart-14ebe85d-6145-4a31-bfd7-866718b4b988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450136907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3450136907
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3106746921
Short name T507
Test name
Test status
Simulation time 829609970 ps
CPU time 5.32 seconds
Started Aug 07 06:13:32 PM PDT 24
Finished Aug 07 06:13:37 PM PDT 24
Peak memory 217652 kb
Host smart-4c6fd295-42b0-49d7-8c0a-d4f6c6277308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106746921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3106746921
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.407942313
Short name T467
Test name
Test status
Simulation time 308712941 ps
CPU time 30.03 seconds
Started Aug 07 06:13:30 PM PDT 24
Finished Aug 07 06:14:00 PM PDT 24
Peak memory 250840 kb
Host smart-d5a145fe-a5a6-4f69-b534-e17526ff13c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407942313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.407942313
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.4018608719
Short name T572
Test name
Test status
Simulation time 483575552 ps
CPU time 8.33 seconds
Started Aug 07 06:13:27 PM PDT 24
Finished Aug 07 06:13:35 PM PDT 24
Peak memory 250812 kb
Host smart-e46a1988-f8a7-4df2-a8bd-bf4d89958571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018608719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.4018608719
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3016325455
Short name T499
Test name
Test status
Simulation time 12024430969 ps
CPU time 86.88 seconds
Started Aug 07 06:13:30 PM PDT 24
Finished Aug 07 06:14:57 PM PDT 24
Peak memory 283192 kb
Host smart-7d29500c-0396-4d1c-bd37-22076af75e6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016325455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3016325455
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2529307471
Short name T858
Test name
Test status
Simulation time 59212817731 ps
CPU time 291.45 seconds
Started Aug 07 06:13:32 PM PDT 24
Finished Aug 07 06:18:24 PM PDT 24
Peak memory 283812 kb
Host smart-e8ae7cff-194c-4e09-bf30-0507cbe2882d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2529307471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.2529307471
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3593312946
Short name T599
Test name
Test status
Simulation time 24285477 ps
CPU time 0.75 seconds
Started Aug 07 06:13:29 PM PDT 24
Finished Aug 07 06:13:30 PM PDT 24
Peak memory 208652 kb
Host smart-d1de2dc3-f89c-40fb-98a9-cb4e713b6248
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593312946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3593312946
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.250089267
Short name T270
Test name
Test status
Simulation time 18265542 ps
CPU time 1 seconds
Started Aug 07 06:14:49 PM PDT 24
Finished Aug 07 06:14:50 PM PDT 24
Peak memory 208904 kb
Host smart-794bce5d-80cf-448b-bafd-448f4166e155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250089267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.250089267
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.4219725964
Short name T645
Test name
Test status
Simulation time 2018374989 ps
CPU time 20.97 seconds
Started Aug 07 06:14:50 PM PDT 24
Finished Aug 07 06:15:11 PM PDT 24
Peak memory 218216 kb
Host smart-7755e804-925c-48f0-85bb-c44ad4795f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219725964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.4219725964
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.340191680
Short name T379
Test name
Test status
Simulation time 5027368224 ps
CPU time 16.4 seconds
Started Aug 07 06:14:56 PM PDT 24
Finished Aug 07 06:15:13 PM PDT 24
Peak memory 217668 kb
Host smart-64edb438-a31f-4c15-8b0b-848f3716e596
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340191680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.340191680
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3069745157
Short name T423
Test name
Test status
Simulation time 64732107 ps
CPU time 2.65 seconds
Started Aug 07 06:14:53 PM PDT 24
Finished Aug 07 06:14:55 PM PDT 24
Peak memory 218200 kb
Host smart-80125679-ea42-4cb8-ac59-12d3bf3a35c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069745157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3069745157
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.409663859
Short name T66
Test name
Test status
Simulation time 561854514 ps
CPU time 12.52 seconds
Started Aug 07 06:14:50 PM PDT 24
Finished Aug 07 06:15:03 PM PDT 24
Peak memory 219820 kb
Host smart-5acf62ed-87bc-4fc9-8391-06c03eb97c1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409663859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.409663859
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1464708638
Short name T327
Test name
Test status
Simulation time 569910670 ps
CPU time 10.8 seconds
Started Aug 07 06:14:53 PM PDT 24
Finished Aug 07 06:15:04 PM PDT 24
Peak memory 226132 kb
Host smart-0182baa0-1c38-4c74-a877-257f5150cc16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464708638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1464708638
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3224717436
Short name T300
Test name
Test status
Simulation time 1962729324 ps
CPU time 10.15 seconds
Started Aug 07 06:14:52 PM PDT 24
Finished Aug 07 06:15:02 PM PDT 24
Peak memory 218168 kb
Host smart-243ce8ed-c789-4456-b0c3-d9bfb0e07ad3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224717436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3224717436
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3764051598
Short name T560
Test name
Test status
Simulation time 1247567258 ps
CPU time 12.3 seconds
Started Aug 07 06:14:56 PM PDT 24
Finished Aug 07 06:15:08 PM PDT 24
Peak memory 226012 kb
Host smart-1b1fcb5e-92a3-4f91-8978-9b6bed5d37cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764051598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3764051598
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1358369557
Short name T83
Test name
Test status
Simulation time 290018912 ps
CPU time 4.78 seconds
Started Aug 07 06:14:50 PM PDT 24
Finished Aug 07 06:14:55 PM PDT 24
Peak memory 217736 kb
Host smart-f5b5d77e-af8f-46dd-8174-55e3ee44ef93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358369557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1358369557
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2100536119
Short name T446
Test name
Test status
Simulation time 214344549 ps
CPU time 18.62 seconds
Started Aug 07 06:14:48 PM PDT 24
Finished Aug 07 06:15:07 PM PDT 24
Peak memory 245532 kb
Host smart-99685bd2-6a01-4245-bab5-3d4af79caf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100536119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2100536119
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1827657377
Short name T862
Test name
Test status
Simulation time 452378440 ps
CPU time 7.18 seconds
Started Aug 07 06:14:53 PM PDT 24
Finished Aug 07 06:15:01 PM PDT 24
Peak memory 250276 kb
Host smart-70eb6749-2a1a-44d1-9826-8bc6b1aa2eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827657377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1827657377
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1842612074
Short name T419
Test name
Test status
Simulation time 602164516 ps
CPU time 32 seconds
Started Aug 07 06:14:53 PM PDT 24
Finished Aug 07 06:15:25 PM PDT 24
Peak memory 250880 kb
Host smart-57f36943-c1b0-49d7-8b44-a3e0fc168167
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842612074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1842612074
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.172390991
Short name T867
Test name
Test status
Simulation time 14985510 ps
CPU time 0.94 seconds
Started Aug 07 06:14:53 PM PDT 24
Finished Aug 07 06:14:54 PM PDT 24
Peak memory 211856 kb
Host smart-07e20cd8-7acc-4600-8678-e045edd148d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172390991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.172390991
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3498740670
Short name T725
Test name
Test status
Simulation time 67685957 ps
CPU time 1.13 seconds
Started Aug 07 06:14:54 PM PDT 24
Finished Aug 07 06:14:56 PM PDT 24
Peak memory 208928 kb
Host smart-13a68601-191b-44e5-b2a7-e604221f254b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498740670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3498740670
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3436524066
Short name T588
Test name
Test status
Simulation time 474553274 ps
CPU time 11.93 seconds
Started Aug 07 06:14:49 PM PDT 24
Finished Aug 07 06:15:01 PM PDT 24
Peak memory 218156 kb
Host smart-7a0ecc25-0140-4021-9278-aaed8f716aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436524066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3436524066
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3933443353
Short name T185
Test name
Test status
Simulation time 4337651273 ps
CPU time 10.17 seconds
Started Aug 07 06:14:54 PM PDT 24
Finished Aug 07 06:15:04 PM PDT 24
Peak memory 217532 kb
Host smart-3f36e5c3-257a-4f24-bc61-a30d572ec083
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933443353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3933443353
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2083428133
Short name T577
Test name
Test status
Simulation time 129377412 ps
CPU time 2.08 seconds
Started Aug 07 06:14:49 PM PDT 24
Finished Aug 07 06:14:51 PM PDT 24
Peak memory 218200 kb
Host smart-af627d3b-2507-484a-8e97-dd3b6fd80b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083428133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2083428133
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2901397840
Short name T563
Test name
Test status
Simulation time 2262527138 ps
CPU time 25.36 seconds
Started Aug 07 06:14:48 PM PDT 24
Finished Aug 07 06:15:13 PM PDT 24
Peak memory 218972 kb
Host smart-d93928af-7e56-4870-a477-839b42b25a7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901397840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2901397840
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2707580548
Short name T380
Test name
Test status
Simulation time 1424335957 ps
CPU time 15.64 seconds
Started Aug 07 06:14:53 PM PDT 24
Finished Aug 07 06:15:09 PM PDT 24
Peak memory 225964 kb
Host smart-4b103d7e-9c1e-4d46-ab09-da21901ccd4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707580548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2707580548
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1067278215
Short name T786
Test name
Test status
Simulation time 3318736160 ps
CPU time 10.15 seconds
Started Aug 07 06:14:54 PM PDT 24
Finished Aug 07 06:15:04 PM PDT 24
Peak memory 218256 kb
Host smart-2dd91b94-2d32-410b-a966-a8c48ef4f88d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067278215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1067278215
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2099840265
Short name T360
Test name
Test status
Simulation time 357853801 ps
CPU time 13.59 seconds
Started Aug 07 06:14:50 PM PDT 24
Finished Aug 07 06:15:04 PM PDT 24
Peak memory 225120 kb
Host smart-f09e11cd-0861-4ccf-8ce7-61bedf6ace99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099840265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2099840265
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3778314900
Short name T413
Test name
Test status
Simulation time 31543338 ps
CPU time 1.32 seconds
Started Aug 07 06:14:51 PM PDT 24
Finished Aug 07 06:14:52 PM PDT 24
Peak memory 213772 kb
Host smart-1b3c59c6-dd98-41df-a912-b74c40eb1945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778314900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3778314900
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1116045306
Short name T311
Test name
Test status
Simulation time 243560975 ps
CPU time 26.81 seconds
Started Aug 07 06:14:53 PM PDT 24
Finished Aug 07 06:15:20 PM PDT 24
Peak memory 250928 kb
Host smart-e50eb91c-291d-4e57-add6-c4c80cf55b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116045306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1116045306
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.4263637457
Short name T149
Test name
Test status
Simulation time 689051631 ps
CPU time 6.92 seconds
Started Aug 07 06:14:52 PM PDT 24
Finished Aug 07 06:14:59 PM PDT 24
Peak memory 250360 kb
Host smart-939325df-006f-4428-a7ad-0e8aff3b7672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263637457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.4263637457
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.299227371
Short name T342
Test name
Test status
Simulation time 12075594354 ps
CPU time 264.96 seconds
Started Aug 07 06:14:52 PM PDT 24
Finished Aug 07 06:19:18 PM PDT 24
Peak memory 234272 kb
Host smart-199ff666-ace6-4a10-b909-0860466e739a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299227371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.299227371
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.96574537
Short name T731
Test name
Test status
Simulation time 29390711 ps
CPU time 0.9 seconds
Started Aug 07 06:14:50 PM PDT 24
Finished Aug 07 06:14:51 PM PDT 24
Peak memory 209164 kb
Host smart-69f496e2-c76c-4222-b874-a83a386b3608
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96574537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctr
l_volatile_unlock_smoke.96574537
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1092017167
Short name T792
Test name
Test status
Simulation time 74843354 ps
CPU time 1.01 seconds
Started Aug 07 06:14:59 PM PDT 24
Finished Aug 07 06:15:00 PM PDT 24
Peak memory 208892 kb
Host smart-dbab60af-0672-41b2-9ae0-44a982af66dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092017167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1092017167
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2234270858
Short name T37
Test name
Test status
Simulation time 166459003 ps
CPU time 8.23 seconds
Started Aug 07 06:14:56 PM PDT 24
Finished Aug 07 06:15:05 PM PDT 24
Peak memory 225984 kb
Host smart-a1701095-cc1d-4bb2-b7d8-88e19bae690d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234270858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2234270858
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1211178159
Short name T526
Test name
Test status
Simulation time 1821176642 ps
CPU time 3.65 seconds
Started Aug 07 06:15:04 PM PDT 24
Finished Aug 07 06:15:08 PM PDT 24
Peak memory 217160 kb
Host smart-022addba-fc69-4826-a2fe-3c05678dd0ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211178159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1211178159
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2927238331
Short name T283
Test name
Test status
Simulation time 178585723 ps
CPU time 3.44 seconds
Started Aug 07 06:14:49 PM PDT 24
Finished Aug 07 06:14:52 PM PDT 24
Peak memory 218228 kb
Host smart-dfea069e-d262-4029-a9c5-f7272bca5c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927238331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2927238331
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3957190626
Short name T403
Test name
Test status
Simulation time 351480409 ps
CPU time 12.03 seconds
Started Aug 07 06:14:56 PM PDT 24
Finished Aug 07 06:15:09 PM PDT 24
Peak memory 218996 kb
Host smart-0d2647bf-abae-459b-bc0c-00946f789430
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957190626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3957190626
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.4004672346
Short name T260
Test name
Test status
Simulation time 2221334491 ps
CPU time 10.12 seconds
Started Aug 07 06:15:00 PM PDT 24
Finished Aug 07 06:15:10 PM PDT 24
Peak memory 225964 kb
Host smart-ee7ee12b-a5d3-4194-8e4e-e2d0bb157ae9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004672346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.4004672346
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.310173755
Short name T288
Test name
Test status
Simulation time 272874424 ps
CPU time 7.73 seconds
Started Aug 07 06:15:00 PM PDT 24
Finished Aug 07 06:15:08 PM PDT 24
Peak memory 218140 kb
Host smart-220db6ad-072e-45a4-a529-9d587b2195e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310173755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.310173755
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3761993506
Short name T273
Test name
Test status
Simulation time 761741618 ps
CPU time 9.43 seconds
Started Aug 07 06:14:54 PM PDT 24
Finished Aug 07 06:15:04 PM PDT 24
Peak memory 226012 kb
Host smart-efa5f1f0-eb5d-4008-b6d2-9ffe69755eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761993506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3761993506
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1662353763
Short name T459
Test name
Test status
Simulation time 38092342 ps
CPU time 2.64 seconds
Started Aug 07 06:14:54 PM PDT 24
Finished Aug 07 06:14:56 PM PDT 24
Peak memory 214712 kb
Host smart-e6ca086e-9171-448a-b52f-5999d65f5d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662353763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1662353763
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.4241741263
Short name T876
Test name
Test status
Simulation time 442539286 ps
CPU time 25.09 seconds
Started Aug 07 06:14:53 PM PDT 24
Finished Aug 07 06:15:18 PM PDT 24
Peak memory 251104 kb
Host smart-9fc729d8-f444-4478-94ef-8b199e206bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241741263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.4241741263
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.226171644
Short name T775
Test name
Test status
Simulation time 57713567 ps
CPU time 6.27 seconds
Started Aug 07 06:14:55 PM PDT 24
Finished Aug 07 06:15:01 PM PDT 24
Peak memory 246592 kb
Host smart-3caa2d00-7d46-4bd4-b2ac-227f3161fe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226171644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.226171644
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2489309230
Short name T710
Test name
Test status
Simulation time 6158194619 ps
CPU time 64.61 seconds
Started Aug 07 06:15:01 PM PDT 24
Finished Aug 07 06:16:06 PM PDT 24
Peak memory 250380 kb
Host smart-3ba21b77-5e89-481a-97e6-6ee57c56e765
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489309230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2489309230
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3790015710
Short name T391
Test name
Test status
Simulation time 13704634 ps
CPU time 1.1 seconds
Started Aug 07 06:14:55 PM PDT 24
Finished Aug 07 06:14:56 PM PDT 24
Peak memory 217892 kb
Host smart-9003d0db-2e7d-4230-8c4c-dd6027d72c3b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790015710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3790015710
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2752088893
Short name T72
Test name
Test status
Simulation time 156963190 ps
CPU time 1.24 seconds
Started Aug 07 06:14:57 PM PDT 24
Finished Aug 07 06:14:58 PM PDT 24
Peak memory 209096 kb
Host smart-921c487c-1e30-442e-acc1-2bd6dbcb521f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752088893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2752088893
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1955733077
Short name T811
Test name
Test status
Simulation time 457396709 ps
CPU time 9.53 seconds
Started Aug 07 06:15:00 PM PDT 24
Finished Aug 07 06:15:09 PM PDT 24
Peak memory 218124 kb
Host smart-66f81db1-4b4e-462f-a220-3fc31c3c9e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955733077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1955733077
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3241759710
Short name T801
Test name
Test status
Simulation time 1905807157 ps
CPU time 13.53 seconds
Started Aug 07 06:14:56 PM PDT 24
Finished Aug 07 06:15:10 PM PDT 24
Peak memory 217404 kb
Host smart-cb4f8816-6281-4294-803f-5e9fca42a615
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241759710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3241759710
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3209586212
Short name T181
Test name
Test status
Simulation time 82795565 ps
CPU time 3.12 seconds
Started Aug 07 06:15:01 PM PDT 24
Finished Aug 07 06:15:04 PM PDT 24
Peak memory 218100 kb
Host smart-de25f5fa-759d-4d03-a9e3-23bb580312d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209586212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3209586212
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3304952379
Short name T284
Test name
Test status
Simulation time 1276572035 ps
CPU time 9.29 seconds
Started Aug 07 06:14:56 PM PDT 24
Finished Aug 07 06:15:06 PM PDT 24
Peak memory 218284 kb
Host smart-22183a79-7bac-4c7f-90c8-ff0d59ab0bbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304952379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3304952379
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1921073974
Short name T578
Test name
Test status
Simulation time 1494713613 ps
CPU time 19.26 seconds
Started Aug 07 06:14:58 PM PDT 24
Finished Aug 07 06:15:17 PM PDT 24
Peak memory 225948 kb
Host smart-866d56d0-e8d9-4411-bc91-83765b4b41f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921073974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1921073974
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.4021380836
Short name T627
Test name
Test status
Simulation time 883493531 ps
CPU time 15.39 seconds
Started Aug 07 06:14:55 PM PDT 24
Finished Aug 07 06:15:10 PM PDT 24
Peak memory 225904 kb
Host smart-91eac5a1-4a97-4375-944c-f1a2b96e5e9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021380836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
4021380836
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.736374529
Short name T335
Test name
Test status
Simulation time 213863596 ps
CPU time 6.93 seconds
Started Aug 07 06:14:56 PM PDT 24
Finished Aug 07 06:15:03 PM PDT 24
Peak memory 224840 kb
Host smart-52782951-b284-4d29-99c6-5d50fd472674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736374529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.736374529
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2653202269
Short name T741
Test name
Test status
Simulation time 59250470 ps
CPU time 2.85 seconds
Started Aug 07 06:14:57 PM PDT 24
Finished Aug 07 06:15:00 PM PDT 24
Peak memory 223668 kb
Host smart-2e43afdf-decd-46ad-9677-595e363129c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653202269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2653202269
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1347336641
Short name T712
Test name
Test status
Simulation time 251858011 ps
CPU time 26.44 seconds
Started Aug 07 06:14:54 PM PDT 24
Finished Aug 07 06:15:21 PM PDT 24
Peak memory 250844 kb
Host smart-487cfa2e-f7a4-4401-af35-9a47579f270c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347336641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1347336641
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.694714492
Short name T628
Test name
Test status
Simulation time 847090444 ps
CPU time 6.95 seconds
Started Aug 07 06:15:01 PM PDT 24
Finished Aug 07 06:15:08 PM PDT 24
Peak memory 250584 kb
Host smart-02bb9e4b-4d62-4496-9ff7-258474c913ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694714492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.694714492
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2551318359
Short name T804
Test name
Test status
Simulation time 22559147810 ps
CPU time 137.78 seconds
Started Aug 07 06:14:56 PM PDT 24
Finished Aug 07 06:17:14 PM PDT 24
Peak memory 275608 kb
Host smart-a099bdb0-4330-4694-8462-1d3a2d3b3c48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551318359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2551318359
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1406097790
Short name T331
Test name
Test status
Simulation time 151217912 ps
CPU time 0.86 seconds
Started Aug 07 06:14:56 PM PDT 24
Finished Aug 07 06:14:57 PM PDT 24
Peak memory 208952 kb
Host smart-fd3ffe77-55ec-4c71-a5c5-d1c693fdabab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406097790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1406097790
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2275417874
Short name T547
Test name
Test status
Simulation time 17517805 ps
CPU time 1.11 seconds
Started Aug 07 06:15:04 PM PDT 24
Finished Aug 07 06:15:06 PM PDT 24
Peak memory 208984 kb
Host smart-d2905e8d-7264-4481-bf2d-04f59b008c22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275417874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2275417874
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1741081038
Short name T357
Test name
Test status
Simulation time 452564072 ps
CPU time 8.67 seconds
Started Aug 07 06:14:55 PM PDT 24
Finished Aug 07 06:15:03 PM PDT 24
Peak memory 218144 kb
Host smart-f6bd4ada-c200-4ffc-80a4-f422642e77d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741081038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1741081038
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3333809161
Short name T20
Test name
Test status
Simulation time 536018833 ps
CPU time 4.13 seconds
Started Aug 07 06:15:00 PM PDT 24
Finished Aug 07 06:15:05 PM PDT 24
Peak memory 217260 kb
Host smart-e4dbcf74-8edf-44e4-9bc8-8f27a1e1bc43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333809161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3333809161
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3617869977
Short name T631
Test name
Test status
Simulation time 20946159 ps
CPU time 1.47 seconds
Started Aug 07 06:15:00 PM PDT 24
Finished Aug 07 06:15:01 PM PDT 24
Peak memory 221788 kb
Host smart-ddbc3482-ee99-454d-aac2-61144a567330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617869977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3617869977
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2528801072
Short name T822
Test name
Test status
Simulation time 388616611 ps
CPU time 12.75 seconds
Started Aug 07 06:14:56 PM PDT 24
Finished Aug 07 06:15:09 PM PDT 24
Peak memory 218868 kb
Host smart-0d2e0024-263f-40e4-9f5f-9a1f869a362d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528801072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2528801072
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3066804507
Short name T724
Test name
Test status
Simulation time 342348855 ps
CPU time 11.92 seconds
Started Aug 07 06:15:05 PM PDT 24
Finished Aug 07 06:15:17 PM PDT 24
Peak memory 225848 kb
Host smart-e2c4e014-b71b-4ccb-b7e1-ff17e3cc990e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066804507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3066804507
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.800806740
Short name T558
Test name
Test status
Simulation time 312539767 ps
CPU time 8.65 seconds
Started Aug 07 06:15:03 PM PDT 24
Finished Aug 07 06:15:12 PM PDT 24
Peak memory 225904 kb
Host smart-25fa3d77-c672-45ac-b1f8-7ba3915ef7b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800806740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.800806740
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.525309213
Short name T649
Test name
Test status
Simulation time 330286665 ps
CPU time 12.34 seconds
Started Aug 07 06:14:58 PM PDT 24
Finished Aug 07 06:15:10 PM PDT 24
Peak memory 218288 kb
Host smart-0523608e-70cb-46de-9df7-26884320acc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525309213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.525309213
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3198387673
Short name T15
Test name
Test status
Simulation time 225777147 ps
CPU time 1.97 seconds
Started Aug 07 06:14:55 PM PDT 24
Finished Aug 07 06:14:57 PM PDT 24
Peak memory 214012 kb
Host smart-2e503129-8360-4bd6-971d-9779507112a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198387673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3198387673
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2497033550
Short name T344
Test name
Test status
Simulation time 1041973128 ps
CPU time 32.34 seconds
Started Aug 07 06:15:01 PM PDT 24
Finished Aug 07 06:15:34 PM PDT 24
Peak memory 251032 kb
Host smart-8c27acbb-8eb3-444f-9312-9126d52e1ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497033550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2497033550
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.419346428
Short name T534
Test name
Test status
Simulation time 183890499 ps
CPU time 10.04 seconds
Started Aug 07 06:15:00 PM PDT 24
Finished Aug 07 06:15:10 PM PDT 24
Peak memory 250808 kb
Host smart-dd26cfb4-3fa2-46ff-921a-583a0ca200a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419346428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.419346428
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3376831537
Short name T732
Test name
Test status
Simulation time 5763507636 ps
CPU time 194.23 seconds
Started Aug 07 06:15:05 PM PDT 24
Finished Aug 07 06:18:19 PM PDT 24
Peak memory 267252 kb
Host smart-71afd8f4-4115-441d-bdaa-182e6afab0ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376831537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3376831537
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3906441694
Short name T105
Test name
Test status
Simulation time 30902714446 ps
CPU time 324.53 seconds
Started Aug 07 06:15:05 PM PDT 24
Finished Aug 07 06:20:30 PM PDT 24
Peak memory 283812 kb
Host smart-f62efd8e-7676-490b-9739-6052f5a0ee80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3906441694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3906441694
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2703120024
Short name T782
Test name
Test status
Simulation time 72406366 ps
CPU time 1.08 seconds
Started Aug 07 06:14:53 PM PDT 24
Finished Aug 07 06:14:55 PM PDT 24
Peak memory 211916 kb
Host smart-e1d206cd-5273-435e-946c-ee9bb73aaf4b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703120024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2703120024
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.458076423
Short name T670
Test name
Test status
Simulation time 24165097 ps
CPU time 0.98 seconds
Started Aug 07 06:15:01 PM PDT 24
Finished Aug 07 06:15:02 PM PDT 24
Peak memory 208820 kb
Host smart-b4d20890-156e-4ce3-8c8d-ce8647a32b04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458076423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.458076423
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.573055150
Short name T569
Test name
Test status
Simulation time 898642499 ps
CPU time 12.57 seconds
Started Aug 07 06:15:10 PM PDT 24
Finished Aug 07 06:15:22 PM PDT 24
Peak memory 218200 kb
Host smart-8976e34d-88d1-4d43-95c7-c2243d468723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573055150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.573055150
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2542529518
Short name T25
Test name
Test status
Simulation time 366691074 ps
CPU time 5.97 seconds
Started Aug 07 06:15:07 PM PDT 24
Finished Aug 07 06:15:13 PM PDT 24
Peak memory 217592 kb
Host smart-0943371f-1bd2-4885-81c8-668076b47aa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542529518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2542529518
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.662491008
Short name T679
Test name
Test status
Simulation time 266327968 ps
CPU time 2.57 seconds
Started Aug 07 06:15:03 PM PDT 24
Finished Aug 07 06:15:06 PM PDT 24
Peak memory 218196 kb
Host smart-daac5d05-234f-47fb-a6a3-5b3e897a7b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662491008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.662491008
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.774592568
Short name T730
Test name
Test status
Simulation time 4040883501 ps
CPU time 9.65 seconds
Started Aug 07 06:15:06 PM PDT 24
Finished Aug 07 06:15:15 PM PDT 24
Peak memory 226064 kb
Host smart-cb70744f-a557-4d75-9a6b-6f042f71c2b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774592568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.774592568
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.508107758
Short name T104
Test name
Test status
Simulation time 973295888 ps
CPU time 13.48 seconds
Started Aug 07 06:15:03 PM PDT 24
Finished Aug 07 06:15:17 PM PDT 24
Peak memory 225852 kb
Host smart-baa92645-2ea0-4fa3-bd29-3d97f44357fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508107758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.508107758
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3050074738
Short name T291
Test name
Test status
Simulation time 328919559 ps
CPU time 9.02 seconds
Started Aug 07 06:15:02 PM PDT 24
Finished Aug 07 06:15:11 PM PDT 24
Peak memory 218168 kb
Host smart-53d3b402-dca1-4da1-978d-cdc0e611e9a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050074738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3050074738
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.4250876965
Short name T428
Test name
Test status
Simulation time 675324066 ps
CPU time 13.8 seconds
Started Aug 07 06:15:02 PM PDT 24
Finished Aug 07 06:15:16 PM PDT 24
Peak memory 226008 kb
Host smart-086e3c41-88b6-464b-aec2-605ffb0f626f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250876965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.4250876965
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.582650775
Short name T542
Test name
Test status
Simulation time 99955629 ps
CPU time 3.09 seconds
Started Aug 07 06:15:02 PM PDT 24
Finished Aug 07 06:15:05 PM PDT 24
Peak memory 217540 kb
Host smart-36d079c6-7dbe-4101-badf-0b5c9acefa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582650775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.582650775
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3557486177
Short name T582
Test name
Test status
Simulation time 459505566 ps
CPU time 29.66 seconds
Started Aug 07 06:15:01 PM PDT 24
Finished Aug 07 06:15:31 PM PDT 24
Peak memory 250828 kb
Host smart-2b4029b8-ecfb-46da-bd42-0ce22e277464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557486177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3557486177
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3606586351
Short name T294
Test name
Test status
Simulation time 292060244 ps
CPU time 8.4 seconds
Started Aug 07 06:15:04 PM PDT 24
Finished Aug 07 06:15:12 PM PDT 24
Peak memory 250872 kb
Host smart-0dd08d76-0f88-4d3e-b5d9-142a77de8d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606586351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3606586351
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3015241459
Short name T622
Test name
Test status
Simulation time 8032124119 ps
CPU time 245.95 seconds
Started Aug 07 06:15:05 PM PDT 24
Finished Aug 07 06:19:11 PM PDT 24
Peak memory 258840 kb
Host smart-a75b6471-5808-46ba-acf0-9d9802d6abf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015241459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3015241459
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.2476053635
Short name T147
Test name
Test status
Simulation time 185344390752 ps
CPU time 372.63 seconds
Started Aug 07 06:15:05 PM PDT 24
Finished Aug 07 06:21:17 PM PDT 24
Peak memory 283844 kb
Host smart-a8ed6208-051a-4ce7-a20c-5fe0908b1103
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2476053635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.2476053635
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3639333992
Short name T325
Test name
Test status
Simulation time 64215547 ps
CPU time 0.87 seconds
Started Aug 07 06:15:05 PM PDT 24
Finished Aug 07 06:15:06 PM PDT 24
Peak memory 211900 kb
Host smart-6aad6b9b-c3f7-4894-bba9-726e1a1a3cdb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639333992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3639333992
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1318950086
Short name T748
Test name
Test status
Simulation time 89270956 ps
CPU time 1.1 seconds
Started Aug 07 06:15:11 PM PDT 24
Finished Aug 07 06:15:12 PM PDT 24
Peak memory 209004 kb
Host smart-a480d6d3-52f2-407e-8900-ccf75c11d20f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318950086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1318950086
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.789428271
Short name T179
Test name
Test status
Simulation time 1754964428 ps
CPU time 14.72 seconds
Started Aug 07 06:15:00 PM PDT 24
Finished Aug 07 06:15:15 PM PDT 24
Peak memory 218140 kb
Host smart-666ed291-a1e7-40c8-a5eb-e4463c536362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789428271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.789428271
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.914088734
Short name T487
Test name
Test status
Simulation time 1084582142 ps
CPU time 3.34 seconds
Started Aug 07 06:15:03 PM PDT 24
Finished Aug 07 06:15:06 PM PDT 24
Peak memory 217168 kb
Host smart-905dd5c6-ba91-4a32-b975-774d54af3feb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914088734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.914088734
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.4001849423
Short name T386
Test name
Test status
Simulation time 143337950 ps
CPU time 2.32 seconds
Started Aug 07 06:15:04 PM PDT 24
Finished Aug 07 06:15:07 PM PDT 24
Peak memory 218168 kb
Host smart-b58559f6-42f7-4ad4-a89a-dfb8c9a86658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001849423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.4001849423
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2721784680
Short name T660
Test name
Test status
Simulation time 734527686 ps
CPU time 18.67 seconds
Started Aug 07 06:15:01 PM PDT 24
Finished Aug 07 06:15:20 PM PDT 24
Peak memory 218884 kb
Host smart-72f16960-d32d-4ae0-9694-caea4eeae7fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721784680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2721784680
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3855204270
Short name T399
Test name
Test status
Simulation time 1143465735 ps
CPU time 14.32 seconds
Started Aug 07 06:15:04 PM PDT 24
Finished Aug 07 06:15:18 PM PDT 24
Peak memory 225932 kb
Host smart-e1fc24f1-4cfc-4257-8f02-bc841af05652
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855204270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3855204270
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2641648538
Short name T614
Test name
Test status
Simulation time 802091003 ps
CPU time 8.72 seconds
Started Aug 07 06:15:03 PM PDT 24
Finished Aug 07 06:15:11 PM PDT 24
Peak memory 218144 kb
Host smart-0db6f5e5-f999-423d-b6ea-41bf051522f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641648538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2641648538
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3108929483
Short name T390
Test name
Test status
Simulation time 574169256 ps
CPU time 10.32 seconds
Started Aug 07 06:15:07 PM PDT 24
Finished Aug 07 06:15:18 PM PDT 24
Peak memory 218468 kb
Host smart-b7e6c835-8359-4a8b-88d1-93f0d0ff30ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108929483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3108929483
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.546896917
Short name T176
Test name
Test status
Simulation time 620081103 ps
CPU time 5.03 seconds
Started Aug 07 06:15:02 PM PDT 24
Finished Aug 07 06:15:07 PM PDT 24
Peak memory 217648 kb
Host smart-c29d5019-093b-497c-999a-80120c058aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546896917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.546896917
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3815071118
Short name T834
Test name
Test status
Simulation time 139489873 ps
CPU time 19.43 seconds
Started Aug 07 06:15:05 PM PDT 24
Finished Aug 07 06:15:25 PM PDT 24
Peak memory 250840 kb
Host smart-c61dec60-ed9f-420c-8c7a-ad4d4b51860b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815071118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3815071118
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.626592369
Short name T866
Test name
Test status
Simulation time 196674404 ps
CPU time 6.81 seconds
Started Aug 07 06:15:05 PM PDT 24
Finished Aug 07 06:15:12 PM PDT 24
Peak memory 242564 kb
Host smart-05a4fd51-2404-4afe-af87-8e070aaf7dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626592369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.626592369
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1352397208
Short name T96
Test name
Test status
Simulation time 23573382527 ps
CPU time 455.65 seconds
Started Aug 07 06:15:09 PM PDT 24
Finished Aug 07 06:22:45 PM PDT 24
Peak memory 496592 kb
Host smart-a904d92d-7111-4085-be5d-86d7be47fdf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352397208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1352397208
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.757810
Short name T142
Test name
Test status
Simulation time 27806059062 ps
CPU time 532.33 seconds
Started Aug 07 06:15:09 PM PDT 24
Finished Aug 07 06:24:01 PM PDT 24
Peak memory 404776 kb
Host smart-fc6914f6-2c09-433a-b437-75512527e670
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=757810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.757810
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3838689239
Short name T592
Test name
Test status
Simulation time 23422984 ps
CPU time 0.93 seconds
Started Aug 07 06:15:04 PM PDT 24
Finished Aug 07 06:15:05 PM PDT 24
Peak memory 209156 kb
Host smart-79ee5746-4b31-4ff1-871c-5d9ecbc811f6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838689239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.3838689239
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.4098096816
Short name T511
Test name
Test status
Simulation time 13889464 ps
CPU time 0.86 seconds
Started Aug 07 06:15:11 PM PDT 24
Finished Aug 07 06:15:12 PM PDT 24
Peak memory 208688 kb
Host smart-b4ed4215-1ab2-48dd-baa1-b20925d75e08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098096816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.4098096816
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2328890485
Short name T312
Test name
Test status
Simulation time 784341141 ps
CPU time 20.9 seconds
Started Aug 07 06:15:10 PM PDT 24
Finished Aug 07 06:15:31 PM PDT 24
Peak memory 218148 kb
Host smart-eb66d5f3-5f90-430e-bd02-47f8f8cd0322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328890485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2328890485
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2549701093
Short name T680
Test name
Test status
Simulation time 157801962 ps
CPU time 2.66 seconds
Started Aug 07 06:15:14 PM PDT 24
Finished Aug 07 06:15:17 PM PDT 24
Peak memory 217148 kb
Host smart-6832b000-bdbe-469a-a1c0-2334047d6e22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549701093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2549701093
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1022325690
Short name T14
Test name
Test status
Simulation time 39137065 ps
CPU time 1.55 seconds
Started Aug 07 06:15:10 PM PDT 24
Finished Aug 07 06:15:12 PM PDT 24
Peak memory 218212 kb
Host smart-8d0310cc-c513-4134-9759-0f3b7c777285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022325690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1022325690
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.177045885
Short name T468
Test name
Test status
Simulation time 780653530 ps
CPU time 10.29 seconds
Started Aug 07 06:15:13 PM PDT 24
Finished Aug 07 06:15:23 PM PDT 24
Peak memory 225916 kb
Host smart-7e52aea3-6ebe-4717-a688-1201560c5c9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177045885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.177045885
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.4271319062
Short name T762
Test name
Test status
Simulation time 908953482 ps
CPU time 9.94 seconds
Started Aug 07 06:15:11 PM PDT 24
Finished Aug 07 06:15:21 PM PDT 24
Peak memory 225932 kb
Host smart-abad6f6f-4ac5-4d87-a1d7-83410cabdf28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271319062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.4271319062
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3113859993
Short name T819
Test name
Test status
Simulation time 402477200 ps
CPU time 8.28 seconds
Started Aug 07 06:15:08 PM PDT 24
Finished Aug 07 06:15:16 PM PDT 24
Peak memory 218080 kb
Host smart-ba8fd514-1e47-481c-987a-24fd8080d529
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113859993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
3113859993
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.281731387
Short name T820
Test name
Test status
Simulation time 570462467 ps
CPU time 9.14 seconds
Started Aug 07 06:15:07 PM PDT 24
Finished Aug 07 06:15:16 PM PDT 24
Peak memory 225332 kb
Host smart-56511fcb-cd41-428f-91bc-8d715375e5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281731387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.281731387
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1927398090
Short name T821
Test name
Test status
Simulation time 28803077 ps
CPU time 1.98 seconds
Started Aug 07 06:15:09 PM PDT 24
Finished Aug 07 06:15:11 PM PDT 24
Peak memory 214036 kb
Host smart-3cff9808-029f-4335-b82f-cd8c02e11acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927398090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1927398090
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1356931003
Short name T565
Test name
Test status
Simulation time 493932063 ps
CPU time 29.06 seconds
Started Aug 07 06:15:15 PM PDT 24
Finished Aug 07 06:15:44 PM PDT 24
Peak memory 250904 kb
Host smart-7506cc16-4932-499f-83a5-31da12d28b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356931003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1356931003
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.34142604
Short name T691
Test name
Test status
Simulation time 286902877 ps
CPU time 9.04 seconds
Started Aug 07 06:15:15 PM PDT 24
Finished Aug 07 06:15:24 PM PDT 24
Peak memory 250816 kb
Host smart-e1ae7da3-efb2-40c7-b82c-7587b7612155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34142604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.34142604
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.175773712
Short name T398
Test name
Test status
Simulation time 3122412618 ps
CPU time 103.01 seconds
Started Aug 07 06:15:09 PM PDT 24
Finished Aug 07 06:16:52 PM PDT 24
Peak memory 250924 kb
Host smart-d5dd25bb-5b0a-4160-a079-5302fc25bd49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175773712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.175773712
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1572930611
Short name T600
Test name
Test status
Simulation time 16241140 ps
CPU time 0.97 seconds
Started Aug 07 06:15:07 PM PDT 24
Finished Aug 07 06:15:08 PM PDT 24
Peak memory 211876 kb
Host smart-e175bcdb-7048-4843-bc89-c690f22db511
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572930611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1572930611
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.213541686
Short name T228
Test name
Test status
Simulation time 21871010 ps
CPU time 0.96 seconds
Started Aug 07 06:15:15 PM PDT 24
Finished Aug 07 06:15:16 PM PDT 24
Peak memory 208864 kb
Host smart-b08270f9-b7bb-410e-90ab-08b9bff82980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213541686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.213541686
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1177592573
Short name T393
Test name
Test status
Simulation time 252502344 ps
CPU time 9.86 seconds
Started Aug 07 06:15:07 PM PDT 24
Finished Aug 07 06:15:17 PM PDT 24
Peak memory 218212 kb
Host smart-242571c0-0d54-4747-aba5-7901e239ae16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177592573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1177592573
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3189824190
Short name T168
Test name
Test status
Simulation time 203381964 ps
CPU time 3.81 seconds
Started Aug 07 06:15:15 PM PDT 24
Finished Aug 07 06:15:19 PM PDT 24
Peak memory 217656 kb
Host smart-394e8ecb-b674-46ff-be7f-295554087fa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189824190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3189824190
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1899701745
Short name T250
Test name
Test status
Simulation time 44927728 ps
CPU time 1.62 seconds
Started Aug 07 06:15:15 PM PDT 24
Finished Aug 07 06:15:17 PM PDT 24
Peak memory 222012 kb
Host smart-7f212b3e-0d2a-4422-86ea-93a584c7e0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899701745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1899701745
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3006476567
Short name T267
Test name
Test status
Simulation time 267556510 ps
CPU time 9.84 seconds
Started Aug 07 06:15:14 PM PDT 24
Finished Aug 07 06:15:24 PM PDT 24
Peak memory 219960 kb
Host smart-080afbe0-b39d-4ef7-80f7-deec466c5fb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006476567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3006476567
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1561768715
Short name T368
Test name
Test status
Simulation time 809716864 ps
CPU time 11.32 seconds
Started Aug 07 06:15:16 PM PDT 24
Finished Aug 07 06:15:27 PM PDT 24
Peak memory 225928 kb
Host smart-d102fc5f-9f50-47fb-9ad0-f3ce73800a2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561768715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1561768715
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3393069075
Short name T9
Test name
Test status
Simulation time 2023810197 ps
CPU time 16.87 seconds
Started Aug 07 06:15:14 PM PDT 24
Finished Aug 07 06:15:31 PM PDT 24
Peak memory 218168 kb
Host smart-c742cb50-0026-469a-8488-f4d5c3127346
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393069075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3393069075
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1594771088
Short name T513
Test name
Test status
Simulation time 399021463 ps
CPU time 6.64 seconds
Started Aug 07 06:15:14 PM PDT 24
Finished Aug 07 06:15:20 PM PDT 24
Peak memory 225080 kb
Host smart-6085f2a8-a14a-4586-a0d1-fa34643163b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594771088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1594771088
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.4108438969
Short name T518
Test name
Test status
Simulation time 58541174 ps
CPU time 4.02 seconds
Started Aug 07 06:15:12 PM PDT 24
Finished Aug 07 06:15:16 PM PDT 24
Peak memory 217688 kb
Host smart-a173e13c-c169-4859-84d8-d7ad6ff3c103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108438969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.4108438969
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1934109153
Short name T651
Test name
Test status
Simulation time 233980296 ps
CPU time 25.14 seconds
Started Aug 07 06:15:09 PM PDT 24
Finished Aug 07 06:15:34 PM PDT 24
Peak memory 250848 kb
Host smart-091f373f-675f-47b9-ac33-f5198e0e6c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934109153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1934109153
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2020375936
Short name T253
Test name
Test status
Simulation time 98739225 ps
CPU time 6.29 seconds
Started Aug 07 06:15:08 PM PDT 24
Finished Aug 07 06:15:14 PM PDT 24
Peak memory 247164 kb
Host smart-31fadf43-ff17-4826-9c2e-bb5ffbab5566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020375936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2020375936
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.337766381
Short name T833
Test name
Test status
Simulation time 74506817875 ps
CPU time 128.8 seconds
Started Aug 07 06:15:16 PM PDT 24
Finished Aug 07 06:17:25 PM PDT 24
Peak memory 283776 kb
Host smart-5928ed8f-71e8-4425-bbe9-060219cc4fe4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337766381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.337766381
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3709664309
Short name T672
Test name
Test status
Simulation time 50201447 ps
CPU time 0.93 seconds
Started Aug 07 06:15:12 PM PDT 24
Finished Aug 07 06:15:13 PM PDT 24
Peak memory 211952 kb
Host smart-de405741-eeef-4fae-9c3b-0459adabbca3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709664309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3709664309
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.4258186609
Short name T521
Test name
Test status
Simulation time 94852900 ps
CPU time 1.27 seconds
Started Aug 07 06:15:20 PM PDT 24
Finished Aug 07 06:15:22 PM PDT 24
Peak memory 209036 kb
Host smart-8596d680-a37f-4675-a170-468d1f15f0bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258186609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.4258186609
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2470702659
Short name T543
Test name
Test status
Simulation time 2026157030 ps
CPU time 15.23 seconds
Started Aug 07 06:15:16 PM PDT 24
Finished Aug 07 06:15:31 PM PDT 24
Peak memory 218160 kb
Host smart-9425a6b6-1d4a-458f-8122-6c5a1c5f94ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470702659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2470702659
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.822164975
Short name T504
Test name
Test status
Simulation time 1521889000 ps
CPU time 8.49 seconds
Started Aug 07 06:15:15 PM PDT 24
Finished Aug 07 06:15:23 PM PDT 24
Peak memory 217192 kb
Host smart-441f83ff-c79b-42d8-b070-b5bdeb104b27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822164975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.822164975
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.486004724
Short name T852
Test name
Test status
Simulation time 839541354 ps
CPU time 4.43 seconds
Started Aug 07 06:15:16 PM PDT 24
Finished Aug 07 06:15:20 PM PDT 24
Peak memory 218184 kb
Host smart-75dbd953-f73c-479f-ae64-5e39c3af91f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486004724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.486004724
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.4138151136
Short name T346
Test name
Test status
Simulation time 819328096 ps
CPU time 10.47 seconds
Started Aug 07 06:15:13 PM PDT 24
Finished Aug 07 06:15:23 PM PDT 24
Peak memory 218244 kb
Host smart-a8f1573a-b47e-4f56-935b-c7ca0bee7454
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138151136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.4138151136
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3435136088
Short name T233
Test name
Test status
Simulation time 1257844949 ps
CPU time 8.46 seconds
Started Aug 07 06:15:22 PM PDT 24
Finished Aug 07 06:15:31 PM PDT 24
Peak memory 225928 kb
Host smart-7fa47dda-87a6-4824-9491-70516b7a2ea7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435136088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3435136088
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1561899308
Short name T781
Test name
Test status
Simulation time 1588268983 ps
CPU time 9.64 seconds
Started Aug 07 06:15:14 PM PDT 24
Finished Aug 07 06:15:24 PM PDT 24
Peak memory 218280 kb
Host smart-7364a0d3-74bb-4062-9748-0772dc9da923
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561899308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1561899308
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3234738682
Short name T752
Test name
Test status
Simulation time 240634706 ps
CPU time 8.49 seconds
Started Aug 07 06:15:14 PM PDT 24
Finished Aug 07 06:15:23 PM PDT 24
Peak memory 225976 kb
Host smart-5715dbd6-2e0f-40bc-8efc-ec48efc51f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234738682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3234738682
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1121184020
Short name T609
Test name
Test status
Simulation time 45333488 ps
CPU time 3.02 seconds
Started Aug 07 06:15:13 PM PDT 24
Finished Aug 07 06:15:16 PM PDT 24
Peak memory 214472 kb
Host smart-5744d0e1-d3d6-43f7-a551-3335bdb76636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121184020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1121184020
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3683007500
Short name T383
Test name
Test status
Simulation time 364491192 ps
CPU time 21.92 seconds
Started Aug 07 06:15:14 PM PDT 24
Finished Aug 07 06:15:36 PM PDT 24
Peak memory 250848 kb
Host smart-b4dc07a2-424f-4c46-a03b-cc2c39cf7345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683007500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3683007500
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.871481341
Short name T585
Test name
Test status
Simulation time 60881984 ps
CPU time 7.26 seconds
Started Aug 07 06:15:21 PM PDT 24
Finished Aug 07 06:15:29 PM PDT 24
Peak memory 242632 kb
Host smart-a23e32e7-63a2-4f6f-8b74-3aaf36440941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871481341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.871481341
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.4064048432
Short name T848
Test name
Test status
Simulation time 3754451132 ps
CPU time 90.72 seconds
Started Aug 07 06:15:16 PM PDT 24
Finished Aug 07 06:16:47 PM PDT 24
Peak memory 250936 kb
Host smart-a85ba799-7bbc-4e18-a76e-5297649caef0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064048432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.4064048432
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.533734392
Short name T261
Test name
Test status
Simulation time 38066919 ps
CPU time 1.14 seconds
Started Aug 07 06:15:15 PM PDT 24
Finished Aug 07 06:15:16 PM PDT 24
Peak memory 217688 kb
Host smart-d167f474-0caf-465a-94a8-b7920814ec3e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533734392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.533734392
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3053870942
Short name T793
Test name
Test status
Simulation time 56603462 ps
CPU time 1.12 seconds
Started Aug 07 06:13:39 PM PDT 24
Finished Aug 07 06:13:41 PM PDT 24
Peak memory 208876 kb
Host smart-d49db669-dd7c-4eae-b8b2-4fcecd163e75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053870942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3053870942
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2606667695
Short name T209
Test name
Test status
Simulation time 14096221 ps
CPU time 0.86 seconds
Started Aug 07 06:13:36 PM PDT 24
Finished Aug 07 06:13:37 PM PDT 24
Peak memory 208428 kb
Host smart-ef42a81d-c948-4845-9965-2c6f6f3dce8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606667695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2606667695
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2361622231
Short name T549
Test name
Test status
Simulation time 417650637 ps
CPU time 11.62 seconds
Started Aug 07 06:13:39 PM PDT 24
Finished Aug 07 06:13:51 PM PDT 24
Peak memory 218204 kb
Host smart-a532eea0-c520-447e-ba46-8fb0438ce871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361622231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2361622231
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2881899287
Short name T443
Test name
Test status
Simulation time 80932873 ps
CPU time 2.86 seconds
Started Aug 07 06:13:36 PM PDT 24
Finished Aug 07 06:13:39 PM PDT 24
Peak memory 217088 kb
Host smart-0001675d-b73b-43ba-a01b-99f49d1d3d8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881899287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2881899287
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3024556443
Short name T247
Test name
Test status
Simulation time 4777270871 ps
CPU time 60.77 seconds
Started Aug 07 06:13:38 PM PDT 24
Finished Aug 07 06:14:39 PM PDT 24
Peak memory 218796 kb
Host smart-026ce0d2-d8e3-493f-ba0d-2f2c52fe6a02
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024556443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3024556443
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2956036956
Short name T431
Test name
Test status
Simulation time 1686549812 ps
CPU time 10.7 seconds
Started Aug 07 06:13:40 PM PDT 24
Finished Aug 07 06:13:51 PM PDT 24
Peak memory 217104 kb
Host smart-08e26e7b-4f85-4ba5-a9cf-f1ec555d9dae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956036956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
956036956
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.70746600
Short name T269
Test name
Test status
Simulation time 947496742 ps
CPU time 6.8 seconds
Started Aug 07 06:13:35 PM PDT 24
Finished Aug 07 06:13:42 PM PDT 24
Peak memory 218164 kb
Host smart-727d1380-58d4-4abb-81a5-2ed4d0bcd062
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70746600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_p
rog_failure.70746600
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1653086612
Short name T69
Test name
Test status
Simulation time 4996429160 ps
CPU time 18.35 seconds
Started Aug 07 06:13:37 PM PDT 24
Finished Aug 07 06:13:55 PM PDT 24
Peak memory 217620 kb
Host smart-dd9aa0c4-7d72-4513-bd3e-98a42f8c08ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653086612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1653086612
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2452258789
Short name T717
Test name
Test status
Simulation time 589907530 ps
CPU time 5.24 seconds
Started Aug 07 06:13:40 PM PDT 24
Finished Aug 07 06:13:46 PM PDT 24
Peak memory 217524 kb
Host smart-e8605f85-ece5-4174-a73c-32ee40e55d51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452258789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2452258789
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2552085773
Short name T5
Test name
Test status
Simulation time 7822756249 ps
CPU time 71.38 seconds
Started Aug 07 06:13:39 PM PDT 24
Finished Aug 07 06:14:51 PM PDT 24
Peak memory 277576 kb
Host smart-947deb4e-b201-4b44-abb7-628c2a545e31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552085773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2552085773
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2509230358
Short name T313
Test name
Test status
Simulation time 8334081266 ps
CPU time 30.42 seconds
Started Aug 07 06:13:37 PM PDT 24
Finished Aug 07 06:14:08 PM PDT 24
Peak memory 250832 kb
Host smart-b7f877e5-3d01-4201-80ef-4ef3982ef53a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509230358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2509230358
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.132617987
Short name T615
Test name
Test status
Simulation time 135862050 ps
CPU time 2 seconds
Started Aug 07 06:13:35 PM PDT 24
Finished Aug 07 06:13:37 PM PDT 24
Peak memory 218200 kb
Host smart-9b09e19a-4bbc-438b-8b75-95b323cfb2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132617987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.132617987
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2465592707
Short name T67
Test name
Test status
Simulation time 523087130 ps
CPU time 9.41 seconds
Started Aug 07 06:13:38 PM PDT 24
Finished Aug 07 06:13:48 PM PDT 24
Peak memory 214452 kb
Host smart-dad0ab9e-3de7-41c2-a8be-fcda094081ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465592707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2465592707
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2963888727
Short name T91
Test name
Test status
Simulation time 581132910 ps
CPU time 25.24 seconds
Started Aug 07 06:13:37 PM PDT 24
Finished Aug 07 06:14:03 PM PDT 24
Peak memory 284268 kb
Host smart-ae9feb5a-bae3-4834-8a31-5bf4e9087f84
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963888727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2963888727
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2121337256
Short name T464
Test name
Test status
Simulation time 7468539101 ps
CPU time 14.13 seconds
Started Aug 07 06:13:40 PM PDT 24
Finished Aug 07 06:13:55 PM PDT 24
Peak memory 219908 kb
Host smart-a21e5c49-dd68-46e5-9e7b-e386d8935f9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121337256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2121337256
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3585943015
Short name T180
Test name
Test status
Simulation time 625921225 ps
CPU time 17.11 seconds
Started Aug 07 06:13:43 PM PDT 24
Finished Aug 07 06:14:00 PM PDT 24
Peak memory 225920 kb
Host smart-e72a5b73-0226-4d14-b471-4a2784baa5ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585943015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3585943015
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.874835123
Short name T151
Test name
Test status
Simulation time 702233858 ps
CPU time 13.29 seconds
Started Aug 07 06:13:36 PM PDT 24
Finished Aug 07 06:13:49 PM PDT 24
Peak memory 218152 kb
Host smart-bc841e71-b808-414b-8d8e-8c81ffdf5b27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874835123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.874835123
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2524604283
Short name T397
Test name
Test status
Simulation time 878960061 ps
CPU time 6.57 seconds
Started Aug 07 06:13:39 PM PDT 24
Finished Aug 07 06:13:46 PM PDT 24
Peak memory 224516 kb
Host smart-42973e99-c23b-454d-9639-af79d8b2a34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524604283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2524604283
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1910338341
Short name T304
Test name
Test status
Simulation time 133107067 ps
CPU time 1.65 seconds
Started Aug 07 06:13:43 PM PDT 24
Finished Aug 07 06:13:44 PM PDT 24
Peak memory 213716 kb
Host smart-98426a37-11bd-41b2-ab7f-a7d3d24a45f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910338341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1910338341
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1353348483
Short name T458
Test name
Test status
Simulation time 332992683 ps
CPU time 24.4 seconds
Started Aug 07 06:13:36 PM PDT 24
Finished Aug 07 06:14:00 PM PDT 24
Peak memory 250816 kb
Host smart-f7c50358-6375-429b-99ec-2518bac59885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353348483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1353348483
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.290634135
Short name T452
Test name
Test status
Simulation time 176556674 ps
CPU time 7.41 seconds
Started Aug 07 06:13:42 PM PDT 24
Finished Aug 07 06:13:50 PM PDT 24
Peak memory 250744 kb
Host smart-07709382-2882-4608-8734-b953cd93d591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290634135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.290634135
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1523463548
Short name T402
Test name
Test status
Simulation time 5144313061 ps
CPU time 50.19 seconds
Started Aug 07 06:13:41 PM PDT 24
Finished Aug 07 06:14:31 PM PDT 24
Peak memory 250928 kb
Host smart-2c006e2e-cc30-4b7b-9344-c0f48409d5a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523463548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1523463548
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.2606801014
Short name T145
Test name
Test status
Simulation time 59271669719 ps
CPU time 931.23 seconds
Started Aug 07 06:13:43 PM PDT 24
Finished Aug 07 06:29:14 PM PDT 24
Peak memory 438264 kb
Host smart-83687974-12e1-4002-9477-acef496c5a67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2606801014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.2606801014
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1632262203
Short name T540
Test name
Test status
Simulation time 12983159 ps
CPU time 0.96 seconds
Started Aug 07 06:13:39 PM PDT 24
Finished Aug 07 06:13:40 PM PDT 24
Peak memory 209056 kb
Host smart-0d548932-ba70-45d8-a0dd-be399fb4250b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632262203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1632262203
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1422955485
Short name T587
Test name
Test status
Simulation time 33569119 ps
CPU time 0.9 seconds
Started Aug 07 06:15:21 PM PDT 24
Finished Aug 07 06:15:22 PM PDT 24
Peak memory 208680 kb
Host smart-809e5cde-67b9-4436-903c-a68f12803b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422955485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1422955485
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2412168032
Short name T602
Test name
Test status
Simulation time 359083924 ps
CPU time 8.78 seconds
Started Aug 07 06:15:21 PM PDT 24
Finished Aug 07 06:15:30 PM PDT 24
Peak memory 218196 kb
Host smart-2bd1297e-d661-4313-8f40-9ebbc91801e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412168032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2412168032
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.899539477
Short name T714
Test name
Test status
Simulation time 849349533 ps
CPU time 6.07 seconds
Started Aug 07 06:15:27 PM PDT 24
Finished Aug 07 06:15:33 PM PDT 24
Peak memory 216980 kb
Host smart-b0f7476a-d575-40b2-be7b-c7f7dea2bf85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899539477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.899539477
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3145653660
Short name T745
Test name
Test status
Simulation time 71184944 ps
CPU time 2.2 seconds
Started Aug 07 06:15:23 PM PDT 24
Finished Aug 07 06:15:25 PM PDT 24
Peak memory 222232 kb
Host smart-8f94b19c-62de-41b1-b266-fb11bd6bcef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145653660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3145653660
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.12243421
Short name T276
Test name
Test status
Simulation time 274628663 ps
CPU time 12.79 seconds
Started Aug 07 06:15:19 PM PDT 24
Finished Aug 07 06:15:32 PM PDT 24
Peak memory 226040 kb
Host smart-8efbd691-5aca-4fe5-810c-8636b65e857c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12243421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.12243421
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2508625755
Short name T365
Test name
Test status
Simulation time 324421558 ps
CPU time 13.43 seconds
Started Aug 07 06:15:27 PM PDT 24
Finished Aug 07 06:15:40 PM PDT 24
Peak memory 225856 kb
Host smart-4fc2ba81-9c7d-49a7-af5b-1a269a068609
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508625755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2508625755
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2000495954
Short name T480
Test name
Test status
Simulation time 2453434929 ps
CPU time 13.5 seconds
Started Aug 07 06:15:26 PM PDT 24
Finished Aug 07 06:15:40 PM PDT 24
Peak memory 224932 kb
Host smart-c2088e34-64e3-43c5-9e48-049f50b50f9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000495954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2000495954
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2462130655
Short name T776
Test name
Test status
Simulation time 26034756 ps
CPU time 1.96 seconds
Started Aug 07 06:15:14 PM PDT 24
Finished Aug 07 06:15:16 PM PDT 24
Peak memory 217616 kb
Host smart-fe4b72bd-e3b8-4528-b663-302a57287e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462130655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2462130655
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.472593927
Short name T759
Test name
Test status
Simulation time 148310692 ps
CPU time 21.53 seconds
Started Aug 07 06:15:21 PM PDT 24
Finished Aug 07 06:15:42 PM PDT 24
Peak memory 250832 kb
Host smart-83386edd-c2d8-4cec-b3f6-93ec664743a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472593927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.472593927
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2420619080
Short name T798
Test name
Test status
Simulation time 112853192 ps
CPU time 9.83 seconds
Started Aug 07 06:15:23 PM PDT 24
Finished Aug 07 06:15:33 PM PDT 24
Peak memory 250824 kb
Host smart-ef44e4a0-ae82-4c1d-b7f1-e088903a4df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420619080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2420619080
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.236703648
Short name T859
Test name
Test status
Simulation time 5333538581 ps
CPU time 34.39 seconds
Started Aug 07 06:15:19 PM PDT 24
Finished Aug 07 06:15:54 PM PDT 24
Peak memory 250492 kb
Host smart-0feede12-380b-4850-b284-5ab0cea85466
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236703648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.236703648
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.208761523
Short name T44
Test name
Test status
Simulation time 32671929 ps
CPU time 1.01 seconds
Started Aug 07 06:15:14 PM PDT 24
Finished Aug 07 06:15:15 PM PDT 24
Peak memory 211876 kb
Host smart-6235edfc-349c-4d60-88d5-0c377eaa9ba4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208761523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.208761523
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2367292258
Short name T626
Test name
Test status
Simulation time 85595826 ps
CPU time 0.88 seconds
Started Aug 07 06:15:21 PM PDT 24
Finished Aug 07 06:15:22 PM PDT 24
Peak memory 208744 kb
Host smart-dec071ad-91f5-4e92-9f61-315e7bd89a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367292258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2367292258
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3993603189
Short name T48
Test name
Test status
Simulation time 1232504404 ps
CPU time 9.78 seconds
Started Aug 07 06:15:23 PM PDT 24
Finished Aug 07 06:15:33 PM PDT 24
Peak memory 218328 kb
Host smart-77a0dfd6-977e-4c3c-9746-dbf60ccaede4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993603189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3993603189
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3674361191
Short name T722
Test name
Test status
Simulation time 1487949061 ps
CPU time 9.62 seconds
Started Aug 07 06:15:21 PM PDT 24
Finished Aug 07 06:15:31 PM PDT 24
Peak memory 217484 kb
Host smart-25653029-10af-40ab-94cd-4d2bbd14ee9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674361191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3674361191
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.565184219
Short name T612
Test name
Test status
Simulation time 215591715 ps
CPU time 2.35 seconds
Started Aug 07 06:15:24 PM PDT 24
Finished Aug 07 06:15:26 PM PDT 24
Peak memory 218216 kb
Host smart-351eda95-8b1a-454f-ae44-ab9dd66b2fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565184219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.565184219
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.4179089208
Short name T564
Test name
Test status
Simulation time 226409547 ps
CPU time 9.11 seconds
Started Aug 07 06:15:26 PM PDT 24
Finished Aug 07 06:15:36 PM PDT 24
Peak memory 224928 kb
Host smart-59c2e645-7c4e-4eb5-ada2-8826f785fdda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179089208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.4179089208
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2902967392
Short name T818
Test name
Test status
Simulation time 408061448 ps
CPU time 11.88 seconds
Started Aug 07 06:15:20 PM PDT 24
Finished Aug 07 06:15:33 PM PDT 24
Peak memory 225948 kb
Host smart-ba79a8cd-ecf8-4c3c-a85c-db8318e939ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902967392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2902967392
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2722375910
Short name T361
Test name
Test status
Simulation time 396021695 ps
CPU time 12.86 seconds
Started Aug 07 06:15:23 PM PDT 24
Finished Aug 07 06:15:36 PM PDT 24
Peak memory 218124 kb
Host smart-6abd39f0-2655-4aab-a4fe-f1afb883cff6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722375910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2722375910
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1926340232
Short name T552
Test name
Test status
Simulation time 1444865629 ps
CPU time 7.9 seconds
Started Aug 07 06:15:24 PM PDT 24
Finished Aug 07 06:15:32 PM PDT 24
Peak memory 226044 kb
Host smart-cd21ced2-2e3e-46ec-8278-587852a6f4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926340232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1926340232
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3751269194
Short name T836
Test name
Test status
Simulation time 90263688 ps
CPU time 5.13 seconds
Started Aug 07 06:15:20 PM PDT 24
Finished Aug 07 06:15:26 PM PDT 24
Peak memory 222684 kb
Host smart-87f7233f-7517-4b4f-b7f9-5e0cc005dd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751269194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3751269194
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.4062380246
Short name T636
Test name
Test status
Simulation time 270848292 ps
CPU time 24.9 seconds
Started Aug 07 06:15:19 PM PDT 24
Finished Aug 07 06:15:44 PM PDT 24
Peak memory 245764 kb
Host smart-a4912d9f-15d8-4d3a-8b75-225308fcfdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062380246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.4062380246
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2042312570
Short name T669
Test name
Test status
Simulation time 56740995 ps
CPU time 3.32 seconds
Started Aug 07 06:15:21 PM PDT 24
Finished Aug 07 06:15:25 PM PDT 24
Peak memory 226284 kb
Host smart-27371501-bc29-46f2-92ee-8eec28c33851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042312570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2042312570
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3594233556
Short name T688
Test name
Test status
Simulation time 22810367755 ps
CPU time 154.12 seconds
Started Aug 07 06:15:25 PM PDT 24
Finished Aug 07 06:17:59 PM PDT 24
Peak memory 224996 kb
Host smart-83900da1-983f-4292-a2bb-2262dd547c17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594233556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3594233556
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1534119089
Short name T438
Test name
Test status
Simulation time 58652119 ps
CPU time 0.92 seconds
Started Aug 07 06:15:20 PM PDT 24
Finished Aug 07 06:15:22 PM PDT 24
Peak memory 211892 kb
Host smart-a6cd0038-0fc4-4f01-9c91-678ac8bcc79c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534119089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1534119089
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.246557096
Short name T694
Test name
Test status
Simulation time 57336858 ps
CPU time 0.96 seconds
Started Aug 07 06:15:29 PM PDT 24
Finished Aug 07 06:15:30 PM PDT 24
Peak memory 208828 kb
Host smart-0daba557-ce8b-44e4-850e-3b3059b8ecec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246557096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.246557096
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3660333945
Short name T559
Test name
Test status
Simulation time 1174497391 ps
CPU time 16.98 seconds
Started Aug 07 06:15:28 PM PDT 24
Finished Aug 07 06:15:46 PM PDT 24
Peak memory 226048 kb
Host smart-42c59430-d1b2-40ef-bd4d-e32586d9fec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660333945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3660333945
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.4105160377
Short name T875
Test name
Test status
Simulation time 8130910885 ps
CPU time 5.8 seconds
Started Aug 07 06:15:32 PM PDT 24
Finished Aug 07 06:15:38 PM PDT 24
Peak memory 217664 kb
Host smart-ed83641c-dca0-4645-840f-92f5d3bacf3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105160377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.4105160377
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2755738995
Short name T500
Test name
Test status
Simulation time 61692469 ps
CPU time 3.33 seconds
Started Aug 07 06:15:29 PM PDT 24
Finished Aug 07 06:15:33 PM PDT 24
Peak memory 218112 kb
Host smart-c2c345a4-22bc-4805-8084-139a89e6cdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755738995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2755738995
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1321029158
Short name T510
Test name
Test status
Simulation time 12340793196 ps
CPU time 16.79 seconds
Started Aug 07 06:15:29 PM PDT 24
Finished Aug 07 06:15:46 PM PDT 24
Peak memory 219952 kb
Host smart-a3c0bebe-cda4-4516-a061-d4bd1cd65715
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321029158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1321029158
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.4204946330
Short name T851
Test name
Test status
Simulation time 1573693648 ps
CPU time 15.96 seconds
Started Aug 07 06:15:33 PM PDT 24
Finished Aug 07 06:15:49 PM PDT 24
Peak memory 225872 kb
Host smart-a874bd16-c749-4948-83e6-69baf157a35e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204946330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.4204946330
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2713128467
Short name T65
Test name
Test status
Simulation time 1798355905 ps
CPU time 11.94 seconds
Started Aug 07 06:15:30 PM PDT 24
Finished Aug 07 06:15:42 PM PDT 24
Peak memory 225848 kb
Host smart-036d5fa4-64df-478b-a1a4-41407dd6ba5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713128467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2713128467
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3177936372
Short name T62
Test name
Test status
Simulation time 568370930 ps
CPU time 9.51 seconds
Started Aug 07 06:15:31 PM PDT 24
Finished Aug 07 06:15:41 PM PDT 24
Peak memory 224948 kb
Host smart-e4a80e22-a18b-4187-b71b-a405062764c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177936372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3177936372
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1445046053
Short name T12
Test name
Test status
Simulation time 273915041 ps
CPU time 1.85 seconds
Started Aug 07 06:15:20 PM PDT 24
Finished Aug 07 06:15:22 PM PDT 24
Peak memory 213952 kb
Host smart-6d99c878-e5c4-4456-ab6f-0cb168019fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445046053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1445046053
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.414967924
Short name T603
Test name
Test status
Simulation time 332891439 ps
CPU time 35.22 seconds
Started Aug 07 06:15:22 PM PDT 24
Finished Aug 07 06:15:57 PM PDT 24
Peak memory 250868 kb
Host smart-af43d90a-3787-4994-aef7-ff62131fb48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414967924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.414967924
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1734726713
Short name T10
Test name
Test status
Simulation time 304494811 ps
CPU time 7.39 seconds
Started Aug 07 06:15:21 PM PDT 24
Finished Aug 07 06:15:28 PM PDT 24
Peak memory 250844 kb
Host smart-a27816f8-91a2-4e41-9343-737892da2abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734726713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1734726713
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.220936699
Short name T479
Test name
Test status
Simulation time 15865253394 ps
CPU time 542.2 seconds
Started Aug 07 06:15:29 PM PDT 24
Finished Aug 07 06:24:32 PM PDT 24
Peak memory 271336 kb
Host smart-39bc037d-578a-4a03-a4b5-6c92deb23adf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220936699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.220936699
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.97747509
Short name T548
Test name
Test status
Simulation time 15111397339 ps
CPU time 490.74 seconds
Started Aug 07 06:15:27 PM PDT 24
Finished Aug 07 06:23:38 PM PDT 24
Peak memory 283804 kb
Host smart-b6788a04-067b-4a8a-a204-42efdfa3c180
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=97747509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.97747509
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.4213634878
Short name T856
Test name
Test status
Simulation time 53739332 ps
CPU time 0.92 seconds
Started Aug 07 06:15:31 PM PDT 24
Finished Aug 07 06:15:32 PM PDT 24
Peak memory 208820 kb
Host smart-49e27fc5-88d6-4416-95a7-6a806d958304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213634878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.4213634878
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3739518707
Short name T751
Test name
Test status
Simulation time 826047273 ps
CPU time 14.91 seconds
Started Aug 07 06:15:28 PM PDT 24
Finished Aug 07 06:15:43 PM PDT 24
Peak memory 218204 kb
Host smart-a9917ce6-168a-405e-9508-4ad5abdbdcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739518707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3739518707
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3733676245
Short name T800
Test name
Test status
Simulation time 1790340916 ps
CPU time 5.93 seconds
Started Aug 07 06:15:30 PM PDT 24
Finished Aug 07 06:15:36 PM PDT 24
Peak memory 217104 kb
Host smart-bba50289-994f-46c0-9036-692d759f5273
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733676245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3733676245
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2896828588
Short name T316
Test name
Test status
Simulation time 213376455 ps
CPU time 2.68 seconds
Started Aug 07 06:15:29 PM PDT 24
Finished Aug 07 06:15:31 PM PDT 24
Peak memory 218276 kb
Host smart-7e04f118-1ad4-4111-8c86-45d9255a0f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896828588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2896828588
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2223228507
Short name T740
Test name
Test status
Simulation time 948103256 ps
CPU time 8.55 seconds
Started Aug 07 06:15:27 PM PDT 24
Finished Aug 07 06:15:35 PM PDT 24
Peak memory 226012 kb
Host smart-1961b88e-c0db-4c4a-9620-1ffb161cb5bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223228507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2223228507
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1576093750
Short name T734
Test name
Test status
Simulation time 1609347066 ps
CPU time 7.37 seconds
Started Aug 07 06:15:28 PM PDT 24
Finished Aug 07 06:15:35 PM PDT 24
Peak memory 226136 kb
Host smart-32c4d5cc-7fcb-46fe-9acd-55fbcf9f8c61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576093750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1576093750
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2160651556
Short name T314
Test name
Test status
Simulation time 798640811 ps
CPU time 8.54 seconds
Started Aug 07 06:15:26 PM PDT 24
Finished Aug 07 06:15:35 PM PDT 24
Peak memory 225988 kb
Host smart-ea14e9a5-4574-49ab-8856-7eaaf571f280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160651556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2160651556
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3815755890
Short name T610
Test name
Test status
Simulation time 81775681 ps
CPU time 3.21 seconds
Started Aug 07 06:15:27 PM PDT 24
Finished Aug 07 06:15:31 PM PDT 24
Peak memory 217616 kb
Host smart-ed7aeac5-4881-4a2b-9329-f7fb91fbd07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815755890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3815755890
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3632852590
Short name T790
Test name
Test status
Simulation time 459626051 ps
CPU time 23.13 seconds
Started Aug 07 06:15:29 PM PDT 24
Finished Aug 07 06:15:52 PM PDT 24
Peak memory 250740 kb
Host smart-0f8513b8-b2dd-40dd-bcfa-97cdd484bb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632852590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3632852590
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1309912272
Short name T370
Test name
Test status
Simulation time 207908569 ps
CPU time 3.61 seconds
Started Aug 07 06:15:28 PM PDT 24
Finished Aug 07 06:15:32 PM PDT 24
Peak memory 222560 kb
Host smart-6c81a318-6baf-433d-9876-44a937348109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309912272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1309912272
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1089771448
Short name T78
Test name
Test status
Simulation time 2805998077 ps
CPU time 50.14 seconds
Started Aug 07 06:15:29 PM PDT 24
Finished Aug 07 06:16:19 PM PDT 24
Peak memory 250984 kb
Host smart-8cf6aea6-c13a-4307-9b13-94cb2be7f9c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089771448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1089771448
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1768331013
Short name T171
Test name
Test status
Simulation time 75225344 ps
CPU time 0.99 seconds
Started Aug 07 06:15:30 PM PDT 24
Finished Aug 07 06:15:31 PM PDT 24
Peak memory 211884 kb
Host smart-8121de4c-3437-4cc1-a124-621c6288c3e8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768331013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1768331013
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2771508504
Short name T466
Test name
Test status
Simulation time 56704913 ps
CPU time 0.94 seconds
Started Aug 07 06:15:33 PM PDT 24
Finished Aug 07 06:15:34 PM PDT 24
Peak memory 208876 kb
Host smart-e30b33d7-78ae-4b2d-8a7f-f60f8a7862ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771508504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2771508504
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.4131682033
Short name T768
Test name
Test status
Simulation time 299493202 ps
CPU time 14.19 seconds
Started Aug 07 06:15:30 PM PDT 24
Finished Aug 07 06:15:45 PM PDT 24
Peak memory 225912 kb
Host smart-7d9b2c19-5675-45a5-8007-fcd1cc5f8418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131682033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.4131682033
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2355676931
Short name T749
Test name
Test status
Simulation time 198720290 ps
CPU time 6.06 seconds
Started Aug 07 06:15:28 PM PDT 24
Finished Aug 07 06:15:34 PM PDT 24
Peak memory 217100 kb
Host smart-3605f753-49a7-40d5-bc22-024d526992f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355676931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2355676931
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1103268928
Short name T439
Test name
Test status
Simulation time 60580033 ps
CPU time 1.41 seconds
Started Aug 07 06:15:27 PM PDT 24
Finished Aug 07 06:15:28 PM PDT 24
Peak memory 218148 kb
Host smart-f69ce8a4-866d-4922-a7db-ee36ef3405ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103268928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1103268928
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.4179734380
Short name T221
Test name
Test status
Simulation time 6493542584 ps
CPU time 14.06 seconds
Started Aug 07 06:15:30 PM PDT 24
Finished Aug 07 06:15:44 PM PDT 24
Peak memory 226044 kb
Host smart-5f3459f2-9f11-4996-ab3a-f279e77cfcb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179734380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4179734380
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2806448400
Short name T823
Test name
Test status
Simulation time 557200429 ps
CPU time 15.16 seconds
Started Aug 07 06:15:33 PM PDT 24
Finished Aug 07 06:15:49 PM PDT 24
Peak memory 225852 kb
Host smart-74bf8812-5cdf-4619-841f-adf9ec0dc81b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806448400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2806448400
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1256818873
Short name T532
Test name
Test status
Simulation time 515746937 ps
CPU time 7.2 seconds
Started Aug 07 06:15:28 PM PDT 24
Finished Aug 07 06:15:35 PM PDT 24
Peak memory 225972 kb
Host smart-ad505eaa-ab77-4f29-9795-a00b468053a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256818873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1256818873
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.426023827
Short name T509
Test name
Test status
Simulation time 1218818929 ps
CPU time 7.63 seconds
Started Aug 07 06:15:30 PM PDT 24
Finished Aug 07 06:15:38 PM PDT 24
Peak memory 224412 kb
Host smart-3b356fa2-f90e-4097-b502-25c9a56d8e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426023827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.426023827
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2751902558
Short name T667
Test name
Test status
Simulation time 63963134 ps
CPU time 2.75 seconds
Started Aug 07 06:15:28 PM PDT 24
Finished Aug 07 06:15:31 PM PDT 24
Peak memory 217544 kb
Host smart-544b96dd-1014-46d5-99ae-269ab100df80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751902558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2751902558
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.892568562
Short name T561
Test name
Test status
Simulation time 2092425473 ps
CPU time 22.99 seconds
Started Aug 07 06:15:30 PM PDT 24
Finished Aug 07 06:15:53 PM PDT 24
Peak memory 250784 kb
Host smart-fd484765-2088-4ce6-8601-ed2e8e04f0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892568562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.892568562
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1958580873
Short name T496
Test name
Test status
Simulation time 122501644 ps
CPU time 8.24 seconds
Started Aug 07 06:15:29 PM PDT 24
Finished Aug 07 06:15:37 PM PDT 24
Peak memory 250740 kb
Host smart-95d5f2ce-ddf5-42b2-aadc-742a6649e9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958580873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1958580873
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3348809817
Short name T350
Test name
Test status
Simulation time 3478339472 ps
CPU time 46.89 seconds
Started Aug 07 06:15:31 PM PDT 24
Finished Aug 07 06:16:19 PM PDT 24
Peak memory 250896 kb
Host smart-a0581864-316b-4f25-8046-5576b6c8608f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348809817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3348809817
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1315852604
Short name T405
Test name
Test status
Simulation time 30122154 ps
CPU time 0.98 seconds
Started Aug 07 06:15:32 PM PDT 24
Finished Aug 07 06:15:33 PM PDT 24
Peak memory 211972 kb
Host smart-ef3e736d-8cdb-4641-8ad3-3b670794151f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315852604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1315852604
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1051009094
Short name T524
Test name
Test status
Simulation time 22541393 ps
CPU time 1.01 seconds
Started Aug 07 06:15:32 PM PDT 24
Finished Aug 07 06:15:33 PM PDT 24
Peak memory 208904 kb
Host smart-f8b82c4d-f40c-4101-9158-6821a9d9971e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051009094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1051009094
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3520629006
Short name T644
Test name
Test status
Simulation time 504364527 ps
CPU time 12.13 seconds
Started Aug 07 06:15:34 PM PDT 24
Finished Aug 07 06:15:46 PM PDT 24
Peak memory 226020 kb
Host smart-70d05ff3-a74b-4ee6-be04-72cc1018ee36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520629006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3520629006
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3428291786
Short name T621
Test name
Test status
Simulation time 903215764 ps
CPU time 5.93 seconds
Started Aug 07 06:15:33 PM PDT 24
Finished Aug 07 06:15:39 PM PDT 24
Peak memory 217324 kb
Host smart-eefd4fdd-35c2-482f-a0d2-58e9b14cb442
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428291786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3428291786
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.564862235
Short name T841
Test name
Test status
Simulation time 328001830 ps
CPU time 4.2 seconds
Started Aug 07 06:15:34 PM PDT 24
Finished Aug 07 06:15:38 PM PDT 24
Peak memory 218116 kb
Host smart-c5482776-ee52-4987-a5b0-73b3018440a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564862235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.564862235
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1385441695
Short name T319
Test name
Test status
Simulation time 626815085 ps
CPU time 14.73 seconds
Started Aug 07 06:15:31 PM PDT 24
Finished Aug 07 06:15:45 PM PDT 24
Peak memory 218896 kb
Host smart-2b6bfb2b-465e-42d0-8517-a8e81e0e33b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385441695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1385441695
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2934108790
Short name T825
Test name
Test status
Simulation time 727830977 ps
CPU time 8.75 seconds
Started Aug 07 06:15:33 PM PDT 24
Finished Aug 07 06:15:42 PM PDT 24
Peak memory 225940 kb
Host smart-97a124d8-b889-410e-81c2-390fa623c63e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934108790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2934108790
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2748576144
Short name T763
Test name
Test status
Simulation time 1269504959 ps
CPU time 8.33 seconds
Started Aug 07 06:15:33 PM PDT 24
Finished Aug 07 06:15:42 PM PDT 24
Peak memory 225960 kb
Host smart-bef6e6eb-040a-479f-a3c5-ea4068b65a5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748576144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2748576144
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2564753328
Short name T375
Test name
Test status
Simulation time 1987544536 ps
CPU time 8.16 seconds
Started Aug 07 06:15:33 PM PDT 24
Finished Aug 07 06:15:41 PM PDT 24
Peak memory 226000 kb
Host smart-405be44a-762a-4eb8-9adb-0701123a5309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564753328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2564753328
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1419523386
Short name T785
Test name
Test status
Simulation time 154901577 ps
CPU time 4.92 seconds
Started Aug 07 06:15:31 PM PDT 24
Finished Aug 07 06:15:37 PM PDT 24
Peak memory 217660 kb
Host smart-9de9f64d-1d53-416b-b3ec-504cc931fcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419523386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1419523386
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2538181588
Short name T682
Test name
Test status
Simulation time 658326553 ps
CPU time 23.75 seconds
Started Aug 07 06:15:31 PM PDT 24
Finished Aug 07 06:15:55 PM PDT 24
Peak memory 250848 kb
Host smart-2c682a4d-585a-42f8-a76c-1fbfb889fac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538181588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2538181588
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.192253459
Short name T488
Test name
Test status
Simulation time 97878891 ps
CPU time 7.76 seconds
Started Aug 07 06:15:34 PM PDT 24
Finished Aug 07 06:15:42 PM PDT 24
Peak memory 242660 kb
Host smart-30e171bf-83f3-49b2-945a-79089adde23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192253459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.192253459
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2668394890
Short name T692
Test name
Test status
Simulation time 1657412932 ps
CPU time 62.33 seconds
Started Aug 07 06:15:35 PM PDT 24
Finished Aug 07 06:16:37 PM PDT 24
Peak memory 250744 kb
Host smart-e37d8974-dbd6-4889-9513-a67657018e14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668394890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2668394890
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2930128473
Short name T384
Test name
Test status
Simulation time 13284992 ps
CPU time 0.84 seconds
Started Aug 07 06:15:32 PM PDT 24
Finished Aug 07 06:15:33 PM PDT 24
Peak memory 209076 kb
Host smart-ed04c737-dc37-470b-929d-86afa3eaa29f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930128473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2930128473
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3917820043
Short name T826
Test name
Test status
Simulation time 19118786 ps
CPU time 1.18 seconds
Started Aug 07 06:15:33 PM PDT 24
Finished Aug 07 06:15:35 PM PDT 24
Peak memory 208972 kb
Host smart-11236289-3f20-4110-a76e-33a689cc4afe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917820043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3917820043
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.679467448
Short name T728
Test name
Test status
Simulation time 249519700 ps
CPU time 10.38 seconds
Started Aug 07 06:15:29 PM PDT 24
Finished Aug 07 06:15:40 PM PDT 24
Peak memory 218184 kb
Host smart-a34f7afe-8ce8-4612-a6ba-194709603254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679467448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.679467448
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2714049920
Short name T657
Test name
Test status
Simulation time 37217566 ps
CPU time 1.19 seconds
Started Aug 07 06:15:32 PM PDT 24
Finished Aug 07 06:15:34 PM PDT 24
Peak memory 217116 kb
Host smart-be8b973a-e20c-43a9-9e19-dbadd84e824b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714049920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2714049920
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3147649373
Short name T865
Test name
Test status
Simulation time 57952840 ps
CPU time 2.51 seconds
Started Aug 07 06:15:33 PM PDT 24
Finished Aug 07 06:15:36 PM PDT 24
Peak memory 218204 kb
Host smart-48b0b835-8a3d-4cde-923f-f07cb0c070bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147649373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3147649373
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.273291131
Short name T429
Test name
Test status
Simulation time 1964875323 ps
CPU time 17.59 seconds
Started Aug 07 06:15:32 PM PDT 24
Finished Aug 07 06:15:50 PM PDT 24
Peak memory 218864 kb
Host smart-be7e406f-e008-4747-b12d-8382f53e1010
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273291131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.273291131
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1762397076
Short name T494
Test name
Test status
Simulation time 1101259200 ps
CPU time 8.37 seconds
Started Aug 07 06:15:31 PM PDT 24
Finished Aug 07 06:15:40 PM PDT 24
Peak memory 225952 kb
Host smart-34d614c6-31d0-46bd-8730-5026bfd4051f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762397076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1762397076
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.185354574
Short name T451
Test name
Test status
Simulation time 296422584 ps
CPU time 11.36 seconds
Started Aug 07 06:15:33 PM PDT 24
Finished Aug 07 06:15:45 PM PDT 24
Peak memory 217988 kb
Host smart-24057b55-7c2e-4d4a-b12c-871a33f2bff1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185354574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.185354574
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.4133218096
Short name T575
Test name
Test status
Simulation time 24441489 ps
CPU time 1.3 seconds
Started Aug 07 06:15:35 PM PDT 24
Finished Aug 07 06:15:36 PM PDT 24
Peak memory 213708 kb
Host smart-90142fa8-d178-4b5e-9965-bedc8ee4bc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133218096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.4133218096
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.556199519
Short name T590
Test name
Test status
Simulation time 345813741 ps
CPU time 32.93 seconds
Started Aug 07 06:15:34 PM PDT 24
Finished Aug 07 06:16:08 PM PDT 24
Peak memory 246236 kb
Host smart-435a9fc4-2419-4524-a040-9dcc165a43dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556199519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.556199519
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.524589967
Short name T685
Test name
Test status
Simulation time 170565486 ps
CPU time 4.35 seconds
Started Aug 07 06:15:33 PM PDT 24
Finished Aug 07 06:15:38 PM PDT 24
Peak memory 222692 kb
Host smart-19a4a7c7-32c5-4bd9-9410-9a7d4f0f43e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524589967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.524589967
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1547589241
Short name T747
Test name
Test status
Simulation time 667635609 ps
CPU time 39.6 seconds
Started Aug 07 06:15:33 PM PDT 24
Finished Aug 07 06:16:13 PM PDT 24
Peak memory 250864 kb
Host smart-a28b313b-edd2-4737-9029-46480248627a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547589241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1547589241
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2883954157
Short name T93
Test name
Test status
Simulation time 39816866223 ps
CPU time 703.43 seconds
Started Aug 07 06:15:30 PM PDT 24
Finished Aug 07 06:27:14 PM PDT 24
Peak memory 276552 kb
Host smart-b83f68c5-0705-4955-9ce1-9b2f76ae9d96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2883954157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.2883954157
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1405647861
Short name T33
Test name
Test status
Simulation time 26901477 ps
CPU time 1.08 seconds
Started Aug 07 06:15:33 PM PDT 24
Finished Aug 07 06:15:35 PM PDT 24
Peak memory 217700 kb
Host smart-edd08f55-5db2-4f65-9fe0-49cab875b10d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405647861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1405647861
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.627992475
Short name T289
Test name
Test status
Simulation time 119054818 ps
CPU time 0.95 seconds
Started Aug 07 06:15:41 PM PDT 24
Finished Aug 07 06:15:42 PM PDT 24
Peak memory 208836 kb
Host smart-7caee762-a864-43c2-9deb-feb0ba065b20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627992475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.627992475
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2125647496
Short name T530
Test name
Test status
Simulation time 351799107 ps
CPU time 7.75 seconds
Started Aug 07 06:15:39 PM PDT 24
Finished Aug 07 06:15:47 PM PDT 24
Peak memory 218136 kb
Host smart-37060c49-e297-4dad-88f9-0668892517e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125647496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2125647496
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.953847319
Short name T338
Test name
Test status
Simulation time 991954518 ps
CPU time 7.37 seconds
Started Aug 07 06:15:38 PM PDT 24
Finished Aug 07 06:15:46 PM PDT 24
Peak memory 217332 kb
Host smart-e9a3f734-c444-4759-9554-f684bb8d9cde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953847319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.953847319
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3505008108
Short name T568
Test name
Test status
Simulation time 347094258 ps
CPU time 3.23 seconds
Started Aug 07 06:15:43 PM PDT 24
Finished Aug 07 06:15:46 PM PDT 24
Peak memory 217680 kb
Host smart-3a6b265c-f8cb-498e-a7b7-941044ad85ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505008108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3505008108
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2767301666
Short name T604
Test name
Test status
Simulation time 2340567548 ps
CPU time 16.02 seconds
Started Aug 07 06:15:35 PM PDT 24
Finished Aug 07 06:15:51 PM PDT 24
Peak memory 226052 kb
Host smart-02992dc9-2cf0-45b0-af90-1a49453a47a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767301666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2767301666
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1028350061
Short name T713
Test name
Test status
Simulation time 338699810 ps
CPU time 13.3 seconds
Started Aug 07 06:15:40 PM PDT 24
Finished Aug 07 06:15:53 PM PDT 24
Peak memory 225952 kb
Host smart-0358f29d-0c6a-4e58-9196-f320342d208c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028350061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1028350061
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3175879543
Short name T336
Test name
Test status
Simulation time 605216764 ps
CPU time 12.35 seconds
Started Aug 07 06:15:42 PM PDT 24
Finished Aug 07 06:15:54 PM PDT 24
Peak memory 218204 kb
Host smart-f630b2d3-7568-4deb-a14a-7adc848230e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175879543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3175879543
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2563504602
Short name T616
Test name
Test status
Simulation time 792388114 ps
CPU time 5.69 seconds
Started Aug 07 06:15:39 PM PDT 24
Finished Aug 07 06:15:45 PM PDT 24
Peak memory 224768 kb
Host smart-3cb763b7-b6a4-4ece-a002-ac7582fdc95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563504602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2563504602
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.684941226
Short name T503
Test name
Test status
Simulation time 49626896 ps
CPU time 2.01 seconds
Started Aug 07 06:15:35 PM PDT 24
Finished Aug 07 06:15:37 PM PDT 24
Peak memory 217664 kb
Host smart-6f07446c-8499-4930-8cfb-0f3e560798ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684941226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.684941226
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2979836922
Short name T31
Test name
Test status
Simulation time 167188845 ps
CPU time 23.39 seconds
Started Aug 07 06:15:33 PM PDT 24
Finished Aug 07 06:15:56 PM PDT 24
Peak memory 250912 kb
Host smart-b42b2ee0-6e7c-4db3-9ac2-ea1fd019a605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979836922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2979836922
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.167375672
Short name T259
Test name
Test status
Simulation time 231006203 ps
CPU time 7.03 seconds
Started Aug 07 06:15:39 PM PDT 24
Finished Aug 07 06:15:47 PM PDT 24
Peak memory 250340 kb
Host smart-0313a3fd-dd8e-4337-92da-c5da4075f553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167375672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.167375672
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1150087807
Short name T43
Test name
Test status
Simulation time 167904061 ps
CPU time 0.86 seconds
Started Aug 07 06:15:33 PM PDT 24
Finished Aug 07 06:15:34 PM PDT 24
Peak memory 211860 kb
Host smart-2b85e967-dc24-4b33-b30d-9fe6aa1b283f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150087807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1150087807
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2804907174
Short name T659
Test name
Test status
Simulation time 88689828 ps
CPU time 0.95 seconds
Started Aug 07 06:15:42 PM PDT 24
Finished Aug 07 06:15:43 PM PDT 24
Peak memory 208960 kb
Host smart-81188328-7273-4c5e-8dcf-bec150049585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804907174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2804907174
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.878282844
Short name T301
Test name
Test status
Simulation time 2030909840 ps
CPU time 15.19 seconds
Started Aug 07 06:15:38 PM PDT 24
Finished Aug 07 06:15:53 PM PDT 24
Peak memory 218200 kb
Host smart-a8dce93b-4c37-4d0e-9d29-607febf167dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878282844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.878282844
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1552906557
Short name T271
Test name
Test status
Simulation time 443983740 ps
CPU time 2.24 seconds
Started Aug 07 06:15:43 PM PDT 24
Finished Aug 07 06:15:45 PM PDT 24
Peak memory 217128 kb
Host smart-8d39ecb3-36f2-4eef-8a0a-51840b4ca848
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552906557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1552906557
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2640888013
Short name T720
Test name
Test status
Simulation time 103609610 ps
CPU time 2.35 seconds
Started Aug 07 06:15:39 PM PDT 24
Finished Aug 07 06:15:42 PM PDT 24
Peak memory 222292 kb
Host smart-23dce8ed-b828-4f98-822d-2de1631766fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640888013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2640888013
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1071446755
Short name T508
Test name
Test status
Simulation time 706750585 ps
CPU time 7.39 seconds
Started Aug 07 06:15:39 PM PDT 24
Finished Aug 07 06:15:47 PM PDT 24
Peak memory 225924 kb
Host smart-11d95db5-1c5f-4cb8-83dc-6de9a6bba4e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071446755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1071446755
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2568787880
Short name T805
Test name
Test status
Simulation time 1972544996 ps
CPU time 24.55 seconds
Started Aug 07 06:15:36 PM PDT 24
Finished Aug 07 06:16:01 PM PDT 24
Peak memory 225964 kb
Host smart-6d411a1a-1886-4ca0-b58d-fb59e89d69db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568787880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2568787880
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2935550668
Short name T829
Test name
Test status
Simulation time 233731359 ps
CPU time 6.71 seconds
Started Aug 07 06:15:40 PM PDT 24
Finished Aug 07 06:15:47 PM PDT 24
Peak memory 225960 kb
Host smart-d5612a0e-3d61-4aa2-b0f4-6549e0aab650
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935550668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2935550668
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2262278824
Short name T56
Test name
Test status
Simulation time 441732716 ps
CPU time 11.65 seconds
Started Aug 07 06:15:36 PM PDT 24
Finished Aug 07 06:15:47 PM PDT 24
Peak memory 218304 kb
Host smart-09ca036f-de17-4a91-9d13-49be2a938d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262278824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2262278824
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2705616899
Short name T871
Test name
Test status
Simulation time 67507197 ps
CPU time 1.31 seconds
Started Aug 07 06:15:42 PM PDT 24
Finished Aug 07 06:15:43 PM PDT 24
Peak memory 213684 kb
Host smart-edeb59e8-cca4-40e2-9b70-dab56068221c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705616899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2705616899
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2000047287
Short name T222
Test name
Test status
Simulation time 727215436 ps
CPU time 31.52 seconds
Started Aug 07 06:15:38 PM PDT 24
Finished Aug 07 06:16:10 PM PDT 24
Peak memory 250864 kb
Host smart-3b65cfdd-06aa-4349-b3ad-f34a12f50fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000047287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2000047287
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2051427588
Short name T246
Test name
Test status
Simulation time 287460262 ps
CPU time 8.21 seconds
Started Aug 07 06:15:43 PM PDT 24
Finished Aug 07 06:15:51 PM PDT 24
Peak memory 243364 kb
Host smart-5232e144-24dc-47a8-b851-a8d7846eb06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051427588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2051427588
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2814529171
Short name T492
Test name
Test status
Simulation time 19780445702 ps
CPU time 107.21 seconds
Started Aug 07 06:15:39 PM PDT 24
Finished Aug 07 06:17:27 PM PDT 24
Peak memory 283488 kb
Host smart-c5f234ee-4729-448d-9ed5-2c1c4aac6bfd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814529171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2814529171
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3900889464
Short name T695
Test name
Test status
Simulation time 35735902 ps
CPU time 0.87 seconds
Started Aug 07 06:15:38 PM PDT 24
Finished Aug 07 06:15:39 PM PDT 24
Peak memory 208904 kb
Host smart-a9dcc286-5b5f-4a52-b05a-af7543f99bb5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900889464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3900889464
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3551128889
Short name T474
Test name
Test status
Simulation time 16912323 ps
CPU time 1.1 seconds
Started Aug 07 06:15:44 PM PDT 24
Finished Aug 07 06:15:45 PM PDT 24
Peak memory 208948 kb
Host smart-4b97f2eb-f4d9-409a-8960-2da17ad3c7ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551128889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3551128889
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.870222564
Short name T230
Test name
Test status
Simulation time 674040562 ps
CPU time 14.73 seconds
Started Aug 07 06:15:44 PM PDT 24
Finished Aug 07 06:15:58 PM PDT 24
Peak memory 218260 kb
Host smart-62fd017b-3d65-4f60-a3a7-8767191904a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870222564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.870222564
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2207520623
Short name T733
Test name
Test status
Simulation time 1207346146 ps
CPU time 3.84 seconds
Started Aug 07 06:15:47 PM PDT 24
Finished Aug 07 06:15:51 PM PDT 24
Peak memory 217104 kb
Host smart-a6b98862-73ea-48fa-a8b0-81ef892c511b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207520623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2207520623
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.4149044282
Short name T788
Test name
Test status
Simulation time 19596375 ps
CPU time 1.54 seconds
Started Aug 07 06:15:44 PM PDT 24
Finished Aug 07 06:15:46 PM PDT 24
Peak memory 221780 kb
Host smart-d6f9b8d5-6350-42d9-9a37-128330ee77e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149044282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.4149044282
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.430809920
Short name T707
Test name
Test status
Simulation time 695919063 ps
CPU time 21.48 seconds
Started Aug 07 06:15:49 PM PDT 24
Finished Aug 07 06:16:10 PM PDT 24
Peak memory 218780 kb
Host smart-c3c89893-574a-43f0-b733-de6c3ae43115
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430809920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.430809920
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2294230269
Short name T874
Test name
Test status
Simulation time 275529053 ps
CPU time 9.31 seconds
Started Aug 07 06:15:45 PM PDT 24
Finished Aug 07 06:15:54 PM PDT 24
Peak memory 225844 kb
Host smart-5fedd042-a079-4c81-8b58-e93bc69bdd8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294230269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2294230269
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1216674031
Short name T813
Test name
Test status
Simulation time 350963075 ps
CPU time 12.79 seconds
Started Aug 07 06:15:44 PM PDT 24
Finished Aug 07 06:15:57 PM PDT 24
Peak memory 218160 kb
Host smart-d6b52449-43fc-4fff-8e24-04340ace62da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216674031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1216674031
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1146733952
Short name T155
Test name
Test status
Simulation time 400369286 ps
CPU time 9.14 seconds
Started Aug 07 06:15:47 PM PDT 24
Finished Aug 07 06:15:56 PM PDT 24
Peak memory 218472 kb
Host smart-7015c436-598e-4512-ae5d-27888672a730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146733952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1146733952
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.317672379
Short name T85
Test name
Test status
Simulation time 100755595 ps
CPU time 4.84 seconds
Started Aug 07 06:15:39 PM PDT 24
Finished Aug 07 06:15:44 PM PDT 24
Peak memory 214504 kb
Host smart-e2bbd242-807c-4637-be97-60703c28da38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317672379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.317672379
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2874157737
Short name T447
Test name
Test status
Simulation time 322838078 ps
CPU time 31.08 seconds
Started Aug 07 06:15:39 PM PDT 24
Finished Aug 07 06:16:10 PM PDT 24
Peak memory 250828 kb
Host smart-ffc1b8fb-1c36-41f8-826b-a4f7b1d89896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874157737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2874157737
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1440840202
Short name T555
Test name
Test status
Simulation time 59616796 ps
CPU time 7.21 seconds
Started Aug 07 06:15:48 PM PDT 24
Finished Aug 07 06:15:55 PM PDT 24
Peak memory 250964 kb
Host smart-87262b30-56b5-4b44-9b7e-c11c73c907d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440840202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1440840202
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3800667472
Short name T220
Test name
Test status
Simulation time 7087005886 ps
CPU time 111.08 seconds
Started Aug 07 06:15:44 PM PDT 24
Finished Aug 07 06:17:36 PM PDT 24
Peak memory 250916 kb
Host smart-60a1e834-5cf0-4477-bfe7-a6dd1f7ed8b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800667472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3800667472
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2001824016
Short name T845
Test name
Test status
Simulation time 36895796 ps
CPU time 0.88 seconds
Started Aug 07 06:15:39 PM PDT 24
Finished Aug 07 06:15:40 PM PDT 24
Peak memory 209056 kb
Host smart-e15fab2f-6024-41c4-ab29-f239cb10f53c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001824016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2001824016
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2957702669
Short name T589
Test name
Test status
Simulation time 41499858 ps
CPU time 0.84 seconds
Started Aug 07 06:13:46 PM PDT 24
Finished Aug 07 06:13:47 PM PDT 24
Peak memory 208672 kb
Host smart-8b19f5f5-3f04-43cd-9d7e-d79f852b000a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957702669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2957702669
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1108980665
Short name T629
Test name
Test status
Simulation time 501270900 ps
CPU time 12.69 seconds
Started Aug 07 06:13:37 PM PDT 24
Finished Aug 07 06:13:50 PM PDT 24
Peak memory 218164 kb
Host smart-d4a45949-a988-48cf-9df3-0ad57fa34a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108980665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1108980665
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.670341951
Short name T23
Test name
Test status
Simulation time 630020259 ps
CPU time 7.24 seconds
Started Aug 07 06:13:38 PM PDT 24
Finished Aug 07 06:13:45 PM PDT 24
Peak memory 217316 kb
Host smart-54f3f6fd-8ba3-4069-b8c3-096ade21f71c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670341951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.670341951
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.28019673
Short name T351
Test name
Test status
Simulation time 4819330716 ps
CPU time 32.1 seconds
Started Aug 07 06:13:36 PM PDT 24
Finished Aug 07 06:14:09 PM PDT 24
Peak memory 225916 kb
Host smart-f6b4662e-ae94-4b89-a543-ee8cb9e75e0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28019673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_erro
rs.28019673
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3964097860
Short name T536
Test name
Test status
Simulation time 851422405 ps
CPU time 19.26 seconds
Started Aug 07 06:13:38 PM PDT 24
Finished Aug 07 06:13:58 PM PDT 24
Peak memory 217680 kb
Host smart-9a621de7-9e1c-4ada-a044-d9ec816d98f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964097860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
964097860
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.179752930
Short name T225
Test name
Test status
Simulation time 249682411 ps
CPU time 8.36 seconds
Started Aug 07 06:13:39 PM PDT 24
Finished Aug 07 06:13:48 PM PDT 24
Peak memory 223028 kb
Host smart-f8fc4252-0c36-412b-91c3-1a539e44ca8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179752930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.179752930
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.200956084
Short name T382
Test name
Test status
Simulation time 1578872594 ps
CPU time 10.81 seconds
Started Aug 07 06:13:36 PM PDT 24
Finished Aug 07 06:13:47 PM PDT 24
Peak memory 217476 kb
Host smart-10a0c445-59eb-40d9-9d20-b974290a4c8d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200956084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.200956084
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3041341090
Short name T153
Test name
Test status
Simulation time 338137723 ps
CPU time 7.86 seconds
Started Aug 07 06:13:35 PM PDT 24
Finished Aug 07 06:13:43 PM PDT 24
Peak memory 217496 kb
Host smart-fb9ea1b5-20f4-438b-b33c-b7eb132ffb59
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041341090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3041341090
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.4054223196
Short name T653
Test name
Test status
Simulation time 1455830989 ps
CPU time 55.2 seconds
Started Aug 07 06:13:40 PM PDT 24
Finished Aug 07 06:14:36 PM PDT 24
Peak memory 253740 kb
Host smart-dee458b7-1cc6-4500-9726-9a84516b4b5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054223196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.4054223196
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2550063712
Short name T241
Test name
Test status
Simulation time 1119386804 ps
CPU time 17.01 seconds
Started Aug 07 06:13:39 PM PDT 24
Finished Aug 07 06:13:56 PM PDT 24
Peak memory 250332 kb
Host smart-2687576b-6e93-4d14-8a0e-2b7b81303aac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550063712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2550063712
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3512217067
Short name T514
Test name
Test status
Simulation time 369729288 ps
CPU time 3.21 seconds
Started Aug 07 06:13:38 PM PDT 24
Finished Aug 07 06:13:42 PM PDT 24
Peak memory 218196 kb
Host smart-7194063b-e428-4208-8e60-42750effb83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512217067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3512217067
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1484096880
Short name T648
Test name
Test status
Simulation time 882279735 ps
CPU time 13.4 seconds
Started Aug 07 06:13:34 PM PDT 24
Finished Aug 07 06:13:48 PM PDT 24
Peak memory 217640 kb
Host smart-cd49b9a0-7c88-4979-8fab-9c0f15a0b52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484096880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1484096880
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.166679619
Short name T97
Test name
Test status
Simulation time 459315242 ps
CPU time 21.17 seconds
Started Aug 07 06:13:45 PM PDT 24
Finished Aug 07 06:14:07 PM PDT 24
Peak memory 282244 kb
Host smart-92d71933-c82a-4cb5-922f-e13fb0eb8450
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166679619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.166679619
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1144846447
Short name T256
Test name
Test status
Simulation time 3610494610 ps
CPU time 17.27 seconds
Started Aug 07 06:13:49 PM PDT 24
Finished Aug 07 06:14:06 PM PDT 24
Peak memory 226068 kb
Host smart-69219ca0-0bfa-4e29-90ea-93a444abff8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144846447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1144846447
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1253863474
Short name T863
Test name
Test status
Simulation time 446512591 ps
CPU time 12.79 seconds
Started Aug 07 06:13:46 PM PDT 24
Finished Aug 07 06:13:59 PM PDT 24
Peak memory 225952 kb
Host smart-97573ffc-7213-4b0a-9fa3-73c482ce8a7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253863474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1253863474
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2930116145
Short name T279
Test name
Test status
Simulation time 1079074813 ps
CPU time 7.66 seconds
Started Aug 07 06:13:47 PM PDT 24
Finished Aug 07 06:13:54 PM PDT 24
Peak memory 218132 kb
Host smart-434193c9-f72e-487d-b059-ef7151cb8098
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930116145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
930116145
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2385239688
Short name T796
Test name
Test status
Simulation time 413655696 ps
CPU time 14.34 seconds
Started Aug 07 06:13:39 PM PDT 24
Finished Aug 07 06:13:53 PM PDT 24
Peak memory 218260 kb
Host smart-7fe02da4-dff9-4c99-8789-d81bc459e5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385239688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2385239688
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2681774479
Short name T395
Test name
Test status
Simulation time 362172001 ps
CPU time 5.56 seconds
Started Aug 07 06:13:40 PM PDT 24
Finished Aug 07 06:13:46 PM PDT 24
Peak memory 217640 kb
Host smart-9373d17d-fb5c-4148-8897-f6de249b5e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681774479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2681774479
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3887217654
Short name T827
Test name
Test status
Simulation time 807586950 ps
CPU time 25.26 seconds
Started Aug 07 06:13:38 PM PDT 24
Finished Aug 07 06:14:03 PM PDT 24
Peak memory 250736 kb
Host smart-d7801a0e-25cc-45d0-81af-2c111a45e641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887217654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3887217654
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.169829043
Short name T773
Test name
Test status
Simulation time 141831953 ps
CPU time 8.24 seconds
Started Aug 07 06:13:39 PM PDT 24
Finished Aug 07 06:13:47 PM PDT 24
Peak memory 250836 kb
Host smart-ffc778f4-fef7-4d54-9e77-11837f04c543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169829043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.169829043
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2686635672
Short name T401
Test name
Test status
Simulation time 85380229085 ps
CPU time 397.66 seconds
Started Aug 07 06:13:47 PM PDT 24
Finished Aug 07 06:20:25 PM PDT 24
Peak memory 372708 kb
Host smart-1e0f0e13-835e-4c0f-baf1-e67e6fa86661
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686635672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2686635672
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3593758593
Short name T817
Test name
Test status
Simulation time 25768073 ps
CPU time 0.8 seconds
Started Aug 07 06:13:36 PM PDT 24
Finished Aug 07 06:13:37 PM PDT 24
Peak memory 208860 kb
Host smart-95a72add-0f2c-4adc-aa53-d7feac3ca1df
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593758593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.3593758593
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.656981963
Short name T237
Test name
Test status
Simulation time 93102979 ps
CPU time 0.98 seconds
Started Aug 07 06:15:45 PM PDT 24
Finished Aug 07 06:15:46 PM PDT 24
Peak memory 208816 kb
Host smart-a7622d60-9704-46fc-87c2-a5522ff10cd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656981963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.656981963
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.672202111
Short name T772
Test name
Test status
Simulation time 1236740313 ps
CPU time 12.75 seconds
Started Aug 07 06:15:44 PM PDT 24
Finished Aug 07 06:15:57 PM PDT 24
Peak memory 226032 kb
Host smart-e500b5e5-61b9-4c4d-ae20-3e4d4f097d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672202111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.672202111
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.4053786124
Short name T502
Test name
Test status
Simulation time 422901349 ps
CPU time 3.01 seconds
Started Aug 07 06:15:45 PM PDT 24
Finished Aug 07 06:15:48 PM PDT 24
Peak memory 217016 kb
Host smart-c8377c38-2f7e-4769-bf85-603926d671d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053786124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.4053786124
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3417548597
Short name T769
Test name
Test status
Simulation time 23858957 ps
CPU time 1.77 seconds
Started Aug 07 06:15:44 PM PDT 24
Finished Aug 07 06:15:46 PM PDT 24
Peak memory 218112 kb
Host smart-b9940328-504f-4104-b98b-51dc6c3ea015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417548597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3417548597
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1985448249
Short name T100
Test name
Test status
Simulation time 4569761840 ps
CPU time 13 seconds
Started Aug 07 06:15:45 PM PDT 24
Finished Aug 07 06:15:58 PM PDT 24
Peak memory 219212 kb
Host smart-6660926e-c6d3-4690-8d37-73e544bcf7fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985448249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1985448249
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3733106429
Short name T298
Test name
Test status
Simulation time 272466513 ps
CPU time 8.76 seconds
Started Aug 07 06:15:44 PM PDT 24
Finished Aug 07 06:15:53 PM PDT 24
Peak memory 225920 kb
Host smart-7a070c6b-4014-4036-a337-79668acb7b99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733106429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3733106429
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1115211132
Short name T295
Test name
Test status
Simulation time 443301151 ps
CPU time 6.31 seconds
Started Aug 07 06:15:44 PM PDT 24
Finished Aug 07 06:15:51 PM PDT 24
Peak memory 218068 kb
Host smart-a3131491-9559-4566-9cb6-31903872099d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115211132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1115211132
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.958827041
Short name T323
Test name
Test status
Simulation time 241927389 ps
CPU time 7.19 seconds
Started Aug 07 06:15:44 PM PDT 24
Finished Aug 07 06:15:51 PM PDT 24
Peak memory 218192 kb
Host smart-f15422f2-a907-4399-a7fd-1d9c302219b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958827041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.958827041
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3194865504
Short name T453
Test name
Test status
Simulation time 64392044 ps
CPU time 2.06 seconds
Started Aug 07 06:15:46 PM PDT 24
Finished Aug 07 06:15:48 PM PDT 24
Peak memory 217648 kb
Host smart-ce373b23-d1b9-4a31-9846-75574dd60a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194865504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3194865504
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2239587778
Short name T302
Test name
Test status
Simulation time 266177716 ps
CPU time 30.51 seconds
Started Aug 07 06:15:45 PM PDT 24
Finished Aug 07 06:16:15 PM PDT 24
Peak memory 250844 kb
Host smart-867ab157-79c2-4416-9c4c-cdd76a949b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239587778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2239587778
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3182540978
Short name T755
Test name
Test status
Simulation time 61342369 ps
CPU time 4.17 seconds
Started Aug 07 06:15:44 PM PDT 24
Finished Aug 07 06:15:48 PM PDT 24
Peak memory 222260 kb
Host smart-578aa53d-e4f3-460e-86ec-78854b0b91ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182540978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3182540978
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2884043888
Short name T95
Test name
Test status
Simulation time 25568628186 ps
CPU time 127.53 seconds
Started Aug 07 06:15:43 PM PDT 24
Finished Aug 07 06:17:51 PM PDT 24
Peak memory 283680 kb
Host smart-afeb7ff1-1bd7-40f0-a5f7-773b34c5e548
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884043888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2884043888
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3965334196
Short name T146
Test name
Test status
Simulation time 145725296247 ps
CPU time 861.04 seconds
Started Aug 07 06:15:45 PM PDT 24
Finished Aug 07 06:30:07 PM PDT 24
Peak memory 513236 kb
Host smart-3e946399-35e7-473d-ad05-c2b3178eea96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3965334196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.3965334196
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1958689805
Short name T35
Test name
Test status
Simulation time 39913381 ps
CPU time 0.9 seconds
Started Aug 07 06:15:45 PM PDT 24
Finished Aug 07 06:15:46 PM PDT 24
Peak memory 208740 kb
Host smart-da612295-8bf6-4f67-aa77-121a678dca5f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958689805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1958689805
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.663033171
Short name T606
Test name
Test status
Simulation time 25765074 ps
CPU time 1.25 seconds
Started Aug 07 06:15:50 PM PDT 24
Finished Aug 07 06:15:51 PM PDT 24
Peak memory 209000 kb
Host smart-6df6733b-58b3-4279-a827-654a1c3782ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663033171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.663033171
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2260119179
Short name T318
Test name
Test status
Simulation time 1537715486 ps
CPU time 10.94 seconds
Started Aug 07 06:15:43 PM PDT 24
Finished Aug 07 06:15:54 PM PDT 24
Peak memory 218288 kb
Host smart-48f6023b-d310-4868-b78a-6e7a5c9ced38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260119179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2260119179
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3075251773
Short name T854
Test name
Test status
Simulation time 515007633 ps
CPU time 2.08 seconds
Started Aug 07 06:15:49 PM PDT 24
Finished Aug 07 06:15:51 PM PDT 24
Peak memory 216920 kb
Host smart-dcb657ca-adda-4e01-8888-de24efb0b8a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075251773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3075251773
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3513578309
Short name T678
Test name
Test status
Simulation time 260099305 ps
CPU time 2.98 seconds
Started Aug 07 06:15:46 PM PDT 24
Finished Aug 07 06:15:49 PM PDT 24
Peak memory 218268 kb
Host smart-e6a4ca89-7995-4bdf-9644-77ad1ca77f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513578309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3513578309
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.295607178
Short name T497
Test name
Test status
Simulation time 349790404 ps
CPU time 8.16 seconds
Started Aug 07 06:15:49 PM PDT 24
Finished Aug 07 06:15:57 PM PDT 24
Peak memory 225420 kb
Host smart-84c50258-c474-43be-a29f-d9390dc39c49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295607178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.295607178
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.370464912
Short name T808
Test name
Test status
Simulation time 3221353420 ps
CPU time 17.53 seconds
Started Aug 07 06:15:50 PM PDT 24
Finished Aug 07 06:16:08 PM PDT 24
Peak memory 226008 kb
Host smart-5bd764cb-f04d-4050-bb8d-ad5c70a70faa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370464912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.370464912
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2640576150
Short name T232
Test name
Test status
Simulation time 282665912 ps
CPU time 8.75 seconds
Started Aug 07 06:15:48 PM PDT 24
Finished Aug 07 06:15:57 PM PDT 24
Peak memory 218156 kb
Host smart-c3939447-80e2-4243-8b2f-6593e2f80f63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640576150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2640576150
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.191872591
Short name T332
Test name
Test status
Simulation time 1920413886 ps
CPU time 8.17 seconds
Started Aug 07 06:15:52 PM PDT 24
Finished Aug 07 06:16:00 PM PDT 24
Peak memory 224920 kb
Host smart-ddd6c62e-f631-4ac3-9f0e-8c3bcdc8520d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191872591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.191872591
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3050362168
Short name T328
Test name
Test status
Simulation time 572828377 ps
CPU time 2.29 seconds
Started Aug 07 06:15:44 PM PDT 24
Finished Aug 07 06:15:46 PM PDT 24
Peak memory 214304 kb
Host smart-05220406-5685-4eab-b7fb-893602557687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050362168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3050362168
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3438511106
Short name T668
Test name
Test status
Simulation time 546392829 ps
CPU time 32.37 seconds
Started Aug 07 06:15:46 PM PDT 24
Finished Aug 07 06:16:19 PM PDT 24
Peak memory 250840 kb
Host smart-bd4ecd1c-8b1d-4bdb-b48c-c6f965394722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438511106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3438511106
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3340321101
Short name T528
Test name
Test status
Simulation time 62221061 ps
CPU time 7.31 seconds
Started Aug 07 06:15:44 PM PDT 24
Finished Aug 07 06:15:51 PM PDT 24
Peak memory 250856 kb
Host smart-3a458ee3-f1e7-4031-b449-7fae0e98a188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340321101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3340321101
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1051761689
Short name T726
Test name
Test status
Simulation time 4948557122 ps
CPU time 94.56 seconds
Started Aug 07 06:15:51 PM PDT 24
Finished Aug 07 06:17:25 PM PDT 24
Peak memory 250868 kb
Host smart-cc4e59a4-1330-4520-bfaf-5968657d19cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051761689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1051761689
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4135133523
Short name T36
Test name
Test status
Simulation time 15101594 ps
CPU time 0.8 seconds
Started Aug 07 06:15:47 PM PDT 24
Finished Aug 07 06:15:48 PM PDT 24
Peak memory 208644 kb
Host smart-2cfd4aeb-2733-4004-8464-243f674d8f71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135133523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.4135133523
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.30662956
Short name T47
Test name
Test status
Simulation time 627327250 ps
CPU time 15.97 seconds
Started Aug 07 06:15:48 PM PDT 24
Finished Aug 07 06:16:05 PM PDT 24
Peak memory 218148 kb
Host smart-a2b6be9f-1356-4532-bf32-3fff85b3a250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30662956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.30662956
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3687815027
Short name T586
Test name
Test status
Simulation time 910154240 ps
CPU time 5.91 seconds
Started Aug 07 06:15:49 PM PDT 24
Finished Aug 07 06:15:55 PM PDT 24
Peak memory 217000 kb
Host smart-ab5551f5-618e-4928-873a-7dd3355748d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687815027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3687815027
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3798582080
Short name T387
Test name
Test status
Simulation time 113325806 ps
CPU time 3.14 seconds
Started Aug 07 06:15:53 PM PDT 24
Finished Aug 07 06:15:57 PM PDT 24
Peak memory 218160 kb
Host smart-aea2d50a-8437-4b0a-9fb4-0cc8453f911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798582080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3798582080
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2541339008
Short name T789
Test name
Test status
Simulation time 505582836 ps
CPU time 15.11 seconds
Started Aug 07 06:15:54 PM PDT 24
Finished Aug 07 06:16:09 PM PDT 24
Peak memory 226196 kb
Host smart-929b7e85-c6ad-4430-b3ce-4fe2d89952c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541339008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2541339008
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3953888912
Short name T583
Test name
Test status
Simulation time 1669307263 ps
CPU time 15.58 seconds
Started Aug 07 06:15:50 PM PDT 24
Finished Aug 07 06:16:06 PM PDT 24
Peak memory 225972 kb
Host smart-4f45b31c-ee67-4974-bcc2-63233b6bbac0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953888912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3953888912
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3257545924
Short name T663
Test name
Test status
Simulation time 2319313280 ps
CPU time 7.94 seconds
Started Aug 07 06:15:53 PM PDT 24
Finished Aug 07 06:16:01 PM PDT 24
Peak memory 226020 kb
Host smart-8f95ce77-d02c-446f-a968-e0d913e6f047
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257545924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3257545924
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3664409089
Short name T666
Test name
Test status
Simulation time 243099428 ps
CPU time 6.98 seconds
Started Aug 07 06:15:49 PM PDT 24
Finished Aug 07 06:15:56 PM PDT 24
Peak memory 225164 kb
Host smart-8486731a-fefa-4944-b958-b7e78cd1004d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664409089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3664409089
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2201140910
Short name T618
Test name
Test status
Simulation time 64543316 ps
CPU time 2.17 seconds
Started Aug 07 06:15:51 PM PDT 24
Finished Aug 07 06:15:53 PM PDT 24
Peak memory 217660 kb
Host smart-0751bb25-4bda-4120-931a-2a2fdff0404e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201140910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2201140910
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.2184440102
Short name T601
Test name
Test status
Simulation time 325360651 ps
CPU time 28.38 seconds
Started Aug 07 06:15:47 PM PDT 24
Finished Aug 07 06:16:16 PM PDT 24
Peak memory 250844 kb
Host smart-02f37cc8-575e-4fbb-b0b0-d7ac74b5b77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184440102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2184440102
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1417335611
Short name T425
Test name
Test status
Simulation time 116029181 ps
CPU time 7.71 seconds
Started Aug 07 06:15:51 PM PDT 24
Finished Aug 07 06:15:59 PM PDT 24
Peak memory 250680 kb
Host smart-58936644-1eff-4ea5-b74c-4b6c76511c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417335611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1417335611
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2889292010
Short name T632
Test name
Test status
Simulation time 6580186940 ps
CPU time 231.31 seconds
Started Aug 07 06:15:51 PM PDT 24
Finished Aug 07 06:19:43 PM PDT 24
Peak memory 273972 kb
Host smart-e00b1e72-c64b-4b9d-b5b7-19925d690194
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889292010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2889292010
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.1011112832
Short name T681
Test name
Test status
Simulation time 21325998471 ps
CPU time 491.41 seconds
Started Aug 07 06:15:53 PM PDT 24
Finished Aug 07 06:24:04 PM PDT 24
Peak memory 447588 kb
Host smart-228c12e0-43a4-45d2-b5c5-832a521cf07c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1011112832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.1011112832
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3529857291
Short name T322
Test name
Test status
Simulation time 25472935 ps
CPU time 1.07 seconds
Started Aug 07 06:15:51 PM PDT 24
Finished Aug 07 06:15:52 PM PDT 24
Peak memory 211824 kb
Host smart-02ae7545-0c34-45a3-ac26-3198595cf057
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529857291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3529857291
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2650210008
Short name T175
Test name
Test status
Simulation time 23130785 ps
CPU time 0.84 seconds
Started Aug 07 06:16:00 PM PDT 24
Finished Aug 07 06:16:01 PM PDT 24
Peak memory 208640 kb
Host smart-2cf89780-7a0c-47bb-8711-e2239ab4898d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650210008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2650210008
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2178932336
Short name T787
Test name
Test status
Simulation time 1848256879 ps
CPU time 11.99 seconds
Started Aug 07 06:15:51 PM PDT 24
Finished Aug 07 06:16:03 PM PDT 24
Peak memory 225904 kb
Host smart-42432078-07e1-4a33-8f9f-f746d4542cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178932336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2178932336
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3365966692
Short name T354
Test name
Test status
Simulation time 161611720 ps
CPU time 2.06 seconds
Started Aug 07 06:15:52 PM PDT 24
Finished Aug 07 06:15:54 PM PDT 24
Peak memory 216800 kb
Host smart-3da783f1-90ca-48a6-912e-03aa6ee1a973
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365966692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3365966692
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1161818430
Short name T280
Test name
Test status
Simulation time 138085827 ps
CPU time 2.32 seconds
Started Aug 07 06:15:51 PM PDT 24
Finished Aug 07 06:15:53 PM PDT 24
Peak memory 218120 kb
Host smart-e1a5e0e4-1aca-47d8-8187-8cd1da3f69f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161818430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1161818430
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3884807875
Short name T426
Test name
Test status
Simulation time 716326763 ps
CPU time 16.28 seconds
Started Aug 07 06:15:55 PM PDT 24
Finished Aug 07 06:16:11 PM PDT 24
Peak memory 225956 kb
Host smart-57bafdd5-f8cd-4b26-8077-5041a3726aba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884807875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3884807875
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3780964903
Short name T408
Test name
Test status
Simulation time 880601266 ps
CPU time 9.93 seconds
Started Aug 07 06:15:56 PM PDT 24
Finished Aug 07 06:16:06 PM PDT 24
Peak memory 218164 kb
Host smart-474b0048-4fc1-4ba3-976e-cffdfcf55cf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780964903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3780964903
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3469969987
Short name T371
Test name
Test status
Simulation time 669576290 ps
CPU time 14.73 seconds
Started Aug 07 06:15:47 PM PDT 24
Finished Aug 07 06:16:02 PM PDT 24
Peak memory 226008 kb
Host smart-fa655ef5-074a-4c80-9136-c90a4695e3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469969987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3469969987
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.997414172
Short name T84
Test name
Test status
Simulation time 780653801 ps
CPU time 4.15 seconds
Started Aug 07 06:15:51 PM PDT 24
Finished Aug 07 06:15:55 PM PDT 24
Peak memory 217672 kb
Host smart-39313465-5aa0-41c6-9698-3066bedd5789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997414172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.997414172
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.4003121871
Short name T642
Test name
Test status
Simulation time 168320798 ps
CPU time 19.57 seconds
Started Aug 07 06:15:52 PM PDT 24
Finished Aug 07 06:16:12 PM PDT 24
Peak memory 250552 kb
Host smart-3d354fc0-a8b4-43e2-aed7-a3b8d4801c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003121871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.4003121871
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2428345299
Short name T517
Test name
Test status
Simulation time 61465017 ps
CPU time 6.72 seconds
Started Aug 07 06:15:49 PM PDT 24
Finished Aug 07 06:15:56 PM PDT 24
Peak memory 250712 kb
Host smart-184d48bb-6c4b-4977-af51-43b56a31f574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428345299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2428345299
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.952581116
Short name T491
Test name
Test status
Simulation time 15985205825 ps
CPU time 199.36 seconds
Started Aug 07 06:15:56 PM PDT 24
Finished Aug 07 06:19:16 PM PDT 24
Peak memory 283660 kb
Host smart-d3ea7f58-4f43-4ac8-bd24-c474b6560d52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952581116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.952581116
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1586827085
Short name T143
Test name
Test status
Simulation time 8347406392 ps
CPU time 282.4 seconds
Started Aug 07 06:15:56 PM PDT 24
Finished Aug 07 06:20:39 PM PDT 24
Peak memory 283776 kb
Host smart-289c4fb9-eda8-4be7-ae2f-90acad11e1df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1586827085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.1586827085
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.37932293
Short name T814
Test name
Test status
Simulation time 19404330 ps
CPU time 0.98 seconds
Started Aug 07 06:15:50 PM PDT 24
Finished Aug 07 06:15:51 PM PDT 24
Peak memory 211852 kb
Host smart-7ea793b8-81a1-4a3d-814b-81a289f66d69
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37932293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctr
l_volatile_unlock_smoke.37932293
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3091810407
Short name T74
Test name
Test status
Simulation time 45748555 ps
CPU time 0.84 seconds
Started Aug 07 06:16:10 PM PDT 24
Finished Aug 07 06:16:11 PM PDT 24
Peak memory 208660 kb
Host smart-ef752e2d-3721-4f91-8cb7-82584c12914e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091810407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3091810407
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1283327771
Short name T693
Test name
Test status
Simulation time 1827764753 ps
CPU time 11.06 seconds
Started Aug 07 06:15:56 PM PDT 24
Finished Aug 07 06:16:08 PM PDT 24
Peak memory 218212 kb
Host smart-d20077eb-4aee-4ee3-bcf8-d60d6df428d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283327771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1283327771
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.451617259
Short name T433
Test name
Test status
Simulation time 434888175 ps
CPU time 5.63 seconds
Started Aug 07 06:15:56 PM PDT 24
Finished Aug 07 06:16:02 PM PDT 24
Peak memory 217256 kb
Host smart-3c5b0891-69dc-4a6a-ae3c-76242cdb4b6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451617259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.451617259
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3738782150
Short name T815
Test name
Test status
Simulation time 16081878 ps
CPU time 1.44 seconds
Started Aug 07 06:15:58 PM PDT 24
Finished Aug 07 06:15:59 PM PDT 24
Peak memory 218296 kb
Host smart-ac1adb54-afee-42b5-9f10-8e6bcc76f1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738782150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3738782150
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2856469419
Short name T272
Test name
Test status
Simulation time 622191702 ps
CPU time 12.3 seconds
Started Aug 07 06:15:58 PM PDT 24
Finished Aug 07 06:16:10 PM PDT 24
Peak memory 226092 kb
Host smart-f7c893f0-477f-44cb-8f4d-dea861081410
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856469419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2856469419
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1455096186
Short name T231
Test name
Test status
Simulation time 920678824 ps
CPU time 10.95 seconds
Started Aug 07 06:15:56 PM PDT 24
Finished Aug 07 06:16:07 PM PDT 24
Peak memory 225972 kb
Host smart-cc8d7654-e5ea-429a-b5cf-ed26a9a6b39e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455096186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1455096186
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.921555837
Short name T162
Test name
Test status
Simulation time 258500979 ps
CPU time 10.43 seconds
Started Aug 07 06:15:56 PM PDT 24
Finished Aug 07 06:16:06 PM PDT 24
Peak memory 225964 kb
Host smart-9fa0f6a8-f3c2-4586-a895-9193498087f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921555837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.921555837
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2421952534
Short name T708
Test name
Test status
Simulation time 912807070 ps
CPU time 8.34 seconds
Started Aug 07 06:15:55 PM PDT 24
Finished Aug 07 06:16:04 PM PDT 24
Peak memory 226000 kb
Host smart-87a42e7d-8f0d-4935-83b8-c0321a273f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421952534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2421952534
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.643348730
Short name T63
Test name
Test status
Simulation time 151150061 ps
CPU time 3.23 seconds
Started Aug 07 06:15:56 PM PDT 24
Finished Aug 07 06:16:00 PM PDT 24
Peak memory 214976 kb
Host smart-8723061b-88f0-4bd9-b1e8-079cefc7dd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643348730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.643348730
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1790649215
Short name T828
Test name
Test status
Simulation time 171668419 ps
CPU time 24.15 seconds
Started Aug 07 06:15:58 PM PDT 24
Finished Aug 07 06:16:22 PM PDT 24
Peak memory 250856 kb
Host smart-b1a55fdb-fa31-459d-bdd9-64955430bc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790649215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1790649215
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3645040827
Short name T245
Test name
Test status
Simulation time 71990468 ps
CPU time 8.9 seconds
Started Aug 07 06:15:55 PM PDT 24
Finished Aug 07 06:16:04 PM PDT 24
Peak memory 250844 kb
Host smart-17fd2dc8-3020-45fd-87bc-f0c69353204f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645040827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3645040827
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3389199022
Short name T258
Test name
Test status
Simulation time 15011053 ps
CPU time 1.11 seconds
Started Aug 07 06:15:58 PM PDT 24
Finished Aug 07 06:15:59 PM PDT 24
Peak memory 211896 kb
Host smart-4cacc186-9747-4b87-b938-01a095837864
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389199022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3389199022
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.4166100028
Short name T764
Test name
Test status
Simulation time 30239503 ps
CPU time 1.42 seconds
Started Aug 07 06:16:04 PM PDT 24
Finished Aug 07 06:16:06 PM PDT 24
Peak memory 208964 kb
Host smart-a11994ca-f789-47e2-bc6c-fcc0b9fbb929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166100028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.4166100028
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.4274963470
Short name T450
Test name
Test status
Simulation time 330555116 ps
CPU time 16.1 seconds
Started Aug 07 06:15:57 PM PDT 24
Finished Aug 07 06:16:13 PM PDT 24
Peak memory 218160 kb
Host smart-88eb323e-4d6d-41f8-8479-61eeba2116a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274963470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.4274963470
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.281692060
Short name T437
Test name
Test status
Simulation time 356175347 ps
CPU time 9.22 seconds
Started Aug 07 06:15:56 PM PDT 24
Finished Aug 07 06:16:05 PM PDT 24
Peak memory 217224 kb
Host smart-b63ef94f-28b3-423c-b083-6275c0ddfa3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281692060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.281692060
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3113536012
Short name T2
Test name
Test status
Simulation time 377152041 ps
CPU time 3.4 seconds
Started Aug 07 06:15:57 PM PDT 24
Finished Aug 07 06:16:00 PM PDT 24
Peak memory 222516 kb
Host smart-3b6d62a9-c703-460d-b421-c226b00fddbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113536012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3113536012
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.586395140
Short name T49
Test name
Test status
Simulation time 1373890030 ps
CPU time 14.16 seconds
Started Aug 07 06:15:57 PM PDT 24
Finished Aug 07 06:16:12 PM PDT 24
Peak memory 225912 kb
Host smart-c62214a5-30db-4b0c-8d30-87fdf5e5fe84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586395140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.586395140
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3220901843
Short name T557
Test name
Test status
Simulation time 3796869043 ps
CPU time 16.13 seconds
Started Aug 07 06:15:54 PM PDT 24
Finished Aug 07 06:16:10 PM PDT 24
Peak memory 226032 kb
Host smart-0c6fe8d8-660b-483b-a147-2900bd7288fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220901843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3220901843
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2213267478
Short name T593
Test name
Test status
Simulation time 464598775 ps
CPU time 9.45 seconds
Started Aug 07 06:15:57 PM PDT 24
Finished Aug 07 06:16:07 PM PDT 24
Peak memory 218212 kb
Host smart-b231036c-13e3-41eb-ba49-4eddc103f9cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213267478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2213267478
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1145248645
Short name T432
Test name
Test status
Simulation time 264260245 ps
CPU time 7.68 seconds
Started Aug 07 06:15:57 PM PDT 24
Finished Aug 07 06:16:04 PM PDT 24
Peak memory 218180 kb
Host smart-e7fe0098-71db-4487-9ecf-b979be7fbcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145248645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1145248645
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.158332632
Short name T257
Test name
Test status
Simulation time 34122225 ps
CPU time 1.3 seconds
Started Aug 07 06:15:56 PM PDT 24
Finished Aug 07 06:15:57 PM PDT 24
Peak memory 213664 kb
Host smart-47add2b7-51fc-426e-bda5-9cf0b6147357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158332632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.158332632
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2551886091
Short name T353
Test name
Test status
Simulation time 1231326499 ps
CPU time 33.26 seconds
Started Aug 07 06:15:59 PM PDT 24
Finished Aug 07 06:16:33 PM PDT 24
Peak memory 251032 kb
Host smart-8e878a94-9b53-412a-9d27-773c092991fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551886091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2551886091
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1173088203
Short name T471
Test name
Test status
Simulation time 274552161 ps
CPU time 2.7 seconds
Started Aug 07 06:15:59 PM PDT 24
Finished Aug 07 06:16:02 PM PDT 24
Peak memory 223980 kb
Host smart-2fc2daed-4f1d-4aa0-a62c-35ea079ec367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173088203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1173088203
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1551781155
Short name T780
Test name
Test status
Simulation time 22556600484 ps
CPU time 388.66 seconds
Started Aug 07 06:15:54 PM PDT 24
Finished Aug 07 06:22:23 PM PDT 24
Peak memory 273796 kb
Host smart-253ed5ac-ca57-49f7-99d4-9051006abe9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551781155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1551781155
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2588528693
Short name T807
Test name
Test status
Simulation time 42450856 ps
CPU time 1.07 seconds
Started Aug 07 06:15:59 PM PDT 24
Finished Aug 07 06:16:00 PM PDT 24
Peak memory 217736 kb
Host smart-3e415fe6-979c-43d0-beb2-824c4b2a01d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588528693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2588528693
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2886603960
Short name T92
Test name
Test status
Simulation time 20578537 ps
CPU time 1.07 seconds
Started Aug 07 06:16:03 PM PDT 24
Finished Aug 07 06:16:04 PM PDT 24
Peak memory 208864 kb
Host smart-98a46691-4596-4cd9-b478-87383b6a6306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886603960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2886603960
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3134952544
Short name T268
Test name
Test status
Simulation time 595252358 ps
CPU time 11.17 seconds
Started Aug 07 06:16:01 PM PDT 24
Finished Aug 07 06:16:12 PM PDT 24
Peak memory 218204 kb
Host smart-05e60f31-24b4-46ae-ab9b-ef2512383bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134952544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3134952544
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2808039240
Short name T8
Test name
Test status
Simulation time 3154788112 ps
CPU time 4.56 seconds
Started Aug 07 06:16:05 PM PDT 24
Finished Aug 07 06:16:09 PM PDT 24
Peak memory 217692 kb
Host smart-84aa6f84-a824-4daf-8e8f-fd6317fde2f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808039240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2808039240
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3092932907
Short name T303
Test name
Test status
Simulation time 137318413 ps
CPU time 2.31 seconds
Started Aug 07 06:16:03 PM PDT 24
Finished Aug 07 06:16:05 PM PDT 24
Peak memory 218228 kb
Host smart-6b674aab-2e9c-4aaf-96bd-5c473d9b737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092932907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3092932907
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1895341261
Short name T607
Test name
Test status
Simulation time 325355585 ps
CPU time 10.61 seconds
Started Aug 07 06:16:08 PM PDT 24
Finished Aug 07 06:16:19 PM PDT 24
Peak memory 226016 kb
Host smart-f1db7040-59b4-47e5-9165-97af51f8af26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895341261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1895341261
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1027881427
Short name T686
Test name
Test status
Simulation time 539952916 ps
CPU time 12.2 seconds
Started Aug 07 06:16:05 PM PDT 24
Finished Aug 07 06:16:17 PM PDT 24
Peak memory 225960 kb
Host smart-0497dc57-9f90-4410-8d0a-09f9340dd440
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027881427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1027881427
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2626708790
Short name T366
Test name
Test status
Simulation time 1144100897 ps
CPU time 7.76 seconds
Started Aug 07 06:16:08 PM PDT 24
Finished Aug 07 06:16:16 PM PDT 24
Peak memory 225948 kb
Host smart-a78bfad9-a62c-4e2c-b444-25fb47eb0758
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626708790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2626708790
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2677793703
Short name T54
Test name
Test status
Simulation time 1550495501 ps
CPU time 8.77 seconds
Started Aug 07 06:16:00 PM PDT 24
Finished Aug 07 06:16:08 PM PDT 24
Peak memory 225984 kb
Host smart-35c53bab-0083-472a-a054-c7aeb67a6fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677793703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2677793703
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2036677413
Short name T40
Test name
Test status
Simulation time 134311180 ps
CPU time 5.73 seconds
Started Aug 07 06:16:02 PM PDT 24
Finished Aug 07 06:16:08 PM PDT 24
Peak memory 217632 kb
Host smart-3e6df478-4b9f-47d1-9bf6-b39f963140ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036677413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2036677413
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3434460602
Short name T739
Test name
Test status
Simulation time 268435547 ps
CPU time 28.97 seconds
Started Aug 07 06:16:04 PM PDT 24
Finished Aug 07 06:16:33 PM PDT 24
Peak memory 250840 kb
Host smart-58767ba8-4acf-4390-9a79-8b4820393b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434460602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3434460602
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2717637158
Short name T743
Test name
Test status
Simulation time 51347965 ps
CPU time 6.11 seconds
Started Aug 07 06:16:00 PM PDT 24
Finished Aug 07 06:16:07 PM PDT 24
Peak memory 250692 kb
Host smart-c2d3546c-672e-4087-b428-fa7f82a0827f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717637158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2717637158
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3500432675
Short name T187
Test name
Test status
Simulation time 18110832688 ps
CPU time 128.93 seconds
Started Aug 07 06:16:03 PM PDT 24
Finished Aug 07 06:18:12 PM PDT 24
Peak memory 332820 kb
Host smart-76bdac24-ba6e-4755-aec8-f5fd04ff8e81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500432675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3500432675
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2040934017
Short name T86
Test name
Test status
Simulation time 36047453 ps
CPU time 1.05 seconds
Started Aug 07 06:16:08 PM PDT 24
Finished Aug 07 06:16:09 PM PDT 24
Peak memory 211976 kb
Host smart-f552bfcd-27e9-4eac-aa5e-9707a9e733fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040934017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2040934017
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.758861897
Short name T263
Test name
Test status
Simulation time 15382598 ps
CPU time 0.85 seconds
Started Aug 07 06:16:14 PM PDT 24
Finished Aug 07 06:16:15 PM PDT 24
Peak memory 208856 kb
Host smart-2f085a46-72f1-4f36-a57f-a8822fa24bc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758861897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.758861897
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1223130479
Short name T307
Test name
Test status
Simulation time 320517164 ps
CPU time 11.94 seconds
Started Aug 07 06:16:02 PM PDT 24
Finished Aug 07 06:16:14 PM PDT 24
Peak memory 226020 kb
Host smart-5dc31244-2b90-48fe-903f-20b9446cf0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223130479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1223130479
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3136264454
Short name T167
Test name
Test status
Simulation time 256112290 ps
CPU time 6.23 seconds
Started Aug 07 06:16:02 PM PDT 24
Finished Aug 07 06:16:08 PM PDT 24
Peak memory 217076 kb
Host smart-0ee8d207-e101-4173-9463-12e79a95b6be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136264454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3136264454
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.925205372
Short name T624
Test name
Test status
Simulation time 118726908 ps
CPU time 2.84 seconds
Started Aug 07 06:16:02 PM PDT 24
Finished Aug 07 06:16:05 PM PDT 24
Peak memory 222676 kb
Host smart-ebc631e7-4635-4970-98af-2b9fb037485f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925205372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.925205372
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.4133376253
Short name T420
Test name
Test status
Simulation time 313659449 ps
CPU time 11.75 seconds
Started Aug 07 06:16:07 PM PDT 24
Finished Aug 07 06:16:18 PM PDT 24
Peak memory 218860 kb
Host smart-3581a147-87e1-42c2-aab4-8a4bf2962824
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133376253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.4133376253
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1469376741
Short name T512
Test name
Test status
Simulation time 1258650924 ps
CPU time 11.69 seconds
Started Aug 07 06:16:09 PM PDT 24
Finished Aug 07 06:16:21 PM PDT 24
Peak memory 225960 kb
Host smart-35510e98-4241-4e37-a201-ed6315420077
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469376741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1469376741
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2010979643
Short name T248
Test name
Test status
Simulation time 420257457 ps
CPU time 9.44 seconds
Started Aug 07 06:16:11 PM PDT 24
Finished Aug 07 06:16:21 PM PDT 24
Peak memory 225952 kb
Host smart-ba9b3ba6-bd60-46dd-ba3e-9f712751d458
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010979643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2010979643
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3239129949
Short name T216
Test name
Test status
Simulation time 448664462 ps
CPU time 9.29 seconds
Started Aug 07 06:16:03 PM PDT 24
Finished Aug 07 06:16:12 PM PDT 24
Peak memory 218296 kb
Host smart-e996f08f-87c4-4197-9505-c7042214dbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239129949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3239129949
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3925697432
Short name T570
Test name
Test status
Simulation time 63770431 ps
CPU time 1.94 seconds
Started Aug 07 06:16:04 PM PDT 24
Finished Aug 07 06:16:06 PM PDT 24
Peak memory 217672 kb
Host smart-ef1a8b19-8f71-4fb8-9ddb-b1f19a88554c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925697432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3925697432
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1642066299
Short name T868
Test name
Test status
Simulation time 585235690 ps
CPU time 23.33 seconds
Started Aug 07 06:16:04 PM PDT 24
Finished Aug 07 06:16:28 PM PDT 24
Peak memory 250772 kb
Host smart-775e389a-fb3f-4d9f-9361-150f729376c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642066299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1642066299
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1407853306
Short name T700
Test name
Test status
Simulation time 204315702 ps
CPU time 11.5 seconds
Started Aug 07 06:16:04 PM PDT 24
Finished Aug 07 06:16:15 PM PDT 24
Peak memory 250776 kb
Host smart-cef3da2d-1986-4a84-925e-8f479ef3cc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407853306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1407853306
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2343100481
Short name T362
Test name
Test status
Simulation time 5294541041 ps
CPU time 21.71 seconds
Started Aug 07 06:16:07 PM PDT 24
Finished Aug 07 06:16:29 PM PDT 24
Peak memory 219408 kb
Host smart-eb94b45e-8bfd-46d0-841f-ae14406380a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343100481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2343100481
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.3120755695
Short name T797
Test name
Test status
Simulation time 14264822369 ps
CPU time 466.72 seconds
Started Aug 07 06:16:11 PM PDT 24
Finished Aug 07 06:23:58 PM PDT 24
Peak memory 283776 kb
Host smart-639c0074-6da1-4edf-8797-e17d00f764e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3120755695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.3120755695
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2330502775
Short name T88
Test name
Test status
Simulation time 41181036 ps
CPU time 1.32 seconds
Started Aug 07 06:16:04 PM PDT 24
Finished Aug 07 06:16:06 PM PDT 24
Peak memory 217804 kb
Host smart-b313567c-5f68-4610-82ac-62e38fe095ab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330502775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2330502775
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.470084685
Short name T799
Test name
Test status
Simulation time 14616165 ps
CPU time 0.87 seconds
Started Aug 07 06:16:11 PM PDT 24
Finished Aug 07 06:16:12 PM PDT 24
Peak memory 208840 kb
Host smart-036a5128-58f6-49f3-b03f-cae0f1532d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470084685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.470084685
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1219684354
Short name T352
Test name
Test status
Simulation time 1113266344 ps
CPU time 16.92 seconds
Started Aug 07 06:16:17 PM PDT 24
Finished Aug 07 06:16:34 PM PDT 24
Peak memory 226024 kb
Host smart-2d965438-6710-4b54-abc0-ed2bbc0737ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219684354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1219684354
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2147913832
Short name T21
Test name
Test status
Simulation time 422798246 ps
CPU time 12.09 seconds
Started Aug 07 06:16:08 PM PDT 24
Finished Aug 07 06:16:20 PM PDT 24
Peak memory 217436 kb
Host smart-b24d993b-e69c-4a20-9dc8-2d4c35521fd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147913832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2147913832
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.188030269
Short name T533
Test name
Test status
Simulation time 65227366 ps
CPU time 3.3 seconds
Started Aug 07 06:16:14 PM PDT 24
Finished Aug 07 06:16:17 PM PDT 24
Peak memory 218188 kb
Host smart-c168ab19-cebe-4ebd-88e0-4118bc89bec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188030269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.188030269
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2023894731
Short name T770
Test name
Test status
Simulation time 1029362157 ps
CPU time 10.85 seconds
Started Aug 07 06:16:16 PM PDT 24
Finished Aug 07 06:16:27 PM PDT 24
Peak memory 226032 kb
Host smart-221a135f-796d-4a98-9ac5-9b1cdc865cca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023894731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2023894731
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1162806528
Short name T837
Test name
Test status
Simulation time 600455470 ps
CPU time 14.14 seconds
Started Aug 07 06:16:14 PM PDT 24
Finished Aug 07 06:16:28 PM PDT 24
Peak memory 225840 kb
Host smart-f454e854-a7a7-4184-867c-777804d95c4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162806528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1162806528
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3540129257
Short name T243
Test name
Test status
Simulation time 1574760872 ps
CPU time 15.54 seconds
Started Aug 07 06:16:15 PM PDT 24
Finished Aug 07 06:16:30 PM PDT 24
Peak memory 218144 kb
Host smart-2975ba6a-6e46-475b-9313-c84a4dec060b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540129257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3540129257
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2992069238
Short name T844
Test name
Test status
Simulation time 556579485 ps
CPU time 12.2 seconds
Started Aug 07 06:16:07 PM PDT 24
Finished Aug 07 06:16:19 PM PDT 24
Peak memory 226008 kb
Host smart-eb752857-185b-4e96-a6e1-148e804fcec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992069238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2992069238
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1935195843
Short name T73
Test name
Test status
Simulation time 32704439 ps
CPU time 2.49 seconds
Started Aug 07 06:16:08 PM PDT 24
Finished Aug 07 06:16:11 PM PDT 24
Peak memory 214544 kb
Host smart-3afa075a-e58b-4cdd-a381-731d55b131be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935195843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1935195843
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.922960167
Short name T873
Test name
Test status
Simulation time 4147303669 ps
CPU time 30.07 seconds
Started Aug 07 06:16:08 PM PDT 24
Finished Aug 07 06:16:38 PM PDT 24
Peak memory 250768 kb
Host smart-98e2d007-eca4-4b81-9a90-0f93eb59978c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922960167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.922960167
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.176094740
Short name T483
Test name
Test status
Simulation time 299922894 ps
CPU time 6.8 seconds
Started Aug 07 06:16:17 PM PDT 24
Finished Aug 07 06:16:24 PM PDT 24
Peak memory 250864 kb
Host smart-d409f9e7-0a68-457b-8175-71bb09f845ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176094740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.176094740
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2015633973
Short name T523
Test name
Test status
Simulation time 3614946488 ps
CPU time 91.5 seconds
Started Aug 07 06:16:07 PM PDT 24
Finished Aug 07 06:17:39 PM PDT 24
Peak memory 278124 kb
Host smart-9a1dfe50-d815-4123-ad2d-679904975734
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015633973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2015633973
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.3829020086
Short name T50
Test name
Test status
Simulation time 59989065712 ps
CPU time 986.79 seconds
Started Aug 07 06:16:15 PM PDT 24
Finished Aug 07 06:32:42 PM PDT 24
Peak memory 422020 kb
Host smart-6409adee-ab65-46aa-8497-1b3797f107e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3829020086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.3829020086
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2225494399
Short name T687
Test name
Test status
Simulation time 58249091 ps
CPU time 0.9 seconds
Started Aug 07 06:16:09 PM PDT 24
Finished Aug 07 06:16:10 PM PDT 24
Peak memory 211916 kb
Host smart-87b626c9-c5f7-4c3e-b3c4-f8d23f2738ab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225494399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2225494399
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1286166145
Short name T236
Test name
Test status
Simulation time 61574507 ps
CPU time 0.93 seconds
Started Aug 07 06:16:09 PM PDT 24
Finished Aug 07 06:16:10 PM PDT 24
Peak memory 208892 kb
Host smart-a4b5d846-cd98-4ff3-b47d-f78819e5771d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286166145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1286166145
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3100354622
Short name T444
Test name
Test status
Simulation time 1395624295 ps
CPU time 10.19 seconds
Started Aug 07 06:16:16 PM PDT 24
Finished Aug 07 06:16:26 PM PDT 24
Peak memory 226012 kb
Host smart-8a19fefd-b6f7-405f-b0f0-1c05cd4923be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100354622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3100354622
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2055595986
Short name T188
Test name
Test status
Simulation time 1984846070 ps
CPU time 6.3 seconds
Started Aug 07 06:16:07 PM PDT 24
Finished Aug 07 06:16:13 PM PDT 24
Peak memory 217156 kb
Host smart-2eceda27-8c0e-4dba-b58a-9e76bd32c141
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055595986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2055595986
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3836618325
Short name T574
Test name
Test status
Simulation time 88726763 ps
CPU time 4.22 seconds
Started Aug 07 06:16:18 PM PDT 24
Finished Aug 07 06:16:22 PM PDT 24
Peak memory 218208 kb
Host smart-f61ca9a4-e51f-41f2-96ad-68918ce3144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836618325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3836618325
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2067829141
Short name T702
Test name
Test status
Simulation time 3470858690 ps
CPU time 28.14 seconds
Started Aug 07 06:16:13 PM PDT 24
Finished Aug 07 06:16:42 PM PDT 24
Peak memory 226080 kb
Host smart-353d3ed8-4468-4299-9a6c-9c3c818fd5c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067829141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2067829141
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.846682909
Short name T465
Test name
Test status
Simulation time 857374509 ps
CPU time 6.63 seconds
Started Aug 07 06:16:06 PM PDT 24
Finished Aug 07 06:16:12 PM PDT 24
Peak memory 225944 kb
Host smart-53d1a1a1-457e-438f-8fce-c15b64da6823
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846682909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.846682909
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1458409921
Short name T705
Test name
Test status
Simulation time 2138781131 ps
CPU time 10.93 seconds
Started Aug 07 06:16:10 PM PDT 24
Finished Aug 07 06:16:21 PM PDT 24
Peak memory 218200 kb
Host smart-dc283679-fcfe-44bb-bc5f-2bdc82261f8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458409921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1458409921
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3526662525
Short name T356
Test name
Test status
Simulation time 538786674 ps
CPU time 7.63 seconds
Started Aug 07 06:16:18 PM PDT 24
Finished Aug 07 06:16:25 PM PDT 24
Peak memory 224396 kb
Host smart-3f42e971-92ae-48cb-877b-0cc99e414331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526662525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3526662525
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.4293652331
Short name T310
Test name
Test status
Simulation time 36174035 ps
CPU time 1.63 seconds
Started Aug 07 06:16:10 PM PDT 24
Finished Aug 07 06:16:11 PM PDT 24
Peak memory 213776 kb
Host smart-8a187eb0-43b6-4518-abd0-dbc498d66c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293652331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.4293652331
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.4201400301
Short name T333
Test name
Test status
Simulation time 290133520 ps
CPU time 33.23 seconds
Started Aug 07 06:16:14 PM PDT 24
Finished Aug 07 06:16:47 PM PDT 24
Peak memory 250528 kb
Host smart-b23ec190-02e8-4871-9c78-9c49c8b33cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201400301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.4201400301
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3956955435
Short name T757
Test name
Test status
Simulation time 86581299 ps
CPU time 7.57 seconds
Started Aug 07 06:16:07 PM PDT 24
Finished Aug 07 06:16:15 PM PDT 24
Peak memory 250824 kb
Host smart-f60bb8c0-6954-48f6-8cae-d28ff2f01720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956955435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3956955435
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1046985823
Short name T519
Test name
Test status
Simulation time 2916806328 ps
CPU time 52.04 seconds
Started Aug 07 06:16:10 PM PDT 24
Finished Aug 07 06:17:02 PM PDT 24
Peak memory 274152 kb
Host smart-3e7c78bc-41b7-46c2-bba3-15f7c563fae3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046985823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1046985823
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3607164927
Short name T777
Test name
Test status
Simulation time 52862131 ps
CPU time 0.93 seconds
Started Aug 07 06:16:12 PM PDT 24
Finished Aug 07 06:16:13 PM PDT 24
Peak memory 211836 kb
Host smart-3e46c53e-73c7-4819-8c96-2b955f89b40f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607164927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3607164927
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3309344292
Short name T556
Test name
Test status
Simulation time 50044982 ps
CPU time 0.84 seconds
Started Aug 07 06:13:45 PM PDT 24
Finished Aug 07 06:13:46 PM PDT 24
Peak memory 208692 kb
Host smart-e81a70f1-daea-42fa-8a4b-f99f6df159e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309344292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3309344292
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2385968702
Short name T806
Test name
Test status
Simulation time 278853481 ps
CPU time 11.55 seconds
Started Aug 07 06:13:53 PM PDT 24
Finished Aug 07 06:14:05 PM PDT 24
Peak memory 218272 kb
Host smart-69c6055a-968d-4a5d-a989-ed56dd131782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385968702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2385968702
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3654555838
Short name T664
Test name
Test status
Simulation time 1669289628 ps
CPU time 5.87 seconds
Started Aug 07 06:13:47 PM PDT 24
Finished Aug 07 06:13:53 PM PDT 24
Peak memory 217308 kb
Host smart-0d1bfeb8-5913-4455-92ff-ee628bb92571
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654555838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3654555838
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1198513638
Short name T389
Test name
Test status
Simulation time 9106113195 ps
CPU time 21.83 seconds
Started Aug 07 06:13:45 PM PDT 24
Finished Aug 07 06:14:06 PM PDT 24
Peak memory 218524 kb
Host smart-4c33b746-8595-4999-9c22-36db991fe1f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198513638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1198513638
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2439404388
Short name T329
Test name
Test status
Simulation time 712741111 ps
CPU time 3.16 seconds
Started Aug 07 06:13:48 PM PDT 24
Finished Aug 07 06:13:51 PM PDT 24
Peak memory 217312 kb
Host smart-2438dba6-fc4b-419d-87de-9c72567b97ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439404388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
439404388
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2731390983
Short name T639
Test name
Test status
Simulation time 1535419113 ps
CPU time 12.25 seconds
Started Aug 07 06:13:46 PM PDT 24
Finished Aug 07 06:13:59 PM PDT 24
Peak memory 223268 kb
Host smart-daa26f58-98d4-4e80-85bf-179325ffeaea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731390983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2731390983
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.12960415
Short name T320
Test name
Test status
Simulation time 3314117886 ps
CPU time 10.75 seconds
Started Aug 07 06:13:47 PM PDT 24
Finished Aug 07 06:13:58 PM PDT 24
Peak memory 217636 kb
Host smart-6f778990-730d-4ea7-af37-2b5687915779
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12960415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jt
ag_regwen_during_op.12960415
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.4076101291
Short name T573
Test name
Test status
Simulation time 210272066 ps
CPU time 2.77 seconds
Started Aug 07 06:13:49 PM PDT 24
Finished Aug 07 06:13:52 PM PDT 24
Peak memory 217692 kb
Host smart-839436db-7b72-4d85-8ea0-a2cc3c8bfdc4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076101291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
4076101291
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1884082626
Short name T506
Test name
Test status
Simulation time 1696334441 ps
CPU time 43.2 seconds
Started Aug 07 06:13:47 PM PDT 24
Finished Aug 07 06:14:30 PM PDT 24
Peak memory 283600 kb
Host smart-b6436eb3-05e6-41e8-937d-33be2c371b53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884082626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1884082626
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.431044101
Short name T308
Test name
Test status
Simulation time 3284255602 ps
CPU time 30.91 seconds
Started Aug 07 06:13:45 PM PDT 24
Finished Aug 07 06:14:16 PM PDT 24
Peak memory 250840 kb
Host smart-a5dc4b75-3e82-4ead-822b-b8fc919f1296
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431044101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.431044101
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3100585020
Short name T364
Test name
Test status
Simulation time 284205618 ps
CPU time 3.63 seconds
Started Aug 07 06:13:43 PM PDT 24
Finished Aug 07 06:13:47 PM PDT 24
Peak memory 222568 kb
Host smart-fa1aae8b-dce8-4e45-a2c7-7df857bd960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100585020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3100585020
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.356658852
Short name T697
Test name
Test status
Simulation time 729634623 ps
CPU time 4.86 seconds
Started Aug 07 06:13:51 PM PDT 24
Finished Aug 07 06:13:56 PM PDT 24
Peak memory 222136 kb
Host smart-fb110252-08e3-4539-88a6-9f752c9d9a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356658852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.356658852
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.4257695766
Short name T339
Test name
Test status
Simulation time 208729273 ps
CPU time 10.31 seconds
Started Aug 07 06:13:49 PM PDT 24
Finished Aug 07 06:13:59 PM PDT 24
Peak memory 218872 kb
Host smart-36a6b9b4-957b-40ec-adba-524f5cf75401
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257695766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.4257695766
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.161780716
Short name T597
Test name
Test status
Simulation time 1433569358 ps
CPU time 11.03 seconds
Started Aug 07 06:13:46 PM PDT 24
Finished Aug 07 06:13:57 PM PDT 24
Peak memory 225968 kb
Host smart-6243e424-dd21-4090-8e93-394c776ecfcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161780716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.161780716
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2569691373
Short name T840
Test name
Test status
Simulation time 1369210470 ps
CPU time 10.83 seconds
Started Aug 07 06:13:47 PM PDT 24
Finished Aug 07 06:13:58 PM PDT 24
Peak memory 218056 kb
Host smart-5a8a8976-156e-4266-94e2-8d71dc069a06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569691373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
569691373
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1389803685
Short name T58
Test name
Test status
Simulation time 349034633 ps
CPU time 9.73 seconds
Started Aug 07 06:13:46 PM PDT 24
Finished Aug 07 06:13:56 PM PDT 24
Peak memory 225996 kb
Host smart-6ecd2b22-8fdf-44a1-831a-dea115851bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389803685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1389803685
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3758029952
Short name T676
Test name
Test status
Simulation time 109262032 ps
CPU time 2.91 seconds
Started Aug 07 06:13:45 PM PDT 24
Finished Aug 07 06:13:48 PM PDT 24
Peak memory 217624 kb
Host smart-985b12ab-d059-4733-9ba2-98602b904e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758029952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3758029952
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.960728293
Short name T170
Test name
Test status
Simulation time 6355205133 ps
CPU time 29.51 seconds
Started Aug 07 06:13:46 PM PDT 24
Finished Aug 07 06:14:16 PM PDT 24
Peak memory 250748 kb
Host smart-a10a1612-e766-4e05-8f25-5b8b3742eb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960728293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.960728293
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.860547786
Short name T449
Test name
Test status
Simulation time 56718025 ps
CPU time 3.04 seconds
Started Aug 07 06:13:45 PM PDT 24
Finished Aug 07 06:13:48 PM PDT 24
Peak memory 218140 kb
Host smart-f4303231-3ad7-46c2-9ad2-3ad3b089b2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860547786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.860547786
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2316125089
Short name T421
Test name
Test status
Simulation time 1694694183 ps
CPU time 56.5 seconds
Started Aug 07 06:13:45 PM PDT 24
Finished Aug 07 06:14:42 PM PDT 24
Peak memory 271864 kb
Host smart-c9da545d-43c9-4011-b4aa-eece55da1757
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316125089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2316125089
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.789537776
Short name T675
Test name
Test status
Simulation time 16812273 ps
CPU time 0.75 seconds
Started Aug 07 06:13:46 PM PDT 24
Finished Aug 07 06:13:47 PM PDT 24
Peak memory 206972 kb
Host smart-98390d6f-1fe7-4867-b46c-2a166a762172
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789537776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.789537776
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3724531087
Short name T545
Test name
Test status
Simulation time 15820435 ps
CPU time 1.07 seconds
Started Aug 07 06:13:56 PM PDT 24
Finished Aug 07 06:13:58 PM PDT 24
Peak memory 208852 kb
Host smart-3fb52300-148e-4acb-9b4f-349458339e6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724531087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3724531087
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.306189995
Short name T463
Test name
Test status
Simulation time 1340678533 ps
CPU time 14.04 seconds
Started Aug 07 06:13:54 PM PDT 24
Finished Aug 07 06:14:08 PM PDT 24
Peak memory 226068 kb
Host smart-fe940b21-6f6e-442d-b15b-cda9094e29ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306189995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.306189995
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1212787303
Short name T744
Test name
Test status
Simulation time 335737972 ps
CPU time 1.76 seconds
Started Aug 07 06:13:47 PM PDT 24
Finished Aug 07 06:13:49 PM PDT 24
Peak memory 216992 kb
Host smart-94120ef1-510d-4da0-a006-5d788e379eb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212787303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1212787303
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.67384827
Short name T656
Test name
Test status
Simulation time 13769522939 ps
CPU time 46.09 seconds
Started Aug 07 06:13:46 PM PDT 24
Finished Aug 07 06:14:32 PM PDT 24
Peak memory 219668 kb
Host smart-a2667878-864d-46bd-8fc4-34f1dc0ffc09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67384827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_erro
rs.67384827
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1033151938
Short name T842
Test name
Test status
Simulation time 1598167331 ps
CPU time 15.96 seconds
Started Aug 07 06:13:54 PM PDT 24
Finished Aug 07 06:14:10 PM PDT 24
Peak memory 217620 kb
Host smart-1af9f6ec-81ab-42a5-9f3f-0438bb2a1144
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033151938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
033151938
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.4199148348
Short name T430
Test name
Test status
Simulation time 353745312 ps
CPU time 6.41 seconds
Started Aug 07 06:13:48 PM PDT 24
Finished Aug 07 06:13:54 PM PDT 24
Peak memory 218192 kb
Host smart-bd8c972f-365e-465e-955a-d55084775030
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199148348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.4199148348
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.175439752
Short name T674
Test name
Test status
Simulation time 4696539857 ps
CPU time 25.31 seconds
Started Aug 07 06:13:49 PM PDT 24
Finished Aug 07 06:14:15 PM PDT 24
Peak memory 217640 kb
Host smart-a7853492-c3be-47d3-8c4d-3ecfe5a8e020
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175439752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_regwen_during_op.175439752
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3780668270
Short name T68
Test name
Test status
Simulation time 327612097 ps
CPU time 5.74 seconds
Started Aug 07 06:13:47 PM PDT 24
Finished Aug 07 06:13:53 PM PDT 24
Peak memory 217568 kb
Host smart-8b84bec9-6366-44a7-a799-99c621710249
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780668270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3780668270
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2279457642
Short name T718
Test name
Test status
Simulation time 1064642403 ps
CPU time 51.64 seconds
Started Aug 07 06:13:48 PM PDT 24
Finished Aug 07 06:14:40 PM PDT 24
Peak memory 250724 kb
Host smart-09f889f1-7977-492a-8ad6-3ef14abdac80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279457642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2279457642
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2590454634
Short name T254
Test name
Test status
Simulation time 1178654479 ps
CPU time 14.88 seconds
Started Aug 07 06:13:47 PM PDT 24
Finished Aug 07 06:14:02 PM PDT 24
Peak memory 250804 kb
Host smart-d5396dd5-86c1-4221-9906-a45dcbec8ddd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590454634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2590454634
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1446766983
Short name T613
Test name
Test status
Simulation time 56840185 ps
CPU time 3.08 seconds
Started Aug 07 06:13:54 PM PDT 24
Finished Aug 07 06:13:57 PM PDT 24
Peak memory 218240 kb
Host smart-e2541a96-2a71-4e32-a41f-d56165caa1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446766983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1446766983
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2752497974
Short name T554
Test name
Test status
Simulation time 1023925586 ps
CPU time 10.44 seconds
Started Aug 07 06:13:53 PM PDT 24
Finished Aug 07 06:14:04 PM PDT 24
Peak memory 217664 kb
Host smart-552060f1-bb01-4699-8ce8-dc7e82504baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752497974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2752497974
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.2610792369
Short name T262
Test name
Test status
Simulation time 1111227597 ps
CPU time 14.73 seconds
Started Aug 07 06:14:00 PM PDT 24
Finished Aug 07 06:14:15 PM PDT 24
Peak memory 225912 kb
Host smart-79ca40b4-1ead-4c4b-9e3a-138dbc58c692
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610792369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2610792369
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.506067495
Short name T411
Test name
Test status
Simulation time 1044684602 ps
CPU time 12.58 seconds
Started Aug 07 06:13:54 PM PDT 24
Finished Aug 07 06:14:07 PM PDT 24
Peak memory 225968 kb
Host smart-83c73efc-725e-4022-bcfa-499bf0f43b4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506067495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.506067495
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1486491852
Short name T784
Test name
Test status
Simulation time 334296794 ps
CPU time 11.88 seconds
Started Aug 07 06:13:57 PM PDT 24
Finished Aug 07 06:14:09 PM PDT 24
Peak memory 218160 kb
Host smart-72b5ebf3-0e81-41d5-91f2-7389d048422f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486491852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
486491852
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.884923103
Short name T650
Test name
Test status
Simulation time 605906929 ps
CPU time 7.03 seconds
Started Aug 07 06:13:45 PM PDT 24
Finished Aug 07 06:13:52 PM PDT 24
Peak memory 218296 kb
Host smart-9c835641-8e0d-4db4-8e33-c13893a5b156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884923103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.884923103
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3297148832
Short name T652
Test name
Test status
Simulation time 134458681 ps
CPU time 2.75 seconds
Started Aug 07 06:13:46 PM PDT 24
Finished Aug 07 06:13:49 PM PDT 24
Peak memory 214356 kb
Host smart-2a412a16-180e-4b54-8360-324447778fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297148832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3297148832
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.395249738
Short name T476
Test name
Test status
Simulation time 228551527 ps
CPU time 23.93 seconds
Started Aug 07 06:13:51 PM PDT 24
Finished Aug 07 06:14:15 PM PDT 24
Peak memory 250840 kb
Host smart-18b1a9bc-8eb1-4fbb-b5a1-5464abf2b4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395249738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.395249738
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.1469311070
Short name T251
Test name
Test status
Simulation time 357608402 ps
CPU time 9.21 seconds
Started Aug 07 06:13:50 PM PDT 24
Finished Aug 07 06:13:59 PM PDT 24
Peak memory 250844 kb
Host smart-3d12d077-c6d3-49ea-9367-c3789dd25fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469311070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1469311070
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2330552685
Short name T278
Test name
Test status
Simulation time 8478104726 ps
CPU time 159.12 seconds
Started Aug 07 06:13:59 PM PDT 24
Finished Aug 07 06:16:39 PM PDT 24
Peak memory 275496 kb
Host smart-a3434fd3-eb04-4bf6-82c1-d72f946caaa4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330552685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2330552685
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3258285679
Short name T442
Test name
Test status
Simulation time 23545376 ps
CPU time 0.89 seconds
Started Aug 07 06:13:46 PM PDT 24
Finished Aug 07 06:13:47 PM PDT 24
Peak memory 211952 kb
Host smart-a97c80b7-d989-43fe-b418-db1f6c0ec309
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258285679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3258285679
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.4007936752
Short name T392
Test name
Test status
Simulation time 24897652 ps
CPU time 0.99 seconds
Started Aug 07 06:13:58 PM PDT 24
Finished Aug 07 06:13:59 PM PDT 24
Peak memory 208788 kb
Host smart-fc965c9d-adff-4e32-af4d-5cac0014407f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007936752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.4007936752
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1484731444
Short name T213
Test name
Test status
Simulation time 12418575 ps
CPU time 0.81 seconds
Started Aug 07 06:13:54 PM PDT 24
Finished Aug 07 06:13:55 PM PDT 24
Peak memory 208512 kb
Host smart-794f9188-8d35-4cd7-acc3-0f89fbaa6f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484731444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1484731444
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2152444029
Short name T410
Test name
Test status
Simulation time 1084681523 ps
CPU time 12.97 seconds
Started Aug 07 06:13:56 PM PDT 24
Finished Aug 07 06:14:09 PM PDT 24
Peak memory 218124 kb
Host smart-8c78bcda-9f50-4087-a8f8-3d10eae86093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152444029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2152444029
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3097347565
Short name T417
Test name
Test status
Simulation time 874053197 ps
CPU time 9.54 seconds
Started Aug 07 06:13:57 PM PDT 24
Finished Aug 07 06:14:07 PM PDT 24
Peak memory 217304 kb
Host smart-c946e8a8-555d-42c7-919e-357d27f703fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097347565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3097347565
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3489881574
Short name T299
Test name
Test status
Simulation time 1197213086 ps
CPU time 36.16 seconds
Started Aug 07 06:13:58 PM PDT 24
Finished Aug 07 06:14:34 PM PDT 24
Peak memory 218168 kb
Host smart-94f659d4-4a06-4c51-bdb4-9bd0bee2e632
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489881574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3489881574
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.72562928
Short name T758
Test name
Test status
Simulation time 847362319 ps
CPU time 16.7 seconds
Started Aug 07 06:14:02 PM PDT 24
Finished Aug 07 06:14:19 PM PDT 24
Peak memory 217656 kb
Host smart-0abb110f-8255-4036-8f26-fdb63b35ed34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72562928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.72562928
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1260975020
Short name T861
Test name
Test status
Simulation time 1544703149 ps
CPU time 8.53 seconds
Started Aug 07 06:13:58 PM PDT 24
Finished Aug 07 06:14:07 PM PDT 24
Peak memory 224248 kb
Host smart-ac391aee-0ce8-43ef-a976-5d43bdee4475
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260975020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1260975020
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3586738024
Short name T595
Test name
Test status
Simulation time 855259399 ps
CPU time 11.42 seconds
Started Aug 07 06:13:58 PM PDT 24
Finished Aug 07 06:14:10 PM PDT 24
Peak memory 217568 kb
Host smart-7fde0d05-a695-43a0-b44c-6612391988b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586738024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3586738024
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.282265334
Short name T855
Test name
Test status
Simulation time 193928277 ps
CPU time 6.56 seconds
Started Aug 07 06:14:01 PM PDT 24
Finished Aug 07 06:14:08 PM PDT 24
Peak memory 217728 kb
Host smart-59a75cc6-336d-4edb-aac1-5c816dcedc44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282265334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.282265334
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3329950652
Short name T106
Test name
Test status
Simulation time 1265799604 ps
CPU time 61.79 seconds
Started Aug 07 06:13:55 PM PDT 24
Finished Aug 07 06:14:57 PM PDT 24
Peak memory 267168 kb
Host smart-27d31ad7-dc0b-4937-80ac-609bc783e387
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329950652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3329950652
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3157858851
Short name T654
Test name
Test status
Simulation time 703904072 ps
CPU time 18.33 seconds
Started Aug 07 06:13:57 PM PDT 24
Finished Aug 07 06:14:15 PM PDT 24
Peak memory 250684 kb
Host smart-3e2fd00d-46ad-4104-8841-c5a7a390bcb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157858851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3157858851
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.931361288
Short name T345
Test name
Test status
Simulation time 77141568 ps
CPU time 3.83 seconds
Started Aug 07 06:13:57 PM PDT 24
Finished Aug 07 06:14:01 PM PDT 24
Peak memory 222544 kb
Host smart-36a46958-bbb4-4db1-9e0f-e9a6a1da28fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931361288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.931361288
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3109776197
Short name T754
Test name
Test status
Simulation time 1554906734 ps
CPU time 8.13 seconds
Started Aug 07 06:13:56 PM PDT 24
Finished Aug 07 06:14:04 PM PDT 24
Peak memory 214392 kb
Host smart-8e55f6a0-0bdc-448d-8bc7-9a5f02817990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109776197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3109776197
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.4137608372
Short name T416
Test name
Test status
Simulation time 359288110 ps
CPU time 12.79 seconds
Started Aug 07 06:13:55 PM PDT 24
Finished Aug 07 06:14:08 PM PDT 24
Peak memory 226012 kb
Host smart-d156afea-1b92-4cdc-a776-1d3a0b0fac79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137608372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.4137608372
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.731656212
Short name T611
Test name
Test status
Simulation time 504131996 ps
CPU time 11.82 seconds
Started Aug 07 06:13:55 PM PDT 24
Finished Aug 07 06:14:08 PM PDT 24
Peak memory 225968 kb
Host smart-72a558b1-0fa2-47b7-be37-5b51d7ef17f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731656212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.731656212
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1211375647
Short name T343
Test name
Test status
Simulation time 596714419 ps
CPU time 6.54 seconds
Started Aug 07 06:13:55 PM PDT 24
Finished Aug 07 06:14:02 PM PDT 24
Peak memory 225928 kb
Host smart-62b11bdd-45a2-45c9-b168-7ecaf4a5a559
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211375647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
211375647
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2546025234
Short name T57
Test name
Test status
Simulation time 376821428 ps
CPU time 13.39 seconds
Started Aug 07 06:13:56 PM PDT 24
Finished Aug 07 06:14:10 PM PDT 24
Peak memory 225544 kb
Host smart-fa7cd13e-8f01-4823-ab7c-b3454de744a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546025234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2546025234
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.701017008
Short name T802
Test name
Test status
Simulation time 106887616 ps
CPU time 2.29 seconds
Started Aug 07 06:13:58 PM PDT 24
Finished Aug 07 06:14:00 PM PDT 24
Peak memory 214116 kb
Host smart-fb167f55-6555-4ff1-a2a3-e907561255f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701017008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.701017008
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3565043235
Short name T544
Test name
Test status
Simulation time 805796541 ps
CPU time 17.94 seconds
Started Aug 07 06:14:00 PM PDT 24
Finished Aug 07 06:14:18 PM PDT 24
Peak memory 247116 kb
Host smart-62b0eb24-550f-40c1-8848-1571066d73f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565043235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3565043235
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.747325067
Short name T324
Test name
Test status
Simulation time 121585441 ps
CPU time 3.09 seconds
Started Aug 07 06:13:56 PM PDT 24
Finished Aug 07 06:13:59 PM PDT 24
Peak memory 222400 kb
Host smart-0ce5d2bb-2ba0-4304-88bb-9a0512b10e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747325067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.747325067
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2247816242
Short name T296
Test name
Test status
Simulation time 15640598338 ps
CPU time 23.74 seconds
Started Aug 07 06:13:53 PM PDT 24
Finished Aug 07 06:14:17 PM PDT 24
Peak memory 226072 kb
Host smart-17072927-8eec-4145-936a-9cc8f376de65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247816242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2247816242
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1165136026
Short name T208
Test name
Test status
Simulation time 30184566171 ps
CPU time 562.96 seconds
Started Aug 07 06:13:56 PM PDT 24
Finished Aug 07 06:23:19 PM PDT 24
Peak memory 332972 kb
Host smart-a50d2170-62af-477b-ab67-471b1c3e3caf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1165136026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.1165136026
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.629949850
Short name T658
Test name
Test status
Simulation time 14297330 ps
CPU time 0.99 seconds
Started Aug 07 06:13:57 PM PDT 24
Finished Aug 07 06:13:58 PM PDT 24
Peak memory 209172 kb
Host smart-ae1fe3ae-00c7-46bd-bc1f-0aaef8f7f042
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629949850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.629949850
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.709958749
Short name T165
Test name
Test status
Simulation time 204103869 ps
CPU time 0.96 seconds
Started Aug 07 06:14:01 PM PDT 24
Finished Aug 07 06:14:02 PM PDT 24
Peak memory 208892 kb
Host smart-a7254e96-65af-45f3-86b8-a46eeac9b559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709958749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.709958749
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.282480787
Short name T501
Test name
Test status
Simulation time 36556151 ps
CPU time 0.94 seconds
Started Aug 07 06:13:58 PM PDT 24
Finished Aug 07 06:13:59 PM PDT 24
Peak memory 208756 kb
Host smart-2eb3e74e-eba1-4983-960a-cae36d7b3c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282480787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.282480787
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.4019243330
Short name T870
Test name
Test status
Simulation time 398453825 ps
CPU time 10.92 seconds
Started Aug 07 06:14:02 PM PDT 24
Finished Aug 07 06:14:13 PM PDT 24
Peak memory 218224 kb
Host smart-41242cb8-8dc6-4dd4-811c-dea887374f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019243330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.4019243330
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3600999130
Short name T26
Test name
Test status
Simulation time 127598858 ps
CPU time 4.28 seconds
Started Aug 07 06:13:55 PM PDT 24
Finished Aug 07 06:13:59 PM PDT 24
Peak memory 217092 kb
Host smart-85cdb084-83b0-4caf-98ee-2d1157d51517
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600999130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3600999130
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1904569177
Short name T485
Test name
Test status
Simulation time 9521067585 ps
CPU time 42.16 seconds
Started Aug 07 06:14:01 PM PDT 24
Finished Aug 07 06:14:43 PM PDT 24
Peak memory 218896 kb
Host smart-03fc3309-458a-4ba5-a634-899e62a142bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904569177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1904569177
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2078193909
Short name T282
Test name
Test status
Simulation time 512694588 ps
CPU time 6.87 seconds
Started Aug 07 06:13:54 PM PDT 24
Finished Aug 07 06:14:01 PM PDT 24
Peak memory 217656 kb
Host smart-19b0bc00-72b5-4544-a79c-df59921bea55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078193909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
078193909
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1925679608
Short name T665
Test name
Test status
Simulation time 1516718145 ps
CPU time 3.36 seconds
Started Aug 07 06:13:59 PM PDT 24
Finished Aug 07 06:14:02 PM PDT 24
Peak memory 218168 kb
Host smart-e339759c-d1fe-4512-a67d-f878e7a71aec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925679608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1925679608
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.123553575
Short name T794
Test name
Test status
Simulation time 4620916193 ps
CPU time 19.64 seconds
Started Aug 07 06:14:05 PM PDT 24
Finished Aug 07 06:14:25 PM PDT 24
Peak memory 217932 kb
Host smart-202ec47c-4a36-40e6-a2ad-17eb4f1429f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123553575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.123553575
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.780993969
Short name T101
Test name
Test status
Simulation time 775599073 ps
CPU time 12.58 seconds
Started Aug 07 06:14:00 PM PDT 24
Finished Aug 07 06:14:13 PM PDT 24
Peak memory 217656 kb
Host smart-1d34233e-8fe7-4b81-b797-a55870d5aaa3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780993969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.780993969
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2878791874
Short name T742
Test name
Test status
Simulation time 14768934197 ps
CPU time 45.88 seconds
Started Aug 07 06:13:55 PM PDT 24
Finished Aug 07 06:14:41 PM PDT 24
Peak memory 250824 kb
Host smart-037cb131-63aa-4695-b6fb-e569e001a916
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878791874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2878791874
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1874535437
Short name T290
Test name
Test status
Simulation time 1420552319 ps
CPU time 10.95 seconds
Started Aug 07 06:13:57 PM PDT 24
Finished Aug 07 06:14:08 PM PDT 24
Peak memory 250552 kb
Host smart-0d340727-cb7f-4e62-b13e-f4b672fb9c4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874535437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1874535437
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2142861761
Short name T378
Test name
Test status
Simulation time 101525738 ps
CPU time 3.13 seconds
Started Aug 07 06:13:57 PM PDT 24
Finished Aug 07 06:14:00 PM PDT 24
Peak memory 218196 kb
Host smart-a7feb577-7446-48d8-8b64-363ed33df2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142861761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2142861761
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2249622195
Short name T721
Test name
Test status
Simulation time 1374516231 ps
CPU time 21.76 seconds
Started Aug 07 06:14:06 PM PDT 24
Finished Aug 07 06:14:28 PM PDT 24
Peak memory 214428 kb
Host smart-cf555494-5691-46db-8d93-3f488a009d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249622195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2249622195
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3176123825
Short name T409
Test name
Test status
Simulation time 734404342 ps
CPU time 16.01 seconds
Started Aug 07 06:13:57 PM PDT 24
Finished Aug 07 06:14:13 PM PDT 24
Peak memory 218856 kb
Host smart-b72fcacf-eda0-43c8-bc53-b2cfae4b7cad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176123825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3176123825
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3117341139
Short name T412
Test name
Test status
Simulation time 998454889 ps
CPU time 9.48 seconds
Started Aug 07 06:13:59 PM PDT 24
Finished Aug 07 06:14:09 PM PDT 24
Peak memory 225964 kb
Host smart-5f184468-284e-4822-933a-d8c894916312
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117341139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3117341139
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2298620773
Short name T522
Test name
Test status
Simulation time 293294343 ps
CPU time 11.53 seconds
Started Aug 07 06:14:06 PM PDT 24
Finished Aug 07 06:14:17 PM PDT 24
Peak memory 226136 kb
Host smart-a9f543f3-39ca-4ddf-9015-319b4ec6f8f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298620773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
298620773
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1606961745
Short name T516
Test name
Test status
Simulation time 313124445 ps
CPU time 8.22 seconds
Started Aug 07 06:13:58 PM PDT 24
Finished Aug 07 06:14:06 PM PDT 24
Peak memory 218268 kb
Host smart-7fef2f30-78b1-405e-9464-9a4370698df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606961745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1606961745
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.958444596
Short name T406
Test name
Test status
Simulation time 25581840 ps
CPU time 2.16 seconds
Started Aug 07 06:14:07 PM PDT 24
Finished Aug 07 06:14:09 PM PDT 24
Peak memory 214324 kb
Host smart-ec4ce12d-dcf9-486c-9051-298df9f4e4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958444596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.958444596
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3054589687
Short name T306
Test name
Test status
Simulation time 260303291 ps
CPU time 22.37 seconds
Started Aug 07 06:14:02 PM PDT 24
Finished Aug 07 06:14:25 PM PDT 24
Peak memory 250852 kb
Host smart-86677804-df5c-4084-9bdc-3953fb3dd9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054589687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3054589687
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.315134888
Short name T460
Test name
Test status
Simulation time 188884945 ps
CPU time 2.9 seconds
Started Aug 07 06:13:53 PM PDT 24
Finished Aug 07 06:13:56 PM PDT 24
Peak memory 222160 kb
Host smart-b38aae3a-33fe-4d4b-a70b-4c19ead87d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315134888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.315134888
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1851615060
Short name T525
Test name
Test status
Simulation time 1664572563 ps
CPU time 40.89 seconds
Started Aug 07 06:13:54 PM PDT 24
Finished Aug 07 06:14:35 PM PDT 24
Peak memory 250840 kb
Host smart-40b8b88a-f263-4d12-a263-a7af507cdfa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851615060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1851615060
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2466638353
Short name T596
Test name
Test status
Simulation time 15702640 ps
CPU time 0.9 seconds
Started Aug 07 06:13:55 PM PDT 24
Finished Aug 07 06:13:56 PM PDT 24
Peak memory 208832 kb
Host smart-a4bdcacf-9c41-4856-906f-bbd5ebd18284
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466638353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2466638353
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1915222342
Short name T839
Test name
Test status
Simulation time 83223855 ps
CPU time 0.94 seconds
Started Aug 07 06:14:08 PM PDT 24
Finished Aug 07 06:14:09 PM PDT 24
Peak memory 208832 kb
Host smart-ce59ead5-2a78-4aad-aa51-3c846b55e0a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915222342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1915222342
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1982249109
Short name T212
Test name
Test status
Simulation time 14533871 ps
CPU time 0.92 seconds
Started Aug 07 06:14:04 PM PDT 24
Finished Aug 07 06:14:05 PM PDT 24
Peak memory 208764 kb
Host smart-c69b28af-b26d-4173-a80d-b2379a2c582a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982249109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1982249109
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.949484123
Short name T415
Test name
Test status
Simulation time 195749055 ps
CPU time 10.17 seconds
Started Aug 07 06:14:00 PM PDT 24
Finished Aug 07 06:14:11 PM PDT 24
Peak memory 226056 kb
Host smart-f9661d9e-f37d-455a-b184-36ae00606f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949484123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.949484123
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2243492906
Short name T677
Test name
Test status
Simulation time 307121884 ps
CPU time 3.63 seconds
Started Aug 07 06:14:01 PM PDT 24
Finished Aug 07 06:14:05 PM PDT 24
Peak memory 217080 kb
Host smart-5a353594-54e6-4e09-90bb-f81b9a6a992e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243492906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2243492906
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.4230954421
Short name T285
Test name
Test status
Simulation time 10416382708 ps
CPU time 74.11 seconds
Started Aug 07 06:14:06 PM PDT 24
Finished Aug 07 06:15:20 PM PDT 24
Peak memory 218860 kb
Host smart-e4efc948-af89-41a8-ab47-c4cde926e160
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230954421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.4230954421
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2602721373
Short name T206
Test name
Test status
Simulation time 353083106 ps
CPU time 2.61 seconds
Started Aug 07 06:14:04 PM PDT 24
Finished Aug 07 06:14:07 PM PDT 24
Peak memory 217672 kb
Host smart-983fb8b5-6046-4b17-b3d8-f64fe397ca7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602721373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
602721373
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3324252495
Short name T292
Test name
Test status
Simulation time 118768556 ps
CPU time 4.59 seconds
Started Aug 07 06:14:08 PM PDT 24
Finished Aug 07 06:14:13 PM PDT 24
Peak memory 218168 kb
Host smart-e21790ad-e97a-477b-993e-b101e84103cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324252495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3324252495
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.458879599
Short name T71
Test name
Test status
Simulation time 2221224007 ps
CPU time 15.47 seconds
Started Aug 07 06:14:07 PM PDT 24
Finished Aug 07 06:14:22 PM PDT 24
Peak memory 217592 kb
Host smart-4d6f2088-a541-4c64-ba95-40eb63eb0b28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458879599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.458879599
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2548566027
Short name T535
Test name
Test status
Simulation time 298426633 ps
CPU time 8.22 seconds
Started Aug 07 06:14:05 PM PDT 24
Finished Aug 07 06:14:13 PM PDT 24
Peak memory 217568 kb
Host smart-f54794ed-30b5-483f-a9d4-19d7c22478c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548566027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2548566027
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3999680417
Short name T791
Test name
Test status
Simulation time 3763435266 ps
CPU time 72.64 seconds
Started Aug 07 06:14:04 PM PDT 24
Finished Aug 07 06:15:17 PM PDT 24
Peak memory 280892 kb
Host smart-0cca6f11-1d44-4e3b-a403-0264d1a02fde
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999680417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3999680417
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3409138967
Short name T173
Test name
Test status
Simulation time 651871468 ps
CPU time 11.78 seconds
Started Aug 07 06:14:03 PM PDT 24
Finished Aug 07 06:14:15 PM PDT 24
Peak memory 250272 kb
Host smart-bab1bb1c-3112-4607-95cb-59bf856b0dcd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409138967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3409138967
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3425165567
Short name T99
Test name
Test status
Simulation time 265807028 ps
CPU time 2.84 seconds
Started Aug 07 06:14:07 PM PDT 24
Finished Aug 07 06:14:10 PM PDT 24
Peak memory 218464 kb
Host smart-a81ef443-dde3-4ee8-aade-3c7982bfdc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425165567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3425165567
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.421914416
Short name T765
Test name
Test status
Simulation time 1547674894 ps
CPU time 16.04 seconds
Started Aug 07 06:14:06 PM PDT 24
Finished Aug 07 06:14:23 PM PDT 24
Peak memory 217656 kb
Host smart-cf2942e6-ff37-4cbe-8150-efacdf30747e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421914416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.421914416
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2992908592
Short name T779
Test name
Test status
Simulation time 1657133774 ps
CPU time 13.33 seconds
Started Aug 07 06:14:07 PM PDT 24
Finished Aug 07 06:14:20 PM PDT 24
Peak memory 218880 kb
Host smart-dd18033f-0a04-401d-b185-ad8a845d717d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992908592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2992908592
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.738624495
Short name T469
Test name
Test status
Simulation time 242728745 ps
CPU time 11.47 seconds
Started Aug 07 06:14:04 PM PDT 24
Finished Aug 07 06:14:16 PM PDT 24
Peak memory 225940 kb
Host smart-49a8e3f7-ed6a-4862-924a-fa8b340a5855
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738624495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.738624495
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2346960292
Short name T605
Test name
Test status
Simulation time 1237015138 ps
CPU time 13.05 seconds
Started Aug 07 06:14:06 PM PDT 24
Finished Aug 07 06:14:19 PM PDT 24
Peak memory 226000 kb
Host smart-4b1d1b21-c38d-4400-b2ab-d7078936f48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346960292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2346960292
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3892747483
Short name T766
Test name
Test status
Simulation time 161064729 ps
CPU time 2.93 seconds
Started Aug 07 06:13:56 PM PDT 24
Finished Aug 07 06:13:59 PM PDT 24
Peak memory 214340 kb
Host smart-11d05566-5905-4abc-ab55-32fcba05d746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892747483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3892747483
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2423239918
Short name T495
Test name
Test status
Simulation time 461852035 ps
CPU time 27.66 seconds
Started Aug 07 06:14:02 PM PDT 24
Finished Aug 07 06:14:30 PM PDT 24
Peak memory 250776 kb
Host smart-4ab45fc9-77b2-4205-97d4-35e6e43794b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423239918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2423239918
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2330024014
Short name T699
Test name
Test status
Simulation time 147704188 ps
CPU time 8.25 seconds
Started Aug 07 06:14:01 PM PDT 24
Finished Aug 07 06:14:10 PM PDT 24
Peak memory 250872 kb
Host smart-e1e6ff3a-cd62-4d58-a6d2-d8edecc66e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330024014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2330024014
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3458490028
Short name T462
Test name
Test status
Simulation time 2890911315 ps
CPU time 54.65 seconds
Started Aug 07 06:14:02 PM PDT 24
Finished Aug 07 06:14:57 PM PDT 24
Peak memory 250752 kb
Host smart-9f5c2398-7d6f-4d42-b4e3-fdf97523112d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458490028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3458490028
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1964413039
Short name T277
Test name
Test status
Simulation time 30577369 ps
CPU time 0.95 seconds
Started Aug 07 06:14:06 PM PDT 24
Finished Aug 07 06:14:07 PM PDT 24
Peak memory 212080 kb
Host smart-f32fad98-2c92-461c-aeea-a707f3dc6dd3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964413039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1964413039
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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