Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112663764

1

T1

42483

T2

2547

T3

26416

auto[1]

1460376

1

T2

297

T3

1485

T12

1881

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112660093

1

T1

42483

T2

2547

T3

27010

auto[1]

1464047

1

T2

297

T3

891

T12

1584

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7639684	1			T1	6129		T2	623		T3	7681
auto[IdleSt]	23602888	1			T1	8442		T2	1066		T3	2009
auto[ClkMuxSt]	36773	1			T1	68		T2	6		T3	60
auto[CntIncrSt]	36560	1			T1	68		T2	6		T3	60
auto[CntProgSt]	1722772	1			T1	3400		T2	12		T3	3230
auto[TransCheckSt]	28526	1			T1	68		T3	48		T11	1
auto[TokenHashSt]	46363636	1			T1	13315		T3	991		T11	26
auto[FlashRmaSt]	35876	1			T1	88		T3	77		T11	1
auto[TokenCheck0St]	13147	1			T1	31		T3	32		T11	1
auto[TokenCheck1St]	9713	1			T1	10		T3	21		T11	1
auto[TransProgSt]	506351	1			T3	1699		T11	5		T12	1323
auto[PostTransSt]	14158554	1			T1	10864		T2	397		T3	8072
auto[ScrapSt]	81853	1			T15	4		T21	1803		T44	39
auto[EscalateSt]	7285907	1			T2	734		T3	2983		T12	4886
auto[InvalidSt]	12599644	1			T3	938		T12	3778		T16	520

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2256	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12599644	1			T3	938		T12	3778		T16	520
EscalateSt	7285907	1			T2	734		T3	2983		T12	4886
ScrapSt	81853	1			T15	4		T21	1803		T44	39
PostTransSt	14158554	1			T1	10864		T2	397		T3	8072
TransProgSt	506351	1			T3	1699		T11	5		T12	1323
TokenCheck1St	9713	1			T1	10		T3	21		T11	1
TokenCheck0St	13147	1			T1	31		T3	32		T11	1
FlashRmaSt	35876	1			T1	88		T3	77		T11	1
TokenHashSt	46363636	1			T1	13315		T3	991		T11	26
TransCheckSt	28526	1			T1	68		T3	48		T11	1
CntProgSt	1722772	1			T1	3400		T2	12		T3	3230
CntIncrSt	36560	1			T1	68		T2	6		T3	60
ClkMuxSt	36773	1			T1	68		T2	6		T3	60
IdleSt	23602888	1			T1	8442		T2	1066		T3	2009
ResetSt	7639684	1			T1	6129		T2	623		T3	7681
arcs[ResetSt=>IdleSt]	56517	1			T1	69		T2	7		T3	73
arcs[IdleSt=>ScrapSt]	233	1			T15	1		T21	5		T44	1
arcs[IdleSt=>ClkMuxSt]	36576	1			T1	68		T2	6		T3	60
arcs[ClkMuxSt=>CntIncrSt]	36560	1			T1	68		T2	6		T3	60
arcs[CntIncrSt=>PostTransSt]	2029	1			T10	11		T21	65		T40	12
arcs[CntIncrSt=>CntProgSt]	34475	1			T1	68		T2	6		T3	60
arcs[CntProgSt=>PostTransSt]	5050	1			T2	6		T3	12		T12	15
arcs[CntProgSt=>TransCheckSt]	28526	1			T1	68		T3	48		T11	1
arcs[TransCheckSt=>PostTransSt]	3860	1			T1	29		T10	13		T21	72
arcs[TransCheckSt=>TokenHashSt]	24539	1			T1	39		T3	48		T11	1
arcs[TokenHashSt=>PostTransSt]	10405	1			T1	8		T3	16		T12	9
arcs[TokenHashSt=>FlashRmaSt]	13180	1			T1	31		T3	32		T11	1
arcs[FlashRmaSt=>TokenCheck0St]	13147	1			T1	31		T3	32		T11	1
arcs[TokenCheck0St=>PostTransSt]	3388	1			T1	21		T3	11		T12	22
arcs[TokenCheck0St=>TokenCheck1St]	9713	1			T1	10		T3	21		T11	1
arcs[TokenCheck1St=>PostTransSt]	672	1			T1	10		T10	1		T21	11
arcs[TransProgSt=>PostTransSt]	8291	1			T3	21		T11	1		T12	31
arcs[IdleSt=>EscalateSt]	129	1			T30	2		T50	4		T53	8
arcs[ClkMuxSt=>EscalateSt]	16	1			T30	1		T50	1		T51	1
arcs[CntIncrSt=>EscalateSt]	56	1			T15	1		T30	1		T52	1
arcs[CntProgSt=>EscalateSt]	899	1			T15	25		T30	15		T52	7
arcs[TransCheckSt=>EscalateSt]	127	1			T15	1		T52	4		T57	1
arcs[TokenHashSt=>EscalateSt]	954	1			T15	6		T30	9		T34	1
arcs[FlashRmaSt=>EscalateSt]	33	1			T30	2		T52	1		T50	2
arcs[TokenCheck0St=>EscalateSt]	46	1			T15	2		T57	1		T50	4
arcs[TokenCheck1St=>EscalateSt]	35	1			T52	1		T57	1		T53	2
arcs[TransProgSt=>EscalateSt]	715	1			T15	10		T30	24		T52	2
arcs[PostTransSt=>EscalateSt]	5405	1			T2	6		T3	12		T12	15
arcs[InvalidSt=>EscalateSt]	15365	1			T3	12		T12	20		T16	7

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7639510	1			T1	6129		T2	623		T3	7681
auto[0]	auto[IdleSt]	23602803	1			T1	8442		T2	1066		T3	2009
auto[0]	auto[ClkMuxSt]	36762	1			T1	68		T2	6		T3	60
auto[0]	auto[CntIncrSt]	36523	1			T1	68		T2	6		T3	60
auto[0]	auto[CntProgSt]	1722169	1			T1	3400		T2	12		T3	3230
auto[0]	auto[TransCheckSt]	28443	1			T1	68		T3	48		T11	1
auto[0]	auto[TokenHashSt]	46363019	1			T1	13315		T3	991		T11	26
auto[0]	auto[FlashRmaSt]	35853	1			T1	88		T3	77		T11	1
auto[0]	auto[TokenCheck0St]	13119	1			T1	31		T3	32		T11	1
auto[0]	auto[TokenCheck1St]	9688	1			T1	10		T3	21		T11	1
auto[0]	auto[TransProgSt]	505881	1			T3	1699		T11	5		T12	1323
auto[0]	auto[PostTransSt]	14155760	1			T1	10864		T2	394		T3	8065
auto[0]	auto[ScrapSt]	81819	1			T15	4		T21	1803		T44	39
auto[0]	auto[EscalateSt]	5838203	1			T2	440		T3	1513		T12	3024
auto[0]	auto[InvalidSt]	12591956	1			T3	930		T12	3766		T16	517
auto[1]	auto[ResetSt]	174	1			T15	3		T30	4		T52	3
auto[1]	auto[IdleSt]	85	1			T30	1		T50	4		T53	4
auto[1]	auto[ClkMuxSt]	11	1			T50	1		T51	1		T190	2
auto[1]	auto[CntIncrSt]	37	1			T15	1		T30	1		T57	1
auto[1]	auto[CntProgSt]	603	1			T15	14		T30	11		T52	3
auto[1]	auto[TransCheckSt]	83	1			T52	3		T57	1		T50	3
auto[1]	auto[TokenHashSt]	617	1			T15	5		T30	6		T52	14
auto[1]	auto[FlashRmaSt]	23	1			T30	1		T52	1		T50	2
auto[1]	auto[TokenCheck0St]	28	1			T15	1		T57	1		T50	3
auto[1]	auto[TokenCheck1St]	25	1			T53	1		T191	2		T161	1
auto[1]	auto[TransProgSt]	470	1			T15	7		T30	15		T52	2
auto[1]	auto[PostTransSt]	2794	1			T2	3		T3	7		T12	7
auto[1]	auto[ScrapSt]	34	1			T30	2		T52	1		T50	1
auto[1]	auto[EscalateSt]	1447704	1			T2	294		T3	1470		T12	1862
auto[1]	auto[InvalidSt]	7688	1			T3	8		T12	12		T16	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7639504	1			T1	6129		T2	623		T3	7681
auto[0]	auto[IdleSt]	23602800	1			T1	8442		T2	1066		T3	2009
auto[0]	auto[ClkMuxSt]	36763	1			T1	68		T2	6		T3	60
auto[0]	auto[CntIncrSt]	36522	1			T1	68		T2	6		T3	60
auto[0]	auto[CntProgSt]	1722144	1			T1	3400		T2	12		T3	3230
auto[0]	auto[TransCheckSt]	28442	1			T1	68		T3	48		T11	1
auto[0]	auto[TokenHashSt]	46362989	1			T1	13315		T3	991		T11	26
auto[0]	auto[FlashRmaSt]	35850	1			T1	88		T3	77		T11	1
auto[0]	auto[TokenCheck0St]	13116	1			T1	31		T3	32		T11	1
auto[0]	auto[TokenCheck1St]	9689	1			T1	10		T3	21		T11	1
auto[0]	auto[TransProgSt]	505871	1			T3	1699		T11	5		T12	1323
auto[0]	auto[PostTransSt]	14155834	1			T1	10864		T2	394		T3	8067
auto[0]	auto[ScrapSt]	81822	1			T15	3		T21	1803		T44	39
auto[0]	auto[EscalateSt]	5834524	1			T2	440		T3	2101		T12	3318
auto[0]	auto[InvalidSt]	12591967	1			T3	934		T12	3770		T16	516
auto[1]	auto[ResetSt]	180	1			T15	6		T30	6		T52	1
auto[1]	auto[IdleSt]	88	1			T30	2		T50	1		T53	7
auto[1]	auto[ClkMuxSt]	10	1			T30	1		T51	1		T190	2
auto[1]	auto[CntIncrSt]	38	1			T15	1		T30	1		T52	1
auto[1]	auto[CntProgSt]	628	1			T15	17		T30	12		T52	6
auto[1]	auto[TransCheckSt]	84	1			T15	1		T52	3		T57	1
auto[1]	auto[TokenHashSt]	647	1			T15	3		T30	9		T34	1
auto[1]	auto[FlashRmaSt]	26	1			T30	1		T52	1		T50	1
auto[1]	auto[TokenCheck0St]	31	1			T15	2		T57	1		T50	3
auto[1]	auto[TokenCheck1St]	24	1			T52	1		T57	1		T53	2
auto[1]	auto[TransProgSt]	480	1			T15	7		T30	17		T52	2
auto[1]	auto[PostTransSt]	2720	1			T2	3		T3	5		T12	8
auto[1]	auto[ScrapSt]	31	1			T15	1		T52	1		T93	1
auto[1]	auto[EscalateSt]	1451383	1			T2	294		T3	882		T12	1568
auto[1]	auto[InvalidSt]	7677	1			T3	4		T12	8		T16	4