Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105431792

1

T1

2055

T2

49687

T3

1104

auto[1]

1490973

1

T2

784

T4

1980

T5

3626

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105442748

1

T1

2055

T2

49295

T3

1104

auto[1]

1480017

1

T2

1176

T4

990

T5

3626

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7714448	1			T1	97		T2	2191		T3	104
auto[IdleSt]	22373143	1			T1	1958		T2	21399		T3	1000
auto[ClkMuxSt]	37130	1			T2	20		T4	60		T6	165
auto[CntIncrSt]	36860	1			T2	20		T4	60		T6	159
auto[CntProgSt]	1618091	1			T2	7634		T4	883		T6	1702
auto[TransCheckSt]	28653	1			T4	47		T6	105		T10	1
auto[TokenHashSt]	40625349	1			T4	510		T6	345537		T10	12
auto[FlashRmaSt]	37759	1			T4	112		T6	120		T10	1
auto[TokenCheck0St]	13195	1			T4	41		T6	69		T10	1
auto[TokenCheck1St]	9654	1			T4	22		T6	58		T10	1
auto[TransProgSt]	426310	1			T4	329		T6	742		T10	30
auto[PostTransSt]	13349117	1			T2	10953		T4	9203		T6	38850
auto[ScrapSt]	147251	1			T6	2352		T12	16		T14	12
auto[EscalateSt]	7438846	1			T2	8254		T4	4263		T5	42350
auto[InvalidSt]	13064819	1			T4	2652		T5	148967		T6	4806

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2140	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13064819	1			T4	2652		T5	148967		T6	4806
EscalateSt	7438846	1			T2	8254		T4	4263		T5	42350
ScrapSt	147251	1			T6	2352		T12	16		T14	12
PostTransSt	13349117	1			T2	10953		T4	9203		T6	38850
TransProgSt	426310	1			T4	329		T6	742		T10	30
TokenCheck1St	9654	1			T4	22		T6	58		T10	1
TokenCheck0St	13195	1			T4	41		T6	69		T10	1
FlashRmaSt	37759	1			T4	112		T6	120		T10	1
TokenHashSt	40625349	1			T4	510		T6	345537		T10	12
TransCheckSt	28653	1			T4	47		T6	105		T10	1
CntProgSt	1618091	1			T2	7634		T4	883		T6	1702
CntIncrSt	36860	1			T2	20		T4	60		T6	159
ClkMuxSt	37130	1			T2	20		T4	60		T6	165
IdleSt	22373143	1			T1	1958		T2	21399		T3	1000
ResetSt	7714448	1			T1	97		T2	2191		T3	104
arcs[ResetSt=>IdleSt]	57075	1			T1	1		T2	21		T3	1
arcs[IdleSt=>ScrapSt]	319	1			T6	2		T12	1		T14	3
arcs[IdleSt=>ClkMuxSt]	36889	1			T2	20		T4	60		T6	159
arcs[ClkMuxSt=>CntIncrSt]	36860	1			T2	20		T4	60		T6	159
arcs[CntIncrSt=>PostTransSt]	1887	1			T6	6		T11	9		T17	11
arcs[CntIncrSt=>CntProgSt]	34914	1			T2	20		T4	60		T6	153
arcs[CntProgSt=>PostTransSt]	5178	1			T2	20		T4	13		T6	48
arcs[CntProgSt=>TransCheckSt]	28653	1			T4	47		T6	105		T10	1
arcs[TransCheckSt=>PostTransSt]	3780	1			T6	7		T11	7		T17	16
arcs[TransCheckSt=>TokenHashSt]	24768	1			T4	47		T6	98		T10	1
arcs[TokenHashSt=>PostTransSt]	10717	1			T4	6		T6	29		T11	25
arcs[TokenHashSt=>FlashRmaSt]	13246	1			T4	41		T6	69		T10	1
arcs[FlashRmaSt=>TokenCheck0St]	13195	1			T4	41		T6	69		T10	1
arcs[TokenCheck0St=>PostTransSt]	3477	1			T4	19		T6	11		T11	9
arcs[TokenCheck0St=>TokenCheck1St]	9654	1			T4	22		T6	58		T10	1
arcs[TokenCheck1St=>PostTransSt]	614	1			T11	2		T17	1		T18	1
arcs[TransProgSt=>PostTransSt]	8172	1			T4	22		T6	58		T10	1
arcs[IdleSt=>EscalateSt]	195	1			T55	3		T57	2		T58	7
arcs[ClkMuxSt=>EscalateSt]	29	1			T51	2		T52	3		T53	1
arcs[CntIncrSt=>EscalateSt]	59	1			T54	1		T51	1		T55	2
arcs[CntProgSt=>EscalateSt]	1083	1			T54	47		T56	3		T51	24
arcs[TransCheckSt=>EscalateSt]	105	1			T54	1		T56	3		T57	4
arcs[TokenHashSt=>EscalateSt]	805	1			T54	7		T56	30		T51	8
arcs[FlashRmaSt=>EscalateSt]	51	1			T54	2		T56	2		T51	1
arcs[TokenCheck0St=>EscalateSt]	64	1			T54	1		T56	1		T51	1
arcs[TokenCheck1St=>EscalateSt]	37	1			T54	2		T56	1		T51	2
arcs[TransProgSt=>EscalateSt]	831	1			T54	25		T56	9		T51	26
arcs[PostTransSt=>EscalateSt]	5524	1			T2	20		T4	13		T6	48
arcs[InvalidSt=>EscalateSt]	15137	1			T4	17		T5	74		T6	64

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7714265	1			T1	97		T2	2191		T3	104
auto[0]	auto[IdleSt]	22373004	1			T1	1958		T2	21399		T3	1000
auto[0]	auto[ClkMuxSt]	37108	1			T2	20		T4	60		T6	165
auto[0]	auto[CntIncrSt]	36825	1			T2	20		T4	60		T6	159
auto[0]	auto[CntProgSt]	1617370	1			T2	7634		T4	883		T6	1702
auto[0]	auto[TransCheckSt]	28578	1			T4	47		T6	105		T10	1
auto[0]	auto[TokenHashSt]	40624802	1			T4	510		T6	345537		T10	12
auto[0]	auto[FlashRmaSt]	37722	1			T4	112		T6	120		T10	1
auto[0]	auto[TokenCheck0St]	13147	1			T4	41		T6	69		T10	1
auto[0]	auto[TokenCheck1St]	9631	1			T4	22		T6	58		T10	1
auto[0]	auto[TransProgSt]	425771	1			T4	329		T6	742		T10	30
auto[0]	auto[PostTransSt]	13346337	1			T2	10945		T4	9194		T6	38826
auto[0]	auto[ScrapSt]	147191	1			T6	2352		T12	16		T14	12
auto[0]	auto[EscalateSt]	5960666	1			T2	7478		T4	2303		T5	38761
auto[0]	auto[InvalidSt]	13057235	1			T4	2641		T5	148930		T6	4776
auto[1]	auto[ResetSt]	183	1			T54	3		T56	3		T51	3
auto[1]	auto[IdleSt]	139	1			T55	2		T57	2		T58	4
auto[1]	auto[ClkMuxSt]	22	1			T51	1		T52	2		T53	1
auto[1]	auto[CntIncrSt]	35	1			T54	1		T51	1		T55	2
auto[1]	auto[CntProgSt]	721	1			T54	30		T56	2		T51	14
auto[1]	auto[TransCheckSt]	75	1			T54	1		T56	2		T57	1
auto[1]	auto[TokenHashSt]	547	1			T54	7		T56	21		T51	4
auto[1]	auto[FlashRmaSt]	37	1			T54	2		T56	2		T51	1
auto[1]	auto[TokenCheck0St]	48	1			T54	1		T56	1		T51	1
auto[1]	auto[TokenCheck1St]	23	1			T54	1		T56	1		T51	1
auto[1]	auto[TransProgSt]	539	1			T54	15		T56	7		T51	16
auto[1]	auto[PostTransSt]	2780	1			T2	8		T4	9		T6	24
auto[1]	auto[ScrapSt]	60	1			T54	1		T56	2		T51	4
auto[1]	auto[EscalateSt]	1478180	1			T2	776		T4	1960		T5	3589
auto[1]	auto[InvalidSt]	7584	1			T4	11		T5	37		T6	30

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7714258	1			T1	97		T2	2191		T3	104
auto[0]	auto[IdleSt]	22373015	1			T1	1958		T2	21399		T3	1000
auto[0]	auto[ClkMuxSt]	37113	1			T2	20		T4	60		T6	165
auto[0]	auto[CntIncrSt]	36817	1			T2	20		T4	60		T6	159
auto[0]	auto[CntProgSt]	1617409	1			T2	7634		T4	883		T6	1702
auto[0]	auto[TransCheckSt]	28593	1			T4	47		T6	105		T10	1
auto[0]	auto[TokenHashSt]	40624808	1			T4	510		T6	345537		T10	12
auto[0]	auto[FlashRmaSt]	37732	1			T4	112		T6	120		T10	1
auto[0]	auto[TokenCheck0St]	13161	1			T4	41		T6	69		T10	1
auto[0]	auto[TokenCheck1St]	9631	1			T4	22		T6	58		T10	1
auto[0]	auto[TransProgSt]	425750	1			T4	329		T6	742		T10	30
auto[0]	auto[PostTransSt]	13346267	1			T2	10941		T4	9199		T6	38826
auto[0]	auto[ScrapSt]	147187	1			T6	2352		T12	16		T14	12
auto[0]	auto[EscalateSt]	5971601	1			T2	7090		T4	3283		T5	38761
auto[0]	auto[InvalidSt]	13057266	1			T4	2646		T5	148930		T6	4772
auto[1]	auto[ResetSt]	190	1			T54	1		T56	3		T51	2
auto[1]	auto[IdleSt]	128	1			T55	2		T57	1		T58	4
auto[1]	auto[ClkMuxSt]	17	1			T51	2		T52	1		T53	1
auto[1]	auto[CntIncrSt]	43	1			T54	1		T51	1		T55	2
auto[1]	auto[CntProgSt]	682	1			T54	25		T56	1		T51	18
auto[1]	auto[TransCheckSt]	60	1			T56	2		T57	3		T58	1
auto[1]	auto[TokenHashSt]	541	1			T54	3		T56	21		T51	7
auto[1]	auto[FlashRmaSt]	27	1			T54	1		T56	1		T51	1
auto[1]	auto[TokenCheck0St]	34	1			T54	1		T57	2		T189	1
auto[1]	auto[TokenCheck1St]	23	1			T54	1		T56	1		T51	1
auto[1]	auto[TransProgSt]	560	1			T54	16		T56	4		T51	15
auto[1]	auto[PostTransSt]	2850	1			T2	12		T4	4		T6	24
auto[1]	auto[ScrapSt]	64	1			T56	1		T51	3		T55	1
auto[1]	auto[EscalateSt]	1467245	1			T2	1164		T4	980		T5	3589
auto[1]	auto[InvalidSt]	7553	1			T4	6		T5	37		T6	34