Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117582706

1

T1

24052

T2

31148

T3

4707

auto[1]

1453909

1

T4

19783

T10

396

T12

9874

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117588251

1

T1

24052

T2

31148

T3

4707

auto[1]

1448364

1

T4

20182

T10

198

T12

10043

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7926096	1			T1	1419		T2	1665		T3	117
auto[IdleSt]	24878237	1			T1	15610		T2	22947		T3	4590
auto[ClkMuxSt]	38527	1			T1	14		T2	18		T4	704
auto[CntIncrSt]	38244	1			T1	14		T2	18		T4	704
auto[CntProgSt]	1722786	1			T1	28		T2	99		T4	1191
auto[TransCheckSt]	29639	1			T1	14		T2	18		T4	502
auto[TokenHashSt]	49519548	1			T1	4189		T2	1855		T4	38264
auto[FlashRmaSt]	38690	1			T1	14		T2	45		T4	451
auto[TokenCheck0St]	13774	1			T1	14		T2	18		T4	191
auto[TokenCheck1St]	10053	1			T1	14		T2	18		T4	121
auto[TransProgSt]	387883	1			T1	28		T2	88		T4	231
auto[PostTransSt]	14983751	1			T1	2694		T2	4359		T4	360357
auto[ScrapSt]	149558	1			T12	8		T15	9		T16	8
auto[EscalateSt]	7257138	1			T4	90841		T10	763		T12	15769
auto[InvalidSt]	12040585	1			T4	61976		T13	486		T15	89918

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2106	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12040585	1			T4	61976		T13	486		T15	89918
EscalateSt	7257138	1			T4	90841		T10	763		T12	15769
ScrapSt	149558	1			T12	8		T15	9		T16	8
PostTransSt	14983751	1			T1	2694		T2	4359		T4	360357
TransProgSt	387883	1			T1	28		T2	88		T4	231
TokenCheck1St	10053	1			T1	14		T2	18		T4	121
TokenCheck0St	13774	1			T1	14		T2	18		T4	191
FlashRmaSt	38690	1			T1	14		T2	45		T4	451
TokenHashSt	49519548	1			T1	4189		T2	1855		T4	38264
TransCheckSt	29639	1			T1	14		T2	18		T4	502
CntProgSt	1722786	1			T1	28		T2	99		T4	1191
CntIncrSt	38244	1			T1	14		T2	18		T4	704
ClkMuxSt	38527	1			T1	14		T2	18		T4	704
IdleSt	24878237	1			T1	15610		T2	22947		T3	4590
ResetSt	7926096	1			T1	1419		T2	1665		T3	117
arcs[ResetSt=>IdleSt]	57867	1			T1	14		T2	18		T3	1
arcs[IdleSt=>ScrapSt]	302	1			T12	2		T15	1		T16	2
arcs[IdleSt=>ClkMuxSt]	38289	1			T1	14		T2	18		T4	704
arcs[ClkMuxSt=>CntIncrSt]	38244	1			T1	14		T2	18		T4	704
arcs[CntIncrSt=>PostTransSt]	2085	1			T4	73		T10	8		T15	30
arcs[CntIncrSt=>CntProgSt]	36113	1			T1	14		T2	18		T4	631
arcs[CntProgSt=>PostTransSt]	5484	1			T4	129		T10	6		T15	37
arcs[CntProgSt=>TransCheckSt]	29639	1			T1	14		T2	18		T4	502
arcs[TransCheckSt=>PostTransSt]	4043	1			T4	78		T10	13		T15	32
arcs[TransCheckSt=>TokenHashSt]	25484	1			T1	14		T2	18		T4	424
arcs[TokenHashSt=>PostTransSt]	10875	1			T4	233		T10	34		T15	70
arcs[TokenHashSt=>FlashRmaSt]	13808	1			T1	14		T2	18		T4	191
arcs[FlashRmaSt=>TokenCheck0St]	13774	1			T1	14		T2	18		T4	191
arcs[TokenCheck0St=>PostTransSt]	3662	1			T4	70		T10	10		T15	27
arcs[TokenCheck0St=>TokenCheck1St]	10053	1			T1	14		T2	18		T4	121
arcs[TokenCheck1St=>PostTransSt]	669	1			T4	3		T10	1		T15	1
arcs[TransProgSt=>PostTransSt]	8570	1			T1	14		T2	18		T4	118
arcs[IdleSt=>EscalateSt]	156	1			T16	5		T32	2		T51	5
arcs[ClkMuxSt=>EscalateSt]	45	1			T32	3		T51	1		T52	2
arcs[CntIncrSt=>EscalateSt]	46	1			T12	1		T16	2		T32	1
arcs[CntProgSt=>EscalateSt]	990	1			T12	42		T16	19		T32	19
arcs[TransCheckSt=>EscalateSt]	112	1			T12	1		T16	2		T32	1
arcs[TokenHashSt=>EscalateSt]	801	1			T12	20		T16	11		T32	6
arcs[FlashRmaSt=>EscalateSt]	34	1			T12	2		T16	2		T53	2
arcs[TokenCheck0St=>EscalateSt]	59	1			T12	1		T32	1		T57	1
arcs[TokenCheck1St=>EscalateSt]	34	1			T58	1		T59	1		T51	1
arcs[TransProgSt=>EscalateSt]	780	1			T12	24		T16	11		T32	17
arcs[PostTransSt=>EscalateSt]	5796	1			T4	136		T10	6		T12	1
arcs[InvalidSt=>EscalateSt]	14690	1			T4	268		T13	6		T15	66

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7925929	1			T1	1419		T2	1665		T3	117
auto[0]	auto[IdleSt]	24878134	1			T1	15610		T2	22947		T3	4590
auto[0]	auto[ClkMuxSt]	38503	1			T1	14		T2	18		T4	704
auto[0]	auto[CntIncrSt]	38212	1			T1	14		T2	18		T4	704
auto[0]	auto[CntProgSt]	1722154	1			T1	28		T2	99		T4	1191
auto[0]	auto[TransCheckSt]	29557	1			T1	14		T2	18		T4	502
auto[0]	auto[TokenHashSt]	49519012	1			T1	4189		T2	1855		T4	38264
auto[0]	auto[FlashRmaSt]	38664	1			T1	14		T2	45		T4	451
auto[0]	auto[TokenCheck0St]	13740	1			T1	14		T2	18		T4	191
auto[0]	auto[TokenCheck1St]	10031	1			T1	14		T2	18		T4	121
auto[0]	auto[TransProgSt]	387372	1			T1	28		T2	88		T4	231
auto[0]	auto[PostTransSt]	14980834	1			T1	2694		T2	4359		T4	360298
auto[0]	auto[ScrapSt]	149509	1			T12	6		T15	9		T16	7
auto[0]	auto[EscalateSt]	5815820	1			T4	71258		T10	371		T12	5956
auto[0]	auto[InvalidSt]	12033129	1			T4	61835		T13	482		T15	89882
auto[1]	auto[ResetSt]	167	1			T12	2		T16	4		T32	4
auto[1]	auto[IdleSt]	103	1			T16	3		T32	2		T51	3
auto[1]	auto[ClkMuxSt]	24	1			T32	1		T51	1		T202	2
auto[1]	auto[CntIncrSt]	32	1			T12	1		T16	2		T58	1
auto[1]	auto[CntProgSt]	632	1			T12	25		T16	13		T32	12
auto[1]	auto[TransCheckSt]	82	1			T16	1		T57	2		T51	4
auto[1]	auto[TokenHashSt]	536	1			T12	16		T16	7		T32	4
auto[1]	auto[FlashRmaSt]	26	1			T12	2		T16	2		T53	1
auto[1]	auto[TokenCheck0St]	34	1			T12	1		T32	1		T59	2
auto[1]	auto[TokenCheck1St]	22	1			T58	1		T59	1		T51	1
auto[1]	auto[TransProgSt]	511	1			T12	11		T16	3		T32	9
auto[1]	auto[PostTransSt]	2917	1			T4	59		T10	4		T12	1
auto[1]	auto[ScrapSt]	49	1			T12	2		T16	1		T57	2
auto[1]	auto[EscalateSt]	1441318	1			T4	19583		T10	392		T12	9813
auto[1]	auto[InvalidSt]	7456	1			T4	141		T13	4		T15	36

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7925928	1			T1	1419		T2	1665		T3	117
auto[0]	auto[IdleSt]	24878125	1			T1	15610		T2	22947		T3	4590
auto[0]	auto[ClkMuxSt]	38495	1			T1	14		T2	18		T4	704
auto[0]	auto[CntIncrSt]	38219	1			T1	14		T2	18		T4	704
auto[0]	auto[CntProgSt]	1722103	1			T1	28		T2	99		T4	1191
auto[0]	auto[TransCheckSt]	29562	1			T1	14		T2	18		T4	502
auto[0]	auto[TokenHashSt]	49519021	1			T1	4189		T2	1855		T4	38264
auto[0]	auto[FlashRmaSt]	38667	1			T1	14		T2	45		T4	451
auto[0]	auto[TokenCheck0St]	13734	1			T1	14		T2	18		T4	191
auto[0]	auto[TokenCheck1St]	10024	1			T1	14		T2	18		T4	121
auto[0]	auto[TransProgSt]	387366	1			T1	28		T2	88		T4	231
auto[0]	auto[PostTransSt]	14980776	1			T1	2694		T2	4359		T4	360280
auto[0]	auto[ScrapSt]	149511	1			T12	7		T15	9		T16	7
auto[0]	auto[EscalateSt]	5821263	1			T4	70863		T10	567		T12	5788
auto[0]	auto[InvalidSt]	12033351	1			T4	61849		T13	484		T15	89888
auto[1]	auto[ResetSt]	168	1			T12	3		T16	4		T32	2
auto[1]	auto[IdleSt]	112	1			T16	4		T32	1		T51	4
auto[1]	auto[ClkMuxSt]	32	1			T32	2		T52	2		T158	2
auto[1]	auto[CntIncrSt]	25	1			T16	1		T32	1		T59	1
auto[1]	auto[CntProgSt]	683	1			T12	29		T16	15		T32	13
auto[1]	auto[TransCheckSt]	77	1			T12	1		T16	1		T32	1
auto[1]	auto[TokenHashSt]	527	1			T12	10		T16	6		T32	5
auto[1]	auto[FlashRmaSt]	23	1			T16	2		T53	1		T203	2
auto[1]	auto[TokenCheck0St]	40	1			T32	1		T57	1		T58	2
auto[1]	auto[TokenCheck1St]	29	1			T58	1		T59	1		T51	1
auto[1]	auto[TransProgSt]	517	1			T12	17		T16	9		T32	14
auto[1]	auto[PostTransSt]	2975	1			T4	77		T10	2		T12	1
auto[1]	auto[ScrapSt]	47	1			T12	1		T16	1		T32	1
auto[1]	auto[EscalateSt]	1435875	1			T4	19978		T10	196		T12	9981
auto[1]	auto[InvalidSt]	7234	1			T4	127		T13	2		T15	30