Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49301 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1711 |
1 |
|
|
T10 |
8 |
|
T9 |
8 |
|
T14 |
28 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50258 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
754 |
1 |
|
|
T34 |
20 |
|
T56 |
17 |
|
T57 |
16 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49239 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1773 |
1 |
|
|
T13 |
5 |
|
T35 |
3 |
|
T14 |
11 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49263 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1749 |
1 |
|
|
T13 |
13 |
|
T35 |
5 |
|
T14 |
9 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49242 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1770 |
1 |
|
|
T8 |
1 |
|
T13 |
7 |
|
T35 |
10 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
46317 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
no_err_inj |
4695 |
1 |
|
|
T6 |
15 |
|
T8 |
9 |
|
T12 |
10 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49290 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1722 |
1 |
|
|
T10 |
6 |
|
T9 |
5 |
|
T14 |
18 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50248 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
764 |
1 |
|
|
T34 |
23 |
|
T56 |
14 |
|
T57 |
18 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36609 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
14403 |
1 |
|
|
T6 |
15 |
|
T8 |
15 |
|
T9 |
61 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49312 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1700 |
1 |
|
|
T8 |
1 |
|
T13 |
2 |
|
T35 |
11 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49305 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1707 |
1 |
|
|
T8 |
1 |
|
T13 |
5 |
|
T35 |
3 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49269 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1743 |
1 |
|
|
T8 |
1 |
|
T13 |
11 |
|
T35 |
8 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49359 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1653 |
1 |
|
|
T10 |
7 |
|
T9 |
4 |
|
T14 |
29 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48784 |
1 |
|
|
T2 |
62 |
|
T10 |
70 |
|
T6 |
15 |
auto[1] |
2228 |
1 |
|
|
T1 |
16 |
|
T3 |
13 |
|
T6 |
2 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50242 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
770 |
1 |
|
|
T34 |
16 |
|
T56 |
6 |
|
T57 |
18 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50252 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
760 |
1 |
|
|
T34 |
15 |
|
T56 |
8 |
|
T57 |
18 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50236 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
776 |
1 |
|
|
T34 |
19 |
|
T56 |
21 |
|
T57 |
22 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48370 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
2642 |
1 |
|
|
T8 |
15 |
|
T15 |
39 |
|
T16 |
13 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47217 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
3795 |
1 |
|
|
T47 |
86 |
|
T48 |
78 |
|
T50 |
71 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49229 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1783 |
1 |
|
|
T13 |
3 |
|
T35 |
5 |
|
T14 |
9 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49264 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1748 |
1 |
|
|
T13 |
6 |
|
T35 |
8 |
|
T14 |
6 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49220 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1792 |
1 |
|
|
T8 |
2 |
|
T13 |
6 |
|
T35 |
5 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49363 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1649 |
1 |
|
|
T10 |
14 |
|
T9 |
6 |
|
T14 |
18 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
45743 |
1 |
|
|
T1 |
16 |
|
T3 |
13 |
|
T10 |
60 |
auto[1] |
5269 |
1 |
|
|
T2 |
62 |
|
T10 |
10 |
|
T9 |
8 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47324 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
3688 |
1 |
|
|
T53 |
81 |
|
T54 |
72 |
|
T55 |
58 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51012 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49387 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1625 |
1 |
|
|
T10 |
9 |
|
T9 |
3 |
|
T14 |
17 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49330 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1682 |
1 |
|
|
T10 |
7 |
|
T9 |
17 |
|
T14 |
16 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49306 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[1] |
1706 |
1 |
|
|
T10 |
9 |
|
T9 |
10 |
|
T14 |
20 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
44960 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
no_err_inj |
3410 |
1 |
|
|
T6 |
15 |
|
T12 |
10 |
|
T17 |
6 |
auto[1] |
err_inj |
1357 |
1 |
|
|
T8 |
6 |
|
T15 |
22 |
|
T16 |
8 |
auto[1] |
no_err_inj |
1285 |
1 |
|
|
T8 |
9 |
|
T15 |
17 |
|
T16 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46780 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
1590 |
1 |
|
|
T13 |
6 |
|
T35 |
8 |
|
T14 |
6 |
auto[1] |
auto[0] |
2484 |
1 |
|
|
T8 |
15 |
|
T15 |
36 |
|
T16 |
12 |
auto[1] |
auto[1] |
158 |
1 |
|
|
T15 |
3 |
|
T16 |
1 |
|
T31 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46811 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
1559 |
1 |
|
|
T13 |
5 |
|
T35 |
3 |
|
T14 |
11 |
auto[1] |
auto[0] |
2494 |
1 |
|
|
T8 |
14 |
|
T15 |
35 |
|
T16 |
12 |
auto[1] |
auto[1] |
148 |
1 |
|
|
T8 |
1 |
|
T15 |
4 |
|
T16 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46726 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
1644 |
1 |
|
|
T13 |
6 |
|
T35 |
5 |
|
T14 |
13 |
auto[1] |
auto[0] |
2494 |
1 |
|
|
T8 |
13 |
|
T15 |
37 |
|
T16 |
11 |
auto[1] |
auto[1] |
148 |
1 |
|
|
T8 |
2 |
|
T15 |
2 |
|
T16 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46786 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
1584 |
1 |
|
|
T13 |
13 |
|
T35 |
5 |
|
T14 |
9 |
auto[1] |
auto[0] |
2477 |
1 |
|
|
T8 |
15 |
|
T15 |
38 |
|
T16 |
12 |
auto[1] |
auto[1] |
165 |
1 |
|
|
T15 |
1 |
|
T16 |
1 |
|
T31 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46753 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
1617 |
1 |
|
|
T13 |
7 |
|
T35 |
10 |
|
T14 |
9 |
auto[1] |
auto[0] |
2489 |
1 |
|
|
T8 |
14 |
|
T15 |
38 |
|
T16 |
12 |
auto[1] |
auto[1] |
153 |
1 |
|
|
T8 |
1 |
|
T15 |
1 |
|
T16 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46748 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
1622 |
1 |
|
|
T13 |
5 |
|
T35 |
3 |
|
T14 |
11 |
auto[1] |
auto[0] |
2491 |
1 |
|
|
T8 |
15 |
|
T15 |
35 |
|
T16 |
13 |
auto[1] |
auto[1] |
151 |
1 |
|
|
T15 |
4 |
|
T81 |
2 |
|
T30 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35640 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
969 |
1 |
|
|
T10 |
8 |
|
T14 |
11 |
|
T33 |
8 |
auto[1] |
auto[0] |
13661 |
1 |
|
|
T6 |
15 |
|
T8 |
15 |
|
T9 |
53 |
auto[1] |
auto[1] |
742 |
1 |
|
|
T9 |
8 |
|
T14 |
17 |
|
T15 |
12 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35570 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
1039 |
1 |
|
|
T10 |
6 |
|
T14 |
5 |
|
T33 |
17 |
auto[1] |
auto[0] |
13720 |
1 |
|
|
T6 |
15 |
|
T8 |
15 |
|
T9 |
56 |
auto[1] |
auto[1] |
683 |
1 |
|
|
T9 |
5 |
|
T14 |
13 |
|
T15 |
7 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35258 |
1 |
|
|
T2 |
62 |
|
T10 |
70 |
|
T13 |
58 |
auto[0] |
auto[1] |
1351 |
1 |
|
|
T1 |
16 |
|
T3 |
13 |
|
T6 |
2 |
auto[1] |
auto[0] |
13526 |
1 |
|
|
T6 |
15 |
|
T8 |
15 |
|
T9 |
61 |
auto[1] |
auto[1] |
877 |
1 |
|
|
T14 |
9 |
|
T16 |
19 |
|
T30 |
4 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35621 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
988 |
1 |
|
|
T10 |
7 |
|
T14 |
13 |
|
T33 |
9 |
auto[1] |
auto[0] |
13738 |
1 |
|
|
T6 |
15 |
|
T8 |
15 |
|
T9 |
57 |
auto[1] |
auto[1] |
665 |
1 |
|
|
T9 |
4 |
|
T14 |
16 |
|
T15 |
14 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32029 |
1 |
|
|
T1 |
16 |
|
T3 |
13 |
|
T10 |
60 |
auto[0] |
auto[1] |
4580 |
1 |
|
|
T2 |
62 |
|
T10 |
10 |
|
T14 |
6 |
auto[1] |
auto[0] |
13714 |
1 |
|
|
T6 |
15 |
|
T8 |
15 |
|
T9 |
53 |
auto[1] |
auto[1] |
689 |
1 |
|
|
T9 |
8 |
|
T14 |
8 |
|
T15 |
10 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35479 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
1130 |
1 |
|
|
T13 |
6 |
|
T35 |
8 |
|
T15 |
3 |
auto[1] |
auto[0] |
13785 |
1 |
|
|
T6 |
15 |
|
T8 |
15 |
|
T9 |
61 |
auto[1] |
auto[1] |
618 |
1 |
|
|
T14 |
6 |
|
T16 |
37 |
|
T31 |
2 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35522 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
1087 |
1 |
|
|
T13 |
3 |
|
T35 |
5 |
|
T15 |
1 |
auto[1] |
auto[0] |
13707 |
1 |
|
|
T6 |
15 |
|
T8 |
15 |
|
T9 |
61 |
auto[1] |
auto[1] |
696 |
1 |
|
|
T14 |
9 |
|
T16 |
38 |
|
T31 |
2 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35539 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
1070 |
1 |
|
|
T13 |
5 |
|
T35 |
3 |
|
T15 |
4 |
auto[1] |
auto[0] |
13766 |
1 |
|
|
T6 |
15 |
|
T8 |
14 |
|
T9 |
61 |
auto[1] |
auto[1] |
637 |
1 |
|
|
T8 |
1 |
|
T14 |
11 |
|
T16 |
26 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35544 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
1065 |
1 |
|
|
T13 |
2 |
|
T35 |
11 |
|
T15 |
3 |
auto[1] |
auto[0] |
13768 |
1 |
|
|
T6 |
15 |
|
T8 |
14 |
|
T9 |
61 |
auto[1] |
auto[1] |
635 |
1 |
|
|
T8 |
1 |
|
T14 |
6 |
|
T16 |
30 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35541 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
1068 |
1 |
|
|
T13 |
13 |
|
T35 |
5 |
|
T15 |
1 |
auto[1] |
auto[0] |
13722 |
1 |
|
|
T6 |
15 |
|
T8 |
15 |
|
T9 |
61 |
auto[1] |
auto[1] |
681 |
1 |
|
|
T14 |
9 |
|
T16 |
33 |
|
T31 |
1 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35552 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
1057 |
1 |
|
|
T13 |
5 |
|
T35 |
3 |
|
T15 |
4 |
auto[1] |
auto[0] |
13687 |
1 |
|
|
T6 |
15 |
|
T8 |
15 |
|
T9 |
61 |
auto[1] |
auto[1] |
716 |
1 |
|
|
T14 |
11 |
|
T16 |
38 |
|
T81 |
2 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35613 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
996 |
1 |
|
|
T10 |
9 |
|
T14 |
7 |
|
T33 |
9 |
auto[1] |
auto[0] |
13693 |
1 |
|
|
T6 |
15 |
|
T8 |
15 |
|
T9 |
51 |
auto[1] |
auto[1] |
710 |
1 |
|
|
T9 |
10 |
|
T14 |
13 |
|
T15 |
19 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35608 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
1001 |
1 |
|
|
T10 |
7 |
|
T14 |
7 |
|
T33 |
22 |
auto[1] |
auto[0] |
13722 |
1 |
|
|
T6 |
15 |
|
T8 |
15 |
|
T9 |
44 |
auto[1] |
auto[1] |
681 |
1 |
|
|
T9 |
17 |
|
T14 |
9 |
|
T15 |
7 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35105 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
13 |
auto[0] |
auto[1] |
1504 |
1 |
|
|
T15 |
39 |
|
T37 |
62 |
|
T227 |
10 |
auto[1] |
auto[0] |
13265 |
1 |
|
|
T6 |
15 |
|
T9 |
61 |
|
T12 |
10 |
auto[1] |
auto[1] |
1138 |
1 |
|
|
T8 |
15 |
|
T16 |
13 |
|
T31 |
26 |