Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99494870

1

T1

7608

T2

31217

T3

6772

auto[1]

1339205

1

T1

594

T3

594

T10

594

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99506538

1

T1

7212

T2

31217

T3

6673

auto[1]

1327537

1

T1

990

T3

693

T10

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6953670	1			T1	1842		T2	5927		T3	1895
auto[IdleSt]	21432721	1			T1	2661		T2	7134		T3	2497
auto[ClkMuxSt]	34166	1			T1	16		T2	62		T3	13
auto[CntIncrSt]	33915	1			T1	16		T2	62		T3	13
auto[CntProgSt]	1475559	1			T1	32		T2	3259		T3	26
auto[TransCheckSt]	26463	1			T2	62		T10	55		T6	15
auto[TokenHashSt]	40196075	1			T2	3381		T10	919		T6	168538
auto[FlashRmaSt]	34404	1			T10	67		T6	32		T8	29
auto[TokenCheck0St]	12361	1			T10	13		T6	15		T8	9
auto[TokenCheck1St]	9132	1			T10	8		T6	15		T8	9
auto[TransProgSt]	395860	1			T10	289		T6	316		T8	188
auto[PostTransSt]	12546520	1			T1	1373		T2	11330		T3	1081
auto[ScrapSt]	187620	1			T14	3521		T15	6180		T16	6315
auto[EscalateSt]	6552722	1			T1	2262		T3	1841		T10	1152
auto[InvalidSt]	10941129	1			T8	4210		T13	5668		T35	3421

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1758	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10941129	1			T8	4210		T13	5668		T35	3421
EscalateSt	6552722	1			T1	2262		T3	1841		T10	1152
ScrapSt	187620	1			T14	3521		T15	6180		T16	6315
PostTransSt	12546520	1			T1	1373		T2	11330		T3	1081
TransProgSt	395860	1			T10	289		T6	316		T8	188
TokenCheck1St	9132	1			T10	8		T6	15		T8	9
TokenCheck0St	12361	1			T10	13		T6	15		T8	9
FlashRmaSt	34404	1			T10	67		T6	32		T8	29
TokenHashSt	40196075	1			T2	3381		T10	919		T6	168538
TransCheckSt	26463	1			T2	62		T10	55		T6	15
CntProgSt	1475559	1			T1	32		T2	3259		T3	26
CntIncrSt	33915	1			T1	16		T2	62		T3	13
ClkMuxSt	34166	1			T1	16		T2	62		T3	13
IdleSt	21432721	1			T1	2661		T2	7134		T3	2497
ResetSt	6953670	1			T1	1842		T2	5927		T3	1895
arcs[ResetSt=>IdleSt]	51246	1			T1	17		T2	63		T3	14
arcs[IdleSt=>ScrapSt]	259	1			T14	4		T15	2		T16	3
arcs[IdleSt=>ClkMuxSt]	33944	1			T1	16		T2	62		T3	13
arcs[ClkMuxSt=>CntIncrSt]	33915	1			T1	16		T2	62		T3	13
arcs[CntIncrSt=>PostTransSt]	1683	1			T10	7		T9	17		T14	16
arcs[CntIncrSt=>CntProgSt]	32155	1			T1	16		T2	62		T3	13
arcs[CntProgSt=>PostTransSt]	4664	1			T1	16		T3	13		T10	8
arcs[CntProgSt=>TransCheckSt]	26463	1			T2	62		T10	55		T6	15
arcs[TransCheckSt=>PostTransSt]	3585	1			T10	9		T9	10		T14	20
arcs[TransCheckSt=>TokenHashSt]	22758	1			T2	62		T10	46		T6	15
arcs[TokenHashSt=>PostTransSt]	9485	1			T2	62		T10	33		T9	17
arcs[TokenHashSt=>FlashRmaSt]	12415	1			T10	13		T6	15		T8	9
arcs[FlashRmaSt=>TokenCheck0St]	12361	1			T10	13		T6	15		T8	9
arcs[TokenCheck0St=>PostTransSt]	3169	1			T10	5		T9	5		T14	16
arcs[TokenCheck0St=>TokenCheck1St]	9132	1			T10	8		T6	15		T8	9
arcs[TokenCheck1St=>PostTransSt]	655	1			T10	1		T14	2		T15	2
arcs[TransProgSt=>PostTransSt]	7701	1			T10	7		T6	15		T8	9
arcs[IdleSt=>EscalateSt]	132	1			T48	2		T50	5		T49	2
arcs[ClkMuxSt=>EscalateSt]	29	1			T44	5		T45	1		T46	1
arcs[CntIncrSt=>EscalateSt]	77	1			T47	3		T48	5		T49	4
arcs[CntProgSt=>EscalateSt]	1028	1			T47	31		T48	25		T50	29
arcs[TransCheckSt=>EscalateSt]	120	1			T47	1		T50	1		T49	9
arcs[TokenHashSt=>EscalateSt]	858	1			T47	12		T48	9		T50	5
arcs[FlashRmaSt=>EscalateSt]	54	1			T47	3		T48	1		T50	2
arcs[TokenCheck0St=>EscalateSt]	60	1			T48	2		T44	2		T45	1
arcs[TokenCheck1St=>EscalateSt]	29	1			T48	1		T49	2		T44	1
arcs[TransProgSt=>EscalateSt]	747	1			T47	27		T48	23		T50	18
arcs[PostTransSt=>EscalateSt]	5031	1			T1	16		T3	13		T10	8
arcs[InvalidSt=>EscalateSt]	13002	1			T8	3		T13	41		T35	45

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6953504	1			T1	1842		T2	5927		T3	1895
auto[0]	auto[IdleSt]	21432638	1			T1	2661		T2	7134		T3	2497
auto[0]	auto[ClkMuxSt]	34147	1			T1	16		T2	62		T3	13
auto[0]	auto[CntIncrSt]	33860	1			T1	16		T2	62		T3	13
auto[0]	auto[CntProgSt]	1474873	1			T1	32		T2	3259		T3	26
auto[0]	auto[TransCheckSt]	26382	1			T2	62		T10	55		T6	15
auto[0]	auto[TokenHashSt]	40195502	1			T2	3381		T10	919		T6	168538
auto[0]	auto[FlashRmaSt]	34373	1			T10	67		T6	32		T8	29
auto[0]	auto[TokenCheck0St]	12319	1			T10	13		T6	15		T8	9
auto[0]	auto[TokenCheck1St]	9114	1			T10	8		T6	15		T8	9
auto[0]	auto[TransProgSt]	395368	1			T10	289		T6	316		T8	188
auto[0]	auto[PostTransSt]	12543939	1			T1	1367		T2	11330		T3	1075
auto[0]	auto[ScrapSt]	187570	1			T14	3521		T15	6180		T16	6315
auto[0]	auto[EscalateSt]	5224931	1			T1	1674		T3	1253		T10	564
auto[0]	auto[InvalidSt]	10934592	1			T8	4209		T13	5646		T35	3401
auto[1]	auto[ResetSt]	166	1			T47	4		T48	5		T50	7
auto[1]	auto[IdleSt]	83	1			T48	2		T50	4		T49	1
auto[1]	auto[ClkMuxSt]	19	1			T44	3		T45	1		T46	1
auto[1]	auto[CntIncrSt]	55	1			T47	3		T48	3		T49	2
auto[1]	auto[CntProgSt]	686	1			T47	21		T48	16		T50	19
auto[1]	auto[TransCheckSt]	81	1			T47	1		T50	1		T49	6
auto[1]	auto[TokenHashSt]	573	1			T47	8		T48	4		T50	1
auto[1]	auto[FlashRmaSt]	31	1			T47	1		T48	1		T45	1
auto[1]	auto[TokenCheck0St]	42	1			T48	1		T44	2		T45	1
auto[1]	auto[TokenCheck1St]	18	1			T48	1		T49	2		T223	2
auto[1]	auto[TransProgSt]	492	1			T47	17		T48	19		T50	11
auto[1]	auto[PostTransSt]	2581	1			T1	6		T3	6		T10	6
auto[1]	auto[ScrapSt]	50	1			T48	2		T50	1		T49	1
auto[1]	auto[EscalateSt]	1327791	1			T1	588		T3	588		T10	588
auto[1]	auto[InvalidSt]	6537	1			T8	1		T13	22		T35	20

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6953488	1			T1	1842		T2	5927		T3	1895
auto[0]	auto[IdleSt]	21432629	1			T1	2661		T2	7134		T3	2497
auto[0]	auto[ClkMuxSt]	34148	1			T1	16		T2	62		T3	13
auto[0]	auto[CntIncrSt]	33871	1			T1	16		T2	62		T3	13
auto[0]	auto[CntProgSt]	1474887	1			T1	32		T2	3259		T3	26
auto[0]	auto[TransCheckSt]	26384	1			T2	62		T10	55		T6	15
auto[0]	auto[TokenHashSt]	40195515	1			T2	3381		T10	919		T6	168538
auto[0]	auto[FlashRmaSt]	34371	1			T10	67		T6	32		T8	29
auto[0]	auto[TokenCheck0St]	12325	1			T10	13		T6	15		T8	9
auto[0]	auto[TokenCheck1St]	9109	1			T10	8		T6	15		T8	9
auto[0]	auto[TransProgSt]	395372	1			T10	289		T6	316		T8	188
auto[0]	auto[PostTransSt]	12543952	1			T1	1363		T2	11330		T3	1074
auto[0]	auto[ScrapSt]	187570	1			T14	3521		T15	6180		T16	6315
auto[0]	auto[EscalateSt]	5236495	1			T1	1282		T3	1155		T10	956
auto[0]	auto[InvalidSt]	10934664	1			T8	4208		T13	5649		T35	3396
auto[1]	auto[ResetSt]	182	1			T47	4		T48	4		T50	6
auto[1]	auto[IdleSt]	92	1			T48	1		T50	2		T49	2
auto[1]	auto[ClkMuxSt]	18	1			T44	4		T224	1		T225	1
auto[1]	auto[CntIncrSt]	44	1			T47	1		T48	3		T49	3
auto[1]	auto[CntProgSt]	672	1			T47	19		T48	16		T50	20
auto[1]	auto[TransCheckSt]	79	1			T47	1		T50	1		T49	5
auto[1]	auto[TokenHashSt]	560	1			T47	8		T48	8		T50	4
auto[1]	auto[FlashRmaSt]	33	1			T47	2		T50	2		T44	1
auto[1]	auto[TokenCheck0St]	36	1			T48	2		T44	1		T226	1
auto[1]	auto[TokenCheck1St]	23	1			T48	1		T49	1		T44	1
auto[1]	auto[TransProgSt]	488	1			T47	23		T48	13		T50	11
auto[1]	auto[PostTransSt]	2568	1			T1	10		T3	7		T10	2
auto[1]	auto[ScrapSt]	50	1			T48	3		T49	1		T44	2
auto[1]	auto[EscalateSt]	1316227	1			T1	980		T3	686		T10	196
auto[1]	auto[InvalidSt]	6465	1			T8	2		T13	19		T35	25