Summary for Variable clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39697 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
298 | 
| auto[1] | 
1248 | 
1 | 
 | 
 | 
T4 | 
14 | 
 | 
T10 | 
7 | 
 | 
T11 | 
11 | 
Summary for Variable clk_byp_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
40211 | 
1 | 
 | 
 | 
T1 | 
43 | 
 | 
T2 | 
14 | 
 | 
T4 | 
312 | 
| auto[1] | 
734 | 
1 | 
 | 
 | 
T1 | 
10 | 
 | 
T9 | 
8 | 
 | 
T33 | 
22 | 
Summary for Variable count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39666 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
289 | 
| auto[1] | 
1279 | 
1 | 
 | 
 | 
T4 | 
23 | 
 | 
T7 | 
9 | 
 | 
T15 | 
10 | 
Summary for Variable count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39698 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
291 | 
| auto[1] | 
1247 | 
1 | 
 | 
 | 
T4 | 
21 | 
 | 
T7 | 
9 | 
 | 
T15 | 
7 | 
Summary for Variable count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39702 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
13 | 
 | 
T4 | 
289 | 
| auto[1] | 
1243 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T4 | 
23 | 
 | 
T7 | 
11 | 
Summary for Variable err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
2 | 
0 | 
2 | 
100.00 | 
User Defined Bins for err_inj_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| err_inj | 
37549 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
6 | 
 | 
T4 | 
287 | 
| no_err_inj | 
3396 | 
1 | 
 | 
 | 
T2 | 
8 | 
 | 
T4 | 
25 | 
 | 
T8 | 
10 | 
Summary for Variable flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39684 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
299 | 
| auto[1] | 
1261 | 
1 | 
 | 
 | 
T4 | 
13 | 
 | 
T10 | 
7 | 
 | 
T11 | 
4 | 
Summary for Variable flash_rma_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
40211 | 
1 | 
 | 
 | 
T1 | 
44 | 
 | 
T2 | 
14 | 
 | 
T4 | 
312 | 
| auto[1] | 
734 | 
1 | 
 | 
 | 
T1 | 
9 | 
 | 
T9 | 
11 | 
 | 
T33 | 
27 | 
Summary for Variable jtag_csr_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for jtag_csr_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
31342 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
162 | 
 | 
T7 | 
81 | 
| auto[1] | 
9603 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T4 | 
150 | 
 | 
T14 | 
12 | 
Summary for Variable kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39729 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
293 | 
| auto[1] | 
1216 | 
1 | 
 | 
 | 
T4 | 
19 | 
 | 
T7 | 
7 | 
 | 
T15 | 
8 | 
Summary for Variable lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39731 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
13 | 
 | 
T4 | 
293 | 
| auto[1] | 
1214 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T4 | 
19 | 
 | 
T7 | 
9 | 
Summary for Variable otp_lc_data_i_valid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39678 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
296 | 
| auto[1] | 
1267 | 
1 | 
 | 
 | 
T4 | 
16 | 
 | 
T7 | 
13 | 
 | 
T15 | 
8 | 
Summary for Variable otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_partition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39722 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
297 | 
| auto[1] | 
1223 | 
1 | 
 | 
 | 
T4 | 
15 | 
 | 
T10 | 
6 | 
 | 
T11 | 
7 | 
Summary for Variable otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_prog_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39528 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
312 | 
| auto[1] | 
1417 | 
1 | 
 | 
 | 
T13 | 
20 | 
 | 
T15 | 
26 | 
 | 
T56 | 
16 | 
Summary for Variable otp_rma_token_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
40191 | 
1 | 
 | 
 | 
T1 | 
40 | 
 | 
T2 | 
14 | 
 | 
T4 | 
312 | 
| auto[1] | 
754 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T9 | 
11 | 
 | 
T33 | 
10 | 
Summary for Variable otp_secrets_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
40210 | 
1 | 
 | 
 | 
T1 | 
46 | 
 | 
T2 | 
14 | 
 | 
T4 | 
312 | 
| auto[1] | 
735 | 
1 | 
 | 
 | 
T1 | 
7 | 
 | 
T9 | 
8 | 
 | 
T33 | 
18 | 
Summary for Variable otp_test_tokens_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
40191 | 
1 | 
 | 
 | 
T1 | 
39 | 
 | 
T2 | 
14 | 
 | 
T4 | 
312 | 
| auto[1] | 
754 | 
1 | 
 | 
 | 
T1 | 
14 | 
 | 
T9 | 
12 | 
 | 
T33 | 
21 | 
Summary for Variable post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for post_trans_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39017 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
312 | 
 | 
T7 | 
81 | 
| auto[1] | 
1928 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T14 | 
12 | 
 | 
T15 | 
23 | 
Summary for Variable security_escalation_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for security_escalation_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
37189 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
312 | 
| auto[1] | 
3756 | 
1 | 
 | 
 | 
T31 | 
68 | 
 | 
T35 | 
85 | 
 | 
T47 | 
94 | 
Summary for Variable state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39703 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
12 | 
 | 
T4 | 
290 | 
| auto[1] | 
1242 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T4 | 
22 | 
 | 
T7 | 
5 | 
Summary for Variable state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39716 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
13 | 
 | 
T4 | 
298 | 
| auto[1] | 
1229 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T4 | 
14 | 
 | 
T7 | 
8 | 
Summary for Variable state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39719 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
13 | 
 | 
T4 | 
296 | 
| auto[1] | 
1226 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T4 | 
16 | 
 | 
T7 | 
10 | 
Summary for Variable token_invalid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_invalid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39742 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
298 | 
| auto[1] | 
1203 | 
1 | 
 | 
 | 
T4 | 
14 | 
 | 
T10 | 
12 | 
 | 
T11 | 
8 | 
Summary for Variable token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mismatch_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
35897 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
295 | 
| auto[1] | 
5048 | 
1 | 
 | 
 | 
T4 | 
17 | 
 | 
T10 | 
8 | 
 | 
T11 | 
9 | 
Summary for Variable token_mux_ctrl_redun_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
37153 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
312 | 
| auto[1] | 
3792 | 
1 | 
 | 
 | 
T32 | 
87 | 
 | 
T57 | 
99 | 
 | 
T58 | 
66 | 
Summary for Variable token_mux_digest_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
1 | 
1 | 
50.00  | 
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | 
0 | 
1 | 
1 | 
 | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
40945 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
312 | 
Summary for Variable token_response_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_response_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39690 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
298 | 
| auto[1] | 
1255 | 
1 | 
 | 
 | 
T4 | 
14 | 
 | 
T10 | 
6 | 
 | 
T11 | 
13 | 
Summary for Variable transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39699 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
302 | 
| auto[1] | 
1246 | 
1 | 
 | 
 | 
T4 | 
10 | 
 | 
T10 | 
4 | 
 | 
T11 | 
7 | 
Summary for Variable transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39719 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T2 | 
14 | 
 | 
T4 | 
295 | 
| auto[1] | 
1226 | 
1 | 
 | 
 | 
T4 | 
17 | 
 | 
T10 | 
6 | 
 | 
T11 | 
1 | 
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
| post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
err_inj | 
36577 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
287 | 
 | 
T7 | 
81 | 
| auto[0] | 
no_err_inj | 
2440 | 
1 | 
 | 
 | 
T4 | 
25 | 
 | 
T8 | 
10 | 
 | 
T15 | 
37 | 
| auto[1] | 
err_inj | 
972 | 
1 | 
 | 
 | 
T2 | 
6 | 
 | 
T14 | 
6 | 
 | 
T15 | 
11 | 
| auto[1] | 
no_err_inj | 
956 | 
1 | 
 | 
 | 
T2 | 
8 | 
 | 
T14 | 
6 | 
 | 
T15 | 
12 | 
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
| post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37902 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
298 | 
 | 
T7 | 
73 | 
| auto[0] | 
auto[1] | 
1115 | 
1 | 
 | 
 | 
T4 | 
14 | 
 | 
T7 | 
8 | 
 | 
T15 | 
4 | 
| auto[1] | 
auto[0] | 
1814 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T14 | 
12 | 
 | 
T15 | 
23 | 
| auto[1] | 
auto[1] | 
114 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T80 | 
2 | 
 | 
T101 | 
1 | 
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
| post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37903 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
293 | 
 | 
T7 | 
72 | 
| auto[0] | 
auto[1] | 
1114 | 
1 | 
 | 
 | 
T4 | 
19 | 
 | 
T7 | 
9 | 
 | 
T15 | 
4 | 
| auto[1] | 
auto[0] | 
1828 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T14 | 
11 | 
 | 
T15 | 
22 | 
| auto[1] | 
auto[1] | 
100 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T14 | 
1 | 
 | 
T15 | 
1 | 
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
| post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37881 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
296 | 
 | 
T7 | 
71 | 
| auto[0] | 
auto[1] | 
1136 | 
1 | 
 | 
 | 
T4 | 
16 | 
 | 
T7 | 
10 | 
 | 
T15 | 
6 | 
| auto[1] | 
auto[0] | 
1838 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T14 | 
12 | 
 | 
T15 | 
18 | 
| auto[1] | 
auto[1] | 
90 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T15 | 
5 | 
 | 
T101 | 
1 | 
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
| post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37882 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
291 | 
 | 
T7 | 
72 | 
| auto[0] | 
auto[1] | 
1135 | 
1 | 
 | 
 | 
T4 | 
21 | 
 | 
T7 | 
9 | 
 | 
T15 | 
5 | 
| auto[1] | 
auto[0] | 
1816 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T14 | 
12 | 
 | 
T15 | 
21 | 
| auto[1] | 
auto[1] | 
112 | 
1 | 
 | 
 | 
T15 | 
2 | 
 | 
T217 | 
1 | 
 | 
T218 | 
3 | 
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
| post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37866 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
289 | 
 | 
T7 | 
70 | 
| auto[0] | 
auto[1] | 
1151 | 
1 | 
 | 
 | 
T4 | 
23 | 
 | 
T7 | 
11 | 
 | 
T15 | 
9 | 
| auto[1] | 
auto[0] | 
1836 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T14 | 
11 | 
 | 
T15 | 
23 | 
| auto[1] | 
auto[1] | 
92 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T14 | 
1 | 
 | 
T218 | 
1 | 
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
| post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37863 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
289 | 
 | 
T7 | 
72 | 
| auto[0] | 
auto[1] | 
1154 | 
1 | 
 | 
 | 
T4 | 
23 | 
 | 
T7 | 
9 | 
 | 
T15 | 
9 | 
| auto[1] | 
auto[0] | 
1803 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T14 | 
12 | 
 | 
T15 | 
22 | 
| auto[1] | 
auto[1] | 
125 | 
1 | 
 | 
 | 
T15 | 
1 | 
 | 
T101 | 
2 | 
 | 
T218 | 
1 | 
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
| jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
30554 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
157 | 
 | 
T7 | 
81 | 
| auto[0] | 
auto[1] | 
788 | 
1 | 
 | 
 | 
T4 | 
5 | 
 | 
T10 | 
7 | 
 | 
T11 | 
11 | 
| auto[1] | 
auto[0] | 
9143 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T4 | 
141 | 
 | 
T14 | 
12 | 
| auto[1] | 
auto[1] | 
460 | 
1 | 
 | 
 | 
T4 | 
9 | 
 | 
T38 | 
25 | 
 | 
T81 | 
8 | 
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
| jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
30514 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
158 | 
 | 
T7 | 
81 | 
| auto[0] | 
auto[1] | 
828 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T10 | 
7 | 
 | 
T11 | 
4 | 
| auto[1] | 
auto[0] | 
9170 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T4 | 
141 | 
 | 
T14 | 
12 | 
| auto[1] | 
auto[1] | 
433 | 
1 | 
 | 
 | 
T4 | 
9 | 
 | 
T38 | 
22 | 
 | 
T81 | 
7 | 
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
| jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
30519 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
162 | 
 | 
T7 | 
81 | 
| auto[0] | 
auto[1] | 
823 | 
1 | 
 | 
 | 
T13 | 
20 | 
 | 
T15 | 
10 | 
 | 
T56 | 
16 | 
| auto[1] | 
auto[0] | 
9009 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T4 | 
150 | 
 | 
T14 | 
12 | 
| auto[1] | 
auto[1] | 
594 | 
1 | 
 | 
 | 
T15 | 
16 | 
 | 
T17 | 
13 | 
 | 
T18 | 
6 | 
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
| jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
30558 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
154 | 
 | 
T7 | 
81 | 
| auto[0] | 
auto[1] | 
784 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T10 | 
6 | 
 | 
T11 | 
7 | 
| auto[1] | 
auto[0] | 
9164 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T4 | 
143 | 
 | 
T14 | 
12 | 
| auto[1] | 
auto[1] | 
439 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T38 | 
15 | 
 | 
T81 | 
6 | 
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
| jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
26764 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
152 | 
 | 
T7 | 
81 | 
| auto[0] | 
auto[1] | 
4578 | 
1 | 
 | 
 | 
T4 | 
10 | 
 | 
T10 | 
8 | 
 | 
T11 | 
9 | 
| auto[1] | 
auto[0] | 
9133 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T4 | 
143 | 
 | 
T14 | 
12 | 
| auto[1] | 
auto[1] | 
470 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T38 | 
22 | 
 | 
T81 | 
8 | 
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
| jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
30528 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
155 | 
 | 
T7 | 
73 | 
| auto[0] | 
auto[1] | 
814 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T7 | 
8 | 
 | 
T80 | 
2 | 
| auto[1] | 
auto[0] | 
9188 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T4 | 
143 | 
 | 
T14 | 
12 | 
| auto[1] | 
auto[1] | 
415 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T4 | 
7 | 
 | 
T15 | 
4 | 
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
| jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
30560 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
154 | 
 | 
T7 | 
76 | 
| auto[0] | 
auto[1] | 
782 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T7 | 
5 | 
 | 
T15 | 
1 | 
| auto[1] | 
auto[0] | 
9143 | 
1 | 
 | 
 | 
T2 | 
12 | 
 | 
T4 | 
136 | 
 | 
T14 | 
8 | 
| auto[1] | 
auto[1] | 
460 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T4 | 
14 | 
 | 
T14 | 
4 | 
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
30556 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
149 | 
 | 
T7 | 
72 | 
| auto[0] | 
auto[1] | 
786 | 
1 | 
 | 
 | 
T4 | 
13 | 
 | 
T7 | 
9 | 
 | 
T15 | 
1 | 
| auto[1] | 
auto[0] | 
9175 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T4 | 
144 | 
 | 
T14 | 
11 | 
| auto[1] | 
auto[1] | 
428 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T4 | 
6 | 
 | 
T14 | 
1 | 
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
30592 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
150 | 
 | 
T7 | 
74 | 
| auto[0] | 
auto[1] | 
750 | 
1 | 
 | 
 | 
T4 | 
12 | 
 | 
T7 | 
7 | 
 | 
T80 | 
1 | 
| auto[1] | 
auto[0] | 
9137 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T4 | 
143 | 
 | 
T14 | 
12 | 
| auto[1] | 
auto[1] | 
466 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T15 | 
8 | 
 | 
T16 | 
12 | 
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
| jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
30552 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
151 | 
 | 
T7 | 
72 | 
| auto[0] | 
auto[1] | 
790 | 
1 | 
 | 
 | 
T4 | 
11 | 
 | 
T7 | 
9 | 
 | 
T15 | 
1 | 
| auto[1] | 
auto[0] | 
9146 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T4 | 
140 | 
 | 
T14 | 
12 | 
| auto[1] | 
auto[1] | 
457 | 
1 | 
 | 
 | 
T4 | 
10 | 
 | 
T15 | 
6 | 
 | 
T16 | 
5 | 
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
| jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
30500 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
151 | 
 | 
T7 | 
72 | 
| auto[0] | 
auto[1] | 
842 | 
1 | 
 | 
 | 
T4 | 
11 | 
 | 
T7 | 
9 | 
 | 
T15 | 
1 | 
| auto[1] | 
auto[0] | 
9166 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T4 | 
138 | 
 | 
T14 | 
12 | 
| auto[1] | 
auto[1] | 
437 | 
1 | 
 | 
 | 
T4 | 
12 | 
 | 
T15 | 
9 | 
 | 
T16 | 
8 | 
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
| jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
30582 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
155 | 
 | 
T7 | 
81 | 
| auto[0] | 
auto[1] | 
760 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T10 | 
6 | 
 | 
T11 | 
1 | 
| auto[1] | 
auto[0] | 
9137 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T4 | 
140 | 
 | 
T14 | 
12 | 
| auto[1] | 
auto[1] | 
466 | 
1 | 
 | 
 | 
T4 | 
10 | 
 | 
T38 | 
16 | 
 | 
T81 | 
10 | 
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
| jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
30588 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
159 | 
 | 
T7 | 
81 | 
| auto[0] | 
auto[1] | 
754 | 
1 | 
 | 
 | 
T4 | 
3 | 
 | 
T10 | 
4 | 
 | 
T11 | 
7 | 
| auto[1] | 
auto[0] | 
9111 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T4 | 
143 | 
 | 
T14 | 
12 | 
| auto[1] | 
auto[1] | 
492 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T38 | 
23 | 
 | 
T81 | 
6 | 
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
| jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
30156 | 
1 | 
 | 
 | 
T1 | 
53 | 
 | 
T4 | 
162 | 
 | 
T7 | 
81 | 
| auto[0] | 
auto[1] | 
1186 | 
1 | 
 | 
 | 
T15 | 
11 | 
 | 
T80 | 
11 | 
 | 
T101 | 
14 | 
| auto[1] | 
auto[0] | 
8861 | 
1 | 
 | 
 | 
T4 | 
150 | 
 | 
T15 | 
74 | 
 | 
T16 | 
69 | 
| auto[1] | 
auto[1] | 
742 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T14 | 
12 | 
 | 
T15 | 
12 |