Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59641157

1

T1

21439

T2

74841

T3

27637

auto[1]

1098766

1

T1

1089

T2

196

T4

8481

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59651026

1

T1

21934

T2

74743

T3

27637

auto[1]

1088897

1

T1

594

T2

294

T4

6794

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5343342	1			T1	4814		T2	1273		T3	106
auto[IdleSt]	15560404	1			T1	5606		T2	20897		T3	27531
auto[ClkMuxSt]	28738	1			T1	46		T2	8		T4	146
auto[CntIncrSt]	28519	1			T1	46		T2	8		T4	139
auto[CntProgSt]	1336982	1			T1	82		T2	247		T4	4996
auto[TransCheckSt]	22829	1			T1	36		T2	8		T4	115
auto[TokenHashSt]	17730486	1			T1	763		T2	86		T4	406452
auto[FlashRmaSt]	28400	1			T1	39		T2	8		T4	132
auto[TokenCheck0St]	10266	1			T1	27		T2	8		T4	53
auto[TokenCheck1St]	7490	1			T1	18		T2	8		T4	43
auto[TransProgSt]	344462	1			T1	36		T2	200		T4	1685
auto[PostTransSt]	8616792	1			T1	7356		T2	27744		T4	58223
auto[ScrapSt]	154182	1			T15	61		T31	4		T35	16
auto[EscalateSt]	4506522	1			T1	2461		T2	11346		T4	40816
auto[InvalidSt]	7019212	1			T1	1198		T2	13195		T4	89241

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1297	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7019212	1			T1	1198		T2	13195		T4	89241
EscalateSt	4506522	1			T1	2461		T2	11346		T4	40816
ScrapSt	154182	1			T15	61		T31	4		T35	16
PostTransSt	8616792	1			T1	7356		T2	27744		T4	58223
TransProgSt	344462	1			T1	36		T2	200		T4	1685
TokenCheck1St	7490	1			T1	18		T2	8		T4	43
TokenCheck0St	10266	1			T1	27		T2	8		T4	53
FlashRmaSt	28400	1			T1	39		T2	8		T4	132
TokenHashSt	17730486	1			T1	763		T2	86		T4	406452
TransCheckSt	22829	1			T1	36		T2	8		T4	115
CntProgSt	1336982	1			T1	82		T2	247		T4	4996
CntIncrSt	28519	1			T1	46		T2	8		T4	139
ClkMuxSt	28738	1			T1	46		T2	8		T4	146
IdleSt	15560404	1			T1	5606		T2	20897		T3	27531
ResetSt	5343342	1			T1	4814		T2	1273		T3	106
arcs[ResetSt=>IdleSt]	41662	1			T1	54		T2	15		T3	1
arcs[IdleSt=>ScrapSt]	250	1			T15	2		T31	1		T35	4
arcs[IdleSt=>ClkMuxSt]	28553	1			T1	46		T2	8		T4	139
arcs[ClkMuxSt=>CntIncrSt]	28519	1			T1	46		T2	8		T4	139
arcs[CntIncrSt=>PostTransSt]	1248	1			T4	10		T10	4		T11	7
arcs[CntIncrSt=>CntProgSt]	27213	1			T1	46		T2	8		T4	129
arcs[CntProgSt=>PostTransSt]	3377	1			T1	10		T4	14		T9	8
arcs[CntProgSt=>TransCheckSt]	22829	1			T1	36		T2	8		T4	115
arcs[TransCheckSt=>PostTransSt]	3166	1			T4	17		T10	6		T11	1
arcs[TransCheckSt=>TokenHashSt]	19551	1			T1	36		T2	8		T4	98
arcs[TokenHashSt=>PostTransSt]	8392	1			T1	9		T4	45		T9	5
arcs[TokenHashSt=>FlashRmaSt]	10306	1			T1	27		T2	8		T4	53
arcs[FlashRmaSt=>TokenCheck0St]	10266	1			T1	27		T2	8		T4	53
arcs[TokenCheck0St=>PostTransSt]	2725	1			T1	9		T4	10		T9	11
arcs[TokenCheck0St=>TokenCheck1St]	7490	1			T1	18		T2	8		T4	43
arcs[TokenCheck1St=>PostTransSt]	636	1			T4	3		T12	1		T33	2
arcs[TransProgSt=>PostTransSt]	6074	1			T1	18		T2	8		T4	40
arcs[IdleSt=>EscalateSt]	130	1			T35	3		T45	7		T49	4
arcs[ClkMuxSt=>EscalateSt]	34	1			T35	2		T45	1		T46	1
arcs[CntIncrSt=>EscalateSt]	58	1			T31	4		T47	1		T48	4
arcs[CntProgSt=>EscalateSt]	1007	1			T31	3		T35	20		T47	29
arcs[TransCheckSt=>EscalateSt]	112	1			T31	2		T35	3		T45	7
arcs[TokenHashSt=>EscalateSt]	853	1			T31	38		T35	16		T47	17
arcs[FlashRmaSt=>EscalateSt]	40	1			T31	1		T35	1		T47	4
arcs[TokenCheck0St=>EscalateSt]	51	1			T31	1		T35	2		T47	1
arcs[TokenCheck1St=>EscalateSt]	31	1			T53	1		T46	2		T54	1
arcs[TransProgSt=>EscalateSt]	749	1			T31	7		T35	20		T47	32
arcs[PostTransSt=>EscalateSt]	3762	1			T1	10		T4	14		T9	8
arcs[InvalidSt=>EscalateSt]	9436	1			T1	7		T2	5		T4	141

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5343155	1			T1	4814		T2	1273		T3	106
auto[0]	auto[IdleSt]	15560327	1			T1	5606		T2	20897		T3	27531
auto[0]	auto[ClkMuxSt]	28715	1			T1	46		T2	8		T4	146
auto[0]	auto[CntIncrSt]	28479	1			T1	46		T2	8		T4	139
auto[0]	auto[CntProgSt]	1336292	1			T1	82		T2	247		T4	4996
auto[0]	auto[TransCheckSt]	22751	1			T1	36		T2	8		T4	115
auto[0]	auto[TokenHashSt]	17729928	1			T1	763		T2	86		T4	406452
auto[0]	auto[FlashRmaSt]	28375	1			T1	39		T2	8		T4	132
auto[0]	auto[TokenCheck0St]	10226	1			T1	27		T2	8		T4	53
auto[0]	auto[TokenCheck1St]	7466	1			T1	18		T2	8		T4	43
auto[0]	auto[TransProgSt]	343963	1			T1	36		T2	200		T4	1685
auto[0]	auto[PostTransSt]	8614895	1			T1	7351		T2	27744		T4	58214
auto[0]	auto[ScrapSt]	154140	1			T15	61		T31	4		T35	15
auto[0]	auto[EscalateSt]	3416705	1			T1	1383		T2	11152		T4	32421
auto[0]	auto[InvalidSt]	7014443	1			T1	1192		T2	13193		T4	89164
auto[1]	auto[ResetSt]	187	1			T31	1		T35	4		T47	2
auto[1]	auto[IdleSt]	77	1			T35	3		T45	5		T49	2
auto[1]	auto[ClkMuxSt]	23	1			T35	2		T45	1		T215	1
auto[1]	auto[CntIncrSt]	40	1			T31	4		T47	1		T48	2
auto[1]	auto[CntProgSt]	690	1			T31	1		T35	15		T47	22
auto[1]	auto[TransCheckSt]	78	1			T31	2		T35	3		T45	5
auto[1]	auto[TokenHashSt]	558	1			T31	29		T35	12		T47	9
auto[1]	auto[FlashRmaSt]	25	1			T31	1		T35	1		T47	2
auto[1]	auto[TokenCheck0St]	40	1			T31	1		T35	2		T48	1
auto[1]	auto[TokenCheck1St]	24	1			T46	2		T54	1		T216	2
auto[1]	auto[TransProgSt]	499	1			T31	7		T35	11		T47	21
auto[1]	auto[PostTransSt]	1897	1			T1	5		T4	9		T9	3
auto[1]	auto[ScrapSt]	42	1			T35	1		T47	1		T48	1
auto[1]	auto[EscalateSt]	1089817	1			T1	1078		T2	194		T4	8395
auto[1]	auto[InvalidSt]	4769	1			T1	6		T2	2		T4	77

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5343169	1			T1	4814		T2	1273		T3	106
auto[0]	auto[IdleSt]	15560310	1			T1	5606		T2	20897		T3	27531
auto[0]	auto[ClkMuxSt]	28714	1			T1	46		T2	8		T4	146
auto[0]	auto[CntIncrSt]	28480	1			T1	46		T2	8		T4	139
auto[0]	auto[CntProgSt]	1336333	1			T1	82		T2	247		T4	4996
auto[0]	auto[TransCheckSt]	22758	1			T1	36		T2	8		T4	115
auto[0]	auto[TokenHashSt]	17729910	1			T1	763		T2	86		T4	406452
auto[0]	auto[FlashRmaSt]	28373	1			T1	39		T2	8		T4	132
auto[0]	auto[TokenCheck0St]	10235	1			T1	27		T2	8		T4	53
auto[0]	auto[TokenCheck1St]	7473	1			T1	18		T2	8		T4	43
auto[0]	auto[TransProgSt]	343964	1			T1	36		T2	200		T4	1685
auto[0]	auto[PostTransSt]	8614801	1			T1	7351		T2	27744		T4	58218
auto[0]	auto[ScrapSt]	154127	1			T15	61		T31	3		T35	12
auto[0]	auto[EscalateSt]	3426537	1			T1	1873		T2	11055		T4	34091
auto[0]	auto[InvalidSt]	7014545	1			T1	1197		T2	13192		T4	89177
auto[1]	auto[ResetSt]	173	1			T31	1		T35	7		T47	4
auto[1]	auto[IdleSt]	94	1			T35	2		T45	4		T49	2
auto[1]	auto[ClkMuxSt]	24	1			T35	2		T46	1		T215	2
auto[1]	auto[CntIncrSt]	39	1			T31	1		T47	1		T48	2
auto[1]	auto[CntProgSt]	649	1			T31	2		T35	13		T47	17
auto[1]	auto[TransCheckSt]	71	1			T31	1		T45	3		T53	1
auto[1]	auto[TokenHashSt]	576	1			T31	26		T35	10		T47	14
auto[1]	auto[FlashRmaSt]	27	1			T31	1		T35	1		T47	2
auto[1]	auto[TokenCheck0St]	31	1			T31	1		T47	1		T48	1
auto[1]	auto[TokenCheck1St]	17	1			T53	1		T54	1		T216	1
auto[1]	auto[TransProgSt]	498	1			T31	2		T35	17		T47	22
auto[1]	auto[PostTransSt]	1991	1			T1	5		T4	5		T9	5
auto[1]	auto[ScrapSt]	55	1			T31	1		T35	4		T47	1
auto[1]	auto[EscalateSt]	1079985	1			T1	588		T2	291		T4	6725
auto[1]	auto[InvalidSt]	4667	1			T1	1		T2	3		T4	64