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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.92 97.99 96.04 93.40 97.67 98.55 98.51 96.29


Total test records in report: 1000
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T820 /workspace/coverage/default/14.lc_ctrl_alert_test.2624565772 Aug 12 04:57:17 PM PDT 24 Aug 12 04:57:18 PM PDT 24 14873611 ps
T821 /workspace/coverage/default/30.lc_ctrl_jtag_access.2805345982 Aug 12 04:58:14 PM PDT 24 Aug 12 04:58:18 PM PDT 24 444620447 ps
T822 /workspace/coverage/default/23.lc_ctrl_prog_failure.1841881866 Aug 12 04:57:50 PM PDT 24 Aug 12 04:57:52 PM PDT 24 29431122 ps
T823 /workspace/coverage/default/22.lc_ctrl_smoke.2759734852 Aug 12 04:57:51 PM PDT 24 Aug 12 04:57:54 PM PDT 24 187839482 ps
T824 /workspace/coverage/default/21.lc_ctrl_sec_token_digest.4204431093 Aug 12 04:57:44 PM PDT 24 Aug 12 04:57:56 PM PDT 24 1996914165 ps
T825 /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1545051146 Aug 12 04:56:09 PM PDT 24 Aug 12 04:56:27 PM PDT 24 2398644332 ps
T826 /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1506904037 Aug 12 04:56:16 PM PDT 24 Aug 12 04:56:30 PM PDT 24 3265314335 ps
T827 /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2363189894 Aug 12 04:57:16 PM PDT 24 Aug 12 04:57:17 PM PDT 24 22247534 ps
T828 /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3039029878 Aug 12 04:56:41 PM PDT 24 Aug 12 04:56:46 PM PDT 24 1168698611 ps
T829 /workspace/coverage/default/46.lc_ctrl_sec_mubi.3780942821 Aug 12 04:59:07 PM PDT 24 Aug 12 04:59:20 PM PDT 24 483582996 ps
T830 /workspace/coverage/default/9.lc_ctrl_errors.1512993665 Aug 12 04:56:46 PM PDT 24 Aug 12 04:56:59 PM PDT 24 1283756787 ps
T831 /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1310887801 Aug 12 04:56:18 PM PDT 24 Aug 12 04:56:23 PM PDT 24 1011820171 ps
T832 /workspace/coverage/default/37.lc_ctrl_jtag_access.702114774 Aug 12 04:58:38 PM PDT 24 Aug 12 04:58:45 PM PDT 24 285983010 ps
T833 /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1889319198 Aug 12 04:56:39 PM PDT 24 Aug 12 04:56:54 PM PDT 24 414384986 ps
T834 /workspace/coverage/default/9.lc_ctrl_security_escalation.3430725398 Aug 12 04:56:56 PM PDT 24 Aug 12 04:57:03 PM PDT 24 2182367813 ps
T835 /workspace/coverage/default/49.lc_ctrl_state_failure.2005814479 Aug 12 04:59:14 PM PDT 24 Aug 12 04:59:39 PM PDT 24 192824974 ps
T836 /workspace/coverage/default/25.lc_ctrl_state_post_trans.571452393 Aug 12 04:57:59 PM PDT 24 Aug 12 04:58:07 PM PDT 24 271821361 ps
T837 /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2614644624 Aug 12 04:58:46 PM PDT 24 Aug 12 04:58:57 PM PDT 24 525430951 ps
T838 /workspace/coverage/default/27.lc_ctrl_errors.649818477 Aug 12 04:58:04 PM PDT 24 Aug 12 04:58:16 PM PDT 24 3208043651 ps
T839 /workspace/coverage/default/25.lc_ctrl_alert_test.2225636554 Aug 12 04:58:01 PM PDT 24 Aug 12 04:58:02 PM PDT 24 13722485 ps
T840 /workspace/coverage/default/36.lc_ctrl_smoke.4291158762 Aug 12 04:58:29 PM PDT 24 Aug 12 04:58:31 PM PDT 24 82871146 ps
T841 /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2328256327 Aug 12 04:57:24 PM PDT 24 Aug 12 04:57:36 PM PDT 24 1365917905 ps
T842 /workspace/coverage/default/15.lc_ctrl_alert_test.3333579392 Aug 12 04:57:24 PM PDT 24 Aug 12 04:57:25 PM PDT 24 41998719 ps
T843 /workspace/coverage/default/28.lc_ctrl_state_post_trans.2815761235 Aug 12 04:58:10 PM PDT 24 Aug 12 04:58:17 PM PDT 24 58955712 ps
T844 /workspace/coverage/default/0.lc_ctrl_smoke.1001736897 Aug 12 04:56:04 PM PDT 24 Aug 12 04:56:07 PM PDT 24 263758319 ps
T845 /workspace/coverage/default/8.lc_ctrl_smoke.1313298281 Aug 12 04:56:41 PM PDT 24 Aug 12 04:56:43 PM PDT 24 147671701 ps
T846 /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1126551645 Aug 12 04:56:53 PM PDT 24 Aug 12 04:58:53 PM PDT 24 2659065575 ps
T847 /workspace/coverage/default/46.lc_ctrl_smoke.3007227399 Aug 12 04:59:03 PM PDT 24 Aug 12 04:59:05 PM PDT 24 93843789 ps
T848 /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1586623476 Aug 12 04:57:00 PM PDT 24 Aug 12 04:57:15 PM PDT 24 371138499 ps
T849 /workspace/coverage/default/12.lc_ctrl_jtag_errors.3177032113 Aug 12 04:57:07 PM PDT 24 Aug 12 04:57:58 PM PDT 24 1811163065 ps
T850 /workspace/coverage/default/20.lc_ctrl_sec_token_mux.957783299 Aug 12 04:57:44 PM PDT 24 Aug 12 04:58:08 PM PDT 24 679683158 ps
T851 /workspace/coverage/default/20.lc_ctrl_errors.72420575 Aug 12 04:57:45 PM PDT 24 Aug 12 04:57:56 PM PDT 24 358425338 ps
T852 /workspace/coverage/default/8.lc_ctrl_jtag_priority.557466327 Aug 12 04:56:45 PM PDT 24 Aug 12 04:57:05 PM PDT 24 3848744540 ps
T853 /workspace/coverage/default/27.lc_ctrl_sec_mubi.3641048950 Aug 12 04:58:06 PM PDT 24 Aug 12 04:58:14 PM PDT 24 751597204 ps
T854 /workspace/coverage/default/1.lc_ctrl_security_escalation.2928496256 Aug 12 04:56:08 PM PDT 24 Aug 12 04:56:16 PM PDT 24 304431151 ps
T855 /workspace/coverage/default/41.lc_ctrl_errors.515624692 Aug 12 04:58:53 PM PDT 24 Aug 12 04:59:08 PM PDT 24 11710143540 ps
T856 /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1016630179 Aug 12 04:58:14 PM PDT 24 Aug 12 04:58:25 PM PDT 24 250248938 ps
T857 /workspace/coverage/default/20.lc_ctrl_prog_failure.1401170148 Aug 12 04:57:48 PM PDT 24 Aug 12 04:57:51 PM PDT 24 90154984 ps
T858 /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1730995763 Aug 12 04:56:34 PM PDT 24 Aug 12 04:56:45 PM PDT 24 252920237 ps
T859 /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1307737471 Aug 12 04:58:58 PM PDT 24 Aug 12 04:58:59 PM PDT 24 24206921 ps
T860 /workspace/coverage/default/29.lc_ctrl_state_failure.2275079655 Aug 12 04:58:14 PM PDT 24 Aug 12 04:58:34 PM PDT 24 247995835 ps
T861 /workspace/coverage/default/48.lc_ctrl_jtag_access.2017381627 Aug 12 04:59:13 PM PDT 24 Aug 12 04:59:23 PM PDT 24 6607896761 ps
T862 /workspace/coverage/default/27.lc_ctrl_jtag_access.296354611 Aug 12 04:58:06 PM PDT 24 Aug 12 04:58:11 PM PDT 24 722438744 ps
T863 /workspace/coverage/default/16.lc_ctrl_stress_all.1729806747 Aug 12 04:57:21 PM PDT 24 Aug 12 04:57:36 PM PDT 24 1117442153 ps
T864 /workspace/coverage/default/45.lc_ctrl_stress_all.3187588617 Aug 12 04:59:01 PM PDT 24 Aug 12 05:02:29 PM PDT 24 12832567201 ps
T865 /workspace/coverage/default/43.lc_ctrl_jtag_access.1519148266 Aug 12 04:58:51 PM PDT 24 Aug 12 04:58:57 PM PDT 24 2337825895 ps
T866 /workspace/coverage/default/3.lc_ctrl_jtag_access.1123176942 Aug 12 04:56:17 PM PDT 24 Aug 12 04:56:20 PM PDT 24 271160637 ps
T867 /workspace/coverage/default/41.lc_ctrl_state_failure.2440056628 Aug 12 04:58:44 PM PDT 24 Aug 12 04:59:07 PM PDT 24 270020954 ps
T868 /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1931909183 Aug 12 04:58:13 PM PDT 24 Aug 12 04:58:20 PM PDT 24 270675595 ps
T869 /workspace/coverage/default/3.lc_ctrl_security_escalation.1702662273 Aug 12 04:56:21 PM PDT 24 Aug 12 04:56:29 PM PDT 24 994054448 ps
T870 /workspace/coverage/default/36.lc_ctrl_state_failure.1029416217 Aug 12 04:58:30 PM PDT 24 Aug 12 04:58:53 PM PDT 24 1088194206 ps
T871 /workspace/coverage/default/47.lc_ctrl_jtag_access.1244752615 Aug 12 04:59:09 PM PDT 24 Aug 12 04:59:20 PM PDT 24 1537690539 ps
T872 /workspace/coverage/default/6.lc_ctrl_prog_failure.1646179863 Aug 12 04:56:33 PM PDT 24 Aug 12 04:56:36 PM PDT 24 258310930 ps
T873 /workspace/coverage/default/14.lc_ctrl_security_escalation.2992731279 Aug 12 04:57:15 PM PDT 24 Aug 12 04:57:25 PM PDT 24 1559629275 ps
T874 /workspace/coverage/default/12.lc_ctrl_jtag_access.1602445358 Aug 12 04:57:08 PM PDT 24 Aug 12 04:57:12 PM PDT 24 241335730 ps
T875 /workspace/coverage/default/32.lc_ctrl_smoke.1206087402 Aug 12 04:58:23 PM PDT 24 Aug 12 04:58:27 PM PDT 24 667230754 ps
T876 /workspace/coverage/default/22.lc_ctrl_alert_test.956036851 Aug 12 04:57:51 PM PDT 24 Aug 12 04:57:52 PM PDT 24 171967854 ps
T877 /workspace/coverage/default/12.lc_ctrl_state_post_trans.785035910 Aug 12 04:57:08 PM PDT 24 Aug 12 04:57:16 PM PDT 24 317906989 ps
T214 /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3648090959 Aug 12 04:56:52 PM PDT 24 Aug 12 04:56:53 PM PDT 24 14008089 ps
T183 /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3412153585 Aug 12 04:58:50 PM PDT 24 Aug 12 05:01:12 PM PDT 24 2900539623 ps
T878 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1053296815 Aug 12 04:58:22 PM PDT 24 Aug 12 04:58:46 PM PDT 24 3968422315 ps
T879 /workspace/coverage/default/39.lc_ctrl_sec_mubi.1282791463 Aug 12 04:58:44 PM PDT 24 Aug 12 04:58:54 PM PDT 24 189289539 ps
T880 /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2858463597 Aug 12 04:57:53 PM PDT 24 Aug 12 04:57:55 PM PDT 24 12597627 ps
T881 /workspace/coverage/default/7.lc_ctrl_alert_test.911145188 Aug 12 04:56:40 PM PDT 24 Aug 12 04:56:42 PM PDT 24 57447423 ps
T882 /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2686843481 Aug 12 04:56:46 PM PDT 24 Aug 12 04:56:57 PM PDT 24 1628257164 ps
T123 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2498679132 Aug 12 04:40:05 PM PDT 24 Aug 12 04:40:06 PM PDT 24 52877112 ps
T106 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1167977903 Aug 12 04:40:22 PM PDT 24 Aug 12 04:40:24 PM PDT 24 61313559 ps
T124 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2577658343 Aug 12 04:40:09 PM PDT 24 Aug 12 04:40:14 PM PDT 24 1740317889 ps
T147 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3495653637 Aug 12 04:40:03 PM PDT 24 Aug 12 04:40:05 PM PDT 24 29433817 ps
T116 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.4279265484 Aug 12 04:40:37 PM PDT 24 Aug 12 04:40:38 PM PDT 24 26546353 ps
T110 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.61157705 Aug 12 04:40:28 PM PDT 24 Aug 12 04:40:29 PM PDT 24 86643181 ps
T144 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.159844981 Aug 12 04:40:12 PM PDT 24 Aug 12 04:40:19 PM PDT 24 265340456 ps
T107 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1086014215 Aug 12 04:40:40 PM PDT 24 Aug 12 04:40:43 PM PDT 24 39291913 ps
T199 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.193224091 Aug 12 04:40:31 PM PDT 24 Aug 12 04:40:32 PM PDT 24 62741579 ps
T145 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.431545351 Aug 12 04:40:13 PM PDT 24 Aug 12 04:40:17 PM PDT 24 96036283 ps
T883 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2310715446 Aug 12 04:40:14 PM PDT 24 Aug 12 04:40:15 PM PDT 24 32853665 ps
T113 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2156709722 Aug 12 04:40:40 PM PDT 24 Aug 12 04:40:42 PM PDT 24 50739593 ps
T108 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.4214283840 Aug 12 04:40:32 PM PDT 24 Aug 12 04:40:37 PM PDT 24 119340400 ps
T114 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1883979224 Aug 12 04:40:34 PM PDT 24 Aug 12 04:40:36 PM PDT 24 21546702 ps
T112 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.274282024 Aug 12 04:40:17 PM PDT 24 Aug 12 04:40:18 PM PDT 24 46662771 ps
T884 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.751333098 Aug 12 04:40:32 PM PDT 24 Aug 12 04:40:35 PM PDT 24 58608785 ps
T111 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.858239911 Aug 12 04:40:38 PM PDT 24 Aug 12 04:40:40 PM PDT 24 156259204 ps
T162 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3679434396 Aug 12 04:40:17 PM PDT 24 Aug 12 04:40:19 PM PDT 24 38309114 ps
T146 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2278988483 Aug 12 04:40:22 PM PDT 24 Aug 12 04:40:27 PM PDT 24 193314627 ps
T115 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1677552336 Aug 12 04:40:32 PM PDT 24 Aug 12 04:40:35 PM PDT 24 52475231 ps
T885 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1298263959 Aug 12 04:40:18 PM PDT 24 Aug 12 04:40:20 PM PDT 24 152443789 ps
T184 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1956002165 Aug 12 04:40:36 PM PDT 24 Aug 12 04:40:39 PM PDT 24 322025644 ps
T200 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.465879542 Aug 12 04:40:36 PM PDT 24 Aug 12 04:40:37 PM PDT 24 15680547 ps
T185 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3104108582 Aug 12 04:40:11 PM PDT 24 Aug 12 04:40:15 PM PDT 24 304764612 ps
T188 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1644258472 Aug 12 04:40:14 PM PDT 24 Aug 12 04:40:15 PM PDT 24 47474927 ps
T201 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.884156088 Aug 12 04:40:29 PM PDT 24 Aug 12 04:40:30 PM PDT 24 12916562 ps
T138 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.4012884224 Aug 12 04:40:30 PM PDT 24 Aug 12 04:40:32 PM PDT 24 163529694 ps
T121 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1827335589 Aug 12 04:40:01 PM PDT 24 Aug 12 04:40:05 PM PDT 24 452156580 ps
T202 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.608494523 Aug 12 04:40:20 PM PDT 24 Aug 12 04:40:22 PM PDT 24 22261229 ps
T141 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3762445292 Aug 12 04:40:34 PM PDT 24 Aug 12 04:40:35 PM PDT 24 487644307 ps
T122 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2471261241 Aug 12 04:40:31 PM PDT 24 Aug 12 04:40:35 PM PDT 24 86887550 ps
T886 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.619067047 Aug 12 04:40:32 PM PDT 24 Aug 12 04:40:34 PM PDT 24 33949753 ps
T887 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4001609077 Aug 12 04:40:02 PM PDT 24 Aug 12 04:40:03 PM PDT 24 91791155 ps
T888 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.784776884 Aug 12 04:40:31 PM PDT 24 Aug 12 04:40:34 PM PDT 24 581064880 ps
T889 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.703167984 Aug 12 04:40:03 PM PDT 24 Aug 12 04:40:05 PM PDT 24 22480271 ps
T890 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2648749127 Aug 12 04:40:05 PM PDT 24 Aug 12 04:40:06 PM PDT 24 13258318 ps
T203 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3702980953 Aug 12 04:40:02 PM PDT 24 Aug 12 04:40:03 PM PDT 24 15819682 ps
T189 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2057311342 Aug 12 04:40:39 PM PDT 24 Aug 12 04:40:40 PM PDT 24 42998756 ps
T163 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1322625827 Aug 12 04:40:40 PM PDT 24 Aug 12 04:40:41 PM PDT 24 20332034 ps
T142 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1228379336 Aug 12 04:40:15 PM PDT 24 Aug 12 04:40:19 PM PDT 24 857633779 ps
T118 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.623496760 Aug 12 04:40:38 PM PDT 24 Aug 12 04:40:42 PM PDT 24 216175973 ps
T891 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.190669841 Aug 12 04:40:31 PM PDT 24 Aug 12 04:40:43 PM PDT 24 424057399 ps
T130 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2277291112 Aug 12 04:40:38 PM PDT 24 Aug 12 04:40:41 PM PDT 24 99482697 ps
T164 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2309348448 Aug 12 04:40:02 PM PDT 24 Aug 12 04:40:03 PM PDT 24 34102670 ps
T143 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.806066389 Aug 12 04:40:17 PM PDT 24 Aug 12 04:40:19 PM PDT 24 174510087 ps
T204 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.883979086 Aug 12 04:40:13 PM PDT 24 Aug 12 04:40:14 PM PDT 24 50086343 ps
T135 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.626046322 Aug 12 04:40:13 PM PDT 24 Aug 12 04:40:16 PM PDT 24 331643974 ps
T205 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3487740284 Aug 12 04:40:33 PM PDT 24 Aug 12 04:40:34 PM PDT 24 71593651 ps
T206 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1156137242 Aug 12 04:40:38 PM PDT 24 Aug 12 04:40:39 PM PDT 24 14228980 ps
T892 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.448111103 Aug 12 04:40:13 PM PDT 24 Aug 12 04:40:15 PM PDT 24 276840445 ps
T893 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3966072973 Aug 12 04:40:31 PM PDT 24 Aug 12 04:40:32 PM PDT 24 49184367 ps
T894 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4099852924 Aug 12 04:40:07 PM PDT 24 Aug 12 04:40:09 PM PDT 24 163833665 ps
T207 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.212928844 Aug 12 04:40:14 PM PDT 24 Aug 12 04:40:15 PM PDT 24 37575992 ps
T895 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.617671410 Aug 12 04:40:43 PM PDT 24 Aug 12 04:40:45 PM PDT 24 254655868 ps
T896 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4172526909 Aug 12 04:40:03 PM PDT 24 Aug 12 04:40:13 PM PDT 24 1182657113 ps
T897 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2450337711 Aug 12 04:40:20 PM PDT 24 Aug 12 04:40:22 PM PDT 24 195122184 ps
T119 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.303809483 Aug 12 04:40:14 PM PDT 24 Aug 12 04:40:17 PM PDT 24 270753781 ps
T898 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3521283408 Aug 12 04:40:43 PM PDT 24 Aug 12 04:40:44 PM PDT 24 39105417 ps
T165 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2820451170 Aug 12 04:40:42 PM PDT 24 Aug 12 04:40:46 PM PDT 24 116167456 ps
T166 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3305001213 Aug 12 04:40:13 PM PDT 24 Aug 12 04:40:15 PM PDT 24 152926427 ps
T899 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.486133455 Aug 12 04:40:02 PM PDT 24 Aug 12 04:40:04 PM PDT 24 215972770 ps
T900 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1443153705 Aug 12 04:40:34 PM PDT 24 Aug 12 04:40:36 PM PDT 24 15899732 ps
T120 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1872067707 Aug 12 04:40:04 PM PDT 24 Aug 12 04:40:06 PM PDT 24 52826768 ps
T131 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4189823311 Aug 12 04:40:33 PM PDT 24 Aug 12 04:40:36 PM PDT 24 153554224 ps
T190 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.364983546 Aug 12 04:40:40 PM PDT 24 Aug 12 04:40:41 PM PDT 24 15305595 ps
T901 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.4186929933 Aug 12 04:40:31 PM PDT 24 Aug 12 04:40:33 PM PDT 24 132983468 ps
T902 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3901652792 Aug 12 04:40:22 PM PDT 24 Aug 12 04:40:24 PM PDT 24 52165223 ps
T903 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3843598648 Aug 12 04:40:39 PM PDT 24 Aug 12 04:40:40 PM PDT 24 24656757 ps
T904 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2777578895 Aug 12 04:40:38 PM PDT 24 Aug 12 04:40:39 PM PDT 24 20219878 ps
T905 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3860117617 Aug 12 04:40:34 PM PDT 24 Aug 12 04:40:35 PM PDT 24 283164026 ps
T906 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3053821374 Aug 12 04:40:29 PM PDT 24 Aug 12 04:40:31 PM PDT 24 24962673 ps
T195 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2397323789 Aug 12 04:40:12 PM PDT 24 Aug 12 04:40:14 PM PDT 24 425893294 ps
T907 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1672758053 Aug 12 04:40:38 PM PDT 24 Aug 12 04:40:40 PM PDT 24 26706029 ps
T908 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2242357965 Aug 12 04:40:05 PM PDT 24 Aug 12 04:40:06 PM PDT 24 497632885 ps
T909 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1082349405 Aug 12 04:40:35 PM PDT 24 Aug 12 04:40:37 PM PDT 24 197646075 ps
T910 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1781497221 Aug 12 04:40:19 PM PDT 24 Aug 12 04:40:22 PM PDT 24 97141429 ps
T191 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3832465208 Aug 12 04:40:18 PM PDT 24 Aug 12 04:40:20 PM PDT 24 14773606 ps
T911 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1931016433 Aug 12 04:40:34 PM PDT 24 Aug 12 04:40:36 PM PDT 24 67781190 ps
T912 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2026003910 Aug 12 04:40:30 PM PDT 24 Aug 12 04:40:32 PM PDT 24 121164287 ps
T913 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.905786851 Aug 12 04:40:04 PM PDT 24 Aug 12 04:40:06 PM PDT 24 90006659 ps
T125 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.4052074879 Aug 12 04:40:08 PM PDT 24 Aug 12 04:40:11 PM PDT 24 590362573 ps
T139 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1876643525 Aug 12 04:40:38 PM PDT 24 Aug 12 04:40:40 PM PDT 24 57085449 ps
T914 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3260562452 Aug 12 04:40:31 PM PDT 24 Aug 12 04:40:32 PM PDT 24 114428774 ps
T915 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2233298815 Aug 12 04:40:29 PM PDT 24 Aug 12 04:40:32 PM PDT 24 101825469 ps
T916 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3629730684 Aug 12 04:40:19 PM PDT 24 Aug 12 04:40:22 PM PDT 24 77981284 ps
T917 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1357387475 Aug 12 04:40:22 PM PDT 24 Aug 12 04:40:23 PM PDT 24 67712149 ps
T918 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.238121015 Aug 12 04:40:05 PM PDT 24 Aug 12 04:40:07 PM PDT 24 104619503 ps
T919 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3470275681 Aug 12 04:40:14 PM PDT 24 Aug 12 04:40:15 PM PDT 24 15974464 ps
T920 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4158493543 Aug 12 04:40:31 PM PDT 24 Aug 12 04:40:33 PM PDT 24 110460663 ps
T921 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4132580177 Aug 12 04:40:01 PM PDT 24 Aug 12 04:40:07 PM PDT 24 340497799 ps
T922 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2814681783 Aug 12 04:40:03 PM PDT 24 Aug 12 04:40:19 PM PDT 24 5000047955 ps
T127 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.759889259 Aug 12 04:40:29 PM PDT 24 Aug 12 04:40:33 PM PDT 24 79556866 ps
T923 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4160903365 Aug 12 04:40:30 PM PDT 24 Aug 12 04:40:31 PM PDT 24 32939591 ps
T924 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2927958092 Aug 12 04:40:33 PM PDT 24 Aug 12 04:40:35 PM PDT 24 70875836 ps
T192 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3463559993 Aug 12 04:40:19 PM PDT 24 Aug 12 04:40:20 PM PDT 24 50921090 ps
T925 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1862455546 Aug 12 04:40:39 PM PDT 24 Aug 12 04:40:40 PM PDT 24 14253464 ps
T926 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2147469925 Aug 12 04:40:08 PM PDT 24 Aug 12 04:40:13 PM PDT 24 1067314759 ps
T927 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1542086394 Aug 12 04:40:20 PM PDT 24 Aug 12 04:40:22 PM PDT 24 147144001 ps
T193 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2882008085 Aug 12 04:40:05 PM PDT 24 Aug 12 04:40:06 PM PDT 24 49027877 ps
T928 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2413050969 Aug 12 04:40:02 PM PDT 24 Aug 12 04:40:13 PM PDT 24 444403118 ps
T929 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.723912881 Aug 12 04:40:15 PM PDT 24 Aug 12 04:40:56 PM PDT 24 1781151327 ps
T930 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4252851276 Aug 12 04:40:34 PM PDT 24 Aug 12 04:40:37 PM PDT 24 207805432 ps
T931 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3882303718 Aug 12 04:40:19 PM PDT 24 Aug 12 04:40:21 PM PDT 24 339788980 ps
T194 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.314879119 Aug 12 04:40:01 PM PDT 24 Aug 12 04:40:02 PM PDT 24 47292837 ps
T196 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.465784226 Aug 12 04:40:32 PM PDT 24 Aug 12 04:40:34 PM PDT 24 28962384 ps
T932 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1879192192 Aug 12 04:40:02 PM PDT 24 Aug 12 04:40:04 PM PDT 24 52704149 ps
T933 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3879952350 Aug 12 04:40:29 PM PDT 24 Aug 12 04:40:31 PM PDT 24 197517872 ps
T934 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1717897578 Aug 12 04:40:05 PM PDT 24 Aug 12 04:40:09 PM PDT 24 138033034 ps
T935 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.810992140 Aug 12 04:40:31 PM PDT 24 Aug 12 04:40:52 PM PDT 24 1111064408 ps
T936 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1764537874 Aug 12 04:40:16 PM PDT 24 Aug 12 04:40:19 PM PDT 24 67225703 ps
T937 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.814767970 Aug 12 04:40:21 PM PDT 24 Aug 12 04:40:24 PM PDT 24 177032615 ps
T197 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2766678707 Aug 12 04:40:11 PM PDT 24 Aug 12 04:40:12 PM PDT 24 53724169 ps
T938 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.8939324 Aug 12 04:40:34 PM PDT 24 Aug 12 04:40:35 PM PDT 24 125848283 ps
T939 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3660511305 Aug 12 04:40:28 PM PDT 24 Aug 12 04:40:32 PM PDT 24 52146263 ps
T940 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1454641707 Aug 12 04:40:35 PM PDT 24 Aug 12 04:40:36 PM PDT 24 53426045 ps
T941 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2992425029 Aug 12 04:40:18 PM PDT 24 Aug 12 04:40:22 PM PDT 24 207439494 ps
T942 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4156941745 Aug 12 04:40:16 PM PDT 24 Aug 12 04:40:17 PM PDT 24 53785872 ps
T943 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3142534161 Aug 12 04:40:17 PM PDT 24 Aug 12 04:40:19 PM PDT 24 75083721 ps
T198 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2661277569 Aug 12 04:40:29 PM PDT 24 Aug 12 04:40:30 PM PDT 24 33904051 ps
T944 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.913291950 Aug 12 04:40:07 PM PDT 24 Aug 12 04:40:10 PM PDT 24 100570697 ps
T945 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1851775139 Aug 12 04:40:28 PM PDT 24 Aug 12 04:40:30 PM PDT 24 23132412 ps
T946 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3779323907 Aug 12 04:40:21 PM PDT 24 Aug 12 04:40:22 PM PDT 24 14291119 ps
T947 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3037113896 Aug 12 04:40:23 PM PDT 24 Aug 12 04:40:25 PM PDT 24 92809762 ps
T948 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2025240889 Aug 12 04:40:23 PM PDT 24 Aug 12 04:40:42 PM PDT 24 18943230165 ps
T949 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.14884629 Aug 12 04:40:31 PM PDT 24 Aug 12 04:40:39 PM PDT 24 3183572028 ps
T950 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4188917781 Aug 12 04:40:18 PM PDT 24 Aug 12 04:40:20 PM PDT 24 16521980 ps
T951 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3978895951 Aug 12 04:40:32 PM PDT 24 Aug 12 04:40:34 PM PDT 24 96335731 ps
T952 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.232987851 Aug 12 04:40:33 PM PDT 24 Aug 12 04:40:34 PM PDT 24 65268252 ps
T953 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.571990455 Aug 12 04:40:42 PM PDT 24 Aug 12 04:40:44 PM PDT 24 94450611 ps
T954 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1976598144 Aug 12 04:40:05 PM PDT 24 Aug 12 04:40:07 PM PDT 24 259402270 ps
T955 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4240661145 Aug 12 04:40:06 PM PDT 24 Aug 12 04:40:09 PM PDT 24 892983468 ps
T956 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.846348360 Aug 12 04:40:31 PM PDT 24 Aug 12 04:40:34 PM PDT 24 388424626 ps
T957 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3896478241 Aug 12 04:40:39 PM PDT 24 Aug 12 04:40:41 PM PDT 24 130359051 ps
T133 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3888420807 Aug 12 04:40:22 PM PDT 24 Aug 12 04:40:25 PM PDT 24 128647111 ps
T958 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3167602868 Aug 12 04:40:32 PM PDT 24 Aug 12 04:40:34 PM PDT 24 39113569 ps
T959 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1346551448 Aug 12 04:40:40 PM PDT 24 Aug 12 04:40:43 PM PDT 24 106181645 ps
T960 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1203179842 Aug 12 04:40:19 PM PDT 24 Aug 12 04:40:22 PM PDT 24 937145685 ps
T961 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3063731483 Aug 12 04:40:14 PM PDT 24 Aug 12 04:40:16 PM PDT 24 226310160 ps
T962 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1478360530 Aug 12 04:40:39 PM PDT 24 Aug 12 04:40:40 PM PDT 24 14130075 ps
T137 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.910814518 Aug 12 04:40:29 PM PDT 24 Aug 12 04:40:32 PM PDT 24 109947486 ps
T963 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1581505857 Aug 12 04:40:29 PM PDT 24 Aug 12 04:40:30 PM PDT 24 56818372 ps
T964 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4211054538 Aug 12 04:40:16 PM PDT 24 Aug 12 04:40:17 PM PDT 24 22376781 ps
T126 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3626332092 Aug 12 04:40:41 PM PDT 24 Aug 12 04:40:43 PM PDT 24 136815548 ps
T965 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3205411144 Aug 12 04:40:41 PM PDT 24 Aug 12 04:40:44 PM PDT 24 45448089 ps
T966 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.249439948 Aug 12 04:40:17 PM PDT 24 Aug 12 04:40:19 PM PDT 24 58624149 ps
T967 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3851150310 Aug 12 04:40:33 PM PDT 24 Aug 12 04:40:36 PM PDT 24 477320778 ps
T140 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3658057702 Aug 12 04:40:32 PM PDT 24 Aug 12 04:40:35 PM PDT 24 73113573 ps
T968 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1114643758 Aug 12 04:40:18 PM PDT 24 Aug 12 04:40:19 PM PDT 24 35367017 ps
T969 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2059493325 Aug 12 04:40:20 PM PDT 24 Aug 12 04:40:22 PM PDT 24 13725403 ps
T970 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3910074116 Aug 12 04:40:32 PM PDT 24 Aug 12 04:40:34 PM PDT 24 19794676 ps
T971 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3797126610 Aug 12 04:40:19 PM PDT 24 Aug 12 04:40:29 PM PDT 24 1619860280 ps
T972 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2934754837 Aug 12 04:40:36 PM PDT 24 Aug 12 04:40:37 PM PDT 24 16755054 ps
T973 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3768139054 Aug 12 04:40:19 PM PDT 24 Aug 12 04:40:32 PM PDT 24 1243077399 ps
T974 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.765651152 Aug 12 04:40:22 PM PDT 24 Aug 12 04:40:23 PM PDT 24 59625496 ps
T129 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1583544170 Aug 12 04:40:33 PM PDT 24 Aug 12 04:40:36 PM PDT 24 485901316 ps
T134 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2565102647 Aug 12 04:40:40 PM PDT 24 Aug 12 04:40:43 PM PDT 24 222187738 ps
T975 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2565153729 Aug 12 04:40:19 PM PDT 24 Aug 12 04:40:21 PM PDT 24 43113600 ps
T976 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3540866721 Aug 12 04:40:18 PM PDT 24 Aug 12 04:40:19 PM PDT 24 99822618 ps
T977 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1290517335 Aug 12 04:40:21 PM PDT 24 Aug 12 04:40:24 PM PDT 24 88554677 ps
T978 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1813454541 Aug 12 04:40:03 PM PDT 24 Aug 12 04:40:04 PM PDT 24 22396136 ps
T979 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3510317472 Aug 12 04:40:34 PM PDT 24 Aug 12 04:40:43 PM PDT 24 1866600362 ps
T980 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1428373823 Aug 12 04:40:39 PM PDT 24 Aug 12 04:40:41 PM PDT 24 44804265 ps
T981 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.162526999 Aug 12 04:40:21 PM PDT 24 Aug 12 04:40:23 PM PDT 24 24806977 ps
T982 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1725577482 Aug 12 04:40:32 PM PDT 24 Aug 12 04:40:37 PM PDT 24 1843253086 ps
T136 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4214280762 Aug 12 04:40:04 PM PDT 24 Aug 12 04:40:06 PM PDT 24 252077667 ps
T983 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1862452295 Aug 12 04:40:04 PM PDT 24 Aug 12 04:40:06 PM PDT 24 485351413 ps
T984 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2480556430 Aug 12 04:40:20 PM PDT 24 Aug 12 04:40:22 PM PDT 24 672423444 ps
T985 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.249172861 Aug 12 04:40:24 PM PDT 24 Aug 12 04:40:32 PM PDT 24 1538629014 ps
T986 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2979830709 Aug 12 04:40:21 PM PDT 24 Aug 12 04:40:23 PM PDT 24 27085169 ps
T987 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2811529139 Aug 12 04:40:28 PM PDT 24 Aug 12 04:40:33 PM PDT 24 3148099216 ps
T988 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3271093436 Aug 12 04:40:38 PM PDT 24 Aug 12 04:40:40 PM PDT 24 23404449 ps
T989 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.427174633 Aug 12 04:40:31 PM PDT 24 Aug 12 04:40:34 PM PDT 24 979062011 ps
T990 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1848123220 Aug 12 04:40:34 PM PDT 24 Aug 12 04:40:36 PM PDT 24 333235202 ps
T991 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2052611343 Aug 12 04:40:31 PM PDT 24 Aug 12 04:40:33 PM PDT 24 51014226 ps
T992 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3368067657 Aug 12 04:40:02 PM PDT 24 Aug 12 04:40:05 PM PDT 24 80919296 ps
T993 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.86556862 Aug 12 04:40:32 PM PDT 24 Aug 12 04:40:34 PM PDT 24 43120412 ps
T994 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4096024411 Aug 12 04:40:31 PM PDT 24 Aug 12 04:40:33 PM PDT 24 37614625 ps
T995 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1466924708 Aug 12 04:40:18 PM PDT 24 Aug 12 04:40:41 PM PDT 24 3999575517 ps
T996 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.800754596 Aug 12 04:40:20 PM PDT 24 Aug 12 04:40:22 PM PDT 24 24166921 ps
T128 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1628436731 Aug 12 04:40:14 PM PDT 24 Aug 12 04:40:17 PM PDT 24 114562981 ps
T997 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.792556810 Aug 12 04:40:23 PM PDT 24 Aug 12 04:40:24 PM PDT 24 88448220 ps
T998 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2967865348 Aug 12 04:40:02 PM PDT 24 Aug 12 04:40:04 PM PDT 24 78263668 ps
T999 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1797822135 Aug 12 04:40:17 PM PDT 24 Aug 12 04:40:19 PM PDT 24 204960829 ps
T1000 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.173569753 Aug 12 04:40:17 PM PDT 24 Aug 12 04:40:19 PM PDT 24 28330313 ps
T132 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3564289197 Aug 12 04:40:31 PM PDT 24 Aug 12 04:40:34 PM PDT 24 42809008 ps

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2487252469
Short name T4
Test name
Test status
Simulation time 29814037803 ps
CPU time 292.9 seconds
Started Aug 12 04:56:12 PM PDT 24
Finished Aug 12 05:01:05 PM PDT 24
Peak memory 283808 kb
Host smart-e92dd39e-5d58-4913-9d24-523a670b1658
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487252469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2487252469
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1912234970
Short name T31
Test name
Test status
Simulation time 216580944 ps
CPU time 9.89 seconds
Started Aug 12 04:59:11 PM PDT 24
Finished Aug 12 04:59:21 PM PDT 24
Peak memory 218472 kb
Host smart-d05245b3-92d8-47b4-8e74-d87813d143c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912234970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1912234970
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.556854282
Short name T1
Test name
Test status
Simulation time 225300298 ps
CPU time 11.3 seconds
Started Aug 12 04:57:46 PM PDT 24
Finished Aug 12 04:57:57 PM PDT 24
Peak memory 218456 kb
Host smart-b75bb713-5098-4dde-9e0e-778def120f96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556854282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.556854282
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1769692553
Short name T216
Test name
Test status
Simulation time 1483594463 ps
CPU time 9.27 seconds
Started Aug 12 04:57:29 PM PDT 24
Finished Aug 12 04:57:38 PM PDT 24
Peak memory 218444 kb
Host smart-2e27cd02-affe-4ec7-934f-e526dac145bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769692553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1769692553
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.61157705
Short name T110
Test name
Test status
Simulation time 86643181 ps
CPU time 1.26 seconds
Started Aug 12 04:40:28 PM PDT 24
Finished Aug 12 04:40:29 PM PDT 24
Peak memory 218072 kb
Host smart-2b045c10-b6d1-42ee-bac6-fe7042808f6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61157705 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.61157705
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2481789046
Short name T15
Test name
Test status
Simulation time 28629730019 ps
CPU time 59.96 seconds
Started Aug 12 04:58:34 PM PDT 24
Finished Aug 12 04:59:34 PM PDT 24
Peak memory 270448 kb
Host smart-116743d0-d183-4164-ac13-eec6c4eca1fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481789046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2481789046
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2071211995
Short name T29
Test name
Test status
Simulation time 11656998 ps
CPU time 0.93 seconds
Started Aug 12 04:56:34 PM PDT 24
Finished Aug 12 04:56:35 PM PDT 24
Peak memory 209180 kb
Host smart-356edb56-04c5-4a15-ae1e-646e46f7e396
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071211995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2071211995
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.3657152207
Short name T55
Test name
Test status
Simulation time 2360548915 ps
CPU time 53.63 seconds
Started Aug 12 04:59:11 PM PDT 24
Finished Aug 12 05:00:05 PM PDT 24
Peak memory 275924 kb
Host smart-10f20fb5-e919-46bb-9b48-57dbd390d253
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3657152207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.3657152207
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.309238816
Short name T50
Test name
Test status
Simulation time 2182248169 ps
CPU time 42.68 seconds
Started Aug 12 04:56:07 PM PDT 24
Finished Aug 12 04:56:50 PM PDT 24
Peak memory 284752 kb
Host smart-0d767bb9-56f6-434b-aead-3047534a5494
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309238816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.309238816
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2063518185
Short name T38
Test name
Test status
Simulation time 71000271955 ps
CPU time 203.94 seconds
Started Aug 12 04:58:22 PM PDT 24
Finished Aug 12 05:01:47 PM PDT 24
Peak memory 283904 kb
Host smart-f7022835-965e-4a03-bed2-8de9cb5af401
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063518185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2063518185
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.1857002494
Short name T85
Test name
Test status
Simulation time 1549385023 ps
CPU time 58.15 seconds
Started Aug 12 04:57:54 PM PDT 24
Finished Aug 12 04:58:52 PM PDT 24
Peak memory 251192 kb
Host smart-44b62e54-672e-4dda-87f8-ab3ea3477be3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1857002494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.1857002494
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.4181391182
Short name T32
Test name
Test status
Simulation time 9965286244 ps
CPU time 12.6 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:12 PM PDT 24
Peak memory 218372 kb
Host smart-acc16048-7e51-4722-b703-f1c4ca01120c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181391182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
4181391182
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.4214283840
Short name T108
Test name
Test status
Simulation time 119340400 ps
CPU time 4.53 seconds
Started Aug 12 04:40:32 PM PDT 24
Finished Aug 12 04:40:37 PM PDT 24
Peak memory 218064 kb
Host smart-a4f17cb2-569b-4408-ab94-7ac2b6b98ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214283840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.4214283840
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3381090906
Short name T3
Test name
Test status
Simulation time 287927837 ps
CPU time 5.02 seconds
Started Aug 12 04:56:12 PM PDT 24
Finished Aug 12 04:56:18 PM PDT 24
Peak memory 217776 kb
Host smart-f0bcd3be-f1e7-46cf-a4ae-a891cfd82a4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381090906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3381090906
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3893917773
Short name T79
Test name
Test status
Simulation time 75562010 ps
CPU time 0.89 seconds
Started Aug 12 04:57:45 PM PDT 24
Finished Aug 12 04:57:46 PM PDT 24
Peak memory 209024 kb
Host smart-0c1be6a4-ef1b-445c-9bf3-d50d0750e442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893917773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3893917773
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2309348448
Short name T164
Test name
Test status
Simulation time 34102670 ps
CPU time 1.11 seconds
Started Aug 12 04:40:02 PM PDT 24
Finished Aug 12 04:40:03 PM PDT 24
Peak memory 218688 kb
Host smart-f93babf0-d3ac-4ee8-bbe4-af504868b460
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309348448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2309348448
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3762445292
Short name T141
Test name
Test status
Simulation time 487644307 ps
CPU time 1.21 seconds
Started Aug 12 04:40:34 PM PDT 24
Finished Aug 12 04:40:35 PM PDT 24
Peak memory 209820 kb
Host smart-15e5d476-0b2b-40ef-88f9-d0b5fa7be78f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762445292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3762445292
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2471261241
Short name T122
Test name
Test status
Simulation time 86887550 ps
CPU time 3.25 seconds
Started Aug 12 04:40:31 PM PDT 24
Finished Aug 12 04:40:35 PM PDT 24
Peak memory 218460 kb
Host smart-c9a34167-96f5-438a-b4e8-b57d7c6625e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471261241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2471261241
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.907788164
Short name T33
Test name
Test status
Simulation time 6025753757 ps
CPU time 14.36 seconds
Started Aug 12 04:57:52 PM PDT 24
Finished Aug 12 04:58:07 PM PDT 24
Peak memory 219328 kb
Host smart-4525fade-7138-4607-8936-c1986c8f4172
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907788164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.907788164
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1583544170
Short name T129
Test name
Test status
Simulation time 485901316 ps
CPU time 2.8 seconds
Started Aug 12 04:40:33 PM PDT 24
Finished Aug 12 04:40:36 PM PDT 24
Peak memory 222440 kb
Host smart-5e9d5dbc-4d9b-4288-8139-ece3481d1aca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583544170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1583544170
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3626332092
Short name T126
Test name
Test status
Simulation time 136815548 ps
CPU time 2.68 seconds
Started Aug 12 04:40:41 PM PDT 24
Finished Aug 12 04:40:43 PM PDT 24
Peak memory 223016 kb
Host smart-cbd81590-6002-486f-be40-1dd65aa7580b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626332092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3626332092
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2535890523
Short name T263
Test name
Test status
Simulation time 1649800993 ps
CPU time 29.38 seconds
Started Aug 12 04:57:15 PM PDT 24
Finished Aug 12 04:57:44 PM PDT 24
Peak memory 251104 kb
Host smart-90528c39-7dc7-4ec5-9389-0c0068d5d937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535890523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2535890523
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.3503023435
Short name T103
Test name
Test status
Simulation time 7783511918 ps
CPU time 128.32 seconds
Started Aug 12 04:57:13 PM PDT 24
Finished Aug 12 04:59:22 PM PDT 24
Peak memory 273592 kb
Host smart-0009313a-993f-49a3-8f9c-060e77d6e377
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3503023435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.3503023435
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2277291112
Short name T130
Test name
Test status
Simulation time 99482697 ps
CPU time 2.97 seconds
Started Aug 12 04:40:38 PM PDT 24
Finished Aug 12 04:40:41 PM PDT 24
Peak memory 222800 kb
Host smart-8a3792e3-675e-4808-b117-4c5f4e7f46f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277291112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2277291112
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1876643525
Short name T139
Test name
Test status
Simulation time 57085449 ps
CPU time 1.94 seconds
Started Aug 12 04:40:38 PM PDT 24
Finished Aug 12 04:40:40 PM PDT 24
Peak memory 222508 kb
Host smart-334bd5de-0d43-4456-b775-84c973b3ab43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876643525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1876643525
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3702980953
Short name T203
Test name
Test status
Simulation time 15819682 ps
CPU time 1.09 seconds
Started Aug 12 04:40:02 PM PDT 24
Finished Aug 12 04:40:03 PM PDT 24
Peak memory 210108 kb
Host smart-07a0ec5f-103a-4130-a115-24474fb3e1f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702980953 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3702980953
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1557281928
Short name T12
Test name
Test status
Simulation time 385813143 ps
CPU time 14.87 seconds
Started Aug 12 04:57:08 PM PDT 24
Finished Aug 12 04:57:23 PM PDT 24
Peak memory 226208 kb
Host smart-eec8201a-afe5-411b-b814-6c8c4745573a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557281928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1557281928
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1872067707
Short name T120
Test name
Test status
Simulation time 52826768 ps
CPU time 1.62 seconds
Started Aug 12 04:40:04 PM PDT 24
Finished Aug 12 04:40:06 PM PDT 24
Peak memory 220264 kb
Host smart-818ea7e4-68c1-46f1-97c7-78def81d3df2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872067707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1872067707
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.910814518
Short name T137
Test name
Test status
Simulation time 109947486 ps
CPU time 2.44 seconds
Started Aug 12 04:40:29 PM PDT 24
Finished Aug 12 04:40:32 PM PDT 24
Peak memory 218056 kb
Host smart-83f7e9f5-0b76-4276-b61c-723dccc50c38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910814518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.910814518
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2565102647
Short name T134
Test name
Test status
Simulation time 222187738 ps
CPU time 2.92 seconds
Started Aug 12 04:40:40 PM PDT 24
Finished Aug 12 04:40:43 PM PDT 24
Peak memory 222404 kb
Host smart-ec42d1e2-3610-4a1c-b91a-3a6a115f94bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565102647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2565102647
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.626046322
Short name T135
Test name
Test status
Simulation time 331643974 ps
CPU time 2.79 seconds
Started Aug 12 04:40:13 PM PDT 24
Finished Aug 12 04:40:16 PM PDT 24
Peak memory 218052 kb
Host smart-ba2eb38e-2190-4cfb-be08-562916fc01d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626046322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.626046322
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2809933054
Short name T209
Test name
Test status
Simulation time 10658913 ps
CPU time 0.89 seconds
Started Aug 12 04:56:02 PM PDT 24
Finished Aug 12 04:56:03 PM PDT 24
Peak memory 208760 kb
Host smart-7d70a84c-9928-4d64-b2e4-37e3c70a2519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809933054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2809933054
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1440703698
Short name T212
Test name
Test status
Simulation time 37881739 ps
CPU time 0.95 seconds
Started Aug 12 04:56:17 PM PDT 24
Finished Aug 12 04:56:18 PM PDT 24
Peak memory 208924 kb
Host smart-d1adb8b6-914d-4062-877d-078706bcefc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440703698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1440703698
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1615690075
Short name T211
Test name
Test status
Simulation time 13265055 ps
CPU time 1.04 seconds
Started Aug 12 04:56:30 PM PDT 24
Finished Aug 12 04:56:31 PM PDT 24
Peak memory 208864 kb
Host smart-c0179b67-a370-4bfa-b367-84de3be8b8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615690075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1615690075
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2036666994
Short name T213
Test name
Test status
Simulation time 29369585 ps
CPU time 0.87 seconds
Started Aug 12 04:56:45 PM PDT 24
Finished Aug 12 04:56:46 PM PDT 24
Peak memory 208900 kb
Host smart-e5d1c4ed-5496-4c45-9e90-eadb0b41e65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036666994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2036666994
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.4052074879
Short name T125
Test name
Test status
Simulation time 590362573 ps
CPU time 3.23 seconds
Started Aug 12 04:40:08 PM PDT 24
Finished Aug 12 04:40:11 PM PDT 24
Peak memory 222800 kb
Host smart-c7f5b234-9be2-4ec2-a24e-272c7761b598
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052074879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.4052074879
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4214280762
Short name T136
Test name
Test status
Simulation time 252077667 ps
CPU time 1.81 seconds
Started Aug 12 04:40:04 PM PDT 24
Finished Aug 12 04:40:06 PM PDT 24
Peak memory 218052 kb
Host smart-51f4b2f4-25de-4955-a6b4-c90e4664e20d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214280762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.4214280762
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3564289197
Short name T132
Test name
Test status
Simulation time 42809008 ps
CPU time 1.85 seconds
Started Aug 12 04:40:31 PM PDT 24
Finished Aug 12 04:40:34 PM PDT 24
Peak memory 222272 kb
Host smart-3537c744-ce62-4401-bc63-3eb5262d25c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564289197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3564289197
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1628436731
Short name T128
Test name
Test status
Simulation time 114562981 ps
CPU time 2.62 seconds
Started Aug 12 04:40:14 PM PDT 24
Finished Aug 12 04:40:17 PM PDT 24
Peak memory 218160 kb
Host smart-d041e5a1-3e0f-4d63-b28e-ad95f60725d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628436731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1628436731
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3776260307
Short name T44
Test name
Test status
Simulation time 1653603892 ps
CPU time 12.64 seconds
Started Aug 12 04:57:03 PM PDT 24
Finished Aug 12 04:57:16 PM PDT 24
Peak memory 218444 kb
Host smart-83fb416d-2271-4f0f-b44b-86164e62d0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776260307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3776260307
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2513479125
Short name T7
Test name
Test status
Simulation time 614568587 ps
CPU time 27.04 seconds
Started Aug 12 04:57:03 PM PDT 24
Finished Aug 12 04:57:30 PM PDT 24
Peak memory 251032 kb
Host smart-d95bfc0a-719d-4e94-9592-86670b403d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513479125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2513479125
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2155447986
Short name T8
Test name
Test status
Simulation time 47192965 ps
CPU time 2.08 seconds
Started Aug 12 04:57:15 PM PDT 24
Finished Aug 12 04:57:17 PM PDT 24
Peak memory 217848 kb
Host smart-80deff4c-6ad9-44b4-b5e6-7be78d08680a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155447986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2155447986
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3355287132
Short name T84
Test name
Test status
Simulation time 9919353308 ps
CPU time 82.29 seconds
Started Aug 12 04:56:04 PM PDT 24
Finished Aug 12 04:57:26 PM PDT 24
Peak memory 275252 kb
Host smart-0a22218a-7a67-444a-98b1-a980893c8175
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3355287132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.3355287132
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3495653637
Short name T147
Test name
Test status
Simulation time 29433817 ps
CPU time 1.01 seconds
Started Aug 12 04:40:03 PM PDT 24
Finished Aug 12 04:40:05 PM PDT 24
Peak memory 209856 kb
Host smart-0753e22e-0c39-4908-8c08-dcdc38fcde68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495653637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3495653637
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1976598144
Short name T954
Test name
Test status
Simulation time 259402270 ps
CPU time 1.85 seconds
Started Aug 12 04:40:05 PM PDT 24
Finished Aug 12 04:40:07 PM PDT 24
Peak memory 209112 kb
Host smart-e5930f74-47d1-4fc0-8aff-d032f999c491
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976598144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1976598144
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2648749127
Short name T890
Test name
Test status
Simulation time 13258318 ps
CPU time 1.15 seconds
Started Aug 12 04:40:05 PM PDT 24
Finished Aug 12 04:40:06 PM PDT 24
Peak memory 210312 kb
Host smart-c33eb829-adb5-4ff4-abfa-9f1abe9c39e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648749127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2648749127
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4001609077
Short name T887
Test name
Test status
Simulation time 91791155 ps
CPU time 1.13 seconds
Started Aug 12 04:40:02 PM PDT 24
Finished Aug 12 04:40:03 PM PDT 24
Peak memory 218156 kb
Host smart-ff30cd76-7f35-4529-91aa-0a76258735a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001609077 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.4001609077
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2882008085
Short name T193
Test name
Test status
Simulation time 49027877 ps
CPU time 0.93 seconds
Started Aug 12 04:40:05 PM PDT 24
Finished Aug 12 04:40:06 PM PDT 24
Peak memory 209868 kb
Host smart-f2bf14f7-8f49-4f31-a435-f8dbfbbf416f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882008085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2882008085
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2967865348
Short name T998
Test name
Test status
Simulation time 78263668 ps
CPU time 2.01 seconds
Started Aug 12 04:40:02 PM PDT 24
Finished Aug 12 04:40:04 PM PDT 24
Peak memory 209804 kb
Host smart-fa885e98-5ec5-4bb8-bdae-b82b54a9989c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967865348 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2967865348
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4132580177
Short name T921
Test name
Test status
Simulation time 340497799 ps
CPU time 5.62 seconds
Started Aug 12 04:40:01 PM PDT 24
Finished Aug 12 04:40:07 PM PDT 24
Peak memory 209732 kb
Host smart-0b940a2d-1c6a-4950-b48f-138494a7c2eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132580177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.4132580177
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2577658343
Short name T124
Test name
Test status
Simulation time 1740317889 ps
CPU time 5.21 seconds
Started Aug 12 04:40:09 PM PDT 24
Finished Aug 12 04:40:14 PM PDT 24
Peak memory 209660 kb
Host smart-7cc32ea9-d04d-4d41-b4d8-84a4d0b7bc0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577658343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2577658343
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.905786851
Short name T913
Test name
Test status
Simulation time 90006659 ps
CPU time 1.54 seconds
Started Aug 12 04:40:04 PM PDT 24
Finished Aug 12 04:40:06 PM PDT 24
Peak memory 209808 kb
Host smart-e0e7b8c7-5184-4ceb-bbe4-c2669a8771cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905786851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.905786851
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.486133455
Short name T899
Test name
Test status
Simulation time 215972770 ps
CPU time 2.06 seconds
Started Aug 12 04:40:02 PM PDT 24
Finished Aug 12 04:40:04 PM PDT 24
Peak memory 218080 kb
Host smart-fc675890-dbd4-4924-bff3-8217e3c0e56a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486133
455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.486133455
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3063731483
Short name T961
Test name
Test status
Simulation time 226310160 ps
CPU time 1.61 seconds
Started Aug 12 04:40:14 PM PDT 24
Finished Aug 12 04:40:16 PM PDT 24
Peak memory 209792 kb
Host smart-a4c5b441-e28e-4498-8c17-48e024e47e28
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063731483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3063731483
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1813454541
Short name T978
Test name
Test status
Simulation time 22396136 ps
CPU time 1.5 seconds
Started Aug 12 04:40:03 PM PDT 24
Finished Aug 12 04:40:04 PM PDT 24
Peak memory 211856 kb
Host smart-0d888cb0-3afd-493a-82d0-dc231f4a0ec3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813454541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1813454541
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1827335589
Short name T121
Test name
Test status
Simulation time 452156580 ps
CPU time 3.34 seconds
Started Aug 12 04:40:01 PM PDT 24
Finished Aug 12 04:40:05 PM PDT 24
Peak memory 218148 kb
Host smart-0f066291-ce5f-4866-8605-0c1314db0851
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827335589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1827335589
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2498679132
Short name T123
Test name
Test status
Simulation time 52877112 ps
CPU time 1.15 seconds
Started Aug 12 04:40:05 PM PDT 24
Finished Aug 12 04:40:06 PM PDT 24
Peak memory 209952 kb
Host smart-416e5b3b-414a-4bf0-8b71-34ab775a80be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498679132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2498679132
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.703167984
Short name T889
Test name
Test status
Simulation time 22480271 ps
CPU time 1.44 seconds
Started Aug 12 04:40:03 PM PDT 24
Finished Aug 12 04:40:05 PM PDT 24
Peak memory 208800 kb
Host smart-740436a0-7e63-4543-a6d4-cd9e50ab48bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703167984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.703167984
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.238121015
Short name T918
Test name
Test status
Simulation time 104619503 ps
CPU time 1.35 seconds
Started Aug 12 04:40:05 PM PDT 24
Finished Aug 12 04:40:07 PM PDT 24
Peak memory 219236 kb
Host smart-77b64c6d-7084-4f57-83ce-90548bd17538
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238121015 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.238121015
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.314879119
Short name T194
Test name
Test status
Simulation time 47292837 ps
CPU time 0.86 seconds
Started Aug 12 04:40:01 PM PDT 24
Finished Aug 12 04:40:02 PM PDT 24
Peak memory 209836 kb
Host smart-3ba242e7-6440-467f-abfb-fb663fbeac08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314879119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.314879119
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2242357965
Short name T908
Test name
Test status
Simulation time 497632885 ps
CPU time 1.39 seconds
Started Aug 12 04:40:05 PM PDT 24
Finished Aug 12 04:40:06 PM PDT 24
Peak memory 209764 kb
Host smart-0d27a4b1-bece-4122-8db7-804d641ee570
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242357965 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2242357965
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2413050969
Short name T928
Test name
Test status
Simulation time 444403118 ps
CPU time 10.28 seconds
Started Aug 12 04:40:02 PM PDT 24
Finished Aug 12 04:40:13 PM PDT 24
Peak memory 209676 kb
Host smart-15d38105-372d-4e97-94c0-1eeafdd55f84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413050969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2413050969
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2814681783
Short name T922
Test name
Test status
Simulation time 5000047955 ps
CPU time 16.28 seconds
Started Aug 12 04:40:03 PM PDT 24
Finished Aug 12 04:40:19 PM PDT 24
Peak memory 209892 kb
Host smart-166a1408-0011-4caa-afef-00a2023fa8ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814681783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2814681783
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.913291950
Short name T944
Test name
Test status
Simulation time 100570697 ps
CPU time 2.94 seconds
Started Aug 12 04:40:07 PM PDT 24
Finished Aug 12 04:40:10 PM PDT 24
Peak memory 211020 kb
Host smart-c63c284f-dc57-4f18-ad16-627d0d6700a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913291950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.913291950
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3368067657
Short name T992
Test name
Test status
Simulation time 80919296 ps
CPU time 2.72 seconds
Started Aug 12 04:40:02 PM PDT 24
Finished Aug 12 04:40:05 PM PDT 24
Peak memory 222384 kb
Host smart-3a25bdcd-7fdd-4dd7-8203-023e7d56656a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336806
7657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3368067657
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1717897578
Short name T934
Test name
Test status
Simulation time 138033034 ps
CPU time 3.8 seconds
Started Aug 12 04:40:05 PM PDT 24
Finished Aug 12 04:40:09 PM PDT 24
Peak memory 209852 kb
Host smart-0f47ebc0-d57a-4614-b008-00836e3a400a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717897578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1717897578
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1862452295
Short name T983
Test name
Test status
Simulation time 485351413 ps
CPU time 1.43 seconds
Started Aug 12 04:40:04 PM PDT 24
Finished Aug 12 04:40:06 PM PDT 24
Peak memory 209856 kb
Host smart-6c421619-8597-4e2d-beb4-b3dda3b28e67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862452295 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1862452295
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.212928844
Short name T207
Test name
Test status
Simulation time 37575992 ps
CPU time 1.28 seconds
Started Aug 12 04:40:14 PM PDT 24
Finished Aug 12 04:40:15 PM PDT 24
Peak memory 211920 kb
Host smart-ab731454-ab39-4c28-a749-0084f686e0b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212928844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.212928844
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1883979224
Short name T114
Test name
Test status
Simulation time 21546702 ps
CPU time 1.44 seconds
Started Aug 12 04:40:34 PM PDT 24
Finished Aug 12 04:40:36 PM PDT 24
Peak memory 218244 kb
Host smart-28c74d4b-5fea-496e-8660-2b75683c314e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883979224 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1883979224
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2661277569
Short name T198
Test name
Test status
Simulation time 33904051 ps
CPU time 0.85 seconds
Started Aug 12 04:40:29 PM PDT 24
Finished Aug 12 04:40:30 PM PDT 24
Peak memory 209424 kb
Host smart-7ad04ab1-0eb4-4cf3-be93-14eca8501bdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661277569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2661277569
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.465879542
Short name T200
Test name
Test status
Simulation time 15680547 ps
CPU time 1.15 seconds
Started Aug 12 04:40:36 PM PDT 24
Finished Aug 12 04:40:37 PM PDT 24
Peak memory 209836 kb
Host smart-9fe3456e-2d61-4e09-90ec-5e1cbaf7fe9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465879542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.465879542
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3660511305
Short name T939
Test name
Test status
Simulation time 52146263 ps
CPU time 3.53 seconds
Started Aug 12 04:40:28 PM PDT 24
Finished Aug 12 04:40:32 PM PDT 24
Peak memory 218152 kb
Host smart-03bfc3db-06e7-459e-a022-6d9b99d01475
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660511305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3660511305
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3658057702
Short name T140
Test name
Test status
Simulation time 73113573 ps
CPU time 2.06 seconds
Started Aug 12 04:40:32 PM PDT 24
Finished Aug 12 04:40:35 PM PDT 24
Peak memory 222356 kb
Host smart-b10c2cb2-8c73-4959-8acf-fc7f0f082433
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658057702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3658057702
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1443153705
Short name T900
Test name
Test status
Simulation time 15899732 ps
CPU time 1.12 seconds
Started Aug 12 04:40:34 PM PDT 24
Finished Aug 12 04:40:36 PM PDT 24
Peak memory 209868 kb
Host smart-184a0ee7-5d32-43f7-a372-b0600ff76b4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443153705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1443153705
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2927958092
Short name T924
Test name
Test status
Simulation time 70875836 ps
CPU time 1.2 seconds
Started Aug 12 04:40:33 PM PDT 24
Finished Aug 12 04:40:35 PM PDT 24
Peak memory 209720 kb
Host smart-9d6fb8dc-27b4-4c26-a136-5a1c9b0265cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927958092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2927958092
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3851150310
Short name T967
Test name
Test status
Simulation time 477320778 ps
CPU time 3.05 seconds
Started Aug 12 04:40:33 PM PDT 24
Finished Aug 12 04:40:36 PM PDT 24
Peak memory 218672 kb
Host smart-cefdb499-38ee-4c52-83ae-ef7c965fdbaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851150310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3851150310
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2026003910
Short name T912
Test name
Test status
Simulation time 121164287 ps
CPU time 1.8 seconds
Started Aug 12 04:40:30 PM PDT 24
Finished Aug 12 04:40:32 PM PDT 24
Peak memory 219084 kb
Host smart-ef62328d-b883-4ded-9d7d-d997c8cbe39b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026003910 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2026003910
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.465784226
Short name T196
Test name
Test status
Simulation time 28962384 ps
CPU time 1.03 seconds
Started Aug 12 04:40:32 PM PDT 24
Finished Aug 12 04:40:34 PM PDT 24
Peak memory 209900 kb
Host smart-2d78582e-6641-4d7e-bdb2-4bd2e14d5b5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465784226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.465784226
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3271093436
Short name T988
Test name
Test status
Simulation time 23404449 ps
CPU time 1.24 seconds
Started Aug 12 04:40:38 PM PDT 24
Finished Aug 12 04:40:40 PM PDT 24
Peak memory 211992 kb
Host smart-9062fe31-83e2-4fb7-ad9e-f2778a08b33d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271093436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3271093436
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1082349405
Short name T909
Test name
Test status
Simulation time 197646075 ps
CPU time 2.04 seconds
Started Aug 12 04:40:35 PM PDT 24
Finished Aug 12 04:40:37 PM PDT 24
Peak memory 218032 kb
Host smart-91cd7276-07ad-4313-b3a2-d59ac190a747
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082349405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1082349405
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1851775139
Short name T945
Test name
Test status
Simulation time 23132412 ps
CPU time 1.52 seconds
Started Aug 12 04:40:28 PM PDT 24
Finished Aug 12 04:40:30 PM PDT 24
Peak memory 218264 kb
Host smart-789a3178-d566-4418-b1b7-8a9cd6131594
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851775139 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1851775139
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3167602868
Short name T958
Test name
Test status
Simulation time 39113569 ps
CPU time 0.93 seconds
Started Aug 12 04:40:32 PM PDT 24
Finished Aug 12 04:40:34 PM PDT 24
Peak memory 209832 kb
Host smart-5d5c0102-1f06-442e-adc3-31191ef24e50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167602868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3167602868
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1581505857
Short name T963
Test name
Test status
Simulation time 56818372 ps
CPU time 1.47 seconds
Started Aug 12 04:40:29 PM PDT 24
Finished Aug 12 04:40:30 PM PDT 24
Peak memory 209836 kb
Host smart-697d571d-faa9-4232-a2d2-63e09f2b874c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581505857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1581505857
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.846348360
Short name T956
Test name
Test status
Simulation time 388424626 ps
CPU time 3.11 seconds
Started Aug 12 04:40:31 PM PDT 24
Finished Aug 12 04:40:34 PM PDT 24
Peak memory 218004 kb
Host smart-bc1533cf-4ed8-4863-a03a-bae3545178cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846348360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.846348360
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1672758053
Short name T907
Test name
Test status
Simulation time 26706029 ps
CPU time 2.08 seconds
Started Aug 12 04:40:38 PM PDT 24
Finished Aug 12 04:40:40 PM PDT 24
Peak memory 224976 kb
Host smart-bee2689d-72cc-4a40-8fc9-396545977c81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672758053 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1672758053
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3910074116
Short name T970
Test name
Test status
Simulation time 19794676 ps
CPU time 1.19 seconds
Started Aug 12 04:40:32 PM PDT 24
Finished Aug 12 04:40:34 PM PDT 24
Peak memory 209768 kb
Host smart-934dd4ab-fd69-4cfb-af5d-ccc91d8486d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910074116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3910074116
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.193224091
Short name T199
Test name
Test status
Simulation time 62741579 ps
CPU time 1.33 seconds
Started Aug 12 04:40:31 PM PDT 24
Finished Aug 12 04:40:32 PM PDT 24
Peak memory 210052 kb
Host smart-22e856cb-2c33-4d37-b09c-cbb0084155df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193224091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.193224091
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.4012884224
Short name T138
Test name
Test status
Simulation time 163529694 ps
CPU time 2.27 seconds
Started Aug 12 04:40:30 PM PDT 24
Finished Aug 12 04:40:32 PM PDT 24
Peak memory 218020 kb
Host smart-4f25db5b-7b51-45b7-b87d-51a43a681d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012884224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.4012884224
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.617671410
Short name T895
Test name
Test status
Simulation time 254655868 ps
CPU time 1.86 seconds
Started Aug 12 04:40:43 PM PDT 24
Finished Aug 12 04:40:45 PM PDT 24
Peak memory 224920 kb
Host smart-9e24280e-1afe-4a92-bfb8-4423ef112539
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617671410 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.617671410
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.4279265484
Short name T116
Test name
Test status
Simulation time 26546353 ps
CPU time 1.02 seconds
Started Aug 12 04:40:37 PM PDT 24
Finished Aug 12 04:40:38 PM PDT 24
Peak memory 209840 kb
Host smart-783ce23e-59a5-491a-81d9-04b737e04e40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279265484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.4279265484
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1862455546
Short name T925
Test name
Test status
Simulation time 14253464 ps
CPU time 1.04 seconds
Started Aug 12 04:40:39 PM PDT 24
Finished Aug 12 04:40:40 PM PDT 24
Peak memory 209820 kb
Host smart-5834a866-40c2-431d-98a8-dcce9094e632
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862455546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1862455546
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3205411144
Short name T965
Test name
Test status
Simulation time 45448089 ps
CPU time 3.41 seconds
Started Aug 12 04:40:41 PM PDT 24
Finished Aug 12 04:40:44 PM PDT 24
Peak memory 218184 kb
Host smart-50435407-6807-4934-a901-b9e9a1973716
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205411144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3205411144
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3896478241
Short name T957
Test name
Test status
Simulation time 130359051 ps
CPU time 1.43 seconds
Started Aug 12 04:40:39 PM PDT 24
Finished Aug 12 04:40:41 PM PDT 24
Peak memory 218996 kb
Host smart-6ae3e536-777d-4c19-82a6-95be6b305d0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896478241 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3896478241
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.364983546
Short name T190
Test name
Test status
Simulation time 15305595 ps
CPU time 1.18 seconds
Started Aug 12 04:40:40 PM PDT 24
Finished Aug 12 04:40:41 PM PDT 24
Peak memory 209860 kb
Host smart-7ce4888a-c58e-4587-a889-136d767e3c30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364983546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.364983546
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1428373823
Short name T980
Test name
Test status
Simulation time 44804265 ps
CPU time 1.91 seconds
Started Aug 12 04:40:39 PM PDT 24
Finished Aug 12 04:40:41 PM PDT 24
Peak memory 209880 kb
Host smart-2c63bb4e-842f-421f-a11e-a4beed041dd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428373823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1428373823
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.623496760
Short name T118
Test name
Test status
Simulation time 216175973 ps
CPU time 4.55 seconds
Started Aug 12 04:40:38 PM PDT 24
Finished Aug 12 04:40:42 PM PDT 24
Peak memory 218056 kb
Host smart-793cc31b-d9c5-4000-97c6-d20e92468a45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623496760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.623496760
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2777578895
Short name T904
Test name
Test status
Simulation time 20219878 ps
CPU time 1.13 seconds
Started Aug 12 04:40:38 PM PDT 24
Finished Aug 12 04:40:39 PM PDT 24
Peak memory 219244 kb
Host smart-e6657ed8-d7d4-4857-982d-320b6649963a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777578895 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2777578895
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1478360530
Short name T962
Test name
Test status
Simulation time 14130075 ps
CPU time 0.86 seconds
Started Aug 12 04:40:39 PM PDT 24
Finished Aug 12 04:40:40 PM PDT 24
Peak memory 209608 kb
Host smart-bfe9175b-6230-4cce-a329-c181f837d6bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478360530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1478360530
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3521283408
Short name T898
Test name
Test status
Simulation time 39105417 ps
CPU time 1.01 seconds
Started Aug 12 04:40:43 PM PDT 24
Finished Aug 12 04:40:44 PM PDT 24
Peak memory 209964 kb
Host smart-ce3664a5-16e8-432f-90b0-749356523d96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521283408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3521283408
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.858239911
Short name T111
Test name
Test status
Simulation time 156259204 ps
CPU time 1.68 seconds
Started Aug 12 04:40:38 PM PDT 24
Finished Aug 12 04:40:40 PM PDT 24
Peak memory 218232 kb
Host smart-20b68805-2ddb-4424-a4fc-c3c201f39982
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858239911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.858239911
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1086014215
Short name T107
Test name
Test status
Simulation time 39291913 ps
CPU time 1.96 seconds
Started Aug 12 04:40:40 PM PDT 24
Finished Aug 12 04:40:43 PM PDT 24
Peak memory 222536 kb
Host smart-24f57d54-714c-4832-8562-ac3c15d5bf74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086014215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1086014215
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2156709722
Short name T113
Test name
Test status
Simulation time 50739593 ps
CPU time 1.25 seconds
Started Aug 12 04:40:40 PM PDT 24
Finished Aug 12 04:40:42 PM PDT 24
Peak memory 219096 kb
Host smart-a5dff71e-3320-4b65-8bdf-89f25cb797af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156709722 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2156709722
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1156137242
Short name T206
Test name
Test status
Simulation time 14228980 ps
CPU time 0.87 seconds
Started Aug 12 04:40:38 PM PDT 24
Finished Aug 12 04:40:39 PM PDT 24
Peak memory 209864 kb
Host smart-e3cc5d2b-c211-41a8-b94b-861a45e4bc47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156137242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1156137242
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.571990455
Short name T953
Test name
Test status
Simulation time 94450611 ps
CPU time 1.18 seconds
Started Aug 12 04:40:42 PM PDT 24
Finished Aug 12 04:40:44 PM PDT 24
Peak memory 209984 kb
Host smart-93fddf0a-0321-419c-9ee5-ca736e5476a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571990455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.571990455
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1346551448
Short name T959
Test name
Test status
Simulation time 106181645 ps
CPU time 2.95 seconds
Started Aug 12 04:40:40 PM PDT 24
Finished Aug 12 04:40:43 PM PDT 24
Peak memory 218084 kb
Host smart-98549c91-47da-4f88-a04e-967a4f4dfb53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346551448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1346551448
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1322625827
Short name T163
Test name
Test status
Simulation time 20332034 ps
CPU time 1.26 seconds
Started Aug 12 04:40:40 PM PDT 24
Finished Aug 12 04:40:41 PM PDT 24
Peak memory 218060 kb
Host smart-2ac818a6-d978-404e-8890-84f006a38088
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322625827 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1322625827
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2057311342
Short name T189
Test name
Test status
Simulation time 42998756 ps
CPU time 1 seconds
Started Aug 12 04:40:39 PM PDT 24
Finished Aug 12 04:40:40 PM PDT 24
Peak memory 209912 kb
Host smart-c5391e46-1ea1-4f52-b444-c61c977d4fdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057311342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2057311342
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3843598648
Short name T903
Test name
Test status
Simulation time 24656757 ps
CPU time 1.34 seconds
Started Aug 12 04:40:39 PM PDT 24
Finished Aug 12 04:40:40 PM PDT 24
Peak memory 211960 kb
Host smart-0de64cc6-1890-476c-ae8f-f1600fd2b41b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843598648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3843598648
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2820451170
Short name T165
Test name
Test status
Simulation time 116167456 ps
CPU time 3.29 seconds
Started Aug 12 04:40:42 PM PDT 24
Finished Aug 12 04:40:46 PM PDT 24
Peak memory 218068 kb
Host smart-c5a7602d-7a8d-4034-bf8c-cbdabf5c7b90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820451170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2820451170
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1644258472
Short name T188
Test name
Test status
Simulation time 47474927 ps
CPU time 1.08 seconds
Started Aug 12 04:40:14 PM PDT 24
Finished Aug 12 04:40:15 PM PDT 24
Peak memory 209324 kb
Host smart-a91c3787-7e75-4e93-a85a-2971c5c2a48a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644258472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1644258472
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1797822135
Short name T999
Test name
Test status
Simulation time 204960829 ps
CPU time 1.4 seconds
Started Aug 12 04:40:17 PM PDT 24
Finished Aug 12 04:40:19 PM PDT 24
Peak memory 209836 kb
Host smart-0c4cffc0-9238-4373-8c94-90547c629861
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797822135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1797822135
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1114643758
Short name T968
Test name
Test status
Simulation time 35367017 ps
CPU time 0.9 seconds
Started Aug 12 04:40:18 PM PDT 24
Finished Aug 12 04:40:19 PM PDT 24
Peak memory 210276 kb
Host smart-f914e86d-ab37-4246-9a53-4a2c10fee8f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114643758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1114643758
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.173569753
Short name T1000
Test name
Test status
Simulation time 28330313 ps
CPU time 1.22 seconds
Started Aug 12 04:40:17 PM PDT 24
Finished Aug 12 04:40:19 PM PDT 24
Peak memory 219180 kb
Host smart-e44fe821-b9f8-4a77-a4d0-91914e3e9434
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173569753 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.173569753
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3470275681
Short name T919
Test name
Test status
Simulation time 15974464 ps
CPU time 0.87 seconds
Started Aug 12 04:40:14 PM PDT 24
Finished Aug 12 04:40:15 PM PDT 24
Peak memory 209656 kb
Host smart-f335c19d-4ced-45bf-b1a9-14cde91d60e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470275681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3470275681
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4156941745
Short name T942
Test name
Test status
Simulation time 53785872 ps
CPU time 1.01 seconds
Started Aug 12 04:40:16 PM PDT 24
Finished Aug 12 04:40:17 PM PDT 24
Peak memory 209728 kb
Host smart-4798db27-961f-4f29-b4e9-c7799e7cc242
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156941745 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.4156941745
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2147469925
Short name T926
Test name
Test status
Simulation time 1067314759 ps
CPU time 4.76 seconds
Started Aug 12 04:40:08 PM PDT 24
Finished Aug 12 04:40:13 PM PDT 24
Peak memory 209672 kb
Host smart-7cca2838-3dd5-40e0-8a83-624c84e441ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147469925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2147469925
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4172526909
Short name T896
Test name
Test status
Simulation time 1182657113 ps
CPU time 9.74 seconds
Started Aug 12 04:40:03 PM PDT 24
Finished Aug 12 04:40:13 PM PDT 24
Peak memory 209088 kb
Host smart-8943adb8-4cb2-45b6-b23b-d0a1734ca974
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172526909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4172526909
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1879192192
Short name T932
Test name
Test status
Simulation time 52704149 ps
CPU time 2.07 seconds
Started Aug 12 04:40:02 PM PDT 24
Finished Aug 12 04:40:04 PM PDT 24
Peak memory 211376 kb
Host smart-fcd39f74-c5e7-48f1-9e8a-6e24d08466ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879192192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1879192192
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4240661145
Short name T955
Test name
Test status
Simulation time 892983468 ps
CPU time 2.97 seconds
Started Aug 12 04:40:06 PM PDT 24
Finished Aug 12 04:40:09 PM PDT 24
Peak memory 219192 kb
Host smart-d3fa7643-2999-4f7d-9ffa-26ae77e7c47e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424066
1145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4240661145
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4099852924
Short name T894
Test name
Test status
Simulation time 163833665 ps
CPU time 1.52 seconds
Started Aug 12 04:40:07 PM PDT 24
Finished Aug 12 04:40:09 PM PDT 24
Peak memory 209016 kb
Host smart-30100d95-3228-4bd5-be7d-11cbf842e0f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099852924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.4099852924
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.883979086
Short name T204
Test name
Test status
Simulation time 50086343 ps
CPU time 0.98 seconds
Started Aug 12 04:40:13 PM PDT 24
Finished Aug 12 04:40:14 PM PDT 24
Peak memory 209856 kb
Host smart-7b22b270-e123-4ee0-9608-bcf67b829dc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883979086 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.883979086
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3305001213
Short name T166
Test name
Test status
Simulation time 152926427 ps
CPU time 1.42 seconds
Started Aug 12 04:40:13 PM PDT 24
Finished Aug 12 04:40:15 PM PDT 24
Peak memory 211972 kb
Host smart-ce15f04c-904c-499c-916e-2c5c2e78de82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305001213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3305001213
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1764537874
Short name T936
Test name
Test status
Simulation time 67225703 ps
CPU time 2.33 seconds
Started Aug 12 04:40:16 PM PDT 24
Finished Aug 12 04:40:19 PM PDT 24
Peak memory 218056 kb
Host smart-6c2b86e1-8f86-44b3-8134-7dce07159a00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764537874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1764537874
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3679434396
Short name T162
Test name
Test status
Simulation time 38309114 ps
CPU time 2.03 seconds
Started Aug 12 04:40:17 PM PDT 24
Finished Aug 12 04:40:19 PM PDT 24
Peak memory 209836 kb
Host smart-97c66715-5284-44f0-b97e-fb8a4f08d214
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679434396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3679434396
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2397323789
Short name T195
Test name
Test status
Simulation time 425893294 ps
CPU time 1.76 seconds
Started Aug 12 04:40:12 PM PDT 24
Finished Aug 12 04:40:14 PM PDT 24
Peak memory 209892 kb
Host smart-433e279a-d301-46b0-ae29-ec42378c9ba6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397323789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2397323789
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2766678707
Short name T197
Test name
Test status
Simulation time 53724169 ps
CPU time 0.93 seconds
Started Aug 12 04:40:11 PM PDT 24
Finished Aug 12 04:40:12 PM PDT 24
Peak memory 210312 kb
Host smart-459b021c-a71b-4018-9723-5344eef323be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766678707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2766678707
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1542086394
Short name T927
Test name
Test status
Simulation time 147144001 ps
CPU time 1.46 seconds
Started Aug 12 04:40:20 PM PDT 24
Finished Aug 12 04:40:22 PM PDT 24
Peak memory 219736 kb
Host smart-53405741-e313-4804-90e2-c075e3a5a625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542086394 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1542086394
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2310715446
Short name T883
Test name
Test status
Simulation time 32853665 ps
CPU time 0.95 seconds
Started Aug 12 04:40:14 PM PDT 24
Finished Aug 12 04:40:15 PM PDT 24
Peak memory 209860 kb
Host smart-43d4ea94-d0c0-4757-ac6b-0a1862f36872
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310715446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2310715446
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.448111103
Short name T892
Test name
Test status
Simulation time 276840445 ps
CPU time 1.87 seconds
Started Aug 12 04:40:13 PM PDT 24
Finished Aug 12 04:40:15 PM PDT 24
Peak memory 209828 kb
Host smart-e6e80714-37f0-4920-a203-a0d18dd10ca7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448111103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.448111103
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.159844981
Short name T144
Test name
Test status
Simulation time 265340456 ps
CPU time 6.69 seconds
Started Aug 12 04:40:12 PM PDT 24
Finished Aug 12 04:40:19 PM PDT 24
Peak memory 209636 kb
Host smart-e2273822-9a69-4486-8d85-0d14a58b587d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159844981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.159844981
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.723912881
Short name T929
Test name
Test status
Simulation time 1781151327 ps
CPU time 41.56 seconds
Started Aug 12 04:40:15 PM PDT 24
Finished Aug 12 04:40:56 PM PDT 24
Peak memory 209736 kb
Host smart-d5dc281d-054a-41df-a0c9-1388f647120c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723912881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.723912881
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.431545351
Short name T145
Test name
Test status
Simulation time 96036283 ps
CPU time 3.18 seconds
Started Aug 12 04:40:13 PM PDT 24
Finished Aug 12 04:40:17 PM PDT 24
Peak memory 211628 kb
Host smart-f7d372fa-6c59-4225-92e7-bac501070b7e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431545351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.431545351
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3104108582
Short name T185
Test name
Test status
Simulation time 304764612 ps
CPU time 3.85 seconds
Started Aug 12 04:40:11 PM PDT 24
Finished Aug 12 04:40:15 PM PDT 24
Peak memory 219464 kb
Host smart-e66b8a34-c292-4b81-a384-6136c00b5567
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310410
8582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3104108582
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1228379336
Short name T142
Test name
Test status
Simulation time 857633779 ps
CPU time 3.75 seconds
Started Aug 12 04:40:15 PM PDT 24
Finished Aug 12 04:40:19 PM PDT 24
Peak memory 209872 kb
Host smart-818f2bc2-a323-458c-974b-6ef50bbae744
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228379336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1228379336
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4211054538
Short name T964
Test name
Test status
Simulation time 22376781 ps
CPU time 1.19 seconds
Started Aug 12 04:40:16 PM PDT 24
Finished Aug 12 04:40:17 PM PDT 24
Peak memory 211924 kb
Host smart-8504d2cb-24d1-482b-8de3-135b493e6786
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211054538 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.4211054538
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2450337711
Short name T897
Test name
Test status
Simulation time 195122184 ps
CPU time 1.51 seconds
Started Aug 12 04:40:20 PM PDT 24
Finished Aug 12 04:40:22 PM PDT 24
Peak memory 211960 kb
Host smart-e7322cd1-59d2-44ea-8fb4-fe0c4848d32c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450337711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2450337711
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.303809483
Short name T119
Test name
Test status
Simulation time 270753781 ps
CPU time 3.35 seconds
Started Aug 12 04:40:14 PM PDT 24
Finished Aug 12 04:40:17 PM PDT 24
Peak memory 218016 kb
Host smart-7b31e16e-0088-49f0-b7ca-66eb931a4a24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303809483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.303809483
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3832465208
Short name T191
Test name
Test status
Simulation time 14773606 ps
CPU time 1.18 seconds
Started Aug 12 04:40:18 PM PDT 24
Finished Aug 12 04:40:20 PM PDT 24
Peak memory 209940 kb
Host smart-ccb9fcf7-49a3-4e6c-a683-20ccc541026c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832465208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.3832465208
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3037113896
Short name T947
Test name
Test status
Simulation time 92809762 ps
CPU time 1.53 seconds
Started Aug 12 04:40:23 PM PDT 24
Finished Aug 12 04:40:25 PM PDT 24
Peak memory 209688 kb
Host smart-1c9727ef-e735-4dfa-98a6-a34a6ac326f2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037113896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3037113896
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.800754596
Short name T996
Test name
Test status
Simulation time 24166921 ps
CPU time 1.15 seconds
Started Aug 12 04:40:20 PM PDT 24
Finished Aug 12 04:40:22 PM PDT 24
Peak memory 219848 kb
Host smart-c4392c5b-2151-48de-a151-1de7402e8a27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800754596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.800754596
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2565153729
Short name T975
Test name
Test status
Simulation time 43113600 ps
CPU time 1.5 seconds
Started Aug 12 04:40:19 PM PDT 24
Finished Aug 12 04:40:21 PM PDT 24
Peak memory 223260 kb
Host smart-919ddc55-c309-4a09-828e-047208b6dc60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565153729 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2565153729
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2059493325
Short name T969
Test name
Test status
Simulation time 13725403 ps
CPU time 0.98 seconds
Started Aug 12 04:40:20 PM PDT 24
Finished Aug 12 04:40:22 PM PDT 24
Peak memory 209916 kb
Host smart-33a49052-7f99-467b-b457-4bec2f261b4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059493325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2059493325
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1781497221
Short name T910
Test name
Test status
Simulation time 97141429 ps
CPU time 2.84 seconds
Started Aug 12 04:40:19 PM PDT 24
Finished Aug 12 04:40:22 PM PDT 24
Peak memory 209076 kb
Host smart-d1438bfa-2c1f-4583-b954-d209a6593864
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781497221 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1781497221
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2278988483
Short name T146
Test name
Test status
Simulation time 193314627 ps
CPU time 5.27 seconds
Started Aug 12 04:40:22 PM PDT 24
Finished Aug 12 04:40:27 PM PDT 24
Peak memory 209692 kb
Host smart-647d4b90-a92c-416e-9374-3c7bfe1e0d8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278988483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2278988483
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1466924708
Short name T995
Test name
Test status
Simulation time 3999575517 ps
CPU time 23.71 seconds
Started Aug 12 04:40:18 PM PDT 24
Finished Aug 12 04:40:41 PM PDT 24
Peak memory 209828 kb
Host smart-91a0e717-e34d-4560-b578-00e3f70e221f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466924708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1466924708
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2480556430
Short name T984
Test name
Test status
Simulation time 672423444 ps
CPU time 2.05 seconds
Started Aug 12 04:40:20 PM PDT 24
Finished Aug 12 04:40:22 PM PDT 24
Peak memory 211348 kb
Host smart-eb21ce48-10c6-4022-bf6e-272776e35092
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480556430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2480556430
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3882303718
Short name T931
Test name
Test status
Simulation time 339788980 ps
CPU time 1.6 seconds
Started Aug 12 04:40:19 PM PDT 24
Finished Aug 12 04:40:21 PM PDT 24
Peak memory 219240 kb
Host smart-60f8f10b-96ff-4c5f-b3ad-fc167a42ce58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388230
3718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3882303718
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.806066389
Short name T143
Test name
Test status
Simulation time 174510087 ps
CPU time 1.11 seconds
Started Aug 12 04:40:17 PM PDT 24
Finished Aug 12 04:40:19 PM PDT 24
Peak memory 209828 kb
Host smart-9cc24170-e705-4067-b807-2b2e522eac4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806066389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.806066389
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.792556810
Short name T997
Test name
Test status
Simulation time 88448220 ps
CPU time 0.95 seconds
Started Aug 12 04:40:23 PM PDT 24
Finished Aug 12 04:40:24 PM PDT 24
Peak memory 209832 kb
Host smart-496c6103-6062-45b0-95ed-6978d29ceec1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792556810 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.792556810
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.162526999
Short name T981
Test name
Test status
Simulation time 24806977 ps
CPU time 1.05 seconds
Started Aug 12 04:40:21 PM PDT 24
Finished Aug 12 04:40:23 PM PDT 24
Peak memory 209916 kb
Host smart-390a170d-7b3e-441b-8b8b-31140215f905
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162526999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.162526999
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.814767970
Short name T937
Test name
Test status
Simulation time 177032615 ps
CPU time 2.86 seconds
Started Aug 12 04:40:21 PM PDT 24
Finished Aug 12 04:40:24 PM PDT 24
Peak memory 218948 kb
Host smart-9c5ade35-2840-494c-a778-24bd802e1f49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814767970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.814767970
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1167977903
Short name T106
Test name
Test status
Simulation time 61313559 ps
CPU time 2.63 seconds
Started Aug 12 04:40:22 PM PDT 24
Finished Aug 12 04:40:24 PM PDT 24
Peak memory 218076 kb
Host smart-636d98b5-5126-4e28-b4b4-26f369e31597
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167977903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1167977903
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3142534161
Short name T943
Test name
Test status
Simulation time 75083721 ps
CPU time 1.15 seconds
Started Aug 12 04:40:17 PM PDT 24
Finished Aug 12 04:40:19 PM PDT 24
Peak memory 218200 kb
Host smart-a6f7e82b-cfe2-46be-8159-0aa78f997ea8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142534161 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3142534161
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3779323907
Short name T946
Test name
Test status
Simulation time 14291119 ps
CPU time 0.82 seconds
Started Aug 12 04:40:21 PM PDT 24
Finished Aug 12 04:40:22 PM PDT 24
Peak memory 209676 kb
Host smart-5110756b-32ca-4176-ae85-9610e7f6e1a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779323907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3779323907
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3540866721
Short name T976
Test name
Test status
Simulation time 99822618 ps
CPU time 1.1 seconds
Started Aug 12 04:40:18 PM PDT 24
Finished Aug 12 04:40:19 PM PDT 24
Peak memory 209776 kb
Host smart-09710a62-2cda-4eec-adef-d06ddee83dd0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540866721 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3540866721
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3797126610
Short name T971
Test name
Test status
Simulation time 1619860280 ps
CPU time 9.23 seconds
Started Aug 12 04:40:19 PM PDT 24
Finished Aug 12 04:40:29 PM PDT 24
Peak memory 209692 kb
Host smart-fb5645f8-67fa-42b0-9cf0-f55b92aa45bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797126610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3797126610
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3768139054
Short name T973
Test name
Test status
Simulation time 1243077399 ps
CPU time 12.71 seconds
Started Aug 12 04:40:19 PM PDT 24
Finished Aug 12 04:40:32 PM PDT 24
Peak memory 209828 kb
Host smart-08df8065-402e-4ab3-8211-45a003dd56cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768139054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3768139054
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3629730684
Short name T916
Test name
Test status
Simulation time 77981284 ps
CPU time 2.61 seconds
Started Aug 12 04:40:19 PM PDT 24
Finished Aug 12 04:40:22 PM PDT 24
Peak memory 211316 kb
Host smart-3a339daa-29ce-4d2c-83f1-c37afadfd405
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629730684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3629730684
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3901652792
Short name T902
Test name
Test status
Simulation time 52165223 ps
CPU time 1.52 seconds
Started Aug 12 04:40:22 PM PDT 24
Finished Aug 12 04:40:24 PM PDT 24
Peak memory 219160 kb
Host smart-2e8be1c9-3f2f-4939-b82f-57a90ee88e2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390165
2792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3901652792
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1290517335
Short name T977
Test name
Test status
Simulation time 88554677 ps
CPU time 2.51 seconds
Started Aug 12 04:40:21 PM PDT 24
Finished Aug 12 04:40:24 PM PDT 24
Peak memory 209132 kb
Host smart-2520c644-f5b0-4b8e-8695-0c63d589c238
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290517335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1290517335
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1357387475
Short name T917
Test name
Test status
Simulation time 67712149 ps
CPU time 1.18 seconds
Started Aug 12 04:40:22 PM PDT 24
Finished Aug 12 04:40:23 PM PDT 24
Peak memory 209852 kb
Host smart-dbbcb5c9-7045-453f-ad72-ba80d966c69e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357387475 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1357387475
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.608494523
Short name T202
Test name
Test status
Simulation time 22261229 ps
CPU time 1.06 seconds
Started Aug 12 04:40:20 PM PDT 24
Finished Aug 12 04:40:22 PM PDT 24
Peak memory 209900 kb
Host smart-e1affeac-7d1a-467c-85df-bd64079ddde7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608494523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.608494523
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1203179842
Short name T960
Test name
Test status
Simulation time 937145685 ps
CPU time 2.8 seconds
Started Aug 12 04:40:19 PM PDT 24
Finished Aug 12 04:40:22 PM PDT 24
Peak memory 219048 kb
Host smart-57037743-6796-4884-b1a5-0f2cf9821ac2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203179842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1203179842
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.274282024
Short name T112
Test name
Test status
Simulation time 46662771 ps
CPU time 1.69 seconds
Started Aug 12 04:40:17 PM PDT 24
Finished Aug 12 04:40:18 PM PDT 24
Peak memory 222120 kb
Host smart-4510e5a6-f4d3-44b7-80c4-aef6e9b078b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274282024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.274282024
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.619067047
Short name T886
Test name
Test status
Simulation time 33949753 ps
CPU time 1.22 seconds
Started Aug 12 04:40:32 PM PDT 24
Finished Aug 12 04:40:34 PM PDT 24
Peak memory 218164 kb
Host smart-9c5ab9f8-73b0-4080-a302-525ec47e22df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619067047 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.619067047
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3463559993
Short name T192
Test name
Test status
Simulation time 50921090 ps
CPU time 0.99 seconds
Started Aug 12 04:40:19 PM PDT 24
Finished Aug 12 04:40:20 PM PDT 24
Peak memory 209812 kb
Host smart-37952b58-8575-47a4-b486-06390c637424
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463559993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3463559993
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1298263959
Short name T885
Test name
Test status
Simulation time 152443789 ps
CPU time 1.61 seconds
Started Aug 12 04:40:18 PM PDT 24
Finished Aug 12 04:40:20 PM PDT 24
Peak memory 209824 kb
Host smart-9d559875-a18d-4de2-bd21-d4047261e6f7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298263959 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1298263959
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.249172861
Short name T985
Test name
Test status
Simulation time 1538629014 ps
CPU time 7.75 seconds
Started Aug 12 04:40:24 PM PDT 24
Finished Aug 12 04:40:32 PM PDT 24
Peak memory 209636 kb
Host smart-d36467de-2d1a-4145-ba6c-d6876beeaef8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249172861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.249172861
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2025240889
Short name T948
Test name
Test status
Simulation time 18943230165 ps
CPU time 18.31 seconds
Started Aug 12 04:40:23 PM PDT 24
Finished Aug 12 04:40:42 PM PDT 24
Peak memory 209868 kb
Host smart-9f528388-8aba-43a6-b745-3389a95a6df0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025240889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2025240889
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.765651152
Short name T974
Test name
Test status
Simulation time 59625496 ps
CPU time 1.4 seconds
Started Aug 12 04:40:22 PM PDT 24
Finished Aug 12 04:40:23 PM PDT 24
Peak memory 211308 kb
Host smart-de0b60f3-5186-43e3-a6bb-0fffd35fbab4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765651152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.765651152
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2992425029
Short name T941
Test name
Test status
Simulation time 207439494 ps
CPU time 3.15 seconds
Started Aug 12 04:40:18 PM PDT 24
Finished Aug 12 04:40:22 PM PDT 24
Peak memory 218700 kb
Host smart-05044eb7-5055-4079-85ff-a1fdf2b3600b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299242
5029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2992425029
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.249439948
Short name T966
Test name
Test status
Simulation time 58624149 ps
CPU time 1.91 seconds
Started Aug 12 04:40:17 PM PDT 24
Finished Aug 12 04:40:19 PM PDT 24
Peak memory 209856 kb
Host smart-0dac168d-4ea7-4683-a6bb-35ee11a3c0fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249439948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.249439948
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4188917781
Short name T950
Test name
Test status
Simulation time 16521980 ps
CPU time 1 seconds
Started Aug 12 04:40:18 PM PDT 24
Finished Aug 12 04:40:20 PM PDT 24
Peak memory 209816 kb
Host smart-756304f5-562a-4f1b-9a6a-c2dfd830cba5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188917781 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.4188917781
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.8939324
Short name T938
Test name
Test status
Simulation time 125848283 ps
CPU time 1.12 seconds
Started Aug 12 04:40:34 PM PDT 24
Finished Aug 12 04:40:35 PM PDT 24
Peak memory 209844 kb
Host smart-8919caa0-502a-45f1-b83f-e8109448f527
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8939324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sa
me_csr_outstanding.8939324
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2979830709
Short name T986
Test name
Test status
Simulation time 27085169 ps
CPU time 1.76 seconds
Started Aug 12 04:40:21 PM PDT 24
Finished Aug 12 04:40:23 PM PDT 24
Peak memory 218204 kb
Host smart-4a2546b6-bf67-4b36-aedb-fe2def32b767
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979830709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2979830709
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3888420807
Short name T133
Test name
Test status
Simulation time 128647111 ps
CPU time 2.86 seconds
Started Aug 12 04:40:22 PM PDT 24
Finished Aug 12 04:40:25 PM PDT 24
Peak memory 222652 kb
Host smart-4c7c4f2f-f0ea-4b98-adfc-493ac3813d46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888420807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3888420807
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3053821374
Short name T906
Test name
Test status
Simulation time 24962673 ps
CPU time 1.57 seconds
Started Aug 12 04:40:29 PM PDT 24
Finished Aug 12 04:40:31 PM PDT 24
Peak memory 218092 kb
Host smart-5d13c3ca-d5b9-416d-b81b-f7af93988993
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053821374 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3053821374
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2934754837
Short name T972
Test name
Test status
Simulation time 16755054 ps
CPU time 0.79 seconds
Started Aug 12 04:40:36 PM PDT 24
Finished Aug 12 04:40:37 PM PDT 24
Peak memory 209668 kb
Host smart-6da6ca87-5cfe-4b52-aca7-74c5562196c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934754837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2934754837
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3260562452
Short name T914
Test name
Test status
Simulation time 114428774 ps
CPU time 1.2 seconds
Started Aug 12 04:40:31 PM PDT 24
Finished Aug 12 04:40:32 PM PDT 24
Peak memory 209792 kb
Host smart-ba5fdb4b-ed32-4673-b27a-e1228c3b1301
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260562452 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3260562452
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.14884629
Short name T949
Test name
Test status
Simulation time 3183572028 ps
CPU time 7.59 seconds
Started Aug 12 04:40:31 PM PDT 24
Finished Aug 12 04:40:39 PM PDT 24
Peak memory 209240 kb
Host smart-ade0dd2e-97ac-49a6-8d12-10dcbfd71c9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14884629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.lc_ctrl_jtag_csr_aliasing.14884629
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.810992140
Short name T935
Test name
Test status
Simulation time 1111064408 ps
CPU time 20.96 seconds
Started Aug 12 04:40:31 PM PDT 24
Finished Aug 12 04:40:52 PM PDT 24
Peak memory 209700 kb
Host smart-9b32a4cf-043e-482e-94fb-3e4c2a31c8b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810992140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.810992140
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3966072973
Short name T893
Test name
Test status
Simulation time 49184367 ps
CPU time 1.25 seconds
Started Aug 12 04:40:31 PM PDT 24
Finished Aug 12 04:40:32 PM PDT 24
Peak memory 209892 kb
Host smart-cc850ee2-e112-42dd-b1f9-21bdefb8e227
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966072973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3966072973
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1956002165
Short name T184
Test name
Test status
Simulation time 322025644 ps
CPU time 2.19 seconds
Started Aug 12 04:40:36 PM PDT 24
Finished Aug 12 04:40:39 PM PDT 24
Peak memory 218164 kb
Host smart-5589197d-c454-49a9-abaa-f9c8ae58fc0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195600
2165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1956002165
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.427174633
Short name T989
Test name
Test status
Simulation time 979062011 ps
CPU time 3.13 seconds
Started Aug 12 04:40:31 PM PDT 24
Finished Aug 12 04:40:34 PM PDT 24
Peak memory 209904 kb
Host smart-ef089491-ba24-4bf1-8d05-9911cdfb2a3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427174633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.427174633
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4158493543
Short name T920
Test name
Test status
Simulation time 110460663 ps
CPU time 1.19 seconds
Started Aug 12 04:40:31 PM PDT 24
Finished Aug 12 04:40:33 PM PDT 24
Peak memory 210012 kb
Host smart-4fd6fb0c-f3a8-4231-8772-3e24c0ed867d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158493543 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.4158493543
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3487740284
Short name T205
Test name
Test status
Simulation time 71593651 ps
CPU time 1.04 seconds
Started Aug 12 04:40:33 PM PDT 24
Finished Aug 12 04:40:34 PM PDT 24
Peak memory 209940 kb
Host smart-9871957b-ecb4-431b-834c-5fc0583ad53f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487740284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3487740284
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4252851276
Short name T930
Test name
Test status
Simulation time 207805432 ps
CPU time 2.99 seconds
Started Aug 12 04:40:34 PM PDT 24
Finished Aug 12 04:40:37 PM PDT 24
Peak memory 218888 kb
Host smart-ef050e48-e977-4b85-a661-4cef2740bbe3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252851276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.4252851276
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.759889259
Short name T127
Test name
Test status
Simulation time 79556866 ps
CPU time 3.21 seconds
Started Aug 12 04:40:29 PM PDT 24
Finished Aug 12 04:40:33 PM PDT 24
Peak memory 222484 kb
Host smart-2f13014f-a512-4af7-94ec-8cde71252804
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759889259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.759889259
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4160903365
Short name T923
Test name
Test status
Simulation time 32939591 ps
CPU time 1.41 seconds
Started Aug 12 04:40:30 PM PDT 24
Finished Aug 12 04:40:31 PM PDT 24
Peak memory 219920 kb
Host smart-c4d19616-da59-453a-a318-0cc33209e61f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160903365 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.4160903365
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.884156088
Short name T201
Test name
Test status
Simulation time 12916562 ps
CPU time 0.89 seconds
Started Aug 12 04:40:29 PM PDT 24
Finished Aug 12 04:40:30 PM PDT 24
Peak memory 209856 kb
Host smart-7dc2e3d0-3e89-4ed3-88dc-9581e4e01551
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884156088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.884156088
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.751333098
Short name T884
Test name
Test status
Simulation time 58608785 ps
CPU time 1.99 seconds
Started Aug 12 04:40:32 PM PDT 24
Finished Aug 12 04:40:35 PM PDT 24
Peak memory 209808 kb
Host smart-5fac93bc-4be0-442a-bfd9-166911b3d92f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751333098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.751333098
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1725577482
Short name T982
Test name
Test status
Simulation time 1843253086 ps
CPU time 4.53 seconds
Started Aug 12 04:40:32 PM PDT 24
Finished Aug 12 04:40:37 PM PDT 24
Peak memory 209708 kb
Host smart-dde71007-d508-4554-a7a7-04d7fd348f01
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725577482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1725577482
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3510317472
Short name T979
Test name
Test status
Simulation time 1866600362 ps
CPU time 9.14 seconds
Started Aug 12 04:40:34 PM PDT 24
Finished Aug 12 04:40:43 PM PDT 24
Peak memory 209132 kb
Host smart-88319b4d-cfb2-420e-8735-c32b57e4a219
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510317472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3510317472
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.784776884
Short name T888
Test name
Test status
Simulation time 581064880 ps
CPU time 2.69 seconds
Started Aug 12 04:40:31 PM PDT 24
Finished Aug 12 04:40:34 PM PDT 24
Peak memory 211660 kb
Host smart-ef8c9202-59d0-4327-b0f2-045798c9e000
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784776884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.784776884
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2052611343
Short name T991
Test name
Test status
Simulation time 51014226 ps
CPU time 1.83 seconds
Started Aug 12 04:40:31 PM PDT 24
Finished Aug 12 04:40:33 PM PDT 24
Peak memory 220492 kb
Host smart-b31294f3-f044-45af-9cae-c49893832b24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205261
1343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2052611343
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3978895951
Short name T951
Test name
Test status
Simulation time 96335731 ps
CPU time 1.44 seconds
Started Aug 12 04:40:32 PM PDT 24
Finished Aug 12 04:40:34 PM PDT 24
Peak memory 211988 kb
Host smart-331cd650-ddf8-4b84-98eb-8cdc6e3ceeb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978895951 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3978895951
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.232987851
Short name T952
Test name
Test status
Simulation time 65268252 ps
CPU time 1.18 seconds
Started Aug 12 04:40:33 PM PDT 24
Finished Aug 12 04:40:34 PM PDT 24
Peak memory 209684 kb
Host smart-8a1f18cc-9627-4c23-a729-54e0d9753b45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232987851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.232987851
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1931016433
Short name T911
Test name
Test status
Simulation time 67781190 ps
CPU time 1.99 seconds
Started Aug 12 04:40:34 PM PDT 24
Finished Aug 12 04:40:36 PM PDT 24
Peak memory 218064 kb
Host smart-651d61dc-0aa9-4425-8af2-4e8710a42677
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931016433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1931016433
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.86556862
Short name T993
Test name
Test status
Simulation time 43120412 ps
CPU time 1.47 seconds
Started Aug 12 04:40:32 PM PDT 24
Finished Aug 12 04:40:34 PM PDT 24
Peak memory 218232 kb
Host smart-48f518d1-160a-4055-9632-45696ea1855a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86556862 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.86556862
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3860117617
Short name T905
Test name
Test status
Simulation time 283164026 ps
CPU time 0.89 seconds
Started Aug 12 04:40:34 PM PDT 24
Finished Aug 12 04:40:35 PM PDT 24
Peak memory 209896 kb
Host smart-a6a35305-c2e1-42eb-9b56-34de0c6085bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860117617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3860117617
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1454641707
Short name T940
Test name
Test status
Simulation time 53426045 ps
CPU time 1.03 seconds
Started Aug 12 04:40:35 PM PDT 24
Finished Aug 12 04:40:36 PM PDT 24
Peak memory 209848 kb
Host smart-e7fd8656-9f29-4018-83fa-82f0d8d868e8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454641707 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1454641707
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2811529139
Short name T987
Test name
Test status
Simulation time 3148099216 ps
CPU time 4.68 seconds
Started Aug 12 04:40:28 PM PDT 24
Finished Aug 12 04:40:33 PM PDT 24
Peak memory 209916 kb
Host smart-e70cccc0-9a70-42e2-8975-8efc0915aa3e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811529139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2811529139
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.190669841
Short name T891
Test name
Test status
Simulation time 424057399 ps
CPU time 10.97 seconds
Started Aug 12 04:40:31 PM PDT 24
Finished Aug 12 04:40:43 PM PDT 24
Peak memory 209692 kb
Host smart-77a5517c-fcb6-42f0-93e8-3b1a6b8732f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190669841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.190669841
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3879952350
Short name T933
Test name
Test status
Simulation time 197517872 ps
CPU time 1.7 seconds
Started Aug 12 04:40:29 PM PDT 24
Finished Aug 12 04:40:31 PM PDT 24
Peak memory 211608 kb
Host smart-ad47af59-0a75-4186-855d-2adc7900ade9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879952350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3879952350
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2233298815
Short name T915
Test name
Test status
Simulation time 101825469 ps
CPU time 2.89 seconds
Started Aug 12 04:40:29 PM PDT 24
Finished Aug 12 04:40:32 PM PDT 24
Peak memory 218164 kb
Host smart-8458722b-cbf5-42a9-8eba-987caf14fa5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223329
8815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2233298815
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.4186929933
Short name T901
Test name
Test status
Simulation time 132983468 ps
CPU time 1.26 seconds
Started Aug 12 04:40:31 PM PDT 24
Finished Aug 12 04:40:33 PM PDT 24
Peak memory 209784 kb
Host smart-aa14cfa7-ab89-47a3-9e84-e908512dfd14
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186929933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.4186929933
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1848123220
Short name T990
Test name
Test status
Simulation time 333235202 ps
CPU time 2.02 seconds
Started Aug 12 04:40:34 PM PDT 24
Finished Aug 12 04:40:36 PM PDT 24
Peak memory 212056 kb
Host smart-decfc6d5-92d8-468f-b1cc-3c1f61f4b373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848123220 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1848123220
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4096024411
Short name T994
Test name
Test status
Simulation time 37614625 ps
CPU time 1.42 seconds
Started Aug 12 04:40:31 PM PDT 24
Finished Aug 12 04:40:33 PM PDT 24
Peak memory 211904 kb
Host smart-4ec257fa-2200-4da2-90cd-52f40114c941
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096024411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.4096024411
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1677552336
Short name T115
Test name
Test status
Simulation time 52475231 ps
CPU time 2.42 seconds
Started Aug 12 04:40:32 PM PDT 24
Finished Aug 12 04:40:35 PM PDT 24
Peak memory 218020 kb
Host smart-5af7359a-ad8a-4c48-bda1-32462319ea6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677552336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1677552336
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4189823311
Short name T131
Test name
Test status
Simulation time 153554224 ps
CPU time 3.53 seconds
Started Aug 12 04:40:33 PM PDT 24
Finished Aug 12 04:40:36 PM PDT 24
Peak memory 222704 kb
Host smart-e14912cd-aadc-4efb-a2e7-ab062078172b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189823311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.4189823311
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2968455680
Short name T235
Test name
Test status
Simulation time 47170210 ps
CPU time 0.95 seconds
Started Aug 12 04:56:05 PM PDT 24
Finished Aug 12 04:56:06 PM PDT 24
Peak memory 209112 kb
Host smart-ec24ab95-63dc-44dd-abc9-c32d5ee0d55d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968455680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2968455680
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3233571888
Short name T598
Test name
Test status
Simulation time 1333200299 ps
CPU time 13.85 seconds
Started Aug 12 04:56:03 PM PDT 24
Finished Aug 12 04:56:17 PM PDT 24
Peak memory 218436 kb
Host smart-2747834d-6e01-4e3c-a441-d6f7d6507ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233571888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3233571888
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.425353967
Short name T159
Test name
Test status
Simulation time 1498504319 ps
CPU time 3.04 seconds
Started Aug 12 04:56:05 PM PDT 24
Finished Aug 12 04:56:08 PM PDT 24
Peak memory 217216 kb
Host smart-aa02df2f-3234-4fd3-9803-953d22e500fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425353967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.425353967
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1714765346
Short name T683
Test name
Test status
Simulation time 3828870887 ps
CPU time 34.89 seconds
Started Aug 12 04:56:07 PM PDT 24
Finished Aug 12 04:56:42 PM PDT 24
Peak memory 218996 kb
Host smart-bba94fd9-2525-481c-a659-517e85922664
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714765346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1714765346
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1993342954
Short name T259
Test name
Test status
Simulation time 372364753 ps
CPU time 5.61 seconds
Started Aug 12 04:56:03 PM PDT 24
Finished Aug 12 04:56:09 PM PDT 24
Peak memory 217788 kb
Host smart-78c01692-fcd0-4e30-b5f1-bbf3b3bb5258
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993342954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
993342954
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1887788130
Short name T18
Test name
Test status
Simulation time 579593094 ps
CPU time 5.44 seconds
Started Aug 12 04:56:04 PM PDT 24
Finished Aug 12 04:56:09 PM PDT 24
Peak memory 222216 kb
Host smart-98fb0266-a13d-4bbe-850c-5337c120669a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887788130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1887788130
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2697497471
Short name T526
Test name
Test status
Simulation time 1289550316 ps
CPU time 40.39 seconds
Started Aug 12 04:56:03 PM PDT 24
Finished Aug 12 04:56:43 PM PDT 24
Peak memory 217696 kb
Host smart-d487a2d3-b76d-43cf-a77a-fd39126342fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697497471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2697497471
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2073843681
Short name T509
Test name
Test status
Simulation time 610669092 ps
CPU time 4.24 seconds
Started Aug 12 04:56:04 PM PDT 24
Finished Aug 12 04:56:08 PM PDT 24
Peak memory 217732 kb
Host smart-7fb7cf6f-2fb3-49fe-8229-49eef88288f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073843681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2073843681
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2728415362
Short name T228
Test name
Test status
Simulation time 1965380407 ps
CPU time 72.66 seconds
Started Aug 12 04:56:03 PM PDT 24
Finished Aug 12 04:57:15 PM PDT 24
Peak memory 267468 kb
Host smart-6c2f4a6f-f09a-4d84-83fa-0dc965100fd6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728415362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2728415362
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2771504862
Short name T680
Test name
Test status
Simulation time 328149563 ps
CPU time 15.38 seconds
Started Aug 12 04:56:03 PM PDT 24
Finished Aug 12 04:56:18 PM PDT 24
Peak memory 250956 kb
Host smart-613d9b63-ed6f-43e0-bdd0-3b658fc6305c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771504862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2771504862
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.805742817
Short name T724
Test name
Test status
Simulation time 795040800 ps
CPU time 5.66 seconds
Started Aug 12 04:56:05 PM PDT 24
Finished Aug 12 04:56:11 PM PDT 24
Peak memory 218400 kb
Host smart-2dc90cd4-98cb-4909-8d00-1df8bbf47c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805742817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.805742817
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2845223785
Short name T799
Test name
Test status
Simulation time 518998222 ps
CPU time 23.98 seconds
Started Aug 12 04:56:05 PM PDT 24
Finished Aug 12 04:56:29 PM PDT 24
Peak memory 214948 kb
Host smart-2153d9d9-c6b3-4fd7-bbc3-74e82cdfc7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845223785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2845223785
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3297888393
Short name T635
Test name
Test status
Simulation time 1495347356 ps
CPU time 16.69 seconds
Started Aug 12 04:56:06 PM PDT 24
Finished Aug 12 04:56:23 PM PDT 24
Peak memory 219040 kb
Host smart-c07f0902-3949-4131-bdcd-54fda4eff53c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297888393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3297888393
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1729083563
Short name T267
Test name
Test status
Simulation time 1262693015 ps
CPU time 10.64 seconds
Started Aug 12 04:56:03 PM PDT 24
Finished Aug 12 04:56:13 PM PDT 24
Peak memory 226156 kb
Host smart-b5036814-6cdb-4ca6-9bd7-7cea823f2c04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729083563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1729083563
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3140141638
Short name T468
Test name
Test status
Simulation time 881728371 ps
CPU time 6.58 seconds
Started Aug 12 04:56:03 PM PDT 24
Finished Aug 12 04:56:10 PM PDT 24
Peak memory 226276 kb
Host smart-d01747c7-a43a-4fbf-abdc-d76d6e88396d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140141638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
140141638
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3077199671
Short name T588
Test name
Test status
Simulation time 257131713 ps
CPU time 10.99 seconds
Started Aug 12 04:56:02 PM PDT 24
Finished Aug 12 04:56:13 PM PDT 24
Peak memory 226276 kb
Host smart-b5a93d98-d005-48cd-a1b6-1f0282733bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077199671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3077199671
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1001736897
Short name T844
Test name
Test status
Simulation time 263758319 ps
CPU time 3.14 seconds
Started Aug 12 04:56:04 PM PDT 24
Finished Aug 12 04:56:07 PM PDT 24
Peak memory 215040 kb
Host smart-350090d9-a851-4b47-bb18-ede5ca378195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001736897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1001736897
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1268768718
Short name T728
Test name
Test status
Simulation time 820341307 ps
CPU time 29.6 seconds
Started Aug 12 04:56:06 PM PDT 24
Finished Aug 12 04:56:36 PM PDT 24
Peak memory 245208 kb
Host smart-ff6fe598-8f2a-4a96-9ba1-948929e085c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268768718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1268768718
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2128771813
Short name T554
Test name
Test status
Simulation time 64036218 ps
CPU time 6.94 seconds
Started Aug 12 04:56:02 PM PDT 24
Finished Aug 12 04:56:09 PM PDT 24
Peak memory 250592 kb
Host smart-42a35243-e7df-45bd-bd51-4235d5184008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128771813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2128771813
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.4244542275
Short name T315
Test name
Test status
Simulation time 9906361847 ps
CPU time 277.82 seconds
Started Aug 12 04:56:06 PM PDT 24
Finished Aug 12 05:00:44 PM PDT 24
Peak memory 267564 kb
Host smart-90cfeffd-43ec-460b-b3f3-9e6eddfcf8e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244542275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.4244542275
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1716405900
Short name T388
Test name
Test status
Simulation time 17429227 ps
CPU time 0.76 seconds
Started Aug 12 04:56:01 PM PDT 24
Finished Aug 12 04:56:02 PM PDT 24
Peak memory 208888 kb
Host smart-c003d310-6e3e-4430-8ee7-ed40787c450a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716405900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1716405900
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1277600299
Short name T83
Test name
Test status
Simulation time 14774013 ps
CPU time 1.06 seconds
Started Aug 12 04:56:12 PM PDT 24
Finished Aug 12 04:56:13 PM PDT 24
Peak memory 209036 kb
Host smart-ad9281a5-849d-4e8f-8f5f-df0c224824bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277600299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1277600299
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2040855920
Short name T571
Test name
Test status
Simulation time 26322497 ps
CPU time 0.86 seconds
Started Aug 12 04:56:09 PM PDT 24
Finished Aug 12 04:56:10 PM PDT 24
Peak memory 208752 kb
Host smart-32a01778-dcf8-435a-91ea-e5799c399294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040855920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2040855920
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2138776903
Short name T375
Test name
Test status
Simulation time 2944532213 ps
CPU time 17.38 seconds
Started Aug 12 04:56:10 PM PDT 24
Finished Aug 12 04:56:28 PM PDT 24
Peak memory 218476 kb
Host smart-e5fad71a-f730-4d61-bdb3-e49abeacfb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138776903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2138776903
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3594146587
Short name T748
Test name
Test status
Simulation time 11888112611 ps
CPU time 70.5 seconds
Started Aug 12 04:56:10 PM PDT 24
Finished Aug 12 04:57:20 PM PDT 24
Peak memory 218780 kb
Host smart-d2869aa3-c004-491f-9f59-b86c62b4a245
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594146587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3594146587
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2677944668
Short name T776
Test name
Test status
Simulation time 6893538860 ps
CPU time 15.76 seconds
Started Aug 12 04:56:10 PM PDT 24
Finished Aug 12 04:56:26 PM PDT 24
Peak memory 217860 kb
Host smart-be7c1fdd-55c0-47a2-ab68-2fff86c99771
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677944668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
677944668
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1053848030
Short name T439
Test name
Test status
Simulation time 1664688591 ps
CPU time 7.44 seconds
Started Aug 12 04:56:11 PM PDT 24
Finished Aug 12 04:56:18 PM PDT 24
Peak memory 218304 kb
Host smart-97b22259-345c-4c9f-a83a-b86bd44ee67d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053848030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1053848030
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3203793614
Short name T400
Test name
Test status
Simulation time 4658267446 ps
CPU time 17.11 seconds
Started Aug 12 04:56:10 PM PDT 24
Finished Aug 12 04:56:27 PM PDT 24
Peak memory 217792 kb
Host smart-42048ddc-dc48-4d22-872d-a1ba420c9eec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203793614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3203793614
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.664849635
Short name T525
Test name
Test status
Simulation time 624241260 ps
CPU time 6.49 seconds
Started Aug 12 04:56:11 PM PDT 24
Finished Aug 12 04:56:17 PM PDT 24
Peak memory 217700 kb
Host smart-d0c830d7-326a-44d1-9ca8-75a744b6f78c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664849635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.664849635
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.687364361
Short name T306
Test name
Test status
Simulation time 1840554811 ps
CPU time 72.97 seconds
Started Aug 12 04:56:11 PM PDT 24
Finished Aug 12 04:57:24 PM PDT 24
Peak memory 275664 kb
Host smart-79edaf47-ebff-4362-a493-e8fc5f4192a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687364361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.687364361
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1959715449
Short name T264
Test name
Test status
Simulation time 1298653031 ps
CPU time 13.77 seconds
Started Aug 12 04:56:09 PM PDT 24
Finished Aug 12 04:56:23 PM PDT 24
Peak memory 251004 kb
Host smart-1b970c22-cd0a-4a23-b466-510c93fe0e90
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959715449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1959715449
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2419829383
Short name T338
Test name
Test status
Simulation time 33685669 ps
CPU time 2.5 seconds
Started Aug 12 04:56:05 PM PDT 24
Finished Aug 12 04:56:07 PM PDT 24
Peak memory 218344 kb
Host smart-c5ebcb2f-de86-481b-b1a2-afadfc261dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419829383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2419829383
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2292304351
Short name T729
Test name
Test status
Simulation time 195874147 ps
CPU time 5.16 seconds
Started Aug 12 04:56:09 PM PDT 24
Finished Aug 12 04:56:15 PM PDT 24
Peak memory 222436 kb
Host smart-4c63ea71-d973-4144-a2e6-53a3e6e96737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292304351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2292304351
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1537614665
Short name T90
Test name
Test status
Simulation time 530979937 ps
CPU time 23.12 seconds
Started Aug 12 04:56:09 PM PDT 24
Finished Aug 12 04:56:32 PM PDT 24
Peak memory 268896 kb
Host smart-2507cd10-fe7a-4790-b9e2-424c649abd1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537614665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1537614665
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3401457828
Short name T673
Test name
Test status
Simulation time 248804723 ps
CPU time 11.48 seconds
Started Aug 12 04:56:10 PM PDT 24
Finished Aug 12 04:56:22 PM PDT 24
Peak memory 226152 kb
Host smart-a5e49a81-2206-4703-a242-fe8c8d0b2062
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401457828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3401457828
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2152039492
Short name T247
Test name
Test status
Simulation time 826202400 ps
CPU time 10.04 seconds
Started Aug 12 04:56:10 PM PDT 24
Finished Aug 12 04:56:20 PM PDT 24
Peak memory 226140 kb
Host smart-e291c419-3323-4b5f-aa7a-7c65a364b012
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152039492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2152039492
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.761629230
Short name T457
Test name
Test status
Simulation time 1164293807 ps
CPU time 11.88 seconds
Started Aug 12 04:56:12 PM PDT 24
Finished Aug 12 04:56:24 PM PDT 24
Peak memory 218388 kb
Host smart-8d03577d-2496-4175-b92b-920ce84b957e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761629230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.761629230
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2928496256
Short name T854
Test name
Test status
Simulation time 304431151 ps
CPU time 7.54 seconds
Started Aug 12 04:56:08 PM PDT 24
Finished Aug 12 04:56:16 PM PDT 24
Peak memory 218432 kb
Host smart-ef2fcfd1-cfd4-4207-9297-5de6c33b900e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928496256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2928496256
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1680841461
Short name T368
Test name
Test status
Simulation time 223181491 ps
CPU time 3.37 seconds
Started Aug 12 04:56:06 PM PDT 24
Finished Aug 12 04:56:09 PM PDT 24
Peak memory 217844 kb
Host smart-1854a34b-21fa-4363-83f4-82486d048883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680841461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1680841461
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.187288880
Short name T519
Test name
Test status
Simulation time 741229169 ps
CPU time 20.77 seconds
Started Aug 12 04:56:05 PM PDT 24
Finished Aug 12 04:56:26 PM PDT 24
Peak memory 251024 kb
Host smart-65005a59-9408-40f8-ab97-bf75c12a4bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187288880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.187288880
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1136577598
Short name T464
Test name
Test status
Simulation time 72503905 ps
CPU time 8.83 seconds
Started Aug 12 04:56:08 PM PDT 24
Finished Aug 12 04:56:17 PM PDT 24
Peak memory 250884 kb
Host smart-66b03754-07e5-44f4-ae12-e6124c1ebe65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136577598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1136577598
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.750412792
Short name T491
Test name
Test status
Simulation time 15256296 ps
CPU time 0.87 seconds
Started Aug 12 04:56:04 PM PDT 24
Finished Aug 12 04:56:05 PM PDT 24
Peak memory 209248 kb
Host smart-68f313aa-22fe-4a9c-9753-7c65f85fc254
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750412792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.750412792
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.4228884384
Short name T633
Test name
Test status
Simulation time 41075261 ps
CPU time 0.95 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:01 PM PDT 24
Peak memory 208972 kb
Host smart-25ec7744-1209-41f0-97de-fe015019cde3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228884384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.4228884384
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3708685588
Short name T445
Test name
Test status
Simulation time 1351238290 ps
CPU time 3.92 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:04 PM PDT 24
Peak memory 217804 kb
Host smart-b7e67606-7cd4-448a-8628-aaff07a6e22f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708685588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3708685588
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1759309367
Short name T39
Test name
Test status
Simulation time 1904811473 ps
CPU time 39.97 seconds
Started Aug 12 04:56:59 PM PDT 24
Finished Aug 12 04:57:39 PM PDT 24
Peak memory 218368 kb
Host smart-e8593f91-6ebd-408e-80dc-dc41df3e9845
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759309367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1759309367
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2154467719
Short name T758
Test name
Test status
Simulation time 1137019828 ps
CPU time 9.71 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:10 PM PDT 24
Peak memory 224268 kb
Host smart-0da58f54-baad-49c5-ae60-867f8c431511
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154467719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2154467719
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1338880735
Short name T487
Test name
Test status
Simulation time 398675432 ps
CPU time 6.59 seconds
Started Aug 12 04:56:59 PM PDT 24
Finished Aug 12 04:57:06 PM PDT 24
Peak memory 217716 kb
Host smart-7b8c611f-5696-4b52-bf90-6253ed5154bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338880735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1338880735
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2766314221
Short name T287
Test name
Test status
Simulation time 997522061 ps
CPU time 36.06 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:36 PM PDT 24
Peak memory 250992 kb
Host smart-fda8e916-bd15-40b7-a1ce-477769ab83f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766314221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2766314221
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3691262025
Short name T2
Test name
Test status
Simulation time 765694550 ps
CPU time 26.83 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:27 PM PDT 24
Peak memory 247600 kb
Host smart-5ddf0a36-cf2d-4e48-afb7-9667a67fb87d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691262025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3691262025
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.4004084024
Short name T568
Test name
Test status
Simulation time 111284620 ps
CPU time 1.83 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:02 PM PDT 24
Peak memory 222280 kb
Host smart-81033d72-17ad-43cd-9ce2-facba33eb7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004084024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.4004084024
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1336638713
Short name T757
Test name
Test status
Simulation time 865939129 ps
CPU time 8.28 seconds
Started Aug 12 04:56:59 PM PDT 24
Finished Aug 12 04:57:08 PM PDT 24
Peak memory 226212 kb
Host smart-b19827e1-463a-4bae-b469-02da5b0046af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336638713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1336638713
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1612821616
Short name T410
Test name
Test status
Simulation time 264346168 ps
CPU time 8.31 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:09 PM PDT 24
Peak memory 226156 kb
Host smart-f774839b-1a24-4d36-a97f-279b54975767
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612821616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1612821616
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.663697599
Short name T176
Test name
Test status
Simulation time 368416044 ps
CPU time 8.7 seconds
Started Aug 12 04:57:01 PM PDT 24
Finished Aug 12 04:57:10 PM PDT 24
Peak memory 218356 kb
Host smart-dfd4f6fd-0160-48e9-9319-25b4f6d62683
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663697599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.663697599
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.158659442
Short name T778
Test name
Test status
Simulation time 205578139 ps
CPU time 9.58 seconds
Started Aug 12 04:56:59 PM PDT 24
Finished Aug 12 04:57:09 PM PDT 24
Peak memory 226144 kb
Host smart-cf55f954-7b72-480c-8eed-0b17dbbf9908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158659442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.158659442
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2520681451
Short name T76
Test name
Test status
Simulation time 406133111 ps
CPU time 3.27 seconds
Started Aug 12 04:56:54 PM PDT 24
Finished Aug 12 04:56:57 PM PDT 24
Peak memory 217852 kb
Host smart-020f900a-d51c-4426-9315-9a68ba721c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520681451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2520681451
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.757680438
Short name T441
Test name
Test status
Simulation time 63249000 ps
CPU time 7.6 seconds
Started Aug 12 04:57:03 PM PDT 24
Finished Aug 12 04:57:10 PM PDT 24
Peak memory 251132 kb
Host smart-2e7d9cd7-069d-4bc0-ae73-c3c12ecf4886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757680438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.757680438
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2088758647
Short name T787
Test name
Test status
Simulation time 10546670531 ps
CPU time 225.18 seconds
Started Aug 12 04:57:01 PM PDT 24
Finished Aug 12 05:00:46 PM PDT 24
Peak memory 269020 kb
Host smart-ba9f87ff-1aeb-4880-b942-ee5a047f3f08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088758647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2088758647
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.2225264436
Short name T153
Test name
Test status
Simulation time 5801037845 ps
CPU time 67.63 seconds
Started Aug 12 04:57:02 PM PDT 24
Finished Aug 12 04:58:10 PM PDT 24
Peak memory 260360 kb
Host smart-8dea4d99-6051-4db8-b898-d83951180356
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2225264436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.2225264436
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3019834189
Short name T73
Test name
Test status
Simulation time 37636064 ps
CPU time 1.08 seconds
Started Aug 12 04:56:52 PM PDT 24
Finished Aug 12 04:56:54 PM PDT 24
Peak memory 212024 kb
Host smart-4f121e45-14d1-4bb2-8b76-3f4b2781150a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019834189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3019834189
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3042782845
Short name T716
Test name
Test status
Simulation time 14855996 ps
CPU time 0.86 seconds
Started Aug 12 04:57:07 PM PDT 24
Finished Aug 12 04:57:08 PM PDT 24
Peak memory 208744 kb
Host smart-e54b78c7-02dd-4e62-b474-82993da13817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042782845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3042782845
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.896990629
Short name T696
Test name
Test status
Simulation time 206043907 ps
CPU time 9.82 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:10 PM PDT 24
Peak memory 218364 kb
Host smart-55c7054e-5101-432a-9a59-fa02f74aa171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896990629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.896990629
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1837536243
Short name T781
Test name
Test status
Simulation time 1036034089 ps
CPU time 13.2 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:14 PM PDT 24
Peak memory 217852 kb
Host smart-df665e8a-78da-42e0-ac74-c8aa3edfb4e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837536243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1837536243
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1350614017
Short name T632
Test name
Test status
Simulation time 7352225255 ps
CPU time 58.08 seconds
Started Aug 12 04:57:02 PM PDT 24
Finished Aug 12 04:58:00 PM PDT 24
Peak memory 218980 kb
Host smart-01494ea1-8f86-4eda-8cba-feaf7d48d9d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350614017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1350614017
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2281605496
Short name T761
Test name
Test status
Simulation time 383765361 ps
CPU time 3.31 seconds
Started Aug 12 04:56:59 PM PDT 24
Finished Aug 12 04:57:03 PM PDT 24
Peak memory 218376 kb
Host smart-b1548422-45ff-4b49-9d3c-a07f93b3419c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281605496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2281605496
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2862229137
Short name T689
Test name
Test status
Simulation time 2355129030 ps
CPU time 8.98 seconds
Started Aug 12 04:57:01 PM PDT 24
Finished Aug 12 04:57:11 PM PDT 24
Peak memory 217840 kb
Host smart-ab3f1d32-9d31-4337-9a7f-b22966b42a5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862229137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2862229137
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2064993342
Short name T351
Test name
Test status
Simulation time 1042921614 ps
CPU time 35.06 seconds
Started Aug 12 04:57:01 PM PDT 24
Finished Aug 12 04:57:36 PM PDT 24
Peak memory 251040 kb
Host smart-64ae06d1-59bc-43ef-8069-101c554c6834
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064993342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2064993342
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2682900521
Short name T699
Test name
Test status
Simulation time 701801498 ps
CPU time 10.87 seconds
Started Aug 12 04:57:01 PM PDT 24
Finished Aug 12 04:57:12 PM PDT 24
Peak memory 250564 kb
Host smart-d2c7980b-7263-43d6-82bf-6ccaff402a68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682900521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2682900521
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1069566855
Short name T411
Test name
Test status
Simulation time 224313566 ps
CPU time 3.13 seconds
Started Aug 12 04:56:58 PM PDT 24
Finished Aug 12 04:57:02 PM PDT 24
Peak memory 218384 kb
Host smart-5b499a07-6474-4aa5-8e38-1c3ed747d0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069566855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1069566855
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.4186078512
Short name T94
Test name
Test status
Simulation time 208642825 ps
CPU time 10.09 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:10 PM PDT 24
Peak memory 226180 kb
Host smart-32535f89-d84f-4338-a246-2d9ef6d00577
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186078512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.4186078512
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1586623476
Short name T848
Test name
Test status
Simulation time 371138499 ps
CPU time 13.99 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:15 PM PDT 24
Peak memory 226168 kb
Host smart-9a5797a6-0ec4-4524-ac9a-4802acf681b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586623476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1586623476
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2356972961
Short name T730
Test name
Test status
Simulation time 910567303 ps
CPU time 11.22 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:11 PM PDT 24
Peak memory 226240 kb
Host smart-776772f3-9d34-46e2-87d0-c4fc06b2d6fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356972961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2356972961
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.4289652826
Short name T760
Test name
Test status
Simulation time 2018964210 ps
CPU time 11.57 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:12 PM PDT 24
Peak memory 218488 kb
Host smart-651f7834-e05f-4e7c-b38b-00d265d68e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289652826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.4289652826
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1810015396
Short name T404
Test name
Test status
Simulation time 43146583 ps
CPU time 2.17 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:02 PM PDT 24
Peak memory 214576 kb
Host smart-dc0becf1-ecbc-471e-9bb2-fa4c4dd6c4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810015396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1810015396
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1788242984
Short name T478
Test name
Test status
Simulation time 1093615862 ps
CPU time 32.34 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:32 PM PDT 24
Peak memory 247484 kb
Host smart-7add8c03-45e1-4ccb-be31-6530b44035c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788242984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1788242984
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.4012661299
Short name T117
Test name
Test status
Simulation time 142105231 ps
CPU time 3.19 seconds
Started Aug 12 04:57:01 PM PDT 24
Finished Aug 12 04:57:04 PM PDT 24
Peak memory 224488 kb
Host smart-2774a0ba-3af5-466e-9a01-18315bcf9e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012661299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.4012661299
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3559585477
Short name T186
Test name
Test status
Simulation time 27233228273 ps
CPU time 116.32 seconds
Started Aug 12 04:56:59 PM PDT 24
Finished Aug 12 04:58:56 PM PDT 24
Peak memory 226216 kb
Host smart-1a77192d-35f6-4560-aa98-a70592bcf515
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559585477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3559585477
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.2893439007
Short name T208
Test name
Test status
Simulation time 6244708592 ps
CPU time 67.21 seconds
Started Aug 12 04:57:08 PM PDT 24
Finished Aug 12 04:58:15 PM PDT 24
Peak memory 269024 kb
Host smart-9ce61245-7e97-472a-9d0d-a5beb78f1a99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2893439007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.2893439007
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2501740257
Short name T467
Test name
Test status
Simulation time 120487746 ps
CPU time 1.37 seconds
Started Aug 12 04:56:59 PM PDT 24
Finished Aug 12 04:57:01 PM PDT 24
Peak memory 217956 kb
Host smart-8eb5c7b4-fe21-42b2-9a37-b02152c5302a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501740257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2501740257
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.288560071
Short name T432
Test name
Test status
Simulation time 20929527 ps
CPU time 1.19 seconds
Started Aug 12 04:57:10 PM PDT 24
Finished Aug 12 04:57:12 PM PDT 24
Peak memory 209068 kb
Host smart-daf0eade-6869-48bd-9def-db53f2eed064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288560071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.288560071
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2263640557
Short name T488
Test name
Test status
Simulation time 1284191433 ps
CPU time 12.52 seconds
Started Aug 12 04:57:08 PM PDT 24
Finished Aug 12 04:57:21 PM PDT 24
Peak memory 226300 kb
Host smart-00b2ccfd-e2eb-4d6e-be37-13e1ce91e91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263640557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2263640557
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1602445358
Short name T874
Test name
Test status
Simulation time 241335730 ps
CPU time 4.03 seconds
Started Aug 12 04:57:08 PM PDT 24
Finished Aug 12 04:57:12 PM PDT 24
Peak memory 217816 kb
Host smart-9ba570fa-7263-47d4-9160-b49b4d58e11f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602445358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1602445358
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3177032113
Short name T849
Test name
Test status
Simulation time 1811163065 ps
CPU time 51.01 seconds
Started Aug 12 04:57:07 PM PDT 24
Finished Aug 12 04:57:58 PM PDT 24
Peak memory 218408 kb
Host smart-4a7d5dca-8512-4ac4-a5fd-a0524625e754
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177032113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3177032113
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3431105722
Short name T221
Test name
Test status
Simulation time 391952574 ps
CPU time 12.22 seconds
Started Aug 12 04:57:07 PM PDT 24
Finished Aug 12 04:57:20 PM PDT 24
Peak memory 223652 kb
Host smart-02a5a2f3-6a5f-4b7f-b169-113bf10619f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431105722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3431105722
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1124755623
Short name T95
Test name
Test status
Simulation time 954141763 ps
CPU time 7.41 seconds
Started Aug 12 04:57:07 PM PDT 24
Finished Aug 12 04:57:15 PM PDT 24
Peak memory 217776 kb
Host smart-b59a7908-8bdd-4f57-81fd-e5e67f97cd1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124755623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1124755623
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2612284063
Short name T244
Test name
Test status
Simulation time 17789608231 ps
CPU time 42.92 seconds
Started Aug 12 04:57:06 PM PDT 24
Finished Aug 12 04:57:49 PM PDT 24
Peak memory 275912 kb
Host smart-e78c0abe-8368-4c7d-b6f8-6c7c47cd368c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612284063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2612284063
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1084609204
Short name T648
Test name
Test status
Simulation time 448167507 ps
CPU time 13.66 seconds
Started Aug 12 04:57:07 PM PDT 24
Finished Aug 12 04:57:21 PM PDT 24
Peak memory 251088 kb
Host smart-35460f13-7a3f-4be7-bd6f-bf8da7055a36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084609204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1084609204
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.4025843605
Short name T772
Test name
Test status
Simulation time 75035932 ps
CPU time 3.73 seconds
Started Aug 12 04:57:08 PM PDT 24
Finished Aug 12 04:57:12 PM PDT 24
Peak memory 218348 kb
Host smart-41e9c59f-8923-406f-8a76-8055f622eb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025843605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.4025843605
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1659728788
Short name T444
Test name
Test status
Simulation time 530612492 ps
CPU time 20.6 seconds
Started Aug 12 04:57:10 PM PDT 24
Finished Aug 12 04:57:31 PM PDT 24
Peak memory 226220 kb
Host smart-c3326efb-5207-4795-98e3-d44c05459182
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659728788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1659728788
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1942384455
Short name T590
Test name
Test status
Simulation time 567950756 ps
CPU time 10.13 seconds
Started Aug 12 04:57:07 PM PDT 24
Finished Aug 12 04:57:17 PM PDT 24
Peak memory 226072 kb
Host smart-9d5ed7fd-52be-46d0-8b72-c8bf2e3dc319
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942384455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1942384455
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1614831060
Short name T252
Test name
Test status
Simulation time 2642763210 ps
CPU time 8.58 seconds
Started Aug 12 04:57:07 PM PDT 24
Finished Aug 12 04:57:16 PM PDT 24
Peak memory 218452 kb
Host smart-96dde1c5-2f3d-4d5f-b89a-ebb15d794fb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614831060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1614831060
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3891065505
Short name T77
Test name
Test status
Simulation time 492235178 ps
CPU time 9.99 seconds
Started Aug 12 04:57:10 PM PDT 24
Finished Aug 12 04:57:20 PM PDT 24
Peak memory 226216 kb
Host smart-bcfeba57-460f-428e-af29-31a76baa39d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891065505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3891065505
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.4146322334
Short name T417
Test name
Test status
Simulation time 223234868 ps
CPU time 3.15 seconds
Started Aug 12 04:57:07 PM PDT 24
Finished Aug 12 04:57:11 PM PDT 24
Peak memory 217828 kb
Host smart-f811caa9-a1cd-4360-a94d-1b42557b83a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146322334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.4146322334
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2889505889
Short name T230
Test name
Test status
Simulation time 3376702007 ps
CPU time 17.49 seconds
Started Aug 12 04:57:10 PM PDT 24
Finished Aug 12 04:57:27 PM PDT 24
Peak memory 251160 kb
Host smart-a8014716-de5e-4b61-9e1b-429b67c0fd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889505889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2889505889
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.785035910
Short name T877
Test name
Test status
Simulation time 317906989 ps
CPU time 8.03 seconds
Started Aug 12 04:57:08 PM PDT 24
Finished Aug 12 04:57:16 PM PDT 24
Peak memory 245220 kb
Host smart-d1ba3d70-4773-405d-9557-37f9b3d21480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785035910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.785035910
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.771888520
Short name T686
Test name
Test status
Simulation time 22293040042 ps
CPU time 652.67 seconds
Started Aug 12 04:57:07 PM PDT 24
Finished Aug 12 05:08:00 PM PDT 24
Peak memory 275696 kb
Host smart-010e008e-546d-4129-9c7b-4ad0065f1c10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771888520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.771888520
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3425104463
Short name T664
Test name
Test status
Simulation time 49059543 ps
CPU time 1.02 seconds
Started Aug 12 04:57:06 PM PDT 24
Finished Aug 12 04:57:08 PM PDT 24
Peak memory 212152 kb
Host smart-8b84a597-00a2-4e5c-8007-24feae4f3c96
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425104463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3425104463
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3754012040
Short name T342
Test name
Test status
Simulation time 27258509 ps
CPU time 0.98 seconds
Started Aug 12 04:57:16 PM PDT 24
Finished Aug 12 04:57:17 PM PDT 24
Peak memory 208996 kb
Host smart-db510b31-edb5-4927-88a4-29e2bc163843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754012040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3754012040
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1572942450
Short name T741
Test name
Test status
Simulation time 257947304 ps
CPU time 2.11 seconds
Started Aug 12 04:57:15 PM PDT 24
Finished Aug 12 04:57:17 PM PDT 24
Peak memory 217888 kb
Host smart-f425624f-5512-47f7-954a-04535af2e6a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572942450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1572942450
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2635283732
Short name T81
Test name
Test status
Simulation time 7489030194 ps
CPU time 22.28 seconds
Started Aug 12 04:57:20 PM PDT 24
Finished Aug 12 04:57:42 PM PDT 24
Peak memory 218980 kb
Host smart-e73a027e-9d82-4808-b941-4187216c70a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635283732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2635283732
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2393242443
Short name T486
Test name
Test status
Simulation time 983844810 ps
CPU time 4.41 seconds
Started Aug 12 04:57:08 PM PDT 24
Finished Aug 12 04:57:13 PM PDT 24
Peak memory 222848 kb
Host smart-8911e4b8-6f7a-47f3-be25-20272a5b262d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393242443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2393242443
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3929824442
Short name T536
Test name
Test status
Simulation time 3808873353 ps
CPU time 4.4 seconds
Started Aug 12 04:57:10 PM PDT 24
Finished Aug 12 04:57:14 PM PDT 24
Peak memory 217788 kb
Host smart-30a2b2c2-65d6-4a4d-be61-06f20f9ddaa0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929824442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3929824442
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2340808637
Short name T229
Test name
Test status
Simulation time 4680964420 ps
CPU time 51.28 seconds
Started Aug 12 04:57:07 PM PDT 24
Finished Aug 12 04:57:59 PM PDT 24
Peak memory 275900 kb
Host smart-05c89a7d-1003-405c-8efa-2f1dad32b210
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340808637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2340808637
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1551740581
Short name T262
Test name
Test status
Simulation time 1540439159 ps
CPU time 12.48 seconds
Started Aug 12 04:57:08 PM PDT 24
Finished Aug 12 04:57:20 PM PDT 24
Peak memory 226472 kb
Host smart-59e80c85-14cc-4520-9a61-83da717675ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551740581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1551740581
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.946755554
Short name T56
Test name
Test status
Simulation time 158570081 ps
CPU time 3.52 seconds
Started Aug 12 04:57:09 PM PDT 24
Finished Aug 12 04:57:13 PM PDT 24
Peak memory 222976 kb
Host smart-21eff7c5-9f71-4e90-aa1a-f8382c19ca34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946755554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.946755554
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1798272734
Short name T687
Test name
Test status
Simulation time 2037084032 ps
CPU time 16.73 seconds
Started Aug 12 04:57:16 PM PDT 24
Finished Aug 12 04:57:32 PM PDT 24
Peak memory 226208 kb
Host smart-e09a8346-5357-48e0-a032-d5c7fda3679f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798272734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1798272734
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1754805073
Short name T656
Test name
Test status
Simulation time 1677442542 ps
CPU time 16.53 seconds
Started Aug 12 04:57:17 PM PDT 24
Finished Aug 12 04:57:33 PM PDT 24
Peak memory 226172 kb
Host smart-86524fa4-6bf7-467e-82f7-e72f40047ce8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754805073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1754805073
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1845748768
Short name T555
Test name
Test status
Simulation time 2317678004 ps
CPU time 10.83 seconds
Started Aug 12 04:57:15 PM PDT 24
Finished Aug 12 04:57:26 PM PDT 24
Peak memory 225244 kb
Host smart-8ceb4703-2071-40c0-9752-05694f7d9df2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845748768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1845748768
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3213645518
Short name T376
Test name
Test status
Simulation time 2607584802 ps
CPU time 18.45 seconds
Started Aug 12 04:57:07 PM PDT 24
Finished Aug 12 04:57:26 PM PDT 24
Peak memory 226268 kb
Host smart-01136267-8e8a-4172-97f8-600d6a8d0716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213645518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3213645518
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.605222573
Short name T67
Test name
Test status
Simulation time 46675303 ps
CPU time 2.46 seconds
Started Aug 12 04:57:07 PM PDT 24
Finished Aug 12 04:57:10 PM PDT 24
Peak memory 214544 kb
Host smart-2f490234-bc12-4539-b153-2ccf2186b631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605222573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.605222573
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.598014234
Short name T286
Test name
Test status
Simulation time 1111927370 ps
CPU time 25.74 seconds
Started Aug 12 04:57:07 PM PDT 24
Finished Aug 12 04:57:33 PM PDT 24
Peak memory 251020 kb
Host smart-40de9234-42c8-4af6-a702-0ed3dfe260b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598014234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.598014234
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3833462855
Short name T181
Test name
Test status
Simulation time 364393986 ps
CPU time 9.49 seconds
Started Aug 12 04:57:07 PM PDT 24
Finished Aug 12 04:57:17 PM PDT 24
Peak memory 251024 kb
Host smart-675f7bc5-4eb8-474b-bc9d-f51db633dd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833462855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3833462855
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.4130238990
Short name T381
Test name
Test status
Simulation time 2249510919 ps
CPU time 100.27 seconds
Started Aug 12 04:57:19 PM PDT 24
Finished Aug 12 04:59:00 PM PDT 24
Peak memory 267456 kb
Host smart-0749a05c-5bc5-42c1-a3bf-baca8ce722ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130238990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.4130238990
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2850335271
Short name T570
Test name
Test status
Simulation time 84261470 ps
CPU time 1.14 seconds
Started Aug 12 04:57:08 PM PDT 24
Finished Aug 12 04:57:10 PM PDT 24
Peak memory 217940 kb
Host smart-a52629eb-dcae-447e-b623-f218f784bfef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850335271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2850335271
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2624565772
Short name T820
Test name
Test status
Simulation time 14873611 ps
CPU time 1.05 seconds
Started Aug 12 04:57:17 PM PDT 24
Finished Aug 12 04:57:18 PM PDT 24
Peak memory 209104 kb
Host smart-b5ba805b-64cd-427e-89cf-985efb8efa02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624565772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2624565772
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.413321871
Short name T34
Test name
Test status
Simulation time 267840547 ps
CPU time 10.82 seconds
Started Aug 12 04:57:15 PM PDT 24
Finished Aug 12 04:57:25 PM PDT 24
Peak memory 226164 kb
Host smart-07383757-f57c-492a-bcbd-73e5ab5a3111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413321871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.413321871
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2536164561
Short name T91
Test name
Test status
Simulation time 503079981 ps
CPU time 6.47 seconds
Started Aug 12 04:57:16 PM PDT 24
Finished Aug 12 04:57:22 PM PDT 24
Peak memory 217544 kb
Host smart-a6c44d75-061b-476a-a161-7c2c02726581
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536164561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2536164561
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.778427378
Short name T559
Test name
Test status
Simulation time 3258717132 ps
CPU time 29.69 seconds
Started Aug 12 04:57:16 PM PDT 24
Finished Aug 12 04:57:46 PM PDT 24
Peak memory 218440 kb
Host smart-d02f4940-6d63-44ac-b5aa-7eee809ddc1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778427378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.778427378
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2728937271
Short name T658
Test name
Test status
Simulation time 520178382 ps
CPU time 8.23 seconds
Started Aug 12 04:57:15 PM PDT 24
Finished Aug 12 04:57:23 PM PDT 24
Peak memory 224360 kb
Host smart-529d140d-4c84-4399-a761-eedcb0f7b78a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728937271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2728937271
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1143757637
Short name T576
Test name
Test status
Simulation time 361077771 ps
CPU time 5.3 seconds
Started Aug 12 04:57:16 PM PDT 24
Finished Aug 12 04:57:22 PM PDT 24
Peak memory 217840 kb
Host smart-3a0cc167-02a0-41d6-bedd-a2202e2c5983
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143757637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1143757637
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2970562687
Short name T384
Test name
Test status
Simulation time 6329683275 ps
CPU time 66.57 seconds
Started Aug 12 04:57:15 PM PDT 24
Finished Aug 12 04:58:22 PM PDT 24
Peak memory 267460 kb
Host smart-02db7679-0602-4922-a810-53e1b9e209d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970562687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2970562687
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2092178100
Short name T550
Test name
Test status
Simulation time 1238188898 ps
CPU time 10.73 seconds
Started Aug 12 04:57:20 PM PDT 24
Finished Aug 12 04:57:30 PM PDT 24
Peak memory 248616 kb
Host smart-08508a00-c905-4541-8fae-771a329b6043
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092178100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2092178100
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.4117298745
Short name T459
Test name
Test status
Simulation time 418944110 ps
CPU time 2.61 seconds
Started Aug 12 04:57:15 PM PDT 24
Finished Aug 12 04:57:18 PM PDT 24
Peak memory 218364 kb
Host smart-8e5fb2ea-940c-4b1b-b778-b56e91860a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117298745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.4117298745
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2098719985
Short name T460
Test name
Test status
Simulation time 1309781799 ps
CPU time 9.47 seconds
Started Aug 12 04:57:14 PM PDT 24
Finished Aug 12 04:57:24 PM PDT 24
Peak memory 226176 kb
Host smart-fa7c6d6a-096f-477c-ac8a-13f915cf3e70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098719985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2098719985
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2149147836
Short name T423
Test name
Test status
Simulation time 968224349 ps
CPU time 11.49 seconds
Started Aug 12 04:57:14 PM PDT 24
Finished Aug 12 04:57:25 PM PDT 24
Peak memory 226116 kb
Host smart-b88186e7-86cd-4551-b5bc-9d1d8af21e5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149147836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2149147836
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3239942719
Short name T539
Test name
Test status
Simulation time 1579575995 ps
CPU time 16.1 seconds
Started Aug 12 04:57:17 PM PDT 24
Finished Aug 12 04:57:33 PM PDT 24
Peak memory 226140 kb
Host smart-c87b2366-ce0a-42d8-8259-d4f441f5eec0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239942719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3239942719
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2992731279
Short name T873
Test name
Test status
Simulation time 1559629275 ps
CPU time 9.73 seconds
Started Aug 12 04:57:15 PM PDT 24
Finished Aug 12 04:57:25 PM PDT 24
Peak memory 218428 kb
Host smart-c1ecbde2-7088-4885-8e43-95a6e1fddc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992731279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2992731279
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3022489236
Short name T100
Test name
Test status
Simulation time 1369857268 ps
CPU time 28.63 seconds
Started Aug 12 04:57:16 PM PDT 24
Finished Aug 12 04:57:45 PM PDT 24
Peak memory 251060 kb
Host smart-efbea57f-be72-47e8-a5d3-a4d161093503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022489236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3022489236
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2952472688
Short name T557
Test name
Test status
Simulation time 198395453 ps
CPU time 10.62 seconds
Started Aug 12 04:57:16 PM PDT 24
Finished Aug 12 04:57:27 PM PDT 24
Peak memory 251100 kb
Host smart-49b6f3a2-822c-491a-92ce-86a446171628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952472688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2952472688
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.1884867370
Short name T736
Test name
Test status
Simulation time 4215416420 ps
CPU time 100.6 seconds
Started Aug 12 04:57:14 PM PDT 24
Finished Aug 12 04:58:55 PM PDT 24
Peak memory 277900 kb
Host smart-d79d36c9-e08b-4966-8e76-816538680142
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1884867370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.1884867370
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3745904464
Short name T605
Test name
Test status
Simulation time 21113104 ps
CPU time 0.95 seconds
Started Aug 12 04:57:15 PM PDT 24
Finished Aug 12 04:57:16 PM PDT 24
Peak memory 209096 kb
Host smart-02bd327b-6537-44a3-bdcc-04def200411d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745904464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3745904464
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3333579392
Short name T842
Test name
Test status
Simulation time 41998719 ps
CPU time 0.88 seconds
Started Aug 12 04:57:24 PM PDT 24
Finished Aug 12 04:57:25 PM PDT 24
Peak memory 208976 kb
Host smart-ba06b2ac-aa0d-42df-825f-304a8c333bf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333579392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3333579392
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2586360231
Short name T614
Test name
Test status
Simulation time 1825254495 ps
CPU time 13.3 seconds
Started Aug 12 04:57:22 PM PDT 24
Finished Aug 12 04:57:36 PM PDT 24
Peak memory 218376 kb
Host smart-69337f2c-a1cd-420d-a3fb-42c5213b0506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586360231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2586360231
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1112919946
Short name T692
Test name
Test status
Simulation time 561681581 ps
CPU time 3.43 seconds
Started Aug 12 04:57:31 PM PDT 24
Finished Aug 12 04:57:35 PM PDT 24
Peak memory 217832 kb
Host smart-24e3e57d-bb98-4e8f-8fef-ba78e0dd9b4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112919946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1112919946
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2650192215
Short name T406
Test name
Test status
Simulation time 12688231167 ps
CPU time 58.66 seconds
Started Aug 12 04:57:32 PM PDT 24
Finished Aug 12 04:58:31 PM PDT 24
Peak memory 219064 kb
Host smart-7f97c852-4e3c-4a85-ae60-68147247f71e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650192215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2650192215
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1742634297
Short name T720
Test name
Test status
Simulation time 3282658171 ps
CPU time 11.33 seconds
Started Aug 12 04:57:32 PM PDT 24
Finished Aug 12 04:57:43 PM PDT 24
Peak memory 226188 kb
Host smart-058277ea-c634-44ce-a610-f4c4bc0e3a9d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742634297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1742634297
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1299152489
Short name T60
Test name
Test status
Simulation time 450894277 ps
CPU time 1.6 seconds
Started Aug 12 04:57:23 PM PDT 24
Finished Aug 12 04:57:25 PM PDT 24
Peak memory 217720 kb
Host smart-3e0c0a47-bacc-47cf-ae41-dffee1514cc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299152489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1299152489
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2410312661
Short name T255
Test name
Test status
Simulation time 3085833944 ps
CPU time 105.69 seconds
Started Aug 12 04:57:22 PM PDT 24
Finished Aug 12 04:59:08 PM PDT 24
Peak memory 283748 kb
Host smart-28d2cbf9-a24c-4651-8b43-045f7141cad2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410312661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2410312661
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2857827893
Short name T655
Test name
Test status
Simulation time 596122565 ps
CPU time 18.11 seconds
Started Aug 12 04:57:24 PM PDT 24
Finished Aug 12 04:57:43 PM PDT 24
Peak memory 224164 kb
Host smart-e4a6ff8c-edd6-4735-8aec-7077b29c8165
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857827893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2857827893
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3386100344
Short name T474
Test name
Test status
Simulation time 170354852 ps
CPU time 1.74 seconds
Started Aug 12 04:57:20 PM PDT 24
Finished Aug 12 04:57:21 PM PDT 24
Peak memory 218328 kb
Host smart-7c2bed0b-edd4-4be5-8e75-373acbc5971a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386100344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3386100344
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2748403208
Short name T503
Test name
Test status
Simulation time 371361359 ps
CPU time 14.52 seconds
Started Aug 12 04:57:21 PM PDT 24
Finished Aug 12 04:57:36 PM PDT 24
Peak memory 226148 kb
Host smart-cb943c30-4943-4bea-b071-05ed22b14943
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748403208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2748403208
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3062221726
Short name T580
Test name
Test status
Simulation time 373554815 ps
CPU time 9.83 seconds
Started Aug 12 04:57:26 PM PDT 24
Finished Aug 12 04:57:36 PM PDT 24
Peak memory 226172 kb
Host smart-79dc8d92-7ccb-451a-aa83-9713851867da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062221726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3062221726
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.4062241279
Short name T469
Test name
Test status
Simulation time 7219621295 ps
CPU time 9 seconds
Started Aug 12 04:57:25 PM PDT 24
Finished Aug 12 04:57:34 PM PDT 24
Peak memory 226196 kb
Host smart-ffe25b36-7183-41e4-b536-24a6320e8008
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062241279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
4062241279
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3306554785
Short name T350
Test name
Test status
Simulation time 366355021 ps
CPU time 8.35 seconds
Started Aug 12 04:57:23 PM PDT 24
Finished Aug 12 04:57:32 PM PDT 24
Peak memory 225812 kb
Host smart-b48f26cf-ad39-4baf-a35b-ea1507b7c022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306554785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3306554785
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2580191295
Short name T653
Test name
Test status
Simulation time 99237721 ps
CPU time 5.09 seconds
Started Aug 12 04:57:20 PM PDT 24
Finished Aug 12 04:57:25 PM PDT 24
Peak memory 217756 kb
Host smart-86207577-ef9e-4fc8-9cba-739231be2e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580191295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2580191295
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1819517656
Short name T569
Test name
Test status
Simulation time 136266149 ps
CPU time 7.63 seconds
Started Aug 12 04:57:16 PM PDT 24
Finished Aug 12 04:57:24 PM PDT 24
Peak memory 250300 kb
Host smart-04ebe146-c994-41fb-83aa-c81b1de2b2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819517656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1819517656
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1090661984
Short name T319
Test name
Test status
Simulation time 2114490207 ps
CPU time 18.92 seconds
Started Aug 12 04:57:25 PM PDT 24
Finished Aug 12 04:57:44 PM PDT 24
Peak memory 251040 kb
Host smart-404f0f74-3474-4c15-91f8-6267043194af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090661984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1090661984
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2363189894
Short name T827
Test name
Test status
Simulation time 22247534 ps
CPU time 0.78 seconds
Started Aug 12 04:57:16 PM PDT 24
Finished Aug 12 04:57:17 PM PDT 24
Peak memory 209312 kb
Host smart-7449c51d-21a4-4b4f-a159-54330d552dd6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363189894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2363189894
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1179804852
Short name T299
Test name
Test status
Simulation time 33940064 ps
CPU time 1.19 seconds
Started Aug 12 04:57:29 PM PDT 24
Finished Aug 12 04:57:30 PM PDT 24
Peak memory 208976 kb
Host smart-e33a0bf9-ec5e-4d57-a2fb-56d91944d8f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179804852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1179804852
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.916214688
Short name T10
Test name
Test status
Simulation time 477897562 ps
CPU time 10.69 seconds
Started Aug 12 04:57:26 PM PDT 24
Finished Aug 12 04:57:37 PM PDT 24
Peak memory 218392 kb
Host smart-e31a7dc6-a0d8-495b-a247-924e77ccd1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916214688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.916214688
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.935634381
Short name T25
Test name
Test status
Simulation time 1192856216 ps
CPU time 4.04 seconds
Started Aug 12 04:57:25 PM PDT 24
Finished Aug 12 04:57:29 PM PDT 24
Peak memory 217472 kb
Host smart-eddba384-2c28-49d2-8285-994254b34824
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935634381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.935634381
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.942907351
Short name T481
Test name
Test status
Simulation time 3593161654 ps
CPU time 52.58 seconds
Started Aug 12 04:57:24 PM PDT 24
Finished Aug 12 04:58:17 PM PDT 24
Peak memory 219088 kb
Host smart-6cf2dfc1-0d7c-46e0-87d1-5c72929cab6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942907351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.942907351
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1425821054
Short name T225
Test name
Test status
Simulation time 1871078117 ps
CPU time 14.22 seconds
Started Aug 12 04:57:26 PM PDT 24
Finished Aug 12 04:57:40 PM PDT 24
Peak memory 218356 kb
Host smart-a33d43c9-058e-437e-ab3a-a2b6c59f9f4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425821054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1425821054
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1040902798
Short name T601
Test name
Test status
Simulation time 1078206835 ps
CPU time 4.19 seconds
Started Aug 12 04:57:23 PM PDT 24
Finished Aug 12 04:57:27 PM PDT 24
Peak memory 217836 kb
Host smart-35a06d53-462e-4410-8203-924cd82118ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040902798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1040902798
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1617008767
Short name T505
Test name
Test status
Simulation time 2943269580 ps
CPU time 56.62 seconds
Started Aug 12 04:57:22 PM PDT 24
Finished Aug 12 04:58:19 PM PDT 24
Peak memory 277760 kb
Host smart-1224ba3d-8ebf-4684-ab5c-4eec80288e47
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617008767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1617008767
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.4276230173
Short name T275
Test name
Test status
Simulation time 390460728 ps
CPU time 11.3 seconds
Started Aug 12 04:57:24 PM PDT 24
Finished Aug 12 04:57:35 PM PDT 24
Peak memory 245832 kb
Host smart-6e48b72c-9b6d-4844-8b59-d85dc18038ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276230173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.4276230173
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3049585606
Short name T343
Test name
Test status
Simulation time 50638354 ps
CPU time 2.82 seconds
Started Aug 12 04:57:26 PM PDT 24
Finished Aug 12 04:57:29 PM PDT 24
Peak memory 222380 kb
Host smart-f898360d-9c89-4474-9224-64b8c1cce725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049585606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3049585606
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.140634178
Short name T371
Test name
Test status
Simulation time 1774680980 ps
CPU time 14.85 seconds
Started Aug 12 04:57:26 PM PDT 24
Finished Aug 12 04:57:41 PM PDT 24
Peak memory 220104 kb
Host smart-9da118fa-3376-4b4e-be8a-e8460e21948b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140634178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.140634178
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2328256327
Short name T841
Test name
Test status
Simulation time 1365917905 ps
CPU time 12.07 seconds
Started Aug 12 04:57:24 PM PDT 24
Finished Aug 12 04:57:36 PM PDT 24
Peak memory 226088 kb
Host smart-c776b6db-965a-4944-a0d8-4db289ad6ff1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328256327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2328256327
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.4082027893
Short name T675
Test name
Test status
Simulation time 1138816037 ps
CPU time 10.79 seconds
Started Aug 12 04:57:22 PM PDT 24
Finished Aug 12 04:57:33 PM PDT 24
Peak memory 218380 kb
Host smart-993172bd-3f8e-4e3a-8ef7-a4f5569aa922
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082027893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
4082027893
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.144334164
Short name T434
Test name
Test status
Simulation time 524249828 ps
CPU time 11.51 seconds
Started Aug 12 04:57:25 PM PDT 24
Finished Aug 12 04:57:36 PM PDT 24
Peak memory 218424 kb
Host smart-bd84252b-7b4d-4451-a374-d76b51631da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144334164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.144334164
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.4099924766
Short name T685
Test name
Test status
Simulation time 49578540 ps
CPU time 1.86 seconds
Started Aug 12 04:57:22 PM PDT 24
Finished Aug 12 04:57:24 PM PDT 24
Peak memory 217788 kb
Host smart-a2c4ec48-58d2-44c6-8736-da6ba080cb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099924766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.4099924766
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1338590519
Short name T816
Test name
Test status
Simulation time 388060133 ps
CPU time 34.03 seconds
Started Aug 12 04:57:27 PM PDT 24
Finished Aug 12 04:58:01 PM PDT 24
Peak memory 251212 kb
Host smart-3c880912-76e6-4180-bae2-c6d463a14c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338590519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1338590519
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2416926492
Short name T513
Test name
Test status
Simulation time 1049260570 ps
CPU time 6.49 seconds
Started Aug 12 04:57:24 PM PDT 24
Finished Aug 12 04:57:31 PM PDT 24
Peak memory 246900 kb
Host smart-4d58bc39-e0b8-4176-96d4-f155aa8cf966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416926492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2416926492
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1729806747
Short name T863
Test name
Test status
Simulation time 1117442153 ps
CPU time 15.59 seconds
Started Aug 12 04:57:21 PM PDT 24
Finished Aug 12 04:57:36 PM PDT 24
Peak memory 247396 kb
Host smart-e6d772df-1e62-491b-9cf1-d23997455fdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729806747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1729806747
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2102330130
Short name T512
Test name
Test status
Simulation time 29435868 ps
CPU time 0.87 seconds
Started Aug 12 04:57:22 PM PDT 24
Finished Aug 12 04:57:23 PM PDT 24
Peak memory 209136 kb
Host smart-532f316e-cd13-44ea-b496-516c104da9af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102330130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2102330130
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2401459327
Short name T701
Test name
Test status
Simulation time 46436496 ps
CPU time 0.88 seconds
Started Aug 12 04:57:37 PM PDT 24
Finished Aug 12 04:57:39 PM PDT 24
Peak memory 208848 kb
Host smart-60f19128-ae6a-4217-8913-542a45e10ecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401459327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2401459327
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1883535575
Short name T471
Test name
Test status
Simulation time 1239148268 ps
CPU time 13.01 seconds
Started Aug 12 04:57:37 PM PDT 24
Finished Aug 12 04:57:51 PM PDT 24
Peak memory 226208 kb
Host smart-263a56db-967e-4236-815f-27ab3c5d6c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883535575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1883535575
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2522631275
Short name T818
Test name
Test status
Simulation time 1516843250 ps
CPU time 6.72 seconds
Started Aug 12 04:57:30 PM PDT 24
Finished Aug 12 04:57:36 PM PDT 24
Peak memory 217532 kb
Host smart-6b2a1107-625f-4e46-b5ba-f5bbcab0ad5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522631275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2522631275
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.322260064
Short name T405
Test name
Test status
Simulation time 6861720537 ps
CPU time 48.8 seconds
Started Aug 12 04:57:40 PM PDT 24
Finished Aug 12 04:58:29 PM PDT 24
Peak memory 218492 kb
Host smart-952117fe-5621-45a7-87b4-292aed762311
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322260064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.322260064
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2927925747
Short name T369
Test name
Test status
Simulation time 1306332907 ps
CPU time 18.38 seconds
Started Aug 12 04:57:35 PM PDT 24
Finished Aug 12 04:57:54 PM PDT 24
Peak memory 218316 kb
Host smart-e18791bd-006b-4f28-a98f-c56adaaf651a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927925747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2927925747
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1748230089
Short name T407
Test name
Test status
Simulation time 1156554138 ps
CPU time 5.17 seconds
Started Aug 12 04:57:30 PM PDT 24
Finished Aug 12 04:57:35 PM PDT 24
Peak memory 217700 kb
Host smart-533e18ca-cd53-4f42-9d92-f43b56f012d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748230089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1748230089
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3201648036
Short name T634
Test name
Test status
Simulation time 6023437661 ps
CPU time 57.22 seconds
Started Aug 12 04:57:30 PM PDT 24
Finished Aug 12 04:58:28 PM PDT 24
Peak memory 277456 kb
Host smart-01e2b1a0-f398-4c32-8f08-f5dfffa40e9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201648036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3201648036
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.456738515
Short name T14
Test name
Test status
Simulation time 604675761 ps
CPU time 22.24 seconds
Started Aug 12 04:57:41 PM PDT 24
Finished Aug 12 04:58:03 PM PDT 24
Peak memory 251032 kb
Host smart-33b20128-55ff-4eed-952f-c466e64167cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456738515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.456738515
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.421103956
Short name T359
Test name
Test status
Simulation time 127570762 ps
CPU time 3.72 seconds
Started Aug 12 04:57:32 PM PDT 24
Finished Aug 12 04:57:36 PM PDT 24
Peak memory 222764 kb
Host smart-05a77b83-9b11-422d-915b-5bb1cb87c531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421103956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.421103956
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.187676765
Short name T291
Test name
Test status
Simulation time 541925961 ps
CPU time 8.3 seconds
Started Aug 12 04:57:30 PM PDT 24
Finished Aug 12 04:57:39 PM PDT 24
Peak memory 219124 kb
Host smart-7090a94c-9a21-4d5b-ab3e-734a9b00f571
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187676765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.187676765
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2761943119
Short name T514
Test name
Test status
Simulation time 303770205 ps
CPU time 10.65 seconds
Started Aug 12 04:57:30 PM PDT 24
Finished Aug 12 04:57:40 PM PDT 24
Peak memory 226120 kb
Host smart-c9f7d2c5-0277-4964-a9af-cf4237216328
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761943119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2761943119
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2379313539
Short name T706
Test name
Test status
Simulation time 690150483 ps
CPU time 10.09 seconds
Started Aug 12 04:57:30 PM PDT 24
Finished Aug 12 04:57:40 PM PDT 24
Peak memory 226164 kb
Host smart-33bf7ba7-35cf-42c1-a826-2fd7a1bb10ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379313539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2379313539
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3532819354
Short name T46
Test name
Test status
Simulation time 344845118 ps
CPU time 12.31 seconds
Started Aug 12 04:57:39 PM PDT 24
Finished Aug 12 04:57:52 PM PDT 24
Peak memory 218472 kb
Host smart-92caee61-d3b5-428d-aa57-c22dbc18a9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532819354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3532819354
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2521263995
Short name T223
Test name
Test status
Simulation time 63837462 ps
CPU time 2.57 seconds
Started Aug 12 04:57:31 PM PDT 24
Finished Aug 12 04:57:34 PM PDT 24
Peak memory 214388 kb
Host smart-64428e19-16bb-4410-8a8c-29c1f019b0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521263995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2521263995
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1230391715
Short name T744
Test name
Test status
Simulation time 232085312 ps
CPU time 25.77 seconds
Started Aug 12 04:57:30 PM PDT 24
Finished Aug 12 04:57:56 PM PDT 24
Peak memory 251036 kb
Host smart-f5b65dd1-8509-4fe6-9992-da8cdea9501a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230391715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1230391715
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.162402403
Short name T604
Test name
Test status
Simulation time 170470776 ps
CPU time 9.52 seconds
Started Aug 12 04:57:36 PM PDT 24
Finished Aug 12 04:57:46 PM PDT 24
Peak memory 251100 kb
Host smart-ab685b76-61bf-4627-ac60-fb7874ed7ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162402403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.162402403
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.151868450
Short name T619
Test name
Test status
Simulation time 420112818 ps
CPU time 11.57 seconds
Started Aug 12 04:57:32 PM PDT 24
Finished Aug 12 04:57:43 PM PDT 24
Peak memory 224700 kb
Host smart-567cfd26-a7d7-4b3a-9a0f-c0676769ba9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151868450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.151868450
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.1259573569
Short name T150
Test name
Test status
Simulation time 10529779106 ps
CPU time 52.47 seconds
Started Aug 12 04:57:37 PM PDT 24
Finished Aug 12 04:58:29 PM PDT 24
Peak memory 267624 kb
Host smart-1f66721f-f0c0-426a-b0cf-9f4ddb665ceb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1259573569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.1259573569
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1379296207
Short name T742
Test name
Test status
Simulation time 64762808 ps
CPU time 1.05 seconds
Started Aug 12 04:57:31 PM PDT 24
Finished Aug 12 04:57:32 PM PDT 24
Peak memory 212084 kb
Host smart-9b1f7517-458d-4de0-8381-5e45a4e21cd6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379296207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1379296207
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2302413453
Short name T602
Test name
Test status
Simulation time 82261278 ps
CPU time 1 seconds
Started Aug 12 04:57:38 PM PDT 24
Finished Aug 12 04:57:39 PM PDT 24
Peak memory 208988 kb
Host smart-709a55aa-bbf1-4ac3-932c-79aa55dbe1ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302413453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2302413453
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.909372867
Short name T595
Test name
Test status
Simulation time 546865263 ps
CPU time 10.44 seconds
Started Aug 12 04:57:40 PM PDT 24
Finished Aug 12 04:57:51 PM PDT 24
Peak memory 218528 kb
Host smart-0c5addca-d459-4e1c-a575-423a9392bc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909372867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.909372867
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1471246821
Short name T790
Test name
Test status
Simulation time 84701142 ps
CPU time 1.17 seconds
Started Aug 12 04:57:41 PM PDT 24
Finished Aug 12 04:57:43 PM PDT 24
Peak memory 217892 kb
Host smart-9b0067a8-f488-4e03-9b79-8275c1c0c3e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471246821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1471246821
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2033754888
Short name T334
Test name
Test status
Simulation time 2332755712 ps
CPU time 22.87 seconds
Started Aug 12 04:57:38 PM PDT 24
Finished Aug 12 04:58:01 PM PDT 24
Peak memory 218360 kb
Host smart-57447328-5ed6-4c5b-8805-517a1d2fc33f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033754888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2033754888
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.781519708
Short name T572
Test name
Test status
Simulation time 784451643 ps
CPU time 6.78 seconds
Started Aug 12 04:57:38 PM PDT 24
Finished Aug 12 04:57:45 PM PDT 24
Peak memory 222240 kb
Host smart-70c1a3da-1f49-4d86-aac3-685f35eb7ca6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781519708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.781519708
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1538299828
Short name T620
Test name
Test status
Simulation time 1724071793 ps
CPU time 6.75 seconds
Started Aug 12 04:57:37 PM PDT 24
Finished Aug 12 04:57:44 PM PDT 24
Peak memory 217760 kb
Host smart-e3691274-3ae8-4fde-ac11-a6ea194612e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538299828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1538299828
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.172248145
Short name T355
Test name
Test status
Simulation time 4793963258 ps
CPU time 25.74 seconds
Started Aug 12 04:57:30 PM PDT 24
Finished Aug 12 04:57:56 PM PDT 24
Peak memory 251012 kb
Host smart-537ac86f-5521-4e33-b931-45b1482e2bcc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172248145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.172248145
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2938742950
Short name T260
Test name
Test status
Simulation time 1112823144 ps
CPU time 8.94 seconds
Started Aug 12 04:57:29 PM PDT 24
Finished Aug 12 04:57:39 PM PDT 24
Peak memory 250428 kb
Host smart-2a122787-a064-43e9-b64b-f8d9f0425850
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938742950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2938742950
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.938363342
Short name T266
Test name
Test status
Simulation time 90572686 ps
CPU time 3.56 seconds
Started Aug 12 04:57:30 PM PDT 24
Finished Aug 12 04:57:34 PM PDT 24
Peak memory 218400 kb
Host smart-97628a4c-bc86-4d45-bd57-0c2d76822026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938363342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.938363342
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.314926196
Short name T767
Test name
Test status
Simulation time 294512919 ps
CPU time 13.85 seconds
Started Aug 12 04:57:35 PM PDT 24
Finished Aug 12 04:57:49 PM PDT 24
Peak memory 218972 kb
Host smart-27636c6d-716a-4ffb-a2e5-7676407d8796
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314926196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.314926196
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3785580290
Short name T586
Test name
Test status
Simulation time 255103231 ps
CPU time 10.35 seconds
Started Aug 12 04:57:38 PM PDT 24
Finished Aug 12 04:57:49 PM PDT 24
Peak memory 226088 kb
Host smart-51bea565-7292-44e9-bd8b-c70dbd1bd47c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785580290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3785580290
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2817457650
Short name T611
Test name
Test status
Simulation time 1350298496 ps
CPU time 13.88 seconds
Started Aug 12 04:57:36 PM PDT 24
Finished Aug 12 04:57:50 PM PDT 24
Peak memory 218368 kb
Host smart-ecfc13cf-4607-4d02-b66f-48f8a2be2d45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817457650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2817457650
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.259774934
Short name T323
Test name
Test status
Simulation time 370030639 ps
CPU time 6.79 seconds
Started Aug 12 04:57:35 PM PDT 24
Finished Aug 12 04:57:41 PM PDT 24
Peak memory 215084 kb
Host smart-b0e8b2dc-4c2b-48b3-8f33-da4885d9cae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259774934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.259774934
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2826341055
Short name T501
Test name
Test status
Simulation time 1071723781 ps
CPU time 27.43 seconds
Started Aug 12 04:57:29 PM PDT 24
Finished Aug 12 04:57:57 PM PDT 24
Peak memory 251272 kb
Host smart-ad85f061-177a-49f1-9730-ad3bad480f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826341055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2826341055
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.4291916220
Short name T345
Test name
Test status
Simulation time 121492191 ps
CPU time 6.8 seconds
Started Aug 12 04:57:40 PM PDT 24
Finished Aug 12 04:57:47 PM PDT 24
Peak memory 246952 kb
Host smart-fe7732fa-962b-42a8-8012-0732d49f5e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291916220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.4291916220
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1793666937
Short name T704
Test name
Test status
Simulation time 10176111510 ps
CPU time 57.91 seconds
Started Aug 12 04:57:37 PM PDT 24
Finished Aug 12 04:58:35 PM PDT 24
Peak memory 271152 kb
Host smart-ed843784-eb69-46b9-8d93-c384f84e2f7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793666937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1793666937
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.30534674
Short name T450
Test name
Test status
Simulation time 15015647 ps
CPU time 0.92 seconds
Started Aug 12 04:57:41 PM PDT 24
Finished Aug 12 04:57:42 PM PDT 24
Peak memory 212072 kb
Host smart-a4de6ea7-6d75-4b9a-b47d-21da9d7da3dd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30534674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_volatile_unlock_smoke.30534674
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.4139080789
Short name T581
Test name
Test status
Simulation time 15890714 ps
CPU time 0.94 seconds
Started Aug 12 04:57:41 PM PDT 24
Finished Aug 12 04:57:42 PM PDT 24
Peak memory 208968 kb
Host smart-98c7e230-41f7-4d63-a899-d19869d5ba5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139080789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.4139080789
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3377737750
Short name T169
Test name
Test status
Simulation time 4896794895 ps
CPU time 9.13 seconds
Started Aug 12 04:57:38 PM PDT 24
Finished Aug 12 04:57:47 PM PDT 24
Peak memory 217272 kb
Host smart-cb3529ab-932f-44e5-a77f-ae2809b8f01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377737750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3377737750
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.88946230
Short name T667
Test name
Test status
Simulation time 48415970 ps
CPU time 1.87 seconds
Started Aug 12 04:57:38 PM PDT 24
Finished Aug 12 04:57:40 PM PDT 24
Peak memory 217772 kb
Host smart-b49a0941-e6d3-4396-ad2c-25bdc9392397
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88946230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.88946230
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2685081421
Short name T249
Test name
Test status
Simulation time 2181596656 ps
CPU time 34.08 seconds
Started Aug 12 04:57:36 PM PDT 24
Finished Aug 12 04:58:10 PM PDT 24
Peak memory 218444 kb
Host smart-f34f4bb2-bd16-4b27-b693-36007eaf50ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685081421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2685081421
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1635403458
Short name T625
Test name
Test status
Simulation time 1180014955 ps
CPU time 8.65 seconds
Started Aug 12 04:57:40 PM PDT 24
Finished Aug 12 04:57:48 PM PDT 24
Peak memory 223184 kb
Host smart-a55193f3-ed1e-44f8-9518-0b302d855b80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635403458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1635403458
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.174076571
Short name T807
Test name
Test status
Simulation time 319179756 ps
CPU time 4.76 seconds
Started Aug 12 04:57:38 PM PDT 24
Finished Aug 12 04:57:43 PM PDT 24
Peak memory 217700 kb
Host smart-4a63d690-1e2e-4053-9b09-3ac639dfa3d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174076571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
174076571
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.427488949
Short name T325
Test name
Test status
Simulation time 2193408887 ps
CPU time 83.5 seconds
Started Aug 12 04:57:37 PM PDT 24
Finished Aug 12 04:59:01 PM PDT 24
Peak memory 281372 kb
Host smart-85ff1247-8115-43be-9c26-b2073ff1a2a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427488949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.427488949
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.87583969
Short name T448
Test name
Test status
Simulation time 1499545540 ps
CPU time 15.33 seconds
Started Aug 12 04:57:38 PM PDT 24
Finished Aug 12 04:57:53 PM PDT 24
Peak memory 250448 kb
Host smart-c9a868b3-d1cb-4b66-8d0d-770f7fc3c1ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87583969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_j
tag_state_post_trans.87583969
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.50521121
Short name T182
Test name
Test status
Simulation time 696230192 ps
CPU time 2.77 seconds
Started Aug 12 04:57:39 PM PDT 24
Finished Aug 12 04:57:41 PM PDT 24
Peak memory 218348 kb
Host smart-4eaa9f13-d673-4b73-ad84-fdc0436c2ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50521121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.50521121
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3543278653
Short name T372
Test name
Test status
Simulation time 390750519 ps
CPU time 11.28 seconds
Started Aug 12 04:57:36 PM PDT 24
Finished Aug 12 04:57:48 PM PDT 24
Peak memory 218612 kb
Host smart-1e58d6a8-4a84-4f93-9046-5e98014b9e7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543278653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3543278653
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1020935175
Short name T663
Test name
Test status
Simulation time 220060878 ps
CPU time 10.49 seconds
Started Aug 12 04:57:40 PM PDT 24
Finished Aug 12 04:57:51 PM PDT 24
Peak memory 226088 kb
Host smart-9a388683-ba33-4b7e-9e72-d9f72d3005ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020935175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1020935175
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2739659164
Short name T546
Test name
Test status
Simulation time 843767434 ps
CPU time 7.86 seconds
Started Aug 12 04:57:37 PM PDT 24
Finished Aug 12 04:57:45 PM PDT 24
Peak memory 226228 kb
Host smart-8fc7c46f-ea92-4e03-ab49-8151a4b50fc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739659164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2739659164
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.567346811
Short name T49
Test name
Test status
Simulation time 1015556378 ps
CPU time 9.85 seconds
Started Aug 12 04:57:37 PM PDT 24
Finished Aug 12 04:57:47 PM PDT 24
Peak memory 226236 kb
Host smart-1c522bc2-87eb-4d4d-ae62-1b447cfd8219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567346811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.567346811
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1043408622
Short name T59
Test name
Test status
Simulation time 454666493 ps
CPU time 3.37 seconds
Started Aug 12 04:57:37 PM PDT 24
Finished Aug 12 04:57:41 PM PDT 24
Peak memory 217832 kb
Host smart-f51ac813-cc2b-4b2e-a7c3-4038ecd8ab39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043408622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1043408622
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2258233348
Short name T104
Test name
Test status
Simulation time 212354282 ps
CPU time 26.8 seconds
Started Aug 12 04:57:37 PM PDT 24
Finished Aug 12 04:58:04 PM PDT 24
Peak memory 249884 kb
Host smart-92e52381-f7a8-44cb-bc93-6dd5a7d2b29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258233348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2258233348
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2451717455
Short name T361
Test name
Test status
Simulation time 63265788 ps
CPU time 7.79 seconds
Started Aug 12 04:57:35 PM PDT 24
Finished Aug 12 04:57:43 PM PDT 24
Peak memory 244280 kb
Host smart-ba2c7f17-f603-4e91-a58f-cf954dddfd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451717455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2451717455
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2213727842
Short name T789
Test name
Test status
Simulation time 2919025258 ps
CPU time 28.36 seconds
Started Aug 12 04:57:35 PM PDT 24
Finished Aug 12 04:58:04 PM PDT 24
Peak memory 250884 kb
Host smart-7a857ddc-72b9-4194-9f29-78d0049fb8af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213727842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2213727842
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2616051489
Short name T451
Test name
Test status
Simulation time 110790033 ps
CPU time 0.85 seconds
Started Aug 12 04:57:36 PM PDT 24
Finished Aug 12 04:57:37 PM PDT 24
Peak memory 212100 kb
Host smart-71d66ddc-45d5-4db9-aa8f-7497f17d24ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616051489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2616051489
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1341820208
Short name T712
Test name
Test status
Simulation time 184770767 ps
CPU time 0.95 seconds
Started Aug 12 04:56:18 PM PDT 24
Finished Aug 12 04:56:19 PM PDT 24
Peak memory 208916 kb
Host smart-ab5e7943-faab-4bd5-b432-942cc327fc71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341820208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1341820208
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.46437645
Short name T553
Test name
Test status
Simulation time 18504786 ps
CPU time 0.81 seconds
Started Aug 12 04:56:12 PM PDT 24
Finished Aug 12 04:56:13 PM PDT 24
Peak memory 209080 kb
Host smart-df67b95b-7a00-447f-9207-665376a379ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46437645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.46437645
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3259963749
Short name T504
Test name
Test status
Simulation time 328953399 ps
CPU time 11.05 seconds
Started Aug 12 04:56:11 PM PDT 24
Finished Aug 12 04:56:22 PM PDT 24
Peak memory 218340 kb
Host smart-79f20bc7-a157-462c-be2a-f56f4d4d754a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259963749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3259963749
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1667199887
Short name T774
Test name
Test status
Simulation time 208999364 ps
CPU time 2.99 seconds
Started Aug 12 04:56:11 PM PDT 24
Finished Aug 12 04:56:14 PM PDT 24
Peak memory 217844 kb
Host smart-0dcfd970-7df4-4eee-abe9-185379fbb10a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667199887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1667199887
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.46432153
Short name T500
Test name
Test status
Simulation time 989381481 ps
CPU time 29.96 seconds
Started Aug 12 04:56:09 PM PDT 24
Finished Aug 12 04:56:40 PM PDT 24
Peak memory 218272 kb
Host smart-36226ee8-549f-4592-aa45-6dcf41ab2061
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46432153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_erro
rs.46432153
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.773362816
Short name T442
Test name
Test status
Simulation time 886552702 ps
CPU time 6.61 seconds
Started Aug 12 04:56:09 PM PDT 24
Finished Aug 12 04:56:16 PM PDT 24
Peak memory 217816 kb
Host smart-ef9119f9-e90e-43f7-9ac9-23ade36e8cbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773362816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.773362816
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2064541531
Short name T549
Test name
Test status
Simulation time 120120405 ps
CPU time 4.44 seconds
Started Aug 12 04:56:09 PM PDT 24
Finished Aug 12 04:56:14 PM PDT 24
Peak memory 218248 kb
Host smart-e2f85465-3d00-42d0-9298-056d58658f82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064541531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2064541531
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3036740559
Short name T63
Test name
Test status
Simulation time 783717533 ps
CPU time 23.03 seconds
Started Aug 12 04:56:10 PM PDT 24
Finished Aug 12 04:56:33 PM PDT 24
Peak memory 217784 kb
Host smart-5c49b879-39a9-4b7e-9d17-31a43a6c82a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036740559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3036740559
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1667151572
Short name T786
Test name
Test status
Simulation time 1659903893 ps
CPU time 10.23 seconds
Started Aug 12 04:56:11 PM PDT 24
Finished Aug 12 04:56:22 PM PDT 24
Peak memory 217780 kb
Host smart-1c5280df-9482-492d-b063-085068eb6638
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667151572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1667151572
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3988279439
Short name T809
Test name
Test status
Simulation time 1113445700 ps
CPU time 49.75 seconds
Started Aug 12 04:56:10 PM PDT 24
Finished Aug 12 04:57:00 PM PDT 24
Peak memory 251032 kb
Host smart-f2fafdb7-9dc1-4cb5-8e76-757d72413549
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988279439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3988279439
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2024496454
Short name T248
Test name
Test status
Simulation time 534316875 ps
CPU time 16.07 seconds
Started Aug 12 04:56:12 PM PDT 24
Finished Aug 12 04:56:29 PM PDT 24
Peak memory 225804 kb
Host smart-eed508d6-b808-4c31-919d-fcee4e4aec22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024496454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2024496454
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3043479062
Short name T545
Test name
Test status
Simulation time 85784098 ps
CPU time 1.79 seconds
Started Aug 12 04:56:09 PM PDT 24
Finished Aug 12 04:56:11 PM PDT 24
Peak memory 222164 kb
Host smart-9206361a-f252-4d61-ac7e-183f8a834c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043479062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3043479062
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.724392938
Short name T429
Test name
Test status
Simulation time 747095538 ps
CPU time 9.66 seconds
Started Aug 12 04:56:09 PM PDT 24
Finished Aug 12 04:56:19 PM PDT 24
Peak memory 217776 kb
Host smart-0bf9acbb-b663-4c58-968c-303abc4d986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724392938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.724392938
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.63546955
Short name T51
Test name
Test status
Simulation time 229764444 ps
CPU time 35.14 seconds
Started Aug 12 04:56:17 PM PDT 24
Finished Aug 12 04:56:52 PM PDT 24
Peak memory 282448 kb
Host smart-bcc235d1-a106-4a25-8152-d964d33910c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63546955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.63546955
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1868970791
Short name T239
Test name
Test status
Simulation time 307347534 ps
CPU time 9.2 seconds
Started Aug 12 04:56:12 PM PDT 24
Finished Aug 12 04:56:21 PM PDT 24
Peak memory 218400 kb
Host smart-17ea0c25-5c32-4a57-85d2-cbbf2089b7b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868970791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1868970791
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1887799828
Short name T402
Test name
Test status
Simulation time 287112406 ps
CPU time 10.22 seconds
Started Aug 12 04:56:20 PM PDT 24
Finished Aug 12 04:56:31 PM PDT 24
Peak memory 218344 kb
Host smart-251e26b9-a11b-4fb2-8b58-28b49dd9e98d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887799828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1887799828
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1545051146
Short name T825
Test name
Test status
Simulation time 2398644332 ps
CPU time 18.19 seconds
Started Aug 12 04:56:09 PM PDT 24
Finished Aug 12 04:56:27 PM PDT 24
Peak memory 218400 kb
Host smart-2916a39c-dd2a-45cc-96ac-cc56a51974a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545051146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
545051146
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3056577585
Short name T657
Test name
Test status
Simulation time 339274026 ps
CPU time 12.71 seconds
Started Aug 12 04:56:11 PM PDT 24
Finished Aug 12 04:56:24 PM PDT 24
Peak memory 226224 kb
Host smart-f65b0da9-7d5d-48e9-8bfe-59147622ebde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056577585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3056577585
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2745400055
Short name T785
Test name
Test status
Simulation time 232833719 ps
CPU time 3.65 seconds
Started Aug 12 04:56:11 PM PDT 24
Finished Aug 12 04:56:15 PM PDT 24
Peak memory 217800 kb
Host smart-c9a4947f-2582-4b3d-950a-b58336f6f711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745400055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2745400055
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.281898912
Short name T171
Test name
Test status
Simulation time 1334766903 ps
CPU time 20.91 seconds
Started Aug 12 04:56:10 PM PDT 24
Finished Aug 12 04:56:31 PM PDT 24
Peak memory 251020 kb
Host smart-9ee760e1-581c-471a-a16e-65df8df68512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281898912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.281898912
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2007025269
Short name T364
Test name
Test status
Simulation time 303831399 ps
CPU time 11.08 seconds
Started Aug 12 04:56:11 PM PDT 24
Finished Aug 12 04:56:22 PM PDT 24
Peak memory 251088 kb
Host smart-03e1888a-824e-4f22-8f52-3160495fefbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007025269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2007025269
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.442031391
Short name T731
Test name
Test status
Simulation time 4828312706 ps
CPU time 146.79 seconds
Started Aug 12 04:56:17 PM PDT 24
Finished Aug 12 04:58:44 PM PDT 24
Peak memory 267484 kb
Host smart-e02b3b73-b537-48d6-a9bf-4c857c945712
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442031391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.442031391
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.4213700630
Short name T627
Test name
Test status
Simulation time 2399281485 ps
CPU time 39.84 seconds
Started Aug 12 04:56:18 PM PDT 24
Finished Aug 12 04:56:58 PM PDT 24
Peak memory 264064 kb
Host smart-8a1d01e3-f822-4bbe-ac7c-44161e2cf8a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4213700630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.4213700630
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1665069241
Short name T30
Test name
Test status
Simulation time 13723876 ps
CPU time 0.97 seconds
Started Aug 12 04:56:12 PM PDT 24
Finished Aug 12 04:56:13 PM PDT 24
Peak memory 209392 kb
Host smart-eeed0452-ab31-4620-9b16-5faaa3a8fe53
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665069241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1665069241
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.72420575
Short name T851
Test name
Test status
Simulation time 358425338 ps
CPU time 11.02 seconds
Started Aug 12 04:57:45 PM PDT 24
Finished Aug 12 04:57:56 PM PDT 24
Peak memory 218332 kb
Host smart-2b6e3b93-5725-46fa-8665-e5b6d4954cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72420575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.72420575
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2851155404
Short name T157
Test name
Test status
Simulation time 68520348 ps
CPU time 2.5 seconds
Started Aug 12 04:57:46 PM PDT 24
Finished Aug 12 04:57:49 PM PDT 24
Peak memory 217236 kb
Host smart-034c6e42-567a-4704-91f7-cbafb7f9706e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851155404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2851155404
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1401170148
Short name T857
Test name
Test status
Simulation time 90154984 ps
CPU time 3.07 seconds
Started Aug 12 04:57:48 PM PDT 24
Finished Aug 12 04:57:51 PM PDT 24
Peak memory 222452 kb
Host smart-6ec86a66-be4f-4a59-85a4-78062c6127bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401170148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1401170148
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.261719358
Short name T631
Test name
Test status
Simulation time 264331433 ps
CPU time 13.96 seconds
Started Aug 12 04:57:44 PM PDT 24
Finished Aug 12 04:57:58 PM PDT 24
Peak memory 226124 kb
Host smart-d6c19f4e-5106-4773-b3a2-8d893564c923
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261719358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.261719358
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3476071058
Short name T771
Test name
Test status
Simulation time 2687081715 ps
CPU time 9.02 seconds
Started Aug 12 04:57:46 PM PDT 24
Finished Aug 12 04:57:56 PM PDT 24
Peak memory 226180 kb
Host smart-db9ea707-98fb-42e3-8691-c34b6c691631
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476071058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3476071058
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.957783299
Short name T850
Test name
Test status
Simulation time 679683158 ps
CPU time 23.39 seconds
Started Aug 12 04:57:44 PM PDT 24
Finished Aug 12 04:58:08 PM PDT 24
Peak memory 218416 kb
Host smart-ca6de4e2-e3c9-45d9-b78d-db6e1dddf867
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957783299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.957783299
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2928525243
Short name T48
Test name
Test status
Simulation time 299658454 ps
CPU time 9.32 seconds
Started Aug 12 04:57:45 PM PDT 24
Finished Aug 12 04:57:54 PM PDT 24
Peak memory 218408 kb
Host smart-a3071e5e-bb76-4248-b079-a7f7643fede0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928525243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2928525243
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2084126893
Short name T296
Test name
Test status
Simulation time 25876222 ps
CPU time 2.11 seconds
Started Aug 12 04:57:38 PM PDT 24
Finished Aug 12 04:57:41 PM PDT 24
Peak memory 223672 kb
Host smart-1c27cbaa-dc47-48e1-90af-32334d718f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084126893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2084126893
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.109977227
Short name T766
Test name
Test status
Simulation time 210418073 ps
CPU time 22.02 seconds
Started Aug 12 04:57:45 PM PDT 24
Finished Aug 12 04:58:07 PM PDT 24
Peak memory 251064 kb
Host smart-79dc9f46-d501-443e-b5cf-fd874179a68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109977227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.109977227
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.840925127
Short name T454
Test name
Test status
Simulation time 237300193 ps
CPU time 6.86 seconds
Started Aug 12 04:57:45 PM PDT 24
Finished Aug 12 04:57:52 PM PDT 24
Peak memory 250624 kb
Host smart-22193a76-b879-48a7-8df2-8a8c9d2f0b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840925127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.840925127
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3625388728
Short name T819
Test name
Test status
Simulation time 8835229171 ps
CPU time 54.1 seconds
Started Aug 12 04:57:45 PM PDT 24
Finished Aug 12 04:58:39 PM PDT 24
Peak memory 272908 kb
Host smart-514aaf75-ad14-4fa4-afa3-042c83761b54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625388728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3625388728
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2723636711
Short name T465
Test name
Test status
Simulation time 50737565 ps
CPU time 1.01 seconds
Started Aug 12 04:57:46 PM PDT 24
Finished Aug 12 04:57:47 PM PDT 24
Peak memory 218016 kb
Host smart-78ce7912-9bc9-4b60-ad54-6e1ec60b5e01
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723636711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2723636711
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1699824627
Short name T167
Test name
Test status
Simulation time 77868577 ps
CPU time 1.03 seconds
Started Aug 12 04:57:46 PM PDT 24
Finished Aug 12 04:57:47 PM PDT 24
Peak memory 209016 kb
Host smart-a09550c3-8018-4a6d-b3cc-16b942e27007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699824627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1699824627
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1233521132
Short name T636
Test name
Test status
Simulation time 312257946 ps
CPU time 14.44 seconds
Started Aug 12 04:57:46 PM PDT 24
Finished Aug 12 04:58:00 PM PDT 24
Peak memory 226168 kb
Host smart-1150c6b2-b83d-468c-84a2-0b5a72c2318e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233521132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1233521132
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2673558874
Short name T20
Test name
Test status
Simulation time 1023064231 ps
CPU time 19.38 seconds
Started Aug 12 04:57:43 PM PDT 24
Finished Aug 12 04:58:02 PM PDT 24
Peak memory 217544 kb
Host smart-21b2e12c-028b-46a3-b848-16e77b2420ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673558874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2673558874
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.972241060
Short name T220
Test name
Test status
Simulation time 48151972 ps
CPU time 1.57 seconds
Started Aug 12 04:57:45 PM PDT 24
Finished Aug 12 04:57:46 PM PDT 24
Peak memory 218404 kb
Host smart-269e533a-058a-41cd-bbe7-07b3411010b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972241060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.972241060
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.4204431093
Short name T824
Test name
Test status
Simulation time 1996914165 ps
CPU time 11.84 seconds
Started Aug 12 04:57:44 PM PDT 24
Finished Aug 12 04:57:56 PM PDT 24
Peak memory 226140 kb
Host smart-2f1575e1-e7ff-4e11-8680-fe65b9a00e8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204431093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.4204431093
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3928782836
Short name T652
Test name
Test status
Simulation time 1707611362 ps
CPU time 9.06 seconds
Started Aug 12 04:57:47 PM PDT 24
Finished Aug 12 04:57:56 PM PDT 24
Peak memory 226164 kb
Host smart-1b8548e2-67b9-4c04-8ac5-40df0d29d5b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928782836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3928782836
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.897384562
Short name T99
Test name
Test status
Simulation time 1594626813 ps
CPU time 8.22 seconds
Started Aug 12 04:57:47 PM PDT 24
Finished Aug 12 04:57:55 PM PDT 24
Peak memory 218484 kb
Host smart-40542b4e-a53d-4e3f-b2a9-5414e09971ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897384562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.897384562
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1149406159
Short name T290
Test name
Test status
Simulation time 149431081 ps
CPU time 2.88 seconds
Started Aug 12 04:57:45 PM PDT 24
Finished Aug 12 04:57:48 PM PDT 24
Peak memory 215036 kb
Host smart-e0db2afb-48b9-4395-9c2e-1a4110e02c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149406159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1149406159
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3666739936
Short name T297
Test name
Test status
Simulation time 286282869 ps
CPU time 34.11 seconds
Started Aug 12 04:57:46 PM PDT 24
Finished Aug 12 04:58:20 PM PDT 24
Peak memory 250912 kb
Host smart-418e2593-8590-4e1b-8906-829821a5e39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666739936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3666739936
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.4053885404
Short name T812
Test name
Test status
Simulation time 354012727 ps
CPU time 9.14 seconds
Started Aug 12 04:57:46 PM PDT 24
Finished Aug 12 04:57:56 PM PDT 24
Peak memory 250796 kb
Host smart-8af4cb9d-b780-4ff4-a381-d9506597e9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053885404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.4053885404
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.385030488
Short name T721
Test name
Test status
Simulation time 15579989758 ps
CPU time 136.73 seconds
Started Aug 12 04:57:45 PM PDT 24
Finished Aug 12 05:00:02 PM PDT 24
Peak memory 251176 kb
Host smart-c423ec78-0560-431a-9e41-1640f64711c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385030488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.385030488
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.892638943
Short name T27
Test name
Test status
Simulation time 26986876 ps
CPU time 0.94 seconds
Started Aug 12 04:57:45 PM PDT 24
Finished Aug 12 04:57:46 PM PDT 24
Peak memory 212072 kb
Host smart-75106116-1763-4e31-b28c-3d2b7ea7beb5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892638943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.892638943
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.956036851
Short name T876
Test name
Test status
Simulation time 171967854 ps
CPU time 1.41 seconds
Started Aug 12 04:57:51 PM PDT 24
Finished Aug 12 04:57:52 PM PDT 24
Peak memory 209072 kb
Host smart-45721423-ef03-4661-b459-f0c70b6b7b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956036851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.956036851
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2212944834
Short name T360
Test name
Test status
Simulation time 218931656 ps
CPU time 10.63 seconds
Started Aug 12 04:57:53 PM PDT 24
Finished Aug 12 04:58:03 PM PDT 24
Peak memory 218456 kb
Host smart-3beb4c10-9228-4853-963e-bf5348cb908d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212944834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2212944834
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.743329473
Short name T187
Test name
Test status
Simulation time 1532182066 ps
CPU time 11.06 seconds
Started Aug 12 04:57:54 PM PDT 24
Finished Aug 12 04:58:05 PM PDT 24
Peak memory 217780 kb
Host smart-cd1973e1-3ba8-473f-8e0d-34a9d21ace05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743329473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.743329473
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2145476487
Short name T743
Test name
Test status
Simulation time 99755560 ps
CPU time 1.76 seconds
Started Aug 12 04:57:50 PM PDT 24
Finished Aug 12 04:57:52 PM PDT 24
Peak memory 218480 kb
Host smart-f4a9c3a5-03b0-44e1-8347-02f89ed7270b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145476487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2145476487
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1273231898
Short name T560
Test name
Test status
Simulation time 400519017 ps
CPU time 6.71 seconds
Started Aug 12 04:57:54 PM PDT 24
Finished Aug 12 04:58:01 PM PDT 24
Peak memory 226188 kb
Host smart-8a087c03-64d7-454b-9019-8d855bf6e329
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273231898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1273231898
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2754328081
Short name T421
Test name
Test status
Simulation time 419805437 ps
CPU time 10.46 seconds
Started Aug 12 04:57:52 PM PDT 24
Finished Aug 12 04:58:03 PM PDT 24
Peak memory 218404 kb
Host smart-1da66b25-3b9d-41c0-a2d5-83cbc40b83b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754328081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2754328081
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.861104866
Short name T397
Test name
Test status
Simulation time 1001091502 ps
CPU time 10.17 seconds
Started Aug 12 04:57:50 PM PDT 24
Finished Aug 12 04:58:01 PM PDT 24
Peak memory 218436 kb
Host smart-4f0f61aa-1070-44a4-92b7-a6b071f9b0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861104866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.861104866
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2759734852
Short name T823
Test name
Test status
Simulation time 187839482 ps
CPU time 2.52 seconds
Started Aug 12 04:57:51 PM PDT 24
Finished Aug 12 04:57:54 PM PDT 24
Peak memory 222872 kb
Host smart-3d833484-aaf6-409d-afdb-09a880bff67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759734852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2759734852
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2430469264
Short name T332
Test name
Test status
Simulation time 369802653 ps
CPU time 19.43 seconds
Started Aug 12 04:57:52 PM PDT 24
Finished Aug 12 04:58:11 PM PDT 24
Peak memory 251144 kb
Host smart-c2de35bf-ba9d-43fe-82ff-8d822e5bd770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430469264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2430469264
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3230323910
Short name T811
Test name
Test status
Simulation time 181477284 ps
CPU time 8.3 seconds
Started Aug 12 04:57:51 PM PDT 24
Finished Aug 12 04:58:00 PM PDT 24
Peak memory 251032 kb
Host smart-b727a75a-ba71-448f-9915-5ffe6766a4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230323910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3230323910
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3228972564
Short name T691
Test name
Test status
Simulation time 17058353040 ps
CPU time 159.43 seconds
Started Aug 12 04:57:51 PM PDT 24
Finished Aug 12 05:00:31 PM PDT 24
Peak memory 271044 kb
Host smart-db062179-7a0e-4b3c-8914-1fd2fc82803f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228972564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3228972564
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2858463597
Short name T880
Test name
Test status
Simulation time 12597627 ps
CPU time 0.99 seconds
Started Aug 12 04:57:53 PM PDT 24
Finished Aug 12 04:57:55 PM PDT 24
Peak memory 209184 kb
Host smart-831f8ad7-dde8-412a-a7fa-a729b6229144
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858463597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2858463597
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.4073111692
Short name T693
Test name
Test status
Simulation time 19034364 ps
CPU time 0.96 seconds
Started Aug 12 04:57:52 PM PDT 24
Finished Aug 12 04:57:53 PM PDT 24
Peak memory 208940 kb
Host smart-4e5e8431-fb2d-48ad-9b38-1d395f45d25b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073111692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.4073111692
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3274686266
Short name T11
Test name
Test status
Simulation time 269243697 ps
CPU time 12.13 seconds
Started Aug 12 04:57:54 PM PDT 24
Finished Aug 12 04:58:06 PM PDT 24
Peak memory 218352 kb
Host smart-40aae0b9-ca7e-4c95-ab65-8f92bb9b6ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274686266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3274686266
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1849511800
Short name T684
Test name
Test status
Simulation time 470914382 ps
CPU time 5.9 seconds
Started Aug 12 04:57:51 PM PDT 24
Finished Aug 12 04:57:57 PM PDT 24
Peak memory 217796 kb
Host smart-877bee18-d945-46ab-a13e-40842434319d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849511800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1849511800
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1841881866
Short name T822
Test name
Test status
Simulation time 29431122 ps
CPU time 1.95 seconds
Started Aug 12 04:57:50 PM PDT 24
Finished Aug 12 04:57:52 PM PDT 24
Peak memory 218416 kb
Host smart-bd22eb12-b370-4a70-8154-6c898cf68100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841881866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1841881866
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1300512718
Short name T759
Test name
Test status
Simulation time 1455086953 ps
CPU time 14.76 seconds
Started Aug 12 04:57:54 PM PDT 24
Finished Aug 12 04:58:09 PM PDT 24
Peak memory 226140 kb
Host smart-f0ecf13d-f5d1-4030-a36e-174e7daa5f94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300512718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1300512718
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.526962478
Short name T285
Test name
Test status
Simulation time 1060506967 ps
CPU time 11.82 seconds
Started Aug 12 04:57:51 PM PDT 24
Finished Aug 12 04:58:03 PM PDT 24
Peak memory 226108 kb
Host smart-6aaad540-8be3-4ba7-9d48-816b968234d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526962478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.526962478
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3761016009
Short name T530
Test name
Test status
Simulation time 427358417 ps
CPU time 6.15 seconds
Started Aug 12 04:57:54 PM PDT 24
Finished Aug 12 04:58:00 PM PDT 24
Peak memory 218448 kb
Host smart-447e3eac-7920-4ca5-8236-1d8a13cb958c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761016009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3761016009
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2536499485
Short name T344
Test name
Test status
Simulation time 766981757 ps
CPU time 7.86 seconds
Started Aug 12 04:57:51 PM PDT 24
Finished Aug 12 04:57:59 PM PDT 24
Peak memory 218492 kb
Host smart-005e8f4c-de7c-4de9-a69a-c3f23a94515d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536499485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2536499485
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1851047878
Short name T756
Test name
Test status
Simulation time 31623251 ps
CPU time 1.82 seconds
Started Aug 12 04:57:53 PM PDT 24
Finished Aug 12 04:57:55 PM PDT 24
Peak memory 217792 kb
Host smart-97ec5d15-1dac-47ce-9737-8a0a77298172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851047878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1851047878
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1329625737
Short name T339
Test name
Test status
Simulation time 318580253 ps
CPU time 37.73 seconds
Started Aug 12 04:57:52 PM PDT 24
Finished Aug 12 04:58:30 PM PDT 24
Peak memory 247664 kb
Host smart-01038917-c5e9-4594-a881-c1dd28d97896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329625737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1329625737
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3972833607
Short name T577
Test name
Test status
Simulation time 126473296 ps
CPU time 6.28 seconds
Started Aug 12 04:57:52 PM PDT 24
Finished Aug 12 04:57:58 PM PDT 24
Peak memory 247300 kb
Host smart-a5ae379a-4785-4b9b-ae5c-9e3a1801ea9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972833607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3972833607
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.553033933
Short name T426
Test name
Test status
Simulation time 8242399787 ps
CPU time 80.73 seconds
Started Aug 12 04:57:52 PM PDT 24
Finished Aug 12 04:59:13 PM PDT 24
Peak memory 267520 kb
Host smart-d5e09a08-669c-4fa6-84cf-5f16037bfa71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553033933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.553033933
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3969039856
Short name T791
Test name
Test status
Simulation time 39038091 ps
CPU time 0.77 seconds
Started Aug 12 04:57:51 PM PDT 24
Finished Aug 12 04:57:52 PM PDT 24
Peak memory 208936 kb
Host smart-388c931f-19e1-435b-a9da-153470d7f136
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969039856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3969039856
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2833596515
Short name T222
Test name
Test status
Simulation time 54151237 ps
CPU time 1.08 seconds
Started Aug 12 04:57:59 PM PDT 24
Finished Aug 12 04:58:01 PM PDT 24
Peak memory 209008 kb
Host smart-23be3558-7a1d-4ad9-a06b-e1e905befd26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833596515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2833596515
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2193833716
Short name T158
Test name
Test status
Simulation time 283621179 ps
CPU time 13.79 seconds
Started Aug 12 04:57:52 PM PDT 24
Finished Aug 12 04:58:05 PM PDT 24
Peak memory 218360 kb
Host smart-f515dafe-0179-4d20-a650-2562d1666fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193833716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2193833716
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.226896462
Short name T650
Test name
Test status
Simulation time 967440895 ps
CPU time 12.66 seconds
Started Aug 12 04:57:52 PM PDT 24
Finished Aug 12 04:58:05 PM PDT 24
Peak memory 217596 kb
Host smart-ec1a2292-4298-478d-9c95-930b30cfa84e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226896462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.226896462
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1509567994
Short name T638
Test name
Test status
Simulation time 274545422 ps
CPU time 2.57 seconds
Started Aug 12 04:57:53 PM PDT 24
Finished Aug 12 04:57:55 PM PDT 24
Peak memory 222308 kb
Host smart-b7c42dd2-774a-41e7-bbb7-da292e9bdfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509567994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1509567994
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3219858879
Short name T723
Test name
Test status
Simulation time 259150854 ps
CPU time 10.89 seconds
Started Aug 12 04:58:00 PM PDT 24
Finished Aug 12 04:58:11 PM PDT 24
Peak memory 219708 kb
Host smart-380b994c-5148-497a-8d5e-9d1ec86f191d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219858879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3219858879
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3628698016
Short name T618
Test name
Test status
Simulation time 977028834 ps
CPU time 27.98 seconds
Started Aug 12 04:58:00 PM PDT 24
Finished Aug 12 04:58:28 PM PDT 24
Peak memory 226096 kb
Host smart-b8e64a16-3a66-45a2-a123-5dd0dd496059
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628698016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3628698016
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3171857836
Short name T57
Test name
Test status
Simulation time 529955568 ps
CPU time 14.55 seconds
Started Aug 12 04:58:01 PM PDT 24
Finished Aug 12 04:58:15 PM PDT 24
Peak memory 218440 kb
Host smart-8c48a813-9ab0-4858-bb85-356ef2f58560
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171857836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3171857836
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1769417689
Short name T387
Test name
Test status
Simulation time 484074515 ps
CPU time 10.83 seconds
Started Aug 12 04:57:52 PM PDT 24
Finished Aug 12 04:58:03 PM PDT 24
Peak memory 218092 kb
Host smart-a0d1c2df-c83e-4b00-9f23-ccf4be7bdff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769417689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1769417689
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2430238223
Short name T573
Test name
Test status
Simulation time 923659537 ps
CPU time 6.04 seconds
Started Aug 12 04:57:53 PM PDT 24
Finished Aug 12 04:57:59 PM PDT 24
Peak memory 223528 kb
Host smart-e9a9804c-cfe3-4746-8e0f-0748adb21a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430238223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2430238223
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.792055958
Short name T499
Test name
Test status
Simulation time 3212131342 ps
CPU time 26.52 seconds
Started Aug 12 04:57:52 PM PDT 24
Finished Aug 12 04:58:19 PM PDT 24
Peak memory 251160 kb
Host smart-68cfbe76-456e-4301-88b5-a2a5fef78eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792055958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.792055958
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.223645676
Short name T302
Test name
Test status
Simulation time 518191431 ps
CPU time 6.94 seconds
Started Aug 12 04:57:52 PM PDT 24
Finished Aug 12 04:57:59 PM PDT 24
Peak memory 247276 kb
Host smart-74c33286-1cb1-4c17-b256-9904be621169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223645676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.223645676
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2554391768
Short name T16
Test name
Test status
Simulation time 19746155472 ps
CPU time 178.63 seconds
Started Aug 12 04:57:58 PM PDT 24
Finished Aug 12 05:00:57 PM PDT 24
Peak memory 274232 kb
Host smart-056fca29-6a92-41f8-9378-c2dd027263f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554391768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2554391768
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2493972846
Short name T243
Test name
Test status
Simulation time 48331289 ps
CPU time 0.85 seconds
Started Aug 12 04:57:53 PM PDT 24
Finished Aug 12 04:57:54 PM PDT 24
Peak memory 209024 kb
Host smart-db99029b-ab5a-48a9-821e-960eeea00e77
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493972846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2493972846
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2225636554
Short name T839
Test name
Test status
Simulation time 13722485 ps
CPU time 1.02 seconds
Started Aug 12 04:58:01 PM PDT 24
Finished Aug 12 04:58:02 PM PDT 24
Peak memory 208992 kb
Host smart-4b6f47d2-7823-460b-ab6a-67f92aeefe8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225636554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2225636554
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.192819136
Short name T340
Test name
Test status
Simulation time 857069200 ps
CPU time 11.74 seconds
Started Aug 12 04:57:58 PM PDT 24
Finished Aug 12 04:58:10 PM PDT 24
Peak memory 218360 kb
Host smart-b2ba9bdd-734f-45ec-9429-3c4087ff5a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192819136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.192819136
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3062227859
Short name T649
Test name
Test status
Simulation time 3160017758 ps
CPU time 17.92 seconds
Started Aug 12 04:58:01 PM PDT 24
Finished Aug 12 04:58:19 PM PDT 24
Peak memory 217896 kb
Host smart-bafc1ffd-51b7-49be-ba34-d27c161d5dd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062227859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3062227859
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2933862973
Short name T538
Test name
Test status
Simulation time 185640176 ps
CPU time 4.51 seconds
Started Aug 12 04:57:59 PM PDT 24
Finished Aug 12 04:58:04 PM PDT 24
Peak memory 218348 kb
Host smart-e90a50fa-ef02-4fa1-a31b-4c189c4ab8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933862973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2933862973
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2866086249
Short name T597
Test name
Test status
Simulation time 1260033753 ps
CPU time 14.23 seconds
Started Aug 12 04:57:59 PM PDT 24
Finished Aug 12 04:58:14 PM PDT 24
Peak memory 226208 kb
Host smart-c3f4e2dd-74ff-482e-ad3b-e04b478de838
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866086249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2866086249
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2689553440
Short name T707
Test name
Test status
Simulation time 738107235 ps
CPU time 10.06 seconds
Started Aug 12 04:58:00 PM PDT 24
Finished Aug 12 04:58:11 PM PDT 24
Peak memory 226116 kb
Host smart-b83de879-d793-403e-a6c3-06fbcf752ef8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689553440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2689553440
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3519115720
Short name T629
Test name
Test status
Simulation time 426733522 ps
CPU time 12.03 seconds
Started Aug 12 04:57:59 PM PDT 24
Finished Aug 12 04:58:11 PM PDT 24
Peak memory 225924 kb
Host smart-dbd77ee9-3a17-4814-a781-0eb39cb94737
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519115720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3519115720
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.934400797
Short name T626
Test name
Test status
Simulation time 622520430 ps
CPU time 5.88 seconds
Started Aug 12 04:57:58 PM PDT 24
Finished Aug 12 04:58:04 PM PDT 24
Peak memory 218468 kb
Host smart-83cd00dc-25d7-43e8-910e-ab75211e03e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934400797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.934400797
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2528762567
Short name T242
Test name
Test status
Simulation time 179872423 ps
CPU time 3.34 seconds
Started Aug 12 04:57:57 PM PDT 24
Finished Aug 12 04:58:00 PM PDT 24
Peak memory 217824 kb
Host smart-09f37a8d-9974-4c3f-a3d2-3e2361676e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528762567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2528762567
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3921303575
Short name T713
Test name
Test status
Simulation time 171116579 ps
CPU time 23.64 seconds
Started Aug 12 04:58:00 PM PDT 24
Finished Aug 12 04:58:23 PM PDT 24
Peak memory 251100 kb
Host smart-b0cdab59-447d-446f-9bef-4d2fed62d5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921303575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3921303575
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.571452393
Short name T836
Test name
Test status
Simulation time 271821361 ps
CPU time 7.78 seconds
Started Aug 12 04:57:59 PM PDT 24
Finished Aug 12 04:58:07 PM PDT 24
Peak memory 251016 kb
Host smart-ed497cd3-e312-45b2-a6d4-1731468ceac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571452393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.571452393
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2079711442
Short name T502
Test name
Test status
Simulation time 25547708059 ps
CPU time 855.15 seconds
Started Aug 12 04:58:00 PM PDT 24
Finished Aug 12 05:12:15 PM PDT 24
Peak memory 283560 kb
Host smart-3ec9dc37-37fc-4138-8bf3-b9d8144a2836
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079711442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2079711442
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1939020691
Short name T37
Test name
Test status
Simulation time 20199300 ps
CPU time 0.97 seconds
Started Aug 12 04:57:59 PM PDT 24
Finished Aug 12 04:58:00 PM PDT 24
Peak memory 217888 kb
Host smart-bc38b75c-d6fa-4be0-b519-daae3bafb438
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939020691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1939020691
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.113025216
Short name T224
Test name
Test status
Simulation time 60860756 ps
CPU time 1.04 seconds
Started Aug 12 04:58:06 PM PDT 24
Finished Aug 12 04:58:07 PM PDT 24
Peak memory 208996 kb
Host smart-935a3b82-62eb-42a3-9580-b87699e54595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113025216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.113025216
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3066464707
Short name T533
Test name
Test status
Simulation time 1205836262 ps
CPU time 11.68 seconds
Started Aug 12 04:58:04 PM PDT 24
Finished Aug 12 04:58:16 PM PDT 24
Peak memory 218376 kb
Host smart-add61a2f-9d8c-478c-80a5-9a42be135d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066464707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3066464707
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3635788802
Short name T725
Test name
Test status
Simulation time 1733521284 ps
CPU time 4.63 seconds
Started Aug 12 04:57:59 PM PDT 24
Finished Aug 12 04:58:04 PM PDT 24
Peak memory 217840 kb
Host smart-e58e0386-434a-4f05-99f9-58277b02129c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635788802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3635788802
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3449533830
Short name T272
Test name
Test status
Simulation time 197277111 ps
CPU time 2.46 seconds
Started Aug 12 04:58:00 PM PDT 24
Finished Aug 12 04:58:03 PM PDT 24
Peak memory 218344 kb
Host smart-727cbd8b-8ecf-4bc4-a96e-fc4c0e1ef8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449533830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3449533830
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1944062098
Short name T714
Test name
Test status
Simulation time 16686142146 ps
CPU time 25.78 seconds
Started Aug 12 04:58:05 PM PDT 24
Finished Aug 12 04:58:31 PM PDT 24
Peak memory 219692 kb
Host smart-46cd1d8c-4a22-456e-aacf-78ffa8859fed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944062098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1944062098
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2556417115
Short name T544
Test name
Test status
Simulation time 967508850 ps
CPU time 13.29 seconds
Started Aug 12 04:58:06 PM PDT 24
Finished Aug 12 04:58:19 PM PDT 24
Peak memory 226064 kb
Host smart-51d0da9d-79ee-4f1e-9e79-7b6f8b5a9c97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556417115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2556417115
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3265750735
Short name T583
Test name
Test status
Simulation time 338379184 ps
CPU time 13.35 seconds
Started Aug 12 04:58:06 PM PDT 24
Finished Aug 12 04:58:20 PM PDT 24
Peak memory 218380 kb
Host smart-f87653ef-f858-4ed7-9a57-1e8f8250b82c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265750735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3265750735
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.991492153
Short name T531
Test name
Test status
Simulation time 693269059 ps
CPU time 7.98 seconds
Started Aug 12 04:57:59 PM PDT 24
Finished Aug 12 04:58:07 PM PDT 24
Peak memory 225452 kb
Host smart-aa78b16d-2fba-494f-aadb-1034ba2f08bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991492153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.991492153
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3030839104
Short name T727
Test name
Test status
Simulation time 81801288 ps
CPU time 1.11 seconds
Started Aug 12 04:58:04 PM PDT 24
Finished Aug 12 04:58:06 PM PDT 24
Peak memory 217792 kb
Host smart-95dd85bb-4b02-45b3-ab4f-a667f270231f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030839104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3030839104
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3538865513
Short name T532
Test name
Test status
Simulation time 956401956 ps
CPU time 22.94 seconds
Started Aug 12 04:57:59 PM PDT 24
Finished Aug 12 04:58:22 PM PDT 24
Peak memory 250996 kb
Host smart-069b1d41-68ec-4af7-89f8-2c0c20c865b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538865513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3538865513
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3198520731
Short name T80
Test name
Test status
Simulation time 102421003 ps
CPU time 7.12 seconds
Started Aug 12 04:57:57 PM PDT 24
Finished Aug 12 04:58:04 PM PDT 24
Peak memory 251080 kb
Host smart-02392347-1b22-47e0-8859-8ebeb2b6e8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198520731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3198520731
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1932881373
Short name T318
Test name
Test status
Simulation time 7535992912 ps
CPU time 41.43 seconds
Started Aug 12 04:58:06 PM PDT 24
Finished Aug 12 04:58:47 PM PDT 24
Peak memory 245088 kb
Host smart-977c14a1-87b7-4468-bb22-d7fe35444018
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932881373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1932881373
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.3056530155
Short name T43
Test name
Test status
Simulation time 8140760954 ps
CPU time 89.99 seconds
Started Aug 12 04:58:03 PM PDT 24
Finished Aug 12 04:59:33 PM PDT 24
Peak memory 276376 kb
Host smart-68060336-7306-49b6-a828-1a27739abfaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3056530155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.3056530155
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1800724947
Short name T370
Test name
Test status
Simulation time 36338667 ps
CPU time 0.92 seconds
Started Aug 12 04:58:01 PM PDT 24
Finished Aug 12 04:58:02 PM PDT 24
Peak memory 209132 kb
Host smart-3f6d2854-d628-43d6-81c7-ad1e780d93ed
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800724947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1800724947
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.4117770093
Short name T542
Test name
Test status
Simulation time 181583909 ps
CPU time 0.87 seconds
Started Aug 12 04:58:07 PM PDT 24
Finished Aug 12 04:58:08 PM PDT 24
Peak memory 208844 kb
Host smart-7d0ea13f-28d9-4fa5-869a-d39dd96fc765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117770093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.4117770093
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.649818477
Short name T838
Test name
Test status
Simulation time 3208043651 ps
CPU time 11.97 seconds
Started Aug 12 04:58:04 PM PDT 24
Finished Aug 12 04:58:16 PM PDT 24
Peak memory 226284 kb
Host smart-52985eb9-0127-48c6-81a3-b2d1bdf34d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649818477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.649818477
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.296354611
Short name T862
Test name
Test status
Simulation time 722438744 ps
CPU time 5.11 seconds
Started Aug 12 04:58:06 PM PDT 24
Finished Aug 12 04:58:11 PM PDT 24
Peak memory 217612 kb
Host smart-fa147e58-dd6d-4dee-9836-d9500baf895b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296354611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.296354611
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1029562371
Short name T335
Test name
Test status
Simulation time 71972348 ps
CPU time 2.02 seconds
Started Aug 12 04:58:04 PM PDT 24
Finished Aug 12 04:58:06 PM PDT 24
Peak memory 218404 kb
Host smart-80e36dc3-0dee-4622-af90-930928807878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029562371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1029562371
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3641048950
Short name T853
Test name
Test status
Simulation time 751597204 ps
CPU time 7.96 seconds
Started Aug 12 04:58:06 PM PDT 24
Finished Aug 12 04:58:14 PM PDT 24
Peak memory 226208 kb
Host smart-18fff51d-bbcc-4d0d-8a64-b369a8b622ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641048950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3641048950
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2955770386
Short name T484
Test name
Test status
Simulation time 1316075725 ps
CPU time 12.71 seconds
Started Aug 12 04:58:06 PM PDT 24
Finished Aug 12 04:58:19 PM PDT 24
Peak memory 226092 kb
Host smart-a1ed2d6d-97dd-4781-b675-683e5637003f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955770386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2955770386
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3425875678
Short name T348
Test name
Test status
Simulation time 729853833 ps
CPU time 11.26 seconds
Started Aug 12 04:58:05 PM PDT 24
Finished Aug 12 04:58:16 PM PDT 24
Peak memory 218352 kb
Host smart-78aaa4ed-bf3b-4275-a508-48aca124ad5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425875678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
3425875678
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.104100053
Short name T659
Test name
Test status
Simulation time 181198930 ps
CPU time 8.4 seconds
Started Aug 12 04:58:09 PM PDT 24
Finished Aug 12 04:58:18 PM PDT 24
Peak memory 225624 kb
Host smart-5a09b632-cebd-4fbc-9b92-34c60ea9c9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104100053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.104100053
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2750812529
Short name T293
Test name
Test status
Simulation time 160033223 ps
CPU time 2.89 seconds
Started Aug 12 04:58:08 PM PDT 24
Finished Aug 12 04:58:11 PM PDT 24
Peak memory 214644 kb
Host smart-4a2c6129-215e-4f1f-b900-9932ffbf7431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750812529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2750812529
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2034446799
Short name T367
Test name
Test status
Simulation time 430406897 ps
CPU time 18.76 seconds
Started Aug 12 04:58:03 PM PDT 24
Finished Aug 12 04:58:22 PM PDT 24
Peak memory 251064 kb
Host smart-02643dbb-4549-4c97-b3c8-bd19861cf5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034446799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2034446799
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1961915576
Short name T456
Test name
Test status
Simulation time 249665024 ps
CPU time 6.14 seconds
Started Aug 12 04:58:07 PM PDT 24
Finished Aug 12 04:58:13 PM PDT 24
Peak memory 247080 kb
Host smart-3a5e2b2b-25eb-4ac0-92d9-c35dec118062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961915576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1961915576
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3397729795
Short name T288
Test name
Test status
Simulation time 20521479614 ps
CPU time 215.92 seconds
Started Aug 12 04:58:05 PM PDT 24
Finished Aug 12 05:01:41 PM PDT 24
Peak memory 283868 kb
Host smart-ad235bed-98f9-412c-8d73-9fd41456eba5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397729795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3397729795
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3398552930
Short name T240
Test name
Test status
Simulation time 18130744 ps
CPU time 1.26 seconds
Started Aug 12 04:58:05 PM PDT 24
Finished Aug 12 04:58:06 PM PDT 24
Peak memory 217956 kb
Host smart-bbb152ec-2f4f-4c95-a288-cc0a65a2ed8d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398552930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3398552930
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.798113967
Short name T801
Test name
Test status
Simulation time 103490165 ps
CPU time 0.9 seconds
Started Aug 12 04:58:15 PM PDT 24
Finished Aug 12 04:58:16 PM PDT 24
Peak memory 208888 kb
Host smart-c19e55fc-e649-4ef5-a610-b522fabd91b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798113967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.798113967
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3466014655
Short name T651
Test name
Test status
Simulation time 1123055548 ps
CPU time 7.28 seconds
Started Aug 12 04:58:14 PM PDT 24
Finished Aug 12 04:58:21 PM PDT 24
Peak memory 218276 kb
Host smart-a6384c63-8f77-4a49-825b-6ff2812e31e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466014655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3466014655
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3753742218
Short name T321
Test name
Test status
Simulation time 610590181 ps
CPU time 2.55 seconds
Started Aug 12 04:58:17 PM PDT 24
Finished Aug 12 04:58:19 PM PDT 24
Peak memory 217764 kb
Host smart-30c12cc2-72e6-4c33-a151-460dca629696
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753742218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3753742218
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2095375198
Short name T300
Test name
Test status
Simulation time 22569712 ps
CPU time 1.56 seconds
Started Aug 12 04:58:04 PM PDT 24
Finished Aug 12 04:58:06 PM PDT 24
Peak memory 218352 kb
Host smart-9a06b996-6fdb-4ca0-a9a5-6fdd8eb1a5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095375198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2095375198
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2179701001
Short name T168
Test name
Test status
Simulation time 1960517895 ps
CPU time 14.1 seconds
Started Aug 12 04:58:13 PM PDT 24
Finished Aug 12 04:58:27 PM PDT 24
Peak memory 219068 kb
Host smart-1a2ad0cc-c0bd-46f7-a09d-d8bcb5256770
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179701001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2179701001
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1377971420
Short name T802
Test name
Test status
Simulation time 1541747767 ps
CPU time 12.22 seconds
Started Aug 12 04:58:13 PM PDT 24
Finished Aug 12 04:58:26 PM PDT 24
Peak memory 226092 kb
Host smart-9493c78d-1557-4310-a6ed-1bcf2a017461
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377971420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1377971420
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1016630179
Short name T856
Test name
Test status
Simulation time 250248938 ps
CPU time 10.57 seconds
Started Aug 12 04:58:14 PM PDT 24
Finished Aug 12 04:58:25 PM PDT 24
Peak memory 218500 kb
Host smart-c8a5f489-e3ed-478c-9043-cddd020d0e58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016630179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1016630179
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2826109118
Short name T452
Test name
Test status
Simulation time 278692077 ps
CPU time 7.88 seconds
Started Aug 12 04:58:14 PM PDT 24
Finished Aug 12 04:58:22 PM PDT 24
Peak memory 218432 kb
Host smart-37ce940b-ba97-4ed4-a813-bcbb98eb4ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826109118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2826109118
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3136164606
Short name T64
Test name
Test status
Simulation time 85083749 ps
CPU time 2.92 seconds
Started Aug 12 04:58:07 PM PDT 24
Finished Aug 12 04:58:10 PM PDT 24
Peak memory 217788 kb
Host smart-35eb5854-d0df-4d5a-b1e2-034f617bb0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136164606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3136164606
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3779045075
Short name T817
Test name
Test status
Simulation time 348414609 ps
CPU time 28.16 seconds
Started Aug 12 04:58:10 PM PDT 24
Finished Aug 12 04:58:38 PM PDT 24
Peak memory 251116 kb
Host smart-b6e0c1fe-b5c6-47b6-91a7-96163fe27756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779045075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3779045075
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2815761235
Short name T843
Test name
Test status
Simulation time 58955712 ps
CPU time 6.71 seconds
Started Aug 12 04:58:10 PM PDT 24
Finished Aug 12 04:58:17 PM PDT 24
Peak memory 250612 kb
Host smart-cec0b921-1e1a-4c9b-8651-15179dd01147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815761235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2815761235
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3773806791
Short name T399
Test name
Test status
Simulation time 10502056394 ps
CPU time 63.84 seconds
Started Aug 12 04:58:17 PM PDT 24
Finished Aug 12 04:59:21 PM PDT 24
Peak memory 249744 kb
Host smart-ab0e47e9-7852-4a10-85f2-7c2ce47f5c41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773806791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3773806791
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2996442817
Short name T425
Test name
Test status
Simulation time 40927957 ps
CPU time 1.14 seconds
Started Aug 12 04:58:07 PM PDT 24
Finished Aug 12 04:58:08 PM PDT 24
Peak memory 212096 kb
Host smart-ed13cd35-81c2-44e8-9e6d-5f3fe059c9d8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996442817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2996442817
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2837305699
Short name T279
Test name
Test status
Simulation time 76353848 ps
CPU time 1.07 seconds
Started Aug 12 04:58:13 PM PDT 24
Finished Aug 12 04:58:14 PM PDT 24
Peak memory 209104 kb
Host smart-e6dd28a4-12ac-40c1-8feb-ea9df599611b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837305699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2837305699
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2582677924
Short name T311
Test name
Test status
Simulation time 1731031084 ps
CPU time 15.32 seconds
Started Aug 12 04:58:18 PM PDT 24
Finished Aug 12 04:58:34 PM PDT 24
Peak memory 226224 kb
Host smart-1c46aac5-cc71-45a9-ba33-0ec209d6e3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582677924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2582677924
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1485710651
Short name T672
Test name
Test status
Simulation time 1608984152 ps
CPU time 5.66 seconds
Started Aug 12 04:58:16 PM PDT 24
Finished Aug 12 04:58:21 PM PDT 24
Peak memory 217608 kb
Host smart-3570d17d-0a33-43a1-ae39-584535047c0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485710651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1485710651
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.507106225
Short name T245
Test name
Test status
Simulation time 39655844 ps
CPU time 2.64 seconds
Started Aug 12 04:58:13 PM PDT 24
Finished Aug 12 04:58:16 PM PDT 24
Peak memory 222424 kb
Host smart-beab33d1-5ccd-4728-92f0-785747cb238b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507106225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.507106225
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3764287036
Short name T717
Test name
Test status
Simulation time 787881411 ps
CPU time 18.28 seconds
Started Aug 12 04:58:16 PM PDT 24
Finished Aug 12 04:58:34 PM PDT 24
Peak memory 226140 kb
Host smart-2ec0a5fc-da16-47d8-af79-45b4c51b93d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764287036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3764287036
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.341947024
Short name T610
Test name
Test status
Simulation time 2245381843 ps
CPU time 12.87 seconds
Started Aug 12 04:58:13 PM PDT 24
Finished Aug 12 04:58:26 PM PDT 24
Peak memory 226168 kb
Host smart-072c2614-2904-4a48-8e67-51284747362e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341947024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.341947024
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3172966635
Short name T427
Test name
Test status
Simulation time 199058784 ps
CPU time 6.14 seconds
Started Aug 12 04:58:16 PM PDT 24
Finished Aug 12 04:58:23 PM PDT 24
Peak memory 218420 kb
Host smart-1af32464-8ea0-4eda-ad9c-8d53393762ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172966635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3172966635
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1417635212
Short name T458
Test name
Test status
Simulation time 222575558 ps
CPU time 10.18 seconds
Started Aug 12 04:58:15 PM PDT 24
Finished Aug 12 04:58:26 PM PDT 24
Peak memory 218488 kb
Host smart-57461bef-220c-410b-a78e-f01c6a7a6de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417635212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1417635212
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.545816283
Short name T547
Test name
Test status
Simulation time 47651669 ps
CPU time 2.54 seconds
Started Aug 12 04:58:15 PM PDT 24
Finished Aug 12 04:58:18 PM PDT 24
Peak memory 214544 kb
Host smart-dd566864-2529-4d42-b154-a4a7e5087e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545816283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.545816283
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2275079655
Short name T860
Test name
Test status
Simulation time 247995835 ps
CPU time 19.73 seconds
Started Aug 12 04:58:14 PM PDT 24
Finished Aug 12 04:58:34 PM PDT 24
Peak memory 251096 kb
Host smart-208a34f8-bc26-4403-92a3-f78c5bc93d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275079655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2275079655
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1093240860
Short name T265
Test name
Test status
Simulation time 88277953 ps
CPU time 6.82 seconds
Started Aug 12 04:58:14 PM PDT 24
Finished Aug 12 04:58:21 PM PDT 24
Peak memory 250900 kb
Host smart-932a9761-7fdc-413e-bcc6-b7e93fa3d6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093240860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1093240860
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3520563466
Short name T62
Test name
Test status
Simulation time 4065377513 ps
CPU time 98.49 seconds
Started Aug 12 04:58:18 PM PDT 24
Finished Aug 12 04:59:56 PM PDT 24
Peak memory 283872 kb
Host smart-2a4e3fbf-13d4-49d2-bbe9-b237137fd706
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520563466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3520563466
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.2277227643
Short name T148
Test name
Test status
Simulation time 8578020870 ps
CPU time 80.12 seconds
Started Aug 12 04:58:13 PM PDT 24
Finished Aug 12 04:59:34 PM PDT 24
Peak memory 267576 kb
Host smart-8b6dbc82-0d5e-4d9d-a8e9-43a6fefe9da9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2277227643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.2277227643
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1635555675
Short name T386
Test name
Test status
Simulation time 33067120 ps
CPU time 0.99 seconds
Started Aug 12 04:58:15 PM PDT 24
Finished Aug 12 04:58:16 PM PDT 24
Peak memory 213096 kb
Host smart-cbd51db3-006c-48d9-b014-2b3fad022a60
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635555675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1635555675
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2912904653
Short name T346
Test name
Test status
Simulation time 19166204 ps
CPU time 0.91 seconds
Started Aug 12 04:56:18 PM PDT 24
Finished Aug 12 04:56:19 PM PDT 24
Peak memory 208920 kb
Host smart-05887cb7-9ae4-4905-b383-112d82d6a93c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912904653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2912904653
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1462471126
Short name T453
Test name
Test status
Simulation time 12025473 ps
CPU time 0.86 seconds
Started Aug 12 04:56:18 PM PDT 24
Finished Aug 12 04:56:19 PM PDT 24
Peak memory 208748 kb
Host smart-ae0e2f22-d56d-4ceb-9082-bd5cb35c0a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462471126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1462471126
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.302680090
Short name T690
Test name
Test status
Simulation time 420953198 ps
CPU time 17.7 seconds
Started Aug 12 04:56:20 PM PDT 24
Finished Aug 12 04:56:38 PM PDT 24
Peak memory 218364 kb
Host smart-6c754f99-4272-45bd-834a-61a2c9a227c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302680090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.302680090
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1123176942
Short name T866
Test name
Test status
Simulation time 271160637 ps
CPU time 3.6 seconds
Started Aug 12 04:56:17 PM PDT 24
Finished Aug 12 04:56:20 PM PDT 24
Peak memory 217736 kb
Host smart-58f17028-732e-4d9d-88b3-85a0d3a96b02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123176942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1123176942
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3544289962
Short name T428
Test name
Test status
Simulation time 2799394794 ps
CPU time 27.6 seconds
Started Aug 12 04:56:17 PM PDT 24
Finished Aug 12 04:56:45 PM PDT 24
Peak memory 219024 kb
Host smart-3d3a3c55-ef47-4887-84c6-e31e36c6d795
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544289962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3544289962
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2894895409
Short name T556
Test name
Test status
Simulation time 848521796 ps
CPU time 6.35 seconds
Started Aug 12 04:56:19 PM PDT 24
Finished Aug 12 04:56:26 PM PDT 24
Peak memory 217976 kb
Host smart-7808a47f-2801-4748-85a1-5e9b7574e4ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894895409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
894895409
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1506904037
Short name T826
Test name
Test status
Simulation time 3265314335 ps
CPU time 13.58 seconds
Started Aug 12 04:56:16 PM PDT 24
Finished Aug 12 04:56:30 PM PDT 24
Peak memory 218600 kb
Host smart-6a8c693a-a8be-498e-acac-b04925729a09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506904037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1506904037
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3141019899
Short name T68
Test name
Test status
Simulation time 2326284971 ps
CPU time 32.14 seconds
Started Aug 12 04:56:19 PM PDT 24
Finished Aug 12 04:56:51 PM PDT 24
Peak memory 217780 kb
Host smart-6bc64e49-c051-4807-9f75-ea51cff8102a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141019899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3141019899
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1458182768
Short name T69
Test name
Test status
Simulation time 352550662 ps
CPU time 10.12 seconds
Started Aug 12 04:56:17 PM PDT 24
Finished Aug 12 04:56:28 PM PDT 24
Peak memory 217868 kb
Host smart-db893e68-9f49-4489-bc56-b5aae7a31339
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458182768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1458182768
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1865009505
Short name T524
Test name
Test status
Simulation time 4222047732 ps
CPU time 84.15 seconds
Started Aug 12 04:56:18 PM PDT 24
Finished Aug 12 04:57:43 PM PDT 24
Peak memory 267500 kb
Host smart-752555e6-6623-44ff-a405-3a66c3e64c30
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865009505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1865009505
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3486482432
Short name T589
Test name
Test status
Simulation time 2102637911 ps
CPU time 19.83 seconds
Started Aug 12 04:56:21 PM PDT 24
Finished Aug 12 04:56:41 PM PDT 24
Peak memory 247072 kb
Host smart-2e1d2f12-2031-4ec3-8be6-1c15cda51cdc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486482432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3486482432
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.4023737264
Short name T527
Test name
Test status
Simulation time 253877065 ps
CPU time 3.24 seconds
Started Aug 12 04:56:17 PM PDT 24
Finished Aug 12 04:56:21 PM PDT 24
Peak memory 218392 kb
Host smart-9fbcd90c-617b-474b-8492-6abf10a1352e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023737264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.4023737264
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3795881528
Short name T347
Test name
Test status
Simulation time 858650297 ps
CPU time 14.54 seconds
Started Aug 12 04:56:17 PM PDT 24
Finished Aug 12 04:56:31 PM PDT 24
Peak memory 217816 kb
Host smart-9b787ba1-2561-44f6-a10f-1ce4a44cc712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795881528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3795881528
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.563036730
Short name T89
Test name
Test status
Simulation time 214087001 ps
CPU time 41.61 seconds
Started Aug 12 04:56:20 PM PDT 24
Finished Aug 12 04:57:02 PM PDT 24
Peak memory 282512 kb
Host smart-251f4c60-0532-4041-89ab-14a18697e54e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563036730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.563036730
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2151237100
Short name T314
Test name
Test status
Simulation time 1281954769 ps
CPU time 14.25 seconds
Started Aug 12 04:56:18 PM PDT 24
Finished Aug 12 04:56:32 PM PDT 24
Peak memory 218964 kb
Host smart-c6cafa0b-0425-46b5-b8f2-d290ff8a1f11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151237100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2151237100
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1982226185
Short name T674
Test name
Test status
Simulation time 394064881 ps
CPU time 16.46 seconds
Started Aug 12 04:56:15 PM PDT 24
Finished Aug 12 04:56:32 PM PDT 24
Peak memory 226152 kb
Host smart-a385f496-f8a7-49ac-ba12-a4aeade432b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982226185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1982226185
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3850854371
Short name T455
Test name
Test status
Simulation time 320752150 ps
CPU time 7.67 seconds
Started Aug 12 04:56:21 PM PDT 24
Finished Aug 12 04:56:29 PM PDT 24
Peak memory 226200 kb
Host smart-a98360b1-7e26-4fec-b7e8-6d08e42e2600
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850854371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
850854371
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1702662273
Short name T869
Test name
Test status
Simulation time 994054448 ps
CPU time 8.65 seconds
Started Aug 12 04:56:21 PM PDT 24
Finished Aug 12 04:56:29 PM PDT 24
Peak memory 218484 kb
Host smart-84a93b07-1b68-4a89-83f2-9cf209122c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702662273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1702662273
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1570481222
Short name T738
Test name
Test status
Simulation time 95031410 ps
CPU time 1.99 seconds
Started Aug 12 04:56:21 PM PDT 24
Finished Aug 12 04:56:23 PM PDT 24
Peak memory 214560 kb
Host smart-c4c420b1-58b3-40fb-b139-e1b898b19d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570481222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1570481222
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.805932701
Short name T449
Test name
Test status
Simulation time 392900644 ps
CPU time 22.92 seconds
Started Aug 12 04:56:18 PM PDT 24
Finished Aug 12 04:56:41 PM PDT 24
Peak memory 251020 kb
Host smart-0aa6806e-ec8c-408f-9b5f-b19c73b5747d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805932701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.805932701
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.323842070
Short name T711
Test name
Test status
Simulation time 77669211 ps
CPU time 6.76 seconds
Started Aug 12 04:56:17 PM PDT 24
Finished Aug 12 04:56:24 PM PDT 24
Peak memory 247232 kb
Host smart-7053c390-9fea-4265-a927-c565f211aa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323842070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.323842070
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.180801254
Short name T621
Test name
Test status
Simulation time 6511202643 ps
CPU time 45.22 seconds
Started Aug 12 04:56:17 PM PDT 24
Finished Aug 12 04:57:02 PM PDT 24
Peak memory 251108 kb
Host smart-967d2a17-f568-4016-ad9a-451ebfcaf3b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180801254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.180801254
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3999857014
Short name T152
Test name
Test status
Simulation time 14126834651 ps
CPU time 93.54 seconds
Started Aug 12 04:56:19 PM PDT 24
Finished Aug 12 04:57:53 PM PDT 24
Peak memory 269540 kb
Host smart-15b89576-03a8-4e5f-b5eb-970e25218423
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3999857014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.3999857014
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3749573097
Short name T751
Test name
Test status
Simulation time 47664690 ps
CPU time 0.89 seconds
Started Aug 12 04:56:19 PM PDT 24
Finished Aug 12 04:56:20 PM PDT 24
Peak memory 209072 kb
Host smart-df93a007-9aa2-4f32-b3f0-9b4fe7b9f34e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749573097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3749573097
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3602643054
Short name T593
Test name
Test status
Simulation time 61070389 ps
CPU time 1.09 seconds
Started Aug 12 04:58:14 PM PDT 24
Finished Aug 12 04:58:15 PM PDT 24
Peak memory 209080 kb
Host smart-92791000-bac7-4401-8087-6044bc512769
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602643054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3602643054
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.15189776
Short name T483
Test name
Test status
Simulation time 278957196 ps
CPU time 13.29 seconds
Started Aug 12 04:58:18 PM PDT 24
Finished Aug 12 04:58:31 PM PDT 24
Peak memory 218432 kb
Host smart-867466bb-8e3b-43ad-b4a5-0e6f2364762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15189776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.15189776
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2805345982
Short name T821
Test name
Test status
Simulation time 444620447 ps
CPU time 3.8 seconds
Started Aug 12 04:58:14 PM PDT 24
Finished Aug 12 04:58:18 PM PDT 24
Peak memory 217772 kb
Host smart-3cc7e61d-ebc6-4e69-9ba2-1c96f9dc5578
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805345982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2805345982
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3253182129
Short name T254
Test name
Test status
Simulation time 74969814 ps
CPU time 3.5 seconds
Started Aug 12 04:58:13 PM PDT 24
Finished Aug 12 04:58:17 PM PDT 24
Peak memory 222596 kb
Host smart-59d1a402-aec1-4b9a-82bc-3ad0dd7862c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253182129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3253182129
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3719025704
Short name T41
Test name
Test status
Simulation time 258196373 ps
CPU time 10.2 seconds
Started Aug 12 04:58:18 PM PDT 24
Finished Aug 12 04:58:28 PM PDT 24
Peak memory 226224 kb
Host smart-c44a72c2-c1d2-4837-a7e5-7d67b0508de2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719025704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3719025704
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2331047875
Short name T413
Test name
Test status
Simulation time 246325616 ps
CPU time 8.31 seconds
Started Aug 12 04:58:15 PM PDT 24
Finished Aug 12 04:58:23 PM PDT 24
Peak memory 226144 kb
Host smart-246a8bb2-be48-422a-bb32-c972a4dce152
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331047875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2331047875
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1931909183
Short name T868
Test name
Test status
Simulation time 270675595 ps
CPU time 7.37 seconds
Started Aug 12 04:58:13 PM PDT 24
Finished Aug 12 04:58:20 PM PDT 24
Peak memory 218376 kb
Host smart-66222785-0842-44b5-987e-94f80eee90c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931909183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1931909183
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.259487373
Short name T330
Test name
Test status
Simulation time 366439094 ps
CPU time 8.66 seconds
Started Aug 12 04:58:15 PM PDT 24
Finished Aug 12 04:58:24 PM PDT 24
Peak memory 225200 kb
Host smart-34c7b52c-7b07-4f84-8f6d-19e0ead0fb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259487373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.259487373
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1920074384
Short name T377
Test name
Test status
Simulation time 13243093 ps
CPU time 1.06 seconds
Started Aug 12 04:58:15 PM PDT 24
Finished Aug 12 04:58:16 PM PDT 24
Peak memory 217804 kb
Host smart-48caaae6-2ed2-4937-badd-e0e11a588536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920074384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1920074384
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.4064079111
Short name T440
Test name
Test status
Simulation time 308941137 ps
CPU time 26.51 seconds
Started Aug 12 04:58:16 PM PDT 24
Finished Aug 12 04:58:42 PM PDT 24
Peak memory 250892 kb
Host smart-b3ac15c2-b81c-44ba-bfb5-c36f13f9f863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064079111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.4064079111
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3798288022
Short name T617
Test name
Test status
Simulation time 347597276 ps
CPU time 4.1 seconds
Started Aug 12 04:58:12 PM PDT 24
Finished Aug 12 04:58:16 PM PDT 24
Peak memory 226444 kb
Host smart-c21f02f6-4d45-4337-be91-d56d88ad6d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798288022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3798288022
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3765503557
Short name T395
Test name
Test status
Simulation time 8025132380 ps
CPU time 317.76 seconds
Started Aug 12 04:58:15 PM PDT 24
Finished Aug 12 05:03:33 PM PDT 24
Peak memory 273536 kb
Host smart-7ab30dba-e750-426e-846e-f4e1efea8d39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765503557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3765503557
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.4073488976
Short name T28
Test name
Test status
Simulation time 22982114 ps
CPU time 1.12 seconds
Started Aug 12 04:58:15 PM PDT 24
Finished Aug 12 04:58:16 PM PDT 24
Peak memory 212120 kb
Host smart-ed53c056-ad8d-48cd-8cbc-114d9e3aad2b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073488976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.4073488976
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.669193712
Short name T232
Test name
Test status
Simulation time 16542002 ps
CPU time 0.88 seconds
Started Aug 12 04:58:23 PM PDT 24
Finished Aug 12 04:58:24 PM PDT 24
Peak memory 208864 kb
Host smart-176f45b0-0c72-4887-9500-aaa0b17b9c65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669193712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.669193712
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2312343588
Short name T479
Test name
Test status
Simulation time 577582408 ps
CPU time 11.18 seconds
Started Aug 12 04:58:23 PM PDT 24
Finished Aug 12 04:58:35 PM PDT 24
Peak memory 218368 kb
Host smart-adb394d1-5c46-4f07-b3a4-12a37a69ba23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312343588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2312343588
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1106902256
Short name T641
Test name
Test status
Simulation time 1710496270 ps
CPU time 6.06 seconds
Started Aug 12 04:58:23 PM PDT 24
Finished Aug 12 04:58:30 PM PDT 24
Peak memory 217836 kb
Host smart-ce474100-8394-4eb5-867d-cfd4f42c9795
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106902256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1106902256
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2858570542
Short name T365
Test name
Test status
Simulation time 15105867 ps
CPU time 1.63 seconds
Started Aug 12 04:58:22 PM PDT 24
Finished Aug 12 04:58:24 PM PDT 24
Peak memory 218372 kb
Host smart-8fdf71ab-f875-4110-a731-3792c5eab12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858570542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2858570542
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1118817728
Short name T354
Test name
Test status
Simulation time 322932624 ps
CPU time 14.84 seconds
Started Aug 12 04:58:24 PM PDT 24
Finished Aug 12 04:58:39 PM PDT 24
Peak memory 219128 kb
Host smart-f53517e3-b9d6-46f6-99a7-2687edfe6901
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118817728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1118817728
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1053296815
Short name T878
Test name
Test status
Simulation time 3968422315 ps
CPU time 23.77 seconds
Started Aug 12 04:58:22 PM PDT 24
Finished Aug 12 04:58:46 PM PDT 24
Peak memory 226232 kb
Host smart-74841c88-e322-42a7-9d1f-67bcd31073fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053296815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1053296815
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.338738281
Short name T408
Test name
Test status
Simulation time 297446481 ps
CPU time 7.89 seconds
Started Aug 12 04:58:23 PM PDT 24
Finished Aug 12 04:58:31 PM PDT 24
Peak memory 225360 kb
Host smart-49561f30-3fc7-4010-be64-5a795970a1d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338738281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.338738281
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2900967061
Short name T516
Test name
Test status
Simulation time 554517847 ps
CPU time 9.89 seconds
Started Aug 12 04:58:24 PM PDT 24
Finished Aug 12 04:58:34 PM PDT 24
Peak memory 218412 kb
Host smart-778dcda5-5b67-4feb-a2a0-851cad2c2262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900967061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2900967061
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2268825014
Short name T623
Test name
Test status
Simulation time 65366453 ps
CPU time 1.73 seconds
Started Aug 12 04:58:24 PM PDT 24
Finished Aug 12 04:58:26 PM PDT 24
Peak memory 214220 kb
Host smart-3af0b896-010e-4807-9430-8940f80beae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268825014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2268825014
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1745691768
Short name T231
Test name
Test status
Simulation time 1045215777 ps
CPU time 28.6 seconds
Started Aug 12 04:58:25 PM PDT 24
Finished Aug 12 04:58:54 PM PDT 24
Peak memory 247192 kb
Host smart-1dfce522-845b-4e3c-8d7b-2a063acf98d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745691768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1745691768
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3407486689
Short name T522
Test name
Test status
Simulation time 88280382 ps
CPU time 9.92 seconds
Started Aug 12 04:58:24 PM PDT 24
Finished Aug 12 04:58:34 PM PDT 24
Peak memory 251060 kb
Host smart-2e6e97a0-7a5f-4fa1-9054-a1fda7dfee96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407486689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3407486689
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2455959702
Short name T558
Test name
Test status
Simulation time 33572784407 ps
CPU time 240.33 seconds
Started Aug 12 04:58:23 PM PDT 24
Finished Aug 12 05:02:23 PM PDT 24
Peak memory 283908 kb
Host smart-7cfff440-cbfa-4365-bf77-abe39d1e23bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455959702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2455959702
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1049708835
Short name T804
Test name
Test status
Simulation time 58727217 ps
CPU time 1.13 seconds
Started Aug 12 04:58:24 PM PDT 24
Finished Aug 12 04:58:26 PM PDT 24
Peak memory 217976 kb
Host smart-52439301-3763-4af8-815d-d5662eadc4c7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049708835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1049708835
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2400836855
Short name T295
Test name
Test status
Simulation time 68124824 ps
CPU time 1.03 seconds
Started Aug 12 04:58:24 PM PDT 24
Finished Aug 12 04:58:25 PM PDT 24
Peak memory 208908 kb
Host smart-ff621b99-5e39-4034-af2e-3005b918c436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400836855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2400836855
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.4095997788
Short name T639
Test name
Test status
Simulation time 1245270394 ps
CPU time 13.65 seconds
Started Aug 12 04:58:31 PM PDT 24
Finished Aug 12 04:58:45 PM PDT 24
Peak memory 218284 kb
Host smart-0392ac9e-33b8-42d9-a5a2-b5a168c48047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095997788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.4095997788
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.4054504947
Short name T498
Test name
Test status
Simulation time 942534464 ps
CPU time 13.32 seconds
Started Aug 12 04:58:23 PM PDT 24
Finished Aug 12 04:58:36 PM PDT 24
Peak memory 217792 kb
Host smart-ba7d524a-d49b-4061-82b4-79761847406d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054504947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.4054504947
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1563881138
Short name T564
Test name
Test status
Simulation time 194336113 ps
CPU time 2.88 seconds
Started Aug 12 04:58:22 PM PDT 24
Finished Aug 12 04:58:25 PM PDT 24
Peak memory 218492 kb
Host smart-cf0ca41b-8eb3-43fe-9182-8acfd0c8d675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563881138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1563881138
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1308612315
Short name T645
Test name
Test status
Simulation time 330279781 ps
CPU time 14.26 seconds
Started Aug 12 04:58:24 PM PDT 24
Finished Aug 12 04:58:39 PM PDT 24
Peak memory 226144 kb
Host smart-c71fefff-898c-4d5f-9395-03f97acb97a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308612315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1308612315
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1964849833
Short name T177
Test name
Test status
Simulation time 2154325148 ps
CPU time 15.49 seconds
Started Aug 12 04:58:24 PM PDT 24
Finished Aug 12 04:58:39 PM PDT 24
Peak memory 226180 kb
Host smart-07a4d8da-8c44-4867-b05c-bf2fae4bc463
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964849833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1964849833
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3497041781
Short name T788
Test name
Test status
Simulation time 318197721 ps
CPU time 12.76 seconds
Started Aug 12 04:58:25 PM PDT 24
Finished Aug 12 04:58:38 PM PDT 24
Peak memory 218340 kb
Host smart-792eb24d-6e49-4301-b5b8-0d272e859d00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497041781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3497041781
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3569955158
Short name T215
Test name
Test status
Simulation time 807537394 ps
CPU time 15.57 seconds
Started Aug 12 04:58:22 PM PDT 24
Finished Aug 12 04:58:38 PM PDT 24
Peak memory 218484 kb
Host smart-4805065c-e7c5-486f-9122-831b7d9158dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569955158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3569955158
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1206087402
Short name T875
Test name
Test status
Simulation time 667230754 ps
CPU time 4.47 seconds
Started Aug 12 04:58:23 PM PDT 24
Finished Aug 12 04:58:27 PM PDT 24
Peak memory 217832 kb
Host smart-e3efc141-79fc-44ae-a487-92b333e9e2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206087402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1206087402
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.672142564
Short name T102
Test name
Test status
Simulation time 235397349 ps
CPU time 23.62 seconds
Started Aug 12 04:58:26 PM PDT 24
Finished Aug 12 04:58:50 PM PDT 24
Peak memory 251100 kb
Host smart-196fad16-20ef-437a-a265-49488da6b80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672142564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.672142564
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1217865920
Short name T518
Test name
Test status
Simulation time 60413445 ps
CPU time 2.94 seconds
Started Aug 12 04:58:24 PM PDT 24
Finished Aug 12 04:58:27 PM PDT 24
Peak memory 218468 kb
Host smart-bcdef20b-202b-4f22-97d5-6b0bc03ed035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217865920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1217865920
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.61425790
Short name T97
Test name
Test status
Simulation time 48468592 ps
CPU time 0.97 seconds
Started Aug 12 04:58:22 PM PDT 24
Finished Aug 12 04:58:24 PM PDT 24
Peak memory 209336 kb
Host smart-b9090b65-fe66-458b-a7ef-551f8728b0c6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61425790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctr
l_volatile_unlock_smoke.61425790
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.68594553
Short name T682
Test name
Test status
Simulation time 18983890 ps
CPU time 1.14 seconds
Started Aug 12 04:58:29 PM PDT 24
Finished Aug 12 04:58:30 PM PDT 24
Peak memory 209096 kb
Host smart-9e70e6b9-ab05-4a63-826b-4fa0e39432e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68594553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.68594553
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.217571450
Short name T393
Test name
Test status
Simulation time 697167889 ps
CPU time 15.18 seconds
Started Aug 12 04:58:22 PM PDT 24
Finished Aug 12 04:58:37 PM PDT 24
Peak memory 218376 kb
Host smart-114d946c-9ad0-487e-a7fe-b3f092d32958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217571450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.217571450
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.373134155
Short name T6
Test name
Test status
Simulation time 722637789 ps
CPU time 9.71 seconds
Started Aug 12 04:58:26 PM PDT 24
Finished Aug 12 04:58:36 PM PDT 24
Peak memory 217836 kb
Host smart-d8e358fe-9b63-43dc-9033-fe035e0a3f4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373134155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.373134155
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1344609892
Short name T269
Test name
Test status
Simulation time 627057647 ps
CPU time 2.26 seconds
Started Aug 12 04:58:21 PM PDT 24
Finished Aug 12 04:58:23 PM PDT 24
Peak memory 218336 kb
Host smart-16b8dc40-42e6-4adc-adac-e4ae0f197c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344609892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1344609892
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1083901025
Short name T703
Test name
Test status
Simulation time 3177271635 ps
CPU time 22.34 seconds
Started Aug 12 04:58:31 PM PDT 24
Finished Aug 12 04:58:53 PM PDT 24
Peak memory 226196 kb
Host smart-5e48b518-9126-4594-a2cd-8f2a191daef0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083901025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1083901025
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.888948999
Short name T280
Test name
Test status
Simulation time 289132810 ps
CPU time 10.48 seconds
Started Aug 12 04:58:35 PM PDT 24
Finished Aug 12 04:58:45 PM PDT 24
Peak memory 226160 kb
Host smart-4b9c180e-9b7e-4a2d-addd-3f60d6a43025
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888948999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.888948999
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.725789201
Short name T624
Test name
Test status
Simulation time 774788137 ps
CPU time 7.68 seconds
Started Aug 12 04:58:31 PM PDT 24
Finished Aug 12 04:58:39 PM PDT 24
Peak memory 226116 kb
Host smart-572d9977-c997-41ec-b465-2bd08ff0ea2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725789201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.725789201
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.241201247
Short name T661
Test name
Test status
Simulation time 2004311270 ps
CPU time 8.72 seconds
Started Aug 12 04:58:20 PM PDT 24
Finished Aug 12 04:58:29 PM PDT 24
Peak memory 218428 kb
Host smart-cb235230-1f64-4383-83a3-337348d4d5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241201247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.241201247
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1185466288
Short name T529
Test name
Test status
Simulation time 117811026 ps
CPU time 1.96 seconds
Started Aug 12 04:58:23 PM PDT 24
Finished Aug 12 04:58:25 PM PDT 24
Peak memory 217764 kb
Host smart-1e70924a-7eb3-4101-89bd-95240e84a39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185466288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1185466288
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.4063785868
Short name T378
Test name
Test status
Simulation time 553480898 ps
CPU time 22.8 seconds
Started Aug 12 04:58:25 PM PDT 24
Finished Aug 12 04:58:48 PM PDT 24
Peak memory 250972 kb
Host smart-6d6b58f3-7974-48ce-876b-f714a701775a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063785868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.4063785868
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3975870797
Short name T401
Test name
Test status
Simulation time 166888706 ps
CPU time 3.46 seconds
Started Aug 12 04:58:21 PM PDT 24
Finished Aug 12 04:58:25 PM PDT 24
Peak memory 222592 kb
Host smart-dd9f0877-5e87-466e-9515-1730781ba497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975870797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3975870797
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.477747636
Short name T105
Test name
Test status
Simulation time 26517666145 ps
CPU time 202.57 seconds
Started Aug 12 04:58:31 PM PDT 24
Finished Aug 12 05:01:54 PM PDT 24
Peak memory 280416 kb
Host smart-5475f439-5cef-4e3e-8b35-f24b511ebe32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477747636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.477747636
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3138792798
Short name T416
Test name
Test status
Simulation time 37758765 ps
CPU time 0.82 seconds
Started Aug 12 04:58:21 PM PDT 24
Finished Aug 12 04:58:22 PM PDT 24
Peak memory 209056 kb
Host smart-135fdb33-5a4c-479a-9272-f9f8eaf538e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138792798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3138792798
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1025891925
Short name T770
Test name
Test status
Simulation time 43991719 ps
CPU time 0.97 seconds
Started Aug 12 04:58:35 PM PDT 24
Finished Aug 12 04:58:36 PM PDT 24
Peak memory 209024 kb
Host smart-15f07a75-9a09-4a2c-859f-0be0ddb00830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025891925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1025891925
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.3568157839
Short name T773
Test name
Test status
Simulation time 1976776789 ps
CPU time 14.45 seconds
Started Aug 12 04:58:29 PM PDT 24
Finished Aug 12 04:58:44 PM PDT 24
Peak memory 218352 kb
Host smart-a9970b8f-0133-499d-a30e-55c911120dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568157839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3568157839
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3014817282
Short name T274
Test name
Test status
Simulation time 252491549 ps
CPU time 3.53 seconds
Started Aug 12 04:58:35 PM PDT 24
Finished Aug 12 04:58:38 PM PDT 24
Peak memory 217292 kb
Host smart-1d2962ec-e7fa-448e-abc9-d2a9be19275e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014817282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3014817282
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3900789865
Short name T814
Test name
Test status
Simulation time 66301139 ps
CPU time 2.9 seconds
Started Aug 12 04:58:34 PM PDT 24
Finished Aug 12 04:58:37 PM PDT 24
Peak memory 218424 kb
Host smart-433cd6d5-7183-4eec-8d64-f08123604c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900789865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3900789865
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1719119693
Short name T676
Test name
Test status
Simulation time 404813469 ps
CPU time 14.13 seconds
Started Aug 12 04:58:31 PM PDT 24
Finished Aug 12 04:58:46 PM PDT 24
Peak memory 219008 kb
Host smart-dc11a6a7-a81b-40cb-9d70-d9769db51a5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719119693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1719119693
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3173615728
Short name T574
Test name
Test status
Simulation time 803786793 ps
CPU time 14.37 seconds
Started Aug 12 04:58:30 PM PDT 24
Finished Aug 12 04:58:45 PM PDT 24
Peak memory 226068 kb
Host smart-0b3c12b8-8a5d-4956-8fb1-fb951ab3bcd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173615728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3173615728
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3321729610
Short name T382
Test name
Test status
Simulation time 804756849 ps
CPU time 6.59 seconds
Started Aug 12 04:58:32 PM PDT 24
Finished Aug 12 04:58:39 PM PDT 24
Peak memory 226200 kb
Host smart-4ef6604e-038f-45ee-9587-749bf373990d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321729610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3321729610
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.850969196
Short name T356
Test name
Test status
Simulation time 425234522 ps
CPU time 15.04 seconds
Started Aug 12 04:58:35 PM PDT 24
Finished Aug 12 04:58:50 PM PDT 24
Peak memory 226232 kb
Host smart-90f9b0ca-55f1-4e2d-b5c9-83956bf69d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850969196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.850969196
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2461314689
Short name T379
Test name
Test status
Simulation time 46347330 ps
CPU time 1.3 seconds
Started Aug 12 04:58:29 PM PDT 24
Finished Aug 12 04:58:30 PM PDT 24
Peak memory 217780 kb
Host smart-a0606365-2a20-40f5-9ef8-f3c29a9c3ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461314689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2461314689
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3201915666
Short name T754
Test name
Test status
Simulation time 143044900 ps
CPU time 12.82 seconds
Started Aug 12 04:58:33 PM PDT 24
Finished Aug 12 04:58:46 PM PDT 24
Peak memory 251052 kb
Host smart-1d1d35c8-aac8-4353-ba67-97fc4224f74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201915666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3201915666
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2134935118
Short name T562
Test name
Test status
Simulation time 509181913 ps
CPU time 9.12 seconds
Started Aug 12 04:58:31 PM PDT 24
Finished Aug 12 04:58:40 PM PDT 24
Peak memory 251128 kb
Host smart-4bf53c52-e864-4ef6-83fc-b67c4014ae59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134935118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2134935118
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2496477097
Short name T303
Test name
Test status
Simulation time 26059206177 ps
CPU time 221.16 seconds
Started Aug 12 04:58:35 PM PDT 24
Finished Aug 12 05:02:16 PM PDT 24
Peak memory 283928 kb
Host smart-bd704cd1-667b-4ed7-af8f-a2411c479862
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496477097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2496477097
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1061847647
Short name T328
Test name
Test status
Simulation time 15477218 ps
CPU time 1.19 seconds
Started Aug 12 04:58:30 PM PDT 24
Finished Aug 12 04:58:32 PM PDT 24
Peak memory 212172 kb
Host smart-0cc11f2c-dc17-407d-b1a5-65776eba93aa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061847647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1061847647
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3944948006
Short name T155
Test name
Test status
Simulation time 36830649 ps
CPU time 1 seconds
Started Aug 12 04:58:29 PM PDT 24
Finished Aug 12 04:58:30 PM PDT 24
Peak memory 208956 kb
Host smart-7739531f-b8e1-4c72-af0c-550f13f39ef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944948006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3944948006
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3182571888
Short name T237
Test name
Test status
Simulation time 504252461 ps
CPU time 22.25 seconds
Started Aug 12 04:58:31 PM PDT 24
Finished Aug 12 04:58:54 PM PDT 24
Peak memory 218392 kb
Host smart-b1a08565-9f09-4030-a58e-c2f7be87ebad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182571888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3182571888
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1176357508
Short name T726
Test name
Test status
Simulation time 1783262133 ps
CPU time 5.26 seconds
Started Aug 12 04:58:30 PM PDT 24
Finished Aug 12 04:58:35 PM PDT 24
Peak memory 217480 kb
Host smart-d994e7ef-8117-447b-adae-d43218edd6b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176357508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1176357508
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3525394420
Short name T281
Test name
Test status
Simulation time 207368682 ps
CPU time 2.44 seconds
Started Aug 12 04:58:30 PM PDT 24
Finished Aug 12 04:58:32 PM PDT 24
Peak memory 218312 kb
Host smart-a5a5ffd3-42f7-4af4-a708-5e5421e583c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525394420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3525394420
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.785971866
Short name T294
Test name
Test status
Simulation time 218633123 ps
CPU time 10.28 seconds
Started Aug 12 04:58:31 PM PDT 24
Finished Aug 12 04:58:41 PM PDT 24
Peak memory 218656 kb
Host smart-f5eb30b5-799d-4604-880c-ec4b7790484c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785971866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.785971866
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3681101944
Short name T473
Test name
Test status
Simulation time 1272376533 ps
CPU time 12.63 seconds
Started Aug 12 04:58:35 PM PDT 24
Finished Aug 12 04:58:47 PM PDT 24
Peak memory 226156 kb
Host smart-c112e1ed-0f21-4b39-8522-44b71ce2b0d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681101944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3681101944
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3654125051
Short name T552
Test name
Test status
Simulation time 746530266 ps
CPU time 7.78 seconds
Started Aug 12 04:58:29 PM PDT 24
Finished Aug 12 04:58:37 PM PDT 24
Peak memory 218328 kb
Host smart-5db028a2-7b59-49bb-bed2-90b22b87fdbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654125051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3654125051
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2337276082
Short name T461
Test name
Test status
Simulation time 1600778998 ps
CPU time 10.25 seconds
Started Aug 12 04:58:29 PM PDT 24
Finished Aug 12 04:58:39 PM PDT 24
Peak memory 218408 kb
Host smart-5096460e-d8db-42e5-af4a-f4aa9e09a99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337276082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2337276082
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3942197154
Short name T234
Test name
Test status
Simulation time 112496359 ps
CPU time 2.18 seconds
Started Aug 12 04:58:29 PM PDT 24
Finished Aug 12 04:58:32 PM PDT 24
Peak memory 217784 kb
Host smart-49b3c105-1e7b-4225-9b81-65831fd3c96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942197154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3942197154
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3707038327
Short name T308
Test name
Test status
Simulation time 258224126 ps
CPU time 24.24 seconds
Started Aug 12 04:58:30 PM PDT 24
Finished Aug 12 04:58:55 PM PDT 24
Peak memory 245376 kb
Host smart-a7ee0aa2-1aaf-41f3-abb9-247d7319a290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707038327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3707038327
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.4158490698
Short name T646
Test name
Test status
Simulation time 73524691 ps
CPU time 7.01 seconds
Started Aug 12 04:58:30 PM PDT 24
Finished Aug 12 04:58:37 PM PDT 24
Peak memory 251092 kb
Host smart-5243326c-431b-4451-b497-292d286842c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158490698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.4158490698
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1068292342
Short name T151
Test name
Test status
Simulation time 9159400559 ps
CPU time 85.21 seconds
Started Aug 12 04:58:34 PM PDT 24
Finished Aug 12 04:59:59 PM PDT 24
Peak memory 268508 kb
Host smart-b45926ac-9baf-4889-9d09-7f4f2c814353
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1068292342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1068292342
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1161775652
Short name T705
Test name
Test status
Simulation time 24751198 ps
CPU time 0.95 seconds
Started Aug 12 04:58:31 PM PDT 24
Finished Aug 12 04:58:32 PM PDT 24
Peak memory 209100 kb
Host smart-a396b0ef-d506-433a-afcf-598c703a65d9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161775652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1161775652
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3576431841
Short name T637
Test name
Test status
Simulation time 48545879 ps
CPU time 0.82 seconds
Started Aug 12 04:58:37 PM PDT 24
Finished Aug 12 04:58:38 PM PDT 24
Peak memory 208848 kb
Host smart-075dd07e-4af2-4011-815d-8a7c7008a724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576431841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3576431841
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2730121055
Short name T477
Test name
Test status
Simulation time 788334420 ps
CPU time 11.7 seconds
Started Aug 12 04:58:30 PM PDT 24
Finished Aug 12 04:58:42 PM PDT 24
Peak memory 226144 kb
Host smart-abf5a902-8d8a-4153-a478-b957d6d609b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730121055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2730121055
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1805870072
Short name T23
Test name
Test status
Simulation time 1886699071 ps
CPU time 8.45 seconds
Started Aug 12 04:58:36 PM PDT 24
Finished Aug 12 04:58:45 PM PDT 24
Peak memory 217528 kb
Host smart-248fcaef-ba52-4bab-9ef4-0377ff9ca08d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805870072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1805870072
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.806714724
Short name T298
Test name
Test status
Simulation time 61270708 ps
CPU time 1.67 seconds
Started Aug 12 04:58:30 PM PDT 24
Finished Aug 12 04:58:32 PM PDT 24
Peak memory 218360 kb
Host smart-5bdb7eac-3984-4d05-a9b9-1cc243f8b223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806714724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.806714724
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2053966069
Short name T480
Test name
Test status
Simulation time 5548656856 ps
CPU time 15.57 seconds
Started Aug 12 04:58:37 PM PDT 24
Finished Aug 12 04:58:53 PM PDT 24
Peak memory 219092 kb
Host smart-2a908da8-f207-4b3d-8ea7-a51d4015eca1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053966069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2053966069
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.912909885
Short name T540
Test name
Test status
Simulation time 421977944 ps
CPU time 13.09 seconds
Started Aug 12 04:58:36 PM PDT 24
Finished Aug 12 04:58:49 PM PDT 24
Peak memory 226172 kb
Host smart-dfe4806e-4175-4ef3-91b0-da38c2f79f7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912909885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.912909885
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.4143882367
Short name T808
Test name
Test status
Simulation time 1326744958 ps
CPU time 9.45 seconds
Started Aug 12 04:58:36 PM PDT 24
Finished Aug 12 04:58:45 PM PDT 24
Peak memory 226336 kb
Host smart-01b7b784-2217-4d7e-90ca-c6d41f2340d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143882367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
4143882367
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3008312931
Short name T496
Test name
Test status
Simulation time 581371850 ps
CPU time 8.53 seconds
Started Aug 12 04:58:36 PM PDT 24
Finished Aug 12 04:58:44 PM PDT 24
Peak memory 226120 kb
Host smart-d0e34862-e206-40c0-abdf-5ae0b6e811b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008312931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3008312931
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.4291158762
Short name T840
Test name
Test status
Simulation time 82871146 ps
CPU time 1.63 seconds
Started Aug 12 04:58:29 PM PDT 24
Finished Aug 12 04:58:31 PM PDT 24
Peak memory 217828 kb
Host smart-523e3024-a847-49c7-9d51-ef5b249985dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291158762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.4291158762
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1029416217
Short name T870
Test name
Test status
Simulation time 1088194206 ps
CPU time 22.32 seconds
Started Aug 12 04:58:30 PM PDT 24
Finished Aug 12 04:58:53 PM PDT 24
Peak memory 251036 kb
Host smart-bda5767d-8dea-4bcb-a8f1-00837d660723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029416217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1029416217
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2182318309
Short name T600
Test name
Test status
Simulation time 242164627 ps
CPU time 8.74 seconds
Started Aug 12 04:58:32 PM PDT 24
Finished Aug 12 04:58:41 PM PDT 24
Peak memory 251028 kb
Host smart-bfb834c2-6635-4e5c-a051-977656f8f3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182318309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2182318309
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2961644521
Short name T497
Test name
Test status
Simulation time 10742707367 ps
CPU time 366.59 seconds
Started Aug 12 04:58:35 PM PDT 24
Finished Aug 12 05:04:42 PM PDT 24
Peak memory 222740 kb
Host smart-5ec98987-d2d7-440f-8999-2981047e2138
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961644521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2961644521
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2123903576
Short name T537
Test name
Test status
Simulation time 89129298 ps
CPU time 0.83 seconds
Started Aug 12 04:58:31 PM PDT 24
Finished Aug 12 04:58:32 PM PDT 24
Peak memory 209260 kb
Host smart-d7585eb7-cc9c-4f19-8fa7-a20ead59ffca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123903576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2123903576
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3228463061
Short name T331
Test name
Test status
Simulation time 29313684 ps
CPU time 1.41 seconds
Started Aug 12 04:58:35 PM PDT 24
Finished Aug 12 04:58:37 PM PDT 24
Peak memory 209148 kb
Host smart-92fe786f-4ba7-4183-a933-a5bf0ec732dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228463061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3228463061
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2455818960
Short name T722
Test name
Test status
Simulation time 244442479 ps
CPU time 9.06 seconds
Started Aug 12 04:58:39 PM PDT 24
Finished Aug 12 04:58:48 PM PDT 24
Peak memory 218424 kb
Host smart-663108f7-efa8-466c-ac2d-401078951e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455818960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2455818960
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.702114774
Short name T832
Test name
Test status
Simulation time 285983010 ps
CPU time 7.64 seconds
Started Aug 12 04:58:38 PM PDT 24
Finished Aug 12 04:58:45 PM PDT 24
Peak memory 218140 kb
Host smart-3f63fc6b-1824-4259-8b4b-5992176e0f37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702114774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.702114774
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.119120853
Short name T307
Test name
Test status
Simulation time 836126799 ps
CPU time 2.94 seconds
Started Aug 12 04:58:38 PM PDT 24
Finished Aug 12 04:58:41 PM PDT 24
Peak memory 218404 kb
Host smart-b8e5df60-07db-48ae-9adf-be55057e9e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119120853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.119120853
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1718310308
Short name T603
Test name
Test status
Simulation time 1533833484 ps
CPU time 12.48 seconds
Started Aug 12 04:58:39 PM PDT 24
Finished Aug 12 04:58:52 PM PDT 24
Peak memory 220020 kb
Host smart-81c56185-6d0a-4697-ac26-135dfd0264a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718310308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1718310308
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3716751343
Short name T517
Test name
Test status
Simulation time 366579846 ps
CPU time 14.52 seconds
Started Aug 12 04:58:36 PM PDT 24
Finished Aug 12 04:58:51 PM PDT 24
Peak memory 226156 kb
Host smart-91674695-d74c-47b2-84b0-75e585b6275e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716751343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3716751343
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2748450550
Short name T698
Test name
Test status
Simulation time 1331988276 ps
CPU time 14.65 seconds
Started Aug 12 04:58:37 PM PDT 24
Finished Aug 12 04:58:52 PM PDT 24
Peak memory 226220 kb
Host smart-35436c49-0d12-4d49-a63e-dc2bd17644c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748450550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2748450550
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.221358670
Short name T779
Test name
Test status
Simulation time 1664152040 ps
CPU time 14.31 seconds
Started Aug 12 04:58:39 PM PDT 24
Finished Aug 12 04:58:53 PM PDT 24
Peak memory 218412 kb
Host smart-302701fa-ef17-479f-b888-3ba9cca72c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221358670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.221358670
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3595482405
Short name T409
Test name
Test status
Simulation time 111497727 ps
CPU time 2.33 seconds
Started Aug 12 04:58:39 PM PDT 24
Finished Aug 12 04:58:41 PM PDT 24
Peak memory 214500 kb
Host smart-035d6c42-bd7b-4e06-b858-30e8e1e6053e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595482405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3595482405
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2597859124
Short name T733
Test name
Test status
Simulation time 309825021 ps
CPU time 34.32 seconds
Started Aug 12 04:58:36 PM PDT 24
Finished Aug 12 04:59:10 PM PDT 24
Peak memory 251040 kb
Host smart-114f8ea9-bf46-4eff-88e3-578e7d7dda90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597859124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2597859124
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1356177298
Short name T392
Test name
Test status
Simulation time 407493388 ps
CPU time 3.62 seconds
Started Aug 12 04:58:38 PM PDT 24
Finished Aug 12 04:58:42 PM PDT 24
Peak memory 222484 kb
Host smart-b3504f67-1a2e-4a23-9047-4f4395671001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356177298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1356177298
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.792799755
Short name T71
Test name
Test status
Simulation time 2786529620 ps
CPU time 58.1 seconds
Started Aug 12 04:58:38 PM PDT 24
Finished Aug 12 04:59:36 PM PDT 24
Peak memory 226288 kb
Host smart-570478ae-cffa-497c-9957-f933a67a14af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792799755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.792799755
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1777351291
Short name T668
Test name
Test status
Simulation time 36150365 ps
CPU time 1.11 seconds
Started Aug 12 04:58:36 PM PDT 24
Finished Aug 12 04:58:38 PM PDT 24
Peak memory 212040 kb
Host smart-aa63b812-ce86-48ea-9427-7e26db9eb545
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777351291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1777351291
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.308345409
Short name T82
Test name
Test status
Simulation time 11710739 ps
CPU time 1.01 seconds
Started Aug 12 04:58:40 PM PDT 24
Finished Aug 12 04:58:42 PM PDT 24
Peak memory 208964 kb
Host smart-96691c33-ab62-4e5e-9d1b-30c74aa80daf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308345409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.308345409
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.982949165
Short name T180
Test name
Test status
Simulation time 445781014 ps
CPU time 13.8 seconds
Started Aug 12 04:58:40 PM PDT 24
Finished Aug 12 04:58:54 PM PDT 24
Peak memory 218380 kb
Host smart-2a31026c-8bce-4cf3-ada5-7f6942783a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982949165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.982949165
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.4223507055
Short name T616
Test name
Test status
Simulation time 1442749754 ps
CPU time 4.59 seconds
Started Aug 12 04:58:37 PM PDT 24
Finished Aug 12 04:58:42 PM PDT 24
Peak memory 217796 kb
Host smart-92e2c4f7-3dcc-4f46-9d49-de7878df6a01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223507055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.4223507055
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.658335852
Short name T13
Test name
Test status
Simulation time 103042532 ps
CPU time 4.66 seconds
Started Aug 12 04:58:38 PM PDT 24
Finished Aug 12 04:58:42 PM PDT 24
Peak memory 218408 kb
Host smart-ef529892-de1e-44eb-a8f7-1ec424e82dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658335852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.658335852
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1929920562
Short name T9
Test name
Test status
Simulation time 224846088 ps
CPU time 10.2 seconds
Started Aug 12 04:58:38 PM PDT 24
Finished Aug 12 04:58:48 PM PDT 24
Peak memory 218668 kb
Host smart-2335a6d8-df99-4ef4-9845-29e529fc476f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929920562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1929920562
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.678585156
Short name T599
Test name
Test status
Simulation time 1608443705 ps
CPU time 11.95 seconds
Started Aug 12 04:58:41 PM PDT 24
Finished Aug 12 04:58:53 PM PDT 24
Peak memory 226096 kb
Host smart-6691237e-81fd-429b-a511-56c0d91ddcd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678585156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di
gest.678585156
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3674249634
Short name T309
Test name
Test status
Simulation time 1680638852 ps
CPU time 9.81 seconds
Started Aug 12 04:58:37 PM PDT 24
Finished Aug 12 04:58:47 PM PDT 24
Peak memory 226156 kb
Host smart-bf28c306-0331-4acc-be2f-d4e511857b9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674249634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3674249634
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1925292283
Short name T289
Test name
Test status
Simulation time 925875338 ps
CPU time 7.87 seconds
Started Aug 12 04:58:38 PM PDT 24
Finished Aug 12 04:58:46 PM PDT 24
Peak memory 218504 kb
Host smart-53347cc5-d63d-45f0-8ce6-ef94bf5fa868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925292283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1925292283
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.452615849
Short name T70
Test name
Test status
Simulation time 566417996 ps
CPU time 7.9 seconds
Started Aug 12 04:58:37 PM PDT 24
Finished Aug 12 04:58:45 PM PDT 24
Peak memory 217792 kb
Host smart-4159b71e-2bd9-42de-be35-d700a0dc7874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452615849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.452615849
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3832282057
Short name T396
Test name
Test status
Simulation time 238131967 ps
CPU time 20.19 seconds
Started Aug 12 04:58:37 PM PDT 24
Finished Aug 12 04:58:57 PM PDT 24
Peak memory 245728 kb
Host smart-5c52f186-c8ed-4605-b604-5587e5de2318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832282057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3832282057
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2152260681
Short name T815
Test name
Test status
Simulation time 225736994 ps
CPU time 6.65 seconds
Started Aug 12 04:58:36 PM PDT 24
Finished Aug 12 04:58:43 PM PDT 24
Peak memory 247128 kb
Host smart-6792f9f0-ae84-4533-b266-7632006a004b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152260681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2152260681
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3767285672
Short name T87
Test name
Test status
Simulation time 19413465129 ps
CPU time 300.65 seconds
Started Aug 12 04:58:39 PM PDT 24
Finished Aug 12 05:03:40 PM PDT 24
Peak memory 246452 kb
Host smart-2a53e2db-5e80-4300-a1b6-24ccd1bea363
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767285672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3767285672
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.456850621
Short name T174
Test name
Test status
Simulation time 2350752883 ps
CPU time 49.41 seconds
Started Aug 12 04:58:41 PM PDT 24
Finished Aug 12 04:59:31 PM PDT 24
Peak memory 267656 kb
Host smart-4f39bfe4-2efe-49fb-b12f-268168ec9da9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=456850621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.456850621
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3789429096
Short name T710
Test name
Test status
Simulation time 31489263 ps
CPU time 0.98 seconds
Started Aug 12 04:58:37 PM PDT 24
Finished Aug 12 04:58:38 PM PDT 24
Peak memory 212068 kb
Host smart-5e73b2f1-c5d5-4ce4-89ba-2fc766281524
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789429096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3789429096
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1351689159
Short name T694
Test name
Test status
Simulation time 20772702 ps
CPU time 1.25 seconds
Started Aug 12 04:58:44 PM PDT 24
Finished Aug 12 04:58:46 PM PDT 24
Peak memory 209044 kb
Host smart-155ab7f4-117a-4f4c-9a1f-baff4b95e108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351689159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1351689159
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2341350635
Short name T541
Test name
Test status
Simulation time 6389651332 ps
CPU time 10.96 seconds
Started Aug 12 04:58:44 PM PDT 24
Finished Aug 12 04:58:55 PM PDT 24
Peak memory 226196 kb
Host smart-b3130267-a51f-4a0d-9e7b-f5868a16b8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341350635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2341350635
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2892494032
Short name T511
Test name
Test status
Simulation time 763784803 ps
CPU time 9.83 seconds
Started Aug 12 04:58:52 PM PDT 24
Finished Aug 12 04:59:02 PM PDT 24
Peak memory 217852 kb
Host smart-be2b84d2-f66e-41e0-9892-deae0459b031
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892494032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2892494032
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1937599758
Short name T792
Test name
Test status
Simulation time 22683782 ps
CPU time 1.88 seconds
Started Aug 12 04:58:37 PM PDT 24
Finished Aug 12 04:58:39 PM PDT 24
Peak memory 218384 kb
Host smart-69f61ba6-c982-4c6f-8f18-54aff2d25fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937599758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1937599758
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1282791463
Short name T879
Test name
Test status
Simulation time 189289539 ps
CPU time 9.67 seconds
Started Aug 12 04:58:44 PM PDT 24
Finished Aug 12 04:58:54 PM PDT 24
Peak memory 226164 kb
Host smart-5979fe9d-49f4-42ba-9900-6b12101f7068
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282791463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1282791463
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1526328313
Short name T322
Test name
Test status
Simulation time 1071487779 ps
CPU time 10.1 seconds
Started Aug 12 04:58:46 PM PDT 24
Finished Aug 12 04:58:56 PM PDT 24
Peak memory 226084 kb
Host smart-e3df2b39-ebce-44c5-aa8b-caffef089e40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526328313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1526328313
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2347425044
Short name T261
Test name
Test status
Simulation time 966096814 ps
CPU time 8.03 seconds
Started Aug 12 04:58:44 PM PDT 24
Finished Aug 12 04:58:52 PM PDT 24
Peak memory 218380 kb
Host smart-74b178a3-ccd2-416f-8d2b-7280345c2f32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347425044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2347425044
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3388580476
Short name T800
Test name
Test status
Simulation time 3189052509 ps
CPU time 9.81 seconds
Started Aug 12 04:58:53 PM PDT 24
Finished Aug 12 04:59:03 PM PDT 24
Peak memory 226144 kb
Host smart-a1d27ee0-5312-4020-87a5-0598c4bb24bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388580476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3388580476
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2102343399
Short name T490
Test name
Test status
Simulation time 189953377 ps
CPU time 1.39 seconds
Started Aug 12 04:58:41 PM PDT 24
Finished Aug 12 04:58:42 PM PDT 24
Peak memory 213960 kb
Host smart-591d33f0-b88f-4f1e-8a86-c5fb4237e6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102343399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2102343399
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.511848318
Short name T763
Test name
Test status
Simulation time 405360073 ps
CPU time 24.28 seconds
Started Aug 12 04:58:42 PM PDT 24
Finished Aug 12 04:59:07 PM PDT 24
Peak memory 251168 kb
Host smart-127fa641-9f40-4fc1-b0b1-d1bf7cf72fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511848318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.511848318
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3617980879
Short name T775
Test name
Test status
Simulation time 112462534 ps
CPU time 3.53 seconds
Started Aug 12 04:58:41 PM PDT 24
Finished Aug 12 04:58:44 PM PDT 24
Peak memory 222524 kb
Host smart-5910e138-940e-4f4a-9393-a06bc3728f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617980879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3617980879
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3659360924
Short name T798
Test name
Test status
Simulation time 72897081172 ps
CPU time 267.1 seconds
Started Aug 12 04:58:47 PM PDT 24
Finished Aug 12 05:03:15 PM PDT 24
Peak memory 300260 kb
Host smart-59dac878-e7bb-409b-aafe-b2ecb72e46f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659360924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3659360924
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.2758896915
Short name T109
Test name
Test status
Simulation time 4445135178 ps
CPU time 71.5 seconds
Started Aug 12 04:58:53 PM PDT 24
Finished Aug 12 05:00:05 PM PDT 24
Peak memory 226396 kb
Host smart-5f90556c-2319-4ee1-bcc8-026f1f8caef7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2758896915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.2758896915
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2014821512
Short name T329
Test name
Test status
Simulation time 13668694 ps
CPU time 0.97 seconds
Started Aug 12 04:58:40 PM PDT 24
Finished Aug 12 04:58:41 PM PDT 24
Peak memory 209384 kb
Host smart-cfde71ec-c122-46e3-8d79-fb0d67164be1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014821512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2014821512
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3257107423
Short name T443
Test name
Test status
Simulation time 75166522 ps
CPU time 0.83 seconds
Started Aug 12 04:56:25 PM PDT 24
Finished Aug 12 04:56:26 PM PDT 24
Peak memory 208948 kb
Host smart-2ecec362-ec88-4532-a060-b797d6436100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257107423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3257107423
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.859774234
Short name T794
Test name
Test status
Simulation time 685989015 ps
CPU time 14.37 seconds
Started Aug 12 04:56:20 PM PDT 24
Finished Aug 12 04:56:35 PM PDT 24
Peak memory 218408 kb
Host smart-f351fba4-e433-4543-ab5f-d3b1017f78ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859774234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.859774234
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.59367436
Short name T19
Test name
Test status
Simulation time 304823301 ps
CPU time 4.77 seconds
Started Aug 12 04:56:25 PM PDT 24
Finished Aug 12 04:56:30 PM PDT 24
Peak memory 217276 kb
Host smart-eea7d183-e158-4691-a475-d17b249f59ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59367436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.59367436
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3951978834
Short name T341
Test name
Test status
Simulation time 947421883 ps
CPU time 18.63 seconds
Started Aug 12 04:56:27 PM PDT 24
Finished Aug 12 04:56:46 PM PDT 24
Peak memory 218380 kb
Host smart-f58be0a4-3e9b-4487-95d0-bd1b8fb523c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951978834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3951978834
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1322460419
Short name T246
Test name
Test status
Simulation time 197544986 ps
CPU time 1.57 seconds
Started Aug 12 04:56:25 PM PDT 24
Finished Aug 12 04:56:26 PM PDT 24
Peak memory 217912 kb
Host smart-e9def7da-4932-4328-98ec-76ac2dde9b10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322460419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
322460419
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.4162464259
Short name T17
Test name
Test status
Simulation time 1841604806 ps
CPU time 7.54 seconds
Started Aug 12 04:56:19 PM PDT 24
Finished Aug 12 04:56:27 PM PDT 24
Peak memory 218468 kb
Host smart-286b18b0-4043-4333-8d4e-e07885905097
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162464259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.4162464259
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.970195169
Short name T236
Test name
Test status
Simulation time 3181260115 ps
CPU time 14.95 seconds
Started Aug 12 04:56:25 PM PDT 24
Finished Aug 12 04:56:40 PM PDT 24
Peak memory 217780 kb
Host smart-00523b2f-158e-4f0a-99c1-94b3d576c3bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970195169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.970195169
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1310887801
Short name T831
Test name
Test status
Simulation time 1011820171 ps
CPU time 4.91 seconds
Started Aug 12 04:56:18 PM PDT 24
Finished Aug 12 04:56:23 PM PDT 24
Peak memory 217700 kb
Host smart-98018068-70a5-4229-a790-3f0f20d9e456
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310887801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1310887801
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3933537885
Short name T795
Test name
Test status
Simulation time 2518640855 ps
CPU time 50.75 seconds
Started Aug 12 04:56:16 PM PDT 24
Finished Aug 12 04:57:07 PM PDT 24
Peak memory 275624 kb
Host smart-4ebea452-d5b2-4a83-9a95-4a53a08422de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933537885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3933537885
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3986248907
Short name T647
Test name
Test status
Simulation time 1787860825 ps
CPU time 13.24 seconds
Started Aug 12 04:56:18 PM PDT 24
Finished Aug 12 04:56:31 PM PDT 24
Peak memory 222008 kb
Host smart-d764d4d9-5b75-42cb-8f87-f7b5c4c6b047
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986248907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3986248907
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2028665385
Short name T476
Test name
Test status
Simulation time 55072231 ps
CPU time 2.86 seconds
Started Aug 12 04:56:21 PM PDT 24
Finished Aug 12 04:56:24 PM PDT 24
Peak memory 218416 kb
Host smart-e7973cdc-eb99-4823-982c-a01091c2ca61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028665385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2028665385
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1128584840
Short name T75
Test name
Test status
Simulation time 3140885116 ps
CPU time 17.13 seconds
Started Aug 12 04:56:20 PM PDT 24
Finished Aug 12 04:56:37 PM PDT 24
Peak memory 217992 kb
Host smart-a71e9502-76f0-4476-9742-2f265a008469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128584840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1128584840
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2046060551
Short name T52
Test name
Test status
Simulation time 117933404 ps
CPU time 25.32 seconds
Started Aug 12 04:56:24 PM PDT 24
Finished Aug 12 04:56:50 PM PDT 24
Peak memory 282160 kb
Host smart-18756128-2289-47ea-b66b-5f26a9f06c38
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046060551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2046060551
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2286249473
Short name T219
Test name
Test status
Simulation time 2392561369 ps
CPU time 17.19 seconds
Started Aug 12 04:56:30 PM PDT 24
Finished Aug 12 04:56:47 PM PDT 24
Peak memory 226208 kb
Host smart-6cdb77bd-a690-4ec3-a039-3c7e954ded36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286249473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2286249473
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3606371067
Short name T233
Test name
Test status
Simulation time 2896121444 ps
CPU time 9.97 seconds
Started Aug 12 04:56:24 PM PDT 24
Finished Aug 12 04:56:34 PM PDT 24
Peak memory 226148 kb
Host smart-fb207bb4-32b0-4654-a4e5-5b0fbd52dfe7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606371067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3606371067
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3189009208
Short name T317
Test name
Test status
Simulation time 5635717942 ps
CPU time 11.33 seconds
Started Aug 12 04:56:23 PM PDT 24
Finished Aug 12 04:56:35 PM PDT 24
Peak memory 226220 kb
Host smart-6cb004d1-c568-4d62-916d-3a4c7754d230
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189009208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
189009208
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2376710190
Short name T732
Test name
Test status
Simulation time 247686287 ps
CPU time 8.09 seconds
Started Aug 12 04:56:20 PM PDT 24
Finished Aug 12 04:56:28 PM PDT 24
Peak memory 218480 kb
Host smart-c2428a44-a376-40d3-b3b3-00b8baecf809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376710190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2376710190
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1991870789
Short name T74
Test name
Test status
Simulation time 109475875 ps
CPU time 2.83 seconds
Started Aug 12 04:56:16 PM PDT 24
Finished Aug 12 04:56:19 PM PDT 24
Peak memory 214756 kb
Host smart-6a751473-1301-4778-9e32-9d5bc0e85786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991870789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1991870789
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.975379105
Short name T630
Test name
Test status
Simulation time 295820705 ps
CPU time 29.6 seconds
Started Aug 12 04:56:20 PM PDT 24
Finished Aug 12 04:56:50 PM PDT 24
Peak memory 247560 kb
Host smart-51212093-476b-4755-8efe-59d804ed3dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975379105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.975379105
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.207882067
Short name T765
Test name
Test status
Simulation time 103912697 ps
CPU time 6.3 seconds
Started Aug 12 04:56:16 PM PDT 24
Finished Aug 12 04:56:22 PM PDT 24
Peak memory 250644 kb
Host smart-734a610b-850f-4d86-98a5-f9b082b4ab52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207882067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.207882067
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3279698466
Short name T313
Test name
Test status
Simulation time 68211664190 ps
CPU time 525.78 seconds
Started Aug 12 04:56:28 PM PDT 24
Finished Aug 12 05:05:14 PM PDT 24
Peak memory 251148 kb
Host smart-690b118f-d87b-4111-9328-51a978129a15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279698466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3279698466
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.527640024
Short name T768
Test name
Test status
Simulation time 12484069 ps
CPU time 1.07 seconds
Started Aug 12 04:56:20 PM PDT 24
Finished Aug 12 04:56:21 PM PDT 24
Peak memory 212116 kb
Host smart-b6201b07-b804-4184-a2aa-cba2a4224591
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527640024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.527640024
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.616356646
Short name T276
Test name
Test status
Simulation time 127153353 ps
CPU time 0.97 seconds
Started Aug 12 04:58:43 PM PDT 24
Finished Aug 12 04:58:44 PM PDT 24
Peak memory 209016 kb
Host smart-35a07e68-cb0c-488a-8c7f-eeddd4583ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616356646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.616356646
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3619319161
Short name T745
Test name
Test status
Simulation time 198459794 ps
CPU time 10.11 seconds
Started Aug 12 04:58:44 PM PDT 24
Finished Aug 12 04:58:54 PM PDT 24
Peak memory 218384 kb
Host smart-59d9a62f-515d-4c98-a7c0-f83664db613c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619319161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3619319161
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1510863766
Short name T320
Test name
Test status
Simulation time 312649212 ps
CPU time 4.78 seconds
Started Aug 12 04:58:49 PM PDT 24
Finished Aug 12 04:58:54 PM PDT 24
Peak memory 217432 kb
Host smart-d124ad35-01d1-4e07-9838-44e7d82ca68e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510863766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1510863766
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.117979810
Short name T702
Test name
Test status
Simulation time 41937205 ps
CPU time 2.49 seconds
Started Aug 12 04:58:44 PM PDT 24
Finished Aug 12 04:58:47 PM PDT 24
Peak memory 218384 kb
Host smart-1f9c5e00-c163-427d-a2fb-921b64b050e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117979810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.117979810
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1558318979
Short name T173
Test name
Test status
Simulation time 271607807 ps
CPU time 12.73 seconds
Started Aug 12 04:58:46 PM PDT 24
Finished Aug 12 04:58:58 PM PDT 24
Peak memory 226140 kb
Host smart-61337cd0-a3b6-4409-9cf2-118e547d1004
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558318979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1558318979
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2700862817
Short name T316
Test name
Test status
Simulation time 759535033 ps
CPU time 8.71 seconds
Started Aug 12 04:58:44 PM PDT 24
Finished Aug 12 04:58:53 PM PDT 24
Peak memory 226084 kb
Host smart-082dc3c1-cde8-469a-b32d-2c5da3eca8e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700862817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2700862817
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1046802548
Short name T671
Test name
Test status
Simulation time 1511647267 ps
CPU time 10.21 seconds
Started Aug 12 04:58:43 PM PDT 24
Finished Aug 12 04:58:53 PM PDT 24
Peak memory 226108 kb
Host smart-0dd50936-3871-42fa-a265-15f8fe1c951b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046802548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1046802548
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.163968097
Short name T806
Test name
Test status
Simulation time 615003955 ps
CPU time 9.94 seconds
Started Aug 12 04:58:45 PM PDT 24
Finished Aug 12 04:58:55 PM PDT 24
Peak memory 218492 kb
Host smart-b1ba42d9-778d-4e34-b493-f3dcda9c902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163968097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.163968097
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.161890117
Short name T719
Test name
Test status
Simulation time 46261928 ps
CPU time 2.8 seconds
Started Aug 12 04:58:46 PM PDT 24
Finished Aug 12 04:58:49 PM PDT 24
Peak memory 217788 kb
Host smart-ff8329d0-bf43-4667-97ea-14c68f7edd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161890117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.161890117
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1965552626
Short name T326
Test name
Test status
Simulation time 961382135 ps
CPU time 24.74 seconds
Started Aug 12 04:58:45 PM PDT 24
Finished Aug 12 04:59:10 PM PDT 24
Peak memory 251064 kb
Host smart-58c1e275-dfcc-4c8e-bc40-c5dce2a13e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965552626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1965552626
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1450592033
Short name T218
Test name
Test status
Simulation time 781205856 ps
CPU time 9.82 seconds
Started Aug 12 04:58:49 PM PDT 24
Finished Aug 12 04:58:59 PM PDT 24
Peak memory 243180 kb
Host smart-fe2c709e-a0a7-46d5-b833-211a131755ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450592033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1450592033
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.660043331
Short name T508
Test name
Test status
Simulation time 13643252405 ps
CPU time 184.07 seconds
Started Aug 12 04:58:42 PM PDT 24
Finished Aug 12 05:01:47 PM PDT 24
Peak memory 283892 kb
Host smart-47710738-2bf1-4714-8570-6d0a7219cd24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660043331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.660043331
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3204297511
Short name T253
Test name
Test status
Simulation time 30541116 ps
CPU time 0.94 seconds
Started Aug 12 04:58:49 PM PDT 24
Finished Aug 12 04:58:50 PM PDT 24
Peak memory 209124 kb
Host smart-77203375-627a-49eb-8ce1-cc6b41428036
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204297511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3204297511
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.242204282
Short name T366
Test name
Test status
Simulation time 79011963 ps
CPU time 1.21 seconds
Started Aug 12 04:58:53 PM PDT 24
Finished Aug 12 04:58:54 PM PDT 24
Peak memory 209028 kb
Host smart-4c79b6ba-979d-4e5c-ba67-82631eafed03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242204282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.242204282
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.515624692
Short name T855
Test name
Test status
Simulation time 11710143540 ps
CPU time 15.03 seconds
Started Aug 12 04:58:53 PM PDT 24
Finished Aug 12 04:59:08 PM PDT 24
Peak memory 218824 kb
Host smart-3133e532-608a-4a4e-8468-b357db1b9d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515624692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.515624692
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3704785679
Short name T389
Test name
Test status
Simulation time 1358315665 ps
CPU time 9.71 seconds
Started Aug 12 04:58:44 PM PDT 24
Finished Aug 12 04:58:53 PM PDT 24
Peak memory 217608 kb
Host smart-ae8310d8-edbf-4a09-81b4-a8588ed6303b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704785679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3704785679
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2732158372
Short name T271
Test name
Test status
Simulation time 139144505 ps
CPU time 3.87 seconds
Started Aug 12 04:58:44 PM PDT 24
Finished Aug 12 04:58:48 PM PDT 24
Peak memory 218400 kb
Host smart-ce3c5c58-caf9-4c37-a5c5-cfdec4d1f24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732158372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2732158372
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1539756024
Short name T510
Test name
Test status
Simulation time 306543223 ps
CPU time 14.2 seconds
Started Aug 12 04:58:46 PM PDT 24
Finished Aug 12 04:59:00 PM PDT 24
Peak memory 218992 kb
Host smart-f04b5c33-fcc1-4995-b660-c73cd073d96f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539756024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1539756024
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1834793499
Short name T301
Test name
Test status
Simulation time 354891722 ps
CPU time 13.61 seconds
Started Aug 12 04:58:45 PM PDT 24
Finished Aug 12 04:58:58 PM PDT 24
Peak memory 226120 kb
Host smart-fde6ff7c-0b27-42ff-b692-4694363c4268
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834793499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1834793499
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2614644624
Short name T837
Test name
Test status
Simulation time 525430951 ps
CPU time 10.96 seconds
Started Aug 12 04:58:46 PM PDT 24
Finished Aug 12 04:58:57 PM PDT 24
Peak memory 226140 kb
Host smart-352fb5c4-3a3b-40f0-bf8e-9fc4c1e30bb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614644624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2614644624
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3379789066
Short name T515
Test name
Test status
Simulation time 764099249 ps
CPU time 8.01 seconds
Started Aug 12 04:58:53 PM PDT 24
Finished Aug 12 04:59:01 PM PDT 24
Peak memory 218380 kb
Host smart-35e256a4-1f55-442e-aa0b-69ab02db1aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379789066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3379789066
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3180033676
Short name T596
Test name
Test status
Simulation time 629644257 ps
CPU time 4.47 seconds
Started Aug 12 04:58:46 PM PDT 24
Finished Aug 12 04:58:50 PM PDT 24
Peak memory 217776 kb
Host smart-be3e7eea-0caf-41ce-9b91-2f106781fd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180033676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3180033676
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2440056628
Short name T867
Test name
Test status
Simulation time 270020954 ps
CPU time 23.01 seconds
Started Aug 12 04:58:44 PM PDT 24
Finished Aug 12 04:59:07 PM PDT 24
Peak memory 251120 kb
Host smart-e656c811-f670-4c7b-9167-1cd57f4216cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440056628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2440056628
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1363723271
Short name T101
Test name
Test status
Simulation time 107586560 ps
CPU time 9.37 seconds
Started Aug 12 04:58:44 PM PDT 24
Finished Aug 12 04:58:53 PM PDT 24
Peak memory 251036 kb
Host smart-00c7df0e-b403-44ac-98c4-217414e2702a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363723271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1363723271
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2462694132
Short name T644
Test name
Test status
Simulation time 824512638 ps
CPU time 31.5 seconds
Started Aug 12 04:58:53 PM PDT 24
Finished Aug 12 04:59:24 PM PDT 24
Peak memory 245780 kb
Host smart-25f743ee-d131-4b6b-a3f2-c6db11472575
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462694132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2462694132
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2881411414
Short name T753
Test name
Test status
Simulation time 38445493923 ps
CPU time 103.92 seconds
Started Aug 12 04:58:50 PM PDT 24
Finished Aug 12 05:00:34 PM PDT 24
Peak memory 271164 kb
Host smart-5d040d22-409a-452a-a82e-63db0cbc0b70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2881411414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2881411414
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1164593111
Short name T277
Test name
Test status
Simulation time 15389405 ps
CPU time 1.15 seconds
Started Aug 12 04:58:49 PM PDT 24
Finished Aug 12 04:58:50 PM PDT 24
Peak memory 212100 kb
Host smart-cf97e75a-2608-4b51-a661-23eabd63dedf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164593111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1164593111
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3713023338
Short name T250
Test name
Test status
Simulation time 102080141 ps
CPU time 0.9 seconds
Started Aug 12 04:58:50 PM PDT 24
Finished Aug 12 04:58:51 PM PDT 24
Peak memory 208904 kb
Host smart-6f5717d5-d82f-4dbe-ab76-046de0d7a7fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713023338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3713023338
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1996374429
Short name T495
Test name
Test status
Simulation time 3461627695 ps
CPU time 13.72 seconds
Started Aug 12 04:58:55 PM PDT 24
Finished Aug 12 04:59:09 PM PDT 24
Peak memory 219140 kb
Host smart-414e7b7a-63ab-4c43-979b-0ff687a2c167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996374429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1996374429
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.842564814
Short name T24
Test name
Test status
Simulation time 1783684711 ps
CPU time 11.27 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:10 PM PDT 24
Peak memory 217440 kb
Host smart-8b049d28-efb5-435e-b127-091ba6461dcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842564814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.842564814
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2334342990
Short name T755
Test name
Test status
Simulation time 111860816 ps
CPU time 3.72 seconds
Started Aug 12 04:58:53 PM PDT 24
Finished Aug 12 04:58:57 PM PDT 24
Peak memory 222808 kb
Host smart-9cc2860b-2029-4547-96cc-cadbff62e51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334342990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2334342990
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2973297504
Short name T446
Test name
Test status
Simulation time 780158078 ps
CPU time 11.94 seconds
Started Aug 12 04:58:54 PM PDT 24
Finished Aug 12 04:59:06 PM PDT 24
Peak memory 226140 kb
Host smart-b9ad935b-e91f-4b07-8d7c-227ffca2575a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973297504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2973297504
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1870165220
Short name T241
Test name
Test status
Simulation time 1348482494 ps
CPU time 11.8 seconds
Started Aug 12 04:58:50 PM PDT 24
Finished Aug 12 04:59:02 PM PDT 24
Peak memory 226156 kb
Host smart-49701da8-223a-435c-a0a4-4ae4a8790cd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870165220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1870165220
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3708966239
Short name T447
Test name
Test status
Simulation time 1276334995 ps
CPU time 8.58 seconds
Started Aug 12 04:58:54 PM PDT 24
Finished Aug 12 04:59:02 PM PDT 24
Peak memory 218420 kb
Host smart-6084b8b4-b569-4354-91d4-b6868c68c1a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708966239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3708966239
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2765104769
Short name T797
Test name
Test status
Simulation time 1488047892 ps
CPU time 11.32 seconds
Started Aug 12 04:58:50 PM PDT 24
Finished Aug 12 04:59:01 PM PDT 24
Peak memory 218544 kb
Host smart-2ea462c1-a40a-4465-972e-f55368dee0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765104769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2765104769
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.891620446
Short name T613
Test name
Test status
Simulation time 313782251 ps
CPU time 5.64 seconds
Started Aug 12 04:58:55 PM PDT 24
Finished Aug 12 04:59:01 PM PDT 24
Peak memory 217844 kb
Host smart-e66e496e-5114-4fff-b209-66fe414baae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891620446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.891620446
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3936578052
Short name T172
Test name
Test status
Simulation time 485761945 ps
CPU time 21.67 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:21 PM PDT 24
Peak memory 244252 kb
Host smart-47737add-380d-4dfd-bb28-cbccc89332a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936578052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3936578052
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1714721403
Short name T431
Test name
Test status
Simulation time 139733200 ps
CPU time 6.25 seconds
Started Aug 12 04:58:51 PM PDT 24
Finished Aug 12 04:58:57 PM PDT 24
Peak memory 247552 kb
Host smart-41ead490-3bdc-42de-b203-108bce6a0308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714721403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1714721403
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3636743376
Short name T312
Test name
Test status
Simulation time 15072290819 ps
CPU time 30.74 seconds
Started Aug 12 04:58:53 PM PDT 24
Finished Aug 12 04:59:24 PM PDT 24
Peak memory 247088 kb
Host smart-a2fb8e38-c2b6-422f-93e2-b50316c58b25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636743376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3636743376
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3412153585
Short name T183
Test name
Test status
Simulation time 2900539623 ps
CPU time 142.01 seconds
Started Aug 12 04:58:50 PM PDT 24
Finished Aug 12 05:01:12 PM PDT 24
Peak memory 267596 kb
Host smart-7c5d3edd-1efd-4929-9bac-6cb1aeef8096
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3412153585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3412153585
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3280555908
Short name T156
Test name
Test status
Simulation time 53077708 ps
CPU time 1.04 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:00 PM PDT 24
Peak memory 212052 kb
Host smart-b2aad1e6-9def-45c8-9af6-34df55f4248f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280555908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3280555908
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1984074850
Short name T810
Test name
Test status
Simulation time 52777404 ps
CPU time 1.07 seconds
Started Aug 12 04:58:58 PM PDT 24
Finished Aug 12 04:58:59 PM PDT 24
Peak memory 209012 kb
Host smart-95d3841c-0c59-48f2-a9a3-74314af064e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984074850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1984074850
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3876207889
Short name T292
Test name
Test status
Simulation time 1211623469 ps
CPU time 16.17 seconds
Started Aug 12 04:59:01 PM PDT 24
Finished Aug 12 04:59:17 PM PDT 24
Peak memory 218296 kb
Host smart-b27227c4-9036-4846-8e42-6778da4c3ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876207889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3876207889
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1519148266
Short name T865
Test name
Test status
Simulation time 2337825895 ps
CPU time 6.18 seconds
Started Aug 12 04:58:51 PM PDT 24
Finished Aug 12 04:58:57 PM PDT 24
Peak memory 217892 kb
Host smart-61af999d-05cc-47b4-b2df-0f45d2990cef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519148266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1519148266
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1901982225
Short name T353
Test name
Test status
Simulation time 21027405 ps
CPU time 1.96 seconds
Started Aug 12 04:58:54 PM PDT 24
Finished Aug 12 04:58:56 PM PDT 24
Peak memory 218360 kb
Host smart-c0ddb624-a926-4215-875e-62b626e0443f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901982225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1901982225
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3313014031
Short name T762
Test name
Test status
Simulation time 2225544897 ps
CPU time 17.98 seconds
Started Aug 12 04:58:53 PM PDT 24
Finished Aug 12 04:59:11 PM PDT 24
Peak memory 220228 kb
Host smart-8daf53e6-a7f4-4f1e-aa00-9378f76ab71c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313014031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3313014031
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2822145855
Short name T175
Test name
Test status
Simulation time 252134517 ps
CPU time 9.28 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:08 PM PDT 24
Peak memory 226080 kb
Host smart-ddecb923-6989-4530-87d6-8d4c2409a224
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822145855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2822145855
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2345355518
Short name T462
Test name
Test status
Simulation time 969384415 ps
CPU time 9.24 seconds
Started Aug 12 04:58:51 PM PDT 24
Finished Aug 12 04:59:00 PM PDT 24
Peak memory 218416 kb
Host smart-54b935ed-81f6-479c-b0ff-c178c6524b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345355518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2345355518
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3859688183
Short name T608
Test name
Test status
Simulation time 79082548 ps
CPU time 2 seconds
Started Aug 12 04:58:54 PM PDT 24
Finished Aug 12 04:58:56 PM PDT 24
Peak memory 217884 kb
Host smart-e375dd05-a94a-4987-a93c-c7ae45d76da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859688183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3859688183
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2027549115
Short name T746
Test name
Test status
Simulation time 400485741 ps
CPU time 23.52 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:23 PM PDT 24
Peak memory 250988 kb
Host smart-21b47223-1b53-463b-b6e1-9271b9f71e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027549115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2027549115
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3745459117
Short name T584
Test name
Test status
Simulation time 154424962 ps
CPU time 10.96 seconds
Started Aug 12 04:58:53 PM PDT 24
Finished Aug 12 04:59:04 PM PDT 24
Peak memory 251060 kb
Host smart-ec9fee87-92b7-4bf1-9db9-bc62c28e9e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745459117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3745459117
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1095537541
Short name T489
Test name
Test status
Simulation time 3596196110 ps
CPU time 122.5 seconds
Started Aug 12 04:59:01 PM PDT 24
Finished Aug 12 05:01:03 PM PDT 24
Peak memory 283888 kb
Host smart-9db0f060-5e52-4cb3-b971-6783de50429d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095537541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1095537541
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3955863209
Short name T36
Test name
Test status
Simulation time 25688286 ps
CPU time 0.99 seconds
Started Aug 12 04:58:51 PM PDT 24
Finished Aug 12 04:58:52 PM PDT 24
Peak memory 212096 kb
Host smart-e3b4cee6-e161-4e16-af2e-9ab50185fdc6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955863209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3955863209
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2329095922
Short name T305
Test name
Test status
Simulation time 45188584 ps
CPU time 0.92 seconds
Started Aug 12 04:59:01 PM PDT 24
Finished Aug 12 04:59:02 PM PDT 24
Peak memory 208936 kb
Host smart-aae5ef42-69fa-434f-a952-59a4aae4a9f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329095922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2329095922
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3087888764
Short name T643
Test name
Test status
Simulation time 1490745059 ps
CPU time 15.46 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:14 PM PDT 24
Peak memory 218272 kb
Host smart-afc7a3bd-b829-4a5f-9702-48f1eeecb93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087888764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3087888764
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3596468653
Short name T475
Test name
Test status
Simulation time 378740736 ps
CPU time 2.33 seconds
Started Aug 12 04:59:00 PM PDT 24
Finished Aug 12 04:59:02 PM PDT 24
Peak memory 217784 kb
Host smart-615a56d8-461e-4423-8831-d326894c0e24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596468653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3596468653
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.695535813
Short name T268
Test name
Test status
Simulation time 1014390422 ps
CPU time 6.92 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:06 PM PDT 24
Peak memory 218336 kb
Host smart-d97f39af-bab6-493a-921d-1747ad82ed0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695535813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.695535813
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1722988431
Short name T737
Test name
Test status
Simulation time 385680151 ps
CPU time 17.27 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:16 PM PDT 24
Peak memory 219072 kb
Host smart-251c2182-8237-4f97-b40e-14a1f0ede25d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722988431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1722988431
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.4060970369
Short name T688
Test name
Test status
Simulation time 430771744 ps
CPU time 15.97 seconds
Started Aug 12 04:58:58 PM PDT 24
Finished Aug 12 04:59:14 PM PDT 24
Peak memory 226084 kb
Host smart-a64b3216-dd8d-4c76-833e-c90228db9403
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060970369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.4060970369
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1094720010
Short name T494
Test name
Test status
Simulation time 600001279 ps
CPU time 7.52 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:06 PM PDT 24
Peak memory 218380 kb
Host smart-5915005e-d0c7-430c-98d9-69ee6900526e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094720010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1094720010
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2064590546
Short name T54
Test name
Test status
Simulation time 1389430541 ps
CPU time 10.31 seconds
Started Aug 12 04:59:00 PM PDT 24
Finished Aug 12 04:59:10 PM PDT 24
Peak memory 218444 kb
Host smart-1f3c9005-1a40-41c1-8cc5-d5930ab0a4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064590546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2064590546
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3693277317
Short name T764
Test name
Test status
Simulation time 95457158 ps
CPU time 3.61 seconds
Started Aug 12 04:59:01 PM PDT 24
Finished Aug 12 04:59:05 PM PDT 24
Peak memory 217756 kb
Host smart-b00473fa-12d5-42dc-a6ad-e75991859ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693277317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3693277317
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.482748372
Short name T606
Test name
Test status
Simulation time 1149819512 ps
CPU time 29.3 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:29 PM PDT 24
Peak memory 251028 kb
Host smart-f2b6e364-2d62-442e-9aea-cea294a3ffa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482748372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.482748372
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3102767596
Short name T565
Test name
Test status
Simulation time 302796531 ps
CPU time 8.94 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:08 PM PDT 24
Peak memory 250984 kb
Host smart-bdb653b7-c550-48eb-bd39-837d9d8e2b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102767596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3102767596
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1303355903
Short name T78
Test name
Test status
Simulation time 14903285106 ps
CPU time 163.33 seconds
Started Aug 12 04:59:02 PM PDT 24
Finished Aug 12 05:01:45 PM PDT 24
Peak memory 267480 kb
Host smart-5a08ca6c-1b0a-495d-b9b9-61c8d0cb10d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303355903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1303355903
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3637170401
Short name T695
Test name
Test status
Simulation time 57754055 ps
CPU time 1.35 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:00 PM PDT 24
Peak memory 212088 kb
Host smart-b9fc35e8-672a-4f84-9cc1-0e4796ea2faf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637170401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3637170401
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2690248588
Short name T227
Test name
Test status
Simulation time 23211860 ps
CPU time 1.29 seconds
Started Aug 12 04:59:01 PM PDT 24
Finished Aug 12 04:59:03 PM PDT 24
Peak memory 209176 kb
Host smart-6c04a53f-2d5f-4b8b-81ea-c51c1504ff2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690248588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2690248588
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1453548674
Short name T420
Test name
Test status
Simulation time 5345750270 ps
CPU time 9.47 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:09 PM PDT 24
Peak memory 218404 kb
Host smart-f05431ae-0b34-43fc-ab2d-3354cace634e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453548674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1453548674
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.4019592611
Short name T424
Test name
Test status
Simulation time 601039873 ps
CPU time 5.69 seconds
Started Aug 12 04:59:01 PM PDT 24
Finished Aug 12 04:59:07 PM PDT 24
Peak memory 217436 kb
Host smart-3b3359b4-97b9-4569-80ef-2c26b258790a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019592611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.4019592611
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.467460774
Short name T609
Test name
Test status
Simulation time 189359533 ps
CPU time 2.52 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:01 PM PDT 24
Peak memory 218340 kb
Host smart-bc00aa0a-93ac-4eee-9a1f-8bd1a6fd228f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467460774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.467460774
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3709897683
Short name T697
Test name
Test status
Simulation time 374666091 ps
CPU time 13.32 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:12 PM PDT 24
Peak memory 220108 kb
Host smart-d9b35fbd-5298-4cf5-9b15-2a84beaf8176
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709897683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3709897683
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2904572303
Short name T669
Test name
Test status
Simulation time 202487032 ps
CPU time 9.85 seconds
Started Aug 12 04:59:01 PM PDT 24
Finished Aug 12 04:59:11 PM PDT 24
Peak memory 226104 kb
Host smart-d3d48fb9-185c-483a-a8de-f532ebe817e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904572303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2904572303
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2790579523
Short name T337
Test name
Test status
Simulation time 1596917711 ps
CPU time 9.22 seconds
Started Aug 12 04:59:00 PM PDT 24
Finished Aug 12 04:59:10 PM PDT 24
Peak memory 226160 kb
Host smart-bf399524-a037-4745-b705-264993e29d0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790579523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2790579523
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3743997019
Short name T53
Test name
Test status
Simulation time 1140533846 ps
CPU time 12.86 seconds
Started Aug 12 04:58:59 PM PDT 24
Finished Aug 12 04:59:12 PM PDT 24
Peak memory 218404 kb
Host smart-c5363b32-c317-49e0-8dc3-307eb7beedef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743997019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3743997019
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3792634494
Short name T579
Test name
Test status
Simulation time 54485562 ps
CPU time 3.24 seconds
Started Aug 12 04:59:00 PM PDT 24
Finished Aug 12 04:59:04 PM PDT 24
Peak memory 214916 kb
Host smart-d907188b-0001-48dd-9a6d-a9cd3ad363bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792634494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3792634494
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1430616017
Short name T506
Test name
Test status
Simulation time 1124642495 ps
CPU time 30.4 seconds
Started Aug 12 04:59:01 PM PDT 24
Finished Aug 12 04:59:32 PM PDT 24
Peak memory 251064 kb
Host smart-2ad94eab-df4b-4283-886f-e18dfe37252d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430616017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1430616017
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.379898385
Short name T92
Test name
Test status
Simulation time 368017742 ps
CPU time 4.01 seconds
Started Aug 12 04:59:00 PM PDT 24
Finished Aug 12 04:59:04 PM PDT 24
Peak memory 222744 kb
Host smart-93e562a4-9f31-4361-ad90-b725a3ec06cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379898385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.379898385
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3187588617
Short name T864
Test name
Test status
Simulation time 12832567201 ps
CPU time 208.33 seconds
Started Aug 12 04:59:01 PM PDT 24
Finished Aug 12 05:02:29 PM PDT 24
Peak memory 277576 kb
Host smart-e08847ae-e8dc-4e45-9db9-385d4fb89f91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187588617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3187588617
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1307737471
Short name T859
Test name
Test status
Simulation time 24206921 ps
CPU time 1.02 seconds
Started Aug 12 04:58:58 PM PDT 24
Finished Aug 12 04:58:59 PM PDT 24
Peak memory 212104 kb
Host smart-e718929b-76c4-4e93-8ccb-853a7142d411
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307737471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1307737471
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3423255441
Short name T777
Test name
Test status
Simulation time 16268419 ps
CPU time 0.95 seconds
Started Aug 12 04:59:11 PM PDT 24
Finished Aug 12 04:59:12 PM PDT 24
Peak memory 208988 kb
Host smart-28799d29-0842-40e4-959d-8d06a6f957d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423255441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3423255441
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.772834483
Short name T660
Test name
Test status
Simulation time 1077893881 ps
CPU time 10.95 seconds
Started Aug 12 04:59:08 PM PDT 24
Finished Aug 12 04:59:19 PM PDT 24
Peak memory 226140 kb
Host smart-e2593ae7-90d8-4b59-9cef-bdfced1fa268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772834483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.772834483
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3560233908
Short name T782
Test name
Test status
Simulation time 2876113935 ps
CPU time 8.44 seconds
Started Aug 12 04:59:07 PM PDT 24
Finished Aug 12 04:59:15 PM PDT 24
Peak memory 217868 kb
Host smart-f32ee63c-4a75-42d4-b775-eb92a2bfad65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560233908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3560233908
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1912573371
Short name T336
Test name
Test status
Simulation time 72092099 ps
CPU time 1.64 seconds
Started Aug 12 04:59:01 PM PDT 24
Finished Aug 12 04:59:03 PM PDT 24
Peak memory 222092 kb
Host smart-a602e22e-8609-434a-ad6f-c327ef5a92ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912573371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1912573371
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3780942821
Short name T829
Test name
Test status
Simulation time 483582996 ps
CPU time 12.98 seconds
Started Aug 12 04:59:07 PM PDT 24
Finished Aug 12 04:59:20 PM PDT 24
Peak memory 226144 kb
Host smart-bc54ecc1-27e5-4200-a5c7-b6ec023d8888
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780942821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3780942821
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1518045770
Short name T170
Test name
Test status
Simulation time 1424569978 ps
CPU time 11.28 seconds
Started Aug 12 04:59:09 PM PDT 24
Finished Aug 12 04:59:20 PM PDT 24
Peak memory 226164 kb
Host smart-74dbd104-e953-4b85-991f-a664ab5d7df3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518045770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1518045770
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.884321583
Short name T58
Test name
Test status
Simulation time 987157801 ps
CPU time 10.69 seconds
Started Aug 12 04:59:08 PM PDT 24
Finished Aug 12 04:59:19 PM PDT 24
Peak memory 226200 kb
Host smart-0665b8e8-2b33-41e7-a6c9-ec80d13beab3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884321583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.884321583
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1651926052
Short name T45
Test name
Test status
Simulation time 695566098 ps
CPU time 13.41 seconds
Started Aug 12 04:59:08 PM PDT 24
Finished Aug 12 04:59:21 PM PDT 24
Peak memory 218440 kb
Host smart-06b423c6-3530-4fcd-9de0-2588c7f543d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651926052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1651926052
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3007227399
Short name T847
Test name
Test status
Simulation time 93843789 ps
CPU time 2.06 seconds
Started Aug 12 04:59:03 PM PDT 24
Finished Aug 12 04:59:05 PM PDT 24
Peak memory 214612 kb
Host smart-13c2cd21-1bc4-4c96-9b62-fa3e4bac3cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007227399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3007227399
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3715090346
Short name T493
Test name
Test status
Simulation time 944179687 ps
CPU time 20.07 seconds
Started Aug 12 04:59:03 PM PDT 24
Finished Aug 12 04:59:23 PM PDT 24
Peak memory 251116 kb
Host smart-f705dc83-9f9a-4496-acb3-db4e096675cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715090346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3715090346
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.217459860
Short name T273
Test name
Test status
Simulation time 66157186 ps
CPU time 8.17 seconds
Started Aug 12 04:59:00 PM PDT 24
Finished Aug 12 04:59:09 PM PDT 24
Peak memory 251032 kb
Host smart-8e036498-ad62-4ee0-afd0-b6e70b962afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217459860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.217459860
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1611940216
Short name T86
Test name
Test status
Simulation time 3267730357 ps
CPU time 29.57 seconds
Started Aug 12 04:59:08 PM PDT 24
Finished Aug 12 04:59:38 PM PDT 24
Peak memory 234744 kb
Host smart-5e6a737b-86b6-4772-a5a4-5eac80b0f320
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611940216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1611940216
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3237527197
Short name T96
Test name
Test status
Simulation time 36623786 ps
CPU time 0.78 seconds
Started Aug 12 04:59:00 PM PDT 24
Finished Aug 12 04:59:00 PM PDT 24
Peak memory 208888 kb
Host smart-8cd201e2-0cb6-4c7a-8e2c-b1e2dfbd5503
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237527197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3237527197
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3560276721
Short name T735
Test name
Test status
Simulation time 18109279 ps
CPU time 0.91 seconds
Started Aug 12 04:59:09 PM PDT 24
Finished Aug 12 04:59:10 PM PDT 24
Peak memory 208900 kb
Host smart-21c7bf23-b1f0-4237-885d-b966d9a12b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560276721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3560276721
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1437108752
Short name T42
Test name
Test status
Simulation time 782463110 ps
CPU time 15.35 seconds
Started Aug 12 04:59:09 PM PDT 24
Finished Aug 12 04:59:25 PM PDT 24
Peak memory 218252 kb
Host smart-02193d11-1059-4c6d-99ac-10fb7d0837c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437108752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1437108752
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1244752615
Short name T871
Test name
Test status
Simulation time 1537690539 ps
CPU time 10.43 seconds
Started Aug 12 04:59:09 PM PDT 24
Finished Aug 12 04:59:20 PM PDT 24
Peak memory 217900 kb
Host smart-b5b813f5-ef3a-4308-ad3a-08aae6cb089e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244752615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1244752615
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2448640606
Short name T750
Test name
Test status
Simulation time 45211973 ps
CPU time 2.64 seconds
Started Aug 12 04:59:07 PM PDT 24
Finished Aug 12 04:59:10 PM PDT 24
Peak memory 218320 kb
Host smart-8c4ef492-f310-4c46-a832-b16fb140a132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448640606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2448640606
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2387322736
Short name T383
Test name
Test status
Simulation time 4117648479 ps
CPU time 10.04 seconds
Started Aug 12 04:59:12 PM PDT 24
Finished Aug 12 04:59:22 PM PDT 24
Peak memory 226268 kb
Host smart-70ddeec4-98ec-4b91-810c-8381863331a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387322736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2387322736
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1245783478
Short name T507
Test name
Test status
Simulation time 1648351611 ps
CPU time 21.93 seconds
Started Aug 12 04:59:08 PM PDT 24
Finished Aug 12 04:59:31 PM PDT 24
Peak memory 226092 kb
Host smart-7d958bdd-1cff-4d24-9b8d-55b1e583c8e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245783478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1245783478
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2147084149
Short name T715
Test name
Test status
Simulation time 685309065 ps
CPU time 15.13 seconds
Started Aug 12 04:59:09 PM PDT 24
Finished Aug 12 04:59:24 PM PDT 24
Peak memory 226172 kb
Host smart-5fa8ccfd-6b03-48aa-b872-79273eaa6a23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147084149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2147084149
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2979954147
Short name T585
Test name
Test status
Simulation time 75664379 ps
CPU time 1.79 seconds
Started Aug 12 04:59:09 PM PDT 24
Finished Aug 12 04:59:11 PM PDT 24
Peak memory 214200 kb
Host smart-67457d74-678a-4de1-82f3-e7e31337709e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979954147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2979954147
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2848759008
Short name T357
Test name
Test status
Simulation time 797523808 ps
CPU time 28.18 seconds
Started Aug 12 04:59:08 PM PDT 24
Finished Aug 12 04:59:36 PM PDT 24
Peak memory 245572 kb
Host smart-1f9b6f42-316f-42f8-8104-11258c15da20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848759008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2848759008
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3664842076
Short name T283
Test name
Test status
Simulation time 120252093 ps
CPU time 8.3 seconds
Started Aug 12 04:59:12 PM PDT 24
Finished Aug 12 04:59:21 PM PDT 24
Peak memory 251132 kb
Host smart-a6d19ba8-86ab-4373-95e4-ef134857e248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664842076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3664842076
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2298547130
Short name T88
Test name
Test status
Simulation time 1850394507 ps
CPU time 94.71 seconds
Started Aug 12 04:59:12 PM PDT 24
Finished Aug 12 05:00:47 PM PDT 24
Peak memory 251612 kb
Host smart-ec07d70f-4b23-4ac8-8a3c-cf8d7bdd95e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298547130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2298547130
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2608203168
Short name T739
Test name
Test status
Simulation time 20330404 ps
CPU time 1.6 seconds
Started Aug 12 04:59:11 PM PDT 24
Finished Aug 12 04:59:13 PM PDT 24
Peak memory 217996 kb
Host smart-28a25ee7-7ffd-4440-8569-fa2d9041de42
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608203168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2608203168
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3671566794
Short name T749
Test name
Test status
Simulation time 37839286 ps
CPU time 0.98 seconds
Started Aug 12 04:59:11 PM PDT 24
Finished Aug 12 04:59:12 PM PDT 24
Peak memory 208904 kb
Host smart-2c8928b1-564c-4cc8-b7c0-2ac9677d5c18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671566794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3671566794
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.23074855
Short name T640
Test name
Test status
Simulation time 1272765378 ps
CPU time 14.54 seconds
Started Aug 12 04:59:10 PM PDT 24
Finished Aug 12 04:59:24 PM PDT 24
Peak memory 218420 kb
Host smart-c0998d51-5a05-4ff2-b4b2-428f159673d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23074855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.23074855
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2017381627
Short name T861
Test name
Test status
Simulation time 6607896761 ps
CPU time 9.91 seconds
Started Aug 12 04:59:13 PM PDT 24
Finished Aug 12 04:59:23 PM PDT 24
Peak memory 217896 kb
Host smart-c45d036e-79ae-49a2-bbb6-d00921e8a3ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017381627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2017381627
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.816357971
Short name T362
Test name
Test status
Simulation time 196927929 ps
CPU time 2.26 seconds
Started Aug 12 04:59:12 PM PDT 24
Finished Aug 12 04:59:14 PM PDT 24
Peak memory 218424 kb
Host smart-29c9d356-2c3b-45a6-9cef-01766c2f27f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816357971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.816357971
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1008027928
Short name T563
Test name
Test status
Simulation time 1433111864 ps
CPU time 11.81 seconds
Started Aug 12 04:59:08 PM PDT 24
Finished Aug 12 04:59:19 PM PDT 24
Peak memory 226208 kb
Host smart-7263cf34-73d2-49df-9205-e3c95989eb56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008027928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1008027928
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.714721471
Short name T394
Test name
Test status
Simulation time 508702694 ps
CPU time 12.17 seconds
Started Aug 12 04:59:11 PM PDT 24
Finished Aug 12 04:59:24 PM PDT 24
Peak memory 226144 kb
Host smart-85c2f127-bd4a-4458-8893-29bda36eaa24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714721471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.714721471
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.605416448
Short name T561
Test name
Test status
Simulation time 511128003 ps
CPU time 9.29 seconds
Started Aug 12 04:59:08 PM PDT 24
Finished Aug 12 04:59:18 PM PDT 24
Peak memory 218384 kb
Host smart-0a8b4394-2407-4407-bdc6-bcfd82d27408
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605416448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.605416448
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.709864895
Short name T35
Test name
Test status
Simulation time 853606386 ps
CPU time 10.59 seconds
Started Aug 12 04:59:11 PM PDT 24
Finished Aug 12 04:59:22 PM PDT 24
Peak memory 218476 kb
Host smart-af732d3c-0b78-41bb-9fd3-a74958a59965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709864895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.709864895
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3945030595
Short name T780
Test name
Test status
Simulation time 93635625 ps
CPU time 2.33 seconds
Started Aug 12 04:59:10 PM PDT 24
Finished Aug 12 04:59:12 PM PDT 24
Peak memory 214512 kb
Host smart-5bc21996-b6b0-4113-ab39-37259674c3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945030595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3945030595
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1912810588
Short name T278
Test name
Test status
Simulation time 239944953 ps
CPU time 24.33 seconds
Started Aug 12 04:59:10 PM PDT 24
Finished Aug 12 04:59:34 PM PDT 24
Peak memory 250988 kb
Host smart-e75148a1-f5fd-41d5-9d45-823a73a43d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912810588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1912810588
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2178215924
Short name T430
Test name
Test status
Simulation time 69134225 ps
CPU time 8.44 seconds
Started Aug 12 04:59:09 PM PDT 24
Finished Aug 12 04:59:18 PM PDT 24
Peak memory 251032 kb
Host smart-7b5e0521-e746-48bd-a950-85f35c992f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178215924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2178215924
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3630727122
Short name T66
Test name
Test status
Simulation time 8630365482 ps
CPU time 47 seconds
Started Aug 12 04:59:10 PM PDT 24
Finished Aug 12 04:59:57 PM PDT 24
Peak memory 250780 kb
Host smart-7ea6c590-2c6a-4bb2-9224-74ab0856ff8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630727122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3630727122
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.294706022
Short name T161
Test name
Test status
Simulation time 19229693344 ps
CPU time 115.68 seconds
Started Aug 12 04:59:12 PM PDT 24
Finished Aug 12 05:01:08 PM PDT 24
Peak memory 264912 kb
Host smart-37fb683d-8775-4d99-b409-63e89167ae8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=294706022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.294706022
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2357248307
Short name T591
Test name
Test status
Simulation time 36961063 ps
CPU time 0.99 seconds
Started Aug 12 04:59:13 PM PDT 24
Finished Aug 12 04:59:14 PM PDT 24
Peak memory 212008 kb
Host smart-559e098d-6cb1-401b-a258-5c49e4b0ffc1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357248307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2357248307
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.4058275858
Short name T258
Test name
Test status
Simulation time 18806032 ps
CPU time 1.17 seconds
Started Aug 12 04:59:13 PM PDT 24
Finished Aug 12 04:59:14 PM PDT 24
Peak memory 209068 kb
Host smart-c4fde25b-7ad3-4613-9b65-d799519c3c05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058275858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.4058275858
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1804461251
Short name T419
Test name
Test status
Simulation time 1335647491 ps
CPU time 11.33 seconds
Started Aug 12 04:59:11 PM PDT 24
Finished Aug 12 04:59:23 PM PDT 24
Peak memory 218268 kb
Host smart-ed5f9881-5a53-4e4a-9ca2-fa0d1bfbf6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804461251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1804461251
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1563429686
Short name T566
Test name
Test status
Simulation time 196348086 ps
CPU time 1.78 seconds
Started Aug 12 04:59:13 PM PDT 24
Finished Aug 12 04:59:15 PM PDT 24
Peak memory 217648 kb
Host smart-6b16db0f-5da9-4b51-b017-bcdb07ffa137
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563429686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1563429686
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1830921429
Short name T528
Test name
Test status
Simulation time 64998267 ps
CPU time 3.78 seconds
Started Aug 12 04:59:12 PM PDT 24
Finished Aug 12 04:59:16 PM PDT 24
Peak memory 218424 kb
Host smart-035a591d-f701-4708-a270-7e9d4798b3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830921429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1830921429
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2124300641
Short name T472
Test name
Test status
Simulation time 891214570 ps
CPU time 13.04 seconds
Started Aug 12 04:59:11 PM PDT 24
Finished Aug 12 04:59:24 PM PDT 24
Peak memory 218384 kb
Host smart-d39f125b-06e3-4f6a-ae59-253414db7b68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124300641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2124300641
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2379581869
Short name T492
Test name
Test status
Simulation time 1109448634 ps
CPU time 11.7 seconds
Started Aug 12 04:59:13 PM PDT 24
Finished Aug 12 04:59:25 PM PDT 24
Peak memory 226136 kb
Host smart-8e8e2a37-4fd2-4739-aeac-f9a0ba345eac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379581869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2379581869
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.356298165
Short name T398
Test name
Test status
Simulation time 1289496458 ps
CPU time 11.17 seconds
Started Aug 12 04:59:11 PM PDT 24
Finished Aug 12 04:59:22 PM PDT 24
Peak memory 218368 kb
Host smart-4a3156ae-f76b-480b-80ae-fcdd15e06b0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356298165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.356298165
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2721127607
Short name T333
Test name
Test status
Simulation time 1070230876 ps
CPU time 8.85 seconds
Started Aug 12 04:59:13 PM PDT 24
Finished Aug 12 04:59:22 PM PDT 24
Peak memory 218408 kb
Host smart-d6f556e1-813b-4815-bc90-a3bb1f67505b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721127607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2721127607
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2311215931
Short name T769
Test name
Test status
Simulation time 26699802 ps
CPU time 1.45 seconds
Started Aug 12 04:59:12 PM PDT 24
Finished Aug 12 04:59:14 PM PDT 24
Peak memory 213716 kb
Host smart-7f3ba29d-905f-4e4c-a868-78098f504886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311215931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2311215931
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2005814479
Short name T835
Test name
Test status
Simulation time 192824974 ps
CPU time 24.79 seconds
Started Aug 12 04:59:14 PM PDT 24
Finished Aug 12 04:59:39 PM PDT 24
Peak memory 251120 kb
Host smart-9acbfc00-263b-42e4-b649-24894508fca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005814479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2005814479
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.757110893
Short name T178
Test name
Test status
Simulation time 92511005 ps
CPU time 8.08 seconds
Started Aug 12 04:59:13 PM PDT 24
Finished Aug 12 04:59:21 PM PDT 24
Peak memory 251072 kb
Host smart-b113e353-1ca8-49ec-8a06-55125e68c29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757110893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.757110893
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3829972088
Short name T628
Test name
Test status
Simulation time 20732108856 ps
CPU time 181.69 seconds
Started Aug 12 04:59:11 PM PDT 24
Finished Aug 12 05:02:13 PM PDT 24
Peak memory 283872 kb
Host smart-df2ebcd3-9c83-4d26-a191-27c39405ab40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829972088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3829972088
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.983561240
Short name T612
Test name
Test status
Simulation time 21370986 ps
CPU time 0.77 seconds
Started Aug 12 04:59:11 PM PDT 24
Finished Aug 12 04:59:12 PM PDT 24
Peak memory 209080 kb
Host smart-104e5511-7399-461d-a7c9-a46aed8c1ef1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983561240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.983561240
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3213990850
Short name T93
Test name
Test status
Simulation time 57346158 ps
CPU time 0.83 seconds
Started Aug 12 04:56:35 PM PDT 24
Finished Aug 12 04:56:36 PM PDT 24
Peak memory 208824 kb
Host smart-d0c8813b-0ce5-4743-a9a5-632d5822fa1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213990850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3213990850
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.4199071550
Short name T666
Test name
Test status
Simulation time 1119730244 ps
CPU time 11.02 seconds
Started Aug 12 04:56:30 PM PDT 24
Finished Aug 12 04:56:41 PM PDT 24
Peak memory 218352 kb
Host smart-2c03a824-c5b7-444c-a5d7-3c477c08744a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199071550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.4199071550
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1924434225
Short name T22
Test name
Test status
Simulation time 300209219 ps
CPU time 2.87 seconds
Started Aug 12 04:56:27 PM PDT 24
Finished Aug 12 04:56:30 PM PDT 24
Peak memory 217380 kb
Host smart-3aa43df3-6612-412f-8649-0c895d932968
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924434225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1924434225
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.857021038
Short name T327
Test name
Test status
Simulation time 5965007952 ps
CPU time 22.77 seconds
Started Aug 12 04:56:26 PM PDT 24
Finished Aug 12 04:56:49 PM PDT 24
Peak memory 218388 kb
Host smart-7503f1b7-aa83-4a45-b3a0-fd28c58382e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857021038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.857021038
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1471886445
Short name T418
Test name
Test status
Simulation time 871419159 ps
CPU time 10.99 seconds
Started Aug 12 04:56:27 PM PDT 24
Finished Aug 12 04:56:38 PM PDT 24
Peak memory 217824 kb
Host smart-dc2e2fd7-2484-4f3d-93f4-32ff6d1b8231
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471886445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
471886445
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.516098222
Short name T543
Test name
Test status
Simulation time 215688222 ps
CPU time 1.92 seconds
Started Aug 12 04:56:25 PM PDT 24
Finished Aug 12 04:56:27 PM PDT 24
Peak memory 221592 kb
Host smart-5de8df17-11ca-43ce-b32a-c0a5f2dcf452
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516098222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.516098222
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3135679554
Short name T284
Test name
Test status
Simulation time 3435484904 ps
CPU time 13.11 seconds
Started Aug 12 04:56:24 PM PDT 24
Finished Aug 12 04:56:38 PM PDT 24
Peak memory 217792 kb
Host smart-14dd6cc6-e8b5-4335-b6ce-9a687b158e68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135679554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3135679554
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.23278511
Short name T251
Test name
Test status
Simulation time 791286693 ps
CPU time 3.08 seconds
Started Aug 12 04:56:24 PM PDT 24
Finished Aug 12 04:56:27 PM PDT 24
Peak memory 217700 kb
Host smart-94b7e1b2-2c86-4351-a362-e15b9ba41243
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23278511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.23278511
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3205667148
Short name T587
Test name
Test status
Simulation time 6083149101 ps
CPU time 86.6 seconds
Started Aug 12 04:56:24 PM PDT 24
Finished Aug 12 04:57:51 PM PDT 24
Peak memory 250980 kb
Host smart-e433e4e4-0f46-46ea-bfd3-a1ebc02ea3fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205667148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3205667148
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3339496975
Short name T435
Test name
Test status
Simulation time 1201258861 ps
CPU time 38.9 seconds
Started Aug 12 04:56:23 PM PDT 24
Finished Aug 12 04:57:02 PM PDT 24
Peak memory 250844 kb
Host smart-5c298e8f-fc95-4ea2-a71a-66cca4e15d1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339496975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3339496975
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1429166836
Short name T592
Test name
Test status
Simulation time 49317669 ps
CPU time 1.92 seconds
Started Aug 12 04:56:24 PM PDT 24
Finished Aug 12 04:56:26 PM PDT 24
Peak memory 218336 kb
Host smart-0f2a411c-0369-49a5-9261-558ef5c0e4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429166836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1429166836
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.620406555
Short name T65
Test name
Test status
Simulation time 175479840 ps
CPU time 12.02 seconds
Started Aug 12 04:56:25 PM PDT 24
Finished Aug 12 04:56:37 PM PDT 24
Peak memory 217832 kb
Host smart-1e8c277c-a923-450d-bc49-719b871fc64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620406555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.620406555
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1865631689
Short name T40
Test name
Test status
Simulation time 347507556 ps
CPU time 16.17 seconds
Started Aug 12 04:56:24 PM PDT 24
Finished Aug 12 04:56:41 PM PDT 24
Peak memory 219300 kb
Host smart-f76a01f7-19d7-4d37-82dd-aaa3a92193b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865631689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1865631689
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.664574863
Short name T670
Test name
Test status
Simulation time 720731093 ps
CPU time 16.71 seconds
Started Aug 12 04:56:24 PM PDT 24
Finished Aug 12 04:56:41 PM PDT 24
Peak memory 226076 kb
Host smart-b0ae264d-22a3-41ec-9734-454b42d5eadb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664574863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.664574863
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2128275304
Short name T436
Test name
Test status
Simulation time 426211468 ps
CPU time 10.18 seconds
Started Aug 12 04:56:25 PM PDT 24
Finished Aug 12 04:56:35 PM PDT 24
Peak memory 218380 kb
Host smart-1834199b-1f60-4397-b40a-d37e0216f8bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128275304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
128275304
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.547146840
Short name T438
Test name
Test status
Simulation time 1003135651 ps
CPU time 8.26 seconds
Started Aug 12 04:56:25 PM PDT 24
Finished Aug 12 04:56:33 PM PDT 24
Peak memory 218440 kb
Host smart-c2aba530-547b-401d-8e04-3c22e8040cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547146840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.547146840
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1674519209
Short name T654
Test name
Test status
Simulation time 50681378 ps
CPU time 3.63 seconds
Started Aug 12 04:56:26 PM PDT 24
Finished Aug 12 04:56:30 PM PDT 24
Peak memory 215324 kb
Host smart-77334ff1-f07c-44ab-b22b-b2d7e61c26ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674519209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1674519209
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3087912397
Short name T422
Test name
Test status
Simulation time 5595913008 ps
CPU time 30.8 seconds
Started Aug 12 04:56:23 PM PDT 24
Finished Aug 12 04:56:54 PM PDT 24
Peak memory 251180 kb
Host smart-357f3a29-7911-4bf1-bc5e-3eb51c95042b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087912397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3087912397
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1541010291
Short name T358
Test name
Test status
Simulation time 139117863 ps
CPU time 9.13 seconds
Started Aug 12 04:56:26 PM PDT 24
Finished Aug 12 04:56:36 PM PDT 24
Peak memory 251092 kb
Host smart-7dc618c9-613e-425e-b956-3894b67d7334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541010291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1541010291
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3323810730
Short name T352
Test name
Test status
Simulation time 43305942446 ps
CPU time 221.48 seconds
Started Aug 12 04:56:35 PM PDT 24
Finished Aug 12 05:00:17 PM PDT 24
Peak memory 422064 kb
Host smart-6c3411a1-6af7-47fe-9330-32310d856e03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323810730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3323810730
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.28308334
Short name T160
Test name
Test status
Simulation time 2945114934 ps
CPU time 111.6 seconds
Started Aug 12 04:56:32 PM PDT 24
Finished Aug 12 04:58:24 PM PDT 24
Peak memory 267500 kb
Host smart-993d9947-2f16-4800-be2d-02977a663aa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=28308334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.28308334
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3273607523
Short name T385
Test name
Test status
Simulation time 12638176 ps
CPU time 0.83 seconds
Started Aug 12 04:56:25 PM PDT 24
Finished Aug 12 04:56:26 PM PDT 24
Peak memory 209004 kb
Host smart-23dad77a-4550-4690-b515-c66aa1e84886
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273607523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3273607523
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3748351868
Short name T575
Test name
Test status
Simulation time 23404059 ps
CPU time 0.83 seconds
Started Aug 12 04:56:33 PM PDT 24
Finished Aug 12 04:56:33 PM PDT 24
Peak memory 208868 kb
Host smart-ae66ef9c-329c-4936-847d-9122a74ac3a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748351868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3748351868
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.724004998
Short name T210
Test name
Test status
Simulation time 45058886 ps
CPU time 0.98 seconds
Started Aug 12 04:56:33 PM PDT 24
Finished Aug 12 04:56:34 PM PDT 24
Peak memory 208748 kb
Host smart-45c1f954-c2be-44fc-a13c-c476aeccce0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724004998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.724004998
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.4103118034
Short name T803
Test name
Test status
Simulation time 1746484066 ps
CPU time 18.46 seconds
Started Aug 12 04:56:32 PM PDT 24
Finished Aug 12 04:56:51 PM PDT 24
Peak memory 218412 kb
Host smart-ed0dee37-a50c-48c6-b6d4-5a37a420ad54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103118034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.4103118034
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.316282010
Short name T437
Test name
Test status
Simulation time 1596650615 ps
CPU time 2.91 seconds
Started Aug 12 04:56:34 PM PDT 24
Finished Aug 12 04:56:37 PM PDT 24
Peak memory 217836 kb
Host smart-1e3d1748-84b6-42dc-afa0-575411bc62f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316282010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.316282010
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.4086688619
Short name T403
Test name
Test status
Simulation time 6597909703 ps
CPU time 24.29 seconds
Started Aug 12 04:56:34 PM PDT 24
Finished Aug 12 04:56:58 PM PDT 24
Peak memory 219016 kb
Host smart-5306b140-eeee-4f71-8738-ecd0c44ac85c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086688619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.4086688619
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2920366753
Short name T578
Test name
Test status
Simulation time 164169481 ps
CPU time 3.38 seconds
Started Aug 12 04:56:32 PM PDT 24
Finished Aug 12 04:56:36 PM PDT 24
Peak memory 217884 kb
Host smart-f403119d-eb7b-451d-bc74-ac78e8c331f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920366753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2
920366753
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2728176677
Short name T718
Test name
Test status
Simulation time 736714754 ps
CPU time 6.53 seconds
Started Aug 12 04:56:34 PM PDT 24
Finished Aug 12 04:56:41 PM PDT 24
Peak memory 218264 kb
Host smart-b5775c77-0700-4008-bac3-434c634d7252
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728176677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2728176677
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1766306395
Short name T607
Test name
Test status
Simulation time 1432955206 ps
CPU time 10.67 seconds
Started Aug 12 04:56:32 PM PDT 24
Finished Aug 12 04:56:43 PM PDT 24
Peak memory 217772 kb
Host smart-c85f3197-fa32-47a6-82ab-0eabd9412faf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766306395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1766306395
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1409887145
Short name T622
Test name
Test status
Simulation time 733889909 ps
CPU time 8.55 seconds
Started Aug 12 04:56:32 PM PDT 24
Finished Aug 12 04:56:40 PM PDT 24
Peak memory 217704 kb
Host smart-c2a05ad9-316b-4b16-ac44-7d6fccdfdd10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409887145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1409887145
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3389227678
Short name T415
Test name
Test status
Simulation time 15424042546 ps
CPU time 44.05 seconds
Started Aug 12 04:56:33 PM PDT 24
Finished Aug 12 04:57:17 PM PDT 24
Peak memory 267456 kb
Host smart-a6b7a4e1-1908-4d73-9e9c-59422387bf93
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389227678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3389227678
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2750289368
Short name T414
Test name
Test status
Simulation time 930429744 ps
CPU time 31.18 seconds
Started Aug 12 04:56:34 PM PDT 24
Finished Aug 12 04:57:05 PM PDT 24
Peak memory 251008 kb
Host smart-d2ede6e4-fa91-488e-9339-c1ed0b2a2b13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750289368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2750289368
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1646179863
Short name T872
Test name
Test status
Simulation time 258310930 ps
CPU time 2.98 seconds
Started Aug 12 04:56:33 PM PDT 24
Finished Aug 12 04:56:36 PM PDT 24
Peak memory 218412 kb
Host smart-5417955b-2d99-418d-8daa-1a6480d7f05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646179863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1646179863
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1772941972
Short name T98
Test name
Test status
Simulation time 460812260 ps
CPU time 6.61 seconds
Started Aug 12 04:56:31 PM PDT 24
Finished Aug 12 04:56:38 PM PDT 24
Peak memory 214684 kb
Host smart-3dc34a01-5c8a-4576-8648-7e3eb68ca1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772941972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1772941972
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3971425777
Short name T520
Test name
Test status
Simulation time 345367076 ps
CPU time 13.4 seconds
Started Aug 12 04:56:32 PM PDT 24
Finished Aug 12 04:56:46 PM PDT 24
Peak memory 219304 kb
Host smart-b9d3b41b-9885-40dd-88ef-8ba9f378577a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971425777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3971425777
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1730995763
Short name T858
Test name
Test status
Simulation time 252920237 ps
CPU time 10.91 seconds
Started Aug 12 04:56:34 PM PDT 24
Finished Aug 12 04:56:45 PM PDT 24
Peak memory 226160 kb
Host smart-01b9ced7-4ffd-493a-a4ec-3d6e7bf0032e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730995763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1730995763
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2681703715
Short name T784
Test name
Test status
Simulation time 255698258 ps
CPU time 9.15 seconds
Started Aug 12 04:56:35 PM PDT 24
Finished Aug 12 04:56:45 PM PDT 24
Peak memory 226184 kb
Host smart-c4019308-82a1-4925-8336-14eaf0cda563
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681703715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
681703715
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1480453954
Short name T679
Test name
Test status
Simulation time 977398023 ps
CPU time 16.63 seconds
Started Aug 12 04:56:34 PM PDT 24
Finished Aug 12 04:56:51 PM PDT 24
Peak memory 218496 kb
Host smart-6b1bc0d9-60a0-45fd-b601-3e4f700f5ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480453954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1480453954
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3038429214
Short name T740
Test name
Test status
Simulation time 233817474 ps
CPU time 3.6 seconds
Started Aug 12 04:56:32 PM PDT 24
Finished Aug 12 04:56:35 PM PDT 24
Peak memory 215152 kb
Host smart-6fad70cf-a0b3-4960-9d81-da6f698338dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038429214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3038429214
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1601158645
Short name T374
Test name
Test status
Simulation time 794014414 ps
CPU time 22.04 seconds
Started Aug 12 04:56:32 PM PDT 24
Finished Aug 12 04:56:54 PM PDT 24
Peak memory 251028 kb
Host smart-17e1ca7a-3ab0-42f3-a843-20fc7f6c3c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601158645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1601158645
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3587948693
Short name T463
Test name
Test status
Simulation time 70887207 ps
CPU time 8.1 seconds
Started Aug 12 04:56:32 PM PDT 24
Finished Aug 12 04:56:41 PM PDT 24
Peak memory 251060 kb
Host smart-55d2a25f-8e11-40a7-b1ab-5617d9767a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587948693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3587948693
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.903938080
Short name T681
Test name
Test status
Simulation time 58360418805 ps
CPU time 409.5 seconds
Started Aug 12 04:56:33 PM PDT 24
Finished Aug 12 05:03:22 PM PDT 24
Peak memory 283888 kb
Host smart-d70f572c-ea33-401f-9bd1-88f95b42a7ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903938080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.903938080
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.2112723060
Short name T149
Test name
Test status
Simulation time 4735294178 ps
CPU time 159.77 seconds
Started Aug 12 04:56:34 PM PDT 24
Finished Aug 12 04:59:14 PM PDT 24
Peak memory 259240 kb
Host smart-9bcdd66a-f4e8-4c90-9fb2-a17c64deb475
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2112723060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.2112723060
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.911145188
Short name T881
Test name
Test status
Simulation time 57447423 ps
CPU time 1.07 seconds
Started Aug 12 04:56:40 PM PDT 24
Finished Aug 12 04:56:42 PM PDT 24
Peak memory 209116 kb
Host smart-42903f6a-1b12-46ff-aa32-1da32faf11f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911145188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.911145188
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1537736488
Short name T813
Test name
Test status
Simulation time 11287979 ps
CPU time 0.82 seconds
Started Aug 12 04:56:38 PM PDT 24
Finished Aug 12 04:56:40 PM PDT 24
Peak memory 208756 kb
Host smart-dd2b8748-edf6-4088-a7e9-549cab03826b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537736488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1537736488
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2812224050
Short name T523
Test name
Test status
Simulation time 1503205019 ps
CPU time 13.77 seconds
Started Aug 12 04:56:37 PM PDT 24
Finished Aug 12 04:56:51 PM PDT 24
Peak memory 218412 kb
Host smart-053bdcd2-e9ae-45c9-8860-cce81785f214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812224050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2812224050
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3581337988
Short name T21
Test name
Test status
Simulation time 532598793 ps
CPU time 12.74 seconds
Started Aug 12 04:56:38 PM PDT 24
Finished Aug 12 04:56:51 PM PDT 24
Peak memory 217804 kb
Host smart-eafd5801-0de6-4ec2-aabd-2d1a5ce6ed72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581337988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3581337988
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1602045389
Short name T567
Test name
Test status
Simulation time 4696618344 ps
CPU time 27.84 seconds
Started Aug 12 04:56:46 PM PDT 24
Finished Aug 12 04:57:14 PM PDT 24
Peak memory 218372 kb
Host smart-8e3971ea-90bd-48ff-ac28-c258282f02d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602045389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1602045389
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3934793709
Short name T433
Test name
Test status
Simulation time 763418027 ps
CPU time 9.74 seconds
Started Aug 12 04:56:39 PM PDT 24
Finished Aug 12 04:56:49 PM PDT 24
Peak memory 217932 kb
Host smart-d5d2b168-7428-43f2-8126-85e3891c1b35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934793709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
934793709
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.112924603
Short name T551
Test name
Test status
Simulation time 518643844 ps
CPU time 8.29 seconds
Started Aug 12 04:56:46 PM PDT 24
Finished Aug 12 04:56:55 PM PDT 24
Peak memory 218304 kb
Host smart-7947a86a-6592-4d92-a814-ae0ac2e963aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112924603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.112924603
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2343392818
Short name T709
Test name
Test status
Simulation time 660375985 ps
CPU time 9.28 seconds
Started Aug 12 04:56:39 PM PDT 24
Finished Aug 12 04:56:49 PM PDT 24
Peak memory 217692 kb
Host smart-e1926ca7-27c8-4d37-8620-544faa2139fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343392818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2343392818
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3039029878
Short name T828
Test name
Test status
Simulation time 1168698611 ps
CPU time 5 seconds
Started Aug 12 04:56:41 PM PDT 24
Finished Aug 12 04:56:46 PM PDT 24
Peak memory 217792 kb
Host smart-2cbb378d-4725-4a1f-8587-adae6b72b2d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039029878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3039029878
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.634099317
Short name T796
Test name
Test status
Simulation time 2213970402 ps
CPU time 37 seconds
Started Aug 12 04:56:40 PM PDT 24
Finished Aug 12 04:57:17 PM PDT 24
Peak memory 267496 kb
Host smart-1afc63b3-ee4f-4e70-96d9-a7ff7047c99b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634099317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.634099317
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2047495069
Short name T535
Test name
Test status
Simulation time 597055695 ps
CPU time 21.68 seconds
Started Aug 12 04:56:42 PM PDT 24
Finished Aug 12 04:57:04 PM PDT 24
Peak memory 246688 kb
Host smart-19e0ce5e-0c66-466f-b7ed-51309a0aa847
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047495069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2047495069
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1068421767
Short name T678
Test name
Test status
Simulation time 165319975 ps
CPU time 3.54 seconds
Started Aug 12 04:56:39 PM PDT 24
Finished Aug 12 04:56:42 PM PDT 24
Peak memory 218356 kb
Host smart-648374f8-e658-48a8-860c-3514ec2a2f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068421767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1068421767
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1889319198
Short name T833
Test name
Test status
Simulation time 414384986 ps
CPU time 14.45 seconds
Started Aug 12 04:56:39 PM PDT 24
Finished Aug 12 04:56:54 PM PDT 24
Peak memory 217792 kb
Host smart-cbf68731-68c1-4177-a487-ce275dd57c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889319198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1889319198
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3787565373
Short name T734
Test name
Test status
Simulation time 4311613759 ps
CPU time 17 seconds
Started Aug 12 04:56:47 PM PDT 24
Finished Aug 12 04:57:04 PM PDT 24
Peak memory 226208 kb
Host smart-712dfbc5-5916-404a-bdbd-21be490a5209
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787565373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3787565373
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2686843481
Short name T882
Test name
Test status
Simulation time 1628257164 ps
CPU time 10.33 seconds
Started Aug 12 04:56:46 PM PDT 24
Finished Aug 12 04:56:57 PM PDT 24
Peak memory 226096 kb
Host smart-27420ffc-a313-489f-8760-c7443ab57a43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686843481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2686843481
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.367389499
Short name T534
Test name
Test status
Simulation time 2004380462 ps
CPU time 10.84 seconds
Started Aug 12 04:56:38 PM PDT 24
Finished Aug 12 04:56:49 PM PDT 24
Peak memory 218416 kb
Host smart-651ad8d3-ddb7-4b94-8507-a6f5ecc71b6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367389499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.367389499
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2717362444
Short name T47
Test name
Test status
Simulation time 306044730 ps
CPU time 10.41 seconds
Started Aug 12 04:56:42 PM PDT 24
Finished Aug 12 04:56:52 PM PDT 24
Peak memory 218536 kb
Host smart-a1a713a3-1d2f-4808-9c4a-801ea56e49c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717362444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2717362444
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2111483261
Short name T282
Test name
Test status
Simulation time 22790602 ps
CPU time 1.78 seconds
Started Aug 12 04:56:31 PM PDT 24
Finished Aug 12 04:56:33 PM PDT 24
Peak memory 214112 kb
Host smart-2e5aef0e-3a31-4796-8f4f-fbb3d22d37dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111483261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2111483261
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3747422412
Short name T257
Test name
Test status
Simulation time 270487229 ps
CPU time 28.2 seconds
Started Aug 12 04:56:32 PM PDT 24
Finished Aug 12 04:57:00 PM PDT 24
Peak memory 251024 kb
Host smart-b665584d-2520-417d-8059-8fe0261c5e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747422412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3747422412
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1188687907
Short name T700
Test name
Test status
Simulation time 539902904 ps
CPU time 6.61 seconds
Started Aug 12 04:56:38 PM PDT 24
Finished Aug 12 04:56:45 PM PDT 24
Peak memory 247084 kb
Host smart-9d3c56c8-9cfc-43da-916b-43cc31e17a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188687907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1188687907
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1583495167
Short name T783
Test name
Test status
Simulation time 13358141545 ps
CPU time 140.16 seconds
Started Aug 12 04:56:38 PM PDT 24
Finished Aug 12 04:58:59 PM PDT 24
Peak memory 251108 kb
Host smart-198a5eac-eb2a-4066-84e1-0e7c1e4e4f61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583495167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1583495167
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2255797632
Short name T304
Test name
Test status
Simulation time 144483419 ps
CPU time 0.88 seconds
Started Aug 12 04:56:34 PM PDT 24
Finished Aug 12 04:56:35 PM PDT 24
Peak memory 212048 kb
Host smart-320de1c4-071f-4b8f-b17f-2ffb9d7e2e15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255797632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2255797632
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.965707705
Short name T310
Test name
Test status
Simulation time 58845138 ps
CPU time 0.94 seconds
Started Aug 12 04:56:48 PM PDT 24
Finished Aug 12 04:56:50 PM PDT 24
Peak memory 208980 kb
Host smart-9ccbdfcc-b6ec-43a2-bbc6-461bf71b3931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965707705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.965707705
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.467699835
Short name T179
Test name
Test status
Simulation time 1760935682 ps
CPU time 13.25 seconds
Started Aug 12 04:56:46 PM PDT 24
Finished Aug 12 04:56:59 PM PDT 24
Peak memory 218356 kb
Host smart-eadb5b2a-bd5c-4bb7-a1b6-cfaac125a48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467699835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.467699835
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1485127646
Short name T805
Test name
Test status
Simulation time 870647197 ps
CPU time 7.92 seconds
Started Aug 12 04:56:46 PM PDT 24
Finished Aug 12 04:56:54 PM PDT 24
Peak memory 217860 kb
Host smart-addd3a23-9b55-42bf-abab-d03477184b4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485127646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1485127646
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3394997857
Short name T412
Test name
Test status
Simulation time 3921653326 ps
CPU time 104.69 seconds
Started Aug 12 04:56:50 PM PDT 24
Finished Aug 12 04:58:36 PM PDT 24
Peak memory 220276 kb
Host smart-f69aee6b-19b5-42f0-b547-7b938272510e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394997857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3394997857
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.557466327
Short name T852
Test name
Test status
Simulation time 3848744540 ps
CPU time 19.44 seconds
Started Aug 12 04:56:45 PM PDT 24
Finished Aug 12 04:57:05 PM PDT 24
Peak memory 217948 kb
Host smart-2729dffc-ad49-4179-bca6-b7f29141d6a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557466327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.557466327
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.684520262
Short name T752
Test name
Test status
Simulation time 5174108307 ps
CPU time 15.74 seconds
Started Aug 12 04:56:44 PM PDT 24
Finished Aug 12 04:57:00 PM PDT 24
Peak memory 220072 kb
Host smart-883a36ea-c485-439f-a801-61e4fc658bff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684520262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.684520262
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1126690141
Short name T708
Test name
Test status
Simulation time 780068922 ps
CPU time 24.58 seconds
Started Aug 12 04:56:45 PM PDT 24
Finished Aug 12 04:57:10 PM PDT 24
Peak memory 217788 kb
Host smart-52734994-56fb-40e6-9702-44819333cc8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126690141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1126690141
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1214038566
Short name T72
Test name
Test status
Simulation time 132778864 ps
CPU time 1.68 seconds
Started Aug 12 04:56:46 PM PDT 24
Finished Aug 12 04:56:47 PM PDT 24
Peak memory 217792 kb
Host smart-6fbddc57-3e35-4115-b1a1-68826b7c95a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214038566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1214038566
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.932002996
Short name T270
Test name
Test status
Simulation time 1518085405 ps
CPU time 47.62 seconds
Started Aug 12 04:56:48 PM PDT 24
Finished Aug 12 04:57:36 PM PDT 24
Peak memory 268108 kb
Host smart-3a37e642-1b2f-4f23-8164-102e2ae6f922
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932002996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.932002996
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3514772239
Short name T390
Test name
Test status
Simulation time 408813276 ps
CPU time 13.65 seconds
Started Aug 12 04:56:46 PM PDT 24
Finished Aug 12 04:57:00 PM PDT 24
Peak memory 251000 kb
Host smart-d3d846fb-bcee-4dc3-b4b6-c3cb6b66526e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514772239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3514772239
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2226694831
Short name T521
Test name
Test status
Simulation time 30815906 ps
CPU time 1.97 seconds
Started Aug 12 04:56:47 PM PDT 24
Finished Aug 12 04:56:49 PM PDT 24
Peak memory 218344 kb
Host smart-840daafe-2163-4b14-ad72-e230e1bb6e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226694831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2226694831
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.4135103317
Short name T665
Test name
Test status
Simulation time 1078279665 ps
CPU time 15.47 seconds
Started Aug 12 04:56:44 PM PDT 24
Finished Aug 12 04:57:00 PM PDT 24
Peak memory 214992 kb
Host smart-9e379901-64b3-49a7-8540-7abb6740d754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135103317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.4135103317
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3438072831
Short name T154
Test name
Test status
Simulation time 1101056489 ps
CPU time 13.17 seconds
Started Aug 12 04:56:46 PM PDT 24
Finished Aug 12 04:56:59 PM PDT 24
Peak memory 220088 kb
Host smart-34184c29-fe37-4473-939e-93273d76d2d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438072831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3438072831
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2742392595
Short name T226
Test name
Test status
Simulation time 1506083613 ps
CPU time 10.02 seconds
Started Aug 12 04:56:46 PM PDT 24
Finished Aug 12 04:56:56 PM PDT 24
Peak memory 225440 kb
Host smart-10aec90a-b3af-4b2e-ba16-8504a654f175
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742392595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2742392595
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3270010099
Short name T363
Test name
Test status
Simulation time 1062862771 ps
CPU time 10.51 seconds
Started Aug 12 04:56:45 PM PDT 24
Finished Aug 12 04:56:55 PM PDT 24
Peak memory 218396 kb
Host smart-ce14d7ee-63a0-48a2-8c9f-3818279c0348
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270010099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
270010099
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3532658381
Short name T485
Test name
Test status
Simulation time 1435501851 ps
CPU time 13.15 seconds
Started Aug 12 04:56:47 PM PDT 24
Finished Aug 12 04:57:01 PM PDT 24
Peak memory 218476 kb
Host smart-0e672f3a-8ae4-4060-9954-4591dfd10218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532658381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3532658381
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1313298281
Short name T845
Test name
Test status
Simulation time 147671701 ps
CPU time 1.78 seconds
Started Aug 12 04:56:41 PM PDT 24
Finished Aug 12 04:56:43 PM PDT 24
Peak memory 217876 kb
Host smart-96988a12-c9df-4329-bfcb-203c9926c398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313298281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1313298281
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1947674117
Short name T662
Test name
Test status
Simulation time 406517957 ps
CPU time 24.29 seconds
Started Aug 12 04:56:39 PM PDT 24
Finished Aug 12 04:57:03 PM PDT 24
Peak memory 251000 kb
Host smart-a753e600-70aa-4517-bc4c-f4ceaadef511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947674117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1947674117
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3379546752
Short name T217
Test name
Test status
Simulation time 79831892 ps
CPU time 4.28 seconds
Started Aug 12 04:56:38 PM PDT 24
Finished Aug 12 04:56:43 PM PDT 24
Peak memory 226512 kb
Host smart-bb6c2935-ca5c-4ca0-a851-06fc687ff5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379546752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3379546752
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.115695749
Short name T677
Test name
Test status
Simulation time 6221470553 ps
CPU time 89.97 seconds
Started Aug 12 04:56:52 PM PDT 24
Finished Aug 12 04:58:22 PM PDT 24
Peak memory 250896 kb
Host smart-cbd3a403-3d5a-4ce9-beef-c674488b764e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115695749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.115695749
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3018692437
Short name T324
Test name
Test status
Simulation time 14590738 ps
CPU time 1 seconds
Started Aug 12 04:56:38 PM PDT 24
Finished Aug 12 04:56:40 PM PDT 24
Peak memory 218040 kb
Host smart-2d7d91e4-7c70-437e-8c79-aba183e718ca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018692437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3018692437
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3594560769
Short name T380
Test name
Test status
Simulation time 31500344 ps
CPU time 0.93 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:01 PM PDT 24
Peak memory 208952 kb
Host smart-61a607ed-30c9-46ab-b45a-fe722ccc20aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594560769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3594560769
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3648090959
Short name T214
Test name
Test status
Simulation time 14008089 ps
CPU time 0.85 seconds
Started Aug 12 04:56:52 PM PDT 24
Finished Aug 12 04:56:53 PM PDT 24
Peak memory 208696 kb
Host smart-23c73012-dd06-42aa-9f28-c8f8e580f07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648090959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3648090959
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1512993665
Short name T830
Test name
Test status
Simulation time 1283756787 ps
CPU time 12.71 seconds
Started Aug 12 04:56:46 PM PDT 24
Finished Aug 12 04:56:59 PM PDT 24
Peak memory 218348 kb
Host smart-c027e026-fd82-4a56-8b5d-1a5274e28cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512993665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1512993665
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1002601573
Short name T5
Test name
Test status
Simulation time 450709700 ps
CPU time 6.47 seconds
Started Aug 12 04:56:54 PM PDT 24
Finished Aug 12 04:57:01 PM PDT 24
Peak memory 217232 kb
Host smart-7248df0c-2d8c-4953-b6d4-3116d2cf590a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002601573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1002601573
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3358559534
Short name T793
Test name
Test status
Simulation time 1869980713 ps
CPU time 34.02 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:34 PM PDT 24
Peak memory 218324 kb
Host smart-9a71dc78-169f-400e-a64e-baa133689f2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358559534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3358559534
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2187300681
Short name T61
Test name
Test status
Simulation time 2351526519 ps
CPU time 11.65 seconds
Started Aug 12 04:56:52 PM PDT 24
Finished Aug 12 04:57:03 PM PDT 24
Peak memory 217876 kb
Host smart-18bca427-24f1-46a0-857b-bbf6f4c6e6b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187300681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
187300681
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3454915311
Short name T466
Test name
Test status
Simulation time 856009032 ps
CPU time 7.01 seconds
Started Aug 12 04:56:53 PM PDT 24
Finished Aug 12 04:57:00 PM PDT 24
Peak memory 222984 kb
Host smart-a5d8e289-7ca9-4a4b-8fa6-ffc1a348d0e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454915311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3454915311
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1833095988
Short name T256
Test name
Test status
Simulation time 6916885591 ps
CPU time 36.17 seconds
Started Aug 12 04:56:54 PM PDT 24
Finished Aug 12 04:57:30 PM PDT 24
Peak memory 217812 kb
Host smart-f6c77df6-a6ea-457f-9c5f-cf773e73097d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833095988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1833095988
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2008747242
Short name T615
Test name
Test status
Simulation time 546905775 ps
CPU time 5.58 seconds
Started Aug 12 04:56:54 PM PDT 24
Finished Aug 12 04:56:59 PM PDT 24
Peak memory 217732 kb
Host smart-9c073586-e9d5-4325-9585-6527237fc0b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008747242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2008747242
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1910501715
Short name T391
Test name
Test status
Simulation time 2561624223 ps
CPU time 54.8 seconds
Started Aug 12 04:56:53 PM PDT 24
Finished Aug 12 04:57:48 PM PDT 24
Peak memory 283796 kb
Host smart-247cfece-55ed-44a0-abd4-7194fe98e9d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910501715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1910501715
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.855635072
Short name T747
Test name
Test status
Simulation time 1078219213 ps
CPU time 19.61 seconds
Started Aug 12 04:56:53 PM PDT 24
Finished Aug 12 04:57:12 PM PDT 24
Peak memory 250852 kb
Host smart-145b02b2-185c-47f5-b5f6-d155646d9dd6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855635072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.855635072
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1113990047
Short name T482
Test name
Test status
Simulation time 317060516 ps
CPU time 1.66 seconds
Started Aug 12 04:56:48 PM PDT 24
Finished Aug 12 04:56:50 PM PDT 24
Peak memory 218384 kb
Host smart-667b99a8-7a96-4bac-8134-3fd7b30c8126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113990047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1113990047
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1402791397
Short name T349
Test name
Test status
Simulation time 360066044 ps
CPU time 13.69 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:14 PM PDT 24
Peak memory 214336 kb
Host smart-de5d18f9-a5e1-417c-945a-8a696f09c7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402791397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1402791397
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1805689559
Short name T548
Test name
Test status
Simulation time 271856770 ps
CPU time 10.05 seconds
Started Aug 12 04:56:52 PM PDT 24
Finished Aug 12 04:57:02 PM PDT 24
Peak memory 226180 kb
Host smart-786e21d4-acd2-4371-8c9a-a30c166cd69b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805689559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1805689559
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2401464663
Short name T582
Test name
Test status
Simulation time 264833496 ps
CPU time 10.25 seconds
Started Aug 12 04:56:55 PM PDT 24
Finished Aug 12 04:57:05 PM PDT 24
Peak memory 226096 kb
Host smart-0ff58211-3607-4a35-a158-6fee1c050be3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401464663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2401464663
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2325702525
Short name T594
Test name
Test status
Simulation time 1705505899 ps
CPU time 9.62 seconds
Started Aug 12 04:56:53 PM PDT 24
Finished Aug 12 04:57:03 PM PDT 24
Peak memory 218416 kb
Host smart-572226ba-65b3-45ec-a683-dc1fe2407ea6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325702525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
325702525
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3430725398
Short name T834
Test name
Test status
Simulation time 2182367813 ps
CPU time 7.52 seconds
Started Aug 12 04:56:56 PM PDT 24
Finished Aug 12 04:57:03 PM PDT 24
Peak memory 225756 kb
Host smart-35d29e4e-4686-4c62-9ca7-f97863d9d5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430725398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3430725398
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3048770950
Short name T373
Test name
Test status
Simulation time 170454673 ps
CPU time 3.06 seconds
Started Aug 12 04:56:45 PM PDT 24
Finished Aug 12 04:56:48 PM PDT 24
Peak memory 214816 kb
Host smart-efd6d271-e35a-4dc2-842b-043d83facab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048770950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3048770950
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1411945594
Short name T642
Test name
Test status
Simulation time 275795807 ps
CPU time 23.64 seconds
Started Aug 12 04:56:47 PM PDT 24
Finished Aug 12 04:57:10 PM PDT 24
Peak memory 251264 kb
Host smart-cd87cbc4-1cd2-467f-9a0d-6ff8e79fb976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411945594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1411945594
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.4233520474
Short name T238
Test name
Test status
Simulation time 80549794 ps
CPU time 7.37 seconds
Started Aug 12 04:56:48 PM PDT 24
Finished Aug 12 04:56:56 PM PDT 24
Peak memory 251040 kb
Host smart-3701469f-cc7f-459b-baec-03a0c175e5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233520474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.4233520474
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1517290982
Short name T470
Test name
Test status
Simulation time 362011043 ps
CPU time 29.65 seconds
Started Aug 12 04:57:00 PM PDT 24
Finished Aug 12 04:57:30 PM PDT 24
Peak memory 251052 kb
Host smart-fd4e8e99-0d2e-431b-b8c1-ba49412220be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517290982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1517290982
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1126551645
Short name T846
Test name
Test status
Simulation time 2659065575 ps
CPU time 119.67 seconds
Started Aug 12 04:56:53 PM PDT 24
Finished Aug 12 04:58:53 PM PDT 24
Peak memory 275856 kb
Host smart-af6645c8-6fb4-4a91-98e7-3bd44f4a9666
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1126551645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.1126551645
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.221635563
Short name T26
Test name
Test status
Simulation time 12581608 ps
CPU time 0.81 seconds
Started Aug 12 04:56:45 PM PDT 24
Finished Aug 12 04:56:46 PM PDT 24
Peak memory 209008 kb
Host smart-60e532cc-ccce-438d-9257-89b63d32f479
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221635563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.221635563
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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