Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40109 |
1 |
|
|
T1 |
346 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1275 |
1 |
|
|
T1 |
25 |
|
T11 |
8 |
|
T5 |
17 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40663 |
1 |
|
|
T1 |
371 |
|
T2 |
84 |
|
T3 |
75 |
auto[1] |
721 |
1 |
|
|
T3 |
17 |
|
T65 |
11 |
|
T46 |
11 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40056 |
1 |
|
|
T1 |
360 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1328 |
1 |
|
|
T1 |
11 |
|
T4 |
4 |
|
T15 |
11 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40005 |
1 |
|
|
T1 |
363 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1379 |
1 |
|
|
T1 |
8 |
|
T4 |
9 |
|
T15 |
8 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40036 |
1 |
|
|
T1 |
361 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1348 |
1 |
|
|
T1 |
10 |
|
T4 |
7 |
|
T15 |
2 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
38135 |
1 |
|
|
T1 |
347 |
|
T2 |
84 |
|
T3 |
92 |
no_err_inj |
3249 |
1 |
|
|
T1 |
24 |
|
T12 |
8 |
|
T4 |
39 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40249 |
1 |
|
|
T1 |
346 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1135 |
1 |
|
|
T1 |
25 |
|
T11 |
12 |
|
T5 |
20 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40617 |
1 |
|
|
T1 |
371 |
|
T2 |
84 |
|
T3 |
73 |
auto[1] |
767 |
1 |
|
|
T3 |
19 |
|
T65 |
13 |
|
T46 |
13 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
31992 |
1 |
|
|
T1 |
355 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
9392 |
1 |
|
|
T1 |
16 |
|
T4 |
91 |
|
T5 |
39 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40080 |
1 |
|
|
T1 |
359 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1304 |
1 |
|
|
T1 |
12 |
|
T4 |
4 |
|
T15 |
8 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40055 |
1 |
|
|
T1 |
361 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1329 |
1 |
|
|
T1 |
10 |
|
T4 |
7 |
|
T15 |
9 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40078 |
1 |
|
|
T1 |
353 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1306 |
1 |
|
|
T1 |
18 |
|
T4 |
10 |
|
T15 |
7 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40198 |
1 |
|
|
T1 |
335 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1186 |
1 |
|
|
T1 |
36 |
|
T11 |
8 |
|
T5 |
23 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39653 |
1 |
|
|
T1 |
369 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1731 |
1 |
|
|
T1 |
2 |
|
T63 |
14 |
|
T21 |
11 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40631 |
1 |
|
|
T1 |
371 |
|
T2 |
84 |
|
T3 |
69 |
auto[1] |
753 |
1 |
|
|
T3 |
23 |
|
T65 |
14 |
|
T46 |
13 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40555 |
1 |
|
|
T1 |
371 |
|
T2 |
84 |
|
T3 |
73 |
auto[1] |
829 |
1 |
|
|
T3 |
19 |
|
T65 |
11 |
|
T46 |
12 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40627 |
1 |
|
|
T1 |
371 |
|
T2 |
84 |
|
T3 |
78 |
auto[1] |
757 |
1 |
|
|
T3 |
14 |
|
T65 |
16 |
|
T46 |
9 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39534 |
1 |
|
|
T1 |
347 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1850 |
1 |
|
|
T1 |
24 |
|
T4 |
28 |
|
T5 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37770 |
1 |
|
|
T1 |
371 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
3614 |
1 |
|
|
T30 |
63 |
|
T52 |
53 |
|
T55 |
66 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40051 |
1 |
|
|
T1 |
364 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1333 |
1 |
|
|
T1 |
7 |
|
T4 |
9 |
|
T15 |
5 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40008 |
1 |
|
|
T1 |
352 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1376 |
1 |
|
|
T1 |
19 |
|
T4 |
14 |
|
T15 |
5 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40077 |
1 |
|
|
T1 |
362 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1307 |
1 |
|
|
T1 |
9 |
|
T4 |
10 |
|
T15 |
3 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40208 |
1 |
|
|
T1 |
339 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1176 |
1 |
|
|
T1 |
32 |
|
T11 |
14 |
|
T5 |
23 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36544 |
1 |
|
|
T1 |
337 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
4840 |
1 |
|
|
T1 |
34 |
|
T11 |
16 |
|
T5 |
32 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37653 |
1 |
|
|
T1 |
371 |
|
T3 |
92 |
|
T11 |
96 |
auto[1] |
3731 |
1 |
|
|
T2 |
84 |
|
T14 |
59 |
|
T64 |
75 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41384 |
1 |
|
|
T1 |
371 |
|
T2 |
84 |
|
T3 |
92 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40224 |
1 |
|
|
T1 |
339 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1160 |
1 |
|
|
T1 |
32 |
|
T11 |
7 |
|
T5 |
29 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40144 |
1 |
|
|
T1 |
337 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1240 |
1 |
|
|
T1 |
34 |
|
T11 |
17 |
|
T5 |
19 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40174 |
1 |
|
|
T1 |
348 |
|
T2 |
84 |
|
T3 |
92 |
auto[1] |
1210 |
1 |
|
|
T1 |
23 |
|
T11 |
14 |
|
T5 |
18 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
37231 |
1 |
|
|
T1 |
337 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
no_err_inj |
2303 |
1 |
|
|
T1 |
10 |
|
T12 |
8 |
|
T4 |
22 |
auto[1] |
err_inj |
904 |
1 |
|
|
T1 |
10 |
|
T4 |
11 |
|
T5 |
4 |
auto[1] |
no_err_inj |
946 |
1 |
|
|
T1 |
14 |
|
T4 |
17 |
|
T5 |
8 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38254 |
1 |
|
|
T1 |
328 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
1280 |
1 |
|
|
T1 |
19 |
|
T4 |
13 |
|
T15 |
5 |
auto[1] |
auto[0] |
1754 |
1 |
|
|
T1 |
24 |
|
T4 |
27 |
|
T5 |
11 |
auto[1] |
auto[1] |
96 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T32 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38296 |
1 |
|
|
T1 |
337 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
1238 |
1 |
|
|
T1 |
10 |
|
T4 |
6 |
|
T15 |
9 |
auto[1] |
auto[0] |
1759 |
1 |
|
|
T1 |
24 |
|
T4 |
27 |
|
T5 |
12 |
auto[1] |
auto[1] |
91 |
1 |
|
|
T4 |
1 |
|
T156 |
1 |
|
T224 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38319 |
1 |
|
|
T1 |
339 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
1215 |
1 |
|
|
T1 |
8 |
|
T4 |
10 |
|
T15 |
3 |
auto[1] |
auto[0] |
1758 |
1 |
|
|
T1 |
23 |
|
T4 |
28 |
|
T5 |
12 |
auto[1] |
auto[1] |
92 |
1 |
|
|
T1 |
1 |
|
T156 |
1 |
|
T159 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38282 |
1 |
|
|
T1 |
340 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
1252 |
1 |
|
|
T1 |
7 |
|
T4 |
5 |
|
T15 |
8 |
auto[1] |
auto[0] |
1723 |
1 |
|
|
T1 |
23 |
|
T4 |
24 |
|
T5 |
11 |
auto[1] |
auto[1] |
127 |
1 |
|
|
T1 |
1 |
|
T4 |
4 |
|
T5 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38288 |
1 |
|
|
T1 |
341 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
1246 |
1 |
|
|
T1 |
6 |
|
T4 |
6 |
|
T15 |
2 |
auto[1] |
auto[0] |
1748 |
1 |
|
|
T1 |
20 |
|
T4 |
27 |
|
T5 |
12 |
auto[1] |
auto[1] |
102 |
1 |
|
|
T1 |
4 |
|
T4 |
1 |
|
T159 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38317 |
1 |
|
|
T1 |
337 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
1217 |
1 |
|
|
T1 |
10 |
|
T4 |
4 |
|
T15 |
11 |
auto[1] |
auto[0] |
1739 |
1 |
|
|
T1 |
23 |
|
T4 |
28 |
|
T5 |
11 |
auto[1] |
auto[1] |
111 |
1 |
|
|
T1 |
1 |
|
T5 |
1 |
|
T32 |
3 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31164 |
1 |
|
|
T1 |
330 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
828 |
1 |
|
|
T1 |
25 |
|
T11 |
8 |
|
T5 |
17 |
auto[1] |
auto[0] |
8945 |
1 |
|
|
T1 |
16 |
|
T4 |
91 |
|
T5 |
39 |
auto[1] |
auto[1] |
447 |
1 |
|
|
T18 |
13 |
|
T91 |
7 |
|
T92 |
8 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31233 |
1 |
|
|
T1 |
330 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
759 |
1 |
|
|
T1 |
25 |
|
T11 |
12 |
|
T5 |
20 |
auto[1] |
auto[0] |
9016 |
1 |
|
|
T1 |
16 |
|
T4 |
91 |
|
T5 |
39 |
auto[1] |
auto[1] |
376 |
1 |
|
|
T18 |
12 |
|
T91 |
8 |
|
T49 |
1 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30939 |
1 |
|
|
T1 |
355 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
1053 |
1 |
|
|
T63 |
14 |
|
T225 |
17 |
|
T91 |
9 |
auto[1] |
auto[0] |
8714 |
1 |
|
|
T1 |
14 |
|
T4 |
91 |
|
T5 |
39 |
auto[1] |
auto[1] |
678 |
1 |
|
|
T1 |
2 |
|
T21 |
11 |
|
T226 |
11 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31167 |
1 |
|
|
T1 |
319 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
825 |
1 |
|
|
T1 |
36 |
|
T11 |
8 |
|
T5 |
23 |
auto[1] |
auto[0] |
9031 |
1 |
|
|
T1 |
16 |
|
T4 |
91 |
|
T5 |
39 |
auto[1] |
auto[1] |
361 |
1 |
|
|
T18 |
10 |
|
T91 |
8 |
|
T92 |
4 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
27562 |
1 |
|
|
T1 |
321 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
4430 |
1 |
|
|
T1 |
34 |
|
T11 |
16 |
|
T5 |
32 |
auto[1] |
auto[0] |
8982 |
1 |
|
|
T1 |
16 |
|
T4 |
91 |
|
T5 |
39 |
auto[1] |
auto[1] |
410 |
1 |
|
|
T18 |
11 |
|
T91 |
11 |
|
T92 |
6 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31101 |
1 |
|
|
T1 |
336 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
891 |
1 |
|
|
T1 |
19 |
|
T15 |
5 |
|
T5 |
1 |
auto[1] |
auto[0] |
8907 |
1 |
|
|
T1 |
16 |
|
T4 |
77 |
|
T5 |
39 |
auto[1] |
auto[1] |
485 |
1 |
|
|
T4 |
14 |
|
T19 |
12 |
|
T20 |
6 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31137 |
1 |
|
|
T1 |
348 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
855 |
1 |
|
|
T1 |
7 |
|
T15 |
5 |
|
T32 |
2 |
auto[1] |
auto[0] |
8914 |
1 |
|
|
T1 |
16 |
|
T4 |
82 |
|
T5 |
39 |
auto[1] |
auto[1] |
478 |
1 |
|
|
T4 |
9 |
|
T19 |
7 |
|
T20 |
11 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31118 |
1 |
|
|
T1 |
345 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
874 |
1 |
|
|
T1 |
10 |
|
T15 |
9 |
|
T89 |
6 |
auto[1] |
auto[0] |
8937 |
1 |
|
|
T1 |
16 |
|
T4 |
84 |
|
T5 |
39 |
auto[1] |
auto[1] |
455 |
1 |
|
|
T4 |
7 |
|
T19 |
10 |
|
T20 |
2 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31123 |
1 |
|
|
T1 |
344 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
869 |
1 |
|
|
T1 |
11 |
|
T15 |
8 |
|
T32 |
1 |
auto[1] |
auto[0] |
8957 |
1 |
|
|
T1 |
15 |
|
T4 |
87 |
|
T5 |
39 |
auto[1] |
auto[1] |
435 |
1 |
|
|
T1 |
1 |
|
T4 |
4 |
|
T19 |
12 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31115 |
1 |
|
|
T1 |
347 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
877 |
1 |
|
|
T1 |
8 |
|
T15 |
8 |
|
T5 |
1 |
auto[1] |
auto[0] |
8890 |
1 |
|
|
T1 |
16 |
|
T4 |
82 |
|
T5 |
39 |
auto[1] |
auto[1] |
502 |
1 |
|
|
T4 |
9 |
|
T19 |
11 |
|
T20 |
11 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31128 |
1 |
|
|
T1 |
344 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
864 |
1 |
|
|
T1 |
11 |
|
T15 |
11 |
|
T5 |
1 |
auto[1] |
auto[0] |
8928 |
1 |
|
|
T1 |
16 |
|
T4 |
87 |
|
T5 |
39 |
auto[1] |
auto[1] |
464 |
1 |
|
|
T4 |
4 |
|
T19 |
8 |
|
T20 |
4 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31158 |
1 |
|
|
T1 |
332 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
834 |
1 |
|
|
T1 |
23 |
|
T11 |
14 |
|
T5 |
18 |
auto[1] |
auto[0] |
9016 |
1 |
|
|
T1 |
16 |
|
T4 |
91 |
|
T5 |
39 |
auto[1] |
auto[1] |
376 |
1 |
|
|
T18 |
6 |
|
T91 |
11 |
|
T92 |
8 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31153 |
1 |
|
|
T1 |
321 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
839 |
1 |
|
|
T1 |
34 |
|
T11 |
17 |
|
T5 |
19 |
auto[1] |
auto[0] |
8991 |
1 |
|
|
T1 |
16 |
|
T4 |
91 |
|
T5 |
39 |
auto[1] |
auto[1] |
401 |
1 |
|
|
T18 |
8 |
|
T91 |
11 |
|
T92 |
6 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30840 |
1 |
|
|
T1 |
345 |
|
T2 |
84 |
|
T3 |
92 |
auto[0] |
auto[1] |
1152 |
1 |
|
|
T1 |
10 |
|
T5 |
12 |
|
T32 |
13 |
auto[1] |
auto[0] |
8694 |
1 |
|
|
T1 |
2 |
|
T4 |
63 |
|
T5 |
39 |
auto[1] |
auto[1] |
698 |
1 |
|
|
T1 |
14 |
|
T4 |
28 |
|
T156 |
13 |