Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60551854

1

T1

758204

T2

49124

T3

30570

auto[1]

1127437

1

T1

4156

T3

990

T11

594

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60529380

1

T1

756223

T2

49124

T3

28986

auto[1]

1149911

1

T1

6137

T3

2574

T11

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5423112	1			T1	39752		T2	7515		T3	8797
auto[IdleSt]	15733436	1			T1	51626		T2	2844		T3	2609
auto[ClkMuxSt]	28237	1			T1	267		T2	84		T3	73
auto[CntIncrSt]	28022	1			T1	267		T2	84		T3	73
auto[CntProgSt]	1378150	1			T1	38049		T2	168		T3	1869
auto[TransCheckSt]	21908	1			T1	206		T2	84		T3	56
auto[TokenHashSt]	17469153	1			T1	510847		T2	25227		T3	1237
auto[FlashRmaSt]	28167	1			T1	148		T2	87		T3	124
auto[TokenCheck0St]	9917	1			T1	85		T2	27		T3	49
auto[TokenCheck1St]	7189	1			T1	61		T2	8		T3	30
auto[TransProgSt]	376028	1			T1	12302		T3	1019		T11	288
auto[PostTransSt]	8547182	1			T1	70027		T2	12996		T3	9460
auto[ScrapSt]	119580	1			T12	29		T4	16		T5	1528
auto[EscalateSt]	4855754	1			T1	21053		T3	4711		T11	1080
auto[InvalidSt]	7652072	1			T1	17660		T3	1453		T4	88388

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1384	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7652072	1			T1	17660		T3	1453		T4	88388
EscalateSt	4855754	1			T1	21053		T3	4711		T11	1080
ScrapSt	119580	1			T12	29		T4	16		T5	1528
PostTransSt	8547182	1			T1	70027		T2	12996		T3	9460
TransProgSt	376028	1			T1	12302		T3	1019		T11	288
TokenCheck1St	7189	1			T1	61		T2	8		T3	30
TokenCheck0St	9917	1			T1	85		T2	27		T3	49
FlashRmaSt	28167	1			T1	148		T2	87		T3	124
TokenHashSt	17469153	1			T1	510847		T2	25227		T3	1237
TransCheckSt	21908	1			T1	206		T2	84		T3	56
CntProgSt	1378150	1			T1	38049		T2	168		T3	1869
CntIncrSt	28022	1			T1	267		T2	84		T3	73
ClkMuxSt	28237	1			T1	267		T2	84		T3	73
IdleSt	15733436	1			T1	51626		T2	2844		T3	2609
ResetSt	5423112	1			T1	39752		T2	7515		T3	8797
arcs[ResetSt=>IdleSt]	41950	1			T1	361		T2	85		T3	93
arcs[IdleSt=>ScrapSt]	227	1			T12	1		T4	1		T5	5
arcs[IdleSt=>ClkMuxSt]	28061	1			T1	267		T2	84		T3	73
arcs[ClkMuxSt=>CntIncrSt]	28022	1			T1	267		T2	84		T3	73
arcs[CntIncrSt=>PostTransSt]	1244	1			T1	34		T11	17		T5	19
arcs[CntIncrSt=>CntProgSt]	26707	1			T1	233		T2	84		T3	73
arcs[CntProgSt=>PostTransSt]	3717	1			T1	27		T3	17		T11	8
arcs[CntProgSt=>TransCheckSt]	21908	1			T1	206		T2	84		T3	56
arcs[TransCheckSt=>PostTransSt]	3086	1			T1	23		T2	44		T11	14
arcs[TransCheckSt=>TokenHashSt]	18734	1			T1	183		T2	40		T3	56
arcs[TokenHashSt=>PostTransSt]	8076	1			T1	98		T2	13		T3	7
arcs[TokenHashSt=>FlashRmaSt]	9957	1			T1	85		T2	27		T3	49
arcs[FlashRmaSt=>TokenCheck0St]	9917	1			T1	85		T2	27		T3	49
arcs[TokenCheck0St=>PostTransSt]	2675	1			T1	24		T2	19		T3	19
arcs[TokenCheck0St=>TokenCheck1St]	7189	1			T1	61		T2	8		T3	30
arcs[TokenCheck1St=>PostTransSt]	608	1			T1	1		T2	8		T14	7
arcs[TransProgSt=>PostTransSt]	5734	1			T1	60		T3	30		T11	8
arcs[IdleSt=>EscalateSt]	151	1			T52	1		T53	6		T57	8
arcs[ClkMuxSt=>EscalateSt]	39	1			T52	1		T53	2		T54	3
arcs[CntIncrSt=>EscalateSt]	71	1			T30	1		T52	2		T55	1
arcs[CntProgSt=>EscalateSt]	1082	1			T30	29		T52	18		T55	6
arcs[TransCheckSt=>EscalateSt]	88	1			T55	5		T58	2		T56	1
arcs[TokenHashSt=>EscalateSt]	701	1			T30	5		T52	5		T55	33
arcs[FlashRmaSt=>EscalateSt]	40	1			T56	1		T53	2		T54	1
arcs[TokenCheck0St=>EscalateSt]	53	1			T30	1		T56	2		T53	1
arcs[TokenCheck1St=>EscalateSt]	36	1			T58	2		T53	2		T57	1
arcs[TransProgSt=>EscalateSt]	811	1			T30	21		T52	20		T55	5
arcs[PostTransSt=>EscalateSt]	3975	1			T1	27		T3	17		T11	8
arcs[InvalidSt=>EscalateSt]	10255	1			T1	77		T3	19		T4	54

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5422949	1			T1	39752		T2	7515		T3	8797
auto[0]	auto[IdleSt]	15733330	1			T1	51626		T2	2844		T3	2609
auto[0]	auto[ClkMuxSt]	28210	1			T1	267		T2	84		T3	73
auto[0]	auto[CntIncrSt]	27974	1			T1	267		T2	84		T3	73
auto[0]	auto[CntProgSt]	1377423	1			T1	38049		T2	168		T3	1869
auto[0]	auto[TransCheckSt]	21845	1			T1	206		T2	84		T3	56
auto[0]	auto[TokenHashSt]	17468683	1			T1	510847		T2	25227		T3	1237
auto[0]	auto[FlashRmaSt]	28138	1			T1	148		T2	87		T3	124
auto[0]	auto[TokenCheck0St]	9878	1			T1	85		T2	27		T3	49
auto[0]	auto[TokenCheck1St]	7167	1			T1	61		T2	8		T3	30
auto[0]	auto[TransProgSt]	375524	1			T1	12302		T3	1019		T11	288
auto[0]	auto[PostTransSt]	8545169	1			T1	70015		T2	12996		T3	9455
auto[0]	auto[ScrapSt]	119541	1			T12	29		T4	16		T5	1528
auto[0]	auto[EscalateSt]	3737633	1			T1	16939		T3	3731		T11	492
auto[0]	auto[InvalidSt]	7647006	1			T1	17630		T3	1448		T4	88359
auto[1]	auto[ResetSt]	163	1			T55	4		T58	3		T56	2
auto[1]	auto[IdleSt]	106	1			T52	1		T53	3		T57	7
auto[1]	auto[ClkMuxSt]	27	1			T52	1		T53	2		T54	2
auto[1]	auto[CntIncrSt]	48	1			T52	1		T55	1		T58	1
auto[1]	auto[CntProgSt]	727	1			T30	22		T52	12		T55	5
auto[1]	auto[TransCheckSt]	63	1			T55	3		T58	1		T56	1
auto[1]	auto[TokenHashSt]	470	1			T30	3		T52	2		T55	21
auto[1]	auto[FlashRmaSt]	29	1			T53	2		T54	1		T223	1
auto[1]	auto[TokenCheck0St]	39	1			T56	2		T57	1		T223	1
auto[1]	auto[TokenCheck1St]	22	1			T58	2		T53	1		T223	1
auto[1]	auto[TransProgSt]	504	1			T30	14		T52	13		T55	3
auto[1]	auto[PostTransSt]	2013	1			T1	12		T3	5		T11	6
auto[1]	auto[ScrapSt]	39	1			T30	3		T52	3		T55	2
auto[1]	auto[EscalateSt]	1118121	1			T1	4114		T3	980		T11	588
auto[1]	auto[InvalidSt]	5066	1			T1	30		T3	5		T4	29

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5422938	1			T1	39752		T2	7515		T3	8797
auto[0]	auto[IdleSt]	15733341	1			T1	51626		T2	2844		T3	2609
auto[0]	auto[ClkMuxSt]	28209	1			T1	267		T2	84		T3	73
auto[0]	auto[CntIncrSt]	27980	1			T1	267		T2	84		T3	73
auto[0]	auto[CntProgSt]	1377425	1			T1	38049		T2	168		T3	1869
auto[0]	auto[TransCheckSt]	21847	1			T1	206		T2	84		T3	56
auto[0]	auto[TokenHashSt]	17468678	1			T1	510847		T2	25227		T3	1237
auto[0]	auto[FlashRmaSt]	28145	1			T1	148		T2	87		T3	124
auto[0]	auto[TokenCheck0St]	9886	1			T1	85		T2	27		T3	49
auto[0]	auto[TokenCheck1St]	7159	1			T1	61		T2	8		T3	30
auto[0]	auto[TransProgSt]	375474	1			T1	12302		T3	1019		T11	288
auto[0]	auto[PostTransSt]	8545147	1			T1	70012		T2	12996		T3	9448
auto[0]	auto[ScrapSt]	119541	1			T12	29		T4	16		T5	1528
auto[0]	auto[EscalateSt]	3715343	1			T1	14978		T3	2163		T11	884
auto[0]	auto[InvalidSt]	7646883	1			T1	17613		T3	1439		T4	88363
auto[1]	auto[ResetSt]	174	1			T52	2		T55	1		T58	5
auto[1]	auto[IdleSt]	95	1			T52	1		T53	6		T57	4
auto[1]	auto[ClkMuxSt]	28	1			T52	1		T53	2		T54	2
auto[1]	auto[CntIncrSt]	42	1			T30	1		T52	2		T53	2
auto[1]	auto[CntProgSt]	725	1			T30	17		T52	13		T55	4
auto[1]	auto[TransCheckSt]	61	1			T55	4		T58	1		T53	3
auto[1]	auto[TokenHashSt]	475	1			T30	3		T52	4		T55	22
auto[1]	auto[FlashRmaSt]	22	1			T56	1		T53	1		T54	1
auto[1]	auto[TokenCheck0St]	31	1			T30	1		T56	1		T53	1
auto[1]	auto[TokenCheck1St]	30	1			T58	2		T53	2		T57	1
auto[1]	auto[TransProgSt]	554	1			T30	13		T52	12		T55	5
auto[1]	auto[PostTransSt]	2035	1			T1	15		T3	12		T11	2
auto[1]	auto[ScrapSt]	39	1			T30	2		T52	2		T55	2
auto[1]	auto[EscalateSt]	1140411	1			T1	6075		T3	2548		T11	196
auto[1]	auto[InvalidSt]	5189	1			T1	47		T3	14		T4	25