Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59779787

1

T1

1588

T2

41435

T3

36696

auto[1]

1163859

1

T2

1485

T4

198

T5

396

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59786395

1

T1

1588

T2

41534

T3

36696

auto[1]

1157251

1

T2

1386

T4

297

T13

891

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5408948	1			T1	111		T2	5694		T3	72
auto[IdleSt]	16828786	1			T1	1477		T2	4779		T3	36624
auto[ClkMuxSt]	29004	1			T2	49		T4	8		T11	1
auto[CntIncrSt]	28762	1			T2	49		T4	8		T11	1
auto[CntProgSt]	1228840	1			T2	949		T4	16		T11	186
auto[TransCheckSt]	22591	1			T2	35		T4	8		T11	1
auto[TokenHashSt]	16343132	1			T2	17513		T4	3214		T11	58
auto[FlashRmaSt]	27641	1			T2	187		T4	8		T11	1
auto[TokenCheck0St]	10023	1			T2	29		T4	8		T11	1
auto[TokenCheck1St]	7220	1			T2	18		T4	8		T11	1
auto[TransProgSt]	259981	1			T2	403		T4	16		T11	81
auto[PostTransSt]	8690568	1			T2	6950		T4	1336		T11	562
auto[ScrapSt]	120776	1			T14	1193		T7	319		T28	831
auto[EscalateSt]	4748844	1			T2	3953		T4	879		T5	602
auto[InvalidSt]	7187063	1			T2	2312		T4	377		T16	2335

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1467	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7187063	1			T2	2312		T4	377		T16	2335
EscalateSt	4748844	1			T2	3953		T4	879		T5	602
ScrapSt	120776	1			T14	1193		T7	319		T28	831
PostTransSt	8690568	1			T2	6950		T4	1336		T11	562
TransProgSt	259981	1			T2	403		T4	16		T11	81
TokenCheck1St	7220	1			T2	18		T4	8		T11	1
TokenCheck0St	10023	1			T2	29		T4	8		T11	1
FlashRmaSt	27641	1			T2	187		T4	8		T11	1
TokenHashSt	16343132	1			T2	17513		T4	3214		T11	58
TransCheckSt	22591	1			T2	35		T4	8		T11	1
CntProgSt	1228840	1			T2	949		T4	16		T11	186
CntIncrSt	28762	1			T2	49		T4	8		T11	1
ClkMuxSt	29004	1			T2	49		T4	8		T11	1
IdleSt	16828786	1			T1	1477		T2	4779		T3	36624
ResetSt	5408948	1			T1	111		T2	5694		T3	72
arcs[ResetSt=>IdleSt]	42838	1			T1	1		T2	65		T3	1
arcs[IdleSt=>ScrapSt]	240	1			T14	1		T7	1		T28	1
arcs[IdleSt=>ClkMuxSt]	28811	1			T2	49		T4	8		T11	1
arcs[ClkMuxSt=>CntIncrSt]	28762	1			T2	49		T4	8		T11	1
arcs[CntIncrSt=>PostTransSt]	1282	1			T18	18		T29	7		T34	13
arcs[CntIncrSt=>CntProgSt]	27420	1			T2	49		T4	8		T11	1
arcs[CntProgSt=>PostTransSt]	3700	1			T2	14		T5	4		T13	20
arcs[CntProgSt=>TransCheckSt]	22591	1			T2	35		T4	8		T11	1
arcs[TransCheckSt=>PostTransSt]	3138	1			T18	10		T29	8		T34	5
arcs[TransCheckSt=>TokenHashSt]	19362	1			T2	35		T4	8		T11	1
arcs[TokenHashSt=>PostTransSt]	8561	1			T2	6		T12	83		T15	97
arcs[TokenHashSt=>FlashRmaSt]	10069	1			T2	29		T4	8		T11	1
arcs[FlashRmaSt=>TokenCheck0St]	10023	1			T2	29		T4	8		T11	1
arcs[TokenCheck0St=>PostTransSt]	2742	1			T2	11		T16	14		T17	14
arcs[TokenCheck0St=>TokenCheck1St]	7220	1			T2	18		T4	8		T11	1
arcs[TokenCheck1St=>PostTransSt]	575	1			T16	1		T17	1		T18	1
arcs[TransProgSt=>PostTransSt]	5796	1			T2	18		T4	8		T11	1
arcs[IdleSt=>EscalateSt]	183	1			T45	4		T49	3		T46	1
arcs[ClkMuxSt=>EscalateSt]	49	1			T45	2		T46	2		T47	1
arcs[CntIncrSt=>EscalateSt]	60	1			T48	1		T45	2		T47	2
arcs[CntProgSt=>EscalateSt]	1129	1			T48	32		T45	8		T49	12
arcs[TransCheckSt=>EscalateSt]	91	1			T45	1		T49	1		T46	1
arcs[TokenHashSt=>EscalateSt]	732	1			T48	4		T45	23		T36	2
arcs[FlashRmaSt=>EscalateSt]	46	1			T45	1		T49	1		T46	1
arcs[TokenCheck0St=>EscalateSt]	61	1			T48	2		T49	2		T47	2
arcs[TokenCheck1St=>EscalateSt]	35	1			T48	1		T45	1		T47	1
arcs[TransProgSt=>EscalateSt]	814	1			T48	29		T45	11		T49	12
arcs[PostTransSt=>EscalateSt]	3986	1			T2	14		T5	4		T13	20
arcs[InvalidSt=>EscalateSt]	10142	1			T2	15		T4	5		T16	12

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5408789	1			T1	111		T2	5694		T3	72
auto[0]	auto[IdleSt]	16828665	1			T1	1477		T2	4779		T3	36624
auto[0]	auto[ClkMuxSt]	28970	1			T2	49		T4	8		T11	1
auto[0]	auto[CntIncrSt]	28719	1			T2	49		T4	8		T11	1
auto[0]	auto[CntProgSt]	1228075	1			T2	949		T4	16		T11	186
auto[0]	auto[TransCheckSt]	22530	1			T2	35		T4	8		T11	1
auto[0]	auto[TokenHashSt]	16342631	1			T2	17513		T4	3214		T11	58
auto[0]	auto[FlashRmaSt]	27612	1			T2	187		T4	8		T11	1
auto[0]	auto[TokenCheck0St]	9982	1			T2	29		T4	8		T11	1
auto[0]	auto[TokenCheck1St]	7192	1			T2	18		T4	8		T11	1
auto[0]	auto[TransProgSt]	259444	1			T2	403		T4	16		T11	81
auto[0]	auto[PostTransSt]	8688509	1			T2	6945		T4	1336		T11	562
auto[0]	auto[ScrapSt]	120727	1			T14	1193		T7	319		T28	831
auto[0]	auto[EscalateSt]	3594456	1			T2	2483		T4	683		T5	210
auto[0]	auto[InvalidSt]	7182019	1			T2	2302		T4	375		T16	2331
auto[1]	auto[ResetSt]	159	1			T48	2		T45	1		T49	1
auto[1]	auto[IdleSt]	121	1			T45	3		T49	2		T46	1
auto[1]	auto[ClkMuxSt]	34	1			T45	2		T46	1		T47	1
auto[1]	auto[CntIncrSt]	43	1			T48	1		T45	2		T47	1
auto[1]	auto[CntProgSt]	765	1			T48	21		T45	4		T49	9
auto[1]	auto[TransCheckSt]	61	1			T45	1		T209	1		T210	4
auto[1]	auto[TokenHashSt]	501	1			T48	3		T45	16		T36	1
auto[1]	auto[FlashRmaSt]	29	1			T49	1		T211	1		T212	1
auto[1]	auto[TokenCheck0St]	41	1			T48	2		T47	1		T209	4
auto[1]	auto[TokenCheck1St]	28	1			T48	1		T45	1		T47	1
auto[1]	auto[TransProgSt]	537	1			T48	20		T45	8		T49	4
auto[1]	auto[PostTransSt]	2059	1			T2	5		T5	4		T13	11
auto[1]	auto[ScrapSt]	49	1			T45	1		T49	2		T46	1
auto[1]	auto[EscalateSt]	1154388	1			T2	1470		T4	196		T5	392
auto[1]	auto[InvalidSt]	5044	1			T2	10		T4	2		T16	4

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5408785	1			T1	111		T2	5694		T3	72
auto[0]	auto[IdleSt]	16828652	1			T1	1477		T2	4779		T3	36624
auto[0]	auto[ClkMuxSt]	28975	1			T2	49		T4	8		T11	1
auto[0]	auto[CntIncrSt]	28729	1			T2	49		T4	8		T11	1
auto[0]	auto[CntProgSt]	1228105	1			T2	949		T4	16		T11	186
auto[0]	auto[TransCheckSt]	22538	1			T2	35		T4	8		T11	1
auto[0]	auto[TokenHashSt]	16342656	1			T2	17513		T4	3214		T11	58
auto[0]	auto[FlashRmaSt]	27605	1			T2	187		T4	8		T11	1
auto[0]	auto[TokenCheck0St]	9979	1			T2	29		T4	8		T11	1
auto[0]	auto[TokenCheck1St]	7198	1			T2	18		T4	8		T11	1
auto[0]	auto[TransProgSt]	259443	1			T2	403		T4	16		T11	81
auto[0]	auto[PostTransSt]	8688543	1			T2	6941		T4	1336		T11	562
auto[0]	auto[ScrapSt]	120720	1			T14	1193		T7	319		T28	831
auto[0]	auto[EscalateSt]	3601035	1			T2	2581		T4	585		T5	602
auto[0]	auto[InvalidSt]	7181965	1			T2	2307		T4	374		T16	2327
auto[1]	auto[ResetSt]	163	1			T48	2		T45	5		T49	3
auto[1]	auto[IdleSt]	134	1			T45	3		T49	3		T46	1
auto[1]	auto[ClkMuxSt]	29	1			T46	1		T213	2		T214	1
auto[1]	auto[CntIncrSt]	33	1			T47	1		T212	3		T215	1
auto[1]	auto[CntProgSt]	735	1			T48	19		T45	4		T49	7
auto[1]	auto[TransCheckSt]	53	1			T49	1		T46	1		T216	2
auto[1]	auto[TokenHashSt]	476	1			T48	2		T45	15		T36	1
auto[1]	auto[FlashRmaSt]	36	1			T45	1		T49	1		T46	1
auto[1]	auto[TokenCheck0St]	44	1			T49	2		T47	2		T211	1
auto[1]	auto[TokenCheck1St]	22	1			T216	1		T215	2		T213	1
auto[1]	auto[TransProgSt]	538	1			T48	20		T45	8		T49	8
auto[1]	auto[PostTransSt]	2025	1			T2	9		T13	9		T16	1
auto[1]	auto[ScrapSt]	56	1			T45	1		T49	1		T216	3
auto[1]	auto[EscalateSt]	1147809	1			T2	1372		T4	294		T13	882
auto[1]	auto[InvalidSt]	5098	1			T2	5		T4	3		T16	8