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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.23 97.99 95.95 93.40 100.00 98.55 98.76 95.94


Total test records in report: 1000
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T811 /workspace/coverage/default/45.lc_ctrl_sec_mubi.3258492941 Aug 15 05:11:01 PM PDT 24 Aug 15 05:11:15 PM PDT 24 872142692 ps
T812 /workspace/coverage/default/1.lc_ctrl_smoke.1152168899 Aug 15 05:07:24 PM PDT 24 Aug 15 05:07:26 PM PDT 24 25504703 ps
T813 /workspace/coverage/default/17.lc_ctrl_sec_mubi.3026282279 Aug 15 05:09:18 PM PDT 24 Aug 15 05:09:33 PM PDT 24 2722816725 ps
T814 /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2641406343 Aug 15 05:11:17 PM PDT 24 Aug 15 05:11:18 PM PDT 24 14209552 ps
T815 /workspace/coverage/default/0.lc_ctrl_prog_failure.3722123758 Aug 15 05:07:24 PM PDT 24 Aug 15 05:07:29 PM PDT 24 328994479 ps
T816 /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1749187432 Aug 15 05:07:59 PM PDT 24 Aug 15 05:08:26 PM PDT 24 4411383622 ps
T817 /workspace/coverage/default/13.lc_ctrl_state_post_trans.417179818 Aug 15 05:08:51 PM PDT 24 Aug 15 05:09:01 PM PDT 24 854848907 ps
T818 /workspace/coverage/default/20.lc_ctrl_smoke.1818288337 Aug 15 05:09:26 PM PDT 24 Aug 15 05:09:31 PM PDT 24 404227339 ps
T819 /workspace/coverage/default/8.lc_ctrl_prog_failure.4215450573 Aug 15 05:08:18 PM PDT 24 Aug 15 05:08:22 PM PDT 24 160978727 ps
T820 /workspace/coverage/default/0.lc_ctrl_state_post_trans.1693811604 Aug 15 05:07:19 PM PDT 24 Aug 15 05:07:26 PM PDT 24 84734800 ps
T821 /workspace/coverage/default/47.lc_ctrl_security_escalation.246396367 Aug 15 05:11:08 PM PDT 24 Aug 15 05:11:23 PM PDT 24 1481081507 ps
T822 /workspace/coverage/default/21.lc_ctrl_alert_test.2341349669 Aug 15 05:09:43 PM PDT 24 Aug 15 05:09:45 PM PDT 24 133896475 ps
T823 /workspace/coverage/default/32.lc_ctrl_errors.1217870582 Aug 15 05:10:24 PM PDT 24 Aug 15 05:10:34 PM PDT 24 300651313 ps
T824 /workspace/coverage/default/2.lc_ctrl_smoke.3746391633 Aug 15 05:07:34 PM PDT 24 Aug 15 05:07:36 PM PDT 24 39434488 ps
T825 /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2914415097 Aug 15 05:07:36 PM PDT 24 Aug 15 05:07:37 PM PDT 24 26485557 ps
T826 /workspace/coverage/default/23.lc_ctrl_alert_test.1399928716 Aug 15 05:09:43 PM PDT 24 Aug 15 05:09:45 PM PDT 24 24219376 ps
T827 /workspace/coverage/default/29.lc_ctrl_stress_all.4081237198 Aug 15 05:10:11 PM PDT 24 Aug 15 05:11:48 PM PDT 24 2611711023 ps
T828 /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.254193175 Aug 15 05:10:02 PM PDT 24 Aug 15 05:11:05 PM PDT 24 1544671536 ps
T829 /workspace/coverage/default/31.lc_ctrl_alert_test.3865752293 Aug 15 05:10:19 PM PDT 24 Aug 15 05:10:20 PM PDT 24 100120627 ps
T830 /workspace/coverage/default/8.lc_ctrl_jtag_access.4009081464 Aug 15 05:08:19 PM PDT 24 Aug 15 05:08:27 PM PDT 24 298966784 ps
T831 /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1480513781 Aug 15 05:07:54 PM PDT 24 Aug 15 05:07:55 PM PDT 24 33763704 ps
T832 /workspace/coverage/default/42.lc_ctrl_prog_failure.347117967 Aug 15 05:10:51 PM PDT 24 Aug 15 05:10:54 PM PDT 24 74819847 ps
T833 /workspace/coverage/default/16.lc_ctrl_stress_all.2622861981 Aug 15 05:09:09 PM PDT 24 Aug 15 05:16:56 PM PDT 24 56008482790 ps
T834 /workspace/coverage/default/49.lc_ctrl_state_failure.764391598 Aug 15 05:11:28 PM PDT 24 Aug 15 05:11:59 PM PDT 24 547384664 ps
T835 /workspace/coverage/default/46.lc_ctrl_prog_failure.1652736159 Aug 15 05:11:07 PM PDT 24 Aug 15 05:11:09 PM PDT 24 33645066 ps
T836 /workspace/coverage/default/48.lc_ctrl_stress_all.1523393858 Aug 15 05:11:18 PM PDT 24 Aug 15 05:12:34 PM PDT 24 1107569320 ps
T837 /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1044657789 Aug 15 05:10:22 PM PDT 24 Aug 15 05:10:37 PM PDT 24 1043103556 ps
T838 /workspace/coverage/default/7.lc_ctrl_alert_test.1290043699 Aug 15 05:08:11 PM PDT 24 Aug 15 05:08:12 PM PDT 24 13780977 ps
T839 /workspace/coverage/default/0.lc_ctrl_alert_test.2252335829 Aug 15 05:07:19 PM PDT 24 Aug 15 05:07:20 PM PDT 24 72917158 ps
T840 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.795827862 Aug 15 05:08:43 PM PDT 24 Aug 15 05:08:55 PM PDT 24 522675396 ps
T841 /workspace/coverage/default/10.lc_ctrl_smoke.1532447445 Aug 15 05:08:26 PM PDT 24 Aug 15 05:08:29 PM PDT 24 99577296 ps
T842 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.35432940 Aug 15 05:09:02 PM PDT 24 Aug 15 05:09:09 PM PDT 24 3534435862 ps
T843 /workspace/coverage/default/32.lc_ctrl_smoke.625986027 Aug 15 05:10:19 PM PDT 24 Aug 15 05:10:21 PM PDT 24 115179342 ps
T844 /workspace/coverage/default/49.lc_ctrl_state_post_trans.662552427 Aug 15 05:11:16 PM PDT 24 Aug 15 05:11:23 PM PDT 24 214253434 ps
T845 /workspace/coverage/default/11.lc_ctrl_security_escalation.1408218599 Aug 15 05:08:36 PM PDT 24 Aug 15 05:08:51 PM PDT 24 1102931975 ps
T846 /workspace/coverage/default/38.lc_ctrl_errors.783929816 Aug 15 05:10:46 PM PDT 24 Aug 15 05:11:01 PM PDT 24 1618392848 ps
T847 /workspace/coverage/default/6.lc_ctrl_security_escalation.1175335760 Aug 15 05:07:58 PM PDT 24 Aug 15 05:08:09 PM PDT 24 1195338824 ps
T848 /workspace/coverage/default/38.lc_ctrl_alert_test.2848401440 Aug 15 05:10:41 PM PDT 24 Aug 15 05:10:42 PM PDT 24 71538144 ps
T849 /workspace/coverage/default/3.lc_ctrl_jtag_access.3054670396 Aug 15 05:07:45 PM PDT 24 Aug 15 05:07:55 PM PDT 24 342580395 ps
T850 /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2219193820 Aug 15 05:09:38 PM PDT 24 Aug 15 05:09:39 PM PDT 24 92961037 ps
T851 /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2792166752 Aug 15 05:08:14 PM PDT 24 Aug 15 05:08:19 PM PDT 24 320248255 ps
T852 /workspace/coverage/default/11.lc_ctrl_sec_token_mux.847566730 Aug 15 05:08:48 PM PDT 24 Aug 15 05:08:56 PM PDT 24 341170021 ps
T853 /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1313680896 Aug 15 05:07:35 PM PDT 24 Aug 15 05:07:48 PM PDT 24 475335993 ps
T854 /workspace/coverage/default/43.lc_ctrl_state_failure.4227979718 Aug 15 05:10:54 PM PDT 24 Aug 15 05:11:21 PM PDT 24 977429260 ps
T855 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3688072131 Aug 15 05:07:49 PM PDT 24 Aug 15 05:07:58 PM PDT 24 333834671 ps
T856 /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3731231678 Aug 15 05:10:30 PM PDT 24 Aug 15 05:10:31 PM PDT 24 94305406 ps
T857 /workspace/coverage/default/13.lc_ctrl_stress_all.1476996459 Aug 15 05:08:53 PM PDT 24 Aug 15 05:14:33 PM PDT 24 16007989839 ps
T858 /workspace/coverage/default/8.lc_ctrl_state_failure.324015240 Aug 15 05:08:15 PM PDT 24 Aug 15 05:08:43 PM PDT 24 283033992 ps
T859 /workspace/coverage/default/45.lc_ctrl_stress_all.3931152409 Aug 15 05:11:09 PM PDT 24 Aug 15 05:13:07 PM PDT 24 13436444946 ps
T860 /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3571306903 Aug 15 05:07:35 PM PDT 24 Aug 15 05:07:42 PM PDT 24 300598530 ps
T861 /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1002252088 Aug 15 05:08:59 PM PDT 24 Aug 15 05:09:06 PM PDT 24 460615447 ps
T862 /workspace/coverage/default/15.lc_ctrl_sec_mubi.4076055582 Aug 15 05:09:01 PM PDT 24 Aug 15 05:09:17 PM PDT 24 647782342 ps
T863 /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1169055276 Aug 15 05:08:52 PM PDT 24 Aug 15 05:09:05 PM PDT 24 470767545 ps
T864 /workspace/coverage/default/24.lc_ctrl_errors.2546205183 Aug 15 05:09:46 PM PDT 24 Aug 15 05:09:57 PM PDT 24 3941343800 ps
T865 /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.293088095 Aug 15 05:07:23 PM PDT 24 Aug 15 05:07:41 PM PDT 24 462645292 ps
T866 /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1437349236 Aug 15 05:07:18 PM PDT 24 Aug 15 05:07:30 PM PDT 24 742908831 ps
T867 /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1498763881 Aug 15 05:07:52 PM PDT 24 Aug 15 05:08:14 PM PDT 24 2063141794 ps
T868 /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2539582568 Aug 15 05:09:45 PM PDT 24 Aug 15 05:09:46 PM PDT 24 45744929 ps
T869 /workspace/coverage/default/4.lc_ctrl_jtag_priority.2269282531 Aug 15 05:07:48 PM PDT 24 Aug 15 05:07:51 PM PDT 24 392849881 ps
T870 /workspace/coverage/default/8.lc_ctrl_jtag_priority.2004601489 Aug 15 05:08:21 PM PDT 24 Aug 15 05:08:38 PM PDT 24 2921930418 ps
T871 /workspace/coverage/default/47.lc_ctrl_state_failure.3029743631 Aug 15 05:11:08 PM PDT 24 Aug 15 05:11:34 PM PDT 24 2835773020 ps
T872 /workspace/coverage/default/46.lc_ctrl_jtag_access.860114645 Aug 15 05:11:11 PM PDT 24 Aug 15 05:11:17 PM PDT 24 225281931 ps
T873 /workspace/coverage/default/16.lc_ctrl_alert_test.1685089000 Aug 15 05:09:13 PM PDT 24 Aug 15 05:09:14 PM PDT 24 23669895 ps
T78 /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1527004818 Aug 15 05:07:18 PM PDT 24 Aug 15 05:07:49 PM PDT 24 4132634039 ps
T874 /workspace/coverage/default/33.lc_ctrl_prog_failure.3959087478 Aug 15 05:10:20 PM PDT 24 Aug 15 05:10:24 PM PDT 24 198265778 ps
T202 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1690387927 Aug 15 05:05:27 PM PDT 24 Aug 15 05:05:28 PM PDT 24 40262690 ps
T115 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3690759662 Aug 15 05:05:09 PM PDT 24 Aug 15 05:05:11 PM PDT 24 105343085 ps
T116 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2493855445 Aug 15 05:06:14 PM PDT 24 Aug 15 05:06:16 PM PDT 24 30700627 ps
T117 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3908183884 Aug 15 05:05:08 PM PDT 24 Aug 15 05:05:10 PM PDT 24 92068313 ps
T141 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.322878623 Aug 15 05:05:35 PM PDT 24 Aug 15 05:05:46 PM PDT 24 2883841756 ps
T140 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1040627851 Aug 15 05:06:11 PM PDT 24 Aug 15 05:06:12 PM PDT 24 345359936 ps
T203 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3861762106 Aug 15 05:06:06 PM PDT 24 Aug 15 05:06:07 PM PDT 24 26017986 ps
T111 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3664994363 Aug 15 05:05:54 PM PDT 24 Aug 15 05:05:56 PM PDT 24 94493152 ps
T108 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1547034577 Aug 15 05:06:19 PM PDT 24 Aug 15 05:06:23 PM PDT 24 106762611 ps
T142 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1165424931 Aug 15 05:06:04 PM PDT 24 Aug 15 05:06:05 PM PDT 24 201435617 ps
T109 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1674225866 Aug 15 05:05:17 PM PDT 24 Aug 15 05:05:20 PM PDT 24 212835547 ps
T155 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.310887388 Aug 15 05:06:12 PM PDT 24 Aug 15 05:06:14 PM PDT 24 32885939 ps
T156 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.506508621 Aug 15 05:05:38 PM PDT 24 Aug 15 05:05:39 PM PDT 24 49445743 ps
T119 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1726037858 Aug 15 05:05:01 PM PDT 24 Aug 15 05:05:03 PM PDT 24 103820398 ps
T875 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2818053079 Aug 15 05:06:28 PM PDT 24 Aug 15 05:06:29 PM PDT 24 12989785 ps
T876 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4288801416 Aug 15 05:05:59 PM PDT 24 Aug 15 05:06:09 PM PDT 24 371619475 ps
T877 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3878141788 Aug 15 05:05:54 PM PDT 24 Aug 15 05:05:56 PM PDT 24 324663118 ps
T157 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1353068403 Aug 15 05:06:20 PM PDT 24 Aug 15 05:06:22 PM PDT 24 44106263 ps
T158 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1171075105 Aug 15 05:04:52 PM PDT 24 Aug 15 05:04:54 PM PDT 24 108298493 ps
T159 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2198769205 Aug 15 05:05:26 PM PDT 24 Aug 15 05:05:27 PM PDT 24 26111824 ps
T110 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.543238250 Aug 15 05:06:21 PM PDT 24 Aug 15 05:06:25 PM PDT 24 105640822 ps
T878 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4187175450 Aug 15 05:06:04 PM PDT 24 Aug 15 05:06:06 PM PDT 24 60705715 ps
T160 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.49241937 Aug 15 05:05:04 PM PDT 24 Aug 15 05:05:07 PM PDT 24 96334642 ps
T161 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.891075015 Aug 15 05:06:03 PM PDT 24 Aug 15 05:06:04 PM PDT 24 55593358 ps
T112 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.929171291 Aug 15 05:06:20 PM PDT 24 Aug 15 05:06:23 PM PDT 24 146506589 ps
T879 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4028536842 Aug 15 05:05:49 PM PDT 24 Aug 15 05:05:51 PM PDT 24 72275914 ps
T113 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2853541470 Aug 15 05:06:20 PM PDT 24 Aug 15 05:06:22 PM PDT 24 183639932 ps
T880 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3161256874 Aug 15 05:06:06 PM PDT 24 Aug 15 05:06:21 PM PDT 24 3036626217 ps
T162 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3995110211 Aug 15 05:05:48 PM PDT 24 Aug 15 05:05:49 PM PDT 24 58210384 ps
T185 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3969669245 Aug 15 05:05:18 PM PDT 24 Aug 15 05:05:22 PM PDT 24 2119488052 ps
T881 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.917906458 Aug 15 05:05:58 PM PDT 24 Aug 15 05:06:09 PM PDT 24 5075611968 ps
T882 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1419373532 Aug 15 05:06:22 PM PDT 24 Aug 15 05:06:24 PM PDT 24 126338993 ps
T114 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.950178929 Aug 15 05:06:14 PM PDT 24 Aug 15 05:06:15 PM PDT 24 15828918 ps
T175 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3178822432 Aug 15 05:06:11 PM PDT 24 Aug 15 05:06:13 PM PDT 24 23678198 ps
T883 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2904288771 Aug 15 05:05:17 PM PDT 24 Aug 15 05:05:29 PM PDT 24 2421987728 ps
T884 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.938235456 Aug 15 05:05:09 PM PDT 24 Aug 15 05:05:35 PM PDT 24 2594646546 ps
T885 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1939749614 Aug 15 05:05:35 PM PDT 24 Aug 15 05:05:36 PM PDT 24 43712453 ps
T120 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1615576959 Aug 15 05:06:14 PM PDT 24 Aug 15 05:06:16 PM PDT 24 91585930 ps
T886 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1863481358 Aug 15 05:04:53 PM PDT 24 Aug 15 05:04:58 PM PDT 24 873486680 ps
T131 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3173152404 Aug 15 05:06:12 PM PDT 24 Aug 15 05:06:15 PM PDT 24 66849195 ps
T134 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.113892099 Aug 15 05:05:36 PM PDT 24 Aug 15 05:05:39 PM PDT 24 150997989 ps
T887 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2149737049 Aug 15 05:06:27 PM PDT 24 Aug 15 05:06:28 PM PDT 24 49882130 ps
T133 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1876252892 Aug 15 05:06:02 PM PDT 24 Aug 15 05:06:06 PM PDT 24 316994867 ps
T888 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2032287683 Aug 15 05:05:17 PM PDT 24 Aug 15 05:05:19 PM PDT 24 37129331 ps
T121 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1576725687 Aug 15 05:05:27 PM PDT 24 Aug 15 05:05:28 PM PDT 24 38034469 ps
T889 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1841987286 Aug 15 05:06:12 PM PDT 24 Aug 15 05:06:13 PM PDT 24 38300751 ps
T189 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2331889728 Aug 15 05:06:20 PM PDT 24 Aug 15 05:06:21 PM PDT 24 15415327 ps
T890 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3082920102 Aug 15 05:06:23 PM PDT 24 Aug 15 05:06:24 PM PDT 24 32139684 ps
T891 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1321421881 Aug 15 05:06:19 PM PDT 24 Aug 15 05:06:21 PM PDT 24 19446719 ps
T892 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.4013778258 Aug 15 05:05:19 PM PDT 24 Aug 15 05:05:20 PM PDT 24 41866597 ps
T138 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3147331433 Aug 15 05:05:47 PM PDT 24 Aug 15 05:05:49 PM PDT 24 248679254 ps
T893 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2454038711 Aug 15 05:05:18 PM PDT 24 Aug 15 05:05:26 PM PDT 24 898987441 ps
T894 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3926520638 Aug 15 05:05:37 PM PDT 24 Aug 15 05:05:38 PM PDT 24 21720462 ps
T895 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.727167094 Aug 15 05:05:17 PM PDT 24 Aug 15 05:05:19 PM PDT 24 161914544 ps
T124 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.372211208 Aug 15 05:05:36 PM PDT 24 Aug 15 05:05:40 PM PDT 24 350601981 ps
T896 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2087137717 Aug 15 05:05:36 PM PDT 24 Aug 15 05:05:39 PM PDT 24 226916193 ps
T190 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.182835982 Aug 15 05:06:11 PM PDT 24 Aug 15 05:06:13 PM PDT 24 31241807 ps
T123 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2950502692 Aug 15 05:06:04 PM PDT 24 Aug 15 05:06:08 PM PDT 24 239806195 ps
T897 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2454000929 Aug 15 05:05:36 PM PDT 24 Aug 15 05:05:37 PM PDT 24 98086385 ps
T898 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1368381166 Aug 15 05:05:47 PM PDT 24 Aug 15 05:05:49 PM PDT 24 65597146 ps
T899 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.784089139 Aug 15 05:05:37 PM PDT 24 Aug 15 05:05:38 PM PDT 24 88275254 ps
T900 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2593123916 Aug 15 05:06:28 PM PDT 24 Aug 15 05:06:29 PM PDT 24 53529223 ps
T901 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1504206990 Aug 15 05:05:26 PM PDT 24 Aug 15 05:05:28 PM PDT 24 27771475 ps
T902 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1498044182 Aug 15 05:05:59 PM PDT 24 Aug 15 05:06:02 PM PDT 24 181971448 ps
T130 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.284282875 Aug 15 05:05:54 PM PDT 24 Aug 15 05:05:57 PM PDT 24 59068304 ps
T139 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3106019928 Aug 15 05:06:20 PM PDT 24 Aug 15 05:06:24 PM PDT 24 418016456 ps
T903 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4128097696 Aug 15 05:06:01 PM PDT 24 Aug 15 05:06:05 PM PDT 24 296445423 ps
T904 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2298415616 Aug 15 05:05:47 PM PDT 24 Aug 15 05:05:48 PM PDT 24 123349595 ps
T905 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3540542966 Aug 15 05:06:21 PM PDT 24 Aug 15 05:06:22 PM PDT 24 80946809 ps
T128 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3369652138 Aug 15 05:06:10 PM PDT 24 Aug 15 05:06:14 PM PDT 24 252483515 ps
T132 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3102879909 Aug 15 05:06:28 PM PDT 24 Aug 15 05:06:31 PM PDT 24 298524448 ps
T906 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1994500353 Aug 15 05:05:47 PM PDT 24 Aug 15 05:05:49 PM PDT 24 175251943 ps
T907 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3303377373 Aug 15 05:06:29 PM PDT 24 Aug 15 05:06:33 PM PDT 24 167512122 ps
T908 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2262905775 Aug 15 05:04:53 PM PDT 24 Aug 15 05:04:57 PM PDT 24 96049049 ps
T909 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.116823424 Aug 15 05:05:55 PM PDT 24 Aug 15 05:05:56 PM PDT 24 57655957 ps
T122 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.167279922 Aug 15 05:05:57 PM PDT 24 Aug 15 05:05:59 PM PDT 24 182012292 ps
T910 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2683862781 Aug 15 05:05:46 PM PDT 24 Aug 15 05:05:47 PM PDT 24 146628350 ps
T911 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.400776 Aug 15 05:06:26 PM PDT 24 Aug 15 05:06:28 PM PDT 24 101260407 ps
T191 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.454152265 Aug 15 05:06:12 PM PDT 24 Aug 15 05:06:13 PM PDT 24 15126792 ps
T912 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1995255278 Aug 15 05:06:20 PM PDT 24 Aug 15 05:06:21 PM PDT 24 22243655 ps
T913 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3759034065 Aug 15 05:06:16 PM PDT 24 Aug 15 05:06:17 PM PDT 24 88743888 ps
T136 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2356093576 Aug 15 05:06:14 PM PDT 24 Aug 15 05:06:16 PM PDT 24 77161097 ps
T914 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2271798047 Aug 15 05:05:19 PM PDT 24 Aug 15 05:05:20 PM PDT 24 170085730 ps
T915 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1112649624 Aug 15 05:06:20 PM PDT 24 Aug 15 05:06:21 PM PDT 24 29055019 ps
T916 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.110331786 Aug 15 05:05:46 PM PDT 24 Aug 15 05:05:49 PM PDT 24 45560462 ps
T917 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2539141024 Aug 15 05:06:20 PM PDT 24 Aug 15 05:06:21 PM PDT 24 96840268 ps
T137 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.4150733835 Aug 15 05:05:20 PM PDT 24 Aug 15 05:05:23 PM PDT 24 126423150 ps
T192 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2475257306 Aug 15 05:05:01 PM PDT 24 Aug 15 05:05:02 PM PDT 24 50203809 ps
T918 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3737820268 Aug 15 05:05:01 PM PDT 24 Aug 15 05:05:03 PM PDT 24 322043168 ps
T919 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.137765348 Aug 15 05:05:58 PM PDT 24 Aug 15 05:05:59 PM PDT 24 71330174 ps
T920 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.548454605 Aug 15 05:05:26 PM PDT 24 Aug 15 05:05:27 PM PDT 24 68135897 ps
T921 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2549753527 Aug 15 05:06:28 PM PDT 24 Aug 15 05:06:30 PM PDT 24 21036916 ps
T193 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2647243187 Aug 15 05:06:20 PM PDT 24 Aug 15 05:06:21 PM PDT 24 17083064 ps
T922 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2365029198 Aug 15 05:06:04 PM PDT 24 Aug 15 05:06:11 PM PDT 24 273480825 ps
T923 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1323950111 Aug 15 05:05:55 PM PDT 24 Aug 15 05:05:57 PM PDT 24 193818063 ps
T194 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.123770805 Aug 15 05:05:26 PM PDT 24 Aug 15 05:05:27 PM PDT 24 20384471 ps
T924 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4101245970 Aug 15 05:05:59 PM PDT 24 Aug 15 05:06:01 PM PDT 24 172709126 ps
T925 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3589683723 Aug 15 05:06:19 PM PDT 24 Aug 15 05:06:22 PM PDT 24 37040368 ps
T926 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2686629607 Aug 15 05:06:12 PM PDT 24 Aug 15 05:06:14 PM PDT 24 117410944 ps
T927 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3770951321 Aug 15 05:05:46 PM PDT 24 Aug 15 05:05:48 PM PDT 24 34489858 ps
T125 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2155528893 Aug 15 05:06:23 PM PDT 24 Aug 15 05:06:26 PM PDT 24 204947096 ps
T928 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1507310205 Aug 15 05:04:52 PM PDT 24 Aug 15 05:05:13 PM PDT 24 12346432005 ps
T929 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.451772634 Aug 15 05:06:22 PM PDT 24 Aug 15 05:06:26 PM PDT 24 399236481 ps
T930 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.551859420 Aug 15 05:05:55 PM PDT 24 Aug 15 05:05:56 PM PDT 24 86234545 ps
T931 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3810832454 Aug 15 05:05:10 PM PDT 24 Aug 15 05:05:13 PM PDT 24 1905580758 ps
T126 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1870340042 Aug 15 05:06:13 PM PDT 24 Aug 15 05:06:16 PM PDT 24 147921224 ps
T932 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2134137298 Aug 15 05:06:29 PM PDT 24 Aug 15 05:06:30 PM PDT 24 30834369 ps
T933 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2597019087 Aug 15 05:06:21 PM PDT 24 Aug 15 05:06:23 PM PDT 24 47487430 ps
T934 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2978672502 Aug 15 05:06:20 PM PDT 24 Aug 15 05:06:22 PM PDT 24 14253594 ps
T935 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3888911401 Aug 15 05:05:00 PM PDT 24 Aug 15 05:05:01 PM PDT 24 59712443 ps
T936 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3078392583 Aug 15 05:05:55 PM PDT 24 Aug 15 05:05:57 PM PDT 24 127459382 ps
T937 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4246075355 Aug 15 05:06:10 PM PDT 24 Aug 15 05:06:12 PM PDT 24 19036781 ps
T938 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2683411460 Aug 15 05:05:56 PM PDT 24 Aug 15 05:06:11 PM PDT 24 1653821033 ps
T939 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.195680734 Aug 15 05:05:36 PM PDT 24 Aug 15 05:05:38 PM PDT 24 358240156 ps
T940 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1518976889 Aug 15 05:06:11 PM PDT 24 Aug 15 05:06:12 PM PDT 24 135451074 ps
T941 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3468871685 Aug 15 05:05:36 PM PDT 24 Aug 15 05:05:37 PM PDT 24 24863328 ps
T942 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1691397726 Aug 15 05:05:28 PM PDT 24 Aug 15 05:05:38 PM PDT 24 839238116 ps
T943 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.953060964 Aug 15 05:06:03 PM PDT 24 Aug 15 05:06:05 PM PDT 24 47788188 ps
T944 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.86843672 Aug 15 05:05:28 PM PDT 24 Aug 15 05:05:29 PM PDT 24 14878168 ps
T945 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.919622152 Aug 15 05:06:03 PM PDT 24 Aug 15 05:06:28 PM PDT 24 5729423505 ps
T946 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3622490208 Aug 15 05:04:55 PM PDT 24 Aug 15 05:04:57 PM PDT 24 58042274 ps
T947 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.18435805 Aug 15 05:06:05 PM PDT 24 Aug 15 05:06:06 PM PDT 24 43346154 ps
T129 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3507374326 Aug 15 05:06:29 PM PDT 24 Aug 15 05:06:32 PM PDT 24 376512283 ps
T195 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.878243721 Aug 15 05:06:13 PM PDT 24 Aug 15 05:06:14 PM PDT 24 23556652 ps
T948 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.609878076 Aug 15 05:05:36 PM PDT 24 Aug 15 05:05:38 PM PDT 24 23288906 ps
T949 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1913634979 Aug 15 05:06:03 PM PDT 24 Aug 15 05:06:06 PM PDT 24 188274112 ps
T950 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.925395315 Aug 15 05:06:19 PM PDT 24 Aug 15 05:06:24 PM PDT 24 545987199 ps
T951 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1302710532 Aug 15 05:06:03 PM PDT 24 Aug 15 05:06:04 PM PDT 24 24419753 ps
T952 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.329728286 Aug 15 05:06:20 PM PDT 24 Aug 15 05:06:23 PM PDT 24 30729433 ps
T135 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.716754571 Aug 15 05:05:48 PM PDT 24 Aug 15 05:05:51 PM PDT 24 719298107 ps
T953 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1660560189 Aug 15 05:05:10 PM PDT 24 Aug 15 05:05:13 PM PDT 24 136235166 ps
T954 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1963911211 Aug 15 05:05:46 PM PDT 24 Aug 15 05:05:47 PM PDT 24 16899229 ps
T955 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1329719461 Aug 15 05:05:57 PM PDT 24 Aug 15 05:05:58 PM PDT 24 13763930 ps
T956 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3331841514 Aug 15 05:04:52 PM PDT 24 Aug 15 05:04:53 PM PDT 24 222181855 ps
T957 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1026330092 Aug 15 05:05:10 PM PDT 24 Aug 15 05:05:16 PM PDT 24 857174977 ps
T958 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1582202672 Aug 15 05:06:03 PM PDT 24 Aug 15 05:06:10 PM PDT 24 2634025689 ps
T959 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1688344688 Aug 15 05:05:47 PM PDT 24 Aug 15 05:05:50 PM PDT 24 519664476 ps
T960 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3616910287 Aug 15 05:06:22 PM PDT 24 Aug 15 05:06:23 PM PDT 24 24484442 ps
T961 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1804808764 Aug 15 05:05:27 PM PDT 24 Aug 15 05:05:31 PM PDT 24 129799025 ps
T962 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1286120575 Aug 15 05:05:36 PM PDT 24 Aug 15 05:05:38 PM PDT 24 977829332 ps
T196 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3824835347 Aug 15 05:05:21 PM PDT 24 Aug 15 05:05:22 PM PDT 24 20126541 ps
T963 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4186220095 Aug 15 05:05:27 PM PDT 24 Aug 15 05:05:30 PM PDT 24 118903807 ps
T964 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.542550877 Aug 15 05:05:53 PM PDT 24 Aug 15 05:05:56 PM PDT 24 256610151 ps
T965 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1319179281 Aug 15 05:05:48 PM PDT 24 Aug 15 05:05:49 PM PDT 24 26157076 ps
T197 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.703376750 Aug 15 05:05:46 PM PDT 24 Aug 15 05:05:47 PM PDT 24 40418553 ps
T966 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2084217146 Aug 15 05:05:48 PM PDT 24 Aug 15 05:05:50 PM PDT 24 17459643 ps
T967 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2195511413 Aug 15 05:06:20 PM PDT 24 Aug 15 05:06:21 PM PDT 24 45869003 ps
T968 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3098346375 Aug 15 05:06:20 PM PDT 24 Aug 15 05:06:22 PM PDT 24 21317376 ps
T969 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.833683987 Aug 15 05:05:27 PM PDT 24 Aug 15 05:05:33 PM PDT 24 445453837 ps
T970 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2722261529 Aug 15 05:06:04 PM PDT 24 Aug 15 05:06:06 PM PDT 24 141755370 ps
T971 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2349081348 Aug 15 05:05:54 PM PDT 24 Aug 15 05:05:56 PM PDT 24 47205837 ps
T972 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3590040969 Aug 15 05:05:37 PM PDT 24 Aug 15 05:05:38 PM PDT 24 59607429 ps
T973 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1517827821 Aug 15 05:05:56 PM PDT 24 Aug 15 05:06:14 PM PDT 24 2908021279 ps
T974 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.902964865 Aug 15 05:05:36 PM PDT 24 Aug 15 05:06:34 PM PDT 24 11375875788 ps
T975 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3918489270 Aug 15 05:05:18 PM PDT 24 Aug 15 05:05:19 PM PDT 24 109387425 ps
T976 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3885848429 Aug 15 05:06:03 PM PDT 24 Aug 15 05:06:33 PM PDT 24 2633619211 ps
T977 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2144929088 Aug 15 05:05:48 PM PDT 24 Aug 15 05:05:50 PM PDT 24 97484766 ps
T978 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.445850939 Aug 15 05:04:55 PM PDT 24 Aug 15 05:04:57 PM PDT 24 159338838 ps
T200 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3762353 Aug 15 05:05:19 PM PDT 24 Aug 15 05:05:20 PM PDT 24 69427059 ps
T979 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1585245104 Aug 15 05:05:47 PM PDT 24 Aug 15 05:05:49 PM PDT 24 81414148 ps
T980 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3527261783 Aug 15 05:05:19 PM PDT 24 Aug 15 05:05:20 PM PDT 24 15123559 ps
T981 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3825173282 Aug 15 05:05:19 PM PDT 24 Aug 15 05:05:21 PM PDT 24 64917858 ps
T982 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.743044941 Aug 15 05:05:37 PM PDT 24 Aug 15 05:05:38 PM PDT 24 93972145 ps
T983 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1529125597 Aug 15 05:05:47 PM PDT 24 Aug 15 05:05:52 PM PDT 24 2360881128 ps
T984 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.924962420 Aug 15 05:05:46 PM PDT 24 Aug 15 05:05:57 PM PDT 24 1375519848 ps
T198 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.280013237 Aug 15 05:05:45 PM PDT 24 Aug 15 05:05:47 PM PDT 24 11815517 ps
T985 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3560954247 Aug 15 05:06:09 PM PDT 24 Aug 15 05:06:12 PM PDT 24 939725795 ps
T199 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3140180866 Aug 15 05:05:37 PM PDT 24 Aug 15 05:05:39 PM PDT 24 87261547 ps
T986 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.825503544 Aug 15 05:06:05 PM PDT 24 Aug 15 05:06:08 PM PDT 24 145188297 ps
T987 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1587443685 Aug 15 05:05:49 PM PDT 24 Aug 15 05:05:51 PM PDT 24 128701477 ps
T988 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.806952857 Aug 15 05:05:58 PM PDT 24 Aug 15 05:05:59 PM PDT 24 15839887 ps
T989 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1130173301 Aug 15 05:05:20 PM PDT 24 Aug 15 05:05:22 PM PDT 24 102342051 ps
T990 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1461249523 Aug 15 05:05:17 PM PDT 24 Aug 15 05:05:23 PM PDT 24 155404536 ps
T991 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1941278499 Aug 15 05:05:04 PM PDT 24 Aug 15 05:05:05 PM PDT 24 35355594 ps
T992 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3082303778 Aug 15 05:06:03 PM PDT 24 Aug 15 05:06:05 PM PDT 24 313755263 ps
T993 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1159299878 Aug 15 05:05:09 PM PDT 24 Aug 15 05:05:12 PM PDT 24 71501890 ps
T994 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1883359295 Aug 15 05:05:18 PM PDT 24 Aug 15 05:05:22 PM PDT 24 127909455 ps
T995 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2118553095 Aug 15 05:06:03 PM PDT 24 Aug 15 05:06:04 PM PDT 24 48188204 ps
T996 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1250190825 Aug 15 05:06:20 PM PDT 24 Aug 15 05:06:21 PM PDT 24 55693945 ps
T997 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3752811902 Aug 15 05:06:20 PM PDT 24 Aug 15 05:06:22 PM PDT 24 251093637 ps
T127 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3583219934 Aug 15 05:04:55 PM PDT 24 Aug 15 05:05:00 PM PDT 24 118814142 ps
T998 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1547643270 Aug 15 05:05:57 PM PDT 24 Aug 15 05:06:00 PM PDT 24 382360439 ps
T999 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4099337581 Aug 15 05:04:53 PM PDT 24 Aug 15 05:04:54 PM PDT 24 127503429 ps
T201 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.44850770 Aug 15 05:06:04 PM PDT 24 Aug 15 05:06:05 PM PDT 24 18103006 ps
T1000 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2120138286 Aug 15 05:05:56 PM PDT 24 Aug 15 05:06:00 PM PDT 24 103585471 ps

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.4214415915
Short name T2
Test name
Test status
Simulation time 437973224 ps
CPU time 12.53 seconds
Started Aug 15 05:09:00 PM PDT 24
Finished Aug 15 05:09:13 PM PDT 24
Peak memory 226052 kb
Host smart-0617092e-8f54-456a-a0cd-7a550772e7b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214415915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.4214415915
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.4163027289
Short name T10
Test name
Test status
Simulation time 10369886014 ps
CPU time 178.75 seconds
Started Aug 15 05:08:45 PM PDT 24
Finished Aug 15 05:11:44 PM PDT 24
Peak memory 283540 kb
Host smart-5f8b212c-3964-4129-ad75-8eb159487412
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163027289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.4163027289
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1602465559
Short name T45
Test name
Test status
Simulation time 341552755 ps
CPU time 8.35 seconds
Started Aug 15 05:07:27 PM PDT 24
Finished Aug 15 05:07:35 PM PDT 24
Peak memory 218360 kb
Host smart-1a9c3712-7693-4781-8f28-460938683da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602465559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1602465559
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1968836854
Short name T36
Test name
Test status
Simulation time 63405101813 ps
CPU time 124.19 seconds
Started Aug 15 05:11:07 PM PDT 24
Finished Aug 15 05:13:11 PM PDT 24
Peak memory 282600 kb
Host smart-e871d02c-0ec3-45ce-9b04-192bf2879875
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968836854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1968836854
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.994540578
Short name T87
Test name
Test status
Simulation time 13485988340 ps
CPU time 159.92 seconds
Started Aug 15 05:09:36 PM PDT 24
Finished Aug 15 05:12:16 PM PDT 24
Peak memory 283916 kb
Host smart-ee2fc51b-54e2-4bd8-a705-222ac2085cc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=994540578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.994540578
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1086751585
Short name T12
Test name
Test status
Simulation time 2879995141 ps
CPU time 13.76 seconds
Started Aug 15 05:09:26 PM PDT 24
Finished Aug 15 05:09:40 PM PDT 24
Peak memory 226136 kb
Host smart-76f7367c-856e-47be-a4ae-93b6330f2ea2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086751585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1086751585
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1547034577
Short name T108
Test name
Test status
Simulation time 106762611 ps
CPU time 3.08 seconds
Started Aug 15 05:06:19 PM PDT 24
Finished Aug 15 05:06:23 PM PDT 24
Peak memory 218288 kb
Host smart-c1091a9f-4545-4d45-a3b9-98238d2b11b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547034577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1547034577
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1325275567
Short name T31
Test name
Test status
Simulation time 12691001 ps
CPU time 0.8 seconds
Started Aug 15 05:10:19 PM PDT 24
Finished Aug 15 05:10:20 PM PDT 24
Peak memory 208988 kb
Host smart-ed8751e4-31ee-4605-9eb6-8c2d6ef5d0f7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325275567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1325275567
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2621335252
Short name T50
Test name
Test status
Simulation time 2228147908 ps
CPU time 24.37 seconds
Started Aug 15 05:07:36 PM PDT 24
Finished Aug 15 05:08:01 PM PDT 24
Peak memory 269224 kb
Host smart-a180de79-b69a-4e08-a94f-3b5cd88ae52f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621335252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2621335252
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.4283332849
Short name T53
Test name
Test status
Simulation time 5447392538 ps
CPU time 240.71 seconds
Started Aug 15 05:11:12 PM PDT 24
Finished Aug 15 05:15:13 PM PDT 24
Peak memory 333056 kb
Host smart-a653beda-e8d0-410b-81a6-646a5434d743
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4283332849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.4283332849
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3371373678
Short name T278
Test name
Test status
Simulation time 1825867189 ps
CPU time 13.07 seconds
Started Aug 15 05:11:08 PM PDT 24
Finished Aug 15 05:11:21 PM PDT 24
Peak memory 226144 kb
Host smart-1fb88201-06b3-478d-9ad2-ec596e63fa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371373678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3371373678
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2244460598
Short name T21
Test name
Test status
Simulation time 3691503849 ps
CPU time 7.02 seconds
Started Aug 15 05:10:11 PM PDT 24
Finished Aug 15 05:10:18 PM PDT 24
Peak memory 217724 kb
Host smart-d3134a86-0850-4642-96a9-552db6555aed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244460598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2244460598
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2875596621
Short name T169
Test name
Test status
Simulation time 1095359016 ps
CPU time 12.48 seconds
Started Aug 15 05:10:28 PM PDT 24
Finished Aug 15 05:10:41 PM PDT 24
Peak memory 218436 kb
Host smart-3c3dc5e8-bd2a-4fcf-8477-b5b776e87b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875596621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2875596621
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1674225866
Short name T109
Test name
Test status
Simulation time 212835547 ps
CPU time 3.42 seconds
Started Aug 15 05:05:17 PM PDT 24
Finished Aug 15 05:05:20 PM PDT 24
Peak memory 220676 kb
Host smart-17ede2a5-2655-4755-8fd8-bf9a9232d352
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167422
5866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1674225866
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2854090310
Short name T44
Test name
Test status
Simulation time 247663387 ps
CPU time 25.9 seconds
Started Aug 15 05:08:38 PM PDT 24
Finished Aug 15 05:09:04 PM PDT 24
Peak memory 250644 kb
Host smart-c9a1322c-2618-46ba-ac90-cf2392eb4ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854090310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2854090310
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3379164826
Short name T171
Test name
Test status
Simulation time 3624614985 ps
CPU time 112.54 seconds
Started Aug 15 05:07:18 PM PDT 24
Finished Aug 15 05:09:10 PM PDT 24
Peak memory 268916 kb
Host smart-355b52a9-6d7a-48f8-a076-33ca26c6374c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379164826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3379164826
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1490603162
Short name T1
Test name
Test status
Simulation time 33106108 ps
CPU time 0.92 seconds
Started Aug 15 05:10:03 PM PDT 24
Finished Aug 15 05:10:04 PM PDT 24
Peak memory 208960 kb
Host smart-08bec95d-0e2c-470b-93ef-948cfb8bcaeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490603162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1490603162
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2689301624
Short name T149
Test name
Test status
Simulation time 1291973993 ps
CPU time 11.54 seconds
Started Aug 15 05:08:48 PM PDT 24
Finished Aug 15 05:09:00 PM PDT 24
Peak memory 218280 kb
Host smart-4323fb35-5559-4396-b921-dbed70398150
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689301624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2689301624
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2198769205
Short name T159
Test name
Test status
Simulation time 26111824 ps
CPU time 1.11 seconds
Started Aug 15 05:05:26 PM PDT 24
Finished Aug 15 05:05:27 PM PDT 24
Peak memory 210064 kb
Host smart-dcb30114-1974-43e7-a865-5dd1e68b314e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198769205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2198769205
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1194453849
Short name T83
Test name
Test status
Simulation time 18136763518 ps
CPU time 270.3 seconds
Started Aug 15 05:08:44 PM PDT 24
Finished Aug 15 05:13:15 PM PDT 24
Peak memory 252920 kb
Host smart-c1a91e74-d5a1-46b9-9aea-9f7626bcf218
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194453849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1194453849
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.543238250
Short name T110
Test name
Test status
Simulation time 105640822 ps
CPU time 4.25 seconds
Started Aug 15 05:06:21 PM PDT 24
Finished Aug 15 05:06:25 PM PDT 24
Peak memory 218428 kb
Host smart-852346a3-32ac-4663-8166-03a3a1c302f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543238250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.543238250
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.929171291
Short name T112
Test name
Test status
Simulation time 146506589 ps
CPU time 2.9 seconds
Started Aug 15 05:06:20 PM PDT 24
Finished Aug 15 05:06:23 PM PDT 24
Peak memory 219324 kb
Host smart-20651752-5137-4934-8ed5-b1b06f319268
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929171291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.929171291
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1830791933
Short name T18
Test name
Test status
Simulation time 4577447806 ps
CPU time 66.99 seconds
Started Aug 15 05:09:20 PM PDT 24
Finished Aug 15 05:10:28 PM PDT 24
Peak memory 218984 kb
Host smart-3905f4b9-14b2-49d3-852b-7854f553a19e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830791933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1830791933
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3507374326
Short name T129
Test name
Test status
Simulation time 376512283 ps
CPU time 3.15 seconds
Started Aug 15 05:06:29 PM PDT 24
Finished Aug 15 05:06:32 PM PDT 24
Peak memory 223212 kb
Host smart-29e300bf-8b00-4e9a-8ce8-64aa71ba8742
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507374326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3507374326
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3106019928
Short name T139
Test name
Test status
Simulation time 418016456 ps
CPU time 3.28 seconds
Started Aug 15 05:06:20 PM PDT 24
Finished Aug 15 05:06:24 PM PDT 24
Peak memory 222964 kb
Host smart-c67de6b4-39df-4372-a276-2db775e5b75d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106019928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3106019928
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.372211208
Short name T124
Test name
Test status
Simulation time 350601981 ps
CPU time 4.07 seconds
Started Aug 15 05:05:36 PM PDT 24
Finished Aug 15 05:05:40 PM PDT 24
Peak memory 218236 kb
Host smart-aabcbf37-d04e-41e7-8fb3-a1dc0a1dae2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372211208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.372211208
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1876252892
Short name T133
Test name
Test status
Simulation time 316994867 ps
CPU time 3.17 seconds
Started Aug 15 05:06:02 PM PDT 24
Finished Aug 15 05:06:06 PM PDT 24
Peak memory 223036 kb
Host smart-270eeb32-5d2e-47d6-8ed5-4eb5c9bc5bd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876252892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1876252892
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1171075105
Short name T158
Test name
Test status
Simulation time 108298493 ps
CPU time 1.43 seconds
Started Aug 15 05:04:52 PM PDT 24
Finished Aug 15 05:04:54 PM PDT 24
Peak memory 210064 kb
Host smart-b7cfb977-5d09-4054-b4e4-14ed49796616
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171075105 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1171075105
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1135515073
Short name T91
Test name
Test status
Simulation time 13791127901 ps
CPU time 46.17 seconds
Started Aug 15 05:07:29 PM PDT 24
Finished Aug 15 05:08:15 PM PDT 24
Peak memory 259492 kb
Host smart-ec2919db-2b26-4536-b8d4-1a4e18213212
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1135515073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.1135515073
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1726037858
Short name T119
Test name
Test status
Simulation time 103820398 ps
CPU time 1.34 seconds
Started Aug 15 05:05:01 PM PDT 24
Finished Aug 15 05:05:03 PM PDT 24
Peak memory 218368 kb
Host smart-ca73a6f1-4328-45f1-843e-91903b0157f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726037858 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1726037858
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3102879909
Short name T132
Test name
Test status
Simulation time 298524448 ps
CPU time 2.71 seconds
Started Aug 15 05:06:28 PM PDT 24
Finished Aug 15 05:06:31 PM PDT 24
Peak memory 222676 kb
Host smart-0866d551-8e8a-4ecc-bc83-5c76b7f638a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102879909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3102879909
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3852944537
Short name T207
Test name
Test status
Simulation time 22712773 ps
CPU time 0.95 seconds
Started Aug 15 05:07:18 PM PDT 24
Finished Aug 15 05:07:19 PM PDT 24
Peak memory 208884 kb
Host smart-d921334d-db9e-4f77-b5e8-864e16848433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852944537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3852944537
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1908279380
Short name T208
Test name
Test status
Simulation time 10941609 ps
CPU time 0.95 seconds
Started Aug 15 05:08:19 PM PDT 24
Finished Aug 15 05:08:20 PM PDT 24
Peak memory 208832 kb
Host smart-08f7f1bc-a753-486c-8a08-dc0cbecc04bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908279380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1908279380
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3698690483
Short name T60
Test name
Test status
Simulation time 21021770145 ps
CPU time 172.04 seconds
Started Aug 15 05:10:41 PM PDT 24
Finished Aug 15 05:13:34 PM PDT 24
Peak memory 300088 kb
Host smart-8fbc81e8-17e8-4b74-a5e1-0acea57a583e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698690483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3698690483
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2497008038
Short name T19
Test name
Test status
Simulation time 294575469 ps
CPU time 3.43 seconds
Started Aug 15 05:09:17 PM PDT 24
Finished Aug 15 05:09:20 PM PDT 24
Peak memory 221848 kb
Host smart-ba76588f-1c15-4532-ae4c-5939eaffc37d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497008038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2497008038
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3583219934
Short name T127
Test name
Test status
Simulation time 118814142 ps
CPU time 4.4 seconds
Started Aug 15 05:04:55 PM PDT 24
Finished Aug 15 05:05:00 PM PDT 24
Peak memory 218320 kb
Host smart-14238bb3-bbd7-45ec-8ee5-1349ca0ce9d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583219934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3583219934
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2155528893
Short name T125
Test name
Test status
Simulation time 204947096 ps
CPU time 2.83 seconds
Started Aug 15 05:06:23 PM PDT 24
Finished Aug 15 05:06:26 PM PDT 24
Peak memory 222784 kb
Host smart-2b0e822b-9415-4eb2-9756-a9d4657d94b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155528893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2155528893
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.4150733835
Short name T137
Test name
Test status
Simulation time 126423150 ps
CPU time 2.13 seconds
Started Aug 15 05:05:20 PM PDT 24
Finished Aug 15 05:05:23 PM PDT 24
Peak memory 222740 kb
Host smart-1dcb84e4-da4f-48da-b908-bd239898cb08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150733835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.4150733835
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.167279922
Short name T122
Test name
Test status
Simulation time 182012292 ps
CPU time 1.8 seconds
Started Aug 15 05:05:57 PM PDT 24
Finished Aug 15 05:05:59 PM PDT 24
Peak memory 222500 kb
Host smart-e075cb81-4d17-4c33-9d60-0ee881ff715c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167279922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.167279922
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1894128933
Short name T42
Test name
Test status
Simulation time 1332818187 ps
CPU time 44.3 seconds
Started Aug 15 05:07:22 PM PDT 24
Finished Aug 15 05:08:06 PM PDT 24
Peak memory 218928 kb
Host smart-366098a7-9a05-4ca5-b162-0a97e246acb6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894128933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1894128933
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1261389236
Short name T43
Test name
Test status
Simulation time 1107781724 ps
CPU time 9.41 seconds
Started Aug 15 05:10:28 PM PDT 24
Finished Aug 15 05:10:38 PM PDT 24
Peak memory 218348 kb
Host smart-ea02ee99-b240-4bd2-959a-d8822bacd62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261389236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1261389236
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3378074013
Short name T16
Test name
Test status
Simulation time 611909000 ps
CPU time 9.75 seconds
Started Aug 15 05:09:43 PM PDT 24
Finished Aug 15 05:09:53 PM PDT 24
Peak memory 226076 kb
Host smart-f0d0b737-30c7-4362-be1e-72342bb82268
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378074013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3378074013
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1941278499
Short name T991
Test name
Test status
Simulation time 35355594 ps
CPU time 1.69 seconds
Started Aug 15 05:05:04 PM PDT 24
Finished Aug 15 05:05:05 PM PDT 24
Peak memory 210156 kb
Host smart-e7062644-11e5-454b-9189-f81bf14f3f0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941278499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1941278499
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.49241937
Short name T160
Test name
Test status
Simulation time 96334642 ps
CPU time 3.23 seconds
Started Aug 15 05:05:04 PM PDT 24
Finished Aug 15 05:05:07 PM PDT 24
Peak memory 209912 kb
Host smart-241b32ee-d573-4ca1-9923-0278edb25f15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49241937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash.49241937
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2475257306
Short name T192
Test name
Test status
Simulation time 50203809 ps
CPU time 0.92 seconds
Started Aug 15 05:05:01 PM PDT 24
Finished Aug 15 05:05:02 PM PDT 24
Peak memory 210420 kb
Host smart-3b8eda4a-3281-4b80-9213-0e07bf89cd15
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475257306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2475257306
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3888911401
Short name T935
Test name
Test status
Simulation time 59712443 ps
CPU time 0.88 seconds
Started Aug 15 05:05:00 PM PDT 24
Finished Aug 15 05:05:01 PM PDT 24
Peak memory 208900 kb
Host smart-5a41891c-10ce-4980-b468-7b7933d9cfdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888911401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3888911401
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3331841514
Short name T956
Test name
Test status
Simulation time 222181855 ps
CPU time 1.18 seconds
Started Aug 15 05:04:52 PM PDT 24
Finished Aug 15 05:04:53 PM PDT 24
Peak memory 208692 kb
Host smart-d05130df-c91f-4f00-9c6d-db2573b08520
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331841514 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3331841514
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1863481358
Short name T886
Test name
Test status
Simulation time 873486680 ps
CPU time 5.47 seconds
Started Aug 15 05:04:53 PM PDT 24
Finished Aug 15 05:04:58 PM PDT 24
Peak memory 209848 kb
Host smart-d80beae4-a16d-4d2d-92ca-db643270ec84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863481358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1863481358
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1507310205
Short name T928
Test name
Test status
Simulation time 12346432005 ps
CPU time 20.3 seconds
Started Aug 15 05:04:52 PM PDT 24
Finished Aug 15 05:05:13 PM PDT 24
Peak memory 210184 kb
Host smart-ad6d1be9-ee9e-4075-95ac-b60db4287180
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507310205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1507310205
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.445850939
Short name T978
Test name
Test status
Simulation time 159338838 ps
CPU time 1.76 seconds
Started Aug 15 05:04:55 PM PDT 24
Finished Aug 15 05:04:57 PM PDT 24
Peak memory 211868 kb
Host smart-432ab03b-5468-441c-bd01-e70bfb1b66d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445850939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.445850939
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3622490208
Short name T946
Test name
Test status
Simulation time 58042274 ps
CPU time 1.48 seconds
Started Aug 15 05:04:55 PM PDT 24
Finished Aug 15 05:04:57 PM PDT 24
Peak memory 218376 kb
Host smart-4a425dfc-bdf6-4236-8398-8f19ad315114
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362249
0208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3622490208
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4099337581
Short name T999
Test name
Test status
Simulation time 127503429 ps
CPU time 1.06 seconds
Started Aug 15 05:04:53 PM PDT 24
Finished Aug 15 05:04:54 PM PDT 24
Peak memory 210016 kb
Host smart-dffccdc1-2b48-4295-b149-7811275d015b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099337581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.4099337581
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3737820268
Short name T918
Test name
Test status
Simulation time 322043168 ps
CPU time 1.31 seconds
Started Aug 15 05:05:01 PM PDT 24
Finished Aug 15 05:05:03 PM PDT 24
Peak memory 209792 kb
Host smart-4c179c60-79dc-4f8c-b4a6-8db71d0e7729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737820268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3737820268
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2262905775
Short name T908
Test name
Test status
Simulation time 96049049 ps
CPU time 4.25 seconds
Started Aug 15 05:04:53 PM PDT 24
Finished Aug 15 05:04:57 PM PDT 24
Peak memory 218264 kb
Host smart-05325c27-f8ce-4705-8258-89a26d0a9b10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262905775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2262905775
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3824835347
Short name T196
Test name
Test status
Simulation time 20126541 ps
CPU time 1.4 seconds
Started Aug 15 05:05:21 PM PDT 24
Finished Aug 15 05:05:22 PM PDT 24
Peak memory 210120 kb
Host smart-1147529c-011c-45f7-964f-304e5d8fc4d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824835347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3824835347
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.727167094
Short name T895
Test name
Test status
Simulation time 161914544 ps
CPU time 1.83 seconds
Started Aug 15 05:05:17 PM PDT 24
Finished Aug 15 05:05:19 PM PDT 24
Peak memory 209060 kb
Host smart-18e34a52-6da5-49b9-9c2e-6e9206c37576
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727167094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.727167094
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3762353
Short name T200
Test name
Test status
Simulation time 69427059 ps
CPU time 1.17 seconds
Started Aug 15 05:05:19 PM PDT 24
Finished Aug 15 05:05:20 PM PDT 24
Peak memory 212444 kb
Host smart-baa761ab-f0ce-48f7-9820-066457cd27f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset.3762353
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3918489270
Short name T975
Test name
Test status
Simulation time 109387425 ps
CPU time 0.98 seconds
Started Aug 15 05:05:18 PM PDT 24
Finished Aug 15 05:05:19 PM PDT 24
Peak memory 218320 kb
Host smart-04d10e47-f45b-4633-bd1f-0aa2b1bda311
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918489270 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3918489270
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3527261783
Short name T980
Test name
Test status
Simulation time 15123559 ps
CPU time 1.02 seconds
Started Aug 15 05:05:19 PM PDT 24
Finished Aug 15 05:05:20 PM PDT 24
Peak memory 209888 kb
Host smart-28237949-5851-4d9f-935c-ce41d35edc8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527261783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3527261783
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1159299878
Short name T993
Test name
Test status
Simulation time 71501890 ps
CPU time 2.25 seconds
Started Aug 15 05:05:09 PM PDT 24
Finished Aug 15 05:05:12 PM PDT 24
Peak memory 210088 kb
Host smart-f3bd23c4-3bda-4349-8dde-4c8f60983cd3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159299878 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1159299878
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1026330092
Short name T957
Test name
Test status
Simulation time 857174977 ps
CPU time 5.68 seconds
Started Aug 15 05:05:10 PM PDT 24
Finished Aug 15 05:05:16 PM PDT 24
Peak memory 209356 kb
Host smart-9c0b6a9a-4fd7-4dc8-9638-b0101ec088c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026330092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1026330092
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.938235456
Short name T884
Test name
Test status
Simulation time 2594646546 ps
CPU time 25.13 seconds
Started Aug 15 05:05:09 PM PDT 24
Finished Aug 15 05:05:35 PM PDT 24
Peak memory 210220 kb
Host smart-d6b8027b-7b80-468a-94d7-c9394050ef1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938235456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.938235456
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1660560189
Short name T953
Test name
Test status
Simulation time 136235166 ps
CPU time 2.53 seconds
Started Aug 15 05:05:10 PM PDT 24
Finished Aug 15 05:05:13 PM PDT 24
Peak memory 211624 kb
Host smart-1bdf6672-b7fe-4d9b-9603-d2f85ca7f61e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660560189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1660560189
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3810832454
Short name T931
Test name
Test status
Simulation time 1905580758 ps
CPU time 3.04 seconds
Started Aug 15 05:05:10 PM PDT 24
Finished Aug 15 05:05:13 PM PDT 24
Peak memory 218212 kb
Host smart-934eef17-457c-4f89-9a1b-f8013aeba288
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381083
2454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3810832454
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3690759662
Short name T115
Test name
Test status
Simulation time 105343085 ps
CPU time 1.58 seconds
Started Aug 15 05:05:09 PM PDT 24
Finished Aug 15 05:05:11 PM PDT 24
Peak memory 210072 kb
Host smart-4781f114-f8a6-4c68-a764-638e3868d302
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690759662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3690759662
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3908183884
Short name T117
Test name
Test status
Simulation time 92068313 ps
CPU time 1.38 seconds
Started Aug 15 05:05:08 PM PDT 24
Finished Aug 15 05:05:10 PM PDT 24
Peak memory 218328 kb
Host smart-9242ee8d-f890-45d5-9e69-5088be964156
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908183884 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3908183884
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.4013778258
Short name T892
Test name
Test status
Simulation time 41866597 ps
CPU time 1.4 seconds
Started Aug 15 05:05:19 PM PDT 24
Finished Aug 15 05:05:20 PM PDT 24
Peak memory 209836 kb
Host smart-3b22a0f9-aea2-4c23-b217-3c6c93bd8d92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013778258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.4013778258
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1461249523
Short name T990
Test name
Test status
Simulation time 155404536 ps
CPU time 5.76 seconds
Started Aug 15 05:05:17 PM PDT 24
Finished Aug 15 05:05:23 PM PDT 24
Peak memory 218304 kb
Host smart-89abe1c4-acc5-4b5a-89af-91a0c53a856b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461249523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1461249523
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3969669245
Short name T185
Test name
Test status
Simulation time 2119488052 ps
CPU time 4.04 seconds
Started Aug 15 05:05:18 PM PDT 24
Finished Aug 15 05:05:22 PM PDT 24
Peak memory 218216 kb
Host smart-42f6d896-80c0-401a-9f5c-078b28ce18f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969669245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3969669245
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.950178929
Short name T114
Test name
Test status
Simulation time 15828918 ps
CPU time 1.05 seconds
Started Aug 15 05:06:14 PM PDT 24
Finished Aug 15 05:06:15 PM PDT 24
Peak memory 218360 kb
Host smart-21cbba0f-8c0f-4ccd-838c-32d7b1b4de5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950178929 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.950178929
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.182835982
Short name T190
Test name
Test status
Simulation time 31241807 ps
CPU time 0.98 seconds
Started Aug 15 05:06:11 PM PDT 24
Finished Aug 15 05:06:13 PM PDT 24
Peak memory 210120 kb
Host smart-cedf95c3-cdd9-4539-af7d-147894d2d34f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182835982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.182835982
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3759034065
Short name T913
Test name
Test status
Simulation time 88743888 ps
CPU time 1.22 seconds
Started Aug 15 05:06:16 PM PDT 24
Finished Aug 15 05:06:17 PM PDT 24
Peak memory 210080 kb
Host smart-7fc851a3-98d8-4a14-bafc-3064d5506748
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759034065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3759034065
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3560954247
Short name T985
Test name
Test status
Simulation time 939725795 ps
CPU time 2.15 seconds
Started Aug 15 05:06:09 PM PDT 24
Finished Aug 15 05:06:12 PM PDT 24
Peak memory 218320 kb
Host smart-2ffa62e1-ca19-4331-88df-c7052d3f351e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560954247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3560954247
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3369652138
Short name T128
Test name
Test status
Simulation time 252483515 ps
CPU time 3.88 seconds
Started Aug 15 05:06:10 PM PDT 24
Finished Aug 15 05:06:14 PM PDT 24
Peak memory 218308 kb
Host smart-6727d8c6-3ac3-4b00-9996-88aef1c69b4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369652138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3369652138
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.310887388
Short name T155
Test name
Test status
Simulation time 32885939 ps
CPU time 1.76 seconds
Started Aug 15 05:06:12 PM PDT 24
Finished Aug 15 05:06:14 PM PDT 24
Peak memory 218288 kb
Host smart-b55589a9-d414-49dc-b022-59cac9345190
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310887388 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.310887388
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.878243721
Short name T195
Test name
Test status
Simulation time 23556652 ps
CPU time 1.04 seconds
Started Aug 15 05:06:13 PM PDT 24
Finished Aug 15 05:06:14 PM PDT 24
Peak memory 210024 kb
Host smart-404ffef7-8661-4500-b4c5-9e3360b93c39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878243721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.878243721
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1040627851
Short name T140
Test name
Test status
Simulation time 345359936 ps
CPU time 1.46 seconds
Started Aug 15 05:06:11 PM PDT 24
Finished Aug 15 05:06:12 PM PDT 24
Peak memory 212252 kb
Host smart-a1985a93-a2e7-40de-a87c-b2942b9711e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040627851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1040627851
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1615576959
Short name T120
Test name
Test status
Simulation time 91585930 ps
CPU time 2.14 seconds
Started Aug 15 05:06:14 PM PDT 24
Finished Aug 15 05:06:16 PM PDT 24
Peak memory 218356 kb
Host smart-835d86f2-740f-4687-9deb-542938e230f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615576959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1615576959
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1870340042
Short name T126
Test name
Test status
Simulation time 147921224 ps
CPU time 2.3 seconds
Started Aug 15 05:06:13 PM PDT 24
Finished Aug 15 05:06:16 PM PDT 24
Peak memory 218304 kb
Host smart-3b59832a-b963-4e8b-a66c-4502268bc87c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870340042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1870340042
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3540542966
Short name T905
Test name
Test status
Simulation time 80946809 ps
CPU time 1.11 seconds
Started Aug 15 05:06:21 PM PDT 24
Finished Aug 15 05:06:22 PM PDT 24
Peak memory 219460 kb
Host smart-7c1670f4-bc4f-49f5-b0b5-4b2d753c088d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540542966 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3540542966
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2493855445
Short name T116
Test name
Test status
Simulation time 30700627 ps
CPU time 0.95 seconds
Started Aug 15 05:06:14 PM PDT 24
Finished Aug 15 05:06:16 PM PDT 24
Peak memory 210088 kb
Host smart-cffcc3c0-c8b8-4d26-911c-410874c48961
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493855445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2493855445
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4246075355
Short name T937
Test name
Test status
Simulation time 19036781 ps
CPU time 1.45 seconds
Started Aug 15 05:06:10 PM PDT 24
Finished Aug 15 05:06:12 PM PDT 24
Peak memory 209956 kb
Host smart-0f2d0a42-f0ff-42c9-84f7-740bbcf4c910
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246075355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.4246075355
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2686629607
Short name T926
Test name
Test status
Simulation time 117410944 ps
CPU time 2.3 seconds
Started Aug 15 05:06:12 PM PDT 24
Finished Aug 15 05:06:14 PM PDT 24
Peak memory 218424 kb
Host smart-cb47c20d-cb3c-4825-92f4-6a8cd9ef8c67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686629607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2686629607
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2356093576
Short name T136
Test name
Test status
Simulation time 77161097 ps
CPU time 1.85 seconds
Started Aug 15 05:06:14 PM PDT 24
Finished Aug 15 05:06:16 PM PDT 24
Peak memory 218316 kb
Host smart-c0f0c865-0d84-4118-b1f9-d7e9aa284509
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356093576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2356093576
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.329728286
Short name T952
Test name
Test status
Simulation time 30729433 ps
CPU time 2.31 seconds
Started Aug 15 05:06:20 PM PDT 24
Finished Aug 15 05:06:23 PM PDT 24
Peak memory 226428 kb
Host smart-616d2b4d-7483-4223-82a0-2725c0484baf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329728286 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.329728286
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2647243187
Short name T193
Test name
Test status
Simulation time 17083064 ps
CPU time 1.17 seconds
Started Aug 15 05:06:20 PM PDT 24
Finished Aug 15 05:06:21 PM PDT 24
Peak memory 209844 kb
Host smart-69288393-2169-40aa-b5fb-cbc968c41077
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647243187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2647243187
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3098346375
Short name T968
Test name
Test status
Simulation time 21317376 ps
CPU time 1.56 seconds
Started Aug 15 05:06:20 PM PDT 24
Finished Aug 15 05:06:22 PM PDT 24
Peak memory 212320 kb
Host smart-37e9830b-ce96-44d9-a0be-e589cb22d293
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098346375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3098346375
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2597019087
Short name T933
Test name
Test status
Simulation time 47487430 ps
CPU time 1.72 seconds
Started Aug 15 05:06:21 PM PDT 24
Finished Aug 15 05:06:23 PM PDT 24
Peak memory 218288 kb
Host smart-f8f2b303-d20c-4b66-ab8e-5393e7cc9e39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597019087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2597019087
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1112649624
Short name T915
Test name
Test status
Simulation time 29055019 ps
CPU time 1.39 seconds
Started Aug 15 05:06:20 PM PDT 24
Finished Aug 15 05:06:21 PM PDT 24
Peak memory 219952 kb
Host smart-4645038f-ddaa-41be-86a3-3b55101b66c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112649624 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1112649624
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2978672502
Short name T934
Test name
Test status
Simulation time 14253594 ps
CPU time 0.91 seconds
Started Aug 15 05:06:20 PM PDT 24
Finished Aug 15 05:06:22 PM PDT 24
Peak memory 210108 kb
Host smart-fb84d15d-889a-4a48-9b4a-609b29527279
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978672502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2978672502
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1353068403
Short name T157
Test name
Test status
Simulation time 44106263 ps
CPU time 1.39 seconds
Started Aug 15 05:06:20 PM PDT 24
Finished Aug 15 05:06:22 PM PDT 24
Peak memory 210032 kb
Host smart-de86f742-4842-49d0-9dee-a58561b8b1d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353068403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1353068403
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3589683723
Short name T925
Test name
Test status
Simulation time 37040368 ps
CPU time 2.89 seconds
Started Aug 15 05:06:19 PM PDT 24
Finished Aug 15 05:06:22 PM PDT 24
Peak memory 218436 kb
Host smart-140d85bd-828d-4b8e-ad57-a138aa7be53f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589683723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3589683723
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3616910287
Short name T960
Test name
Test status
Simulation time 24484442 ps
CPU time 1.19 seconds
Started Aug 15 05:06:22 PM PDT 24
Finished Aug 15 05:06:23 PM PDT 24
Peak memory 218380 kb
Host smart-4e10651a-99de-458f-9b17-d60ed110561d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616910287 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3616910287
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1250190825
Short name T996
Test name
Test status
Simulation time 55693945 ps
CPU time 0.88 seconds
Started Aug 15 05:06:20 PM PDT 24
Finished Aug 15 05:06:21 PM PDT 24
Peak memory 209836 kb
Host smart-c76c958c-9af9-4d65-a23c-d4ae0e92a0da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250190825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1250190825
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1419373532
Short name T882
Test name
Test status
Simulation time 126338993 ps
CPU time 1.61 seconds
Started Aug 15 05:06:22 PM PDT 24
Finished Aug 15 05:06:24 PM PDT 24
Peak memory 210276 kb
Host smart-6644f7bf-1037-4625-a234-801bae0ca280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419373532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1419373532
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.925395315
Short name T950
Test name
Test status
Simulation time 545987199 ps
CPU time 4.8 seconds
Started Aug 15 05:06:19 PM PDT 24
Finished Aug 15 05:06:24 PM PDT 24
Peak memory 218216 kb
Host smart-aebd884e-7f98-418b-a118-b7462dae213b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925395315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.925395315
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2853541470
Short name T113
Test name
Test status
Simulation time 183639932 ps
CPU time 2.06 seconds
Started Aug 15 05:06:20 PM PDT 24
Finished Aug 15 05:06:22 PM PDT 24
Peak memory 222828 kb
Host smart-b5bcf5dd-bba9-423d-8afe-29d9cacbab5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853541470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2853541470
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3082920102
Short name T890
Test name
Test status
Simulation time 32139684 ps
CPU time 1.24 seconds
Started Aug 15 05:06:23 PM PDT 24
Finished Aug 15 05:06:24 PM PDT 24
Peak memory 218436 kb
Host smart-5c277f92-129a-46d7-81ea-02d489db8728
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082920102 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3082920102
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2195511413
Short name T967
Test name
Test status
Simulation time 45869003 ps
CPU time 0.85 seconds
Started Aug 15 05:06:20 PM PDT 24
Finished Aug 15 05:06:21 PM PDT 24
Peak memory 209876 kb
Host smart-ce792b74-f66d-4495-b403-79321266149b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195511413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2195511413
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2539141024
Short name T917
Test name
Test status
Simulation time 96840268 ps
CPU time 1.31 seconds
Started Aug 15 05:06:20 PM PDT 24
Finished Aug 15 05:06:21 PM PDT 24
Peak memory 218328 kb
Host smart-6017abc4-c552-449b-8a60-88ae7aeebeab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539141024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2539141024
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3752811902
Short name T997
Test name
Test status
Simulation time 251093637 ps
CPU time 2.14 seconds
Started Aug 15 05:06:20 PM PDT 24
Finished Aug 15 05:06:22 PM PDT 24
Peak memory 218536 kb
Host smart-489892fc-9332-475b-94aa-87a45c2723f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752811902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3752811902
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1995255278
Short name T912
Test name
Test status
Simulation time 22243655 ps
CPU time 0.91 seconds
Started Aug 15 05:06:20 PM PDT 24
Finished Aug 15 05:06:21 PM PDT 24
Peak memory 218240 kb
Host smart-98a7ad9d-8f5b-4e16-bd65-31d0bf2db24a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995255278 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1995255278
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2331889728
Short name T189
Test name
Test status
Simulation time 15415327 ps
CPU time 0.95 seconds
Started Aug 15 05:06:20 PM PDT 24
Finished Aug 15 05:06:21 PM PDT 24
Peak memory 209984 kb
Host smart-539d3072-adb6-462d-9b54-815d5f3aa0c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331889728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2331889728
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1321421881
Short name T891
Test name
Test status
Simulation time 19446719 ps
CPU time 1.23 seconds
Started Aug 15 05:06:19 PM PDT 24
Finished Aug 15 05:06:21 PM PDT 24
Peak memory 210084 kb
Host smart-9f2c1387-63f5-415d-83a1-690a1e74ef32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321421881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1321421881
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.400776
Short name T911
Test name
Test status
Simulation time 101260407 ps
CPU time 1.5 seconds
Started Aug 15 05:06:26 PM PDT 24
Finished Aug 15 05:06:28 PM PDT 24
Peak memory 218452 kb
Host smart-2b2cd66b-a5df-4ec2-840d-bdba97c7acd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400776 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.400776
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2818053079
Short name T875
Test name
Test status
Simulation time 12989785 ps
CPU time 0.83 seconds
Started Aug 15 05:06:28 PM PDT 24
Finished Aug 15 05:06:29 PM PDT 24
Peak memory 209888 kb
Host smart-e17ea2c5-1e3d-4f7a-9d15-14ee6627edf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818053079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2818053079
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2549753527
Short name T921
Test name
Test status
Simulation time 21036916 ps
CPU time 1.5 seconds
Started Aug 15 05:06:28 PM PDT 24
Finished Aug 15 05:06:30 PM PDT 24
Peak memory 210212 kb
Host smart-ed04a136-205d-45f0-abea-f1a613b75344
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549753527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2549753527
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.451772634
Short name T929
Test name
Test status
Simulation time 399236481 ps
CPU time 4.72 seconds
Started Aug 15 05:06:22 PM PDT 24
Finished Aug 15 05:06:26 PM PDT 24
Peak memory 218288 kb
Host smart-93af5545-4403-461e-b95b-d0a533beed86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451772634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.451772634
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2593123916
Short name T900
Test name
Test status
Simulation time 53529223 ps
CPU time 1.17 seconds
Started Aug 15 05:06:28 PM PDT 24
Finished Aug 15 05:06:29 PM PDT 24
Peak memory 218284 kb
Host smart-422180f1-b2a2-4513-8d0d-54fab548f82f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593123916 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2593123916
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2134137298
Short name T932
Test name
Test status
Simulation time 30834369 ps
CPU time 0.86 seconds
Started Aug 15 05:06:29 PM PDT 24
Finished Aug 15 05:06:30 PM PDT 24
Peak memory 209948 kb
Host smart-57bccb76-37b7-4bcd-825e-d6d69101602e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134137298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2134137298
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2149737049
Short name T887
Test name
Test status
Simulation time 49882130 ps
CPU time 1.46 seconds
Started Aug 15 05:06:27 PM PDT 24
Finished Aug 15 05:06:28 PM PDT 24
Peak memory 212088 kb
Host smart-ad085287-781b-4328-8139-5a62b94a830a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149737049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2149737049
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3303377373
Short name T907
Test name
Test status
Simulation time 167512122 ps
CPU time 3.53 seconds
Started Aug 15 05:06:29 PM PDT 24
Finished Aug 15 05:06:33 PM PDT 24
Peak memory 218256 kb
Host smart-5a0aa1f5-4666-4226-bc06-8730a4b43c00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303377373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3303377373
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1504206990
Short name T901
Test name
Test status
Simulation time 27771475 ps
CPU time 1.94 seconds
Started Aug 15 05:05:26 PM PDT 24
Finished Aug 15 05:05:28 PM PDT 24
Peak memory 209356 kb
Host smart-4fe24c98-c37b-4ba5-a260-0907e986986c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504206990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1504206990
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.548454605
Short name T920
Test name
Test status
Simulation time 68135897 ps
CPU time 1.11 seconds
Started Aug 15 05:05:26 PM PDT 24
Finished Aug 15 05:05:27 PM PDT 24
Peak memory 219872 kb
Host smart-32237cbb-fb3b-48b0-96ca-d3b60124c1db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548454605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.548454605
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1576725687
Short name T121
Test name
Test status
Simulation time 38034469 ps
CPU time 1.18 seconds
Started Aug 15 05:05:27 PM PDT 24
Finished Aug 15 05:05:28 PM PDT 24
Peak memory 218340 kb
Host smart-92ef830d-c62d-4960-bfec-6e78570f293f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576725687 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1576725687
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.123770805
Short name T194
Test name
Test status
Simulation time 20384471 ps
CPU time 0.87 seconds
Started Aug 15 05:05:26 PM PDT 24
Finished Aug 15 05:05:27 PM PDT 24
Peak memory 210108 kb
Host smart-96db06df-26ba-4c40-9f9f-c8f41190097b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123770805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.123770805
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3825173282
Short name T981
Test name
Test status
Simulation time 64917858 ps
CPU time 1.27 seconds
Started Aug 15 05:05:19 PM PDT 24
Finished Aug 15 05:05:21 PM PDT 24
Peak memory 210100 kb
Host smart-a9346a23-afdd-424a-822d-0f26f4e0b74c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825173282 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3825173282
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2904288771
Short name T883
Test name
Test status
Simulation time 2421987728 ps
CPU time 11.29 seconds
Started Aug 15 05:05:17 PM PDT 24
Finished Aug 15 05:05:29 PM PDT 24
Peak memory 210084 kb
Host smart-b740a267-c203-47ea-8a76-94669aa65f0d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904288771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2904288771
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2454038711
Short name T893
Test name
Test status
Simulation time 898987441 ps
CPU time 8.04 seconds
Started Aug 15 05:05:18 PM PDT 24
Finished Aug 15 05:05:26 PM PDT 24
Peak memory 209916 kb
Host smart-6840a53e-1f89-471a-8520-db59ab489cb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454038711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2454038711
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2271798047
Short name T914
Test name
Test status
Simulation time 170085730 ps
CPU time 1.22 seconds
Started Aug 15 05:05:19 PM PDT 24
Finished Aug 15 05:05:20 PM PDT 24
Peak memory 211500 kb
Host smart-85999d22-e7c4-4aac-ac64-82ceebe8ae81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271798047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2271798047
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1130173301
Short name T989
Test name
Test status
Simulation time 102342051 ps
CPU time 1.74 seconds
Started Aug 15 05:05:20 PM PDT 24
Finished Aug 15 05:05:22 PM PDT 24
Peak memory 210080 kb
Host smart-67c353d0-4015-42b6-8094-6f69aa6bfa6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130173301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1130173301
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2032287683
Short name T888
Test name
Test status
Simulation time 37129331 ps
CPU time 1.77 seconds
Started Aug 15 05:05:17 PM PDT 24
Finished Aug 15 05:05:19 PM PDT 24
Peak memory 218204 kb
Host smart-67addb34-2a49-4e0d-9230-dcd1b923f36f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032287683 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2032287683
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.86843672
Short name T944
Test name
Test status
Simulation time 14878168 ps
CPU time 1 seconds
Started Aug 15 05:05:28 PM PDT 24
Finished Aug 15 05:05:29 PM PDT 24
Peak memory 218332 kb
Host smart-f4551c7a-7a16-4f9c-b839-899ae13c79bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86843672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_s
ame_csr_outstanding.86843672
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1883359295
Short name T994
Test name
Test status
Simulation time 127909455 ps
CPU time 3.14 seconds
Started Aug 15 05:05:18 PM PDT 24
Finished Aug 15 05:05:22 PM PDT 24
Peak memory 218224 kb
Host smart-44353cec-83b9-44ae-8d97-88c4f04e2fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883359295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1883359295
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.609878076
Short name T948
Test name
Test status
Simulation time 23288906 ps
CPU time 1.1 seconds
Started Aug 15 05:05:36 PM PDT 24
Finished Aug 15 05:05:38 PM PDT 24
Peak memory 210040 kb
Host smart-54329677-54bd-4d8b-b627-fa4a3955d9e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609878076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.609878076
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2454000929
Short name T897
Test name
Test status
Simulation time 98086385 ps
CPU time 1.51 seconds
Started Aug 15 05:05:36 PM PDT 24
Finished Aug 15 05:05:37 PM PDT 24
Peak memory 210004 kb
Host smart-4a61cb09-004a-47d1-a3a9-5ce8d8160821
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454000929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2454000929
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3140180866
Short name T199
Test name
Test status
Simulation time 87261547 ps
CPU time 1.17 seconds
Started Aug 15 05:05:37 PM PDT 24
Finished Aug 15 05:05:39 PM PDT 24
Peak memory 211912 kb
Host smart-5a8b64f8-9967-46fc-a4c0-4d02d0956b7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140180866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3140180866
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3468871685
Short name T941
Test name
Test status
Simulation time 24863328 ps
CPU time 1.73 seconds
Started Aug 15 05:05:36 PM PDT 24
Finished Aug 15 05:05:37 PM PDT 24
Peak memory 218480 kb
Host smart-8d008f5f-151a-4df2-bdc3-1f8999d32823
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468871685 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3468871685
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.743044941
Short name T982
Test name
Test status
Simulation time 93972145 ps
CPU time 1.05 seconds
Started Aug 15 05:05:37 PM PDT 24
Finished Aug 15 05:05:38 PM PDT 24
Peak memory 210060 kb
Host smart-8c2eb436-bc97-4c18-84e9-4ba857fc06fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743044941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.743044941
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.784089139
Short name T899
Test name
Test status
Simulation time 88275254 ps
CPU time 0.93 seconds
Started Aug 15 05:05:37 PM PDT 24
Finished Aug 15 05:05:38 PM PDT 24
Peak memory 210032 kb
Host smart-f22b603e-6b50-49ee-a168-3b155e64ba05
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784089139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.784089139
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.833683987
Short name T969
Test name
Test status
Simulation time 445453837 ps
CPU time 6.73 seconds
Started Aug 15 05:05:27 PM PDT 24
Finished Aug 15 05:05:33 PM PDT 24
Peak memory 209844 kb
Host smart-5e2b51f5-0374-4e5c-aaf8-d6e8d19f8372
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833683987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.833683987
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1691397726
Short name T942
Test name
Test status
Simulation time 839238116 ps
CPU time 9.66 seconds
Started Aug 15 05:05:28 PM PDT 24
Finished Aug 15 05:05:38 PM PDT 24
Peak memory 209916 kb
Host smart-a7a5cb5c-b74b-4142-a867-19b570114c30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691397726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1691397726
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1804808764
Short name T961
Test name
Test status
Simulation time 129799025 ps
CPU time 3.54 seconds
Started Aug 15 05:05:27 PM PDT 24
Finished Aug 15 05:05:31 PM PDT 24
Peak memory 211604 kb
Host smart-a3506aed-f277-42f0-b220-ff2c79f8cf96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804808764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1804808764
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1286120575
Short name T962
Test name
Test status
Simulation time 977829332 ps
CPU time 1.87 seconds
Started Aug 15 05:05:36 PM PDT 24
Finished Aug 15 05:05:38 PM PDT 24
Peak memory 219520 kb
Host smart-0990dd45-d832-4cac-b651-e592a80d5f22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128612
0575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1286120575
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4186220095
Short name T963
Test name
Test status
Simulation time 118903807 ps
CPU time 3.29 seconds
Started Aug 15 05:05:27 PM PDT 24
Finished Aug 15 05:05:30 PM PDT 24
Peak memory 210036 kb
Host smart-c06acbc9-bfcb-49ab-a8f5-8a9e2f50a2b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186220095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.4186220095
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1690387927
Short name T202
Test name
Test status
Simulation time 40262690 ps
CPU time 1.04 seconds
Started Aug 15 05:05:27 PM PDT 24
Finished Aug 15 05:05:28 PM PDT 24
Peak memory 218244 kb
Host smart-4ae3fe56-a376-4a5a-903f-e953abbdb87d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690387927 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1690387927
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.506508621
Short name T156
Test name
Test status
Simulation time 49445743 ps
CPU time 1.48 seconds
Started Aug 15 05:05:38 PM PDT 24
Finished Aug 15 05:05:39 PM PDT 24
Peak memory 210096 kb
Host smart-1dc86264-db42-4ac7-b96a-c84edb181e31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506508621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.506508621
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.195680734
Short name T939
Test name
Test status
Simulation time 358240156 ps
CPU time 2.05 seconds
Started Aug 15 05:05:36 PM PDT 24
Finished Aug 15 05:05:38 PM PDT 24
Peak memory 218252 kb
Host smart-87ad3abb-ef2f-4484-98f5-78a84f0bb97d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195680734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.195680734
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.703376750
Short name T197
Test name
Test status
Simulation time 40418553 ps
CPU time 1.36 seconds
Started Aug 15 05:05:46 PM PDT 24
Finished Aug 15 05:05:47 PM PDT 24
Peak memory 209988 kb
Host smart-5378e6d8-7862-4895-a06e-c545e976fee6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703376750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.703376750
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4028536842
Short name T879
Test name
Test status
Simulation time 72275914 ps
CPU time 1.81 seconds
Started Aug 15 05:05:49 PM PDT 24
Finished Aug 15 05:05:51 PM PDT 24
Peak memory 210056 kb
Host smart-e94f54e7-037e-4205-ab66-e675cdb366e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028536842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.4028536842
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.280013237
Short name T198
Test name
Test status
Simulation time 11815517 ps
CPU time 0.98 seconds
Started Aug 15 05:05:45 PM PDT 24
Finished Aug 15 05:05:47 PM PDT 24
Peak memory 210020 kb
Host smart-f9cbaeb4-d348-4237-8fd9-e3370aa5cdaf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280013237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.280013237
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1585245104
Short name T979
Test name
Test status
Simulation time 81414148 ps
CPU time 1.46 seconds
Started Aug 15 05:05:47 PM PDT 24
Finished Aug 15 05:05:49 PM PDT 24
Peak memory 218344 kb
Host smart-3c3143e7-a1fc-4d79-9b7b-1d130dcac39f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585245104 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1585245104
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3995110211
Short name T162
Test name
Test status
Simulation time 58210384 ps
CPU time 0.94 seconds
Started Aug 15 05:05:48 PM PDT 24
Finished Aug 15 05:05:49 PM PDT 24
Peak memory 210048 kb
Host smart-e97f17bc-1fe2-4ba3-b0d1-78c0b408873d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995110211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3995110211
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3590040969
Short name T972
Test name
Test status
Simulation time 59607429 ps
CPU time 1.15 seconds
Started Aug 15 05:05:37 PM PDT 24
Finished Aug 15 05:05:38 PM PDT 24
Peak memory 208696 kb
Host smart-751d4dcc-b1e3-468e-81a4-5ef482e803d4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590040969 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3590040969
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.322878623
Short name T141
Test name
Test status
Simulation time 2883841756 ps
CPU time 10.77 seconds
Started Aug 15 05:05:35 PM PDT 24
Finished Aug 15 05:05:46 PM PDT 24
Peak memory 210220 kb
Host smart-f9afd691-bb50-4156-a7d1-fe8961a77bd9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322878623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.322878623
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.902964865
Short name T974
Test name
Test status
Simulation time 11375875788 ps
CPU time 58.24 seconds
Started Aug 15 05:05:36 PM PDT 24
Finished Aug 15 05:06:34 PM PDT 24
Peak memory 210176 kb
Host smart-9a628538-b6a6-4e89-82fb-1852d991fdd7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902964865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.902964865
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2087137717
Short name T896
Test name
Test status
Simulation time 226916193 ps
CPU time 2.94 seconds
Started Aug 15 05:05:36 PM PDT 24
Finished Aug 15 05:05:39 PM PDT 24
Peak memory 211672 kb
Host smart-9aea2efa-bc9e-49e3-b58b-3162092c2834
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087137717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2087137717
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.113892099
Short name T134
Test name
Test status
Simulation time 150997989 ps
CPU time 2.62 seconds
Started Aug 15 05:05:36 PM PDT 24
Finished Aug 15 05:05:39 PM PDT 24
Peak memory 218364 kb
Host smart-713469ba-5b83-4bf3-9ceb-1e30b117a206
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113892
099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.113892099
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1939749614
Short name T885
Test name
Test status
Simulation time 43712453 ps
CPU time 1.21 seconds
Started Aug 15 05:05:35 PM PDT 24
Finished Aug 15 05:05:36 PM PDT 24
Peak memory 210072 kb
Host smart-7772c606-baf9-4762-9af6-befa76d584c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939749614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1939749614
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3926520638
Short name T894
Test name
Test status
Simulation time 21720462 ps
CPU time 1.35 seconds
Started Aug 15 05:05:37 PM PDT 24
Finished Aug 15 05:05:38 PM PDT 24
Peak memory 212168 kb
Host smart-f626cb58-e751-443a-983f-a5c14686e2af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926520638 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3926520638
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2298415616
Short name T904
Test name
Test status
Simulation time 123349595 ps
CPU time 1.05 seconds
Started Aug 15 05:05:47 PM PDT 24
Finished Aug 15 05:05:48 PM PDT 24
Peak memory 210080 kb
Host smart-5cc9cc07-a98d-4bf5-ba2b-20c323af086b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298415616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2298415616
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.110331786
Short name T916
Test name
Test status
Simulation time 45560462 ps
CPU time 2.85 seconds
Started Aug 15 05:05:46 PM PDT 24
Finished Aug 15 05:05:49 PM PDT 24
Peak memory 218400 kb
Host smart-598f269a-de7e-4940-9a00-3cb3fc62c907
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110331786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.110331786
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3147331433
Short name T138
Test name
Test status
Simulation time 248679254 ps
CPU time 2.73 seconds
Started Aug 15 05:05:47 PM PDT 24
Finished Aug 15 05:05:49 PM PDT 24
Peak memory 218308 kb
Host smart-bd14ba8f-b910-4f46-87ce-e0adf837d677
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147331433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3147331433
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1963911211
Short name T954
Test name
Test status
Simulation time 16899229 ps
CPU time 1.35 seconds
Started Aug 15 05:05:46 PM PDT 24
Finished Aug 15 05:05:47 PM PDT 24
Peak memory 220028 kb
Host smart-2267b3b1-d6b9-4965-8dd2-b6801f6f5c58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963911211 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1963911211
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2084217146
Short name T966
Test name
Test status
Simulation time 17459643 ps
CPU time 1.17 seconds
Started Aug 15 05:05:48 PM PDT 24
Finished Aug 15 05:05:50 PM PDT 24
Peak memory 209868 kb
Host smart-0dafcb9f-5da4-407a-95d4-50ef57254454
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084217146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2084217146
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2683862781
Short name T910
Test name
Test status
Simulation time 146628350 ps
CPU time 1.07 seconds
Started Aug 15 05:05:46 PM PDT 24
Finished Aug 15 05:05:47 PM PDT 24
Peak memory 208744 kb
Host smart-29561c61-1a77-490a-8ac4-75fb74fcdead
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683862781 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2683862781
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.924962420
Short name T984
Test name
Test status
Simulation time 1375519848 ps
CPU time 10.87 seconds
Started Aug 15 05:05:46 PM PDT 24
Finished Aug 15 05:05:57 PM PDT 24
Peak memory 209820 kb
Host smart-45d3dd79-4507-4a9a-b18c-5599bed99379
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924962420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.924962420
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1529125597
Short name T983
Test name
Test status
Simulation time 2360881128 ps
CPU time 4.66 seconds
Started Aug 15 05:05:47 PM PDT 24
Finished Aug 15 05:05:52 PM PDT 24
Peak memory 209500 kb
Host smart-4c382145-2bb3-496d-84e8-b0bc3d9357fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529125597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1529125597
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1994500353
Short name T906
Test name
Test status
Simulation time 175251943 ps
CPU time 1.6 seconds
Started Aug 15 05:05:47 PM PDT 24
Finished Aug 15 05:05:49 PM PDT 24
Peak memory 211160 kb
Host smart-b09a8b25-f5af-452a-b4bc-fdb64282992a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994500353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1994500353
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1688344688
Short name T959
Test name
Test status
Simulation time 519664476 ps
CPU time 2.39 seconds
Started Aug 15 05:05:47 PM PDT 24
Finished Aug 15 05:05:50 PM PDT 24
Peak memory 219404 kb
Host smart-48c1e61a-ba86-475e-ba5d-92a67abdc592
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168834
4688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1688344688
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1368381166
Short name T898
Test name
Test status
Simulation time 65597146 ps
CPU time 2.16 seconds
Started Aug 15 05:05:47 PM PDT 24
Finished Aug 15 05:05:49 PM PDT 24
Peak memory 210120 kb
Host smart-e072091f-131d-481d-ac63-5c0de9f4e4a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368381166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1368381166
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3770951321
Short name T927
Test name
Test status
Simulation time 34489858 ps
CPU time 1.6 seconds
Started Aug 15 05:05:46 PM PDT 24
Finished Aug 15 05:05:48 PM PDT 24
Peak memory 209848 kb
Host smart-a125609f-3a26-4e61-afd3-4477c3942f12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770951321 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3770951321
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1319179281
Short name T965
Test name
Test status
Simulation time 26157076 ps
CPU time 1.08 seconds
Started Aug 15 05:05:48 PM PDT 24
Finished Aug 15 05:05:49 PM PDT 24
Peak memory 210144 kb
Host smart-a2e99cea-8abe-4944-9b2a-5b1509d4a6a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319179281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1319179281
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1587443685
Short name T987
Test name
Test status
Simulation time 128701477 ps
CPU time 1.92 seconds
Started Aug 15 05:05:49 PM PDT 24
Finished Aug 15 05:05:51 PM PDT 24
Peak memory 218752 kb
Host smart-17f63d67-b19f-45ff-9759-db076e75ea4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587443685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1587443685
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.716754571
Short name T135
Test name
Test status
Simulation time 719298107 ps
CPU time 2.98 seconds
Started Aug 15 05:05:48 PM PDT 24
Finished Aug 15 05:05:51 PM PDT 24
Peak memory 218284 kb
Host smart-556cc1fc-d423-4ac8-9ebf-daf2291a8d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716754571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.716754571
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3664994363
Short name T111
Test name
Test status
Simulation time 94493152 ps
CPU time 1.79 seconds
Started Aug 15 05:05:54 PM PDT 24
Finished Aug 15 05:05:56 PM PDT 24
Peak memory 218384 kb
Host smart-0f7d7987-20bb-4cca-bf57-04f92efc6e13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664994363 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3664994363
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1329719461
Short name T955
Test name
Test status
Simulation time 13763930 ps
CPU time 1.06 seconds
Started Aug 15 05:05:57 PM PDT 24
Finished Aug 15 05:05:58 PM PDT 24
Peak memory 210020 kb
Host smart-a91dacad-c807-4c39-b89f-5bb0f22e1a2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329719461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1329719461
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.542550877
Short name T964
Test name
Test status
Simulation time 256610151 ps
CPU time 2.33 seconds
Started Aug 15 05:05:53 PM PDT 24
Finished Aug 15 05:05:56 PM PDT 24
Peak memory 210096 kb
Host smart-5eb9da74-cb2d-4bde-bac8-e699c1ecc9e7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542550877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.542550877
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4288801416
Short name T876
Test name
Test status
Simulation time 371619475 ps
CPU time 9.4 seconds
Started Aug 15 05:05:59 PM PDT 24
Finished Aug 15 05:06:09 PM PDT 24
Peak memory 209920 kb
Host smart-e22db18d-b0c3-435a-8ec1-bce73a18a180
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288801416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.4288801416
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1517827821
Short name T973
Test name
Test status
Simulation time 2908021279 ps
CPU time 18.29 seconds
Started Aug 15 05:05:56 PM PDT 24
Finished Aug 15 05:06:14 PM PDT 24
Peak memory 210144 kb
Host smart-e3640a20-ed3f-4088-90eb-1e701b2440d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517827821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1517827821
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2144929088
Short name T977
Test name
Test status
Simulation time 97484766 ps
CPU time 1.47 seconds
Started Aug 15 05:05:48 PM PDT 24
Finished Aug 15 05:05:50 PM PDT 24
Peak memory 211556 kb
Host smart-c50e992c-e3f8-4e32-ba6a-b8afa406753e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144929088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2144929088
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2120138286
Short name T1000
Test name
Test status
Simulation time 103585471 ps
CPU time 3.65 seconds
Started Aug 15 05:05:56 PM PDT 24
Finished Aug 15 05:06:00 PM PDT 24
Peak memory 218392 kb
Host smart-662db8f8-34c4-4ea1-b290-4bf22df89d9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212013
8286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2120138286
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3878141788
Short name T877
Test name
Test status
Simulation time 324663118 ps
CPU time 1.97 seconds
Started Aug 15 05:05:54 PM PDT 24
Finished Aug 15 05:05:56 PM PDT 24
Peak memory 210172 kb
Host smart-a40a94d5-a3ed-47bc-8bc8-fe8f65858ba1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878141788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3878141788
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1323950111
Short name T923
Test name
Test status
Simulation time 193818063 ps
CPU time 1.93 seconds
Started Aug 15 05:05:55 PM PDT 24
Finished Aug 15 05:05:57 PM PDT 24
Peak memory 210184 kb
Host smart-4531454a-1266-408f-85f2-1b56ab523dc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323950111 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1323950111
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.116823424
Short name T909
Test name
Test status
Simulation time 57655957 ps
CPU time 1.04 seconds
Started Aug 15 05:05:55 PM PDT 24
Finished Aug 15 05:05:56 PM PDT 24
Peak memory 209956 kb
Host smart-4da4874e-395b-48bb-86bd-478f8eede318
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116823424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.116823424
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1547643270
Short name T998
Test name
Test status
Simulation time 382360439 ps
CPU time 2.74 seconds
Started Aug 15 05:05:57 PM PDT 24
Finished Aug 15 05:06:00 PM PDT 24
Peak memory 218220 kb
Host smart-1019cd5d-b6f0-4215-8272-5b8b9a69c3d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547643270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1547643270
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.284282875
Short name T130
Test name
Test status
Simulation time 59068304 ps
CPU time 2.03 seconds
Started Aug 15 05:05:54 PM PDT 24
Finished Aug 15 05:05:57 PM PDT 24
Peak memory 222548 kb
Host smart-d3ad9f4b-6197-45ae-9f63-208b09eaa55f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284282875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.284282875
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.18435805
Short name T947
Test name
Test status
Simulation time 43346154 ps
CPU time 0.99 seconds
Started Aug 15 05:06:05 PM PDT 24
Finished Aug 15 05:06:06 PM PDT 24
Peak memory 218164 kb
Host smart-8288062a-9697-454c-8b5b-cbc8fecb445b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18435805 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.18435805
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.806952857
Short name T988
Test name
Test status
Simulation time 15839887 ps
CPU time 1.05 seconds
Started Aug 15 05:05:58 PM PDT 24
Finished Aug 15 05:05:59 PM PDT 24
Peak memory 210136 kb
Host smart-0867ae38-e83d-450e-bbee-76373049fcf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806952857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.806952857
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1498044182
Short name T902
Test name
Test status
Simulation time 181971448 ps
CPU time 2.62 seconds
Started Aug 15 05:05:59 PM PDT 24
Finished Aug 15 05:06:02 PM PDT 24
Peak memory 210080 kb
Host smart-3034c8bc-e899-48b5-8f71-c51cdedb95b1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498044182 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1498044182
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.917906458
Short name T881
Test name
Test status
Simulation time 5075611968 ps
CPU time 10.2 seconds
Started Aug 15 05:05:58 PM PDT 24
Finished Aug 15 05:06:09 PM PDT 24
Peak memory 209544 kb
Host smart-c3c40276-174e-4819-8c46-f0b19c02678b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917906458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.917906458
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2683411460
Short name T938
Test name
Test status
Simulation time 1653821033 ps
CPU time 14.08 seconds
Started Aug 15 05:05:56 PM PDT 24
Finished Aug 15 05:06:11 PM PDT 24
Peak memory 209848 kb
Host smart-ecca21a1-9d32-44ea-a1d4-6a1fc4478aaa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683411460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2683411460
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2349081348
Short name T971
Test name
Test status
Simulation time 47205837 ps
CPU time 1.23 seconds
Started Aug 15 05:05:54 PM PDT 24
Finished Aug 15 05:05:56 PM PDT 24
Peak memory 211492 kb
Host smart-9e8201b8-0e55-4a50-9eee-1f7454933c46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349081348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2349081348
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3078392583
Short name T936
Test name
Test status
Simulation time 127459382 ps
CPU time 2.44 seconds
Started Aug 15 05:05:55 PM PDT 24
Finished Aug 15 05:05:57 PM PDT 24
Peak memory 220288 kb
Host smart-18755543-6e5d-4ebe-a359-e6adc7a3cd74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307839
2583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3078392583
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.137765348
Short name T919
Test name
Test status
Simulation time 71330174 ps
CPU time 1.5 seconds
Started Aug 15 05:05:58 PM PDT 24
Finished Aug 15 05:05:59 PM PDT 24
Peak memory 210120 kb
Host smart-3e1c8fb7-af02-4651-a42c-2f95b90939b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137765348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.137765348
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.551859420
Short name T930
Test name
Test status
Simulation time 86234545 ps
CPU time 1.09 seconds
Started Aug 15 05:05:55 PM PDT 24
Finished Aug 15 05:05:56 PM PDT 24
Peak memory 210096 kb
Host smart-6ad1f55b-a0b4-4411-8248-84e8654b40a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551859420 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.551859420
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.891075015
Short name T161
Test name
Test status
Simulation time 55593358 ps
CPU time 1.45 seconds
Started Aug 15 05:06:03 PM PDT 24
Finished Aug 15 05:06:04 PM PDT 24
Peak memory 210100 kb
Host smart-1a4cd5ac-d07b-4397-9c1b-2191c88a4d0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891075015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.891075015
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4101245970
Short name T924
Test name
Test status
Simulation time 172709126 ps
CPU time 2.2 seconds
Started Aug 15 05:05:59 PM PDT 24
Finished Aug 15 05:06:01 PM PDT 24
Peak memory 218352 kb
Host smart-4a7e9c6d-6c6b-4169-bfaf-eb6977c48ecc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101245970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.4101245970
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1302710532
Short name T951
Test name
Test status
Simulation time 24419753 ps
CPU time 1.19 seconds
Started Aug 15 05:06:03 PM PDT 24
Finished Aug 15 05:06:04 PM PDT 24
Peak memory 219420 kb
Host smart-4a651634-81e2-49c7-8d33-5dd05de44647
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302710532 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1302710532
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.44850770
Short name T201
Test name
Test status
Simulation time 18103006 ps
CPU time 0.94 seconds
Started Aug 15 05:06:04 PM PDT 24
Finished Aug 15 05:06:05 PM PDT 24
Peak memory 210096 kb
Host smart-3e0c5250-f3f8-4d4e-b118-65015ca51286
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44850770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.44850770
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4187175450
Short name T878
Test name
Test status
Simulation time 60705715 ps
CPU time 1.4 seconds
Started Aug 15 05:06:04 PM PDT 24
Finished Aug 15 05:06:06 PM PDT 24
Peak memory 210064 kb
Host smart-23607918-9125-49bd-aa4e-9bb2b2c9f227
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187175450 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.4187175450
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1582202672
Short name T958
Test name
Test status
Simulation time 2634025689 ps
CPU time 6.52 seconds
Started Aug 15 05:06:03 PM PDT 24
Finished Aug 15 05:06:10 PM PDT 24
Peak memory 210148 kb
Host smart-296c28df-e3ea-4ccf-854e-3c6b1e580af0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582202672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1582202672
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3885848429
Short name T976
Test name
Test status
Simulation time 2633619211 ps
CPU time 30.33 seconds
Started Aug 15 05:06:03 PM PDT 24
Finished Aug 15 05:06:33 PM PDT 24
Peak memory 209284 kb
Host smart-9dbdf6da-ea0e-4fdd-8873-25df8ddb4700
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885848429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3885848429
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.825503544
Short name T986
Test name
Test status
Simulation time 145188297 ps
CPU time 3.6 seconds
Started Aug 15 05:06:05 PM PDT 24
Finished Aug 15 05:06:08 PM PDT 24
Peak memory 211688 kb
Host smart-abb21e3a-2d6d-473b-ba77-ee90c87138b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825503544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.825503544
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3082303778
Short name T992
Test name
Test status
Simulation time 313755263 ps
CPU time 2.07 seconds
Started Aug 15 05:06:03 PM PDT 24
Finished Aug 15 05:06:05 PM PDT 24
Peak memory 218284 kb
Host smart-09d849c7-e8d7-47b0-81e8-c0243d7b77ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308230
3778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3082303778
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2722261529
Short name T970
Test name
Test status
Simulation time 141755370 ps
CPU time 1.62 seconds
Started Aug 15 05:06:04 PM PDT 24
Finished Aug 15 05:06:06 PM PDT 24
Peak memory 210084 kb
Host smart-a2af9fb5-6f6f-4cdd-a6d6-fc79a26c507e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722261529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2722261529
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2118553095
Short name T995
Test name
Test status
Simulation time 48188204 ps
CPU time 1.52 seconds
Started Aug 15 05:06:03 PM PDT 24
Finished Aug 15 05:06:04 PM PDT 24
Peak memory 210068 kb
Host smart-fd3728df-47dc-44f2-a28b-90d63b5695bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118553095 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2118553095
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3861762106
Short name T203
Test name
Test status
Simulation time 26017986 ps
CPU time 1.01 seconds
Started Aug 15 05:06:06 PM PDT 24
Finished Aug 15 05:06:07 PM PDT 24
Peak memory 210216 kb
Host smart-924956b2-86eb-4ae8-97f5-d49c2c5933c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861762106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3861762106
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2950502692
Short name T123
Test name
Test status
Simulation time 239806195 ps
CPU time 3.96 seconds
Started Aug 15 05:06:04 PM PDT 24
Finished Aug 15 05:06:08 PM PDT 24
Peak memory 218304 kb
Host smart-54de6b24-7d4f-4e7c-9cdf-811d2dd30992
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950502692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2950502692
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3178822432
Short name T175
Test name
Test status
Simulation time 23678198 ps
CPU time 1.44 seconds
Started Aug 15 05:06:11 PM PDT 24
Finished Aug 15 05:06:13 PM PDT 24
Peak memory 218472 kb
Host smart-7851738d-76c7-4b27-98a5-575ee76db00d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178822432 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3178822432
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.454152265
Short name T191
Test name
Test status
Simulation time 15126792 ps
CPU time 0.9 seconds
Started Aug 15 05:06:12 PM PDT 24
Finished Aug 15 05:06:13 PM PDT 24
Peak memory 210052 kb
Host smart-4caa6ff0-31f4-42fc-a56b-3ea7c2e25b2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454152265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.454152265
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1913634979
Short name T949
Test name
Test status
Simulation time 188274112 ps
CPU time 2.58 seconds
Started Aug 15 05:06:03 PM PDT 24
Finished Aug 15 05:06:06 PM PDT 24
Peak memory 208844 kb
Host smart-b16caaff-ad72-4154-883d-50a73d883786
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913634979 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1913634979
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.919622152
Short name T945
Test name
Test status
Simulation time 5729423505 ps
CPU time 24.82 seconds
Started Aug 15 05:06:03 PM PDT 24
Finished Aug 15 05:06:28 PM PDT 24
Peak memory 209480 kb
Host smart-3862583f-2cc3-4e28-9b51-17f1334460fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919622152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.919622152
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3161256874
Short name T880
Test name
Test status
Simulation time 3036626217 ps
CPU time 15.49 seconds
Started Aug 15 05:06:06 PM PDT 24
Finished Aug 15 05:06:21 PM PDT 24
Peak memory 210204 kb
Host smart-3e716fa9-c7f7-4ca0-accf-a6b7ffa79df6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161256874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3161256874
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2365029198
Short name T922
Test name
Test status
Simulation time 273480825 ps
CPU time 6.69 seconds
Started Aug 15 05:06:04 PM PDT 24
Finished Aug 15 05:06:11 PM PDT 24
Peak memory 211732 kb
Host smart-30bd14fa-ce1a-4296-86ae-24c360bee6f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365029198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2365029198
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4128097696
Short name T903
Test name
Test status
Simulation time 296445423 ps
CPU time 4.12 seconds
Started Aug 15 05:06:01 PM PDT 24
Finished Aug 15 05:06:05 PM PDT 24
Peak memory 221204 kb
Host smart-2978f601-8981-451a-a377-30dc4f4f80d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412809
7696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4128097696
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1165424931
Short name T142
Test name
Test status
Simulation time 201435617 ps
CPU time 1.31 seconds
Started Aug 15 05:06:04 PM PDT 24
Finished Aug 15 05:06:05 PM PDT 24
Peak memory 210104 kb
Host smart-3e22ff59-a7b1-4f4d-a1c5-f849199f6882
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165424931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1165424931
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.953060964
Short name T943
Test name
Test status
Simulation time 47788188 ps
CPU time 1.28 seconds
Started Aug 15 05:06:03 PM PDT 24
Finished Aug 15 05:06:05 PM PDT 24
Peak memory 210080 kb
Host smart-7f9ed9c2-aa84-43c3-8c0a-011a581b6863
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953060964 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.953060964
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1518976889
Short name T940
Test name
Test status
Simulation time 135451074 ps
CPU time 1.31 seconds
Started Aug 15 05:06:11 PM PDT 24
Finished Aug 15 05:06:12 PM PDT 24
Peak memory 210168 kb
Host smart-f0f99472-719b-48cd-bf86-51b292d673c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518976889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1518976889
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1841987286
Short name T889
Test name
Test status
Simulation time 38300751 ps
CPU time 1.47 seconds
Started Aug 15 05:06:12 PM PDT 24
Finished Aug 15 05:06:13 PM PDT 24
Peak memory 218368 kb
Host smart-ea892156-d1bb-47e3-80d4-bdc690355ab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841987286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1841987286
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3173152404
Short name T131
Test name
Test status
Simulation time 66849195 ps
CPU time 2.9 seconds
Started Aug 15 05:06:12 PM PDT 24
Finished Aug 15 05:06:15 PM PDT 24
Peak memory 213708 kb
Host smart-2f698b90-0255-46d5-baca-0d3cfefee143
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173152404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3173152404
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2252335829
Short name T839
Test name
Test status
Simulation time 72917158 ps
CPU time 0.93 seconds
Started Aug 15 05:07:19 PM PDT 24
Finished Aug 15 05:07:20 PM PDT 24
Peak memory 209196 kb
Host smart-9f6a12a8-969c-4aef-af2d-650ac0c967ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252335829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2252335829
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1613749696
Short name T775
Test name
Test status
Simulation time 946485218 ps
CPU time 25.69 seconds
Started Aug 15 05:07:22 PM PDT 24
Finished Aug 15 05:07:48 PM PDT 24
Peak memory 226148 kb
Host smart-27d7f28a-2415-4036-b411-072e3c8b7f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613749696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1613749696
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.96421375
Short name T756
Test name
Test status
Simulation time 1275007205 ps
CPU time 8.18 seconds
Started Aug 15 05:07:24 PM PDT 24
Finished Aug 15 05:07:33 PM PDT 24
Peak memory 217324 kb
Host smart-5d17d84c-6cac-4e03-bb04-186142cf2538
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96421375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.96421375
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2060670914
Short name T584
Test name
Test status
Simulation time 212983103 ps
CPU time 6.17 seconds
Started Aug 15 05:07:18 PM PDT 24
Finished Aug 15 05:07:24 PM PDT 24
Peak memory 217748 kb
Host smart-af1b8363-c94c-4cca-b3b6-5d7a2837a37f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060670914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
060670914
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1437349236
Short name T866
Test name
Test status
Simulation time 742908831 ps
CPU time 12.06 seconds
Started Aug 15 05:07:18 PM PDT 24
Finished Aug 15 05:07:30 PM PDT 24
Peak memory 218272 kb
Host smart-32e011c1-2791-4db2-ab66-fa1f180d399b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437349236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1437349236
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1527004818
Short name T78
Test name
Test status
Simulation time 4132634039 ps
CPU time 30.17 seconds
Started Aug 15 05:07:18 PM PDT 24
Finished Aug 15 05:07:49 PM PDT 24
Peak memory 217740 kb
Host smart-eba53edf-c531-47b0-900f-1e2f12938b80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527004818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1527004818
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1678512103
Short name T610
Test name
Test status
Simulation time 168181037 ps
CPU time 2.54 seconds
Started Aug 15 05:07:19 PM PDT 24
Finished Aug 15 05:07:21 PM PDT 24
Peak memory 217700 kb
Host smart-d079af0c-daf0-4bbe-8d0a-9dee9c0f9c6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678512103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1678512103
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3759099266
Short name T566
Test name
Test status
Simulation time 1272448889 ps
CPU time 61.91 seconds
Started Aug 15 05:07:20 PM PDT 24
Finished Aug 15 05:08:22 PM PDT 24
Peak memory 283664 kb
Host smart-ed1dc922-7f7d-49bc-afaf-c8a81511cc77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759099266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3759099266
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.293088095
Short name T865
Test name
Test status
Simulation time 462645292 ps
CPU time 17.6 seconds
Started Aug 15 05:07:23 PM PDT 24
Finished Aug 15 05:07:41 PM PDT 24
Peak memory 246404 kb
Host smart-e7b57963-6ec3-4c9b-ba80-447d90c15d6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293088095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.293088095
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3722123758
Short name T815
Test name
Test status
Simulation time 328994479 ps
CPU time 4.15 seconds
Started Aug 15 05:07:24 PM PDT 24
Finished Aug 15 05:07:29 PM PDT 24
Peak memory 218304 kb
Host smart-4ea95b44-24cb-4d51-a3f0-dee23b630d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722123758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3722123758
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2275940763
Short name T726
Test name
Test status
Simulation time 1571368070 ps
CPU time 15.66 seconds
Started Aug 15 05:07:23 PM PDT 24
Finished Aug 15 05:07:38 PM PDT 24
Peak memory 214648 kb
Host smart-3183203e-08f8-4351-9e34-6427f0c9a5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275940763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2275940763
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3416938880
Short name T79
Test name
Test status
Simulation time 200466730 ps
CPU time 23.48 seconds
Started Aug 15 05:07:17 PM PDT 24
Finished Aug 15 05:07:40 PM PDT 24
Peak memory 267844 kb
Host smart-51dd1e74-f99e-4558-84f1-e08234c10e55
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416938880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3416938880
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1034693094
Short name T461
Test name
Test status
Simulation time 1426224769 ps
CPU time 12.73 seconds
Started Aug 15 05:07:20 PM PDT 24
Finished Aug 15 05:07:33 PM PDT 24
Peak memory 218968 kb
Host smart-2e621500-8b8f-4c84-ab41-a47023b12cc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034693094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1034693094
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2562640214
Short name T458
Test name
Test status
Simulation time 918582922 ps
CPU time 10 seconds
Started Aug 15 05:07:22 PM PDT 24
Finished Aug 15 05:07:32 PM PDT 24
Peak memory 226144 kb
Host smart-e44a4193-52c9-4992-aa2d-77f4476efd74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562640214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2562640214
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2094785579
Short name T540
Test name
Test status
Simulation time 1211474832 ps
CPU time 11.19 seconds
Started Aug 15 05:07:24 PM PDT 24
Finished Aug 15 05:07:35 PM PDT 24
Peak memory 218288 kb
Host smart-47c3bec9-1816-4fbe-9f44-3c92ecc6367d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094785579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
094785579
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2920010764
Short name T209
Test name
Test status
Simulation time 1454993538 ps
CPU time 14.18 seconds
Started Aug 15 05:07:23 PM PDT 24
Finished Aug 15 05:07:37 PM PDT 24
Peak memory 225620 kb
Host smart-8980837a-03d8-43f2-868a-cb03e43395f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920010764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2920010764
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3648609315
Short name T596
Test name
Test status
Simulation time 42694138 ps
CPU time 1.46 seconds
Started Aug 15 05:07:24 PM PDT 24
Finished Aug 15 05:07:26 PM PDT 24
Peak memory 213912 kb
Host smart-8b66375f-2529-4444-8559-c4c348b2fa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648609315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3648609315
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3718126160
Short name T676
Test name
Test status
Simulation time 1510755968 ps
CPU time 30.59 seconds
Started Aug 15 05:07:24 PM PDT 24
Finished Aug 15 05:07:55 PM PDT 24
Peak memory 250964 kb
Host smart-a2ca33f6-16c8-4074-bc76-3d3fb7af5dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718126160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3718126160
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1693811604
Short name T820
Test name
Test status
Simulation time 84734800 ps
CPU time 7.32 seconds
Started Aug 15 05:07:19 PM PDT 24
Finished Aug 15 05:07:26 PM PDT 24
Peak memory 250856 kb
Host smart-8f3ca406-4303-40d9-8a91-7b2315462ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693811604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1693811604
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3571568088
Short name T783
Test name
Test status
Simulation time 72947977 ps
CPU time 0.75 seconds
Started Aug 15 05:07:18 PM PDT 24
Finished Aug 15 05:07:18 PM PDT 24
Peak memory 207236 kb
Host smart-9f9b19c1-4ba7-41ff-bd9e-c25a9137ec06
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571568088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3571568088
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2501752422
Short name T300
Test name
Test status
Simulation time 42273839 ps
CPU time 0.96 seconds
Started Aug 15 05:07:38 PM PDT 24
Finished Aug 15 05:07:39 PM PDT 24
Peak memory 208964 kb
Host smart-5e121ca6-62ce-429d-b8dd-67e62d06aaa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501752422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2501752422
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.4045303125
Short name T205
Test name
Test status
Simulation time 25008524 ps
CPU time 0.83 seconds
Started Aug 15 05:07:25 PM PDT 24
Finished Aug 15 05:07:26 PM PDT 24
Peak memory 208612 kb
Host smart-a67ed8f0-34bf-4643-905d-f272a8dfc769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045303125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.4045303125
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.476839008
Short name T481
Test name
Test status
Simulation time 215591842 ps
CPU time 8.62 seconds
Started Aug 15 05:07:25 PM PDT 24
Finished Aug 15 05:07:34 PM PDT 24
Peak memory 218348 kb
Host smart-b04ec689-745f-4d4c-896a-581d21802d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476839008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.476839008
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2064257751
Short name T793
Test name
Test status
Simulation time 63614211 ps
CPU time 1.18 seconds
Started Aug 15 05:07:28 PM PDT 24
Finished Aug 15 05:07:30 PM PDT 24
Peak memory 217220 kb
Host smart-4210259e-0d5c-42fa-8af7-a579d3c0ee08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064257751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2064257751
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.185887279
Short name T525
Test name
Test status
Simulation time 3375246375 ps
CPU time 29.91 seconds
Started Aug 15 05:07:26 PM PDT 24
Finished Aug 15 05:07:57 PM PDT 24
Peak memory 218996 kb
Host smart-214460f0-bbc2-491a-be45-e8d216eb3ea3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185887279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.185887279
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2645193796
Short name T304
Test name
Test status
Simulation time 629464766 ps
CPU time 4.88 seconds
Started Aug 15 05:07:27 PM PDT 24
Finished Aug 15 05:07:32 PM PDT 24
Peak memory 217492 kb
Host smart-1afd4cc3-881b-4e11-9602-b4ed2e7a22ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645193796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
645193796
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3623608855
Short name T178
Test name
Test status
Simulation time 318106592 ps
CPU time 3.29 seconds
Started Aug 15 05:07:27 PM PDT 24
Finished Aug 15 05:07:30 PM PDT 24
Peak memory 218224 kb
Host smart-276ffe64-ca27-413e-8052-7e2d4ef30522
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623608855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3623608855
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3119703000
Short name T537
Test name
Test status
Simulation time 5030168717 ps
CPU time 19.23 seconds
Started Aug 15 05:07:25 PM PDT 24
Finished Aug 15 05:07:45 PM PDT 24
Peak memory 217716 kb
Host smart-1db6d5d2-2a94-43ac-ad8c-74a3b1410c8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119703000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3119703000
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3774461357
Short name T103
Test name
Test status
Simulation time 148114469 ps
CPU time 2.71 seconds
Started Aug 15 05:07:26 PM PDT 24
Finished Aug 15 05:07:29 PM PDT 24
Peak memory 217684 kb
Host smart-337756f6-7465-4339-9697-e2fa389dc2cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774461357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3774461357
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.591466165
Short name T777
Test name
Test status
Simulation time 4288199410 ps
CPU time 79.29 seconds
Started Aug 15 05:07:26 PM PDT 24
Finished Aug 15 05:08:45 PM PDT 24
Peak memory 283668 kb
Host smart-7a1ffb31-d44e-424c-8856-56c68f86fb96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591466165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.591466165
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.397308433
Short name T523
Test name
Test status
Simulation time 754867763 ps
CPU time 15.75 seconds
Started Aug 15 05:07:29 PM PDT 24
Finished Aug 15 05:07:45 PM PDT 24
Peak memory 250360 kb
Host smart-ac5561d2-1156-45e5-b78d-a5450cdd8449
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397308433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.397308433
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2862488541
Short name T339
Test name
Test status
Simulation time 162470237 ps
CPU time 2.64 seconds
Started Aug 15 05:07:27 PM PDT 24
Finished Aug 15 05:07:30 PM PDT 24
Peak memory 218260 kb
Host smart-8502459d-1286-4d02-9d52-940b50cb98aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862488541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2862488541
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1474626076
Short name T340
Test name
Test status
Simulation time 288242724 ps
CPU time 6.8 seconds
Started Aug 15 05:07:28 PM PDT 24
Finished Aug 15 05:07:35 PM PDT 24
Peak memory 217708 kb
Host smart-3de53827-70d5-4e5d-9a26-dbe1be9fa5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474626076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1474626076
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2217659540
Short name T633
Test name
Test status
Simulation time 988720151 ps
CPU time 17.8 seconds
Started Aug 15 05:07:28 PM PDT 24
Finished Aug 15 05:07:46 PM PDT 24
Peak memory 218540 kb
Host smart-c3c3dee5-4579-4c5f-ac75-3b4994d3b09c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217659540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2217659540
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3184209379
Short name T717
Test name
Test status
Simulation time 389270060 ps
CPU time 14.8 seconds
Started Aug 15 05:07:26 PM PDT 24
Finished Aug 15 05:07:41 PM PDT 24
Peak memory 226048 kb
Host smart-2f3d470b-639e-46e4-9e70-6691d76a43be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184209379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3184209379
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2492990149
Short name T670
Test name
Test status
Simulation time 620470292 ps
CPU time 12.67 seconds
Started Aug 15 05:07:27 PM PDT 24
Finished Aug 15 05:07:40 PM PDT 24
Peak memory 218200 kb
Host smart-020b4a86-858f-4f9f-bc58-ee1ca31952dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492990149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
492990149
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1152168899
Short name T812
Test name
Test status
Simulation time 25504703 ps
CPU time 1.83 seconds
Started Aug 15 05:07:24 PM PDT 24
Finished Aug 15 05:07:26 PM PDT 24
Peak memory 214116 kb
Host smart-67899f80-1574-4c83-810b-6f6d24d2864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152168899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1152168899
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3350050802
Short name T402
Test name
Test status
Simulation time 314781069 ps
CPU time 26.65 seconds
Started Aug 15 05:07:25 PM PDT 24
Finished Aug 15 05:07:52 PM PDT 24
Peak memory 250936 kb
Host smart-59f4bb0c-8b96-426b-961b-77d5beadadca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350050802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3350050802
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1810252219
Short name T809
Test name
Test status
Simulation time 65354033 ps
CPU time 8.4 seconds
Started Aug 15 05:07:32 PM PDT 24
Finished Aug 15 05:07:41 PM PDT 24
Peak memory 250952 kb
Host smart-d02ae2ea-7adb-4245-96de-559d06a5e430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810252219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1810252219
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3668959083
Short name T186
Test name
Test status
Simulation time 7982280701 ps
CPU time 160.7 seconds
Started Aug 15 05:07:27 PM PDT 24
Finished Aug 15 05:10:08 PM PDT 24
Peak memory 282684 kb
Host smart-634b2da6-52ea-4f26-a16e-b390f74c2795
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668959083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3668959083
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3477960918
Short name T747
Test name
Test status
Simulation time 36623510 ps
CPU time 0.84 seconds
Started Aug 15 05:07:24 PM PDT 24
Finished Aug 15 05:07:25 PM PDT 24
Peak memory 209068 kb
Host smart-a8da5edc-064f-4f18-9922-ae6a41b7ec1d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477960918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3477960918
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1809801764
Short name T765
Test name
Test status
Simulation time 22226699 ps
CPU time 1.28 seconds
Started Aug 15 05:08:38 PM PDT 24
Finished Aug 15 05:08:39 PM PDT 24
Peak memory 208972 kb
Host smart-b6ddbe9a-bf9d-4d9e-bf54-ebc02c78a2ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809801764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1809801764
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1546104467
Short name T444
Test name
Test status
Simulation time 1143134669 ps
CPU time 9.99 seconds
Started Aug 15 05:08:36 PM PDT 24
Finished Aug 15 05:08:46 PM PDT 24
Peak memory 218232 kb
Host smart-3063a9d4-cada-4325-849f-c4873b936e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546104467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1546104467
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.161911371
Short name T659
Test name
Test status
Simulation time 1496755567 ps
CPU time 3.83 seconds
Started Aug 15 05:08:36 PM PDT 24
Finished Aug 15 05:08:40 PM PDT 24
Peak memory 217868 kb
Host smart-a620449d-1892-4c13-8ab6-ca414667f530
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161911371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.161911371
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3980873840
Short name T656
Test name
Test status
Simulation time 5420689322 ps
CPU time 27.46 seconds
Started Aug 15 05:08:34 PM PDT 24
Finished Aug 15 05:09:02 PM PDT 24
Peak memory 218680 kb
Host smart-e439a5ad-a5a5-4b55-ae5d-f8e9fb2e5fe3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980873840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3980873840
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3445829281
Short name T94
Test name
Test status
Simulation time 3514326959 ps
CPU time 10.15 seconds
Started Aug 15 05:08:35 PM PDT 24
Finished Aug 15 05:08:46 PM PDT 24
Peak memory 226112 kb
Host smart-e8561aa5-bd75-457c-8df4-24bc084ab4ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445829281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3445829281
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3307052295
Short name T727
Test name
Test status
Simulation time 244791009 ps
CPU time 8.28 seconds
Started Aug 15 05:08:35 PM PDT 24
Finished Aug 15 05:08:43 PM PDT 24
Peak memory 217680 kb
Host smart-f284c9c4-1963-4ebf-b1d1-77df1747a5cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307052295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3307052295
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2633957565
Short name T601
Test name
Test status
Simulation time 4632190494 ps
CPU time 49.43 seconds
Started Aug 15 05:08:38 PM PDT 24
Finished Aug 15 05:09:28 PM PDT 24
Peak memory 267348 kb
Host smart-ade178e7-3771-4caa-8d4f-6c8e7870b401
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633957565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2633957565
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2582383119
Short name T764
Test name
Test status
Simulation time 1641823773 ps
CPU time 16.14 seconds
Started Aug 15 05:08:35 PM PDT 24
Finished Aug 15 05:08:51 PM PDT 24
Peak memory 247524 kb
Host smart-8c377cb7-7aec-476c-9e63-994c498a12d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582383119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2582383119
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.865492981
Short name T350
Test name
Test status
Simulation time 70612447 ps
CPU time 2.99 seconds
Started Aug 15 05:08:36 PM PDT 24
Finished Aug 15 05:08:39 PM PDT 24
Peak memory 222440 kb
Host smart-3a2f0c81-00b8-4bb7-8c6c-cedc3299093c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865492981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.865492981
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1926569635
Short name T325
Test name
Test status
Simulation time 451546634 ps
CPU time 13.32 seconds
Started Aug 15 05:08:34 PM PDT 24
Finished Aug 15 05:08:47 PM PDT 24
Peak memory 226264 kb
Host smart-758c607f-2106-4d69-82d1-0ffa03ea39dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926569635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1926569635
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2300625604
Short name T373
Test name
Test status
Simulation time 267552805 ps
CPU time 11.68 seconds
Started Aug 15 05:08:35 PM PDT 24
Finished Aug 15 05:08:47 PM PDT 24
Peak memory 226008 kb
Host smart-b106903f-42a0-41d3-9342-e92fb60065dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300625604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.2300625604
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3138860954
Short name T803
Test name
Test status
Simulation time 240280195 ps
CPU time 9.75 seconds
Started Aug 15 05:08:35 PM PDT 24
Finished Aug 15 05:08:44 PM PDT 24
Peak memory 226024 kb
Host smart-2bb54050-1bbe-4676-8527-d7c8d95860f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138860954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3138860954
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2124703455
Short name T649
Test name
Test status
Simulation time 1674535842 ps
CPU time 14.12 seconds
Started Aug 15 05:08:38 PM PDT 24
Finished Aug 15 05:08:52 PM PDT 24
Peak memory 218412 kb
Host smart-958388f1-ffde-4540-bd14-89ef3a6b8b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124703455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2124703455
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1532447445
Short name T841
Test name
Test status
Simulation time 99577296 ps
CPU time 2.08 seconds
Started Aug 15 05:08:26 PM PDT 24
Finished Aug 15 05:08:29 PM PDT 24
Peak memory 214268 kb
Host smart-fedbe227-8ddb-4a75-9c5a-2305eca0f7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532447445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1532447445
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.776571196
Short name T489
Test name
Test status
Simulation time 152043763 ps
CPU time 4.45 seconds
Started Aug 15 05:08:35 PM PDT 24
Finished Aug 15 05:08:40 PM PDT 24
Peak memory 222424 kb
Host smart-64399eaf-ecb2-487a-aa14-5335231a72c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776571196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.776571196
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3512664456
Short name T472
Test name
Test status
Simulation time 5057424457 ps
CPU time 56.35 seconds
Started Aug 15 05:08:37 PM PDT 24
Finished Aug 15 05:09:34 PM PDT 24
Peak memory 242836 kb
Host smart-f2aba575-1808-4e12-b9a5-fc9ef09847b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512664456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3512664456
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2479291003
Short name T643
Test name
Test status
Simulation time 35805334 ps
CPU time 1.01 seconds
Started Aug 15 05:08:35 PM PDT 24
Finished Aug 15 05:08:36 PM PDT 24
Peak memory 217852 kb
Host smart-6f3c15e3-e5ca-4f10-8f0d-3b983181130e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479291003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2479291003
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3550257523
Short name T690
Test name
Test status
Simulation time 75412066 ps
CPU time 0.93 seconds
Started Aug 15 05:08:45 PM PDT 24
Finished Aug 15 05:08:46 PM PDT 24
Peak memory 208968 kb
Host smart-459bcd10-4096-4e99-9280-9ad6a04b9662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550257523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3550257523
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3095717596
Short name T699
Test name
Test status
Simulation time 1919358794 ps
CPU time 12.54 seconds
Started Aug 15 05:08:35 PM PDT 24
Finished Aug 15 05:08:48 PM PDT 24
Peak memory 218356 kb
Host smart-babeb3a4-c949-4555-ac77-397b9864e0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095717596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3095717596
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2380536889
Short name T678
Test name
Test status
Simulation time 2237144853 ps
CPU time 11.1 seconds
Started Aug 15 05:08:42 PM PDT 24
Finished Aug 15 05:08:54 PM PDT 24
Peak memory 217316 kb
Host smart-dcd5fa93-f602-4002-aa3a-1b68b881f0ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380536889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2380536889
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.36469460
Short name T165
Test name
Test status
Simulation time 20078870709 ps
CPU time 50.23 seconds
Started Aug 15 05:08:41 PM PDT 24
Finished Aug 15 05:09:31 PM PDT 24
Peak memory 218840 kb
Host smart-d40f5bd2-8cbe-4b66-9ed5-0d26e62d5606
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36469460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_err
ors.36469460
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.433339195
Short name T330
Test name
Test status
Simulation time 3659509354 ps
CPU time 8.19 seconds
Started Aug 15 05:08:44 PM PDT 24
Finished Aug 15 05:08:52 PM PDT 24
Peak memory 218340 kb
Host smart-9ccb4b8d-3aa4-4f60-86a4-f46d2e38a65d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433339195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.433339195
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2818122365
Short name T486
Test name
Test status
Simulation time 169252576 ps
CPU time 2.68 seconds
Started Aug 15 05:08:34 PM PDT 24
Finished Aug 15 05:08:37 PM PDT 24
Peak memory 217684 kb
Host smart-bd443597-925e-4e03-8778-1a17c2f3ec54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818122365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2818122365
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.740014549
Short name T361
Test name
Test status
Simulation time 3823018915 ps
CPU time 73.37 seconds
Started Aug 15 05:08:44 PM PDT 24
Finished Aug 15 05:09:57 PM PDT 24
Peak memory 276584 kb
Host smart-3fab2405-e3e9-4c4e-9ba5-ea7080d7f1c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740014549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.740014549
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.795827862
Short name T840
Test name
Test status
Simulation time 522675396 ps
CPU time 12.01 seconds
Started Aug 15 05:08:43 PM PDT 24
Finished Aug 15 05:08:55 PM PDT 24
Peak memory 249608 kb
Host smart-9e39369b-8a66-4538-8249-7e9996a34451
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795827862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.795827862
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2142592035
Short name T640
Test name
Test status
Simulation time 29272461 ps
CPU time 1.55 seconds
Started Aug 15 05:08:37 PM PDT 24
Finished Aug 15 05:08:39 PM PDT 24
Peak memory 218332 kb
Host smart-74ad7f15-12b6-4ed1-badf-2da32afe07e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142592035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2142592035
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.1394635711
Short name T645
Test name
Test status
Simulation time 1479619272 ps
CPU time 7.85 seconds
Started Aug 15 05:08:45 PM PDT 24
Finished Aug 15 05:08:53 PM PDT 24
Peak memory 226104 kb
Host smart-721b0812-23d1-4eda-a1f5-c77ff7ae0856
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394635711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1394635711
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3239035792
Short name T234
Test name
Test status
Simulation time 601422972 ps
CPU time 13.18 seconds
Started Aug 15 05:08:46 PM PDT 24
Finished Aug 15 05:08:59 PM PDT 24
Peak memory 226068 kb
Host smart-d934869a-b175-4653-a552-50a31e9b62a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239035792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3239035792
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.847566730
Short name T852
Test name
Test status
Simulation time 341170021 ps
CPU time 7.63 seconds
Started Aug 15 05:08:48 PM PDT 24
Finished Aug 15 05:08:56 PM PDT 24
Peak memory 226064 kb
Host smart-fe7fbbb8-d210-4cf0-9bb7-64f624a2bf98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847566730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.847566730
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1408218599
Short name T845
Test name
Test status
Simulation time 1102931975 ps
CPU time 15.03 seconds
Started Aug 15 05:08:36 PM PDT 24
Finished Aug 15 05:08:51 PM PDT 24
Peak memory 218452 kb
Host smart-991d5822-b805-40c1-9f52-77636d4236fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408218599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1408218599
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3190190818
Short name T457
Test name
Test status
Simulation time 101121439 ps
CPU time 2.07 seconds
Started Aug 15 05:08:37 PM PDT 24
Finished Aug 15 05:08:40 PM PDT 24
Peak memory 217756 kb
Host smart-94294284-1c63-44a5-8f8e-8bfb4a67e39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190190818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3190190818
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1719424767
Short name T641
Test name
Test status
Simulation time 1753953665 ps
CPU time 20.26 seconds
Started Aug 15 05:08:34 PM PDT 24
Finished Aug 15 05:08:55 PM PDT 24
Peak memory 250988 kb
Host smart-928ad1d8-0f7f-415c-95e1-ed6c7c293be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719424767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1719424767
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2308796298
Short name T294
Test name
Test status
Simulation time 312844187 ps
CPU time 4.49 seconds
Started Aug 15 05:08:35 PM PDT 24
Finished Aug 15 05:08:40 PM PDT 24
Peak memory 222872 kb
Host smart-c19ca750-084f-4a15-a649-8cf6d6023f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308796298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2308796298
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3251609832
Short name T341
Test name
Test status
Simulation time 62793960 ps
CPU time 0.93 seconds
Started Aug 15 05:08:34 PM PDT 24
Finished Aug 15 05:08:35 PM PDT 24
Peak memory 211972 kb
Host smart-4a2410ca-c511-4a8c-ba48-ac66027b09d1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251609832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3251609832
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3197220479
Short name T332
Test name
Test status
Simulation time 107293858 ps
CPU time 1.01 seconds
Started Aug 15 05:08:47 PM PDT 24
Finished Aug 15 05:08:49 PM PDT 24
Peak memory 209072 kb
Host smart-559284da-0963-4a1f-8ce5-130ab7f83a1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197220479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3197220479
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3083853324
Short name T509
Test name
Test status
Simulation time 9505144053 ps
CPU time 16.79 seconds
Started Aug 15 05:08:44 PM PDT 24
Finished Aug 15 05:09:01 PM PDT 24
Peak memory 218296 kb
Host smart-f690da8a-2c04-4fe5-9559-6698214653e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083853324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3083853324
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1155416954
Short name T188
Test name
Test status
Simulation time 294071314 ps
CPU time 4.91 seconds
Started Aug 15 05:08:44 PM PDT 24
Finished Aug 15 05:08:49 PM PDT 24
Peak memory 217776 kb
Host smart-98970ad4-22ac-4786-8e66-987179c9af83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155416954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1155416954
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2870133386
Short name T612
Test name
Test status
Simulation time 3467176128 ps
CPU time 45.98 seconds
Started Aug 15 05:08:45 PM PDT 24
Finished Aug 15 05:09:32 PM PDT 24
Peak memory 218984 kb
Host smart-eb5855ec-0e9f-4691-871a-af541d8fbc60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870133386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2870133386
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3538286926
Short name T228
Test name
Test status
Simulation time 207477893 ps
CPU time 6.21 seconds
Started Aug 15 05:08:44 PM PDT 24
Finished Aug 15 05:08:50 PM PDT 24
Peak memory 222988 kb
Host smart-b79982c9-8c36-498f-9958-68e0405d557b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538286926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3538286926
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3788867213
Short name T229
Test name
Test status
Simulation time 1065126204 ps
CPU time 6.61 seconds
Started Aug 15 05:08:48 PM PDT 24
Finished Aug 15 05:08:55 PM PDT 24
Peak memory 217688 kb
Host smart-ece5f8b7-8626-406b-a8e0-949361557b05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788867213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3788867213
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2529331317
Short name T642
Test name
Test status
Simulation time 10592197632 ps
CPU time 54.38 seconds
Started Aug 15 05:08:45 PM PDT 24
Finished Aug 15 05:09:40 PM PDT 24
Peak memory 277496 kb
Host smart-6f95656e-de4f-4f0f-8070-401ca4bd838c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529331317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2529331317
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1180976675
Short name T105
Test name
Test status
Simulation time 1048034532 ps
CPU time 12.06 seconds
Started Aug 15 05:08:43 PM PDT 24
Finished Aug 15 05:08:55 PM PDT 24
Peak memory 250908 kb
Host smart-fa8e4c68-9301-40c7-b95a-e1bbff60ede1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180976675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1180976675
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2844898604
Short name T757
Test name
Test status
Simulation time 90485756 ps
CPU time 2.39 seconds
Started Aug 15 05:08:43 PM PDT 24
Finished Aug 15 05:08:46 PM PDT 24
Peak memory 218320 kb
Host smart-86f6b87f-4b26-4251-9740-d528e6625504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844898604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2844898604
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2758676935
Short name T738
Test name
Test status
Simulation time 418599831 ps
CPU time 17.92 seconds
Started Aug 15 05:08:46 PM PDT 24
Finished Aug 15 05:09:04 PM PDT 24
Peak memory 226136 kb
Host smart-992f20bc-a9a7-4d04-a9e9-77b0e16af2d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758676935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2758676935
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2230227698
Short name T650
Test name
Test status
Simulation time 914662757 ps
CPU time 15.9 seconds
Started Aug 15 05:08:44 PM PDT 24
Finished Aug 15 05:09:00 PM PDT 24
Peak memory 226036 kb
Host smart-a2462bad-735e-40b8-a4b4-064710f83b26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230227698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2230227698
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1137820754
Short name T559
Test name
Test status
Simulation time 363836915 ps
CPU time 14.07 seconds
Started Aug 15 05:08:44 PM PDT 24
Finished Aug 15 05:08:58 PM PDT 24
Peak memory 218508 kb
Host smart-9ecc7c26-e5f7-40a7-b425-76d7346fd889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137820754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1137820754
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3715048572
Short name T575
Test name
Test status
Simulation time 112523893 ps
CPU time 2.06 seconds
Started Aug 15 05:08:44 PM PDT 24
Finished Aug 15 05:08:46 PM PDT 24
Peak memory 214260 kb
Host smart-e04b7678-4482-4af2-aa8b-636fefabdecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715048572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3715048572
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3758864260
Short name T695
Test name
Test status
Simulation time 1644223141 ps
CPU time 27.85 seconds
Started Aug 15 05:08:44 PM PDT 24
Finished Aug 15 05:09:12 PM PDT 24
Peak memory 251064 kb
Host smart-d4c9250d-9632-4c44-a94c-f4bed1b42b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758864260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3758864260
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1955856921
Short name T100
Test name
Test status
Simulation time 68871489 ps
CPU time 7.27 seconds
Started Aug 15 05:08:44 PM PDT 24
Finished Aug 15 05:08:52 PM PDT 24
Peak memory 250964 kb
Host smart-a2fd61e2-dbac-4c54-a856-948959390bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955856921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1955856921
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3321207879
Short name T637
Test name
Test status
Simulation time 19305918 ps
CPU time 0.74 seconds
Started Aug 15 05:08:45 PM PDT 24
Finished Aug 15 05:08:46 PM PDT 24
Peak memory 207216 kb
Host smart-76fa1703-170e-4e09-90ba-c7f226cc5f8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321207879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3321207879
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2925415358
Short name T619
Test name
Test status
Simulation time 113405186 ps
CPU time 1.23 seconds
Started Aug 15 05:08:51 PM PDT 24
Finished Aug 15 05:08:52 PM PDT 24
Peak memory 209108 kb
Host smart-c76f128c-9398-4743-8620-fd81c71fadc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925415358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2925415358
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2572320158
Short name T682
Test name
Test status
Simulation time 437265065 ps
CPU time 13.38 seconds
Started Aug 15 05:08:52 PM PDT 24
Finished Aug 15 05:09:06 PM PDT 24
Peak memory 218248 kb
Host smart-f4805e4d-be2c-49a7-8ce1-48ddbf4029de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572320158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2572320158
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1113019741
Short name T24
Test name
Test status
Simulation time 393707872 ps
CPU time 8.55 seconds
Started Aug 15 05:08:50 PM PDT 24
Finished Aug 15 05:08:58 PM PDT 24
Peak memory 217596 kb
Host smart-393e5d85-1060-4777-b22a-90caec6790ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113019741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1113019741
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.4081648953
Short name T256
Test name
Test status
Simulation time 8256894799 ps
CPU time 33.13 seconds
Started Aug 15 05:08:52 PM PDT 24
Finished Aug 15 05:09:25 PM PDT 24
Peak memory 218840 kb
Host smart-27f76939-ef8e-4323-b490-f1bda76ead0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081648953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.4081648953
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3591106065
Short name T661
Test name
Test status
Simulation time 1194242387 ps
CPU time 10.68 seconds
Started Aug 15 05:08:50 PM PDT 24
Finished Aug 15 05:09:01 PM PDT 24
Peak memory 218292 kb
Host smart-3509008b-6286-4bb7-ae1c-a7eace1335ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591106065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3591106065
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2197056575
Short name T377
Test name
Test status
Simulation time 314582836 ps
CPU time 4.32 seconds
Started Aug 15 05:08:51 PM PDT 24
Finished Aug 15 05:08:55 PM PDT 24
Peak memory 217668 kb
Host smart-d8f203b2-a1d7-4c8d-ba46-d55711c24d92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197056575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2197056575
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3452303456
Short name T438
Test name
Test status
Simulation time 11418049221 ps
CPU time 42.73 seconds
Started Aug 15 05:08:50 PM PDT 24
Finished Aug 15 05:09:33 PM PDT 24
Peak memory 251248 kb
Host smart-5e92fe81-242e-428f-9c59-f2c351398375
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452303456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3452303456
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1713114796
Short name T349
Test name
Test status
Simulation time 2147329128 ps
CPU time 24.91 seconds
Started Aug 15 05:08:52 PM PDT 24
Finished Aug 15 05:09:17 PM PDT 24
Peak memory 248756 kb
Host smart-a8d83542-55c6-4a3b-bc6b-a8dffcdfa494
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713114796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1713114796
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2757106725
Short name T148
Test name
Test status
Simulation time 97561642 ps
CPU time 1.85 seconds
Started Aug 15 05:08:50 PM PDT 24
Finished Aug 15 05:08:53 PM PDT 24
Peak memory 218272 kb
Host smart-2bdd956d-0c57-4547-a0d9-3926e027f83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757106725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2757106725
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.721836254
Short name T362
Test name
Test status
Simulation time 1490216844 ps
CPU time 13.57 seconds
Started Aug 15 05:08:51 PM PDT 24
Finished Aug 15 05:09:05 PM PDT 24
Peak memory 218984 kb
Host smart-498ebfdf-a57b-4eff-83e6-c788fd262058
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721836254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.721836254
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.4043271091
Short name T35
Test name
Test status
Simulation time 494415196 ps
CPU time 16.18 seconds
Started Aug 15 05:08:50 PM PDT 24
Finished Aug 15 05:09:07 PM PDT 24
Peak memory 226068 kb
Host smart-dd786e99-d4ed-48b9-ae09-fa784b86fe72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043271091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.4043271091
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1169055276
Short name T863
Test name
Test status
Simulation time 470767545 ps
CPU time 12.36 seconds
Started Aug 15 05:08:52 PM PDT 24
Finished Aug 15 05:09:05 PM PDT 24
Peak memory 226064 kb
Host smart-bb4895a3-c0f0-41f4-b117-a6b2d7862111
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169055276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1169055276
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3416050678
Short name T662
Test name
Test status
Simulation time 822198937 ps
CPU time 7.48 seconds
Started Aug 15 05:08:51 PM PDT 24
Finished Aug 15 05:08:59 PM PDT 24
Peak memory 218404 kb
Host smart-80882908-1764-423c-aec0-677fc13ca97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416050678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3416050678
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3772981651
Short name T555
Test name
Test status
Simulation time 203452195 ps
CPU time 2.05 seconds
Started Aug 15 05:08:46 PM PDT 24
Finished Aug 15 05:08:48 PM PDT 24
Peak memory 214436 kb
Host smart-6df02695-58aa-49f1-9b09-603baf69669f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772981651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3772981651
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1446552663
Short name T90
Test name
Test status
Simulation time 261791555 ps
CPU time 21.99 seconds
Started Aug 15 05:08:51 PM PDT 24
Finished Aug 15 05:09:13 PM PDT 24
Peak memory 250948 kb
Host smart-7d299fae-367b-48a0-ba54-726ad7726836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446552663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1446552663
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.417179818
Short name T817
Test name
Test status
Simulation time 854848907 ps
CPU time 10.22 seconds
Started Aug 15 05:08:51 PM PDT 24
Finished Aug 15 05:09:01 PM PDT 24
Peak memory 246556 kb
Host smart-eb534f3e-bd42-4221-8edb-0e7b1feb1cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417179818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.417179818
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1476996459
Short name T857
Test name
Test status
Simulation time 16007989839 ps
CPU time 339.28 seconds
Started Aug 15 05:08:53 PM PDT 24
Finished Aug 15 05:14:33 PM PDT 24
Peak memory 259136 kb
Host smart-83bd259a-d7e1-4987-bedb-37df1234ceef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476996459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1476996459
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2674312365
Short name T421
Test name
Test status
Simulation time 21867061 ps
CPU time 0.95 seconds
Started Aug 15 05:08:48 PM PDT 24
Finished Aug 15 05:08:49 PM PDT 24
Peak memory 209272 kb
Host smart-feb439d9-fc9b-4793-a228-137afd5eccab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674312365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2674312365
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2743408444
Short name T363
Test name
Test status
Simulation time 43686633 ps
CPU time 0.92 seconds
Started Aug 15 05:09:00 PM PDT 24
Finished Aug 15 05:09:01 PM PDT 24
Peak memory 208960 kb
Host smart-628d6800-802a-44cd-9295-9cf8d62059c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743408444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2743408444
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.831134816
Short name T477
Test name
Test status
Simulation time 1902352280 ps
CPU time 14.85 seconds
Started Aug 15 05:08:51 PM PDT 24
Finished Aug 15 05:09:06 PM PDT 24
Peak memory 218236 kb
Host smart-f20abb9b-e8b8-4749-9f5c-b80edb4951eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831134816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.831134816
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1046141416
Short name T697
Test name
Test status
Simulation time 5082115610 ps
CPU time 10.47 seconds
Started Aug 15 05:09:00 PM PDT 24
Finished Aug 15 05:09:11 PM PDT 24
Peak memory 217808 kb
Host smart-9ae52ce8-4cdd-433c-bd86-9c926a98107e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046141416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1046141416
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2275054495
Short name T82
Test name
Test status
Simulation time 5058350812 ps
CPU time 64.39 seconds
Started Aug 15 05:08:51 PM PDT 24
Finished Aug 15 05:09:55 PM PDT 24
Peak memory 218600 kb
Host smart-658883f8-9f39-41ad-8571-23ff7695985e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275054495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2275054495
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1574916173
Short name T802
Test name
Test status
Simulation time 863615415 ps
CPU time 3.93 seconds
Started Aug 15 05:08:52 PM PDT 24
Finished Aug 15 05:08:56 PM PDT 24
Peak memory 218248 kb
Host smart-02b09cd9-a56e-43a3-be26-a96624fe22f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574916173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1574916173
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1412723897
Short name T270
Test name
Test status
Simulation time 137853670 ps
CPU time 4.73 seconds
Started Aug 15 05:08:50 PM PDT 24
Finished Aug 15 05:08:55 PM PDT 24
Peak memory 217688 kb
Host smart-88e463c1-b118-4434-a009-d825869a93a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412723897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1412723897
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.4051058176
Short name T582
Test name
Test status
Simulation time 3881928771 ps
CPU time 34.38 seconds
Started Aug 15 05:08:51 PM PDT 24
Finished Aug 15 05:09:26 PM PDT 24
Peak memory 250864 kb
Host smart-cd7a7401-2d38-4094-8f18-7ceb94709114
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051058176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.4051058176
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.3109537508
Short name T730
Test name
Test status
Simulation time 1278000248 ps
CPU time 20.28 seconds
Started Aug 15 05:08:52 PM PDT 24
Finished Aug 15 05:09:12 PM PDT 24
Peak memory 223312 kb
Host smart-dd7bb369-7b5e-45fe-a5db-e3eba250ef87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109537508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.3109537508
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.564178708
Short name T691
Test name
Test status
Simulation time 151451258 ps
CPU time 1.97 seconds
Started Aug 15 05:08:52 PM PDT 24
Finished Aug 15 05:08:54 PM PDT 24
Peak memory 218324 kb
Host smart-aad66dda-1144-4d29-ba28-5e23e648aa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564178708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.564178708
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3160206683
Short name T605
Test name
Test status
Simulation time 255142357 ps
CPU time 11.13 seconds
Started Aug 15 05:08:59 PM PDT 24
Finished Aug 15 05:09:10 PM PDT 24
Peak memory 226100 kb
Host smart-c95ea1a6-a50b-42d3-aa95-cf97b2e3e635
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160206683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3160206683
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1279668253
Short name T585
Test name
Test status
Simulation time 411641405 ps
CPU time 8.99 seconds
Started Aug 15 05:09:00 PM PDT 24
Finished Aug 15 05:09:09 PM PDT 24
Peak memory 226072 kb
Host smart-6828094f-4eb6-480a-aadd-39b2d019c899
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279668253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1279668253
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1980429483
Short name T702
Test name
Test status
Simulation time 262550854 ps
CPU time 10.03 seconds
Started Aug 15 05:08:53 PM PDT 24
Finished Aug 15 05:09:03 PM PDT 24
Peak memory 218400 kb
Host smart-dc1d6b4d-8c34-4540-91c9-384dee08fa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980429483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1980429483
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3254592867
Short name T466
Test name
Test status
Simulation time 70132870 ps
CPU time 2.1 seconds
Started Aug 15 05:08:53 PM PDT 24
Finished Aug 15 05:08:55 PM PDT 24
Peak memory 222416 kb
Host smart-8e76c6ae-4bfe-4e52-b00e-5c25701d3f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254592867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3254592867
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.312550194
Short name T437
Test name
Test status
Simulation time 335207667 ps
CPU time 35.2 seconds
Started Aug 15 05:08:53 PM PDT 24
Finished Aug 15 05:09:28 PM PDT 24
Peak memory 251032 kb
Host smart-aa731402-f5a3-48ec-9d4e-0da9a52984fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312550194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.312550194
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.658090976
Short name T282
Test name
Test status
Simulation time 547467884 ps
CPU time 7.88 seconds
Started Aug 15 05:08:52 PM PDT 24
Finished Aug 15 05:09:00 PM PDT 24
Peak memory 250812 kb
Host smart-2e05cee2-9297-45ef-988c-c2c167942da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658090976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.658090976
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.143874408
Short name T593
Test name
Test status
Simulation time 10285321371 ps
CPU time 186.26 seconds
Started Aug 15 05:09:01 PM PDT 24
Finished Aug 15 05:12:07 PM PDT 24
Peak memory 283568 kb
Host smart-9213a549-9015-4aa9-a43b-a83d2519515f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143874408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.143874408
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.3736948635
Short name T221
Test name
Test status
Simulation time 2217946749 ps
CPU time 71.59 seconds
Started Aug 15 05:09:00 PM PDT 24
Finished Aug 15 05:10:11 PM PDT 24
Peak memory 251320 kb
Host smart-f4b0322f-0af5-4f97-84be-a863c4b037a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3736948635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.3736948635
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1718126925
Short name T30
Test name
Test status
Simulation time 47227558 ps
CPU time 1.47 seconds
Started Aug 15 05:08:52 PM PDT 24
Finished Aug 15 05:08:53 PM PDT 24
Peak memory 217868 kb
Host smart-9deda8e6-79eb-4050-bcae-33cddcac1550
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718126925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1718126925
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3757045363
Short name T296
Test name
Test status
Simulation time 60919887 ps
CPU time 0.9 seconds
Started Aug 15 05:09:09 PM PDT 24
Finished Aug 15 05:09:10 PM PDT 24
Peak memory 208944 kb
Host smart-bffd2188-d59c-4294-99f2-1a177f47bee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757045363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3757045363
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1631092929
Short name T766
Test name
Test status
Simulation time 568235591 ps
CPU time 12.17 seconds
Started Aug 15 05:09:01 PM PDT 24
Finished Aug 15 05:09:13 PM PDT 24
Peak memory 226076 kb
Host smart-fc1c763f-281d-4a46-bb4b-bebfed298740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631092929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1631092929
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1584130661
Short name T491
Test name
Test status
Simulation time 61087945 ps
CPU time 1.63 seconds
Started Aug 15 05:08:59 PM PDT 24
Finished Aug 15 05:09:01 PM PDT 24
Peak memory 217200 kb
Host smart-d4994ad2-1795-4c5e-b5ce-e8d08f6be88f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584130661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1584130661
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3598625870
Short name T183
Test name
Test status
Simulation time 1232480874 ps
CPU time 25.63 seconds
Started Aug 15 05:09:02 PM PDT 24
Finished Aug 15 05:09:28 PM PDT 24
Peak memory 218368 kb
Host smart-c1a51b50-0464-4035-a8c6-d20437228020
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598625870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3598625870
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3983728434
Short name T479
Test name
Test status
Simulation time 2333101495 ps
CPU time 16.06 seconds
Started Aug 15 05:09:05 PM PDT 24
Finished Aug 15 05:09:21 PM PDT 24
Peak memory 218340 kb
Host smart-d31dc553-4832-44bc-ae1d-a84346a1a755
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983728434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3983728434
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1002252088
Short name T861
Test name
Test status
Simulation time 460615447 ps
CPU time 6.19 seconds
Started Aug 15 05:08:59 PM PDT 24
Finished Aug 15 05:09:06 PM PDT 24
Peak memory 217636 kb
Host smart-ea4433cd-de3d-4d84-8209-67b50682c5c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002252088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1002252088
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2456216700
Short name T266
Test name
Test status
Simulation time 3768018014 ps
CPU time 44.38 seconds
Started Aug 15 05:08:59 PM PDT 24
Finished Aug 15 05:09:43 PM PDT 24
Peak memory 252244 kb
Host smart-a508de2b-ec25-4277-a6b8-65c5b04362a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456216700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2456216700
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1811277204
Short name T218
Test name
Test status
Simulation time 3644264433 ps
CPU time 14.13 seconds
Started Aug 15 05:09:02 PM PDT 24
Finished Aug 15 05:09:16 PM PDT 24
Peak memory 251024 kb
Host smart-88d4783e-fb38-4da0-9c6f-e36f8a9e95c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811277204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1811277204
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2370429520
Short name T799
Test name
Test status
Simulation time 50498835 ps
CPU time 2.79 seconds
Started Aug 15 05:09:02 PM PDT 24
Finished Aug 15 05:09:05 PM PDT 24
Peak memory 222324 kb
Host smart-951cc1cb-11eb-4c8c-bd48-85169d033c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370429520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2370429520
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.4076055582
Short name T862
Test name
Test status
Simulation time 647782342 ps
CPU time 15.19 seconds
Started Aug 15 05:09:01 PM PDT 24
Finished Aug 15 05:09:17 PM PDT 24
Peak memory 218972 kb
Host smart-c91a095b-6f99-493b-9706-0194402afc6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076055582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.4076055582
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.4140809238
Short name T312
Test name
Test status
Simulation time 289775173 ps
CPU time 11.56 seconds
Started Aug 15 05:09:00 PM PDT 24
Finished Aug 15 05:09:12 PM PDT 24
Peak memory 226016 kb
Host smart-e0e09879-aeb6-4919-9280-3e7c6da44ab6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140809238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.4140809238
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.35432940
Short name T842
Test name
Test status
Simulation time 3534435862 ps
CPU time 7.21 seconds
Started Aug 15 05:09:02 PM PDT 24
Finished Aug 15 05:09:09 PM PDT 24
Peak memory 226124 kb
Host smart-1730fda8-934c-4b29-8d15-def8bcfec17d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35432940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.35432940
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1047917918
Short name T528
Test name
Test status
Simulation time 314106164 ps
CPU time 12.3 seconds
Started Aug 15 05:09:00 PM PDT 24
Finished Aug 15 05:09:12 PM PDT 24
Peak memory 226120 kb
Host smart-1ed41924-6777-408f-b707-ae4fd284b723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047917918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1047917918
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.748479039
Short name T63
Test name
Test status
Simulation time 19134513 ps
CPU time 1.56 seconds
Started Aug 15 05:09:00 PM PDT 24
Finished Aug 15 05:09:02 PM PDT 24
Peak memory 213748 kb
Host smart-7f19db3d-ec1b-4c96-86ab-1cfe7c433edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748479039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.748479039
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3404006072
Short name T151
Test name
Test status
Simulation time 1026508342 ps
CPU time 31.05 seconds
Started Aug 15 05:09:00 PM PDT 24
Finished Aug 15 05:09:31 PM PDT 24
Peak memory 250948 kb
Host smart-2cb1fa3c-e2b5-4761-8320-c28671167754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404006072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3404006072
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1460182913
Short name T435
Test name
Test status
Simulation time 119829077 ps
CPU time 7.93 seconds
Started Aug 15 05:08:58 PM PDT 24
Finished Aug 15 05:09:07 PM PDT 24
Peak memory 250940 kb
Host smart-b834617b-a5c4-42cd-bfdb-1f739ff53c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460182913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1460182913
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3392603865
Short name T572
Test name
Test status
Simulation time 31072672025 ps
CPU time 290.7 seconds
Started Aug 15 05:09:08 PM PDT 24
Finished Aug 15 05:13:59 PM PDT 24
Peak memory 332928 kb
Host smart-6cd0eb15-5c67-4a69-bed9-019b2bff6ced
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392603865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3392603865
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.3035016135
Short name T89
Test name
Test status
Simulation time 10035380691 ps
CPU time 94.93 seconds
Started Aug 15 05:09:09 PM PDT 24
Finished Aug 15 05:10:44 PM PDT 24
Peak memory 251128 kb
Host smart-a47cf4ea-837f-4fcb-8efa-379bb8ac0d2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3035016135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.3035016135
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2505400910
Short name T554
Test name
Test status
Simulation time 18441541 ps
CPU time 1.02 seconds
Started Aug 15 05:09:00 PM PDT 24
Finished Aug 15 05:09:01 PM PDT 24
Peak memory 213048 kb
Host smart-63941c07-4da1-4d66-9c79-4e97aab7a4dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505400910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2505400910
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1685089000
Short name T873
Test name
Test status
Simulation time 23669895 ps
CPU time 1.13 seconds
Started Aug 15 05:09:13 PM PDT 24
Finished Aug 15 05:09:14 PM PDT 24
Peak memory 209036 kb
Host smart-916f5027-316d-4389-8bf3-b4bdbc2cd84e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685089000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1685089000
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1891460663
Short name T734
Test name
Test status
Simulation time 242996135 ps
CPU time 8.54 seconds
Started Aug 15 05:09:09 PM PDT 24
Finished Aug 15 05:09:17 PM PDT 24
Peak memory 218308 kb
Host smart-2a744a86-9036-48e7-84e4-79257bc4a070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891460663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1891460663
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.191187414
Short name T354
Test name
Test status
Simulation time 229828130 ps
CPU time 6.21 seconds
Started Aug 15 05:09:09 PM PDT 24
Finished Aug 15 05:09:16 PM PDT 24
Peak memory 217728 kb
Host smart-af235bed-c089-476b-b7d6-5e34d58a4434
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191187414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.191187414
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2174656749
Short name T443
Test name
Test status
Simulation time 2112434844 ps
CPU time 59.14 seconds
Started Aug 15 05:09:10 PM PDT 24
Finished Aug 15 05:10:09 PM PDT 24
Peak memory 218264 kb
Host smart-5cd46675-64ed-4b34-baa0-d7427ab2125b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174656749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2174656749
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3935540704
Short name T467
Test name
Test status
Simulation time 352765663 ps
CPU time 11.38 seconds
Started Aug 15 05:09:09 PM PDT 24
Finished Aug 15 05:09:21 PM PDT 24
Peak memory 223240 kb
Host smart-541d8225-11e0-40d3-a228-2c3ca0bbb046
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935540704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3935540704
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2064020546
Short name T292
Test name
Test status
Simulation time 568752114 ps
CPU time 4.85 seconds
Started Aug 15 05:09:08 PM PDT 24
Finished Aug 15 05:09:13 PM PDT 24
Peak memory 217696 kb
Host smart-7467ca7e-0182-47a6-9699-76480616bf46
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064020546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2064020546
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1031299247
Short name T333
Test name
Test status
Simulation time 2107733126 ps
CPU time 76.66 seconds
Started Aug 15 05:09:08 PM PDT 24
Finished Aug 15 05:10:25 PM PDT 24
Peak memory 267296 kb
Host smart-92f7c8f8-9073-4b7d-b5f2-b012a4bd3f77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031299247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1031299247
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.605849657
Short name T603
Test name
Test status
Simulation time 849928304 ps
CPU time 8.77 seconds
Started Aug 15 05:09:11 PM PDT 24
Finished Aug 15 05:09:20 PM PDT 24
Peak memory 250464 kb
Host smart-3331b320-8891-4677-89d4-3f9e60ca51c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605849657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.605849657
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2751246571
Short name T290
Test name
Test status
Simulation time 286494647 ps
CPU time 4.02 seconds
Started Aug 15 05:09:09 PM PDT 24
Finished Aug 15 05:09:13 PM PDT 24
Peak memory 222580 kb
Host smart-52277dda-439b-4c8e-a05e-b9f26be5bf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751246571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2751246571
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1697770656
Short name T721
Test name
Test status
Simulation time 945771858 ps
CPU time 10.8 seconds
Started Aug 15 05:09:09 PM PDT 24
Finished Aug 15 05:09:20 PM PDT 24
Peak memory 218308 kb
Host smart-5130c72e-be06-4985-89d3-91cb2d15893d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697770656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1697770656
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2144555908
Short name T770
Test name
Test status
Simulation time 954710373 ps
CPU time 20.5 seconds
Started Aug 15 05:09:09 PM PDT 24
Finished Aug 15 05:09:29 PM PDT 24
Peak memory 225972 kb
Host smart-b37a7b85-68f3-40f0-a850-3ff52ecd4e0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144555908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2144555908
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.689603502
Short name T302
Test name
Test status
Simulation time 1520228553 ps
CPU time 12.06 seconds
Started Aug 15 05:09:12 PM PDT 24
Finished Aug 15 05:09:25 PM PDT 24
Peak memory 226016 kb
Host smart-040370ae-9414-4b1d-a955-cb9b3cf10043
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689603502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.689603502
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2646049042
Short name T768
Test name
Test status
Simulation time 1089970234 ps
CPU time 8.68 seconds
Started Aug 15 05:09:10 PM PDT 24
Finished Aug 15 05:09:18 PM PDT 24
Peak memory 218356 kb
Host smart-194db555-dffd-475d-8413-83d89999b35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646049042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2646049042
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3094222413
Short name T431
Test name
Test status
Simulation time 42238415 ps
CPU time 2.24 seconds
Started Aug 15 05:09:10 PM PDT 24
Finished Aug 15 05:09:12 PM PDT 24
Peak memory 214376 kb
Host smart-85050f9e-37b2-4706-8d75-b392f9572f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094222413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3094222413
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3294439579
Short name T790
Test name
Test status
Simulation time 787994120 ps
CPU time 32.92 seconds
Started Aug 15 05:09:10 PM PDT 24
Finished Aug 15 05:09:43 PM PDT 24
Peak memory 250972 kb
Host smart-1e1d4d12-8398-4df0-91b6-1966902b293c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294439579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3294439579
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1194603748
Short name T665
Test name
Test status
Simulation time 124813898 ps
CPU time 2.98 seconds
Started Aug 15 05:09:12 PM PDT 24
Finished Aug 15 05:09:15 PM PDT 24
Peak memory 226392 kb
Host smart-6c635cfb-6b99-4967-a5b1-b872fd1bd13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194603748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1194603748
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2622861981
Short name T833
Test name
Test status
Simulation time 56008482790 ps
CPU time 466.18 seconds
Started Aug 15 05:09:09 PM PDT 24
Finished Aug 15 05:16:56 PM PDT 24
Peak memory 250612 kb
Host smart-080f9b40-5b5f-4aa4-8b3c-e61e02d405ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622861981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2622861981
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2919895068
Short name T560
Test name
Test status
Simulation time 23166067 ps
CPU time 0.8 seconds
Started Aug 15 05:09:10 PM PDT 24
Finished Aug 15 05:09:11 PM PDT 24
Peak memory 208988 kb
Host smart-3e3f489d-2275-4d27-9174-1a8b3f0d6cff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919895068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2919895068
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1703994611
Short name T624
Test name
Test status
Simulation time 33463969 ps
CPU time 0.87 seconds
Started Aug 15 05:09:21 PM PDT 24
Finished Aug 15 05:09:22 PM PDT 24
Peak memory 209000 kb
Host smart-f6c13b8f-6a90-4700-8c93-68d06d6c72a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703994611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1703994611
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.185873999
Short name T723
Test name
Test status
Simulation time 752186551 ps
CPU time 8.59 seconds
Started Aug 15 05:09:18 PM PDT 24
Finished Aug 15 05:09:27 PM PDT 24
Peak memory 218244 kb
Host smart-0d36e68e-f7f6-4dfc-af2f-6099c4bd71c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185873999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.185873999
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1622294453
Short name T789
Test name
Test status
Simulation time 175404755 ps
CPU time 3.03 seconds
Started Aug 15 05:09:17 PM PDT 24
Finished Aug 15 05:09:21 PM PDT 24
Peak memory 217304 kb
Host smart-017d91a3-47c8-49d7-8898-9b0372063570
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622294453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1622294453
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.292124510
Short name T96
Test name
Test status
Simulation time 3300764795 ps
CPU time 84.23 seconds
Started Aug 15 05:09:17 PM PDT 24
Finished Aug 15 05:10:41 PM PDT 24
Peak memory 218348 kb
Host smart-ac12e03b-9af4-4085-bf25-b09a222fb3a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292124510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.292124510
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1139317308
Short name T301
Test name
Test status
Simulation time 828447543 ps
CPU time 5.75 seconds
Started Aug 15 05:09:18 PM PDT 24
Finished Aug 15 05:09:24 PM PDT 24
Peak memory 221764 kb
Host smart-7a2afa05-1dba-43a7-90ad-76e4f1917bd9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139317308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1139317308
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.529762986
Short name T7
Test name
Test status
Simulation time 191910913 ps
CPU time 3.98 seconds
Started Aug 15 05:09:20 PM PDT 24
Finished Aug 15 05:09:24 PM PDT 24
Peak memory 217708 kb
Host smart-088c3f26-8523-4d18-a4ef-d27e07f0634e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529762986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
529762986
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1675115285
Short name T714
Test name
Test status
Simulation time 2477282114 ps
CPU time 78.43 seconds
Started Aug 15 05:09:16 PM PDT 24
Finished Aug 15 05:10:35 PM PDT 24
Peak memory 254796 kb
Host smart-99799ddb-9610-4b3f-8dcf-9f80ee9770da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675115285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1675115285
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3845309355
Short name T318
Test name
Test status
Simulation time 328399205 ps
CPU time 10.58 seconds
Started Aug 15 05:09:23 PM PDT 24
Finished Aug 15 05:09:33 PM PDT 24
Peak memory 218224 kb
Host smart-1481ca4b-7f08-49b0-a1e8-b9dde3cef849
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845309355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3845309355
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1774446235
Short name T805
Test name
Test status
Simulation time 52368642 ps
CPU time 2.86 seconds
Started Aug 15 05:09:17 PM PDT 24
Finished Aug 15 05:09:20 PM PDT 24
Peak memory 218336 kb
Host smart-940b965c-9bc2-4f58-b3ec-5bea849abf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774446235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1774446235
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3026282279
Short name T813
Test name
Test status
Simulation time 2722816725 ps
CPU time 14.07 seconds
Started Aug 15 05:09:18 PM PDT 24
Finished Aug 15 05:09:33 PM PDT 24
Peak memory 226184 kb
Host smart-aadd6f33-217d-49a2-854c-293723b5725c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026282279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3026282279
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2228613255
Short name T391
Test name
Test status
Simulation time 995465213 ps
CPU time 12.05 seconds
Started Aug 15 05:09:18 PM PDT 24
Finished Aug 15 05:09:30 PM PDT 24
Peak memory 226084 kb
Host smart-87ebb3c0-2a22-43d4-8084-445ed5cef565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228613255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2228613255
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.4261316100
Short name T375
Test name
Test status
Simulation time 4092405361 ps
CPU time 9.7 seconds
Started Aug 15 05:09:17 PM PDT 24
Finished Aug 15 05:09:27 PM PDT 24
Peak memory 226132 kb
Host smart-fff5e91f-4e06-4449-a2c9-04f9c2993d45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261316100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
4261316100
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2176871645
Short name T98
Test name
Test status
Simulation time 1507828485 ps
CPU time 13.41 seconds
Started Aug 15 05:09:19 PM PDT 24
Finished Aug 15 05:09:33 PM PDT 24
Peak memory 218408 kb
Host smart-fcf7a8e8-d0ad-4a92-8e4f-93bc694fedb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176871645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2176871645
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1858487459
Short name T61
Test name
Test status
Simulation time 160769653 ps
CPU time 2.94 seconds
Started Aug 15 05:09:10 PM PDT 24
Finished Aug 15 05:09:13 PM PDT 24
Peak memory 214724 kb
Host smart-40294baa-4b8b-43f1-b3fe-3c3157b90dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858487459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1858487459
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3355382858
Short name T587
Test name
Test status
Simulation time 273213545 ps
CPU time 23.74 seconds
Started Aug 15 05:09:13 PM PDT 24
Finished Aug 15 05:09:37 PM PDT 24
Peak memory 250972 kb
Host smart-e7409cbd-a216-45ef-8005-b45c8cbc1fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355382858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3355382858
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1702726387
Short name T497
Test name
Test status
Simulation time 343571994 ps
CPU time 7.53 seconds
Started Aug 15 05:09:10 PM PDT 24
Finished Aug 15 05:09:18 PM PDT 24
Peak memory 250972 kb
Host smart-d6bc18bd-c8a3-4cfe-aac2-715da8582c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702726387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1702726387
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1121977770
Short name T353
Test name
Test status
Simulation time 5278327416 ps
CPU time 52.95 seconds
Started Aug 15 05:09:17 PM PDT 24
Finished Aug 15 05:10:10 PM PDT 24
Peak memory 268860 kb
Host smart-35e216f5-3244-42cc-a515-3e35f09bcf72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121977770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1121977770
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.322288577
Short name T62
Test name
Test status
Simulation time 45023269 ps
CPU time 0.87 seconds
Started Aug 15 05:09:11 PM PDT 24
Finished Aug 15 05:09:12 PM PDT 24
Peak memory 211928 kb
Host smart-6873e44f-1d09-4d75-9dd2-7234b2f3050b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322288577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.322288577
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.798265893
Short name T68
Test name
Test status
Simulation time 23276785 ps
CPU time 1.26 seconds
Started Aug 15 05:09:30 PM PDT 24
Finished Aug 15 05:09:32 PM PDT 24
Peak memory 209088 kb
Host smart-2d104582-e2b5-4fb2-9df9-ea44e0d4e51a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798265893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.798265893
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3413208180
Short name T611
Test name
Test status
Simulation time 3007515631 ps
CPU time 11.88 seconds
Started Aug 15 05:09:18 PM PDT 24
Finished Aug 15 05:09:30 PM PDT 24
Peak memory 219028 kb
Host smart-f0ca2715-3d9d-4500-89e2-f7065be847d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413208180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3413208180
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2734613260
Short name T187
Test name
Test status
Simulation time 1824034386 ps
CPU time 12.02 seconds
Started Aug 15 05:09:19 PM PDT 24
Finished Aug 15 05:09:31 PM PDT 24
Peak memory 217416 kb
Host smart-52ba7614-9287-407e-ad08-61fcadbd6071
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734613260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2734613260
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3229788631
Short name T622
Test name
Test status
Simulation time 1718327874 ps
CPU time 5.46 seconds
Started Aug 15 05:09:22 PM PDT 24
Finished Aug 15 05:09:28 PM PDT 24
Peak memory 217672 kb
Host smart-ceb0eecc-9769-44c8-969e-eda94ede098e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229788631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3229788631
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3178403629
Short name T410
Test name
Test status
Simulation time 887070341 ps
CPU time 34.53 seconds
Started Aug 15 05:09:19 PM PDT 24
Finished Aug 15 05:09:54 PM PDT 24
Peak memory 250864 kb
Host smart-1413cf13-86e8-4ff3-9a7e-d4c3c4829fb2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178403629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3178403629
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.4078184280
Short name T471
Test name
Test status
Simulation time 704176510 ps
CPU time 15.97 seconds
Started Aug 15 05:09:23 PM PDT 24
Finished Aug 15 05:09:39 PM PDT 24
Peak memory 250900 kb
Host smart-02422cec-a2ab-48ad-b131-3f6a95351daf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078184280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.4078184280
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3731948645
Short name T755
Test name
Test status
Simulation time 235352025 ps
CPU time 2.71 seconds
Started Aug 15 05:09:17 PM PDT 24
Finished Aug 15 05:09:20 PM PDT 24
Peak memory 222288 kb
Host smart-c988868f-8d32-45a8-95e6-c2da24f0b9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731948645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3731948645
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.756547684
Short name T369
Test name
Test status
Simulation time 224399251 ps
CPU time 8.99 seconds
Started Aug 15 05:09:18 PM PDT 24
Finished Aug 15 05:09:27 PM PDT 24
Peak memory 218336 kb
Host smart-15acf0c3-8f6c-4aef-b745-1695c1df8ca9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756547684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.756547684
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.392559219
Short name T277
Test name
Test status
Simulation time 3426626719 ps
CPU time 16.19 seconds
Started Aug 15 05:09:18 PM PDT 24
Finished Aug 15 05:09:34 PM PDT 24
Peak memory 218940 kb
Host smart-04e0f954-dca2-4d00-ba8d-83a49fc6e575
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392559219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.392559219
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3496888191
Short name T785
Test name
Test status
Simulation time 229062669 ps
CPU time 7.38 seconds
Started Aug 15 05:09:18 PM PDT 24
Finished Aug 15 05:09:26 PM PDT 24
Peak memory 226052 kb
Host smart-3898d6f0-8834-465f-9414-b77fa2818269
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496888191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3496888191
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.486903051
Short name T215
Test name
Test status
Simulation time 249743512 ps
CPU time 7.28 seconds
Started Aug 15 05:09:19 PM PDT 24
Finished Aug 15 05:09:27 PM PDT 24
Peak memory 218352 kb
Host smart-00fd8b5b-593c-4845-932d-a5f99b133f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486903051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.486903051
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3169759349
Short name T707
Test name
Test status
Simulation time 86518901 ps
CPU time 3.26 seconds
Started Aug 15 05:09:22 PM PDT 24
Finished Aug 15 05:09:26 PM PDT 24
Peak memory 217744 kb
Host smart-20baf38c-cd0a-46fb-aa33-91962b7b6e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169759349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3169759349
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2366392090
Short name T258
Test name
Test status
Simulation time 358384496 ps
CPU time 31.99 seconds
Started Aug 15 05:09:18 PM PDT 24
Finished Aug 15 05:09:51 PM PDT 24
Peak memory 250876 kb
Host smart-aab1c6bf-8b18-4dd2-9adb-c6d532a248f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366392090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2366392090
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.756271282
Short name T531
Test name
Test status
Simulation time 142116130 ps
CPU time 7.78 seconds
Started Aug 15 05:09:19 PM PDT 24
Finished Aug 15 05:09:27 PM PDT 24
Peak memory 248632 kb
Host smart-3f0eb077-3a8a-40a4-ab1e-95927d071462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756271282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.756271282
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2140535232
Short name T745
Test name
Test status
Simulation time 165976533627 ps
CPU time 137.29 seconds
Started Aug 15 05:09:28 PM PDT 24
Finished Aug 15 05:11:46 PM PDT 24
Peak memory 259284 kb
Host smart-7be68f2a-37cf-411b-bd2e-21877ec2c5bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140535232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2140535232
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2472556705
Short name T485
Test name
Test status
Simulation time 13405362 ps
CPU time 0.9 seconds
Started Aug 15 05:09:17 PM PDT 24
Finished Aug 15 05:09:18 PM PDT 24
Peak memory 208932 kb
Host smart-7fd43a7e-6db7-4c11-a402-cc46e4952b13
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472556705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2472556705
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1171681452
Short name T336
Test name
Test status
Simulation time 27260367 ps
CPU time 0.95 seconds
Started Aug 15 05:09:31 PM PDT 24
Finished Aug 15 05:09:32 PM PDT 24
Peak memory 208936 kb
Host smart-924744eb-4310-431d-994f-483eaa597282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171681452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1171681452
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2372682108
Short name T800
Test name
Test status
Simulation time 1013765830 ps
CPU time 8.53 seconds
Started Aug 15 05:09:26 PM PDT 24
Finished Aug 15 05:09:35 PM PDT 24
Peak memory 218336 kb
Host smart-63db1e04-b1a2-4d65-b034-1cba370ac5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372682108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2372682108
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.511104459
Short name T372
Test name
Test status
Simulation time 681648101 ps
CPU time 7.55 seconds
Started Aug 15 05:09:26 PM PDT 24
Finished Aug 15 05:09:34 PM PDT 24
Peak memory 217412 kb
Host smart-cccceb76-b915-4a3b-bb41-6c2c722edca9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511104459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.511104459
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2547900694
Short name T415
Test name
Test status
Simulation time 4836341230 ps
CPU time 39.96 seconds
Started Aug 15 05:09:27 PM PDT 24
Finished Aug 15 05:10:07 PM PDT 24
Peak memory 219072 kb
Host smart-a6794e13-54a5-4adc-aed6-043a658e4e49
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547900694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2547900694
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.656214310
Short name T761
Test name
Test status
Simulation time 63710176 ps
CPU time 2.84 seconds
Started Aug 15 05:09:26 PM PDT 24
Finished Aug 15 05:09:29 PM PDT 24
Peak memory 218236 kb
Host smart-0012d33e-c875-4bab-ad83-cacb605fa2d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656214310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.656214310
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1243976598
Short name T487
Test name
Test status
Simulation time 367961663 ps
CPU time 5.52 seconds
Started Aug 15 05:09:26 PM PDT 24
Finished Aug 15 05:09:32 PM PDT 24
Peak memory 217740 kb
Host smart-4240d576-d62f-49aa-ad28-b56c23bdefa9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243976598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1243976598
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1304898008
Short name T365
Test name
Test status
Simulation time 8881565105 ps
CPU time 50.89 seconds
Started Aug 15 05:09:28 PM PDT 24
Finished Aug 15 05:10:19 PM PDT 24
Peak memory 278416 kb
Host smart-3c42b1a3-f394-4c04-8d96-1eda39e2e575
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304898008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1304898008
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1956653517
Short name T499
Test name
Test status
Simulation time 365066496 ps
CPU time 13.61 seconds
Started Aug 15 05:09:27 PM PDT 24
Finished Aug 15 05:09:41 PM PDT 24
Peak memory 246056 kb
Host smart-36554da9-2c61-46fe-984f-243bd62786f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956653517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1956653517
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1621385862
Short name T769
Test name
Test status
Simulation time 30798521 ps
CPU time 1.73 seconds
Started Aug 15 05:09:31 PM PDT 24
Finished Aug 15 05:09:33 PM PDT 24
Peak memory 222144 kb
Host smart-fe3834d2-9fb4-4717-9731-2e2fe04e4d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621385862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1621385862
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1188968271
Short name T680
Test name
Test status
Simulation time 251655746 ps
CPU time 12.84 seconds
Started Aug 15 05:09:26 PM PDT 24
Finished Aug 15 05:09:39 PM PDT 24
Peak memory 226148 kb
Host smart-dad918a0-f7cb-41d7-8d00-dcfdc2617a3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188968271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1188968271
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.4001143551
Short name T752
Test name
Test status
Simulation time 832345416 ps
CPU time 10.74 seconds
Started Aug 15 05:09:26 PM PDT 24
Finished Aug 15 05:09:37 PM PDT 24
Peak memory 218296 kb
Host smart-c45996d4-7aeb-495d-83a0-97c1e7afe7c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001143551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
4001143551
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.370543371
Short name T492
Test name
Test status
Simulation time 1029832302 ps
CPU time 9.9 seconds
Started Aug 15 05:09:29 PM PDT 24
Finished Aug 15 05:09:39 PM PDT 24
Peak memory 218392 kb
Host smart-1379a2ff-e70f-43ae-a8da-2ce9c52a642b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370543371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.370543371
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.401682324
Short name T473
Test name
Test status
Simulation time 30960327 ps
CPU time 1.54 seconds
Started Aug 15 05:09:27 PM PDT 24
Finished Aug 15 05:09:29 PM PDT 24
Peak memory 217700 kb
Host smart-7520ca70-f86d-4b39-85d5-a734145828cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401682324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.401682324
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2746962174
Short name T541
Test name
Test status
Simulation time 1016248258 ps
CPU time 29.84 seconds
Started Aug 15 05:09:26 PM PDT 24
Finished Aug 15 05:09:56 PM PDT 24
Peak memory 250948 kb
Host smart-a7129c2d-74c2-4fb9-ba72-8dc8f104d6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746962174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2746962174
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1595151780
Short name T432
Test name
Test status
Simulation time 40222921 ps
CPU time 2.99 seconds
Started Aug 15 05:09:30 PM PDT 24
Finished Aug 15 05:09:33 PM PDT 24
Peak memory 222528 kb
Host smart-b0589ef7-f545-4980-8699-7003f7a7c817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595151780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1595151780
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2628079907
Short name T731
Test name
Test status
Simulation time 30970658130 ps
CPU time 212.09 seconds
Started Aug 15 05:09:27 PM PDT 24
Finished Aug 15 05:13:00 PM PDT 24
Peak memory 240172 kb
Host smart-2add9442-41ae-4cea-a457-176c5cc39c2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628079907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2628079907
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2699115171
Short name T791
Test name
Test status
Simulation time 3157245803 ps
CPU time 57.11 seconds
Started Aug 15 05:09:26 PM PDT 24
Finished Aug 15 05:10:24 PM PDT 24
Peak memory 270568 kb
Host smart-fe03cd65-e1fc-4386-8a7a-33fdaf543f6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2699115171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2699115171
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3693105365
Short name T544
Test name
Test status
Simulation time 41182351 ps
CPU time 0.87 seconds
Started Aug 15 05:09:25 PM PDT 24
Finished Aug 15 05:09:26 PM PDT 24
Peak memory 208648 kb
Host smart-953e86df-2dfc-47ee-a156-08fb0b3c2f34
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693105365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3693105365
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3587882455
Short name T501
Test name
Test status
Simulation time 38950785 ps
CPU time 0.85 seconds
Started Aug 15 05:07:36 PM PDT 24
Finished Aug 15 05:07:37 PM PDT 24
Peak memory 208828 kb
Host smart-9e7b1d9c-1710-44f7-bd2c-6758af3cf155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587882455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3587882455
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1251582819
Short name T360
Test name
Test status
Simulation time 10814268 ps
CPU time 0.84 seconds
Started Aug 15 05:07:37 PM PDT 24
Finished Aug 15 05:07:38 PM PDT 24
Peak memory 209072 kb
Host smart-0fffc761-6e39-4824-a8f8-5afe243234e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251582819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1251582819
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3377148102
Short name T384
Test name
Test status
Simulation time 468889092 ps
CPU time 16.67 seconds
Started Aug 15 05:07:37 PM PDT 24
Finished Aug 15 05:07:54 PM PDT 24
Peak memory 218132 kb
Host smart-31a1f524-81b6-4fcc-acd5-448f9f7e7004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377148102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3377148102
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2745417797
Short name T316
Test name
Test status
Simulation time 54577417 ps
CPU time 2.14 seconds
Started Aug 15 05:07:36 PM PDT 24
Finished Aug 15 05:07:38 PM PDT 24
Peak memory 217156 kb
Host smart-c4fc24d2-68a1-4c90-aa0c-a30ef6b1e85f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745417797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2745417797
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3448000731
Short name T359
Test name
Test status
Simulation time 2334640481 ps
CPU time 36.19 seconds
Started Aug 15 05:07:35 PM PDT 24
Finished Aug 15 05:08:12 PM PDT 24
Peak memory 218328 kb
Host smart-514caa5e-c72d-4d6c-a5aa-341ce3ddb739
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448000731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3448000731
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1427290919
Short name T600
Test name
Test status
Simulation time 820251993 ps
CPU time 5.55 seconds
Started Aug 15 05:07:34 PM PDT 24
Finished Aug 15 05:07:39 PM PDT 24
Peak memory 217876 kb
Host smart-108d4e4d-87a0-4d09-9de7-8d694bb92c14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427290919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
427290919
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3571306903
Short name T860
Test name
Test status
Simulation time 300598530 ps
CPU time 6.12 seconds
Started Aug 15 05:07:35 PM PDT 24
Finished Aug 15 05:07:42 PM PDT 24
Peak memory 218360 kb
Host smart-9d0977f2-574a-429c-aa7f-3dca7438b7a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571306903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3571306903
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2426321000
Short name T801
Test name
Test status
Simulation time 809507581 ps
CPU time 25.26 seconds
Started Aug 15 05:07:33 PM PDT 24
Finished Aug 15 05:07:59 PM PDT 24
Peak memory 217704 kb
Host smart-5bfb8de4-b409-45a1-ac02-9af62c616c76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426321000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2426321000
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1738489848
Short name T243
Test name
Test status
Simulation time 447508151 ps
CPU time 4.27 seconds
Started Aug 15 05:07:37 PM PDT 24
Finished Aug 15 05:07:41 PM PDT 24
Peak memory 217672 kb
Host smart-fc7b3257-de60-4c47-9f30-fbdc1099fc9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738489848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1738489848
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3527513705
Short name T700
Test name
Test status
Simulation time 876820156 ps
CPU time 49.24 seconds
Started Aug 15 05:07:35 PM PDT 24
Finished Aug 15 05:08:24 PM PDT 24
Peak memory 250864 kb
Host smart-af5ca494-91c4-4819-9997-5c5623d84c1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527513705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3527513705
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1201273406
Short name T313
Test name
Test status
Simulation time 314438816 ps
CPU time 10.46 seconds
Started Aug 15 05:07:37 PM PDT 24
Finished Aug 15 05:07:47 PM PDT 24
Peak memory 222912 kb
Host smart-75b99c90-6871-43fc-a1f2-998971082592
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201273406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1201273406
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1284184594
Short name T644
Test name
Test status
Simulation time 191153041 ps
CPU time 4.14 seconds
Started Aug 15 05:07:36 PM PDT 24
Finished Aug 15 05:07:41 PM PDT 24
Peak memory 222804 kb
Host smart-39409afb-0ea7-499f-8110-45b0ad2ac3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284184594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1284184594
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.185499512
Short name T773
Test name
Test status
Simulation time 764266484 ps
CPU time 13.06 seconds
Started Aug 15 05:07:36 PM PDT 24
Finished Aug 15 05:07:49 PM PDT 24
Peak memory 214052 kb
Host smart-53a17718-f56a-45ca-9f31-97997c1bd0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185499512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.185499512
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1752972142
Short name T51
Test name
Test status
Simulation time 846902338 ps
CPU time 40.02 seconds
Started Aug 15 05:07:38 PM PDT 24
Finished Aug 15 05:08:18 PM PDT 24
Peak memory 283652 kb
Host smart-41495e46-c231-4cfe-81f9-30a8fb1e463c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752972142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1752972142
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2096401315
Short name T251
Test name
Test status
Simulation time 1614209609 ps
CPU time 16.92 seconds
Started Aug 15 05:07:36 PM PDT 24
Finished Aug 15 05:07:53 PM PDT 24
Peak memory 226104 kb
Host smart-98497458-dae1-4abc-b4df-b81b92595080
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096401315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2096401315
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1313680896
Short name T853
Test name
Test status
Simulation time 475335993 ps
CPU time 13 seconds
Started Aug 15 05:07:35 PM PDT 24
Finished Aug 15 05:07:48 PM PDT 24
Peak memory 226076 kb
Host smart-8c66c666-e16f-44b8-815b-4d68f2eca60b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313680896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1313680896
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2409147621
Short name T298
Test name
Test status
Simulation time 786452029 ps
CPU time 14.63 seconds
Started Aug 15 05:07:37 PM PDT 24
Finished Aug 15 05:07:52 PM PDT 24
Peak memory 225944 kb
Host smart-d605ee4b-30b2-4692-a707-0b5dce152ffb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409147621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
409147621
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.381536378
Short name T469
Test name
Test status
Simulation time 226748640 ps
CPU time 6.27 seconds
Started Aug 15 05:07:35 PM PDT 24
Finished Aug 15 05:07:41 PM PDT 24
Peak memory 218316 kb
Host smart-f7c84927-2bf9-4a1c-b607-d5ee4db1234a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381536378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.381536378
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3746391633
Short name T824
Test name
Test status
Simulation time 39434488 ps
CPU time 1.58 seconds
Started Aug 15 05:07:34 PM PDT 24
Finished Aug 15 05:07:36 PM PDT 24
Peak memory 217760 kb
Host smart-7974125a-90ca-429c-a11b-e516201be477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746391633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3746391633
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.695249156
Short name T106
Test name
Test status
Simulation time 1678279497 ps
CPU time 29.79 seconds
Started Aug 15 05:07:37 PM PDT 24
Finished Aug 15 05:08:07 PM PDT 24
Peak memory 250932 kb
Host smart-a024fdae-8d90-4b60-847b-62812d8796a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695249156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.695249156
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.787305091
Short name T618
Test name
Test status
Simulation time 323180214 ps
CPU time 7.49 seconds
Started Aug 15 05:07:35 PM PDT 24
Finished Aug 15 05:07:43 PM PDT 24
Peak memory 247004 kb
Host smart-924c9db2-baec-47b6-b37b-16056a4c20d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787305091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.787305091
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1091459248
Short name T38
Test name
Test status
Simulation time 23776151990 ps
CPU time 77.88 seconds
Started Aug 15 05:07:36 PM PDT 24
Finished Aug 15 05:08:54 PM PDT 24
Peak memory 267388 kb
Host smart-0ab05ba1-0068-48f8-a497-b2dd23c79fb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091459248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1091459248
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.124655573
Short name T204
Test name
Test status
Simulation time 9432742712 ps
CPU time 109.42 seconds
Started Aug 15 05:07:37 PM PDT 24
Finished Aug 15 05:09:27 PM PDT 24
Peak memory 273496 kb
Host smart-d82cbe30-0077-4372-8491-48a0499ccab7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=124655573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.124655573
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2914415097
Short name T825
Test name
Test status
Simulation time 26485557 ps
CPU time 0.84 seconds
Started Aug 15 05:07:36 PM PDT 24
Finished Aug 15 05:07:37 PM PDT 24
Peak memory 209084 kb
Host smart-86d22315-16ed-4114-bcdb-5791e3676146
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914415097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2914415097
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.510328695
Short name T85
Test name
Test status
Simulation time 112001058 ps
CPU time 1.06 seconds
Started Aug 15 05:09:36 PM PDT 24
Finished Aug 15 05:09:37 PM PDT 24
Peak memory 209084 kb
Host smart-79ed0edd-ff00-44d8-9ec6-3456b1e1caea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510328695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.510328695
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1840527048
Short name T413
Test name
Test status
Simulation time 1262723128 ps
CPU time 14.23 seconds
Started Aug 15 05:09:26 PM PDT 24
Finished Aug 15 05:09:41 PM PDT 24
Peak memory 218200 kb
Host smart-63872f62-616d-463e-8a5b-e72aa41ed16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840527048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1840527048
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.4046286373
Short name T510
Test name
Test status
Simulation time 904405317 ps
CPU time 6.01 seconds
Started Aug 15 05:09:37 PM PDT 24
Finished Aug 15 05:09:43 PM PDT 24
Peak memory 217528 kb
Host smart-ba3f5b80-f2ac-4b60-a7d1-e9a52956958e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046286373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.4046286373
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2292382847
Short name T99
Test name
Test status
Simulation time 41843741 ps
CPU time 1.53 seconds
Started Aug 15 05:09:30 PM PDT 24
Finished Aug 15 05:09:31 PM PDT 24
Peak memory 222000 kb
Host smart-0f176708-44be-4a5e-aada-fc7a32865520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292382847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2292382847
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.4207808711
Short name T794
Test name
Test status
Simulation time 377021560 ps
CPU time 15.68 seconds
Started Aug 15 05:09:37 PM PDT 24
Finished Aug 15 05:09:53 PM PDT 24
Peak memory 226140 kb
Host smart-8ac885a6-807b-4a62-815c-f76510c8ba3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207808711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.4207808711
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.502183667
Short name T677
Test name
Test status
Simulation time 576025364 ps
CPU time 15.1 seconds
Started Aug 15 05:09:36 PM PDT 24
Finished Aug 15 05:09:51 PM PDT 24
Peak memory 226076 kb
Host smart-864f4a19-c1d7-43b6-ba5e-47d7e9a7d617
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502183667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.502183667
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.302473882
Short name T166
Test name
Test status
Simulation time 2545530235 ps
CPU time 7.46 seconds
Started Aug 15 05:09:35 PM PDT 24
Finished Aug 15 05:09:43 PM PDT 24
Peak memory 218328 kb
Host smart-f684a8e0-1c40-47eb-bb2a-1a56f3f5371b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302473882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.302473882
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.169848693
Short name T638
Test name
Test status
Simulation time 719233314 ps
CPU time 9.25 seconds
Started Aug 15 05:09:25 PM PDT 24
Finished Aug 15 05:09:34 PM PDT 24
Peak memory 218372 kb
Host smart-a5b6b0a8-1b1b-481e-bb4e-2d3c43ac2704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169848693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.169848693
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1818288337
Short name T818
Test name
Test status
Simulation time 404227339 ps
CPU time 5.35 seconds
Started Aug 15 05:09:26 PM PDT 24
Finished Aug 15 05:09:31 PM PDT 24
Peak memory 217736 kb
Host smart-8367e94d-2a15-498c-a446-5b5525881786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818288337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1818288337
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3860195391
Short name T181
Test name
Test status
Simulation time 888807667 ps
CPU time 24.31 seconds
Started Aug 15 05:09:27 PM PDT 24
Finished Aug 15 05:09:52 PM PDT 24
Peak memory 245724 kb
Host smart-db309296-1c49-42c6-8e90-32a011732e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860195391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3860195391
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3424183845
Short name T703
Test name
Test status
Simulation time 56866197 ps
CPU time 5.96 seconds
Started Aug 15 05:09:26 PM PDT 24
Finished Aug 15 05:09:33 PM PDT 24
Peak memory 246312 kb
Host smart-0ad587b6-b3e8-44cf-ab67-b9d6b9d1e31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424183845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3424183845
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2743604709
Short name T713
Test name
Test status
Simulation time 2905962863 ps
CPU time 25.25 seconds
Started Aug 15 05:09:36 PM PDT 24
Finished Aug 15 05:10:02 PM PDT 24
Peak memory 250672 kb
Host smart-03f780d8-6872-4096-be0f-8b125dd4ee4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743604709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2743604709
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1974106464
Short name T685
Test name
Test status
Simulation time 23970028 ps
CPU time 0.8 seconds
Started Aug 15 05:09:26 PM PDT 24
Finished Aug 15 05:09:27 PM PDT 24
Peak memory 208976 kb
Host smart-887891d9-b8fe-43a3-a256-7dca12f665c3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974106464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1974106464
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2341349669
Short name T822
Test name
Test status
Simulation time 133896475 ps
CPU time 1.06 seconds
Started Aug 15 05:09:43 PM PDT 24
Finished Aug 15 05:09:45 PM PDT 24
Peak memory 208936 kb
Host smart-5629c735-3e65-48db-8c59-c961c8bb306e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341349669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2341349669
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3524424177
Short name T381
Test name
Test status
Simulation time 296524318 ps
CPU time 8.89 seconds
Started Aug 15 05:09:36 PM PDT 24
Finished Aug 15 05:09:45 PM PDT 24
Peak memory 218328 kb
Host smart-26694834-c534-4e51-ba98-5aa905806512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524424177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3524424177
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3782063928
Short name T326
Test name
Test status
Simulation time 2104944656 ps
CPU time 4.25 seconds
Started Aug 15 05:09:37 PM PDT 24
Finished Aug 15 05:09:42 PM PDT 24
Peak memory 217160 kb
Host smart-fb4b7cad-59ca-4785-96a0-27bfcdec2b74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782063928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3782063928
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3871600839
Short name T428
Test name
Test status
Simulation time 854107360 ps
CPU time 3.18 seconds
Started Aug 15 05:09:37 PM PDT 24
Finished Aug 15 05:09:40 PM PDT 24
Peak memory 218324 kb
Host smart-08f729df-55fa-4897-ad2a-fcf232e0ecd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871600839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3871600839
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.822101527
Short name T516
Test name
Test status
Simulation time 620151822 ps
CPU time 11.85 seconds
Started Aug 15 05:09:37 PM PDT 24
Finished Aug 15 05:09:49 PM PDT 24
Peak memory 226144 kb
Host smart-c620ab97-93a2-4604-9efb-7887d1a1fb62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822101527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.822101527
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1821649380
Short name T666
Test name
Test status
Simulation time 275263248 ps
CPU time 11.45 seconds
Started Aug 15 05:09:45 PM PDT 24
Finished Aug 15 05:09:56 PM PDT 24
Peak memory 218244 kb
Host smart-a63f29dd-740a-4c73-b0a8-c42f9403bf0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821649380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1821649380
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.955761263
Short name T772
Test name
Test status
Simulation time 262564081 ps
CPU time 9.31 seconds
Started Aug 15 05:09:37 PM PDT 24
Finished Aug 15 05:09:47 PM PDT 24
Peak memory 218260 kb
Host smart-ace354e7-c4b5-4c38-a7b7-6f05b58d7d84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955761263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.955761263
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2383094087
Short name T403
Test name
Test status
Simulation time 4255212940 ps
CPU time 10.29 seconds
Started Aug 15 05:09:34 PM PDT 24
Finished Aug 15 05:09:44 PM PDT 24
Peak memory 218496 kb
Host smart-a4a559e4-72d1-4083-bfec-98a4005c481c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383094087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2383094087
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1936183439
Short name T784
Test name
Test status
Simulation time 35725785 ps
CPU time 1.39 seconds
Started Aug 15 05:09:37 PM PDT 24
Finished Aug 15 05:09:38 PM PDT 24
Peak memory 213820 kb
Host smart-36258cff-541a-4994-9ffa-ac8daa8511f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936183439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1936183439
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1499871933
Short name T262
Test name
Test status
Simulation time 192801626 ps
CPU time 26.54 seconds
Started Aug 15 05:09:34 PM PDT 24
Finished Aug 15 05:10:01 PM PDT 24
Peak memory 250936 kb
Host smart-548a4014-0a14-4cd6-b3a3-ae4b5dea56a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499871933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1499871933
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2138955545
Short name T592
Test name
Test status
Simulation time 233975694 ps
CPU time 3.69 seconds
Started Aug 15 05:09:35 PM PDT 24
Finished Aug 15 05:09:39 PM PDT 24
Peak memory 222412 kb
Host smart-0e7b0aed-dad6-495d-ae1a-b22a1a8d1531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138955545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2138955545
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3143503876
Short name T740
Test name
Test status
Simulation time 16878804009 ps
CPU time 69.83 seconds
Started Aug 15 05:09:36 PM PDT 24
Finished Aug 15 05:10:46 PM PDT 24
Peak memory 269088 kb
Host smart-c8f6236c-752b-42ee-92b3-468979e8833e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143503876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3143503876
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1282894450
Short name T163
Test name
Test status
Simulation time 20304439 ps
CPU time 1.01 seconds
Started Aug 15 05:09:41 PM PDT 24
Finished Aug 15 05:09:42 PM PDT 24
Peak memory 212052 kb
Host smart-6c3a208b-8016-43b9-8147-6be79060fbdf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282894450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1282894450
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.852162144
Short name T474
Test name
Test status
Simulation time 21135866 ps
CPU time 1.21 seconds
Started Aug 15 05:09:37 PM PDT 24
Finished Aug 15 05:09:39 PM PDT 24
Peak memory 209104 kb
Host smart-52cdf47c-9af4-4e9a-97dd-dab6bc8acd14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852162144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.852162144
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1162378358
Short name T235
Test name
Test status
Simulation time 304322910 ps
CPU time 14.17 seconds
Started Aug 15 05:09:37 PM PDT 24
Finished Aug 15 05:09:51 PM PDT 24
Peak memory 218344 kb
Host smart-2c553c04-2edd-49b8-9b36-af747b8a6ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162378358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1162378358
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2459040131
Short name T574
Test name
Test status
Simulation time 4275480326 ps
CPU time 6.47 seconds
Started Aug 15 05:09:36 PM PDT 24
Finished Aug 15 05:09:43 PM PDT 24
Peak memory 217764 kb
Host smart-abb1948b-73a8-4e0d-a57a-359f5e323a8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459040131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2459040131
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2518708192
Short name T743
Test name
Test status
Simulation time 487478986 ps
CPU time 2.98 seconds
Started Aug 15 05:09:36 PM PDT 24
Finished Aug 15 05:09:40 PM PDT 24
Peak memory 218280 kb
Host smart-8113e4c6-3b64-4f4b-a067-288fac8d0cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518708192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2518708192
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.541657958
Short name T742
Test name
Test status
Simulation time 1563547068 ps
CPU time 16.72 seconds
Started Aug 15 05:09:37 PM PDT 24
Finished Aug 15 05:09:54 PM PDT 24
Peak memory 219068 kb
Host smart-fca9fe98-d7ee-429b-a545-f0ea495b7572
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541657958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.541657958
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1501458756
Short name T15
Test name
Test status
Simulation time 382924289 ps
CPU time 12.54 seconds
Started Aug 15 05:09:43 PM PDT 24
Finished Aug 15 05:09:56 PM PDT 24
Peak memory 226052 kb
Host smart-76990018-4799-4ef7-bfd6-e46f7f1332e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501458756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1501458756
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2889283533
Short name T712
Test name
Test status
Simulation time 322198216 ps
CPU time 7.24 seconds
Started Aug 15 05:09:36 PM PDT 24
Finished Aug 15 05:09:43 PM PDT 24
Peak memory 218224 kb
Host smart-1e2d7552-190e-409e-9e9c-d292b94287eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889283533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2889283533
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1130384217
Short name T401
Test name
Test status
Simulation time 1241740633 ps
CPU time 10.94 seconds
Started Aug 15 05:09:41 PM PDT 24
Finished Aug 15 05:09:52 PM PDT 24
Peak memory 218392 kb
Host smart-21e642c8-aa23-48f8-b286-8f8c1b1646d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130384217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1130384217
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3822919854
Short name T504
Test name
Test status
Simulation time 114653432 ps
CPU time 3.02 seconds
Started Aug 15 05:09:37 PM PDT 24
Finished Aug 15 05:09:40 PM PDT 24
Peak memory 223316 kb
Host smart-5e136751-57cc-40a6-bdb9-9fba8f9bc8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822919854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3822919854
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.110570528
Short name T226
Test name
Test status
Simulation time 204227742 ps
CPU time 26.87 seconds
Started Aug 15 05:09:37 PM PDT 24
Finished Aug 15 05:10:04 PM PDT 24
Peak memory 250948 kb
Host smart-c19abf44-c83c-4bd7-a963-65930e9f8c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110570528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.110570528
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.745741250
Short name T297
Test name
Test status
Simulation time 92799349 ps
CPU time 3.79 seconds
Started Aug 15 05:09:41 PM PDT 24
Finished Aug 15 05:09:45 PM PDT 24
Peak memory 226368 kb
Host smart-06faf76c-1032-4b6e-9311-2041e9bbd89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745741250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.745741250
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2988186060
Short name T179
Test name
Test status
Simulation time 6702703190 ps
CPU time 79.84 seconds
Started Aug 15 05:09:43 PM PDT 24
Finished Aug 15 05:11:03 PM PDT 24
Peak memory 276604 kb
Host smart-b3cf2c0e-cd65-4861-8321-c584ed88ade8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988186060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2988186060
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3530614452
Short name T77
Test name
Test status
Simulation time 19850622 ps
CPU time 1.06 seconds
Started Aug 15 05:09:35 PM PDT 24
Finished Aug 15 05:09:36 PM PDT 24
Peak memory 212040 kb
Host smart-70e3fc58-bc6f-4c2f-85f9-ef4706caa477
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530614452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3530614452
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1399928716
Short name T826
Test name
Test status
Simulation time 24219376 ps
CPU time 1.37 seconds
Started Aug 15 05:09:43 PM PDT 24
Finished Aug 15 05:09:45 PM PDT 24
Peak memory 209112 kb
Host smart-0be83739-d588-495d-9984-d9815b46637b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399928716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1399928716
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.145328972
Short name T329
Test name
Test status
Simulation time 246179642 ps
CPU time 8.19 seconds
Started Aug 15 05:09:44 PM PDT 24
Finished Aug 15 05:09:52 PM PDT 24
Peak memory 218260 kb
Host smart-706f982b-e817-4f3c-b288-b44b47df0527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145328972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.145328972
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1528493005
Short name T542
Test name
Test status
Simulation time 118008694 ps
CPU time 3.59 seconds
Started Aug 15 05:09:45 PM PDT 24
Finished Aug 15 05:09:49 PM PDT 24
Peak memory 217756 kb
Host smart-4ee5f0b6-6051-4833-bc43-9aab1ce6deab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528493005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1528493005
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3377011279
Short name T719
Test name
Test status
Simulation time 485696910 ps
CPU time 3.52 seconds
Started Aug 15 05:09:43 PM PDT 24
Finished Aug 15 05:09:47 PM PDT 24
Peak memory 218268 kb
Host smart-03a14634-1ea2-475e-9601-c9dcb64bd361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377011279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3377011279
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1387611713
Short name T219
Test name
Test status
Simulation time 422337545 ps
CPU time 17.55 seconds
Started Aug 15 05:09:43 PM PDT 24
Finished Aug 15 05:10:01 PM PDT 24
Peak memory 218848 kb
Host smart-17ccc9f2-b2f4-4339-846b-e3375f6e0d63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387611713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1387611713
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1481207192
Short name T239
Test name
Test status
Simulation time 2244361950 ps
CPU time 9.77 seconds
Started Aug 15 05:09:46 PM PDT 24
Finished Aug 15 05:09:56 PM PDT 24
Peak memory 226144 kb
Host smart-0acd482c-a423-4424-aec9-d8b497f69fdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481207192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1481207192
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.663427063
Short name T423
Test name
Test status
Simulation time 450572892 ps
CPU time 10.54 seconds
Started Aug 15 05:09:45 PM PDT 24
Finished Aug 15 05:09:56 PM PDT 24
Peak memory 226052 kb
Host smart-1abbc93f-ec9a-4bbd-804e-a3aa6450edce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663427063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.663427063
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1125960464
Short name T275
Test name
Test status
Simulation time 2286878209 ps
CPU time 8.53 seconds
Started Aug 15 05:09:43 PM PDT 24
Finished Aug 15 05:09:52 PM PDT 24
Peak memory 218428 kb
Host smart-16f7ae25-33a4-4ddc-ba23-3325b3136161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125960464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1125960464
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2238971153
Short name T751
Test name
Test status
Simulation time 138952178 ps
CPU time 5.81 seconds
Started Aug 15 05:09:36 PM PDT 24
Finished Aug 15 05:09:42 PM PDT 24
Peak memory 217716 kb
Host smart-59f89bab-0e25-4249-83ce-49b4caa3fd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238971153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2238971153
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3497134669
Short name T225
Test name
Test status
Simulation time 1280611064 ps
CPU time 31.18 seconds
Started Aug 15 05:09:48 PM PDT 24
Finished Aug 15 05:10:19 PM PDT 24
Peak memory 250948 kb
Host smart-22d66087-1e80-43a8-8388-8a7d5b30af7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497134669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3497134669
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.1866718151
Short name T750
Test name
Test status
Simulation time 255237585 ps
CPU time 6.82 seconds
Started Aug 15 05:09:48 PM PDT 24
Finished Aug 15 05:09:55 PM PDT 24
Peak memory 245980 kb
Host smart-38a01051-0f86-48c9-841f-cbdb7c3f9427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866718151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1866718151
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2311153369
Short name T92
Test name
Test status
Simulation time 15649682645 ps
CPU time 656.88 seconds
Started Aug 15 05:09:44 PM PDT 24
Finished Aug 15 05:20:41 PM PDT 24
Peak memory 267388 kb
Host smart-537c86cd-89a5-4872-97fd-e9679f7ca2fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311153369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2311153369
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2219193820
Short name T850
Test name
Test status
Simulation time 92961037 ps
CPU time 0.91 seconds
Started Aug 15 05:09:38 PM PDT 24
Finished Aug 15 05:09:39 PM PDT 24
Peak memory 211996 kb
Host smart-c6e416c6-2e7f-44d4-9c89-c1154c2957e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219193820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2219193820
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.527396749
Short name T705
Test name
Test status
Simulation time 88467619 ps
CPU time 1.09 seconds
Started Aug 15 05:09:45 PM PDT 24
Finished Aug 15 05:09:46 PM PDT 24
Peak memory 209120 kb
Host smart-87fe4034-f5f4-460d-9560-0b0d5a2277cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527396749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.527396749
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2546205183
Short name T864
Test name
Test status
Simulation time 3941343800 ps
CPU time 11.04 seconds
Started Aug 15 05:09:46 PM PDT 24
Finished Aug 15 05:09:57 PM PDT 24
Peak memory 226172 kb
Host smart-216aaf68-293e-4dd0-9d58-0fcfc8819130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546205183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2546205183
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2908805642
Short name T289
Test name
Test status
Simulation time 148600676 ps
CPU time 2.64 seconds
Started Aug 15 05:09:47 PM PDT 24
Finished Aug 15 05:09:49 PM PDT 24
Peak memory 217808 kb
Host smart-830c9849-b76a-45d7-9bca-24d5f0f45cc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908805642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2908805642
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2560229188
Short name T273
Test name
Test status
Simulation time 260181148 ps
CPU time 3.76 seconds
Started Aug 15 05:09:44 PM PDT 24
Finished Aug 15 05:09:48 PM PDT 24
Peak memory 218360 kb
Host smart-3f87e6a9-3f6f-454c-98c3-82d20cde341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560229188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2560229188
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1154279128
Short name T506
Test name
Test status
Simulation time 800945595 ps
CPU time 14.35 seconds
Started Aug 15 05:09:42 PM PDT 24
Finished Aug 15 05:09:57 PM PDT 24
Peak memory 226036 kb
Host smart-bd032919-495e-483e-9b23-2b7281b3cfa8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154279128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1154279128
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.996134320
Short name T54
Test name
Test status
Simulation time 522913519 ps
CPU time 6.65 seconds
Started Aug 15 05:09:45 PM PDT 24
Finished Aug 15 05:09:52 PM PDT 24
Peak memory 218296 kb
Host smart-d1f350ff-c331-41cd-af7b-466c1e26f361
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996134320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.996134320
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2712443956
Short name T760
Test name
Test status
Simulation time 6432099287 ps
CPU time 11.93 seconds
Started Aug 15 05:09:45 PM PDT 24
Finished Aug 15 05:09:57 PM PDT 24
Peak memory 218452 kb
Host smart-aa410b64-0623-4a8e-bac2-933ad83465d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712443956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2712443956
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.476259920
Short name T581
Test name
Test status
Simulation time 107156155 ps
CPU time 1.39 seconds
Started Aug 15 05:09:45 PM PDT 24
Finished Aug 15 05:09:47 PM PDT 24
Peak memory 217728 kb
Host smart-401aefe8-c2f3-4d86-8f06-d90b66a379bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476259920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.476259920
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2264299519
Short name T176
Test name
Test status
Simulation time 982614074 ps
CPU time 26.99 seconds
Started Aug 15 05:09:46 PM PDT 24
Finished Aug 15 05:10:13 PM PDT 24
Peak memory 250864 kb
Host smart-01463c3a-7656-4de9-b67b-90df85cd7772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264299519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2264299519
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.187322613
Short name T588
Test name
Test status
Simulation time 171032884 ps
CPU time 7.97 seconds
Started Aug 15 05:09:48 PM PDT 24
Finished Aug 15 05:09:56 PM PDT 24
Peak memory 250784 kb
Host smart-f75ee866-4285-4bb7-8faa-ca0f558d9461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187322613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.187322613
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3623790108
Short name T67
Test name
Test status
Simulation time 50915919223 ps
CPU time 176.1 seconds
Started Aug 15 05:09:42 PM PDT 24
Finished Aug 15 05:12:39 PM PDT 24
Peak memory 282644 kb
Host smart-c10a36b3-fa96-4f55-9241-410e87faf49b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623790108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3623790108
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2323177961
Short name T590
Test name
Test status
Simulation time 15838369 ps
CPU time 0.82 seconds
Started Aug 15 05:09:44 PM PDT 24
Finished Aug 15 05:09:45 PM PDT 24
Peak memory 208888 kb
Host smart-5903dffd-e3a0-44f9-9b29-f26a17ca489b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323177961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2323177961
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.309779376
Short name T385
Test name
Test status
Simulation time 51717643 ps
CPU time 0.88 seconds
Started Aug 15 05:09:54 PM PDT 24
Finished Aug 15 05:09:55 PM PDT 24
Peak memory 208860 kb
Host smart-30c1220e-3a12-47a0-8795-1fe18bb8f085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309779376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.309779376
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3251886407
Short name T494
Test name
Test status
Simulation time 457580614 ps
CPU time 11.9 seconds
Started Aug 15 05:09:45 PM PDT 24
Finished Aug 15 05:09:57 PM PDT 24
Peak memory 218320 kb
Host smart-271a5481-b041-4736-9ed7-ff8535b8681d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251886407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3251886407
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.352841391
Short name T480
Test name
Test status
Simulation time 1734312433 ps
CPU time 10.55 seconds
Started Aug 15 05:09:54 PM PDT 24
Finished Aug 15 05:10:04 PM PDT 24
Peak memory 217724 kb
Host smart-48a87d51-4e25-4329-bee8-78027f8f81c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352841391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.352841391
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2194165691
Short name T543
Test name
Test status
Simulation time 41385177 ps
CPU time 2.37 seconds
Started Aug 15 05:09:44 PM PDT 24
Finished Aug 15 05:09:46 PM PDT 24
Peak memory 218324 kb
Host smart-ad78cfed-46c6-4736-ab64-46727eb557f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194165691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2194165691
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.738147541
Short name T563
Test name
Test status
Simulation time 4059582090 ps
CPU time 9.18 seconds
Started Aug 15 05:09:55 PM PDT 24
Finished Aug 15 05:10:05 PM PDT 24
Peak memory 219728 kb
Host smart-1121b02d-fcee-480b-9608-e6143cca6cd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738147541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.738147541
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3256342082
Short name T630
Test name
Test status
Simulation time 472058782 ps
CPU time 13.45 seconds
Started Aug 15 05:09:54 PM PDT 24
Finished Aug 15 05:10:08 PM PDT 24
Peak memory 226072 kb
Host smart-c21ebfd3-35dc-4136-b0f7-f5165d900362
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256342082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3256342082
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1021707837
Short name T539
Test name
Test status
Simulation time 251647748 ps
CPU time 6.67 seconds
Started Aug 15 05:09:56 PM PDT 24
Finished Aug 15 05:10:03 PM PDT 24
Peak memory 218272 kb
Host smart-91e27223-14ab-413a-9899-dd2af6f53157
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021707837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1021707837
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.4201590036
Short name T216
Test name
Test status
Simulation time 1024225459 ps
CPU time 7.49 seconds
Started Aug 15 05:09:47 PM PDT 24
Finished Aug 15 05:09:54 PM PDT 24
Peak memory 218384 kb
Host smart-7ed0e155-026c-4519-b6a0-113099f3d322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201590036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.4201590036
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3263199193
Short name T429
Test name
Test status
Simulation time 76847961 ps
CPU time 1.85 seconds
Started Aug 15 05:09:45 PM PDT 24
Finished Aug 15 05:09:47 PM PDT 24
Peak memory 214024 kb
Host smart-59cba96d-e196-4f5d-b5d3-fe0bb1cecf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263199193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3263199193
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3288995980
Short name T672
Test name
Test status
Simulation time 769451356 ps
CPU time 14.19 seconds
Started Aug 15 05:09:44 PM PDT 24
Finished Aug 15 05:09:58 PM PDT 24
Peak memory 250972 kb
Host smart-3f6639d6-1360-4967-8525-fe18698b9c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288995980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3288995980
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.998101645
Short name T547
Test name
Test status
Simulation time 316268691 ps
CPU time 9.48 seconds
Started Aug 15 05:09:46 PM PDT 24
Finished Aug 15 05:09:55 PM PDT 24
Peak memory 250984 kb
Host smart-271aaa94-ea2d-4fd7-a123-2819874f9b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998101645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.998101645
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1633001498
Short name T254
Test name
Test status
Simulation time 10877352841 ps
CPU time 81.35 seconds
Started Aug 15 05:09:59 PM PDT 24
Finished Aug 15 05:11:20 PM PDT 24
Peak memory 259228 kb
Host smart-efd70674-82b4-4561-b307-0deb05d86556
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633001498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1633001498
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2539582568
Short name T868
Test name
Test status
Simulation time 45744929 ps
CPU time 0.76 seconds
Started Aug 15 05:09:45 PM PDT 24
Finished Aug 15 05:09:46 PM PDT 24
Peak memory 209128 kb
Host smart-e1a6c45f-b050-412a-8369-8174b08f94d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539582568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2539582568
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.64062714
Short name T252
Test name
Test status
Simulation time 25847665 ps
CPU time 1.37 seconds
Started Aug 15 05:09:57 PM PDT 24
Finished Aug 15 05:09:59 PM PDT 24
Peak memory 209088 kb
Host smart-a52918ed-816a-4ea6-ae85-af39fe04f16e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64062714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.64062714
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3178781851
Short name T118
Test name
Test status
Simulation time 221962355 ps
CPU time 11.61 seconds
Started Aug 15 05:09:54 PM PDT 24
Finished Aug 15 05:10:05 PM PDT 24
Peak memory 226112 kb
Host smart-926ab36c-e5ab-4d6a-81a4-cb2390274ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178781851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3178781851
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3741276746
Short name T810
Test name
Test status
Simulation time 570195417 ps
CPU time 5.86 seconds
Started Aug 15 05:09:57 PM PDT 24
Finished Aug 15 05:10:03 PM PDT 24
Peak memory 217488 kb
Host smart-b24e9df0-8ac6-47a3-9e7b-c9ed86697f00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741276746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3741276746
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.290669570
Short name T673
Test name
Test status
Simulation time 149463651 ps
CPU time 2.49 seconds
Started Aug 15 05:09:55 PM PDT 24
Finished Aug 15 05:09:57 PM PDT 24
Peak memory 222456 kb
Host smart-1beb6a25-6a01-408e-8f3f-9636a9ca4a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290669570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.290669570
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.4204226466
Short name T583
Test name
Test status
Simulation time 814666660 ps
CPU time 16.12 seconds
Started Aug 15 05:09:53 PM PDT 24
Finished Aug 15 05:10:10 PM PDT 24
Peak memory 218376 kb
Host smart-f43745a0-0a79-400e-a119-bce02f188daa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204226466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.4204226466
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1042661180
Short name T265
Test name
Test status
Simulation time 1969247946 ps
CPU time 12.69 seconds
Started Aug 15 05:09:58 PM PDT 24
Finished Aug 15 05:10:11 PM PDT 24
Peak memory 225972 kb
Host smart-1f8edc9c-dda9-4f8c-a1b4-462744226cde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042661180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1042661180
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1399759496
Short name T725
Test name
Test status
Simulation time 288358321 ps
CPU time 10.43 seconds
Started Aug 15 05:09:53 PM PDT 24
Finished Aug 15 05:10:04 PM PDT 24
Peak memory 216924 kb
Host smart-f32da848-a584-4c39-be0e-a4f6da6a5c20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399759496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1399759496
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1870026017
Short name T625
Test name
Test status
Simulation time 1110536832 ps
CPU time 9 seconds
Started Aug 15 05:09:56 PM PDT 24
Finished Aug 15 05:10:05 PM PDT 24
Peak memory 218392 kb
Host smart-852d5abb-0bf4-474b-9681-61c0966b94ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870026017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1870026017
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.166461338
Short name T56
Test name
Test status
Simulation time 146885666 ps
CPU time 2.63 seconds
Started Aug 15 05:09:53 PM PDT 24
Finished Aug 15 05:09:56 PM PDT 24
Peak memory 214996 kb
Host smart-4f9d459d-8e89-4c91-b280-f061a3138c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166461338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.166461338
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2021684384
Short name T744
Test name
Test status
Simulation time 433254348 ps
CPU time 33.78 seconds
Started Aug 15 05:09:59 PM PDT 24
Finished Aug 15 05:10:33 PM PDT 24
Peak memory 250964 kb
Host smart-8b1679f9-7008-47e9-9ac1-e5345b410c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021684384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2021684384
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1832344455
Short name T240
Test name
Test status
Simulation time 264471618 ps
CPU time 3.32 seconds
Started Aug 15 05:09:54 PM PDT 24
Finished Aug 15 05:09:58 PM PDT 24
Peak memory 222636 kb
Host smart-19a2c697-7949-4af4-adf8-3b0cd98425bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832344455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1832344455
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2129163443
Short name T396
Test name
Test status
Simulation time 2832335927 ps
CPU time 149.89 seconds
Started Aug 15 05:09:56 PM PDT 24
Finished Aug 15 05:12:26 PM PDT 24
Peak memory 250996 kb
Host smart-19187163-aec6-4889-afe9-92f84b449bf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129163443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2129163443
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3492871698
Short name T704
Test name
Test status
Simulation time 121173126 ps
CPU time 0.91 seconds
Started Aug 15 05:09:53 PM PDT 24
Finished Aug 15 05:09:55 PM PDT 24
Peak memory 212028 kb
Host smart-f2145553-92fa-44a1-96d7-e3e59acff2e8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492871698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.3492871698
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.590193384
Short name T66
Test name
Test status
Simulation time 117100707 ps
CPU time 0.96 seconds
Started Aug 15 05:10:03 PM PDT 24
Finished Aug 15 05:10:04 PM PDT 24
Peak memory 208992 kb
Host smart-32a12032-f218-45ea-95be-7de9f2d64549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590193384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.590193384
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.820700995
Short name T420
Test name
Test status
Simulation time 1455257358 ps
CPU time 16.8 seconds
Started Aug 15 05:09:57 PM PDT 24
Finished Aug 15 05:10:14 PM PDT 24
Peak memory 218324 kb
Host smart-29d46fc5-bebf-4d74-a4e5-27e06f694393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820700995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.820700995
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.506254682
Short name T177
Test name
Test status
Simulation time 2260294836 ps
CPU time 6.36 seconds
Started Aug 15 05:09:54 PM PDT 24
Finished Aug 15 05:10:00 PM PDT 24
Peak memory 217832 kb
Host smart-a49ce1b5-778a-4850-9a75-804dc2cc8639
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506254682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.506254682
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.92018141
Short name T586
Test name
Test status
Simulation time 289100292 ps
CPU time 3.11 seconds
Started Aug 15 05:09:55 PM PDT 24
Finished Aug 15 05:09:58 PM PDT 24
Peak memory 218320 kb
Host smart-00f08625-d040-4579-882f-adf27495f764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92018141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.92018141
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3337897568
Short name T508
Test name
Test status
Simulation time 1410809308 ps
CPU time 16.51 seconds
Started Aug 15 05:10:01 PM PDT 24
Finished Aug 15 05:10:18 PM PDT 24
Peak memory 226148 kb
Host smart-35a0ba6f-83b4-4d80-a8bb-8d7c9054ab2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337897568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3337897568
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.108972201
Short name T319
Test name
Test status
Simulation time 1005293223 ps
CPU time 10.31 seconds
Started Aug 15 05:10:05 PM PDT 24
Finished Aug 15 05:10:16 PM PDT 24
Peak memory 226080 kb
Host smart-eacb1ced-b311-4fbf-92b2-346b933bbdc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108972201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.108972201
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.395322059
Short name T698
Test name
Test status
Simulation time 424400517 ps
CPU time 14.07 seconds
Started Aug 15 05:10:02 PM PDT 24
Finished Aug 15 05:10:16 PM PDT 24
Peak memory 218308 kb
Host smart-111898cd-dae0-4618-b9be-e60b9676d730
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395322059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.395322059
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3123541572
Short name T317
Test name
Test status
Simulation time 196685318 ps
CPU time 5.89 seconds
Started Aug 15 05:10:00 PM PDT 24
Finished Aug 15 05:10:06 PM PDT 24
Peak memory 218420 kb
Host smart-3b81ebb3-2fe3-4fe9-891e-a6506d084153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123541572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3123541572
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2423930709
Short name T331
Test name
Test status
Simulation time 28877602 ps
CPU time 2.01 seconds
Started Aug 15 05:09:55 PM PDT 24
Finished Aug 15 05:09:57 PM PDT 24
Peak memory 214232 kb
Host smart-131c674e-ba45-4596-8d97-3eeb9e60e4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423930709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2423930709
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1543592917
Short name T411
Test name
Test status
Simulation time 228284009 ps
CPU time 25.69 seconds
Started Aug 15 05:09:53 PM PDT 24
Finished Aug 15 05:10:19 PM PDT 24
Peak memory 250952 kb
Host smart-1194336c-6fae-4513-9e24-8fc3b3c7500a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543592917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1543592917
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.4134583121
Short name T436
Test name
Test status
Simulation time 1451858175 ps
CPU time 8.66 seconds
Started Aug 15 05:09:55 PM PDT 24
Finished Aug 15 05:10:04 PM PDT 24
Peak memory 247336 kb
Host smart-0fd47e0e-83e8-4a96-9979-41169dbb8c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134583121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.4134583121
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.752859535
Short name T348
Test name
Test status
Simulation time 10794996043 ps
CPU time 111.28 seconds
Started Aug 15 05:10:04 PM PDT 24
Finished Aug 15 05:11:55 PM PDT 24
Peak memory 251020 kb
Host smart-f5649de8-a50e-4ec9-88b5-2c2f5e5d21c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752859535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.752859535
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.254193175
Short name T828
Test name
Test status
Simulation time 1544671536 ps
CPU time 62.97 seconds
Started Aug 15 05:10:02 PM PDT 24
Finished Aug 15 05:11:05 PM PDT 24
Peak memory 268772 kb
Host smart-9e246413-39bd-4353-8abb-3653342abf43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=254193175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.254193175
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1328582910
Short name T786
Test name
Test status
Simulation time 53621851 ps
CPU time 0.74 seconds
Started Aug 15 05:09:59 PM PDT 24
Finished Aug 15 05:10:00 PM PDT 24
Peak memory 209060 kb
Host smart-b5ba7545-ff0f-41f8-85ad-7b99b103321f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328582910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1328582910
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1767609027
Short name T530
Test name
Test status
Simulation time 1167226135 ps
CPU time 16.7 seconds
Started Aug 15 05:10:02 PM PDT 24
Finished Aug 15 05:10:19 PM PDT 24
Peak memory 226036 kb
Host smart-5980f29d-e02f-4745-b83a-db778c824760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767609027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1767609027
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.586707339
Short name T25
Test name
Test status
Simulation time 11027352084 ps
CPU time 6.09 seconds
Started Aug 15 05:10:03 PM PDT 24
Finished Aug 15 05:10:09 PM PDT 24
Peak memory 217768 kb
Host smart-c1ee7474-b1ec-40d3-9eb0-b3ce79a0aed4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586707339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.586707339
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.114821994
Short name T503
Test name
Test status
Simulation time 110286058 ps
CPU time 2.23 seconds
Started Aug 15 05:10:01 PM PDT 24
Finished Aug 15 05:10:04 PM PDT 24
Peak memory 218324 kb
Host smart-cddcb24c-99f2-4c36-b743-676d64e1ad07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114821994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.114821994
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1102262726
Short name T308
Test name
Test status
Simulation time 2166264862 ps
CPU time 15.98 seconds
Started Aug 15 05:10:02 PM PDT 24
Finished Aug 15 05:10:18 PM PDT 24
Peak memory 226184 kb
Host smart-23b032fd-8489-4efb-949b-d085e64c32c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102262726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1102262726
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.4057095296
Short name T307
Test name
Test status
Simulation time 5267930458 ps
CPU time 27.33 seconds
Started Aug 15 05:10:01 PM PDT 24
Finished Aug 15 05:10:28 PM PDT 24
Peak memory 226084 kb
Host smart-934aae19-2cac-4fa7-87b7-40a3e33145f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057095296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.4057095296
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3230094416
Short name T658
Test name
Test status
Simulation time 1270208868 ps
CPU time 9.1 seconds
Started Aug 15 05:10:02 PM PDT 24
Finished Aug 15 05:10:11 PM PDT 24
Peak memory 218268 kb
Host smart-ab4b3a3d-5e62-4030-a7c1-5f445a929b22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230094416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3230094416
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.144450042
Short name T211
Test name
Test status
Simulation time 1055248204 ps
CPU time 8.43 seconds
Started Aug 15 05:10:03 PM PDT 24
Finished Aug 15 05:10:11 PM PDT 24
Peak memory 218416 kb
Host smart-ea13d1c4-ef0c-497e-8ff6-623792d20a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144450042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.144450042
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2931469048
Short name T355
Test name
Test status
Simulation time 54121725 ps
CPU time 3.75 seconds
Started Aug 15 05:10:01 PM PDT 24
Finished Aug 15 05:10:05 PM PDT 24
Peak memory 217760 kb
Host smart-cb94196c-d1cb-4a62-897f-a83468f6998c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931469048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2931469048
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1698476102
Short name T608
Test name
Test status
Simulation time 805559672 ps
CPU time 21.64 seconds
Started Aug 15 05:10:01 PM PDT 24
Finished Aug 15 05:10:23 PM PDT 24
Peak memory 250944 kb
Host smart-02c983f1-571d-447e-b591-4b9d2b70ea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698476102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1698476102
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3523871900
Short name T242
Test name
Test status
Simulation time 268512836 ps
CPU time 8.04 seconds
Started Aug 15 05:10:03 PM PDT 24
Finished Aug 15 05:10:11 PM PDT 24
Peak memory 250964 kb
Host smart-06e85ddf-9ed6-47ea-93fc-12ab77904276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523871900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3523871900
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2465094503
Short name T76
Test name
Test status
Simulation time 13245907482 ps
CPU time 217.24 seconds
Started Aug 15 05:10:05 PM PDT 24
Finished Aug 15 05:13:43 PM PDT 24
Peak memory 267312 kb
Host smart-b860c738-a0cc-4f2c-baa3-928cd3f31280
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465094503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2465094503
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.3915430686
Short name T754
Test name
Test status
Simulation time 1264527870 ps
CPU time 79.11 seconds
Started Aug 15 05:10:05 PM PDT 24
Finished Aug 15 05:11:24 PM PDT 24
Peak memory 275672 kb
Host smart-f9baec08-4474-4017-8c5b-217dd374e353
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3915430686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.3915430686
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1666578502
Short name T71
Test name
Test status
Simulation time 73931849 ps
CPU time 0.98 seconds
Started Aug 15 05:10:01 PM PDT 24
Finished Aug 15 05:10:02 PM PDT 24
Peak memory 211936 kb
Host smart-31bcdde0-725d-4f9d-a13c-8507420deac7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666578502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1666578502
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.4220684545
Short name T711
Test name
Test status
Simulation time 25830224 ps
CPU time 1.02 seconds
Started Aug 15 05:10:12 PM PDT 24
Finished Aug 15 05:10:13 PM PDT 24
Peak memory 209012 kb
Host smart-7b831b81-d977-48db-bf82-a4921ea50be9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220684545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.4220684545
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2337535284
Short name T40
Test name
Test status
Simulation time 418210622 ps
CPU time 10.81 seconds
Started Aug 15 05:10:02 PM PDT 24
Finished Aug 15 05:10:13 PM PDT 24
Peak memory 218264 kb
Host smart-3f78241f-10d6-4553-bbfb-7ef6507e3277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337535284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2337535284
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1228666282
Short name T26
Test name
Test status
Simulation time 1490454398 ps
CPU time 17.86 seconds
Started Aug 15 05:10:09 PM PDT 24
Finished Aug 15 05:10:27 PM PDT 24
Peak memory 217428 kb
Host smart-4a2f0381-0e02-43b3-9dfb-0f222bae33fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228666282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1228666282
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.878718281
Short name T323
Test name
Test status
Simulation time 206155849 ps
CPU time 3.9 seconds
Started Aug 15 05:10:02 PM PDT 24
Finished Aug 15 05:10:06 PM PDT 24
Peak memory 218332 kb
Host smart-f9049324-cf7d-4193-868f-4c74181f5ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878718281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.878718281
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3210730193
Short name T356
Test name
Test status
Simulation time 1112890843 ps
CPU time 9.01 seconds
Started Aug 15 05:10:13 PM PDT 24
Finished Aug 15 05:10:22 PM PDT 24
Peak memory 226048 kb
Host smart-0752eceb-b975-4431-bafd-d555f8a2ac69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210730193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3210730193
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3077768325
Short name T759
Test name
Test status
Simulation time 669793369 ps
CPU time 16.05 seconds
Started Aug 15 05:10:13 PM PDT 24
Finished Aug 15 05:10:29 PM PDT 24
Peak memory 226012 kb
Host smart-15239fec-809d-4260-bea8-16d1696c6a5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077768325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3077768325
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2780870034
Short name T519
Test name
Test status
Simulation time 1345434619 ps
CPU time 10.7 seconds
Started Aug 15 05:10:11 PM PDT 24
Finished Aug 15 05:10:22 PM PDT 24
Peak memory 226032 kb
Host smart-875c600c-6bff-4458-93a6-6fbb4a2abd21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780870034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2780870034
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3090273693
Short name T210
Test name
Test status
Simulation time 342405236 ps
CPU time 14.28 seconds
Started Aug 15 05:10:10 PM PDT 24
Finished Aug 15 05:10:25 PM PDT 24
Peak memory 218400 kb
Host smart-1ea8fb03-49dc-4b16-882a-21a07afd594c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090273693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3090273693
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1483697833
Short name T74
Test name
Test status
Simulation time 54263760 ps
CPU time 3.08 seconds
Started Aug 15 05:10:03 PM PDT 24
Finished Aug 15 05:10:06 PM PDT 24
Peak memory 217748 kb
Host smart-8979b7d2-d83f-4791-bce5-5cafc329ae0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483697833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1483697833
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2826070034
Short name T735
Test name
Test status
Simulation time 292081315 ps
CPU time 29.39 seconds
Started Aug 15 05:10:01 PM PDT 24
Finished Aug 15 05:10:31 PM PDT 24
Peak memory 250812 kb
Host smart-bddaf93e-2e2e-422f-9cc1-3f93bb954a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826070034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2826070034
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.4153233334
Short name T104
Test name
Test status
Simulation time 81876262 ps
CPU time 6.44 seconds
Started Aug 15 05:10:01 PM PDT 24
Finished Aug 15 05:10:08 PM PDT 24
Peak memory 246880 kb
Host smart-a8321cbb-c91a-4648-89e6-2c63188c637d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153233334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.4153233334
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.4081237198
Short name T827
Test name
Test status
Simulation time 2611711023 ps
CPU time 96.24 seconds
Started Aug 15 05:10:11 PM PDT 24
Finished Aug 15 05:11:48 PM PDT 24
Peak memory 251012 kb
Host smart-cb6f633a-fe3c-4fde-92de-0fe7ea951213
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081237198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.4081237198
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3023156413
Short name T145
Test name
Test status
Simulation time 6825614182 ps
CPU time 71.5 seconds
Started Aug 15 05:10:12 PM PDT 24
Finished Aug 15 05:11:23 PM PDT 24
Peak memory 272544 kb
Host smart-0b42094a-a454-4556-8c9d-bb64953b718f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3023156413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.3023156413
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1628185634
Short name T271
Test name
Test status
Simulation time 20718993 ps
CPU time 0.8 seconds
Started Aug 15 05:10:02 PM PDT 24
Finished Aug 15 05:10:03 PM PDT 24
Peak memory 209200 kb
Host smart-0a7da1d0-0ba4-4b0d-b12d-8f29973a2bb3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628185634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1628185634
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.824116259
Short name T620
Test name
Test status
Simulation time 459782328 ps
CPU time 1.27 seconds
Started Aug 15 05:07:47 PM PDT 24
Finished Aug 15 05:07:48 PM PDT 24
Peak memory 209076 kb
Host smart-33aa524e-a926-4f0b-a487-9d4bf9e842bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824116259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.824116259
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2055610658
Short name T206
Test name
Test status
Simulation time 13074035 ps
CPU time 1.01 seconds
Started Aug 15 05:07:50 PM PDT 24
Finished Aug 15 05:07:52 PM PDT 24
Peak memory 208756 kb
Host smart-6b2ea87b-61ce-4ab3-b9ec-a7c8a6c130a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055610658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2055610658
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.399477753
Short name T490
Test name
Test status
Simulation time 848136597 ps
CPU time 16.71 seconds
Started Aug 15 05:07:50 PM PDT 24
Finished Aug 15 05:08:06 PM PDT 24
Peak memory 218284 kb
Host smart-cf39b436-d29e-47e9-a278-93050ba64851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399477753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.399477753
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3054670396
Short name T849
Test name
Test status
Simulation time 342580395 ps
CPU time 9.75 seconds
Started Aug 15 05:07:45 PM PDT 24
Finished Aug 15 05:07:55 PM PDT 24
Peak memory 217720 kb
Host smart-d55ed419-df57-481e-9530-6653066ba9e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054670396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3054670396
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2357732016
Short name T238
Test name
Test status
Simulation time 2674028042 ps
CPU time 29.42 seconds
Started Aug 15 05:07:48 PM PDT 24
Finished Aug 15 05:08:18 PM PDT 24
Peak memory 218980 kb
Host smart-31ac7b08-f65c-4be9-831a-20de41f5ca46
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357732016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2357732016
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.4252609454
Short name T404
Test name
Test status
Simulation time 11819703334 ps
CPU time 6.92 seconds
Started Aug 15 05:07:48 PM PDT 24
Finished Aug 15 05:07:55 PM PDT 24
Peak memory 217844 kb
Host smart-ed760b25-26a4-4b1b-b500-09476a4372a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252609454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.4
252609454
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3274161346
Short name T95
Test name
Test status
Simulation time 1373948204 ps
CPU time 11.6 seconds
Started Aug 15 05:07:47 PM PDT 24
Finished Aug 15 05:07:59 PM PDT 24
Peak memory 223180 kb
Host smart-95b307f3-c172-4a89-807a-e0e86c713eaa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274161346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3274161346
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1498763881
Short name T867
Test name
Test status
Simulation time 2063141794 ps
CPU time 22.36 seconds
Started Aug 15 05:07:52 PM PDT 24
Finished Aug 15 05:08:14 PM PDT 24
Peak memory 217712 kb
Host smart-20d12bcb-dc47-48ce-a2e6-211d7dcda08f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498763881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1498763881
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.186400958
Short name T715
Test name
Test status
Simulation time 2727479441 ps
CPU time 10.35 seconds
Started Aug 15 05:07:47 PM PDT 24
Finished Aug 15 05:07:58 PM PDT 24
Peak memory 217752 kb
Host smart-f80aea88-c523-4bec-812e-315739d4312f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186400958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.186400958
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2649920492
Short name T562
Test name
Test status
Simulation time 2431507727 ps
CPU time 35.13 seconds
Started Aug 15 05:07:48 PM PDT 24
Finished Aug 15 05:08:23 PM PDT 24
Peak memory 267680 kb
Host smart-1954f8dc-8826-4bcc-b822-af993ec02245
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649920492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2649920492
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3944337666
Short name T452
Test name
Test status
Simulation time 4717668309 ps
CPU time 10.58 seconds
Started Aug 15 05:07:48 PM PDT 24
Finished Aug 15 05:07:59 PM PDT 24
Peak memory 223684 kb
Host smart-7366e440-abcc-4266-b6b6-3e7b8ff7e3cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944337666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3944337666
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1154167806
Short name T545
Test name
Test status
Simulation time 342253665 ps
CPU time 3.19 seconds
Started Aug 15 05:07:47 PM PDT 24
Finished Aug 15 05:07:50 PM PDT 24
Peak memory 218476 kb
Host smart-0dd5a6fb-8ef8-46d6-b480-eff27e7cb23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154167806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1154167806
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2108791939
Short name T65
Test name
Test status
Simulation time 575024640 ps
CPU time 4.67 seconds
Started Aug 15 05:07:52 PM PDT 24
Finished Aug 15 05:07:57 PM PDT 24
Peak memory 222876 kb
Host smart-da541d32-5a99-4efd-b15a-5e0e24bfb2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108791939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2108791939
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.313400545
Short name T52
Test name
Test status
Simulation time 1750791448 ps
CPU time 39.6 seconds
Started Aug 15 05:07:51 PM PDT 24
Finished Aug 15 05:08:31 PM PDT 24
Peak memory 269916 kb
Host smart-9363c170-c1b9-47b4-b1ce-0341ed93ae7e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313400545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.313400545
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.962719943
Short name T693
Test name
Test status
Simulation time 1985559993 ps
CPU time 12.39 seconds
Started Aug 15 05:07:48 PM PDT 24
Finished Aug 15 05:08:01 PM PDT 24
Peak memory 226124 kb
Host smart-6255e188-f276-4276-a9da-77f40baddba0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962719943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.962719943
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3688072131
Short name T855
Test name
Test status
Simulation time 333834671 ps
CPU time 9.28 seconds
Started Aug 15 05:07:49 PM PDT 24
Finished Aug 15 05:07:58 PM PDT 24
Peak memory 226052 kb
Host smart-2f707952-88b8-4969-9515-576d8996da6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688072131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3688072131
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.594826161
Short name T58
Test name
Test status
Simulation time 2462847013 ps
CPU time 12.61 seconds
Started Aug 15 05:07:46 PM PDT 24
Finished Aug 15 05:07:59 PM PDT 24
Peak memory 218364 kb
Host smart-efa83aa3-0db5-43b8-8c6f-5ddc04ea35bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594826161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.594826161
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.716665274
Short name T517
Test name
Test status
Simulation time 314970219 ps
CPU time 9.34 seconds
Started Aug 15 05:07:49 PM PDT 24
Finished Aug 15 05:07:58 PM PDT 24
Peak memory 218400 kb
Host smart-7587c367-9977-4ea6-b6d6-9a123913b455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716665274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.716665274
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.4280958423
Short name T753
Test name
Test status
Simulation time 28550808 ps
CPU time 1.95 seconds
Started Aug 15 05:07:46 PM PDT 24
Finished Aug 15 05:07:48 PM PDT 24
Peak memory 217728 kb
Host smart-787c9e60-5439-4f4f-b070-dcc60bf0a220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280958423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.4280958423
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.4204862309
Short name T81
Test name
Test status
Simulation time 823940748 ps
CPU time 33.33 seconds
Started Aug 15 05:07:46 PM PDT 24
Finished Aug 15 05:08:19 PM PDT 24
Peak memory 250972 kb
Host smart-5fb5ab71-e26f-4baa-ad47-0924a56cfb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204862309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.4204862309
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2387935647
Short name T628
Test name
Test status
Simulation time 210205714 ps
CPU time 3.54 seconds
Started Aug 15 05:07:51 PM PDT 24
Finished Aug 15 05:07:55 PM PDT 24
Peak memory 222644 kb
Host smart-4faef82b-457e-4746-a1ef-a1c4676e31f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387935647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2387935647
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2608832483
Short name T792
Test name
Test status
Simulation time 13741561808 ps
CPU time 100.57 seconds
Started Aug 15 05:07:48 PM PDT 24
Finished Aug 15 05:09:28 PM PDT 24
Peak memory 249612 kb
Host smart-cacffb64-f6d7-49e5-aaa3-eab8d3eb0eba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608832483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2608832483
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1855677774
Short name T635
Test name
Test status
Simulation time 43182823 ps
CPU time 0.92 seconds
Started Aug 15 05:07:46 PM PDT 24
Finished Aug 15 05:07:47 PM PDT 24
Peak memory 209028 kb
Host smart-29599e6c-a6f0-45a1-bcac-a0ae742f6380
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855677774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1855677774
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2746381984
Short name T241
Test name
Test status
Simulation time 57451875 ps
CPU time 1.06 seconds
Started Aug 15 05:10:09 PM PDT 24
Finished Aug 15 05:10:11 PM PDT 24
Peak memory 208968 kb
Host smart-74db1895-9428-4e37-96fb-8c7785f1e8d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746381984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2746381984
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2038300240
Short name T314
Test name
Test status
Simulation time 1635375846 ps
CPU time 13.11 seconds
Started Aug 15 05:10:12 PM PDT 24
Finished Aug 15 05:10:25 PM PDT 24
Peak memory 218356 kb
Host smart-7e2b7aa2-bc2b-4339-97fe-799efe3ba218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038300240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2038300240
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.4187110216
Short name T686
Test name
Test status
Simulation time 1857668816 ps
CPU time 11.72 seconds
Started Aug 15 05:10:12 PM PDT 24
Finished Aug 15 05:10:24 PM PDT 24
Peak memory 217316 kb
Host smart-db7d0946-c7ce-4a32-8e0e-49190c829add
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187110216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.4187110216
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3316170270
Short name T606
Test name
Test status
Simulation time 349316712 ps
CPU time 4.13 seconds
Started Aug 15 05:10:11 PM PDT 24
Finished Aug 15 05:10:15 PM PDT 24
Peak memory 222416 kb
Host smart-116f5edc-4a1e-4bda-b7dc-26f4737e6141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316170270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3316170270
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3848177641
Short name T17
Test name
Test status
Simulation time 219696356 ps
CPU time 10.76 seconds
Started Aug 15 05:10:10 PM PDT 24
Finished Aug 15 05:10:21 PM PDT 24
Peak memory 218212 kb
Host smart-b00fc04b-beab-45a2-a6db-869c331a814a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848177641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3848177641
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.236863297
Short name T382
Test name
Test status
Simulation time 752692473 ps
CPU time 11.7 seconds
Started Aug 15 05:10:12 PM PDT 24
Finished Aug 15 05:10:24 PM PDT 24
Peak memory 226072 kb
Host smart-475304de-ada8-46b9-bcc9-62b44d60902b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236863297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.236863297
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1394167066
Short name T720
Test name
Test status
Simulation time 369096404 ps
CPU time 12.72 seconds
Started Aug 15 05:10:14 PM PDT 24
Finished Aug 15 05:10:26 PM PDT 24
Peak memory 218232 kb
Host smart-da5c2944-a6d5-4077-b0bc-5bfb99b47c0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394167066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1394167066
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.2822758518
Short name T536
Test name
Test status
Simulation time 1324843602 ps
CPU time 8.6 seconds
Started Aug 15 05:10:12 PM PDT 24
Finished Aug 15 05:10:21 PM PDT 24
Peak memory 218348 kb
Host smart-8c8670ab-a199-4e17-92b9-24b5c89619a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822758518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2822758518
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1204306192
Short name T589
Test name
Test status
Simulation time 417461600 ps
CPU time 4.46 seconds
Started Aug 15 05:10:10 PM PDT 24
Finished Aug 15 05:10:15 PM PDT 24
Peak memory 217748 kb
Host smart-9192a463-026a-464b-8ece-b9de981c8d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204306192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1204306192
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1660402776
Short name T446
Test name
Test status
Simulation time 1169453483 ps
CPU time 19.9 seconds
Started Aug 15 05:10:11 PM PDT 24
Finished Aug 15 05:10:31 PM PDT 24
Peak memory 250740 kb
Host smart-591ddaf2-ceb3-49ba-8c77-002e0fbea7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660402776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1660402776
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.4190704615
Short name T393
Test name
Test status
Simulation time 71157733 ps
CPU time 6.26 seconds
Started Aug 15 05:10:11 PM PDT 24
Finished Aug 15 05:10:17 PM PDT 24
Peak memory 246824 kb
Host smart-6075ca15-d84a-4bf3-9b1b-df89a18d5bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190704615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.4190704615
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.448423655
Short name T150
Test name
Test status
Simulation time 3329322997 ps
CPU time 56.29 seconds
Started Aug 15 05:10:11 PM PDT 24
Finished Aug 15 05:11:08 PM PDT 24
Peak memory 251028 kb
Host smart-34e43e6e-2ed3-48a6-9533-d5ea53183d27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448423655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.448423655
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.59202060
Short name T172
Test name
Test status
Simulation time 4130501377 ps
CPU time 29.91 seconds
Started Aug 15 05:10:13 PM PDT 24
Finished Aug 15 05:10:43 PM PDT 24
Peak memory 253388 kb
Host smart-2767b496-1b4f-42f3-9e80-a6d19e3e14c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=59202060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.59202060
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3315659971
Short name T249
Test name
Test status
Simulation time 17372734 ps
CPU time 1.38 seconds
Started Aug 15 05:10:12 PM PDT 24
Finished Aug 15 05:10:13 PM PDT 24
Peak memory 218116 kb
Host smart-832d3728-7119-47c8-9233-81136baf3235
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315659971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3315659971
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3865752293
Short name T829
Test name
Test status
Simulation time 100120627 ps
CPU time 0.94 seconds
Started Aug 15 05:10:19 PM PDT 24
Finished Aug 15 05:10:20 PM PDT 24
Peak memory 209148 kb
Host smart-1a3d1f08-c3ed-4521-b7cb-1dce6dad3901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865752293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3865752293
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2550522686
Short name T418
Test name
Test status
Simulation time 869638359 ps
CPU time 13.25 seconds
Started Aug 15 05:10:11 PM PDT 24
Finished Aug 15 05:10:25 PM PDT 24
Peak memory 218348 kb
Host smart-14fab3d1-911f-456b-9b4e-cd027970a6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550522686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2550522686
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2769512876
Short name T409
Test name
Test status
Simulation time 148036857 ps
CPU time 2.91 seconds
Started Aug 15 05:10:10 PM PDT 24
Finished Aug 15 05:10:13 PM PDT 24
Peak memory 222592 kb
Host smart-8c50e889-2805-47ad-aba0-799a4869f729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769512876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2769512876
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2495743975
Short name T621
Test name
Test status
Simulation time 1242737180 ps
CPU time 13.66 seconds
Started Aug 15 05:10:11 PM PDT 24
Finished Aug 15 05:10:24 PM PDT 24
Peak memory 218764 kb
Host smart-164e1428-a58f-4690-9c1c-5af3f8536989
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495743975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2495743975
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.241097687
Short name T374
Test name
Test status
Simulation time 311849127 ps
CPU time 13.05 seconds
Started Aug 15 05:10:12 PM PDT 24
Finished Aug 15 05:10:25 PM PDT 24
Peak memory 226064 kb
Host smart-2757383a-012f-4956-bde2-7cf3f19403df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241097687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.241097687
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2727731151
Short name T303
Test name
Test status
Simulation time 4436862378 ps
CPU time 8.48 seconds
Started Aug 15 05:10:12 PM PDT 24
Finished Aug 15 05:10:20 PM PDT 24
Peak memory 218352 kb
Host smart-224d7e06-08e0-4ec3-9ee3-b11f992d02e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727731151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2727731151
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1289369281
Short name T49
Test name
Test status
Simulation time 507674653 ps
CPU time 8.31 seconds
Started Aug 15 05:10:09 PM PDT 24
Finished Aug 15 05:10:18 PM PDT 24
Peak memory 226148 kb
Host smart-7e133a17-2af3-4a00-95fe-10e2759e4dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289369281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1289369281
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1548155253
Short name T710
Test name
Test status
Simulation time 17549502 ps
CPU time 1.19 seconds
Started Aug 15 05:10:11 PM PDT 24
Finished Aug 15 05:10:12 PM PDT 24
Peak memory 213484 kb
Host smart-abf498b9-a6c7-4c11-921d-d8b654517938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548155253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1548155253
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1829620352
Short name T736
Test name
Test status
Simulation time 553957089 ps
CPU time 22.2 seconds
Started Aug 15 05:10:13 PM PDT 24
Finished Aug 15 05:10:35 PM PDT 24
Peak memory 250916 kb
Host smart-0c9bf0da-e939-47e7-823f-48d3608fe074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829620352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1829620352
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.824449892
Short name T295
Test name
Test status
Simulation time 297091571 ps
CPU time 6.08 seconds
Started Aug 15 05:10:12 PM PDT 24
Finished Aug 15 05:10:18 PM PDT 24
Peak memory 246396 kb
Host smart-66985e4e-c3f2-413c-a260-2103a67e01a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824449892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.824449892
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3276005314
Short name T310
Test name
Test status
Simulation time 8014288972 ps
CPU time 26.83 seconds
Started Aug 15 05:10:26 PM PDT 24
Finished Aug 15 05:10:53 PM PDT 24
Peak memory 216804 kb
Host smart-baff776f-18c4-4bae-84ee-894435ca9553
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276005314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3276005314
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.4140669462
Short name T269
Test name
Test status
Simulation time 12745044 ps
CPU time 1.13 seconds
Started Aug 15 05:10:13 PM PDT 24
Finished Aug 15 05:10:14 PM PDT 24
Peak memory 212012 kb
Host smart-8e167802-067f-4969-8652-7c97d6b46672
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140669462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.4140669462
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2461787902
Short name T257
Test name
Test status
Simulation time 70050792 ps
CPU time 1.13 seconds
Started Aug 15 05:10:22 PM PDT 24
Finished Aug 15 05:10:24 PM PDT 24
Peak memory 209056 kb
Host smart-56fe5e68-4278-4e5e-b73c-546124aa9dab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461787902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2461787902
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1217870582
Short name T823
Test name
Test status
Simulation time 300651313 ps
CPU time 9.65 seconds
Started Aug 15 05:10:24 PM PDT 24
Finished Aug 15 05:10:34 PM PDT 24
Peak memory 225992 kb
Host smart-ec4bd6ae-a4cd-4fc6-8395-102bba55559f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217870582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1217870582
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3153002498
Short name T379
Test name
Test status
Simulation time 1295427246 ps
CPU time 8.68 seconds
Started Aug 15 05:10:28 PM PDT 24
Finished Aug 15 05:10:37 PM PDT 24
Peak memory 217812 kb
Host smart-3ea33d07-e024-44b1-98aa-a9fe99321a98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153002498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3153002498
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3605584441
Short name T378
Test name
Test status
Simulation time 16788803 ps
CPU time 1.54 seconds
Started Aug 15 05:10:19 PM PDT 24
Finished Aug 15 05:10:21 PM PDT 24
Peak memory 222028 kb
Host smart-2d171376-af59-4614-887d-eab2b156c764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605584441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3605584441
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.2667439375
Short name T806
Test name
Test status
Simulation time 2446214173 ps
CPU time 17.09 seconds
Started Aug 15 05:10:19 PM PDT 24
Finished Aug 15 05:10:37 PM PDT 24
Peak memory 220380 kb
Host smart-a362f817-e176-4f8c-a7e4-8b7820370db5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667439375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2667439375
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1044657789
Short name T837
Test name
Test status
Simulation time 1043103556 ps
CPU time 14.45 seconds
Started Aug 15 05:10:22 PM PDT 24
Finished Aug 15 05:10:37 PM PDT 24
Peak memory 226084 kb
Host smart-265840ee-7f5c-4cf5-bcbd-ad8427d7bfc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044657789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1044657789
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.133965137
Short name T233
Test name
Test status
Simulation time 620179532 ps
CPU time 14.15 seconds
Started Aug 15 05:10:20 PM PDT 24
Finished Aug 15 05:10:35 PM PDT 24
Peak memory 225984 kb
Host smart-8b695e2a-7342-4979-9020-8f4c29b6460b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133965137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.133965137
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1559663606
Short name T505
Test name
Test status
Simulation time 466279958 ps
CPU time 9.52 seconds
Started Aug 15 05:10:17 PM PDT 24
Finished Aug 15 05:10:27 PM PDT 24
Peak memory 218360 kb
Host smart-9186dc74-eda1-4651-ac0a-2bf2916c7872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559663606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1559663606
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.625986027
Short name T843
Test name
Test status
Simulation time 115179342 ps
CPU time 2.08 seconds
Started Aug 15 05:10:19 PM PDT 24
Finished Aug 15 05:10:21 PM PDT 24
Peak memory 217748 kb
Host smart-665972e1-5d60-45e4-80d9-7fa681b05336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625986027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.625986027
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.496162661
Short name T154
Test name
Test status
Simulation time 877048310 ps
CPU time 23.22 seconds
Started Aug 15 05:10:20 PM PDT 24
Finished Aug 15 05:10:43 PM PDT 24
Peak memory 244936 kb
Host smart-29a14d81-73a7-4a70-98c9-c5d860b30834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496162661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.496162661
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3677100351
Short name T689
Test name
Test status
Simulation time 178584595 ps
CPU time 7.4 seconds
Started Aug 15 05:10:19 PM PDT 24
Finished Aug 15 05:10:26 PM PDT 24
Peak memory 247568 kb
Host smart-b81e95d3-a9b3-4812-8eea-7bebd91c2134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677100351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3677100351
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1763609018
Short name T578
Test name
Test status
Simulation time 8791714440 ps
CPU time 250.33 seconds
Started Aug 15 05:10:19 PM PDT 24
Finished Aug 15 05:14:29 PM PDT 24
Peak memory 268488 kb
Host smart-4dadafa8-8d56-4a36-9212-540173693c14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763609018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1763609018
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.282343562
Short name T334
Test name
Test status
Simulation time 14083012 ps
CPU time 0.94 seconds
Started Aug 15 05:10:18 PM PDT 24
Finished Aug 15 05:10:19 PM PDT 24
Peak memory 212032 kb
Host smart-86230655-4c61-4442-8b70-8304bccd923e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282343562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.282343562
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1532328382
Short name T617
Test name
Test status
Simulation time 14494418 ps
CPU time 0.89 seconds
Started Aug 15 05:10:21 PM PDT 24
Finished Aug 15 05:10:22 PM PDT 24
Peak memory 208800 kb
Host smart-e6cbbc82-d68b-4a0f-b222-6abb71fd8583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532328382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1532328382
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.428362506
Short name T286
Test name
Test status
Simulation time 1349769804 ps
CPU time 15.73 seconds
Started Aug 15 05:10:18 PM PDT 24
Finished Aug 15 05:10:34 PM PDT 24
Peak memory 226136 kb
Host smart-d680c329-81f6-4974-97d7-2e1cff9fddd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428362506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.428362506
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.230813882
Short name T447
Test name
Test status
Simulation time 170273750 ps
CPU time 5.11 seconds
Started Aug 15 05:10:26 PM PDT 24
Finished Aug 15 05:10:31 PM PDT 24
Peak memory 217172 kb
Host smart-fb064dff-f543-4e4b-9742-6875c20cfbee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230813882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.230813882
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3959087478
Short name T874
Test name
Test status
Simulation time 198265778 ps
CPU time 4.48 seconds
Started Aug 15 05:10:20 PM PDT 24
Finished Aug 15 05:10:24 PM PDT 24
Peak memory 218320 kb
Host smart-94019dc6-d53f-475c-b60a-c764ec215836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959087478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3959087478
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.263819286
Short name T732
Test name
Test status
Simulation time 558929768 ps
CPU time 12.56 seconds
Started Aug 15 05:10:26 PM PDT 24
Finished Aug 15 05:10:39 PM PDT 24
Peak memory 226072 kb
Host smart-224e4e63-a319-420c-8cf3-85f4dc43c94f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263819286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.263819286
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1105233787
Short name T512
Test name
Test status
Simulation time 702509451 ps
CPU time 13.04 seconds
Started Aug 15 05:10:17 PM PDT 24
Finished Aug 15 05:10:30 PM PDT 24
Peak memory 225972 kb
Host smart-80a9b0cf-e44c-4b08-89aa-5d4e6c714453
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105233787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1105233787
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1815395481
Short name T346
Test name
Test status
Simulation time 1403020529 ps
CPU time 7.96 seconds
Started Aug 15 05:10:22 PM PDT 24
Finished Aug 15 05:10:31 PM PDT 24
Peak memory 218280 kb
Host smart-16a2cfef-503a-4350-ad7c-09f49c6f52f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815395481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1815395481
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3307722064
Short name T48
Test name
Test status
Simulation time 244730156 ps
CPU time 11.19 seconds
Started Aug 15 05:10:20 PM PDT 24
Finished Aug 15 05:10:31 PM PDT 24
Peak memory 218380 kb
Host smart-0c71c923-550a-45cc-abbf-3008bc664a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307722064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3307722064
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1189700910
Short name T250
Test name
Test status
Simulation time 362524390 ps
CPU time 2.96 seconds
Started Aug 15 05:10:21 PM PDT 24
Finished Aug 15 05:10:24 PM PDT 24
Peak memory 217764 kb
Host smart-0bd8106f-49ae-4521-aa33-c403dd871aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189700910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1189700910
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3581670537
Short name T597
Test name
Test status
Simulation time 194944815 ps
CPU time 23.42 seconds
Started Aug 15 05:10:17 PM PDT 24
Finished Aug 15 05:10:41 PM PDT 24
Peak memory 250936 kb
Host smart-1d59ea9a-9af2-4a40-9f5e-873fd8a29f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581670537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3581670537
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1384672466
Short name T255
Test name
Test status
Simulation time 230341441 ps
CPU time 8.21 seconds
Started Aug 15 05:10:18 PM PDT 24
Finished Aug 15 05:10:26 PM PDT 24
Peak memory 250996 kb
Host smart-b07ad816-418f-4f2c-ae09-def7562598c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384672466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1384672466
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2721511445
Short name T246
Test name
Test status
Simulation time 5550515085 ps
CPU time 73.39 seconds
Started Aug 15 05:10:24 PM PDT 24
Finished Aug 15 05:11:38 PM PDT 24
Peak memory 251084 kb
Host smart-9db01999-7c7a-4b05-bc95-39d981e69a13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721511445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2721511445
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2769026962
Short name T758
Test name
Test status
Simulation time 23474554 ps
CPU time 0.84 seconds
Started Aug 15 05:10:22 PM PDT 24
Finished Aug 15 05:10:24 PM PDT 24
Peak memory 208996 kb
Host smart-dce6a3aa-e3a2-4f08-8f07-1a642016f936
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769026962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2769026962
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3938164897
Short name T248
Test name
Test status
Simulation time 25593423 ps
CPU time 1.36 seconds
Started Aug 15 05:10:30 PM PDT 24
Finished Aug 15 05:10:32 PM PDT 24
Peak memory 209104 kb
Host smart-9f7fd61c-d667-4470-8eb3-f67d48640b3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938164897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3938164897
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2728858959
Short name T591
Test name
Test status
Simulation time 350912849 ps
CPU time 11.1 seconds
Started Aug 15 05:10:21 PM PDT 24
Finished Aug 15 05:10:32 PM PDT 24
Peak memory 218272 kb
Host smart-b50e091f-7a96-4561-b181-baf0f64a02c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728858959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2728858959
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1775475029
Short name T778
Test name
Test status
Simulation time 172025279 ps
CPU time 5.25 seconds
Started Aug 15 05:10:28 PM PDT 24
Finished Aug 15 05:10:34 PM PDT 24
Peak memory 217740 kb
Host smart-6c915d3c-ec81-49c5-aed4-79c77d351cbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775475029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1775475029
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1085963438
Short name T561
Test name
Test status
Simulation time 121987898 ps
CPU time 3.98 seconds
Started Aug 15 05:10:22 PM PDT 24
Finished Aug 15 05:10:27 PM PDT 24
Peak memory 218324 kb
Host smart-42cb927a-c4fb-469d-9ff0-eba6b21a036f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085963438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1085963438
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1665427478
Short name T376
Test name
Test status
Simulation time 4946028504 ps
CPU time 14.75 seconds
Started Aug 15 05:10:27 PM PDT 24
Finished Aug 15 05:10:42 PM PDT 24
Peak memory 220380 kb
Host smart-68959cec-8191-4622-a390-99ee442ea924
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665427478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1665427478
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2049978368
Short name T553
Test name
Test status
Simulation time 248798049 ps
CPU time 9.25 seconds
Started Aug 15 05:10:28 PM PDT 24
Finished Aug 15 05:10:37 PM PDT 24
Peak memory 226060 kb
Host smart-f8ba5f69-6259-463b-ac87-7763c8260586
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049978368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2049978368
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3624334672
Short name T663
Test name
Test status
Simulation time 256953719 ps
CPU time 6.3 seconds
Started Aug 15 05:10:27 PM PDT 24
Finished Aug 15 05:10:33 PM PDT 24
Peak memory 225520 kb
Host smart-decc62fc-7ebd-47cb-bf79-3caf8c4e686c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624334672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3624334672
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1383260796
Short name T488
Test name
Test status
Simulation time 247753906 ps
CPU time 9.98 seconds
Started Aug 15 05:10:27 PM PDT 24
Finished Aug 15 05:10:37 PM PDT 24
Peak memory 218404 kb
Host smart-c5a5fd2e-b291-464d-a319-dfdbb41af751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383260796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1383260796
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3164539112
Short name T70
Test name
Test status
Simulation time 245178445 ps
CPU time 2.99 seconds
Started Aug 15 05:10:19 PM PDT 24
Finished Aug 15 05:10:22 PM PDT 24
Peak memory 214868 kb
Host smart-ed145adb-e7df-45cf-9b47-34ae64884a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164539112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3164539112
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.4184311833
Short name T311
Test name
Test status
Simulation time 180611550 ps
CPU time 22.51 seconds
Started Aug 15 05:10:20 PM PDT 24
Finished Aug 15 05:10:43 PM PDT 24
Peak memory 250932 kb
Host smart-e7bb0cdd-7eb7-4930-8af1-24f6d7aabe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184311833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.4184311833
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2739236021
Short name T496
Test name
Test status
Simulation time 155744948 ps
CPU time 3.24 seconds
Started Aug 15 05:10:22 PM PDT 24
Finished Aug 15 05:10:26 PM PDT 24
Peak memory 222300 kb
Host smart-ca847201-4863-480d-98e6-fa8600432776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739236021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2739236021
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3714621514
Short name T511
Test name
Test status
Simulation time 2038638621 ps
CPU time 11.11 seconds
Started Aug 15 05:10:33 PM PDT 24
Finished Aug 15 05:10:44 PM PDT 24
Peak memory 248592 kb
Host smart-eb3cf68f-9e58-49cf-b10e-9c8250e46049
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714621514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3714621514
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3004883011
Short name T613
Test name
Test status
Simulation time 15289608 ps
CPU time 0.87 seconds
Started Aug 15 05:10:29 PM PDT 24
Finished Aug 15 05:10:30 PM PDT 24
Peak memory 208948 kb
Host smart-9ae724f7-1169-4213-b74a-90fdce7cc084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004883011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3004883011
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1625452553
Short name T23
Test name
Test status
Simulation time 458654688 ps
CPU time 6 seconds
Started Aug 15 05:10:27 PM PDT 24
Finished Aug 15 05:10:33 PM PDT 24
Peak memory 217516 kb
Host smart-77d5f9ef-1c7f-4465-aa38-0eb7fa2b1f26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625452553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1625452553
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1382065158
Short name T5
Test name
Test status
Simulation time 113307643 ps
CPU time 1.8 seconds
Started Aug 15 05:10:28 PM PDT 24
Finished Aug 15 05:10:30 PM PDT 24
Peak memory 218364 kb
Host smart-eafb644b-4f86-43b3-9765-1f8184f9fa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382065158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1382065158
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.4223487263
Short name T609
Test name
Test status
Simulation time 357034785 ps
CPU time 17.62 seconds
Started Aug 15 05:10:27 PM PDT 24
Finished Aug 15 05:10:45 PM PDT 24
Peak memory 225996 kb
Host smart-56b06fed-274d-4c92-879c-de482ff23917
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223487263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4223487263
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3806365518
Short name T535
Test name
Test status
Simulation time 349413655 ps
CPU time 14.52 seconds
Started Aug 15 05:10:29 PM PDT 24
Finished Aug 15 05:10:44 PM PDT 24
Peak memory 226060 kb
Host smart-30db3a4d-812e-4dae-a8bd-3524d2476e8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806365518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3806365518
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1682202666
Short name T454
Test name
Test status
Simulation time 252817519 ps
CPU time 9.76 seconds
Started Aug 15 05:10:32 PM PDT 24
Finished Aug 15 05:10:42 PM PDT 24
Peak memory 218156 kb
Host smart-c8e9e5ce-a986-4fcf-945c-05b2a223f378
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682202666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1682202666
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3280222914
Short name T475
Test name
Test status
Simulation time 101691207 ps
CPU time 1.58 seconds
Started Aug 15 05:10:29 PM PDT 24
Finished Aug 15 05:10:30 PM PDT 24
Peak memory 213860 kb
Host smart-89b41de5-846c-4892-b7ea-c8b5ce8d427d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280222914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3280222914
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1107660453
Short name T366
Test name
Test status
Simulation time 1913707482 ps
CPU time 25.11 seconds
Started Aug 15 05:10:29 PM PDT 24
Finished Aug 15 05:10:55 PM PDT 24
Peak memory 250980 kb
Host smart-4a7d5529-768b-4b2e-b7c4-ca8beed25874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107660453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1107660453
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.152569919
Short name T315
Test name
Test status
Simulation time 72280398 ps
CPU time 8.03 seconds
Started Aug 15 05:10:29 PM PDT 24
Finished Aug 15 05:10:38 PM PDT 24
Peak memory 250640 kb
Host smart-c2268087-65a1-449b-8751-243013353add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152569919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.152569919
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2412511123
Short name T651
Test name
Test status
Simulation time 10411355394 ps
CPU time 337.51 seconds
Started Aug 15 05:10:28 PM PDT 24
Finished Aug 15 05:16:06 PM PDT 24
Peak memory 283704 kb
Host smart-8cdeb7f5-9928-44a7-88eb-2b802ef644a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412511123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2412511123
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3731231678
Short name T856
Test name
Test status
Simulation time 94305406 ps
CPU time 0.92 seconds
Started Aug 15 05:10:30 PM PDT 24
Finished Aug 15 05:10:31 PM PDT 24
Peak memory 209056 kb
Host smart-7b78b917-f4b4-465f-821a-13ed2f7426cb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731231678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3731231678
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3194367732
Short name T352
Test name
Test status
Simulation time 16062290 ps
CPU time 1.09 seconds
Started Aug 15 05:10:43 PM PDT 24
Finished Aug 15 05:10:44 PM PDT 24
Peak memory 209084 kb
Host smart-bc07df6a-3657-4642-9fc8-0212c17d400d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194367732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3194367732
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1686885986
Short name T634
Test name
Test status
Simulation time 1637028922 ps
CPU time 16.17 seconds
Started Aug 15 05:10:46 PM PDT 24
Finished Aug 15 05:11:03 PM PDT 24
Peak memory 226116 kb
Host smart-0a8d86cd-4c26-41f9-a149-38312e7e0312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686885986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1686885986
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3909414194
Short name T667
Test name
Test status
Simulation time 2582362252 ps
CPU time 6.36 seconds
Started Aug 15 05:10:43 PM PDT 24
Finished Aug 15 05:10:49 PM PDT 24
Peak memory 217876 kb
Host smart-6e3b3700-c0e6-4371-93b2-55e0f67256ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909414194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3909414194
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1372677587
Short name T522
Test name
Test status
Simulation time 79310004 ps
CPU time 3.16 seconds
Started Aug 15 05:10:30 PM PDT 24
Finished Aug 15 05:10:34 PM PDT 24
Peak memory 218328 kb
Host smart-05e372e4-8031-4257-996b-d2bc3acbd51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372677587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1372677587
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3719949405
Short name T534
Test name
Test status
Simulation time 214034664 ps
CPU time 8.45 seconds
Started Aug 15 05:10:41 PM PDT 24
Finished Aug 15 05:10:50 PM PDT 24
Peak memory 218424 kb
Host smart-21f571c6-8427-43ac-ad0d-127a1ac9dbb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719949405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3719949405
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2586197133
Short name T739
Test name
Test status
Simulation time 1703925253 ps
CPU time 18.55 seconds
Started Aug 15 05:10:44 PM PDT 24
Finished Aug 15 05:11:03 PM PDT 24
Peak memory 226048 kb
Host smart-77ce842f-7adf-4c95-abc7-40809e2a75b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586197133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2586197133
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3753655605
Short name T416
Test name
Test status
Simulation time 1089622953 ps
CPU time 8.25 seconds
Started Aug 15 05:10:43 PM PDT 24
Finished Aug 15 05:10:51 PM PDT 24
Peak memory 218224 kb
Host smart-e1875a3f-0841-4666-b246-ca31ef0b8770
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753655605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3753655605
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1389443955
Short name T212
Test name
Test status
Simulation time 5810394441 ps
CPU time 12.07 seconds
Started Aug 15 05:10:46 PM PDT 24
Finished Aug 15 05:10:58 PM PDT 24
Peak memory 218448 kb
Host smart-5a7e653c-8233-4794-8b61-f429a00d5165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389443955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1389443955
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2678336008
Short name T320
Test name
Test status
Simulation time 150045039 ps
CPU time 6.23 seconds
Started Aug 15 05:10:28 PM PDT 24
Finished Aug 15 05:10:35 PM PDT 24
Peak memory 217664 kb
Host smart-92a61e62-bb53-4b43-a4a2-6fec26260b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678336008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2678336008
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.181309319
Short name T795
Test name
Test status
Simulation time 593249164 ps
CPU time 29.03 seconds
Started Aug 15 05:10:28 PM PDT 24
Finished Aug 15 05:10:57 PM PDT 24
Peak memory 247176 kb
Host smart-58ad9255-1236-47c6-aaae-52d7d7ffe80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181309319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.181309319
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3345346576
Short name T623
Test name
Test status
Simulation time 101735576 ps
CPU time 3.72 seconds
Started Aug 15 05:10:28 PM PDT 24
Finished Aug 15 05:10:32 PM PDT 24
Peak memory 218264 kb
Host smart-35cb263e-ea49-4b30-9379-22dead2d4d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345346576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3345346576
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3766368267
Short name T779
Test name
Test status
Simulation time 28245893889 ps
CPU time 156.62 seconds
Started Aug 15 05:10:42 PM PDT 24
Finished Aug 15 05:13:19 PM PDT 24
Peak memory 316500 kb
Host smart-ab2873bf-c4dd-45e1-b565-6cc493ff5541
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766368267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3766368267
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.389269249
Short name T701
Test name
Test status
Simulation time 73392793 ps
CPU time 0.76 seconds
Started Aug 15 05:10:32 PM PDT 24
Finished Aug 15 05:10:33 PM PDT 24
Peak memory 207948 kb
Host smart-0fed5560-c9d4-4b58-b351-5175f07eea2c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389269249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.389269249
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2930027213
Short name T342
Test name
Test status
Simulation time 29825351 ps
CPU time 0.84 seconds
Started Aug 15 05:10:42 PM PDT 24
Finished Aug 15 05:10:43 PM PDT 24
Peak memory 208812 kb
Host smart-5222f96e-5895-405c-b457-0c7e2f59d9f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930027213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2930027213
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.4251769156
Short name T34
Test name
Test status
Simulation time 1733602835 ps
CPU time 18.73 seconds
Started Aug 15 05:10:43 PM PDT 24
Finished Aug 15 05:11:02 PM PDT 24
Peak memory 226044 kb
Host smart-66caf8cf-73ce-4fee-869d-1adb190dae53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251769156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.4251769156
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1674955355
Short name T455
Test name
Test status
Simulation time 717289601 ps
CPU time 8.09 seconds
Started Aug 15 05:10:40 PM PDT 24
Finished Aug 15 05:10:49 PM PDT 24
Peak memory 217488 kb
Host smart-f56b722e-d575-42b8-90e2-d962b93e7b0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674955355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1674955355
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1571638468
Short name T222
Test name
Test status
Simulation time 86212610 ps
CPU time 3.92 seconds
Started Aug 15 05:10:43 PM PDT 24
Finished Aug 15 05:10:47 PM PDT 24
Peak memory 218284 kb
Host smart-9c5639d1-961b-4f0d-a83d-c61c01adcc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571638468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1571638468
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2672501412
Short name T39
Test name
Test status
Simulation time 347895129 ps
CPU time 14.37 seconds
Started Aug 15 05:10:45 PM PDT 24
Finished Aug 15 05:10:59 PM PDT 24
Peak memory 226112 kb
Host smart-0645c0a4-ca3b-4d1b-b1ab-18e35513ad4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672501412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2672501412
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3087953926
Short name T291
Test name
Test status
Simulation time 2034707748 ps
CPU time 15.25 seconds
Started Aug 15 05:10:42 PM PDT 24
Finished Aug 15 05:10:58 PM PDT 24
Peak memory 218332 kb
Host smart-0586b94a-e7a2-4f03-9451-da93b3e7d696
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087953926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3087953926
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.249789237
Short name T324
Test name
Test status
Simulation time 450784015 ps
CPU time 12.32 seconds
Started Aug 15 05:10:44 PM PDT 24
Finished Aug 15 05:10:56 PM PDT 24
Peak memory 218300 kb
Host smart-e78f4208-dee8-48d5-9967-1f00bf2ffa1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249789237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.249789237
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2266200847
Short name T456
Test name
Test status
Simulation time 682718603 ps
CPU time 12.66 seconds
Started Aug 15 05:10:44 PM PDT 24
Finished Aug 15 05:10:56 PM PDT 24
Peak memory 218280 kb
Host smart-29e745fb-10a9-4e27-871e-8bd614efa336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266200847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2266200847
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3435115889
Short name T449
Test name
Test status
Simulation time 62925967 ps
CPU time 1.82 seconds
Started Aug 15 05:10:43 PM PDT 24
Finished Aug 15 05:10:45 PM PDT 24
Peak memory 214236 kb
Host smart-0bd8b9c5-362e-4b2f-b50e-b2adc1779342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435115889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3435115889
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.497475260
Short name T648
Test name
Test status
Simulation time 2280375162 ps
CPU time 26.25 seconds
Started Aug 15 05:10:42 PM PDT 24
Finished Aug 15 05:11:08 PM PDT 24
Peak memory 251096 kb
Host smart-7e1e0418-4708-49ee-8758-4471e1eeaecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497475260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.497475260
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3723423748
Short name T426
Test name
Test status
Simulation time 84603464 ps
CPU time 3.73 seconds
Started Aug 15 05:10:42 PM PDT 24
Finished Aug 15 05:10:46 PM PDT 24
Peak memory 222856 kb
Host smart-ab6246d5-1370-418e-8623-a85744406355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723423748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3723423748
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3434221734
Short name T146
Test name
Test status
Simulation time 3640036499 ps
CPU time 115.79 seconds
Started Aug 15 05:10:42 PM PDT 24
Finished Aug 15 05:12:38 PM PDT 24
Peak memory 253636 kb
Host smart-36304ef8-7ae7-4268-b1f6-d7dba4532cff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3434221734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.3434221734
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3642862480
Short name T293
Test name
Test status
Simulation time 54508489 ps
CPU time 1.09 seconds
Started Aug 15 05:10:43 PM PDT 24
Finished Aug 15 05:10:45 PM PDT 24
Peak memory 217904 kb
Host smart-9e9c3067-22e4-4a8c-9cee-52b6997abc62
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642862480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3642862480
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2848401440
Short name T848
Test name
Test status
Simulation time 71538144 ps
CPU time 0.98 seconds
Started Aug 15 05:10:41 PM PDT 24
Finished Aug 15 05:10:42 PM PDT 24
Peak memory 209004 kb
Host smart-30b66893-b41e-4e3f-867e-6819b339fa16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848401440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2848401440
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.783929816
Short name T846
Test name
Test status
Simulation time 1618392848 ps
CPU time 14.54 seconds
Started Aug 15 05:10:46 PM PDT 24
Finished Aug 15 05:11:01 PM PDT 24
Peak memory 218416 kb
Host smart-9844e625-cef4-491f-ad4e-f840b03f9bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783929816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.783929816
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1491619081
Short name T425
Test name
Test status
Simulation time 385277322 ps
CPU time 5.7 seconds
Started Aug 15 05:10:45 PM PDT 24
Finished Aug 15 05:10:51 PM PDT 24
Peak memory 217752 kb
Host smart-c5f32529-9de6-488b-b216-0b56816c86a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491619081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1491619081
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1174851963
Short name T328
Test name
Test status
Simulation time 28327539 ps
CPU time 1.99 seconds
Started Aug 15 05:10:42 PM PDT 24
Finished Aug 15 05:10:44 PM PDT 24
Peak memory 218328 kb
Host smart-9989a840-d6ca-419a-a5a2-304912de07d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174851963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1174851963
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2901018657
Short name T733
Test name
Test status
Simulation time 10243484516 ps
CPU time 19.12 seconds
Started Aug 15 05:10:46 PM PDT 24
Finished Aug 15 05:11:05 PM PDT 24
Peak memory 219188 kb
Host smart-2a485f05-e62b-4474-8da0-a80607a6815e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901018657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2901018657
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3755938329
Short name T281
Test name
Test status
Simulation time 270955133 ps
CPU time 10.93 seconds
Started Aug 15 05:10:43 PM PDT 24
Finished Aug 15 05:10:54 PM PDT 24
Peak memory 226100 kb
Host smart-2e025c6f-05a8-4d5d-afc3-719c4ea1a077
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755938329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3755938329
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3107703782
Short name T576
Test name
Test status
Simulation time 296032739 ps
CPU time 7.8 seconds
Started Aug 15 05:10:43 PM PDT 24
Finished Aug 15 05:10:51 PM PDT 24
Peak memory 225996 kb
Host smart-934f43d1-95b1-49c9-a5ad-8a36e3371a8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107703782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3107703782
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2717489151
Short name T214
Test name
Test status
Simulation time 3231536683 ps
CPU time 10.46 seconds
Started Aug 15 05:10:41 PM PDT 24
Finished Aug 15 05:10:52 PM PDT 24
Peak memory 218552 kb
Host smart-9067a268-866e-44a1-84ba-efcdde4f48ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717489151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2717489151
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1946626697
Short name T236
Test name
Test status
Simulation time 15455125 ps
CPU time 1.2 seconds
Started Aug 15 05:10:44 PM PDT 24
Finished Aug 15 05:10:46 PM PDT 24
Peak memory 217688 kb
Host smart-698daac6-550b-4b79-ad35-51efeedef775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946626697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1946626697
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2624481027
Short name T107
Test name
Test status
Simulation time 1700815435 ps
CPU time 21.7 seconds
Started Aug 15 05:10:43 PM PDT 24
Finished Aug 15 05:11:05 PM PDT 24
Peak memory 250952 kb
Host smart-366d23da-41d9-49d6-a2cb-8e18c83c2062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624481027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2624481027
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3784005261
Short name T631
Test name
Test status
Simulation time 73976615 ps
CPU time 3.47 seconds
Started Aug 15 05:10:46 PM PDT 24
Finished Aug 15 05:10:50 PM PDT 24
Peak memory 222652 kb
Host smart-4d9ea2e3-cfb4-417f-824c-9cf74e180862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784005261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3784005261
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1308145913
Short name T405
Test name
Test status
Simulation time 9647645229 ps
CPU time 100.77 seconds
Started Aug 15 05:10:43 PM PDT 24
Finished Aug 15 05:12:24 PM PDT 24
Peak memory 270444 kb
Host smart-f07baaef-d494-43ec-9dda-46cbd12a7ab9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308145913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1308145913
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.671343181
Short name T11
Test name
Test status
Simulation time 47504150 ps
CPU time 0.97 seconds
Started Aug 15 05:10:42 PM PDT 24
Finished Aug 15 05:10:43 PM PDT 24
Peak memory 217848 kb
Host smart-1d1eab32-4ab9-4031-8a85-bc52afff9de9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671343181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.671343181
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.167250120
Short name T453
Test name
Test status
Simulation time 36764201 ps
CPU time 1.19 seconds
Started Aug 15 05:10:48 PM PDT 24
Finished Aug 15 05:10:49 PM PDT 24
Peak memory 209016 kb
Host smart-e5056927-0486-464f-8af6-7e4294ba47ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167250120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.167250120
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2095236751
Short name T414
Test name
Test status
Simulation time 3706286847 ps
CPU time 8.7 seconds
Started Aug 15 05:10:45 PM PDT 24
Finished Aug 15 05:10:54 PM PDT 24
Peak memory 218684 kb
Host smart-4c318082-c441-4654-9b2a-5b5e30b8a044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095236751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2095236751
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3235773194
Short name T615
Test name
Test status
Simulation time 16233321088 ps
CPU time 26.73 seconds
Started Aug 15 05:10:49 PM PDT 24
Finished Aug 15 05:11:16 PM PDT 24
Peak memory 217768 kb
Host smart-f528dea6-07bf-4c3c-97bd-82414308eb04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235773194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3235773194
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2440246003
Short name T367
Test name
Test status
Simulation time 76375391 ps
CPU time 3.22 seconds
Started Aug 15 05:10:49 PM PDT 24
Finished Aug 15 05:10:52 PM PDT 24
Peak memory 218312 kb
Host smart-b770a248-ab7d-43a7-9c1e-7cdbb3c7bf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440246003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2440246003
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1183214254
Short name T655
Test name
Test status
Simulation time 325323098 ps
CPU time 15.05 seconds
Started Aug 15 05:10:47 PM PDT 24
Finished Aug 15 05:11:02 PM PDT 24
Peak memory 220020 kb
Host smart-c3ae82a3-2836-49d8-b825-d15823f152fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183214254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1183214254
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3649267929
Short name T569
Test name
Test status
Simulation time 2057633365 ps
CPU time 19.63 seconds
Started Aug 15 05:10:49 PM PDT 24
Finished Aug 15 05:11:08 PM PDT 24
Peak memory 226044 kb
Host smart-4db5f9de-1a0e-458b-8da7-749ccfe07d8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649267929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3649267929
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.360216377
Short name T797
Test name
Test status
Simulation time 487360134 ps
CPU time 10.76 seconds
Started Aug 15 05:10:43 PM PDT 24
Finished Aug 15 05:10:54 PM PDT 24
Peak memory 218320 kb
Host smart-74eee343-c4ef-4915-b7d8-79b7567dc979
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360216377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.360216377
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3906706657
Short name T394
Test name
Test status
Simulation time 1083836012 ps
CPU time 6.48 seconds
Started Aug 15 05:10:47 PM PDT 24
Finished Aug 15 05:10:54 PM PDT 24
Peak memory 218424 kb
Host smart-0523632f-09a0-446f-a3ae-cdca9999599f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906706657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3906706657
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3141915016
Short name T386
Test name
Test status
Simulation time 103973516 ps
CPU time 1.85 seconds
Started Aug 15 05:10:42 PM PDT 24
Finished Aug 15 05:10:45 PM PDT 24
Peak memory 217752 kb
Host smart-acdb783a-476d-4e3a-8aff-94ca19a20b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141915016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3141915016
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.228736451
Short name T27
Test name
Test status
Simulation time 699609127 ps
CPU time 21.22 seconds
Started Aug 15 05:10:43 PM PDT 24
Finished Aug 15 05:11:04 PM PDT 24
Peak memory 250940 kb
Host smart-65574f68-c8f2-4676-ae6b-4a07575d3e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228736451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.228736451
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.804745180
Short name T639
Test name
Test status
Simulation time 123852014 ps
CPU time 9.03 seconds
Started Aug 15 05:10:45 PM PDT 24
Finished Aug 15 05:10:55 PM PDT 24
Peak memory 250948 kb
Host smart-843c9d7e-c222-4b8d-ab53-d96412dc62ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804745180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.804745180
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3572546785
Short name T632
Test name
Test status
Simulation time 2674624396 ps
CPU time 90.28 seconds
Started Aug 15 05:10:45 PM PDT 24
Finished Aug 15 05:12:16 PM PDT 24
Peak memory 250916 kb
Host smart-5807739d-89d3-4426-9f59-f497ccf064e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572546785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3572546785
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3289555310
Short name T406
Test name
Test status
Simulation time 121292711 ps
CPU time 0.99 seconds
Started Aug 15 05:10:48 PM PDT 24
Finished Aug 15 05:10:50 PM PDT 24
Peak memory 211972 kb
Host smart-dd687692-7376-4db9-ae86-aa76bc15ed8a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289555310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3289555310
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1188172233
Short name T86
Test name
Test status
Simulation time 37574809 ps
CPU time 0.84 seconds
Started Aug 15 05:07:58 PM PDT 24
Finished Aug 15 05:07:59 PM PDT 24
Peak memory 208756 kb
Host smart-ada260a8-58f8-4535-b041-6b1e9288e7f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188172233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1188172233
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2708112651
Short name T708
Test name
Test status
Simulation time 107582754 ps
CPU time 0.94 seconds
Started Aug 15 05:07:46 PM PDT 24
Finished Aug 15 05:07:47 PM PDT 24
Peak memory 208788 kb
Host smart-eccd8538-8e92-4e46-ba33-8782a30ccd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708112651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2708112651
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1252124572
Short name T37
Test name
Test status
Simulation time 1560602491 ps
CPU time 17.11 seconds
Started Aug 15 05:07:47 PM PDT 24
Finished Aug 15 05:08:04 PM PDT 24
Peak memory 218308 kb
Host smart-43ecb77a-dfe2-4919-9ca5-f893591bc542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252124572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1252124572
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.519430142
Short name T6
Test name
Test status
Simulation time 2231602413 ps
CPU time 13.01 seconds
Started Aug 15 05:07:50 PM PDT 24
Finished Aug 15 05:08:04 PM PDT 24
Peak memory 217840 kb
Host smart-e8ecbbe5-4e3f-4117-9138-4730ff5d734d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519430142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.519430142
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.529741247
Short name T518
Test name
Test status
Simulation time 4110206435 ps
CPU time 58.69 seconds
Started Aug 15 05:07:48 PM PDT 24
Finished Aug 15 05:08:47 PM PDT 24
Peak memory 220300 kb
Host smart-cfeea724-b595-4107-8d4a-aad9374a2fc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529741247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.529741247
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2269282531
Short name T869
Test name
Test status
Simulation time 392849881 ps
CPU time 3.25 seconds
Started Aug 15 05:07:48 PM PDT 24
Finished Aug 15 05:07:51 PM PDT 24
Peak memory 217844 kb
Host smart-4e41ca55-e3ce-4028-8a37-9a335eb3dcb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269282531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
269282531
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3784521326
Short name T782
Test name
Test status
Simulation time 2250220847 ps
CPU time 14.3 seconds
Started Aug 15 05:07:49 PM PDT 24
Finished Aug 15 05:08:03 PM PDT 24
Peak memory 221984 kb
Host smart-c39322bf-aba5-4aea-a58e-cd1a16f13c65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784521326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3784521326
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2158677160
Short name T548
Test name
Test status
Simulation time 2388520662 ps
CPU time 19.11 seconds
Started Aug 15 05:07:48 PM PDT 24
Finished Aug 15 05:08:07 PM PDT 24
Peak memory 217736 kb
Host smart-827e9bf3-7ecb-41db-948b-5da6013235cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158677160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2158677160
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1632198362
Short name T276
Test name
Test status
Simulation time 1057732016 ps
CPU time 13.81 seconds
Started Aug 15 05:07:47 PM PDT 24
Finished Aug 15 05:08:01 PM PDT 24
Peak memory 217704 kb
Host smart-de53ce92-8a3d-4459-a3e1-0044b5128cc9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632198362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1632198362
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2303567460
Short name T442
Test name
Test status
Simulation time 5663313521 ps
CPU time 36.32 seconds
Started Aug 15 05:07:47 PM PDT 24
Finished Aug 15 05:08:24 PM PDT 24
Peak memory 268456 kb
Host smart-53a281e4-6982-43b4-b090-22f6d9a60ab8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303567460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2303567460
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1742095965
Short name T399
Test name
Test status
Simulation time 7163004617 ps
CPU time 21.63 seconds
Started Aug 15 05:07:47 PM PDT 24
Finished Aug 15 05:08:09 PM PDT 24
Peak memory 250960 kb
Host smart-5e9291b8-edc5-4a48-9b03-18402734bcf5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742095965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1742095965
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1687201785
Short name T652
Test name
Test status
Simulation time 19458061 ps
CPU time 1.51 seconds
Started Aug 15 05:07:52 PM PDT 24
Finished Aug 15 05:07:54 PM PDT 24
Peak memory 218280 kb
Host smart-e3a79e26-8ff5-480c-85ca-68da7e849af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687201785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1687201785
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.114821805
Short name T73
Test name
Test status
Simulation time 1538042744 ps
CPU time 8.58 seconds
Started Aug 15 05:07:45 PM PDT 24
Finished Aug 15 05:07:53 PM PDT 24
Peak memory 217728 kb
Host smart-25fde9e5-04a8-477f-be49-6d2a43987f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114821805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.114821805
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.761477426
Short name T84
Test name
Test status
Simulation time 436643769 ps
CPU time 39.2 seconds
Started Aug 15 05:07:53 PM PDT 24
Finished Aug 15 05:08:33 PM PDT 24
Peak memory 271400 kb
Host smart-ca71156c-aafd-409f-a11b-29c5b6c8d89c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761477426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.761477426
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.4292065085
Short name T684
Test name
Test status
Simulation time 628948762 ps
CPU time 15.16 seconds
Started Aug 15 05:07:55 PM PDT 24
Finished Aug 15 05:08:10 PM PDT 24
Peak memory 219052 kb
Host smart-5f97a109-653c-43bb-b1cb-32ba6d9977ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292065085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.4292065085
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1656395498
Short name T549
Test name
Test status
Simulation time 385946606 ps
CPU time 15.74 seconds
Started Aug 15 05:07:55 PM PDT 24
Finished Aug 15 05:08:11 PM PDT 24
Peak memory 226056 kb
Host smart-3d4e8f5c-d557-48bb-88a8-b3f7d9c9a4ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656395498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1656395498
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3046852734
Short name T57
Test name
Test status
Simulation time 773693492 ps
CPU time 9.29 seconds
Started Aug 15 05:07:58 PM PDT 24
Finished Aug 15 05:08:08 PM PDT 24
Peak memory 225980 kb
Host smart-f811bd8a-b6eb-41d1-a124-80b6608d3958
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046852734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
046852734
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2386620922
Short name T521
Test name
Test status
Simulation time 353906835 ps
CPU time 14.27 seconds
Started Aug 15 05:07:49 PM PDT 24
Finished Aug 15 05:08:03 PM PDT 24
Peak memory 218324 kb
Host smart-4bcfbdff-0dab-4fe7-ac10-2380d4357628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386620922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2386620922
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3748444659
Short name T694
Test name
Test status
Simulation time 353384830 ps
CPU time 5.85 seconds
Started Aug 15 05:07:48 PM PDT 24
Finished Aug 15 05:07:54 PM PDT 24
Peak memory 217676 kb
Host smart-0e40a073-7c30-4ef4-8231-9c89e6031bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748444659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3748444659
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3579293527
Short name T558
Test name
Test status
Simulation time 978295059 ps
CPU time 20.82 seconds
Started Aug 15 05:07:48 PM PDT 24
Finished Aug 15 05:08:09 PM PDT 24
Peak memory 250664 kb
Host smart-bacaf4d0-e82e-4b5e-8903-3e830fa630b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579293527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3579293527
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2230089839
Short name T380
Test name
Test status
Simulation time 209369192 ps
CPU time 8.39 seconds
Started Aug 15 05:07:49 PM PDT 24
Finished Aug 15 05:07:57 PM PDT 24
Peak memory 250980 kb
Host smart-15bc45f2-cba6-4d65-910a-fedf6f07a02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230089839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2230089839
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1897942566
Short name T796
Test name
Test status
Simulation time 12425924979 ps
CPU time 145.67 seconds
Started Aug 15 05:07:55 PM PDT 24
Finished Aug 15 05:10:21 PM PDT 24
Peak memory 238932 kb
Host smart-8fe92cde-b9c3-43fa-a232-2f7299613e72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897942566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1897942566
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.527789474
Short name T737
Test name
Test status
Simulation time 14935008 ps
CPU time 1.14 seconds
Started Aug 15 05:07:49 PM PDT 24
Finished Aug 15 05:07:50 PM PDT 24
Peak memory 212052 kb
Host smart-66f2b295-2777-4e00-b1b5-a10c5a9e338a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527789474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.527789474
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.647766493
Short name T93
Test name
Test status
Simulation time 77519307 ps
CPU time 0.94 seconds
Started Aug 15 05:10:45 PM PDT 24
Finished Aug 15 05:10:46 PM PDT 24
Peak memory 208916 kb
Host smart-126218a1-604f-4961-a8ff-469dae1e6086
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647766493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.647766493
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.82789383
Short name T29
Test name
Test status
Simulation time 555528370 ps
CPU time 9.88 seconds
Started Aug 15 05:10:47 PM PDT 24
Finished Aug 15 05:10:57 PM PDT 24
Peak memory 218292 kb
Host smart-b435c1f8-1688-42e7-abc4-97780139041b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82789383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.82789383
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2170404338
Short name T20
Test name
Test status
Simulation time 2718121447 ps
CPU time 16.83 seconds
Started Aug 15 05:10:46 PM PDT 24
Finished Aug 15 05:11:03 PM PDT 24
Peak memory 217792 kb
Host smart-5a11c549-8f77-41b5-b3d8-d100881e8bd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170404338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2170404338
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2269411109
Short name T724
Test name
Test status
Simulation time 43161526 ps
CPU time 2.04 seconds
Started Aug 15 05:10:47 PM PDT 24
Finished Aug 15 05:10:50 PM PDT 24
Peak memory 218312 kb
Host smart-9e158468-b15a-47cd-81e7-20a661776980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269411109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2269411109
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3928605649
Short name T771
Test name
Test status
Simulation time 327307239 ps
CPU time 14.88 seconds
Started Aug 15 05:10:45 PM PDT 24
Finished Aug 15 05:11:00 PM PDT 24
Peak memory 218348 kb
Host smart-324648df-2558-4a59-a167-87362dac1048
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928605649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3928605649
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.637710197
Short name T538
Test name
Test status
Simulation time 798542951 ps
CPU time 9.37 seconds
Started Aug 15 05:10:47 PM PDT 24
Finished Aug 15 05:10:56 PM PDT 24
Peak memory 225928 kb
Host smart-375ee932-31fe-454a-9670-47086b507cda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637710197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.637710197
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1471760859
Short name T507
Test name
Test status
Simulation time 1025596982 ps
CPU time 11.13 seconds
Started Aug 15 05:10:46 PM PDT 24
Finished Aug 15 05:10:57 PM PDT 24
Peak memory 226080 kb
Host smart-01429f01-e7ce-4274-8186-85de955b1121
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471760859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1471760859
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2267093533
Short name T706
Test name
Test status
Simulation time 295608707 ps
CPU time 7.31 seconds
Started Aug 15 05:10:45 PM PDT 24
Finished Aug 15 05:10:52 PM PDT 24
Peak memory 218352 kb
Host smart-0374aa55-46fe-45c5-9aed-4c81f5cce41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267093533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2267093533
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2630486618
Short name T55
Test name
Test status
Simulation time 530337680 ps
CPU time 3.17 seconds
Started Aug 15 05:10:46 PM PDT 24
Finished Aug 15 05:10:50 PM PDT 24
Peak memory 217808 kb
Host smart-287d959c-4201-4e89-b9ed-586ccae8bd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630486618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2630486618
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3070643209
Short name T550
Test name
Test status
Simulation time 1547865682 ps
CPU time 22.57 seconds
Started Aug 15 05:10:48 PM PDT 24
Finished Aug 15 05:11:11 PM PDT 24
Peak memory 250944 kb
Host smart-0b6ae77d-796f-4827-b582-c2d5ba49446a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070643209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3070643209
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.160511646
Short name T567
Test name
Test status
Simulation time 98720846 ps
CPU time 7.5 seconds
Started Aug 15 05:10:46 PM PDT 24
Finished Aug 15 05:10:54 PM PDT 24
Peak memory 250932 kb
Host smart-d5a156ff-b58a-4bdc-9afe-8dbf802034bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160511646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.160511646
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2427269109
Short name T683
Test name
Test status
Simulation time 5898712778 ps
CPU time 36.26 seconds
Started Aug 15 05:10:47 PM PDT 24
Finished Aug 15 05:11:23 PM PDT 24
Peak memory 252352 kb
Host smart-73744368-dc77-4575-96c5-71a93d056d7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427269109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2427269109
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2971466554
Short name T344
Test name
Test status
Simulation time 42864734 ps
CPU time 0.8 seconds
Started Aug 15 05:10:48 PM PDT 24
Finished Aug 15 05:10:50 PM PDT 24
Peak memory 208836 kb
Host smart-6ea9df9d-a230-48e8-b42d-beb9a10bfeb0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971466554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2971466554
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2785770032
Short name T322
Test name
Test status
Simulation time 90947312 ps
CPU time 1.09 seconds
Started Aug 15 05:10:52 PM PDT 24
Finished Aug 15 05:10:53 PM PDT 24
Peak memory 209144 kb
Host smart-0ba470c9-89a9-4428-8c92-579665d702b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785770032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2785770032
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1099974049
Short name T483
Test name
Test status
Simulation time 1406010405 ps
CPU time 15.37 seconds
Started Aug 15 05:10:49 PM PDT 24
Finished Aug 15 05:11:04 PM PDT 24
Peak memory 218292 kb
Host smart-075eb6e1-de91-4359-9675-1aa75efae45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099974049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1099974049
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3315852579
Short name T647
Test name
Test status
Simulation time 1435559284 ps
CPU time 4.36 seconds
Started Aug 15 05:10:52 PM PDT 24
Finished Aug 15 05:10:56 PM PDT 24
Peak memory 217776 kb
Host smart-d28b83bd-5221-4e1f-8b02-f774ae56ebe2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315852579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3315852579
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2386436824
Short name T595
Test name
Test status
Simulation time 65856952 ps
CPU time 3.49 seconds
Started Aug 15 05:10:45 PM PDT 24
Finished Aug 15 05:10:49 PM PDT 24
Peak memory 222668 kb
Host smart-1c6bc4d4-706b-44e1-b390-6d37c93612e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386436824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2386436824
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2135282973
Short name T259
Test name
Test status
Simulation time 379845368 ps
CPU time 10.46 seconds
Started Aug 15 05:10:56 PM PDT 24
Finished Aug 15 05:11:07 PM PDT 24
Peak memory 218980 kb
Host smart-66653cd1-b9f8-4738-9aa6-2fed2b2dffcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135282973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2135282973
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1818761371
Short name T392
Test name
Test status
Simulation time 1068672978 ps
CPU time 12.88 seconds
Started Aug 15 05:10:51 PM PDT 24
Finished Aug 15 05:11:04 PM PDT 24
Peak memory 225972 kb
Host smart-caff6567-13ab-45ff-ad09-0cfdfcab73e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818761371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1818761371
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.734773045
Short name T419
Test name
Test status
Simulation time 1417041694 ps
CPU time 10.19 seconds
Started Aug 15 05:10:53 PM PDT 24
Finished Aug 15 05:11:03 PM PDT 24
Peak memory 218308 kb
Host smart-951e6aa1-0ba0-4559-8c3e-7c35da8e0985
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734773045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.734773045
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3240315411
Short name T546
Test name
Test status
Simulation time 1232328115 ps
CPU time 10.17 seconds
Started Aug 15 05:10:49 PM PDT 24
Finished Aug 15 05:10:59 PM PDT 24
Peak memory 218408 kb
Host smart-826a0288-2e71-4f4d-9f92-813ddbfc8514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240315411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3240315411
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.274521627
Short name T264
Test name
Test status
Simulation time 27982735 ps
CPU time 2.37 seconds
Started Aug 15 05:10:44 PM PDT 24
Finished Aug 15 05:10:47 PM PDT 24
Peak memory 214116 kb
Host smart-5f78f1e8-3a9a-456e-8a30-b56d72d44061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274521627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.274521627
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.794919614
Short name T397
Test name
Test status
Simulation time 932817616 ps
CPU time 21.42 seconds
Started Aug 15 05:10:47 PM PDT 24
Finished Aug 15 05:11:08 PM PDT 24
Peak memory 250952 kb
Host smart-0cdeb04c-1fb4-4177-98eb-d6a0c3edd1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794919614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.794919614
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3939862167
Short name T217
Test name
Test status
Simulation time 76499011 ps
CPU time 3.41 seconds
Started Aug 15 05:10:48 PM PDT 24
Finished Aug 15 05:10:52 PM PDT 24
Peak memory 226364 kb
Host smart-486d208f-ad6a-41aa-ba4b-e536779bb19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939862167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3939862167
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2628579316
Short name T357
Test name
Test status
Simulation time 8829661871 ps
CPU time 271.18 seconds
Started Aug 15 05:10:54 PM PDT 24
Finished Aug 15 05:15:25 PM PDT 24
Peak memory 283784 kb
Host smart-61e72374-b88a-42f2-9764-5518119a297e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628579316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2628579316
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.1477287021
Short name T143
Test name
Test status
Simulation time 1198595897 ps
CPU time 42.6 seconds
Started Aug 15 05:10:50 PM PDT 24
Finished Aug 15 05:11:32 PM PDT 24
Peak memory 250724 kb
Host smart-663c63c5-e97b-411d-bc09-08d0ca6f3274
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1477287021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.1477287021
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2229806983
Short name T351
Test name
Test status
Simulation time 24574645 ps
CPU time 0.93 seconds
Started Aug 15 05:10:47 PM PDT 24
Finished Aug 15 05:10:48 PM PDT 24
Peak memory 209040 kb
Host smart-b0406569-55cb-43dc-be68-7f4a40d725d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229806983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2229806983
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1171625656
Short name T280
Test name
Test status
Simulation time 55957041 ps
CPU time 1.04 seconds
Started Aug 15 05:10:54 PM PDT 24
Finished Aug 15 05:10:55 PM PDT 24
Peak memory 209020 kb
Host smart-241da9c2-70ca-427f-914e-6f1c1a09db1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171625656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1171625656
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2878221550
Short name T253
Test name
Test status
Simulation time 224445024 ps
CPU time 10.08 seconds
Started Aug 15 05:10:55 PM PDT 24
Finished Aug 15 05:11:05 PM PDT 24
Peak memory 226084 kb
Host smart-5d463195-924a-4f77-acd4-edbdf57df1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878221550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2878221550
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.4208687398
Short name T445
Test name
Test status
Simulation time 212222943 ps
CPU time 6.03 seconds
Started Aug 15 05:10:55 PM PDT 24
Finished Aug 15 05:11:01 PM PDT 24
Peak memory 217292 kb
Host smart-26b8f677-3228-4799-9683-67ed81050b93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208687398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.4208687398
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.347117967
Short name T832
Test name
Test status
Simulation time 74819847 ps
CPU time 2.93 seconds
Started Aug 15 05:10:51 PM PDT 24
Finished Aug 15 05:10:54 PM PDT 24
Peak memory 218300 kb
Host smart-87e20fd9-ff3b-4c98-9115-e27aa2bf8a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347117967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.347117967
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1189441054
Short name T389
Test name
Test status
Simulation time 1279911458 ps
CPU time 15.46 seconds
Started Aug 15 05:10:51 PM PDT 24
Finished Aug 15 05:11:07 PM PDT 24
Peak memory 218964 kb
Host smart-fe06fdf4-fba9-4be8-8fe5-9b7e08fdd829
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189441054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1189441054
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1399839510
Short name T345
Test name
Test status
Simulation time 365961874 ps
CPU time 10.68 seconds
Started Aug 15 05:10:52 PM PDT 24
Finished Aug 15 05:11:03 PM PDT 24
Peak memory 226092 kb
Host smart-2268822b-ffa3-4a21-a104-e499ebd697b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399839510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1399839510
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2068279312
Short name T580
Test name
Test status
Simulation time 1138412019 ps
CPU time 8.14 seconds
Started Aug 15 05:10:53 PM PDT 24
Finished Aug 15 05:11:01 PM PDT 24
Peak memory 226072 kb
Host smart-fafa394b-d901-4d2f-8652-afa963edd345
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068279312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2068279312
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2749159981
Short name T571
Test name
Test status
Simulation time 5031270589 ps
CPU time 10.58 seconds
Started Aug 15 05:10:53 PM PDT 24
Finished Aug 15 05:11:04 PM PDT 24
Peak memory 218480 kb
Host smart-f5013e3c-b9b7-49d5-a61c-cc3382ac735e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749159981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2749159981
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2031778842
Short name T748
Test name
Test status
Simulation time 122219869 ps
CPU time 3.26 seconds
Started Aug 15 05:10:54 PM PDT 24
Finished Aug 15 05:10:58 PM PDT 24
Peak memory 217668 kb
Host smart-fa77221d-e7c4-4007-b9cc-86e793a3394e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031778842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2031778842
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.2636799004
Short name T371
Test name
Test status
Simulation time 1028140803 ps
CPU time 20.56 seconds
Started Aug 15 05:10:49 PM PDT 24
Finished Aug 15 05:11:10 PM PDT 24
Peak memory 250820 kb
Host smart-b329dd06-9e3c-4d23-91b8-cb8455682a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636799004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2636799004
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2515972628
Short name T400
Test name
Test status
Simulation time 172865989 ps
CPU time 2.63 seconds
Started Aug 15 05:10:51 PM PDT 24
Finished Aug 15 05:10:54 PM PDT 24
Peak memory 218240 kb
Host smart-b59d9f11-72d6-4819-bf61-bb2d7d75f2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515972628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2515972628
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3730010370
Short name T675
Test name
Test status
Simulation time 17350181213 ps
CPU time 111.13 seconds
Started Aug 15 05:10:52 PM PDT 24
Finished Aug 15 05:12:44 PM PDT 24
Peak memory 332976 kb
Host smart-23d0d6ba-b31b-44fc-8b08-aca062c5cd9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730010370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3730010370
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.1930010679
Short name T664
Test name
Test status
Simulation time 3083134782 ps
CPU time 92.44 seconds
Started Aug 15 05:10:53 PM PDT 24
Finished Aug 15 05:12:26 PM PDT 24
Peak memory 278856 kb
Host smart-538eaf49-05c7-40af-845b-6e72f2a275b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1930010679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.1930010679
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3023637495
Short name T33
Test name
Test status
Simulation time 29506251 ps
CPU time 0.78 seconds
Started Aug 15 05:10:52 PM PDT 24
Finished Aug 15 05:10:53 PM PDT 24
Peak memory 208840 kb
Host smart-738d3398-c925-4c9c-90cc-8bceb21e3552
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023637495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3023637495
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.29124982
Short name T616
Test name
Test status
Simulation time 19611544 ps
CPU time 0.96 seconds
Started Aug 15 05:11:02 PM PDT 24
Finished Aug 15 05:11:03 PM PDT 24
Peak memory 208956 kb
Host smart-44cc0ba9-47ff-4183-9321-dc3869307c27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29124982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.29124982
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3007947448
Short name T668
Test name
Test status
Simulation time 628752463 ps
CPU time 11.92 seconds
Started Aug 15 05:10:55 PM PDT 24
Finished Aug 15 05:11:07 PM PDT 24
Peak memory 218332 kb
Host smart-e01b702e-633a-4b77-957d-38ac669916a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007947448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3007947448
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.769610598
Short name T8
Test name
Test status
Simulation time 437137436 ps
CPU time 11.35 seconds
Started Aug 15 05:11:01 PM PDT 24
Finished Aug 15 05:11:13 PM PDT 24
Peak memory 217772 kb
Host smart-8009fb72-dbab-4617-ac9d-29dfd2cdc1bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769610598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.769610598
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1650541917
Short name T476
Test name
Test status
Simulation time 24208690 ps
CPU time 1.79 seconds
Started Aug 15 05:10:53 PM PDT 24
Finished Aug 15 05:10:55 PM PDT 24
Peak memory 218336 kb
Host smart-886a6628-24bc-4cca-9fd3-df06731ef12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650541917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1650541917
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.400928605
Short name T762
Test name
Test status
Simulation time 1584581001 ps
CPU time 14.04 seconds
Started Aug 15 05:10:58 PM PDT 24
Finished Aug 15 05:11:13 PM PDT 24
Peak memory 219940 kb
Host smart-3eff1674-b184-4bbd-bccb-c12e718ab98f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400928605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.400928605
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1281924669
Short name T500
Test name
Test status
Simulation time 1533393139 ps
CPU time 15.99 seconds
Started Aug 15 05:11:00 PM PDT 24
Finished Aug 15 05:11:17 PM PDT 24
Peak memory 226060 kb
Host smart-d8bf703d-6702-446e-b91d-bd2d72bbd99a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281924669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1281924669
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3872264054
Short name T451
Test name
Test status
Simulation time 5804126662 ps
CPU time 14.84 seconds
Started Aug 15 05:11:01 PM PDT 24
Finished Aug 15 05:11:16 PM PDT 24
Peak memory 218328 kb
Host smart-16567057-7e28-4888-b3ac-4241bf83ca4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872264054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3872264054
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3806457371
Short name T767
Test name
Test status
Simulation time 1452910693 ps
CPU time 12.41 seconds
Started Aug 15 05:10:52 PM PDT 24
Finished Aug 15 05:11:05 PM PDT 24
Peak memory 218404 kb
Host smart-19ff7cec-a016-40fc-acdf-71f1358aef54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806457371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3806457371
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3649530582
Short name T460
Test name
Test status
Simulation time 29469163 ps
CPU time 1.9 seconds
Started Aug 15 05:10:55 PM PDT 24
Finished Aug 15 05:10:57 PM PDT 24
Peak memory 214104 kb
Host smart-434d0c59-c7d6-4291-8eda-b9209c902a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649530582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3649530582
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.4227979718
Short name T854
Test name
Test status
Simulation time 977429260 ps
CPU time 26.62 seconds
Started Aug 15 05:10:54 PM PDT 24
Finished Aug 15 05:11:21 PM PDT 24
Peak memory 250964 kb
Host smart-3f81e480-ae56-4b1b-bae0-d4a5cc94f247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227979718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.4227979718
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2070994530
Short name T627
Test name
Test status
Simulation time 263169595 ps
CPU time 7.31 seconds
Started Aug 15 05:10:53 PM PDT 24
Finished Aug 15 05:11:01 PM PDT 24
Peak memory 250944 kb
Host smart-87161919-19b3-472b-97df-a7e31a7fafdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070994530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2070994530
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1313141808
Short name T441
Test name
Test status
Simulation time 13299365104 ps
CPU time 300.76 seconds
Started Aug 15 05:11:00 PM PDT 24
Finished Aug 15 05:16:01 PM PDT 24
Peak memory 273292 kb
Host smart-68157b33-8b01-4b32-95a1-85874a6334c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313141808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1313141808
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.3820479051
Short name T174
Test name
Test status
Simulation time 11804602037 ps
CPU time 89.32 seconds
Started Aug 15 05:11:02 PM PDT 24
Finished Aug 15 05:12:32 PM PDT 24
Peak memory 267420 kb
Host smart-99a0ff62-bb45-4250-833c-8880853fc35e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3820479051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.3820479051
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2963065843
Short name T268
Test name
Test status
Simulation time 13152582 ps
CPU time 1.05 seconds
Started Aug 15 05:10:52 PM PDT 24
Finished Aug 15 05:10:53 PM PDT 24
Peak memory 211988 kb
Host smart-db5e63fc-c2db-423a-9c7b-cad975725193
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963065843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2963065843
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1003783429
Short name T463
Test name
Test status
Simulation time 19264356 ps
CPU time 0.98 seconds
Started Aug 15 05:11:03 PM PDT 24
Finished Aug 15 05:11:04 PM PDT 24
Peak memory 208956 kb
Host smart-2d2fd5a8-1bc0-495f-a8aa-38c8a5a2c77a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003783429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1003783429
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1500139988
Short name T370
Test name
Test status
Simulation time 206054394 ps
CPU time 8.05 seconds
Started Aug 15 05:11:01 PM PDT 24
Finished Aug 15 05:11:09 PM PDT 24
Peak memory 226120 kb
Host smart-adfa614d-fbd6-47ce-a783-6d30d4866092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500139988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1500139988
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3650180212
Short name T284
Test name
Test status
Simulation time 473532435 ps
CPU time 7.02 seconds
Started Aug 15 05:11:04 PM PDT 24
Finished Aug 15 05:11:11 PM PDT 24
Peak memory 217204 kb
Host smart-d35825d8-19a6-4f44-ae6f-4e19a26ef2ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650180212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3650180212
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3870821272
Short name T614
Test name
Test status
Simulation time 329450086 ps
CPU time 3.35 seconds
Started Aug 15 05:11:02 PM PDT 24
Finished Aug 15 05:11:05 PM PDT 24
Peak memory 218232 kb
Host smart-c4d67ddc-d6a9-4926-95f9-b71843bda8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870821272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3870821272
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1720836553
Short name T422
Test name
Test status
Simulation time 363722204 ps
CPU time 12.09 seconds
Started Aug 15 05:11:02 PM PDT 24
Finished Aug 15 05:11:14 PM PDT 24
Peak memory 219004 kb
Host smart-2668c024-6ff8-437b-a7bd-03f1db1f1dff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720836553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1720836553
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3078061263
Short name T227
Test name
Test status
Simulation time 523298029 ps
CPU time 9.9 seconds
Started Aug 15 05:11:00 PM PDT 24
Finished Aug 15 05:11:10 PM PDT 24
Peak memory 226036 kb
Host smart-ff57eafd-6727-4615-82c1-be93b64e5364
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078061263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3078061263
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1150775546
Short name T358
Test name
Test status
Simulation time 1271801846 ps
CPU time 12.27 seconds
Started Aug 15 05:11:01 PM PDT 24
Finished Aug 15 05:11:13 PM PDT 24
Peak memory 218236 kb
Host smart-14754527-2043-4a04-8566-4dfc7192b679
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150775546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1150775546
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1042880861
Short name T213
Test name
Test status
Simulation time 1704716922 ps
CPU time 10.06 seconds
Started Aug 15 05:11:04 PM PDT 24
Finished Aug 15 05:11:14 PM PDT 24
Peak memory 225012 kb
Host smart-69fba9eb-984c-4a4d-a0b4-16acf2ebe79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042880861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1042880861
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.4046027129
Short name T28
Test name
Test status
Simulation time 71630551 ps
CPU time 1.19 seconds
Started Aug 15 05:11:01 PM PDT 24
Finished Aug 15 05:11:02 PM PDT 24
Peak memory 217764 kb
Host smart-45f276d7-d2a5-4dfa-a05a-68e6138927e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046027129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.4046027129
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1066316296
Short name T398
Test name
Test status
Simulation time 147844181 ps
CPU time 18.7 seconds
Started Aug 15 05:11:01 PM PDT 24
Finished Aug 15 05:11:20 PM PDT 24
Peak memory 251072 kb
Host smart-191152b8-0f89-47b4-8fee-a1eab5743d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066316296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1066316296
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.838441352
Short name T749
Test name
Test status
Simulation time 246909186 ps
CPU time 8.09 seconds
Started Aug 15 05:11:01 PM PDT 24
Finished Aug 15 05:11:09 PM PDT 24
Peak memory 247532 kb
Host smart-af99e3cd-abda-4567-81ef-271825e01fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838441352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.838441352
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.580475125
Short name T364
Test name
Test status
Simulation time 12409696730 ps
CPU time 73.91 seconds
Started Aug 15 05:11:03 PM PDT 24
Finished Aug 15 05:12:17 PM PDT 24
Peak memory 268840 kb
Host smart-9e95057f-ea62-46ea-983e-a40d6dc4d21d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580475125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.580475125
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3353069732
Short name T32
Test name
Test status
Simulation time 112512595 ps
CPU time 0.82 seconds
Started Aug 15 05:11:01 PM PDT 24
Finished Aug 15 05:11:02 PM PDT 24
Peak memory 208864 kb
Host smart-14f77cf4-f6b3-44e7-8c8d-a1b3b55764c1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353069732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3353069732
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2236115228
Short name T180
Test name
Test status
Simulation time 52530757 ps
CPU time 1.07 seconds
Started Aug 15 05:11:14 PM PDT 24
Finished Aug 15 05:11:15 PM PDT 24
Peak memory 209012 kb
Host smart-4d1e7989-91d2-4410-a57c-49a3e2d2deba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236115228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2236115228
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.4070353528
Short name T244
Test name
Test status
Simulation time 361822880 ps
CPU time 8.02 seconds
Started Aug 15 05:10:59 PM PDT 24
Finished Aug 15 05:11:07 PM PDT 24
Peak memory 218308 kb
Host smart-9323ced0-352e-4f2d-8333-3c4eede1e749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070353528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.4070353528
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2449710708
Short name T557
Test name
Test status
Simulation time 809659139 ps
CPU time 5.96 seconds
Started Aug 15 05:11:00 PM PDT 24
Finished Aug 15 05:11:06 PM PDT 24
Peak memory 217760 kb
Host smart-c0d82356-881e-45ff-8aab-79b19179414a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449710708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2449710708
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.4178634156
Short name T388
Test name
Test status
Simulation time 256828585 ps
CPU time 2.47 seconds
Started Aug 15 05:11:02 PM PDT 24
Finished Aug 15 05:11:05 PM PDT 24
Peak memory 218324 kb
Host smart-3441de9e-c1ac-4579-853a-f3c1a5f082cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178634156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.4178634156
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3258492941
Short name T811
Test name
Test status
Simulation time 872142692 ps
CPU time 13.58 seconds
Started Aug 15 05:11:01 PM PDT 24
Finished Aug 15 05:11:15 PM PDT 24
Peak memory 226140 kb
Host smart-6e1ad195-de11-4620-bf17-5dc128ddcbbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258492941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3258492941
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3478512599
Short name T283
Test name
Test status
Simulation time 6174158049 ps
CPU time 19.11 seconds
Started Aug 15 05:11:07 PM PDT 24
Finished Aug 15 05:11:26 PM PDT 24
Peak memory 226132 kb
Host smart-83334e30-3d83-44dd-a706-eb1896ba8da6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478512599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3478512599
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3320040666
Short name T231
Test name
Test status
Simulation time 387203239 ps
CPU time 8.06 seconds
Started Aug 15 05:11:00 PM PDT 24
Finished Aug 15 05:11:08 PM PDT 24
Peak memory 226024 kb
Host smart-ca152f5f-c01c-4d1f-9f53-4f1554fea605
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320040666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3320040666
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1214359192
Short name T368
Test name
Test status
Simulation time 1191746872 ps
CPU time 7.38 seconds
Started Aug 15 05:11:04 PM PDT 24
Finished Aug 15 05:11:11 PM PDT 24
Peak memory 226124 kb
Host smart-07590ea2-9382-421f-861e-007eb198308f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214359192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1214359192
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.131776716
Short name T526
Test name
Test status
Simulation time 49334824 ps
CPU time 1.63 seconds
Started Aug 15 05:11:00 PM PDT 24
Finished Aug 15 05:11:02 PM PDT 24
Peak memory 214164 kb
Host smart-30b4d0c2-4918-44aa-ab59-132fcce74d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131776716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.131776716
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3373125642
Short name T80
Test name
Test status
Simulation time 587372110 ps
CPU time 37.67 seconds
Started Aug 15 05:11:00 PM PDT 24
Finished Aug 15 05:11:38 PM PDT 24
Peak memory 250768 kb
Host smart-e811c35f-ad44-49a9-8eeb-0341589086b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373125642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3373125642
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2563193872
Short name T167
Test name
Test status
Simulation time 110075636 ps
CPU time 7.25 seconds
Started Aug 15 05:11:01 PM PDT 24
Finished Aug 15 05:11:08 PM PDT 24
Peak memory 250424 kb
Host smart-e5effcda-6378-46d0-91f8-bc60ff1b9bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563193872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2563193872
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3931152409
Short name T859
Test name
Test status
Simulation time 13436444946 ps
CPU time 118.12 seconds
Started Aug 15 05:11:09 PM PDT 24
Finished Aug 15 05:13:07 PM PDT 24
Peak memory 283812 kb
Host smart-866f1b50-f412-4917-8738-f3d85f6cb4ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931152409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3931152409
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.823363585
Short name T147
Test name
Test status
Simulation time 9071631621 ps
CPU time 96.04 seconds
Started Aug 15 05:11:10 PM PDT 24
Finished Aug 15 05:12:46 PM PDT 24
Peak memory 256464 kb
Host smart-87f3e181-a649-4f0a-a766-8a32ddcbd464
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=823363585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.823363585
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2094434102
Short name T498
Test name
Test status
Simulation time 39178548 ps
CPU time 0.82 seconds
Started Aug 15 05:11:00 PM PDT 24
Finished Aug 15 05:11:00 PM PDT 24
Peak memory 208864 kb
Host smart-19565006-4acf-4360-b356-3a8eafad5a15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094434102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2094434102
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1304965182
Short name T607
Test name
Test status
Simulation time 26323752 ps
CPU time 1.23 seconds
Started Aug 15 05:11:08 PM PDT 24
Finished Aug 15 05:11:10 PM PDT 24
Peak memory 209108 kb
Host smart-a7399c6b-8c7b-42a2-942e-e3705319a7cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304965182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1304965182
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2823024299
Short name T450
Test name
Test status
Simulation time 4409154953 ps
CPU time 13.98 seconds
Started Aug 15 05:11:07 PM PDT 24
Finished Aug 15 05:11:21 PM PDT 24
Peak memory 226156 kb
Host smart-0ee36d1d-82cc-4ba3-9b74-682df79aac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823024299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2823024299
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.860114645
Short name T872
Test name
Test status
Simulation time 225281931 ps
CPU time 5.72 seconds
Started Aug 15 05:11:11 PM PDT 24
Finished Aug 15 05:11:17 PM PDT 24
Peak memory 217184 kb
Host smart-e7dc1b74-282e-4863-a362-578744120e1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860114645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.860114645
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1652736159
Short name T835
Test name
Test status
Simulation time 33645066 ps
CPU time 1.61 seconds
Started Aug 15 05:11:07 PM PDT 24
Finished Aug 15 05:11:09 PM PDT 24
Peak memory 218236 kb
Host smart-075efbe5-7c78-4d2f-875f-7364bdf34cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652736159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1652736159
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2689333331
Short name T337
Test name
Test status
Simulation time 382817620 ps
CPU time 12.15 seconds
Started Aug 15 05:11:07 PM PDT 24
Finished Aug 15 05:11:19 PM PDT 24
Peak memory 226156 kb
Host smart-de49e64c-21b7-4477-988e-4feb65c392f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689333331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2689333331
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.89939908
Short name T568
Test name
Test status
Simulation time 497960427 ps
CPU time 11.53 seconds
Started Aug 15 05:11:09 PM PDT 24
Finished Aug 15 05:11:21 PM PDT 24
Peak memory 226072 kb
Host smart-6a9d2587-8fb2-4092-907c-6e8008e5854a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89939908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_dig
est.89939908
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2552811183
Short name T579
Test name
Test status
Simulation time 427694554 ps
CPU time 11.8 seconds
Started Aug 15 05:11:09 PM PDT 24
Finished Aug 15 05:11:21 PM PDT 24
Peak memory 218308 kb
Host smart-e48a0a01-a449-4b2f-af79-0e224da72802
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552811183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2552811183
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2723442428
Short name T72
Test name
Test status
Simulation time 58438349 ps
CPU time 2.4 seconds
Started Aug 15 05:11:08 PM PDT 24
Finished Aug 15 05:11:11 PM PDT 24
Peak memory 217744 kb
Host smart-d7df5eb5-ad17-4316-ba02-eb645e35d9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723442428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2723442428
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2765231574
Short name T387
Test name
Test status
Simulation time 274963165 ps
CPU time 27.49 seconds
Started Aug 15 05:11:15 PM PDT 24
Finished Aug 15 05:11:42 PM PDT 24
Peak memory 250952 kb
Host smart-f3a748bf-480a-4c09-9134-946bcb15e323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765231574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2765231574
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2795836661
Short name T164
Test name
Test status
Simulation time 114591567 ps
CPU time 6.43 seconds
Started Aug 15 05:11:09 PM PDT 24
Finished Aug 15 05:11:16 PM PDT 24
Peak memory 250972 kb
Host smart-8e42df0b-22fb-4584-b650-d5a2a61c1dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795836661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2795836661
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3941586065
Short name T573
Test name
Test status
Simulation time 4843007398 ps
CPU time 99.13 seconds
Started Aug 15 05:11:08 PM PDT 24
Finished Aug 15 05:12:47 PM PDT 24
Peak memory 267544 kb
Host smart-294d23c3-e198-413d-8a6f-cb093cf73f80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3941586065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3941586065
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.293926332
Short name T305
Test name
Test status
Simulation time 13627395 ps
CPU time 0.97 seconds
Started Aug 15 05:11:06 PM PDT 24
Finished Aug 15 05:11:08 PM PDT 24
Peak memory 209056 kb
Host smart-8cd3ffbd-fda6-44a5-b62a-afd8490d95cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293926332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.293926332
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2092389682
Short name T688
Test name
Test status
Simulation time 19266763 ps
CPU time 1.18 seconds
Started Aug 15 05:11:08 PM PDT 24
Finished Aug 15 05:11:09 PM PDT 24
Peak memory 209032 kb
Host smart-d8edc51e-8370-4285-9d7b-54f7d01d2ea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092389682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2092389682
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.4144275875
Short name T495
Test name
Test status
Simulation time 1355370103 ps
CPU time 15.12 seconds
Started Aug 15 05:11:08 PM PDT 24
Finished Aug 15 05:11:23 PM PDT 24
Peak memory 218260 kb
Host smart-a31b3120-27eb-4fd2-bf62-1dda707ed42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144275875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.4144275875
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.331380313
Short name T774
Test name
Test status
Simulation time 188940893 ps
CPU time 3.34 seconds
Started Aug 15 05:11:08 PM PDT 24
Finished Aug 15 05:11:12 PM PDT 24
Peak memory 217672 kb
Host smart-6d1fade9-79a9-46d2-bd95-921fd888f2e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331380313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.331380313
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2045703630
Short name T763
Test name
Test status
Simulation time 162047975 ps
CPU time 2.95 seconds
Started Aug 15 05:11:09 PM PDT 24
Finished Aug 15 05:11:12 PM PDT 24
Peak memory 222576 kb
Host smart-a8428dc5-94d7-4f4d-a831-a3c18c6c61a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045703630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2045703630
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.510088042
Short name T564
Test name
Test status
Simulation time 317017998 ps
CPU time 13.51 seconds
Started Aug 15 05:11:07 PM PDT 24
Finished Aug 15 05:11:21 PM PDT 24
Peak memory 226124 kb
Host smart-e981241e-d05e-4389-8cae-23eeeb38be1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510088042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.510088042
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.331076792
Short name T728
Test name
Test status
Simulation time 1299549830 ps
CPU time 12.08 seconds
Started Aug 15 05:11:13 PM PDT 24
Finished Aug 15 05:11:25 PM PDT 24
Peak memory 226060 kb
Host smart-f7ef867c-6ee4-4550-8d85-339a0d617902
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331076792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.331076792
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2939662144
Short name T808
Test name
Test status
Simulation time 1443224011 ps
CPU time 9.61 seconds
Started Aug 15 05:11:11 PM PDT 24
Finished Aug 15 05:11:21 PM PDT 24
Peak memory 226032 kb
Host smart-eb979a71-f421-41a2-bfff-cc53c80401ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939662144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2939662144
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.246396367
Short name T821
Test name
Test status
Simulation time 1481081507 ps
CPU time 14.63 seconds
Started Aug 15 05:11:08 PM PDT 24
Finished Aug 15 05:11:23 PM PDT 24
Peak memory 218508 kb
Host smart-ad2f99d2-0ffb-4987-91a3-2f47ff957d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246396367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.246396367
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3732987758
Short name T427
Test name
Test status
Simulation time 83620999 ps
CPU time 1.49 seconds
Started Aug 15 05:11:10 PM PDT 24
Finished Aug 15 05:11:11 PM PDT 24
Peak memory 213864 kb
Host smart-3cbb5d50-a838-4628-acf9-c281bc82ea19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732987758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3732987758
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3029743631
Short name T871
Test name
Test status
Simulation time 2835773020 ps
CPU time 25.46 seconds
Started Aug 15 05:11:08 PM PDT 24
Finished Aug 15 05:11:34 PM PDT 24
Peak memory 251000 kb
Host smart-e4149b7c-878c-462a-88f0-565142608500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029743631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3029743631
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2031159658
Short name T722
Test name
Test status
Simulation time 115461721 ps
CPU time 6.18 seconds
Started Aug 15 05:11:08 PM PDT 24
Finished Aug 15 05:11:14 PM PDT 24
Peak memory 246972 kb
Host smart-11c9b645-8358-49fc-81d0-caaa867204f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031159658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2031159658
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3824280160
Short name T41
Test name
Test status
Simulation time 781419881 ps
CPU time 27.73 seconds
Started Aug 15 05:11:14 PM PDT 24
Finished Aug 15 05:11:42 PM PDT 24
Peak memory 218884 kb
Host smart-dbd7acaf-b031-4282-a638-9b0f69a0c657
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824280160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3824280160
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3459372963
Short name T599
Test name
Test status
Simulation time 28887092 ps
CPU time 0.81 seconds
Started Aug 15 05:11:11 PM PDT 24
Finished Aug 15 05:11:12 PM PDT 24
Peak memory 208832 kb
Host smart-49a5ecce-5da1-4787-b2a1-048357003f8a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459372963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3459372963
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.418458641
Short name T261
Test name
Test status
Simulation time 32685961 ps
CPU time 0.79 seconds
Started Aug 15 05:11:19 PM PDT 24
Finished Aug 15 05:11:19 PM PDT 24
Peak memory 209100 kb
Host smart-49651eff-18e0-4251-8c85-2456b25939a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418458641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.418458641
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1356400927
Short name T306
Test name
Test status
Simulation time 786095488 ps
CPU time 11.74 seconds
Started Aug 15 05:11:16 PM PDT 24
Finished Aug 15 05:11:28 PM PDT 24
Peak memory 218356 kb
Host smart-3e069c6f-0b5c-4386-a3b8-fcb30eabb373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356400927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1356400927
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.320576799
Short name T709
Test name
Test status
Simulation time 274431890 ps
CPU time 1.83 seconds
Started Aug 15 05:11:20 PM PDT 24
Finished Aug 15 05:11:22 PM PDT 24
Peak memory 217760 kb
Host smart-7cef89e2-bbec-4ea5-8341-602df3e409dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320576799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.320576799
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2773714766
Short name T417
Test name
Test status
Simulation time 89333905 ps
CPU time 4.35 seconds
Started Aug 15 05:11:17 PM PDT 24
Finished Aug 15 05:11:21 PM PDT 24
Peak memory 222552 kb
Host smart-72da4f90-1db6-48cd-84f9-715823424489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773714766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2773714766
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3070071166
Short name T570
Test name
Test status
Simulation time 209811302 ps
CPU time 10.92 seconds
Started Aug 15 05:11:16 PM PDT 24
Finished Aug 15 05:11:27 PM PDT 24
Peak memory 218360 kb
Host smart-e25c7a03-cc4b-45e2-9f5e-1d28082292d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070071166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3070071166
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1642579320
Short name T484
Test name
Test status
Simulation time 1544539447 ps
CPU time 15.15 seconds
Started Aug 15 05:11:17 PM PDT 24
Finished Aug 15 05:11:32 PM PDT 24
Peak memory 226052 kb
Host smart-1653ae5d-d7d1-4613-993c-2aa15a6e0e63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642579320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1642579320
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2099153017
Short name T347
Test name
Test status
Simulation time 1006816107 ps
CPU time 9.49 seconds
Started Aug 15 05:11:17 PM PDT 24
Finished Aug 15 05:11:27 PM PDT 24
Peak memory 218300 kb
Host smart-87a4f1f9-46cc-460f-adf2-738711c95c63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099153017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2099153017
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1501560202
Short name T47
Test name
Test status
Simulation time 1331015145 ps
CPU time 21.71 seconds
Started Aug 15 05:11:18 PM PDT 24
Finished Aug 15 05:11:40 PM PDT 24
Peak memory 218392 kb
Host smart-69d56642-db4d-426f-a20b-280152a342b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501560202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1501560202
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1711602925
Short name T565
Test name
Test status
Simulation time 163152278 ps
CPU time 1.32 seconds
Started Aug 15 05:11:11 PM PDT 24
Finished Aug 15 05:11:13 PM PDT 24
Peak memory 213952 kb
Host smart-88f211cb-8151-432d-9506-31972015a332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711602925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1711602925
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1495304523
Short name T602
Test name
Test status
Simulation time 783405808 ps
CPU time 29.19 seconds
Started Aug 15 05:11:12 PM PDT 24
Finished Aug 15 05:11:41 PM PDT 24
Peak memory 251060 kb
Host smart-fe18289e-2d27-4c31-a288-fce88ec3461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495304523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1495304523
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.844667619
Short name T407
Test name
Test status
Simulation time 560855856 ps
CPU time 7.21 seconds
Started Aug 15 05:11:15 PM PDT 24
Finished Aug 15 05:11:23 PM PDT 24
Peak memory 250808 kb
Host smart-56d21dd4-2511-480f-9903-75e1fe314413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844667619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.844667619
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1523393858
Short name T836
Test name
Test status
Simulation time 1107569320 ps
CPU time 75.85 seconds
Started Aug 15 05:11:18 PM PDT 24
Finished Aug 15 05:12:34 PM PDT 24
Peak memory 250848 kb
Host smart-7f397688-9985-4769-bbf9-548978b4cd92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523393858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1523393858
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1479784771
Short name T636
Test name
Test status
Simulation time 19267053 ps
CPU time 0.94 seconds
Started Aug 15 05:11:07 PM PDT 24
Finished Aug 15 05:11:08 PM PDT 24
Peak memory 212004 kb
Host smart-d2e48eed-64d5-421a-adb2-cc9a1e85a6e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479784771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1479784771
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.241719681
Short name T533
Test name
Test status
Simulation time 59693787 ps
CPU time 0.87 seconds
Started Aug 15 05:11:15 PM PDT 24
Finished Aug 15 05:11:16 PM PDT 24
Peak memory 208916 kb
Host smart-4e5b6529-cd4e-4a37-9e07-7ecebdec1959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241719681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.241719681
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2382302768
Short name T462
Test name
Test status
Simulation time 947747858 ps
CPU time 19.18 seconds
Started Aug 15 05:11:15 PM PDT 24
Finished Aug 15 05:11:34 PM PDT 24
Peak memory 218348 kb
Host smart-fc0d22e7-6162-4352-9ed3-0c5150b15a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382302768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2382302768
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1804825322
Short name T470
Test name
Test status
Simulation time 377123460 ps
CPU time 5.22 seconds
Started Aug 15 05:11:19 PM PDT 24
Finished Aug 15 05:11:25 PM PDT 24
Peak memory 217528 kb
Host smart-d449197d-87cf-4ca9-86d2-013874578937
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804825322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1804825322
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1092234836
Short name T287
Test name
Test status
Simulation time 47529329 ps
CPU time 2.23 seconds
Started Aug 15 05:11:14 PM PDT 24
Finished Aug 15 05:11:16 PM PDT 24
Peak memory 216992 kb
Host smart-307c9fa6-4b3a-4c51-b780-4b7e1f48ba93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092234836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1092234836
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.290833436
Short name T220
Test name
Test status
Simulation time 1506760318 ps
CPU time 17.65 seconds
Started Aug 15 05:11:15 PM PDT 24
Finished Aug 15 05:11:33 PM PDT 24
Peak memory 226020 kb
Host smart-f65174d4-1e34-409e-a6f3-133d339c392f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290833436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.290833436
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1985098653
Short name T182
Test name
Test status
Simulation time 308923899 ps
CPU time 15.22 seconds
Started Aug 15 05:11:14 PM PDT 24
Finished Aug 15 05:11:29 PM PDT 24
Peak memory 226076 kb
Host smart-6b358778-bd17-4883-989d-6170f9fb53ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985098653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1985098653
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.4062577975
Short name T687
Test name
Test status
Simulation time 275873146 ps
CPU time 9.34 seconds
Started Aug 15 05:11:19 PM PDT 24
Finished Aug 15 05:11:29 PM PDT 24
Peak memory 226072 kb
Host smart-8a3559f8-335c-4626-8e73-6a724fdc6750
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062577975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
4062577975
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.4191107603
Short name T440
Test name
Test status
Simulation time 552800499 ps
CPU time 11.18 seconds
Started Aug 15 05:11:15 PM PDT 24
Finished Aug 15 05:11:27 PM PDT 24
Peak memory 226144 kb
Host smart-e7a7eb1e-d674-4e93-8154-b8a8076b9c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191107603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.4191107603
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3970912252
Short name T804
Test name
Test status
Simulation time 174707201 ps
CPU time 2.48 seconds
Started Aug 15 05:11:16 PM PDT 24
Finished Aug 15 05:11:18 PM PDT 24
Peak memory 217780 kb
Host smart-a7749d13-884e-43f4-b6c3-dc13ca799c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970912252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3970912252
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.764391598
Short name T834
Test name
Test status
Simulation time 547384664 ps
CPU time 31.3 seconds
Started Aug 15 05:11:28 PM PDT 24
Finished Aug 15 05:11:59 PM PDT 24
Peak memory 251012 kb
Host smart-4a391eb2-f559-4930-b13a-c82e8b31ae52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764391598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.764391598
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.662552427
Short name T844
Test name
Test status
Simulation time 214253434 ps
CPU time 6.92 seconds
Started Aug 15 05:11:16 PM PDT 24
Finished Aug 15 05:11:23 PM PDT 24
Peak memory 247096 kb
Host smart-6b75bcb1-dbb2-411f-b363-6a48167fb18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662552427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.662552427
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3635129889
Short name T787
Test name
Test status
Simulation time 6073777158 ps
CPU time 79.02 seconds
Started Aug 15 05:11:18 PM PDT 24
Finished Aug 15 05:12:37 PM PDT 24
Peak memory 274808 kb
Host smart-1e5ccde7-ea59-44f2-8b47-d13e4267f99f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635129889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3635129889
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.4160392360
Short name T88
Test name
Test status
Simulation time 11561228251 ps
CPU time 163.61 seconds
Started Aug 15 05:11:16 PM PDT 24
Finished Aug 15 05:14:00 PM PDT 24
Peak memory 267500 kb
Host smart-ed394cda-7a81-44df-85b1-ef6b09098871
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4160392360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.4160392360
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2641406343
Short name T814
Test name
Test status
Simulation time 14209552 ps
CPU time 1 seconds
Started Aug 15 05:11:17 PM PDT 24
Finished Aug 15 05:11:18 PM PDT 24
Peak memory 209092 kb
Host smart-ad5bd307-c829-4f6a-8f46-b1366840873b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641406343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2641406343
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1143768926
Short name T798
Test name
Test status
Simulation time 76588788 ps
CPU time 0.93 seconds
Started Aug 15 05:07:56 PM PDT 24
Finished Aug 15 05:07:57 PM PDT 24
Peak memory 208984 kb
Host smart-dbc054ca-db88-4532-a230-4be50d93807d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143768926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1143768926
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2355165481
Short name T299
Test name
Test status
Simulation time 30260923 ps
CPU time 1.01 seconds
Started Aug 15 05:07:55 PM PDT 24
Finished Aug 15 05:07:56 PM PDT 24
Peak memory 208772 kb
Host smart-b2f1230c-7a67-44a5-ad91-f48ead701782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355165481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2355165481
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.694548650
Short name T433
Test name
Test status
Simulation time 375576675 ps
CPU time 16.44 seconds
Started Aug 15 05:07:55 PM PDT 24
Finished Aug 15 05:08:11 PM PDT 24
Peak memory 218340 kb
Host smart-78831a33-7c1c-4105-aa05-7357a7146a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694548650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.694548650
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1899822306
Short name T22
Test name
Test status
Simulation time 293810078 ps
CPU time 2.98 seconds
Started Aug 15 05:07:57 PM PDT 24
Finished Aug 15 05:08:00 PM PDT 24
Peak memory 217228 kb
Host smart-062c1eda-23d0-46b1-8059-3afe86193759
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899822306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1899822306
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3957234740
Short name T168
Test name
Test status
Simulation time 16803067521 ps
CPU time 54.71 seconds
Started Aug 15 05:07:57 PM PDT 24
Finished Aug 15 05:08:52 PM PDT 24
Peak memory 219744 kb
Host smart-568fa992-5823-4087-8513-9779c6c5d76a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957234740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3957234740
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1181982684
Short name T746
Test name
Test status
Simulation time 8032776998 ps
CPU time 14.92 seconds
Started Aug 15 05:07:55 PM PDT 24
Finished Aug 15 05:08:10 PM PDT 24
Peak memory 217856 kb
Host smart-94d00c1a-a253-450b-8305-dae817300bd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181982684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
181982684
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1874566903
Short name T263
Test name
Test status
Simulation time 2169871096 ps
CPU time 12.35 seconds
Started Aug 15 05:07:59 PM PDT 24
Finished Aug 15 05:08:12 PM PDT 24
Peak memory 223528 kb
Host smart-3e2532b7-336f-48f8-9e98-b0330a6f9dfb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874566903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1874566903
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1211020228
Short name T237
Test name
Test status
Simulation time 598268571 ps
CPU time 17.12 seconds
Started Aug 15 05:07:57 PM PDT 24
Finished Aug 15 05:08:15 PM PDT 24
Peak memory 217688 kb
Host smart-f9287f8f-9ee4-4f70-90ea-a55be27efa76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211020228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1211020228
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.4186071164
Short name T513
Test name
Test status
Simulation time 271882019 ps
CPU time 7.92 seconds
Started Aug 15 05:07:55 PM PDT 24
Finished Aug 15 05:08:03 PM PDT 24
Peak memory 217692 kb
Host smart-189818ea-07a7-4e33-a391-96f8a81c6903
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186071164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
4186071164
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1979056027
Short name T285
Test name
Test status
Simulation time 13843951330 ps
CPU time 65.94 seconds
Started Aug 15 05:07:56 PM PDT 24
Finished Aug 15 05:09:02 PM PDT 24
Peak memory 283700 kb
Host smart-27d5847b-7489-4e2d-adde-211e7040f466
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979056027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1979056027
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2585423210
Short name T626
Test name
Test status
Simulation time 521167879 ps
CPU time 12.88 seconds
Started Aug 15 05:07:55 PM PDT 24
Finished Aug 15 05:08:08 PM PDT 24
Peak memory 246028 kb
Host smart-65c487ee-fe9e-4840-81a2-37a5388bb629
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585423210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2585423210
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3244567085
Short name T13
Test name
Test status
Simulation time 82098585 ps
CPU time 3.34 seconds
Started Aug 15 05:07:55 PM PDT 24
Finished Aug 15 05:07:59 PM PDT 24
Peak memory 222436 kb
Host smart-dfb8bf35-e354-4917-a90a-715d4cfc5845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244567085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3244567085
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.328539000
Short name T14
Test name
Test status
Simulation time 209201200 ps
CPU time 10.99 seconds
Started Aug 15 05:07:54 PM PDT 24
Finished Aug 15 05:08:05 PM PDT 24
Peak memory 217828 kb
Host smart-414b35ba-3a91-4cf6-a52e-1b0e61a286f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328539000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.328539000
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.798024114
Short name T153
Test name
Test status
Simulation time 1043989401 ps
CPU time 11.36 seconds
Started Aug 15 05:07:59 PM PDT 24
Finished Aug 15 05:08:10 PM PDT 24
Peak memory 220064 kb
Host smart-9c7778ea-c84a-4701-8df3-a565dc310e6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798024114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.798024114
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.839999550
Short name T807
Test name
Test status
Simulation time 686416396 ps
CPU time 12.04 seconds
Started Aug 15 05:07:54 PM PDT 24
Finished Aug 15 05:08:06 PM PDT 24
Peak memory 224712 kb
Host smart-1515add3-36df-4699-a7e1-1b7fb989a400
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839999550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.839999550
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.778785014
Short name T232
Test name
Test status
Simulation time 180476654 ps
CPU time 7.91 seconds
Started Aug 15 05:07:55 PM PDT 24
Finished Aug 15 05:08:03 PM PDT 24
Peak memory 226040 kb
Host smart-19728be4-b887-44cd-9adb-142f353fda6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778785014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.778785014
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2864430186
Short name T327
Test name
Test status
Simulation time 4777439517 ps
CPU time 11.98 seconds
Started Aug 15 05:07:58 PM PDT 24
Finished Aug 15 05:08:10 PM PDT 24
Peak memory 218464 kb
Host smart-374fa662-3782-484f-b2f5-ab2f2ba10277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864430186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2864430186
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.109554111
Short name T493
Test name
Test status
Simulation time 32837748 ps
CPU time 2.4 seconds
Started Aug 15 05:07:54 PM PDT 24
Finished Aug 15 05:07:57 PM PDT 24
Peak memory 214252 kb
Host smart-d3f9f4f8-10b1-49ff-b561-cd09e8113372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109554111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.109554111
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.98458275
Short name T383
Test name
Test status
Simulation time 5567135305 ps
CPU time 40.57 seconds
Started Aug 15 05:07:57 PM PDT 24
Finished Aug 15 05:08:38 PM PDT 24
Peak memory 251032 kb
Host smart-a3e4b2ac-515e-453b-a83b-4c06e8238b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98458275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.98458275
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.373677370
Short name T788
Test name
Test status
Simulation time 89899811 ps
CPU time 4.37 seconds
Started Aug 15 05:07:52 PM PDT 24
Finished Aug 15 05:07:57 PM PDT 24
Peak memory 218356 kb
Host smart-3b2d07ab-daee-4b37-a6b7-8e67450eb1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373677370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.373677370
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1789414181
Short name T395
Test name
Test status
Simulation time 16756207944 ps
CPU time 559.15 seconds
Started Aug 15 05:07:55 PM PDT 24
Finished Aug 15 05:17:14 PM PDT 24
Peak memory 283772 kb
Host smart-1bdce493-1fe4-42a0-a339-cf80d0fdc8ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789414181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1789414181
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.331059070
Short name T527
Test name
Test status
Simulation time 2425813317 ps
CPU time 62.51 seconds
Started Aug 15 05:07:58 PM PDT 24
Finished Aug 15 05:09:00 PM PDT 24
Peak memory 275088 kb
Host smart-6c5bd119-4640-4821-a249-b1f324791ebc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=331059070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.331059070
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1480513781
Short name T831
Test name
Test status
Simulation time 33763704 ps
CPU time 0.91 seconds
Started Aug 15 05:07:54 PM PDT 24
Finished Aug 15 05:07:55 PM PDT 24
Peak memory 217896 kb
Host smart-a2f3d763-3a12-4a82-be35-96605a88c624
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480513781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1480513781
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1592504851
Short name T434
Test name
Test status
Simulation time 27784564 ps
CPU time 1.05 seconds
Started Aug 15 05:08:03 PM PDT 24
Finished Aug 15 05:08:04 PM PDT 24
Peak memory 209068 kb
Host smart-04e6d1cf-30d8-4bad-ae20-1bdaad15bfb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592504851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1592504851
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3690470073
Short name T101
Test name
Test status
Simulation time 11211716 ps
CPU time 0.94 seconds
Started Aug 15 05:07:56 PM PDT 24
Finished Aug 15 05:07:57 PM PDT 24
Peak memory 208864 kb
Host smart-8e90aa8c-b7cb-49a5-9023-fe04bed64b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690470073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3690470073
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3603656287
Short name T679
Test name
Test status
Simulation time 412334186 ps
CPU time 16.29 seconds
Started Aug 15 05:07:56 PM PDT 24
Finished Aug 15 05:08:13 PM PDT 24
Peak memory 218324 kb
Host smart-9ac51aef-6275-4909-87af-35a2ce83b729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603656287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3603656287
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1596587316
Short name T482
Test name
Test status
Simulation time 1143584437 ps
CPU time 14.39 seconds
Started Aug 15 05:08:03 PM PDT 24
Finished Aug 15 05:08:18 PM PDT 24
Peak memory 217500 kb
Host smart-b8bc364e-b153-414b-885f-9260dff2019d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596587316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1596587316
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1876998356
Short name T412
Test name
Test status
Simulation time 2058400447 ps
CPU time 34.96 seconds
Started Aug 15 05:07:59 PM PDT 24
Finished Aug 15 05:08:34 PM PDT 24
Peak memory 218140 kb
Host smart-69b34929-a49f-4b1c-8427-386576f9faca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876998356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1876998356
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1990500398
Short name T741
Test name
Test status
Simulation time 691659717 ps
CPU time 5.29 seconds
Started Aug 15 05:08:02 PM PDT 24
Finished Aug 15 05:08:07 PM PDT 24
Peak memory 217692 kb
Host smart-1a572c70-77d1-4144-bb2a-b37f2e4006f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990500398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
990500398
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1749187432
Short name T816
Test name
Test status
Simulation time 4411383622 ps
CPU time 26.55 seconds
Started Aug 15 05:07:59 PM PDT 24
Finished Aug 15 05:08:26 PM PDT 24
Peak memory 226028 kb
Host smart-a03108a6-7786-4aa4-8b39-4743a708f282
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749187432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1749187432
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1372660432
Short name T224
Test name
Test status
Simulation time 13446864000 ps
CPU time 13.16 seconds
Started Aug 15 05:08:03 PM PDT 24
Finished Aug 15 05:08:16 PM PDT 24
Peak memory 217700 kb
Host smart-e688154b-f0bd-49c9-8b9d-1fc8fa67dff9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372660432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1372660432
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3996284025
Short name T223
Test name
Test status
Simulation time 102741889 ps
CPU time 2.37 seconds
Started Aug 15 05:07:55 PM PDT 24
Finished Aug 15 05:07:58 PM PDT 24
Peak memory 217684 kb
Host smart-288d3a9c-07b1-4162-b2f3-e9d5d9ef59fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996284025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3996284025
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2393537086
Short name T343
Test name
Test status
Simulation time 5628482964 ps
CPU time 68.37 seconds
Started Aug 15 05:07:54 PM PDT 24
Finished Aug 15 05:09:03 PM PDT 24
Peak memory 283684 kb
Host smart-696aba22-a190-42c2-b225-1bf5d1f3f896
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393537086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2393537086
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2708064880
Short name T556
Test name
Test status
Simulation time 5232261964 ps
CPU time 15.97 seconds
Started Aug 15 05:07:59 PM PDT 24
Finished Aug 15 05:08:15 PM PDT 24
Peak memory 245264 kb
Host smart-3d75cfda-237b-44c3-b609-46472e2c31e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708064880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2708064880
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.229653089
Short name T781
Test name
Test status
Simulation time 1219850808 ps
CPU time 4.44 seconds
Started Aug 15 05:07:59 PM PDT 24
Finished Aug 15 05:08:04 PM PDT 24
Peak memory 218304 kb
Host smart-f225e4ed-cfba-4347-a80f-4dc5a687ec72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229653089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.229653089
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.4263592662
Short name T245
Test name
Test status
Simulation time 1099728997 ps
CPU time 15.23 seconds
Started Aug 15 05:07:55 PM PDT 24
Finished Aug 15 05:08:10 PM PDT 24
Peak memory 214180 kb
Host smart-7c6ca8ba-b450-4997-a9c5-e104cc3cb28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263592662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.4263592662
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1536971918
Short name T529
Test name
Test status
Simulation time 989660932 ps
CPU time 12.14 seconds
Started Aug 15 05:08:10 PM PDT 24
Finished Aug 15 05:08:22 PM PDT 24
Peak memory 226124 kb
Host smart-8ba4c701-53ce-46dd-9230-ac82d449f29e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536971918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1536971918
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3367282571
Short name T520
Test name
Test status
Simulation time 2957457672 ps
CPU time 8.89 seconds
Started Aug 15 05:08:10 PM PDT 24
Finished Aug 15 05:08:19 PM PDT 24
Peak memory 226112 kb
Host smart-40c24903-1300-4926-87a2-4dcd8a1a6b66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367282571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3367282571
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.4035293574
Short name T408
Test name
Test status
Simulation time 1178595245 ps
CPU time 8.18 seconds
Started Aug 15 05:08:02 PM PDT 24
Finished Aug 15 05:08:10 PM PDT 24
Peak memory 218484 kb
Host smart-7cf23048-402c-407d-87b7-69a69654e12c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035293574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.4
035293574
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1175335760
Short name T847
Test name
Test status
Simulation time 1195338824 ps
CPU time 10.8 seconds
Started Aug 15 05:07:58 PM PDT 24
Finished Aug 15 05:08:09 PM PDT 24
Peak memory 225416 kb
Host smart-9581add2-873c-483b-ae92-00d77039d55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175335760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1175335760
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1190387040
Short name T430
Test name
Test status
Simulation time 66131207 ps
CPU time 4.29 seconds
Started Aug 15 05:07:57 PM PDT 24
Finished Aug 15 05:08:02 PM PDT 24
Peak memory 217704 kb
Host smart-b1b17c0c-a42a-4ffa-99ac-ff1e86c7b65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190387040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1190387040
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3585674379
Short name T598
Test name
Test status
Simulation time 2660918090 ps
CPU time 24.94 seconds
Started Aug 15 05:07:57 PM PDT 24
Finished Aug 15 05:08:22 PM PDT 24
Peak memory 250964 kb
Host smart-00b76761-e07c-4413-b43a-c17fee9ed290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585674379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3585674379
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3733045659
Short name T152
Test name
Test status
Simulation time 101440610 ps
CPU time 9.47 seconds
Started Aug 15 05:07:58 PM PDT 24
Finished Aug 15 05:08:07 PM PDT 24
Peak memory 250912 kb
Host smart-27c460b5-a64e-4cb9-825d-b4e83ad79419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733045659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3733045659
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2861329104
Short name T515
Test name
Test status
Simulation time 14015867437 ps
CPU time 128.59 seconds
Started Aug 15 05:08:10 PM PDT 24
Finished Aug 15 05:10:18 PM PDT 24
Peak memory 281068 kb
Host smart-2a9d08d2-0087-495b-8d81-fb9801295555
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861329104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2861329104
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2929040712
Short name T272
Test name
Test status
Simulation time 25158764 ps
CPU time 1.09 seconds
Started Aug 15 05:07:57 PM PDT 24
Finished Aug 15 05:07:58 PM PDT 24
Peak memory 212148 kb
Host smart-9b1a2690-19e4-4c0c-9a20-cced2c46f338
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929040712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2929040712
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1290043699
Short name T838
Test name
Test status
Simulation time 13780977 ps
CPU time 0.87 seconds
Started Aug 15 05:08:11 PM PDT 24
Finished Aug 15 05:08:12 PM PDT 24
Peak memory 209000 kb
Host smart-82d5159b-7c2d-4d2a-abdb-7ed2d9660d92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290043699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1290043699
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.225512051
Short name T69
Test name
Test status
Simulation time 151329982 ps
CPU time 0.8 seconds
Started Aug 15 05:08:11 PM PDT 24
Finished Aug 15 05:08:12 PM PDT 24
Peak memory 208664 kb
Host smart-53771f5d-48c2-45e6-b1d9-84cb4d9fa943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225512051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.225512051
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3283270793
Short name T696
Test name
Test status
Simulation time 298412297 ps
CPU time 12.35 seconds
Started Aug 15 05:08:13 PM PDT 24
Finished Aug 15 05:08:26 PM PDT 24
Peak memory 226120 kb
Host smart-572666ee-5d13-410b-89dc-7cdc48982a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283270793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3283270793
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.758099233
Short name T9
Test name
Test status
Simulation time 52905841 ps
CPU time 1.53 seconds
Started Aug 15 05:08:13 PM PDT 24
Finished Aug 15 05:08:15 PM PDT 24
Peak memory 217320 kb
Host smart-1c5eb413-5f84-4c6d-8d24-2d15f490a81b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758099233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.758099233
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2115193343
Short name T654
Test name
Test status
Simulation time 8198480903 ps
CPU time 51.69 seconds
Started Aug 15 05:08:12 PM PDT 24
Finished Aug 15 05:09:04 PM PDT 24
Peak memory 218980 kb
Host smart-3b5b779f-e193-4a32-bd1d-e846dc86c2e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115193343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2115193343
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.455202403
Short name T3
Test name
Test status
Simulation time 370690654 ps
CPU time 4.52 seconds
Started Aug 15 05:08:14 PM PDT 24
Finished Aug 15 05:08:18 PM PDT 24
Peak memory 217748 kb
Host smart-99e94baa-2289-49cf-a5e3-fe7cb70d657d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455202403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.455202403
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2792166752
Short name T851
Test name
Test status
Simulation time 320248255 ps
CPU time 4.8 seconds
Started Aug 15 05:08:14 PM PDT 24
Finished Aug 15 05:08:19 PM PDT 24
Peak memory 218288 kb
Host smart-9613f4bc-07a2-4718-9213-3c2355a20659
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792166752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2792166752
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1047587045
Short name T551
Test name
Test status
Simulation time 661043144 ps
CPU time 15.02 seconds
Started Aug 15 05:08:11 PM PDT 24
Finished Aug 15 05:08:26 PM PDT 24
Peak memory 217680 kb
Host smart-85619d0c-86ac-440c-8ed3-fb1fb7572765
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047587045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1047587045
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2154511105
Short name T64
Test name
Test status
Simulation time 483831110 ps
CPU time 4.09 seconds
Started Aug 15 05:08:13 PM PDT 24
Finished Aug 15 05:08:17 PM PDT 24
Peak memory 217676 kb
Host smart-35b892cf-5710-47b9-a53f-28d5734cd267
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154511105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2154511105
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2718667617
Short name T681
Test name
Test status
Simulation time 10940778260 ps
CPU time 59.06 seconds
Started Aug 15 05:08:11 PM PDT 24
Finished Aug 15 05:09:11 PM PDT 24
Peak memory 281728 kb
Host smart-7cb977ce-d3e6-43cc-aaf5-4c0c7085b126
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718667617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2718667617
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2222215404
Short name T390
Test name
Test status
Simulation time 319654381 ps
CPU time 11.1 seconds
Started Aug 15 05:08:14 PM PDT 24
Finished Aug 15 05:08:25 PM PDT 24
Peak memory 221928 kb
Host smart-f3b9181c-e5c3-4e18-8c7a-dffa7248ad30
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222215404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2222215404
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1905896629
Short name T448
Test name
Test status
Simulation time 18092773 ps
CPU time 1.52 seconds
Started Aug 15 05:08:04 PM PDT 24
Finished Aug 15 05:08:06 PM PDT 24
Peak memory 221864 kb
Host smart-957f34d4-eaf0-4d9b-9f5b-49a159349099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905896629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1905896629
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3190324677
Short name T657
Test name
Test status
Simulation time 1237595743 ps
CPU time 20.72 seconds
Started Aug 15 05:08:11 PM PDT 24
Finished Aug 15 05:08:32 PM PDT 24
Peak memory 217728 kb
Host smart-d9a521a3-f2ab-491f-a99e-5f8ec6a0c506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190324677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3190324677
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2245449886
Short name T424
Test name
Test status
Simulation time 1084002027 ps
CPU time 13.88 seconds
Started Aug 15 05:08:13 PM PDT 24
Finished Aug 15 05:08:27 PM PDT 24
Peak memory 218476 kb
Host smart-9f0c5937-246e-45e2-9ab6-d42fbfecac80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245449886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2245449886
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.257689193
Short name T465
Test name
Test status
Simulation time 676387038 ps
CPU time 14.99 seconds
Started Aug 15 05:08:12 PM PDT 24
Finished Aug 15 05:08:27 PM PDT 24
Peak memory 226056 kb
Host smart-8aad4b7e-c6aa-48be-b53d-aa47a5933d5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257689193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.257689193
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2341914044
Short name T59
Test name
Test status
Simulation time 1120223922 ps
CPU time 7.95 seconds
Started Aug 15 05:08:11 PM PDT 24
Finished Aug 15 05:08:19 PM PDT 24
Peak memory 226080 kb
Host smart-c6da43e1-e05d-4b3f-93ff-68ee0e23017c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341914044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
341914044
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.538535456
Short name T669
Test name
Test status
Simulation time 295915968 ps
CPU time 11.36 seconds
Started Aug 15 05:08:11 PM PDT 24
Finished Aug 15 05:08:22 PM PDT 24
Peak memory 218428 kb
Host smart-a8bb2e95-2ea4-4b01-8e27-5c4ade13c789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538535456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.538535456
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1878200729
Short name T692
Test name
Test status
Simulation time 86935880 ps
CPU time 1.34 seconds
Started Aug 15 05:08:04 PM PDT 24
Finished Aug 15 05:08:06 PM PDT 24
Peak memory 213788 kb
Host smart-3c51be93-3c56-4d44-9de2-c9d5d0dd602b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878200729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1878200729
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2634321133
Short name T309
Test name
Test status
Simulation time 1631719122 ps
CPU time 24.13 seconds
Started Aug 15 05:08:02 PM PDT 24
Finished Aug 15 05:08:27 PM PDT 24
Peak memory 250948 kb
Host smart-c921d4cb-0213-4d05-8e09-64894907716e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634321133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2634321133
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3233998094
Short name T274
Test name
Test status
Simulation time 121995228 ps
CPU time 7.15 seconds
Started Aug 15 05:08:03 PM PDT 24
Finished Aug 15 05:08:10 PM PDT 24
Peak memory 242544 kb
Host smart-fe5f595c-f579-4014-ac52-da265f42ef30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233998094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3233998094
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.4244080903
Short name T288
Test name
Test status
Simulation time 5192214740 ps
CPU time 43.08 seconds
Started Aug 15 05:08:12 PM PDT 24
Finished Aug 15 05:08:55 PM PDT 24
Peak memory 250936 kb
Host smart-9ab87482-49f9-443f-91a0-141bcdbc3fa8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244080903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.4244080903
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1399403507
Short name T144
Test name
Test status
Simulation time 67459980784 ps
CPU time 99.14 seconds
Started Aug 15 05:08:12 PM PDT 24
Finished Aug 15 05:09:51 PM PDT 24
Peak memory 267496 kb
Host smart-617d29b7-44d4-45fd-8cd0-26239c9e509c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1399403507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.1399403507
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2516965549
Short name T718
Test name
Test status
Simulation time 21900509 ps
CPU time 1.01 seconds
Started Aug 15 05:08:10 PM PDT 24
Finished Aug 15 05:08:11 PM PDT 24
Peak memory 212044 kb
Host smart-15a8be99-7ceb-4aef-86dc-71c4f9fb9cbe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516965549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2516965549
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1954255200
Short name T780
Test name
Test status
Simulation time 26162078 ps
CPU time 0.87 seconds
Started Aug 15 05:08:21 PM PDT 24
Finished Aug 15 05:08:22 PM PDT 24
Peak memory 208844 kb
Host smart-bebbfbb0-404b-4d6d-b442-712d9cd07c86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954255200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1954255200
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.759468066
Short name T279
Test name
Test status
Simulation time 1066250382 ps
CPU time 12.11 seconds
Started Aug 15 05:08:20 PM PDT 24
Finished Aug 15 05:08:32 PM PDT 24
Peak memory 218328 kb
Host smart-3d25816a-8b1f-46da-8e7d-b7787e4683ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759468066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.759468066
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.4009081464
Short name T830
Test name
Test status
Simulation time 298966784 ps
CPU time 7.9 seconds
Started Aug 15 05:08:19 PM PDT 24
Finished Aug 15 05:08:27 PM PDT 24
Peak memory 217756 kb
Host smart-624f3408-16ab-4921-966f-9cc3af591295
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009081464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.4009081464
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2402858314
Short name T267
Test name
Test status
Simulation time 976768730 ps
CPU time 33.03 seconds
Started Aug 15 05:08:21 PM PDT 24
Finished Aug 15 05:08:54 PM PDT 24
Peak memory 218824 kb
Host smart-a19ca2cd-c8e4-4f11-a6e4-6e59965af39b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402858314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2402858314
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2004601489
Short name T870
Test name
Test status
Simulation time 2921930418 ps
CPU time 16.83 seconds
Started Aug 15 05:08:21 PM PDT 24
Finished Aug 15 05:08:38 PM PDT 24
Peak memory 217888 kb
Host smart-62fe504f-1007-428f-8f53-7d2af29d66c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004601489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
004601489
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2540182070
Short name T502
Test name
Test status
Simulation time 815169957 ps
CPU time 3.45 seconds
Started Aug 15 05:08:19 PM PDT 24
Finished Aug 15 05:08:23 PM PDT 24
Peak memory 218184 kb
Host smart-c86871a1-7e1a-49f1-91c1-c67272a65b64
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540182070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2540182070
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1895941336
Short name T653
Test name
Test status
Simulation time 1114750082 ps
CPU time 17.93 seconds
Started Aug 15 05:08:22 PM PDT 24
Finished Aug 15 05:08:40 PM PDT 24
Peak memory 217604 kb
Host smart-e9875d74-d377-42a6-9177-19afa50668ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895941336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1895941336
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2627038642
Short name T577
Test name
Test status
Simulation time 1865459633 ps
CPU time 6.99 seconds
Started Aug 15 05:08:18 PM PDT 24
Finished Aug 15 05:08:25 PM PDT 24
Peak memory 217708 kb
Host smart-d3efbf8d-39cd-4210-a682-e4f1613c28bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627038642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2627038642
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1800451689
Short name T260
Test name
Test status
Simulation time 3674772047 ps
CPU time 30.85 seconds
Started Aug 15 05:08:18 PM PDT 24
Finished Aug 15 05:08:49 PM PDT 24
Peak memory 275608 kb
Host smart-a9729301-3f88-4e14-8f32-09ff3b969894
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800451689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1800451689
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3398382695
Short name T230
Test name
Test status
Simulation time 1596174163 ps
CPU time 15.51 seconds
Started Aug 15 05:08:21 PM PDT 24
Finished Aug 15 05:08:37 PM PDT 24
Peak memory 226328 kb
Host smart-01b3e2af-5b81-41c2-80d5-6748d6b83186
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398382695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3398382695
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.4215450573
Short name T819
Test name
Test status
Simulation time 160978727 ps
CPU time 4.17 seconds
Started Aug 15 05:08:18 PM PDT 24
Finished Aug 15 05:08:22 PM PDT 24
Peak memory 218268 kb
Host smart-e70d1004-a54f-4ab0-abc1-cb04b7510693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215450573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.4215450573
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.444364437
Short name T97
Test name
Test status
Simulation time 705552584 ps
CPU time 10.06 seconds
Started Aug 15 05:08:22 PM PDT 24
Finished Aug 15 05:08:32 PM PDT 24
Peak memory 214944 kb
Host smart-a748b880-d6f8-4cda-b741-9aa9021d64c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444364437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.444364437
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3349271954
Short name T439
Test name
Test status
Simulation time 1050931161 ps
CPU time 12.15 seconds
Started Aug 15 05:08:21 PM PDT 24
Finished Aug 15 05:08:33 PM PDT 24
Peak memory 218364 kb
Host smart-242ed90d-a647-42e3-b715-ad9f6c3169d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349271954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3349271954
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.389991416
Short name T335
Test name
Test status
Simulation time 905863419 ps
CPU time 23.68 seconds
Started Aug 15 05:08:19 PM PDT 24
Finished Aug 15 05:08:43 PM PDT 24
Peak memory 226024 kb
Host smart-250bbfa2-6bd7-4c53-8f3d-77222e9c3a6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389991416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.389991416
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1615592423
Short name T478
Test name
Test status
Simulation time 740815076 ps
CPU time 8.54 seconds
Started Aug 15 05:08:20 PM PDT 24
Finished Aug 15 05:08:28 PM PDT 24
Peak memory 218276 kb
Host smart-2a23541a-bd02-4510-9544-9390a43e0343
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615592423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
615592423
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.615879262
Short name T524
Test name
Test status
Simulation time 2000129419 ps
CPU time 10.31 seconds
Started Aug 15 05:08:21 PM PDT 24
Finished Aug 15 05:08:31 PM PDT 24
Peak memory 218412 kb
Host smart-bfa76dff-a427-4326-9882-9d4104f56b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615879262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.615879262
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1636128955
Short name T184
Test name
Test status
Simulation time 77052218 ps
CPU time 2.54 seconds
Started Aug 15 05:08:11 PM PDT 24
Finished Aug 15 05:08:14 PM PDT 24
Peak memory 214656 kb
Host smart-995a7aec-de85-4ea7-9841-6c41d1a9e689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636128955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1636128955
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.324015240
Short name T858
Test name
Test status
Simulation time 283033992 ps
CPU time 28.31 seconds
Started Aug 15 05:08:15 PM PDT 24
Finished Aug 15 05:08:43 PM PDT 24
Peak memory 250948 kb
Host smart-532d06c9-e2de-40b3-b82f-b1c78739af61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324015240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.324015240
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2858799717
Short name T776
Test name
Test status
Simulation time 320388930 ps
CPU time 7.74 seconds
Started Aug 15 05:08:22 PM PDT 24
Finished Aug 15 05:08:30 PM PDT 24
Peak memory 248440 kb
Host smart-e588d226-c984-4449-8d83-66e00db17100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858799717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2858799717
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3853933394
Short name T468
Test name
Test status
Simulation time 61422235593 ps
CPU time 124.59 seconds
Started Aug 15 05:08:21 PM PDT 24
Finished Aug 15 05:10:26 PM PDT 24
Peak memory 283080 kb
Host smart-cbae9f59-835b-48db-8c28-04d4551168f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853933394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3853933394
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.4034784468
Short name T247
Test name
Test status
Simulation time 51745476 ps
CPU time 0.88 seconds
Started Aug 15 05:08:10 PM PDT 24
Finished Aug 15 05:08:11 PM PDT 24
Peak memory 212056 kb
Host smart-12fa6f8f-ce64-4ab0-8dc5-34f5b715ec1a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034784468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.4034784468
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.4140002549
Short name T671
Test name
Test status
Simulation time 140722547 ps
CPU time 1.02 seconds
Started Aug 15 05:08:32 PM PDT 24
Finished Aug 15 05:08:33 PM PDT 24
Peak memory 209008 kb
Host smart-84dcd36c-6b1a-4011-b495-70f4bbc57212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140002549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.4140002549
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3593584298
Short name T604
Test name
Test status
Simulation time 10654424 ps
CPU time 0.92 seconds
Started Aug 15 05:08:27 PM PDT 24
Finished Aug 15 05:08:28 PM PDT 24
Peak memory 208856 kb
Host smart-fa46dd57-30f9-464f-a059-49b3d49a4f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593584298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3593584298
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.132362715
Short name T102
Test name
Test status
Simulation time 378084808 ps
CPU time 11.99 seconds
Started Aug 15 05:08:20 PM PDT 24
Finished Aug 15 05:08:32 PM PDT 24
Peak memory 218284 kb
Host smart-66035ca5-dabf-4b43-b80c-a7bf324beb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132362715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.132362715
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3981638482
Short name T464
Test name
Test status
Simulation time 272803115 ps
CPU time 6.93 seconds
Started Aug 15 05:08:29 PM PDT 24
Finished Aug 15 05:08:36 PM PDT 24
Peak memory 216876 kb
Host smart-86a6001f-662c-4dcb-9fb5-202d6a6c0bde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981638482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3981638482
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3459143721
Short name T646
Test name
Test status
Simulation time 6134952374 ps
CPU time 33.75 seconds
Started Aug 15 05:08:28 PM PDT 24
Finished Aug 15 05:09:02 PM PDT 24
Peak memory 218944 kb
Host smart-6bc58fc5-dba4-4471-80df-d2fcfb01b494
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459143721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3459143721
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1320765714
Short name T459
Test name
Test status
Simulation time 7589259858 ps
CPU time 42.5 seconds
Started Aug 15 05:08:28 PM PDT 24
Finished Aug 15 05:09:11 PM PDT 24
Peak memory 217876 kb
Host smart-0d8cb737-4bdc-4d31-8421-375e432a86d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320765714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
320765714
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.4251005304
Short name T321
Test name
Test status
Simulation time 148702825 ps
CPU time 3.27 seconds
Started Aug 15 05:08:28 PM PDT 24
Finished Aug 15 05:08:31 PM PDT 24
Peak memory 222060 kb
Host smart-55bf61f3-349a-474e-bd1b-6a19ba3b4b47
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251005304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.4251005304
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3656242797
Short name T552
Test name
Test status
Simulation time 3689067413 ps
CPU time 11.55 seconds
Started Aug 15 05:08:32 PM PDT 24
Finished Aug 15 05:08:43 PM PDT 24
Peak memory 217744 kb
Host smart-7a99d3f7-766a-45ee-b416-6db4dfb52252
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656242797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3656242797
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1477677870
Short name T660
Test name
Test status
Simulation time 1481406801 ps
CPU time 7.37 seconds
Started Aug 15 05:08:29 PM PDT 24
Finished Aug 15 05:08:36 PM PDT 24
Peak memory 217304 kb
Host smart-6f80e715-01a5-4826-9a62-020408f84bfb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477677870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1477677870
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.946880186
Short name T716
Test name
Test status
Simulation time 11784399411 ps
CPU time 42.65 seconds
Started Aug 15 05:08:27 PM PDT 24
Finished Aug 15 05:09:10 PM PDT 24
Peak memory 270624 kb
Host smart-ec6e8d51-c24d-4a62-9781-d9057d26f75c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946880186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.946880186
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1009333685
Short name T629
Test name
Test status
Simulation time 797672098 ps
CPU time 24.92 seconds
Started Aug 15 05:08:32 PM PDT 24
Finished Aug 15 05:08:57 PM PDT 24
Peak memory 247636 kb
Host smart-6fea2f12-7e82-40b0-87d5-d759e27ba4ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009333685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1009333685
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2128135246
Short name T532
Test name
Test status
Simulation time 820058285 ps
CPU time 2.61 seconds
Started Aug 15 05:08:21 PM PDT 24
Finished Aug 15 05:08:24 PM PDT 24
Peak memory 218348 kb
Host smart-f01c97c2-8597-49b5-9c95-65b9452b42f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128135246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2128135246
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3350404019
Short name T674
Test name
Test status
Simulation time 359942934 ps
CPU time 13.82 seconds
Started Aug 15 05:08:19 PM PDT 24
Finished Aug 15 05:08:33 PM PDT 24
Peak memory 214816 kb
Host smart-3546fd91-e1f9-4098-bb0a-0a69b698ea11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350404019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3350404019
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2555613969
Short name T338
Test name
Test status
Simulation time 880677217 ps
CPU time 11.82 seconds
Started Aug 15 05:08:26 PM PDT 24
Finished Aug 15 05:08:38 PM PDT 24
Peak memory 226148 kb
Host smart-303df43b-8b8f-46a1-b58e-95eba36d6ce2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555613969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2555613969
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.56418195
Short name T729
Test name
Test status
Simulation time 392023614 ps
CPU time 9.58 seconds
Started Aug 15 05:08:28 PM PDT 24
Finished Aug 15 05:08:38 PM PDT 24
Peak memory 226040 kb
Host smart-57f2d72f-b052-47d7-a9c2-c362188a8180
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56418195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dige
st.56418195
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1055919425
Short name T173
Test name
Test status
Simulation time 1811751306 ps
CPU time 9.28 seconds
Started Aug 15 05:08:28 PM PDT 24
Finished Aug 15 05:08:38 PM PDT 24
Peak memory 225984 kb
Host smart-eb447fb5-289c-46d1-93f1-470dd50c9072
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055919425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
055919425
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3244757415
Short name T46
Test name
Test status
Simulation time 1189581188 ps
CPU time 10.57 seconds
Started Aug 15 05:08:23 PM PDT 24
Finished Aug 15 05:08:34 PM PDT 24
Peak memory 218252 kb
Host smart-f19b5104-2532-4990-9e24-c79f6a8949d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244757415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3244757415
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1967574642
Short name T75
Test name
Test status
Simulation time 208732961 ps
CPU time 2.81 seconds
Started Aug 15 05:08:19 PM PDT 24
Finished Aug 15 05:08:22 PM PDT 24
Peak memory 214524 kb
Host smart-ea24870a-cd52-490f-b84e-c126a005a011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967574642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1967574642
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2631963549
Short name T514
Test name
Test status
Simulation time 504086220 ps
CPU time 24.38 seconds
Started Aug 15 05:08:21 PM PDT 24
Finished Aug 15 05:08:46 PM PDT 24
Peak memory 250976 kb
Host smart-1e6a063c-7148-40d7-956a-75f313cd33c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631963549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2631963549
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3673489267
Short name T4
Test name
Test status
Simulation time 218396685 ps
CPU time 7.23 seconds
Started Aug 15 05:08:17 PM PDT 24
Finished Aug 15 05:08:25 PM PDT 24
Peak memory 250400 kb
Host smart-e3621fea-6800-4c71-b86a-ef6bcb0f3e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673489267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3673489267
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3853176369
Short name T170
Test name
Test status
Simulation time 6326345139 ps
CPU time 118.12 seconds
Started Aug 15 05:08:27 PM PDT 24
Finished Aug 15 05:10:26 PM PDT 24
Peak memory 251132 kb
Host smart-45d2b46d-d9bb-480d-8717-5294a069526d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853176369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3853176369
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.235807125
Short name T594
Test name
Test status
Simulation time 13574605 ps
CPU time 0.94 seconds
Started Aug 15 05:08:18 PM PDT 24
Finished Aug 15 05:08:19 PM PDT 24
Peak memory 209064 kb
Host smart-30d60cef-d784-46ca-adf0-fa8aba41e24c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235807125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.235807125
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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