Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58549657

1

T1

36003

T2

4569

T3

228676

auto[1]

1178812

1

T1

1188

T2

198

T3

1355

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58560795

1

T1

35013

T2

4569

T3

228163

auto[1]

1167674

1

T1

2178

T2

198

T3

1868

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5433005	1			T1	8200		T2	1213		T3	20615
auto[IdleSt]	16069238	1			T1	5905		T2	1016		T3	54053
auto[ClkMuxSt]	28711	1			T1	64		T2	7		T3	61
auto[CntIncrSt]	28506	1			T1	64		T2	7		T3	61
auto[CntProgSt]	1338551	1			T1	603		T2	14		T3	122
auto[TransCheckSt]	22595	1			T1	51		T2	7		T3	47
auto[TokenHashSt]	15147884	1			T1	4395		T2	163		T3	94636
auto[FlashRmaSt]	27665	1			T1	167		T2	34		T3	115
auto[TokenCheck0St]	10188	1			T1	40		T2	7		T3	46
auto[TokenCheck1St]	7540	1			T1	22		T2	7		T3	46
auto[TransProgSt]	305022	1			T1	237		T2	14		T3	92
auto[PostTransSt]	8687538	1			T1	9721		T2	1191		T3	27653
auto[ScrapSt]	246115	1			T3	154		T16	40		T18	1166
auto[EscalateSt]	4894822	1			T1	4588		T2	741		T3	18843
auto[InvalidSt]	7479685	1			T1	3134		T2	345		T3	13484

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1404	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7479685	1			T1	3134		T2	345		T3	13484
EscalateSt	4894822	1			T1	4588		T2	741		T3	18843
ScrapSt	246115	1			T3	154		T16	40		T18	1166
PostTransSt	8687538	1			T1	9721		T2	1191		T3	27653
TransProgSt	305022	1			T1	237		T2	14		T3	92
TokenCheck1St	7540	1			T1	22		T2	7		T3	46
TokenCheck0St	10188	1			T1	40		T2	7		T3	46
FlashRmaSt	27665	1			T1	167		T2	34		T3	115
TokenHashSt	15147884	1			T1	4395		T2	163		T3	94636
TransCheckSt	22595	1			T1	51		T2	7		T3	47
CntProgSt	1338551	1			T1	603		T2	14		T3	122
CntIncrSt	28506	1			T1	64		T2	7		T3	61
ClkMuxSt	28711	1			T1	64		T2	7		T3	61
IdleSt	16069238	1			T1	5905		T2	1016		T3	54053
ResetSt	5433005	1			T1	8200		T2	1213		T3	20615
arcs[ResetSt=>IdleSt]	42337	1			T1	86		T2	13		T3	92
arcs[IdleSt=>ScrapSt]	220	1			T3	2		T16	2		T18	1
arcs[IdleSt=>ClkMuxSt]	28548	1			T1	64		T2	7		T3	61
arcs[ClkMuxSt=>CntIncrSt]	28506	1			T1	64		T2	7		T3	61
arcs[CntIncrSt=>PostTransSt]	1249	1			T13	5		T4	9		T17	10
arcs[CntIncrSt=>CntProgSt]	27187	1			T1	64		T2	7		T3	61
arcs[CntProgSt=>PostTransSt]	3576	1			T1	13		T3	14		T13	9
arcs[CntProgSt=>TransCheckSt]	22595	1			T1	51		T2	7		T3	47
arcs[TransCheckSt=>PostTransSt]	3046	1			T10	42		T13	6		T4	8
arcs[TransCheckSt=>TokenHashSt]	19432	1			T1	51		T2	7		T3	47
arcs[TokenHashSt=>PostTransSt]	8357	1			T1	11		T3	1		T10	14
arcs[TokenHashSt=>FlashRmaSt]	10227	1			T1	40		T2	7		T3	46
arcs[FlashRmaSt=>TokenCheck0St]	10188	1			T1	40		T2	7		T3	46
arcs[TokenCheck0St=>PostTransSt]	2600	1			T1	18		T10	21		T13	6
arcs[TokenCheck0St=>TokenCheck1St]	7540	1			T1	22		T2	7		T3	46
arcs[TokenCheck1St=>PostTransSt]	585	1			T10	11		T13	3		T17	2
arcs[TransProgSt=>PostTransSt]	6172	1			T1	22		T2	7		T3	46
arcs[IdleSt=>EscalateSt]	211	1			T52	4		T53	3		T54	9
arcs[ClkMuxSt=>EscalateSt]	42	1			T52	1		T53	4		T54	2
arcs[CntIncrSt=>EscalateSt]	70	1			T52	1		T53	1		T54	2
arcs[CntProgSt=>EscalateSt]	1016	1			T40	18		T55	34		T52	28
arcs[TransCheckSt=>EscalateSt]	117	1			T55	1		T53	3		T54	7
arcs[TokenHashSt=>EscalateSt]	847	1			T40	11		T55	9		T52	8
arcs[FlashRmaSt=>EscalateSt]	39	1			T40	1		T52	1		T53	2
arcs[TokenCheck0St=>EscalateSt]	48	1			T40	1		T55	2		T52	3
arcs[TokenCheck1St=>EscalateSt]	28	1			T55	1		T53	1		T54	2
arcs[TransProgSt=>EscalateSt]	755	1			T40	20		T55	14		T52	16
arcs[PostTransSt=>EscalateSt]	3978	1			T1	13		T3	14		T13	9
arcs[InvalidSt=>EscalateSt]	9924	1			T1	21		T2	4		T3	19

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5432813	1			T1	8200		T2	1213		T3	20615
auto[0]	auto[IdleSt]	16069102	1			T1	5905		T2	1016		T3	54053
auto[0]	auto[ClkMuxSt]	28686	1			T1	64		T2	7		T3	61
auto[0]	auto[CntIncrSt]	28460	1			T1	64		T2	7		T3	61
auto[0]	auto[CntProgSt]	1337874	1			T1	603		T2	14		T3	122
auto[0]	auto[TransCheckSt]	22505	1			T1	51		T2	7		T3	47
auto[0]	auto[TokenHashSt]	15147323	1			T1	4395		T2	163		T3	94636
auto[0]	auto[FlashRmaSt]	27633	1			T1	167		T2	34		T3	115
auto[0]	auto[TokenCheck0St]	10158	1			T1	40		T2	7		T3	46
auto[0]	auto[TokenCheck1St]	7519	1			T1	22		T2	7		T3	46
auto[0]	auto[TransProgSt]	304510	1			T1	237		T2	14		T3	92
auto[0]	auto[PostTransSt]	8685463	1			T1	9718		T2	1191		T3	27646
auto[0]	auto[ScrapSt]	246087	1			T3	154		T16	40		T18	1166
auto[0]	auto[EscalateSt]	3725446	1			T1	3412		T2	545		T3	17502
auto[0]	auto[InvalidSt]	7474674	1			T1	3125		T2	343		T3	13477
auto[1]	auto[ResetSt]	192	1			T40	4		T55	3		T52	3
auto[1]	auto[IdleSt]	136	1			T52	3		T53	2		T54	6
auto[1]	auto[ClkMuxSt]	25	1			T53	2		T54	1		T210	1
auto[1]	auto[CntIncrSt]	46	1			T52	1		T53	1		T211	1
auto[1]	auto[CntProgSt]	677	1			T40	15		T55	24		T52	14
auto[1]	auto[TransCheckSt]	90	1			T55	1		T53	3		T54	6
auto[1]	auto[TokenHashSt]	561	1			T40	5		T55	6		T52	5
auto[1]	auto[FlashRmaSt]	32	1			T40	1		T53	1		T54	2
auto[1]	auto[TokenCheck0St]	30	1			T40	1		T55	2		T52	2
auto[1]	auto[TokenCheck1St]	21	1			T55	1		T53	1		T54	2
auto[1]	auto[TransProgSt]	512	1			T40	13		T55	9		T52	13
auto[1]	auto[PostTransSt]	2075	1			T1	3		T3	7		T13	6
auto[1]	auto[ScrapSt]	28	1			T40	1		T52	1		T53	1
auto[1]	auto[EscalateSt]	1169376	1			T1	1176		T2	196		T3	1341
auto[1]	auto[InvalidSt]	5011	1			T1	9		T2	2		T3	7

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5432799	1			T1	8200		T2	1213		T3	20615
auto[0]	auto[IdleSt]	16069096	1			T1	5905		T2	1016		T3	54053
auto[0]	auto[ClkMuxSt]	28677	1			T1	64		T2	7		T3	61
auto[0]	auto[CntIncrSt]	28463	1			T1	64		T2	7		T3	61
auto[0]	auto[CntProgSt]	1337870	1			T1	603		T2	14		T3	122
auto[0]	auto[TransCheckSt]	22522	1			T1	51		T2	7		T3	47
auto[0]	auto[TokenHashSt]	15147316	1			T1	4395		T2	163		T3	94636
auto[0]	auto[FlashRmaSt]	27643	1			T1	167		T2	34		T3	115
auto[0]	auto[TokenCheck0St]	10154	1			T1	40		T2	7		T3	46
auto[0]	auto[TokenCheck1St]	7523	1			T1	22		T2	7		T3	46
auto[0]	auto[TransProgSt]	304535	1			T1	237		T2	14		T3	92
auto[0]	auto[PostTransSt]	8685493	1			T1	9711		T2	1191		T3	27646
auto[0]	auto[ScrapSt]	246092	1			T3	154		T16	40		T18	1166
auto[0]	auto[EscalateSt]	3736436	1			T1	2432		T2	545		T3	16994
auto[0]	auto[InvalidSt]	7474772	1			T1	3122		T2	343		T3	13472
auto[1]	auto[ResetSt]	206	1			T40	6		T55	3		T52	3
auto[1]	auto[IdleSt]	142	1			T52	3		T53	2		T54	5
auto[1]	auto[ClkMuxSt]	34	1			T52	1		T53	4		T54	2
auto[1]	auto[CntIncrSt]	43	1			T54	2		T212	1		T213	3
auto[1]	auto[CntProgSt]	681	1			T40	12		T55	21		T52	21
auto[1]	auto[TransCheckSt]	73	1			T53	2		T54	5		T211	1
auto[1]	auto[TokenHashSt]	568	1			T40	9		T55	6		T52	6
auto[1]	auto[FlashRmaSt]	22	1			T40	1		T52	1		T53	1
auto[1]	auto[TokenCheck0St]	34	1			T52	2		T214	1		T211	1
auto[1]	auto[TokenCheck1St]	17	1			T55	1		T53	1		T54	1
auto[1]	auto[TransProgSt]	487	1			T40	14		T55	12		T52	11
auto[1]	auto[PostTransSt]	2045	1			T1	10		T3	7		T13	3
auto[1]	auto[ScrapSt]	23	1			T40	1		T52	2		T54	2
auto[1]	auto[EscalateSt]	1158386	1			T1	2156		T2	196		T3	1849
auto[1]	auto[InvalidSt]	4913	1			T1	12		T2	2		T3	12