Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.25 97.99 95.95 93.40 100.00 98.55 98.76 96.11


Total test records in report: 1008
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T805 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2244922066 Aug 16 04:41:45 PM PDT 24 Aug 16 04:41:55 PM PDT 24 262375553 ps
T806 /workspace/coverage/default/10.lc_ctrl_state_post_trans.1839288647 Aug 16 04:39:18 PM PDT 24 Aug 16 04:39:26 PM PDT 24 220678825 ps
T807 /workspace/coverage/default/36.lc_ctrl_prog_failure.2163482163 Aug 16 04:41:16 PM PDT 24 Aug 16 04:41:19 PM PDT 24 518283216 ps
T808 /workspace/coverage/default/12.lc_ctrl_stress_all.960999718 Aug 16 04:39:41 PM PDT 24 Aug 16 04:40:13 PM PDT 24 1601085987 ps
T809 /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2657273881 Aug 16 04:39:02 PM PDT 24 Aug 16 04:39:03 PM PDT 24 83056926 ps
T810 /workspace/coverage/default/25.lc_ctrl_alert_test.1633691129 Aug 16 04:40:50 PM PDT 24 Aug 16 04:40:51 PM PDT 24 16015710 ps
T811 /workspace/coverage/default/40.lc_ctrl_state_failure.488382999 Aug 16 04:41:28 PM PDT 24 Aug 16 04:41:53 PM PDT 24 1737348324 ps
T812 /workspace/coverage/default/14.lc_ctrl_prog_failure.2964112184 Aug 16 04:39:56 PM PDT 24 Aug 16 04:40:00 PM PDT 24 149973145 ps
T813 /workspace/coverage/default/28.lc_ctrl_errors.43231895 Aug 16 04:40:59 PM PDT 24 Aug 16 04:41:11 PM PDT 24 1529030726 ps
T814 /workspace/coverage/default/22.lc_ctrl_security_escalation.3602108615 Aug 16 04:40:49 PM PDT 24 Aug 16 04:40:59 PM PDT 24 1680466145 ps
T815 /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.363797744 Aug 16 04:39:17 PM PDT 24 Aug 16 04:39:26 PM PDT 24 255737444 ps
T816 /workspace/coverage/default/42.lc_ctrl_prog_failure.393017447 Aug 16 04:41:36 PM PDT 24 Aug 16 04:41:40 PM PDT 24 73479705 ps
T817 /workspace/coverage/default/33.lc_ctrl_sec_mubi.795029158 Aug 16 04:41:08 PM PDT 24 Aug 16 04:41:20 PM PDT 24 1428174639 ps
T818 /workspace/coverage/default/18.lc_ctrl_jtag_errors.417950516 Aug 16 04:40:35 PM PDT 24 Aug 16 04:41:33 PM PDT 24 2018990494 ps
T819 /workspace/coverage/default/39.lc_ctrl_alert_test.1567618459 Aug 16 04:41:34 PM PDT 24 Aug 16 04:41:35 PM PDT 24 54348723 ps
T820 /workspace/coverage/default/48.lc_ctrl_security_escalation.2897477654 Aug 16 04:41:52 PM PDT 24 Aug 16 04:42:14 PM PDT 24 1630790833 ps
T821 /workspace/coverage/default/29.lc_ctrl_state_post_trans.2392396821 Aug 16 04:40:58 PM PDT 24 Aug 16 04:41:05 PM PDT 24 212368506 ps
T822 /workspace/coverage/default/4.lc_ctrl_state_post_trans.258548262 Aug 16 04:38:51 PM PDT 24 Aug 16 04:38:55 PM PDT 24 64671551 ps
T823 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.79747827 Aug 16 04:41:08 PM PDT 24 Aug 16 04:41:30 PM PDT 24 4231916863 ps
T824 /workspace/coverage/default/6.lc_ctrl_errors.4200709446 Aug 16 04:38:59 PM PDT 24 Aug 16 04:39:12 PM PDT 24 351253946 ps
T825 /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2939290635 Aug 16 04:40:36 PM PDT 24 Aug 16 04:41:10 PM PDT 24 5851502127 ps
T826 /workspace/coverage/default/25.lc_ctrl_security_escalation.3941108647 Aug 16 04:40:51 PM PDT 24 Aug 16 04:41:08 PM PDT 24 900959323 ps
T827 /workspace/coverage/default/21.lc_ctrl_sec_token_digest.897799339 Aug 16 04:40:42 PM PDT 24 Aug 16 04:40:55 PM PDT 24 2437496365 ps
T828 /workspace/coverage/default/43.lc_ctrl_prog_failure.3659805571 Aug 16 04:41:40 PM PDT 24 Aug 16 04:41:41 PM PDT 24 14654811 ps
T829 /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.525442961 Aug 16 04:38:44 PM PDT 24 Aug 16 04:40:07 PM PDT 24 9850203276 ps
T830 /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3729287034 Aug 16 04:41:29 PM PDT 24 Aug 16 04:41:30 PM PDT 24 27619114 ps
T831 /workspace/coverage/default/30.lc_ctrl_state_failure.713375952 Aug 16 04:41:07 PM PDT 24 Aug 16 04:41:29 PM PDT 24 968518274 ps
T832 /workspace/coverage/default/36.lc_ctrl_state_failure.846578156 Aug 16 04:41:14 PM PDT 24 Aug 16 04:41:36 PM PDT 24 2952780453 ps
T833 /workspace/coverage/default/26.lc_ctrl_state_post_trans.715892990 Aug 16 04:40:51 PM PDT 24 Aug 16 04:40:56 PM PDT 24 83157562 ps
T834 /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1373408761 Aug 16 04:39:15 PM PDT 24 Aug 16 04:39:25 PM PDT 24 239303716 ps
T835 /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3494883172 Aug 16 04:40:22 PM PDT 24 Aug 16 04:41:04 PM PDT 24 4789184792 ps
T836 /workspace/coverage/default/35.lc_ctrl_stress_all.555470608 Aug 16 04:41:16 PM PDT 24 Aug 16 04:43:14 PM PDT 24 2971388719 ps
T837 /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1944153718 Aug 16 04:40:26 PM PDT 24 Aug 16 04:42:07 PM PDT 24 7278195114 ps
T838 /workspace/coverage/default/29.lc_ctrl_prog_failure.1606201855 Aug 16 04:40:59 PM PDT 24 Aug 16 04:41:01 PM PDT 24 232858702 ps
T839 /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2589140293 Aug 16 04:41:45 PM PDT 24 Aug 16 04:41:58 PM PDT 24 1394006072 ps
T840 /workspace/coverage/default/38.lc_ctrl_security_escalation.2407791537 Aug 16 04:41:18 PM PDT 24 Aug 16 04:41:31 PM PDT 24 333784460 ps
T841 /workspace/coverage/default/13.lc_ctrl_prog_failure.1314841486 Aug 16 04:39:50 PM PDT 24 Aug 16 04:39:53 PM PDT 24 163767940 ps
T842 /workspace/coverage/default/13.lc_ctrl_state_post_trans.1175032754 Aug 16 04:39:50 PM PDT 24 Aug 16 04:40:01 PM PDT 24 193145579 ps
T843 /workspace/coverage/default/40.lc_ctrl_security_escalation.10131713 Aug 16 04:41:27 PM PDT 24 Aug 16 04:41:43 PM PDT 24 423350436 ps
T844 /workspace/coverage/default/44.lc_ctrl_state_post_trans.2641089985 Aug 16 04:41:40 PM PDT 24 Aug 16 04:41:43 PM PDT 24 347218715 ps
T845 /workspace/coverage/default/3.lc_ctrl_state_failure.3707103667 Aug 16 04:38:53 PM PDT 24 Aug 16 04:39:13 PM PDT 24 204324531 ps
T846 /workspace/coverage/default/39.lc_ctrl_errors.92340294 Aug 16 04:41:32 PM PDT 24 Aug 16 04:41:46 PM PDT 24 1971590638 ps
T847 /workspace/coverage/default/13.lc_ctrl_jtag_smoke.605068206 Aug 16 04:39:51 PM PDT 24 Aug 16 04:39:59 PM PDT 24 536901142 ps
T145 /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.1920165425 Aug 16 04:38:44 PM PDT 24 Aug 16 04:40:01 PM PDT 24 4531788671 ps
T848 /workspace/coverage/default/15.lc_ctrl_sec_mubi.3769990640 Aug 16 04:40:19 PM PDT 24 Aug 16 04:40:37 PM PDT 24 370193223 ps
T849 /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2813804957 Aug 16 04:41:46 PM PDT 24 Aug 16 04:41:47 PM PDT 24 14299135 ps
T850 /workspace/coverage/default/18.lc_ctrl_stress_all.3775762829 Aug 16 04:40:38 PM PDT 24 Aug 16 04:41:14 PM PDT 24 6394616222 ps
T851 /workspace/coverage/default/11.lc_ctrl_state_failure.3139493414 Aug 16 04:39:31 PM PDT 24 Aug 16 04:40:05 PM PDT 24 272870618 ps
T852 /workspace/coverage/default/27.lc_ctrl_stress_all.3705645196 Aug 16 04:40:58 PM PDT 24 Aug 16 04:41:29 PM PDT 24 6315042373 ps
T853 /workspace/coverage/default/0.lc_ctrl_jtag_errors.4066497966 Aug 16 04:38:41 PM PDT 24 Aug 16 04:39:25 PM PDT 24 2757744459 ps
T854 /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2723727907 Aug 16 04:38:49 PM PDT 24 Aug 16 04:40:19 PM PDT 24 8682883172 ps
T855 /workspace/coverage/default/45.lc_ctrl_security_escalation.2153885552 Aug 16 04:41:45 PM PDT 24 Aug 16 04:41:56 PM PDT 24 1356812713 ps
T856 /workspace/coverage/default/1.lc_ctrl_alert_test.3041345527 Aug 16 04:38:44 PM PDT 24 Aug 16 04:38:46 PM PDT 24 21743120 ps
T857 /workspace/coverage/default/43.lc_ctrl_sec_token_digest.4100758582 Aug 16 04:41:39 PM PDT 24 Aug 16 04:41:48 PM PDT 24 1433002554 ps
T858 /workspace/coverage/default/46.lc_ctrl_sec_mubi.1231715841 Aug 16 04:41:50 PM PDT 24 Aug 16 04:42:07 PM PDT 24 607496926 ps
T859 /workspace/coverage/default/26.lc_ctrl_alert_test.2826528867 Aug 16 04:40:58 PM PDT 24 Aug 16 04:40:59 PM PDT 24 84344630 ps
T860 /workspace/coverage/default/21.lc_ctrl_state_post_trans.754072630 Aug 16 04:40:48 PM PDT 24 Aug 16 04:40:55 PM PDT 24 275062377 ps
T861 /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3720748682 Aug 16 04:38:52 PM PDT 24 Aug 16 04:38:53 PM PDT 24 44289403 ps
T862 /workspace/coverage/default/16.lc_ctrl_jtag_smoke.707543968 Aug 16 04:40:27 PM PDT 24 Aug 16 04:40:33 PM PDT 24 408628945 ps
T863 /workspace/coverage/default/16.lc_ctrl_state_post_trans.3229301287 Aug 16 04:40:19 PM PDT 24 Aug 16 04:40:22 PM PDT 24 173291702 ps
T864 /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2917837652 Aug 16 04:38:59 PM PDT 24 Aug 16 04:39:11 PM PDT 24 249466381 ps
T865 /workspace/coverage/default/5.lc_ctrl_alert_test.1625734485 Aug 16 04:39:00 PM PDT 24 Aug 16 04:39:01 PM PDT 24 71867173 ps
T146 /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2875605234 Aug 16 04:40:51 PM PDT 24 Aug 16 04:41:52 PM PDT 24 14246622079 ps
T866 /workspace/coverage/default/26.lc_ctrl_errors.2872039927 Aug 16 04:40:54 PM PDT 24 Aug 16 04:41:04 PM PDT 24 196686116 ps
T867 /workspace/coverage/default/10.lc_ctrl_state_failure.1474988746 Aug 16 04:39:21 PM PDT 24 Aug 16 04:39:48 PM PDT 24 1383864445 ps
T868 /workspace/coverage/default/4.lc_ctrl_jtag_access.1384838589 Aug 16 04:38:50 PM PDT 24 Aug 16 04:38:54 PM PDT 24 219372638 ps
T869 /workspace/coverage/default/49.lc_ctrl_smoke.1492875352 Aug 16 04:41:54 PM PDT 24 Aug 16 04:41:57 PM PDT 24 36879543 ps
T870 /workspace/coverage/default/4.lc_ctrl_jtag_priority.385311779 Aug 16 04:38:59 PM PDT 24 Aug 16 04:39:15 PM PDT 24 2651052235 ps
T871 /workspace/coverage/default/9.lc_ctrl_jtag_access.3305275929 Aug 16 04:39:21 PM PDT 24 Aug 16 04:39:25 PM PDT 24 130220149 ps
T872 /workspace/coverage/default/22.lc_ctrl_jtag_access.1316193988 Aug 16 04:40:48 PM PDT 24 Aug 16 04:40:53 PM PDT 24 714845720 ps
T873 /workspace/coverage/default/13.lc_ctrl_security_escalation.2040621538 Aug 16 04:39:50 PM PDT 24 Aug 16 04:40:02 PM PDT 24 3122529833 ps
T874 /workspace/coverage/default/22.lc_ctrl_stress_all.2888499457 Aug 16 04:40:50 PM PDT 24 Aug 16 04:42:34 PM PDT 24 9018918670 ps
T875 /workspace/coverage/default/11.lc_ctrl_sec_mubi.1916318425 Aug 16 04:39:35 PM PDT 24 Aug 16 04:39:44 PM PDT 24 809923680 ps
T100 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1382512486 Aug 16 04:36:22 PM PDT 24 Aug 16 04:36:25 PM PDT 24 109008215 ps
T108 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1249353965 Aug 16 04:36:15 PM PDT 24 Aug 16 04:36:19 PM PDT 24 2055987383 ps
T115 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3203490803 Aug 16 04:36:05 PM PDT 24 Aug 16 04:36:28 PM PDT 24 1796745419 ps
T116 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1776165243 Aug 16 04:36:09 PM PDT 24 Aug 16 04:36:12 PM PDT 24 168552023 ps
T133 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1710105018 Aug 16 04:36:02 PM PDT 24 Aug 16 04:36:03 PM PDT 24 29565304 ps
T101 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3973577977 Aug 16 04:36:31 PM PDT 24 Aug 16 04:36:34 PM PDT 24 294317964 ps
T109 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1848089611 Aug 16 04:36:24 PM PDT 24 Aug 16 04:36:35 PM PDT 24 2345167974 ps
T102 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2312751274 Aug 16 04:36:24 PM PDT 24 Aug 16 04:36:27 PM PDT 24 403154856 ps
T132 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.480228454 Aug 16 04:36:07 PM PDT 24 Aug 16 04:36:08 PM PDT 24 52182660 ps
T876 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3190225091 Aug 16 04:36:00 PM PDT 24 Aug 16 04:36:02 PM PDT 24 140150236 ps
T153 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2245157911 Aug 16 04:36:07 PM PDT 24 Aug 16 04:36:11 PM PDT 24 473191682 ps
T147 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2317029302 Aug 16 04:36:27 PM PDT 24 Aug 16 04:36:29 PM PDT 24 82995937 ps
T107 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.4115300398 Aug 16 04:36:04 PM PDT 24 Aug 16 04:36:05 PM PDT 24 294774763 ps
T877 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2414242510 Aug 16 04:36:06 PM PDT 24 Aug 16 04:36:08 PM PDT 24 77024573 ps
T878 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2363616323 Aug 16 04:36:26 PM PDT 24 Aug 16 04:36:28 PM PDT 24 164634887 ps
T879 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.70023081 Aug 16 04:36:24 PM PDT 24 Aug 16 04:36:25 PM PDT 24 60215822 ps
T106 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3797284215 Aug 16 04:36:41 PM PDT 24 Aug 16 04:36:43 PM PDT 24 21295091 ps
T189 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3148684001 Aug 16 04:36:24 PM PDT 24 Aug 16 04:36:25 PM PDT 24 34403088 ps
T199 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1039874387 Aug 16 04:36:07 PM PDT 24 Aug 16 04:36:08 PM PDT 24 48106183 ps
T200 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1265501114 Aug 16 04:36:28 PM PDT 24 Aug 16 04:36:30 PM PDT 24 99184050 ps
T190 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3441991686 Aug 16 04:36:01 PM PDT 24 Aug 16 04:36:03 PM PDT 24 19452640 ps
T105 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.976795728 Aug 16 04:36:19 PM PDT 24 Aug 16 04:36:21 PM PDT 24 61334130 ps
T154 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3079456124 Aug 16 04:36:28 PM PDT 24 Aug 16 04:36:29 PM PDT 24 30930994 ps
T880 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2834022774 Aug 16 04:36:14 PM PDT 24 Aug 16 04:36:15 PM PDT 24 23137710 ps
T201 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4037117650 Aug 16 04:36:01 PM PDT 24 Aug 16 04:36:03 PM PDT 24 72712579 ps
T202 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3714581656 Aug 16 04:36:37 PM PDT 24 Aug 16 04:36:38 PM PDT 24 47070432 ps
T110 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1605649173 Aug 16 04:36:25 PM PDT 24 Aug 16 04:36:27 PM PDT 24 29886103 ps
T191 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1026180562 Aug 16 04:36:07 PM PDT 24 Aug 16 04:36:08 PM PDT 24 56402932 ps
T119 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2110488237 Aug 16 04:36:03 PM PDT 24 Aug 16 04:36:07 PM PDT 24 323908844 ps
T881 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2649180943 Aug 16 04:36:18 PM PDT 24 Aug 16 04:36:24 PM PDT 24 179475804 ps
T882 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.969330607 Aug 16 04:36:15 PM PDT 24 Aug 16 04:36:16 PM PDT 24 139644002 ps
T203 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4290524077 Aug 16 04:36:32 PM PDT 24 Aug 16 04:36:33 PM PDT 24 30169782 ps
T204 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2638038240 Aug 16 04:36:32 PM PDT 24 Aug 16 04:36:33 PM PDT 24 53457850 ps
T883 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1575165092 Aug 16 04:36:22 PM PDT 24 Aug 16 04:36:23 PM PDT 24 14466134 ps
T113 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2463923302 Aug 16 04:36:31 PM PDT 24 Aug 16 04:36:36 PM PDT 24 510673013 ps
T884 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.370331007 Aug 16 04:36:47 PM PDT 24 Aug 16 04:36:49 PM PDT 24 116344446 ps
T885 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2917726042 Aug 16 04:36:13 PM PDT 24 Aug 16 04:36:15 PM PDT 24 107546395 ps
T111 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.188578949 Aug 16 04:36:08 PM PDT 24 Aug 16 04:36:13 PM PDT 24 445459849 ps
T886 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3251286304 Aug 16 04:36:00 PM PDT 24 Aug 16 04:36:02 PM PDT 24 67064840 ps
T887 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1577720374 Aug 16 04:36:39 PM PDT 24 Aug 16 04:36:41 PM PDT 24 79802803 ps
T114 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3560859878 Aug 16 04:36:12 PM PDT 24 Aug 16 04:36:14 PM PDT 24 29412702 ps
T134 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.649431839 Aug 16 04:36:15 PM PDT 24 Aug 16 04:36:17 PM PDT 24 85289254 ps
T888 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3149428594 Aug 16 04:36:11 PM PDT 24 Aug 16 04:36:13 PM PDT 24 69830460 ps
T889 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3881163701 Aug 16 04:36:25 PM PDT 24 Aug 16 04:36:30 PM PDT 24 1467702494 ps
T890 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.747058875 Aug 16 04:36:26 PM PDT 24 Aug 16 04:36:28 PM PDT 24 517925632 ps
T891 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2206219956 Aug 16 04:36:01 PM PDT 24 Aug 16 04:36:02 PM PDT 24 52929867 ps
T892 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3405351402 Aug 16 04:36:14 PM PDT 24 Aug 16 04:36:15 PM PDT 24 178326523 ps
T893 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2648689311 Aug 16 04:36:28 PM PDT 24 Aug 16 04:36:30 PM PDT 24 40610724 ps
T894 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.748606736 Aug 16 04:36:01 PM PDT 24 Aug 16 04:36:03 PM PDT 24 332404089 ps
T126 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3953326861 Aug 16 04:36:15 PM PDT 24 Aug 16 04:36:18 PM PDT 24 184093112 ps
T895 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2904328061 Aug 16 04:36:04 PM PDT 24 Aug 16 04:36:06 PM PDT 24 18663664 ps
T896 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3647552309 Aug 16 04:35:59 PM PDT 24 Aug 16 04:36:01 PM PDT 24 46106303 ps
T122 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2140976490 Aug 16 04:36:05 PM PDT 24 Aug 16 04:36:11 PM PDT 24 490311661 ps
T127 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2179048717 Aug 16 04:36:20 PM PDT 24 Aug 16 04:36:23 PM PDT 24 107377363 ps
T897 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.572993300 Aug 16 04:36:36 PM PDT 24 Aug 16 04:36:37 PM PDT 24 18931865 ps
T898 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2805943699 Aug 16 04:36:27 PM PDT 24 Aug 16 04:36:28 PM PDT 24 41854567 ps
T899 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.926522139 Aug 16 04:36:03 PM PDT 24 Aug 16 04:36:04 PM PDT 24 163056046 ps
T900 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4235462712 Aug 16 04:36:11 PM PDT 24 Aug 16 04:36:13 PM PDT 24 56980967 ps
T901 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3732757323 Aug 16 04:36:31 PM PDT 24 Aug 16 04:36:32 PM PDT 24 304036441 ps
T902 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2421413412 Aug 16 04:36:38 PM PDT 24 Aug 16 04:36:39 PM PDT 24 37455406 ps
T903 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1680829189 Aug 16 04:36:04 PM PDT 24 Aug 16 04:36:06 PM PDT 24 29127605 ps
T904 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.86892953 Aug 16 04:36:35 PM PDT 24 Aug 16 04:36:36 PM PDT 24 44460933 ps
T905 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2271590779 Aug 16 04:36:06 PM PDT 24 Aug 16 04:36:17 PM PDT 24 911031271 ps
T906 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.748367003 Aug 16 04:36:06 PM PDT 24 Aug 16 04:36:24 PM PDT 24 777509779 ps
T907 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1657066527 Aug 16 04:36:06 PM PDT 24 Aug 16 04:36:20 PM PDT 24 590008648 ps
T908 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2396125725 Aug 16 04:36:27 PM PDT 24 Aug 16 04:36:29 PM PDT 24 80142304 ps
T909 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1773955298 Aug 16 04:36:04 PM PDT 24 Aug 16 04:36:09 PM PDT 24 2633640942 ps
T910 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1223222444 Aug 16 04:36:04 PM PDT 24 Aug 16 04:36:06 PM PDT 24 19952338 ps
T911 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2179516779 Aug 16 04:36:10 PM PDT 24 Aug 16 04:36:12 PM PDT 24 367550036 ps
T912 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1236064407 Aug 16 04:36:31 PM PDT 24 Aug 16 04:36:33 PM PDT 24 212310547 ps
T913 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1205012133 Aug 16 04:36:09 PM PDT 24 Aug 16 04:36:10 PM PDT 24 27583364 ps
T914 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1150028400 Aug 16 04:36:00 PM PDT 24 Aug 16 04:36:02 PM PDT 24 551300399 ps
T915 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2526146995 Aug 16 04:36:33 PM PDT 24 Aug 16 04:36:34 PM PDT 24 53804037 ps
T916 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.120352261 Aug 16 04:36:10 PM PDT 24 Aug 16 04:36:12 PM PDT 24 104062345 ps
T917 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.169644173 Aug 16 04:36:04 PM PDT 24 Aug 16 04:36:05 PM PDT 24 377765512 ps
T918 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2040307216 Aug 16 04:36:23 PM PDT 24 Aug 16 04:36:25 PM PDT 24 95865997 ps
T919 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3948897570 Aug 16 04:36:31 PM PDT 24 Aug 16 04:36:32 PM PDT 24 71776931 ps
T920 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2432691827 Aug 16 04:36:19 PM PDT 24 Aug 16 04:36:24 PM PDT 24 1747436224 ps
T120 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1808627909 Aug 16 04:36:21 PM PDT 24 Aug 16 04:36:23 PM PDT 24 79117754 ps
T921 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.48367261 Aug 16 04:36:23 PM PDT 24 Aug 16 04:36:26 PM PDT 24 119530859 ps
T922 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2487525530 Aug 16 04:36:37 PM PDT 24 Aug 16 04:36:38 PM PDT 24 47607766 ps
T192 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3751156053 Aug 16 04:36:04 PM PDT 24 Aug 16 04:36:06 PM PDT 24 27857415 ps
T923 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2649082458 Aug 16 04:36:01 PM PDT 24 Aug 16 04:36:03 PM PDT 24 104416441 ps
T924 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.382203311 Aug 16 04:36:18 PM PDT 24 Aug 16 04:36:21 PM PDT 24 283769046 ps
T121 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.510333550 Aug 16 04:36:11 PM PDT 24 Aug 16 04:36:13 PM PDT 24 164704448 ps
T925 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3246419514 Aug 16 04:36:08 PM PDT 24 Aug 16 04:36:14 PM PDT 24 73737639 ps
T926 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.216138783 Aug 16 04:36:27 PM PDT 24 Aug 16 04:36:30 PM PDT 24 689183642 ps
T927 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1520501850 Aug 16 04:36:00 PM PDT 24 Aug 16 04:36:01 PM PDT 24 14792146 ps
T928 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3167325249 Aug 16 04:36:14 PM PDT 24 Aug 16 04:36:16 PM PDT 24 54469000 ps
T929 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1723085652 Aug 16 04:36:23 PM PDT 24 Aug 16 04:36:28 PM PDT 24 834214534 ps
T930 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3812279755 Aug 16 04:35:59 PM PDT 24 Aug 16 04:36:01 PM PDT 24 132822947 ps
T131 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.684758530 Aug 16 04:36:07 PM PDT 24 Aug 16 04:36:09 PM PDT 24 413741762 ps
T931 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4193802076 Aug 16 04:36:21 PM PDT 24 Aug 16 04:36:24 PM PDT 24 208022531 ps
T932 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1620676564 Aug 16 04:36:14 PM PDT 24 Aug 16 04:36:15 PM PDT 24 14358768 ps
T933 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.112574312 Aug 16 04:36:55 PM PDT 24 Aug 16 04:36:57 PM PDT 24 630258004 ps
T934 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3201166800 Aug 16 04:36:28 PM PDT 24 Aug 16 04:36:30 PM PDT 24 36750127 ps
T935 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2223618902 Aug 16 04:36:14 PM PDT 24 Aug 16 04:36:17 PM PDT 24 310024906 ps
T936 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3552431978 Aug 16 04:36:14 PM PDT 24 Aug 16 04:36:16 PM PDT 24 41604941 ps
T937 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.306163241 Aug 16 04:36:01 PM PDT 24 Aug 16 04:36:09 PM PDT 24 2966054285 ps
T938 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1512391999 Aug 16 04:36:21 PM PDT 24 Aug 16 04:36:23 PM PDT 24 244835839 ps
T939 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4042334236 Aug 16 04:36:12 PM PDT 24 Aug 16 04:36:17 PM PDT 24 190189861 ps
T940 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2518999137 Aug 16 04:36:20 PM PDT 24 Aug 16 04:36:22 PM PDT 24 54813021 ps
T941 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.12953894 Aug 16 04:36:06 PM PDT 24 Aug 16 04:36:08 PM PDT 24 153381991 ps
T942 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.303201810 Aug 16 04:36:35 PM PDT 24 Aug 16 04:36:38 PM PDT 24 509787716 ps
T193 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4039976672 Aug 16 04:36:13 PM PDT 24 Aug 16 04:36:14 PM PDT 24 40922079 ps
T123 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1518536806 Aug 16 04:36:33 PM PDT 24 Aug 16 04:36:35 PM PDT 24 208229628 ps
T943 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1830013293 Aug 16 04:36:14 PM PDT 24 Aug 16 04:36:28 PM PDT 24 1093113970 ps
T944 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2728461227 Aug 16 04:36:28 PM PDT 24 Aug 16 04:36:30 PM PDT 24 107058153 ps
T945 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2828528637 Aug 16 04:36:02 PM PDT 24 Aug 16 04:36:25 PM PDT 24 37307466574 ps
T946 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2784033105 Aug 16 04:36:07 PM PDT 24 Aug 16 04:36:20 PM PDT 24 1507529185 ps
T947 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4233783028 Aug 16 04:36:16 PM PDT 24 Aug 16 04:36:18 PM PDT 24 93472987 ps
T948 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2548565231 Aug 16 04:36:22 PM PDT 24 Aug 16 04:36:24 PM PDT 24 30650180 ps
T949 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3024765045 Aug 16 04:36:15 PM PDT 24 Aug 16 04:36:20 PM PDT 24 163644009 ps
T950 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1589910153 Aug 16 04:36:32 PM PDT 24 Aug 16 04:36:33 PM PDT 24 41985937 ps
T951 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.582791966 Aug 16 04:36:21 PM PDT 24 Aug 16 04:36:31 PM PDT 24 1751220843 ps
T952 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3566402955 Aug 16 04:36:25 PM PDT 24 Aug 16 04:36:27 PM PDT 24 49588733 ps
T953 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.809918517 Aug 16 04:36:10 PM PDT 24 Aug 16 04:36:12 PM PDT 24 26775336 ps
T954 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2557171828 Aug 16 04:36:11 PM PDT 24 Aug 16 04:36:14 PM PDT 24 52121398 ps
T194 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.975950877 Aug 16 04:36:02 PM PDT 24 Aug 16 04:36:04 PM PDT 24 97719688 ps
T955 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1425741635 Aug 16 04:36:07 PM PDT 24 Aug 16 04:36:08 PM PDT 24 71477603 ps
T956 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1953005602 Aug 16 04:36:29 PM PDT 24 Aug 16 04:36:30 PM PDT 24 12971119 ps
T130 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.365579838 Aug 16 04:36:25 PM PDT 24 Aug 16 04:36:27 PM PDT 24 42413168 ps
T957 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.271606531 Aug 16 04:36:16 PM PDT 24 Aug 16 04:36:18 PM PDT 24 48192809 ps
T958 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2368306664 Aug 16 04:36:18 PM PDT 24 Aug 16 04:36:21 PM PDT 24 107155326 ps
T959 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1925364882 Aug 16 04:36:06 PM PDT 24 Aug 16 04:36:10 PM PDT 24 106564068 ps
T960 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.198217996 Aug 16 04:36:23 PM PDT 24 Aug 16 04:36:24 PM PDT 24 310099835 ps
T961 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1653545389 Aug 16 04:36:04 PM PDT 24 Aug 16 04:36:06 PM PDT 24 16355443 ps
T962 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1661497862 Aug 16 04:36:05 PM PDT 24 Aug 16 04:36:07 PM PDT 24 50900082 ps
T195 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1281911511 Aug 16 04:36:04 PM PDT 24 Aug 16 04:36:06 PM PDT 24 222841699 ps
T963 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1122059196 Aug 16 04:36:06 PM PDT 24 Aug 16 04:36:12 PM PDT 24 199667832 ps
T964 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2452125537 Aug 16 04:36:06 PM PDT 24 Aug 16 04:36:08 PM PDT 24 119363650 ps
T965 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1085893126 Aug 16 04:36:06 PM PDT 24 Aug 16 04:36:12 PM PDT 24 2953578430 ps
T129 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2952491465 Aug 16 04:36:28 PM PDT 24 Aug 16 04:36:31 PM PDT 24 151107132 ps
T966 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.842174803 Aug 16 04:36:01 PM PDT 24 Aug 16 04:36:02 PM PDT 24 201695803 ps
T967 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3307920684 Aug 16 04:36:10 PM PDT 24 Aug 16 04:36:13 PM PDT 24 653702789 ps
T196 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3508893128 Aug 16 04:36:08 PM PDT 24 Aug 16 04:36:09 PM PDT 24 11059316 ps
T968 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3253936628 Aug 16 04:36:13 PM PDT 24 Aug 16 04:36:14 PM PDT 24 76462410 ps
T969 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2359289303 Aug 16 04:36:26 PM PDT 24 Aug 16 04:36:27 PM PDT 24 48721190 ps
T970 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3602606389 Aug 16 04:36:05 PM PDT 24 Aug 16 04:36:07 PM PDT 24 646852311 ps
T971 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2078968454 Aug 16 04:36:23 PM PDT 24 Aug 16 04:36:25 PM PDT 24 115447258 ps
T197 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2336172514 Aug 16 04:36:31 PM PDT 24 Aug 16 04:36:32 PM PDT 24 15687090 ps
T972 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2964144655 Aug 16 04:35:57 PM PDT 24 Aug 16 04:35:58 PM PDT 24 28186813 ps
T198 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4067007927 Aug 16 04:36:06 PM PDT 24 Aug 16 04:36:07 PM PDT 24 19407721 ps
T973 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1559118272 Aug 16 04:36:03 PM PDT 24 Aug 16 04:36:16 PM PDT 24 7775311413 ps
T974 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2273415976 Aug 16 04:36:15 PM PDT 24 Aug 16 04:36:16 PM PDT 24 77263923 ps
T975 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.843141539 Aug 16 04:36:04 PM PDT 24 Aug 16 04:36:07 PM PDT 24 446572750 ps
T976 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1953864771 Aug 16 04:36:10 PM PDT 24 Aug 16 04:36:12 PM PDT 24 60008320 ps
T977 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2816780293 Aug 16 04:36:19 PM PDT 24 Aug 16 04:36:20 PM PDT 24 39866107 ps
T978 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.833950694 Aug 16 04:36:20 PM PDT 24 Aug 16 04:36:21 PM PDT 24 24348044 ps
T979 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.802504431 Aug 16 04:36:02 PM PDT 24 Aug 16 04:36:03 PM PDT 24 29404093 ps
T112 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3650504211 Aug 16 04:36:05 PM PDT 24 Aug 16 04:36:08 PM PDT 24 82784490 ps
T980 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.339181776 Aug 16 04:36:03 PM PDT 24 Aug 16 04:36:07 PM PDT 24 133975276 ps
T981 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2072435854 Aug 16 04:36:28 PM PDT 24 Aug 16 04:36:29 PM PDT 24 93557412 ps
T982 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.968655865 Aug 16 04:36:03 PM PDT 24 Aug 16 04:36:05 PM PDT 24 57169123 ps
T983 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.732394809 Aug 16 04:36:08 PM PDT 24 Aug 16 04:36:23 PM PDT 24 1371377512 ps
T984 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2011124356 Aug 16 04:36:07 PM PDT 24 Aug 16 04:36:08 PM PDT 24 43836083 ps
T985 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2963276371 Aug 16 04:36:09 PM PDT 24 Aug 16 04:36:10 PM PDT 24 27560949 ps
T986 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3239257230 Aug 16 04:36:27 PM PDT 24 Aug 16 04:36:29 PM PDT 24 104585067 ps
T124 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3581824517 Aug 16 04:36:01 PM PDT 24 Aug 16 04:36:03 PM PDT 24 157521646 ps
T987 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3326059112 Aug 16 04:36:09 PM PDT 24 Aug 16 04:36:11 PM PDT 24 251946630 ps
T988 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.827672930 Aug 16 04:36:03 PM PDT 24 Aug 16 04:36:15 PM PDT 24 1973754400 ps
T989 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1842267567 Aug 16 04:36:25 PM PDT 24 Aug 16 04:36:27 PM PDT 24 50949812 ps
T990 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3360354360 Aug 16 04:36:04 PM PDT 24 Aug 16 04:36:14 PM PDT 24 3044986132 ps
T991 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2516173512 Aug 16 04:36:13 PM PDT 24 Aug 16 04:36:14 PM PDT 24 123718836 ps
T992 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3895063495 Aug 16 04:36:03 PM PDT 24 Aug 16 04:36:06 PM PDT 24 261179033 ps
T993 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1929743848 Aug 16 04:36:24 PM PDT 24 Aug 16 04:36:26 PM PDT 24 69455527 ps
T117 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4208544699 Aug 16 04:36:18 PM PDT 24 Aug 16 04:36:21 PM PDT 24 93738158 ps
T994 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2631871917 Aug 16 04:36:26 PM PDT 24 Aug 16 04:36:27 PM PDT 24 80077257 ps
T995 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.434860642 Aug 16 04:36:01 PM PDT 24 Aug 16 04:36:02 PM PDT 24 30124427 ps
T128 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.997212196 Aug 16 04:36:47 PM PDT 24 Aug 16 04:36:50 PM PDT 24 447937346 ps
T996 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3608071549 Aug 16 04:36:27 PM PDT 24 Aug 16 04:36:29 PM PDT 24 460430873 ps
T997 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1273900226 Aug 16 04:36:15 PM PDT 24 Aug 16 04:36:16 PM PDT 24 28389022 ps
T998 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.591885995 Aug 16 04:36:32 PM PDT 24 Aug 16 04:36:33 PM PDT 24 38307907 ps
T999 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4000257041 Aug 16 04:36:18 PM PDT 24 Aug 16 04:36:19 PM PDT 24 52612364 ps
T1000 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4196859687 Aug 16 04:36:01 PM PDT 24 Aug 16 04:36:03 PM PDT 24 101793208 ps
T1001 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.461367196 Aug 16 04:36:05 PM PDT 24 Aug 16 04:36:11 PM PDT 24 961379072 ps
T1002 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2250535590 Aug 16 04:36:42 PM PDT 24 Aug 16 04:36:43 PM PDT 24 53671753 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%