Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39678 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
68 |
auto[1] |
1275 |
1 |
|
|
T3 |
11 |
|
T20 |
8 |
|
T22 |
6 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40216 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
737 |
1 |
|
|
T66 |
15 |
|
T67 |
13 |
|
T68 |
18 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39728 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
1225 |
1 |
|
|
T10 |
8 |
|
T13 |
5 |
|
T45 |
16 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39726 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
1227 |
1 |
|
|
T10 |
4 |
|
T13 |
12 |
|
T45 |
7 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39815 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
1138 |
1 |
|
|
T10 |
5 |
|
T13 |
7 |
|
T45 |
9 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
37911 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
no_err_inj |
3042 |
1 |
|
|
T16 |
10 |
|
T5 |
5 |
|
T23 |
14 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39719 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
68 |
auto[1] |
1234 |
1 |
|
|
T3 |
11 |
|
T20 |
14 |
|
T22 |
4 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40178 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
775 |
1 |
|
|
T66 |
16 |
|
T67 |
16 |
|
T68 |
16 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
30759 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
10194 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T18 |
16 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39710 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
1243 |
1 |
|
|
T10 |
8 |
|
T13 |
5 |
|
T45 |
4 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39758 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
1195 |
1 |
|
|
T10 |
9 |
|
T13 |
8 |
|
T45 |
7 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39805 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
1148 |
1 |
|
|
T10 |
7 |
|
T13 |
3 |
|
T45 |
7 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39674 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
70 |
auto[1] |
1279 |
1 |
|
|
T3 |
9 |
|
T20 |
9 |
|
T22 |
7 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39237 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
1716 |
1 |
|
|
T4 |
1 |
|
T11 |
5 |
|
T15 |
4 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40198 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
755 |
1 |
|
|
T66 |
23 |
|
T67 |
11 |
|
T68 |
18 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40187 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
766 |
1 |
|
|
T66 |
18 |
|
T67 |
10 |
|
T68 |
22 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40223 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
730 |
1 |
|
|
T66 |
17 |
|
T67 |
7 |
|
T68 |
11 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39046 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
1907 |
1 |
|
|
T32 |
15 |
|
T20 |
14 |
|
T21 |
15 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37171 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
3782 |
1 |
|
|
T37 |
51 |
|
T58 |
100 |
|
T59 |
94 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39731 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
1222 |
1 |
|
|
T10 |
5 |
|
T13 |
9 |
|
T45 |
7 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39728 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
1225 |
1 |
|
|
T10 |
7 |
|
T13 |
2 |
|
T45 |
8 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39743 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[1] |
1210 |
1 |
|
|
T10 |
9 |
|
T13 |
4 |
|
T45 |
5 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39651 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
69 |
auto[1] |
1302 |
1 |
|
|
T3 |
10 |
|
T20 |
14 |
|
T22 |
11 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
35925 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
69 |
auto[1] |
5028 |
1 |
|
|
T3 |
10 |
|
T33 |
83 |
|
T35 |
64 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37082 |
1 |
|
|
T3 |
79 |
|
T4 |
1 |
|
T10 |
62 |
auto[1] |
3871 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T14 |
78 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40953 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39645 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
67 |
auto[1] |
1308 |
1 |
|
|
T3 |
12 |
|
T20 |
23 |
|
T22 |
12 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39664 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
71 |
auto[1] |
1289 |
1 |
|
|
T3 |
8 |
|
T20 |
8 |
|
T22 |
14 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39722 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
71 |
auto[1] |
1231 |
1 |
|
|
T3 |
8 |
|
T20 |
21 |
|
T22 |
5 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
36975 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[0] |
no_err_inj |
2071 |
1 |
|
|
T16 |
10 |
|
T5 |
5 |
|
T23 |
14 |
auto[1] |
err_inj |
936 |
1 |
|
|
T32 |
8 |
|
T20 |
6 |
|
T21 |
10 |
auto[1] |
no_err_inj |
971 |
1 |
|
|
T32 |
7 |
|
T20 |
8 |
|
T21 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37930 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[0] |
auto[1] |
1116 |
1 |
|
|
T10 |
7 |
|
T13 |
2 |
|
T45 |
8 |
auto[1] |
auto[0] |
1798 |
1 |
|
|
T32 |
15 |
|
T20 |
14 |
|
T21 |
13 |
auto[1] |
auto[1] |
109 |
1 |
|
|
T21 |
2 |
|
T201 |
1 |
|
T65 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37966 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[0] |
auto[1] |
1080 |
1 |
|
|
T10 |
9 |
|
T13 |
8 |
|
T45 |
7 |
auto[1] |
auto[0] |
1792 |
1 |
|
|
T32 |
14 |
|
T20 |
13 |
|
T21 |
15 |
auto[1] |
auto[1] |
115 |
1 |
|
|
T32 |
1 |
|
T20 |
1 |
|
T22 |
4 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37939 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[0] |
auto[1] |
1107 |
1 |
|
|
T10 |
9 |
|
T13 |
4 |
|
T45 |
5 |
auto[1] |
auto[0] |
1804 |
1 |
|
|
T32 |
14 |
|
T20 |
14 |
|
T21 |
13 |
auto[1] |
auto[1] |
103 |
1 |
|
|
T32 |
1 |
|
T21 |
2 |
|
T22 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37917 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[0] |
auto[1] |
1129 |
1 |
|
|
T10 |
4 |
|
T13 |
12 |
|
T45 |
7 |
auto[1] |
auto[0] |
1809 |
1 |
|
|
T32 |
14 |
|
T20 |
12 |
|
T21 |
15 |
auto[1] |
auto[1] |
98 |
1 |
|
|
T32 |
1 |
|
T20 |
2 |
|
T22 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37991 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[0] |
auto[1] |
1055 |
1 |
|
|
T10 |
5 |
|
T13 |
7 |
|
T45 |
9 |
auto[1] |
auto[0] |
1824 |
1 |
|
|
T32 |
15 |
|
T20 |
14 |
|
T21 |
14 |
auto[1] |
auto[1] |
83 |
1 |
|
|
T21 |
1 |
|
T65 |
2 |
|
T99 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37932 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[0] |
auto[1] |
1114 |
1 |
|
|
T10 |
8 |
|
T13 |
5 |
|
T45 |
16 |
auto[1] |
auto[0] |
1796 |
1 |
|
|
T32 |
13 |
|
T20 |
13 |
|
T21 |
14 |
auto[1] |
auto[1] |
111 |
1 |
|
|
T32 |
2 |
|
T20 |
1 |
|
T21 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29984 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
68 |
auto[0] |
auto[1] |
775 |
1 |
|
|
T3 |
11 |
|
T20 |
5 |
|
T42 |
9 |
auto[1] |
auto[0] |
9694 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T18 |
16 |
auto[1] |
auto[1] |
500 |
1 |
|
|
T20 |
3 |
|
T22 |
6 |
|
T87 |
10 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30001 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
68 |
auto[0] |
auto[1] |
758 |
1 |
|
|
T3 |
11 |
|
T20 |
5 |
|
T42 |
12 |
auto[1] |
auto[0] |
9718 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T18 |
16 |
auto[1] |
auto[1] |
476 |
1 |
|
|
T20 |
9 |
|
T22 |
4 |
|
T87 |
10 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29646 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[0] |
auto[1] |
1113 |
1 |
|
|
T11 |
5 |
|
T15 |
4 |
|
T31 |
11 |
auto[1] |
auto[0] |
9591 |
1 |
|
|
T5 |
5 |
|
T18 |
16 |
|
T19 |
15 |
auto[1] |
auto[1] |
603 |
1 |
|
|
T4 |
1 |
|
T202 |
14 |
|
T95 |
11 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29994 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
70 |
auto[0] |
auto[1] |
765 |
1 |
|
|
T3 |
9 |
|
T20 |
5 |
|
T42 |
11 |
auto[1] |
auto[0] |
9680 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T18 |
16 |
auto[1] |
auto[1] |
514 |
1 |
|
|
T20 |
4 |
|
T22 |
7 |
|
T87 |
12 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
26233 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
69 |
auto[0] |
auto[1] |
4526 |
1 |
|
|
T3 |
10 |
|
T33 |
83 |
|
T35 |
64 |
auto[1] |
auto[0] |
9692 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T18 |
16 |
auto[1] |
auto[1] |
502 |
1 |
|
|
T20 |
8 |
|
T22 |
5 |
|
T87 |
8 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30034 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[0] |
auto[1] |
725 |
1 |
|
|
T10 |
7 |
|
T13 |
2 |
|
T45 |
8 |
auto[1] |
auto[0] |
9694 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T18 |
16 |
auto[1] |
auto[1] |
500 |
1 |
|
|
T20 |
6 |
|
T21 |
2 |
|
T43 |
7 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30010 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[0] |
auto[1] |
749 |
1 |
|
|
T10 |
5 |
|
T13 |
9 |
|
T45 |
7 |
auto[1] |
auto[0] |
9721 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T18 |
16 |
auto[1] |
auto[1] |
473 |
1 |
|
|
T20 |
13 |
|
T21 |
1 |
|
T22 |
1 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30030 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[0] |
auto[1] |
729 |
1 |
|
|
T10 |
9 |
|
T13 |
8 |
|
T45 |
7 |
auto[1] |
auto[0] |
9728 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T18 |
16 |
auto[1] |
auto[1] |
466 |
1 |
|
|
T20 |
2 |
|
T22 |
2 |
|
T43 |
6 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30006 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[0] |
auto[1] |
753 |
1 |
|
|
T10 |
8 |
|
T13 |
5 |
|
T45 |
4 |
auto[1] |
auto[0] |
9704 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T18 |
16 |
auto[1] |
auto[1] |
490 |
1 |
|
|
T20 |
10 |
|
T21 |
1 |
|
T43 |
12 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29995 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[0] |
auto[1] |
764 |
1 |
|
|
T10 |
4 |
|
T13 |
12 |
|
T45 |
7 |
auto[1] |
auto[0] |
9731 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T18 |
16 |
auto[1] |
auto[1] |
463 |
1 |
|
|
T20 |
4 |
|
T43 |
8 |
|
T201 |
2 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30024 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[0] |
auto[1] |
735 |
1 |
|
|
T10 |
8 |
|
T13 |
5 |
|
T45 |
16 |
auto[1] |
auto[0] |
9704 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T18 |
16 |
auto[1] |
auto[1] |
490 |
1 |
|
|
T20 |
5 |
|
T21 |
1 |
|
T22 |
1 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30019 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
71 |
auto[0] |
auto[1] |
740 |
1 |
|
|
T3 |
8 |
|
T20 |
10 |
|
T42 |
12 |
auto[1] |
auto[0] |
9703 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T18 |
16 |
auto[1] |
auto[1] |
491 |
1 |
|
|
T20 |
11 |
|
T22 |
5 |
|
T87 |
12 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29956 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
71 |
auto[0] |
auto[1] |
803 |
1 |
|
|
T3 |
8 |
|
T20 |
4 |
|
T42 |
16 |
auto[1] |
auto[0] |
9708 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T18 |
16 |
auto[1] |
auto[1] |
486 |
1 |
|
|
T20 |
4 |
|
T22 |
14 |
|
T87 |
14 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29650 |
1 |
|
|
T1 |
91 |
|
T2 |
57 |
|
T3 |
79 |
auto[0] |
auto[1] |
1109 |
1 |
|
|
T32 |
15 |
|
T20 |
14 |
|
T22 |
11 |
auto[1] |
auto[0] |
9396 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T18 |
16 |
auto[1] |
auto[1] |
798 |
1 |
|
|
T21 |
15 |
|
T22 |
10 |
|
T201 |
13 |