Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60412503

1

T1

71945

T2

27471

T3

32295

auto[1]

1115609

1

T3

693

T4

98

T10

2475

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60433491

1

T1

71945

T2

27471

T3

32592

auto[1]

1094621

1

T3

396

T10

2079

T11

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5087252	1			T1	8372		T2	8739		T3	8140
auto[IdleSt]	16660168	1			T1	9263		T2	5663		T3	6700
auto[ClkMuxSt]	29000	1			T1	91		T2	57		T3	79
auto[CntIncrSt]	28794	1			T1	91		T2	57		T3	79
auto[CntProgSt]	1458498	1			T1	37251		T2	159		T3	531
auto[TransCheckSt]	22736	1			T1	91		T2	57		T3	60
auto[TokenHashSt]	16559059	1			T1	2469		T2	3784		T3	2984
auto[FlashRmaSt]	26960	1			T1	42		T2	42		T3	41
auto[TokenCheck0St]	9998	1			T1	28		T2	22		T3	20
auto[TokenCheck1St]	7177	1			T1	11		T2	10		T3	12
auto[TransProgSt]	347001	1			T3	110		T16	18		T5	72
auto[PostTransSt]	9672624	1			T1	14236		T2	8881		T3	12768
auto[ScrapSt]	121058	1			T16	32		T37	4		T18	415
auto[EscalateSt]	4576523	1			T3	1464		T4	424		T10	5725
auto[InvalidSt]	6919985	1			T10	3407		T13	8229		T45	4379

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1279	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6919985	1			T10	3407		T13	8229		T45	4379
EscalateSt	4576523	1			T3	1464		T4	424		T10	5725
ScrapSt	121058	1			T16	32		T37	4		T18	415
PostTransSt	9672624	1			T1	14236		T2	8881		T3	12768
TransProgSt	347001	1			T3	110		T16	18		T5	72
TokenCheck1St	7177	1			T1	11		T2	10		T3	12
TokenCheck0St	9998	1			T1	28		T2	22		T3	20
FlashRmaSt	26960	1			T1	42		T2	42		T3	41
TokenHashSt	16559059	1			T1	2469		T2	3784		T3	2984
TransCheckSt	22736	1			T1	91		T2	57		T3	60
CntProgSt	1458498	1			T1	37251		T2	159		T3	531
CntIncrSt	28794	1			T1	91		T2	57		T3	79
ClkMuxSt	29000	1			T1	91		T2	57		T3	79
IdleSt	16660168	1			T1	9263		T2	5663		T3	6700
ResetSt	5087252	1			T1	8372		T2	8739		T3	8140
arcs[ResetSt=>IdleSt]	41850	1			T1	92		T2	58		T3	80
arcs[IdleSt=>ScrapSt]	249	1			T16	1		T37	1		T18	1
arcs[IdleSt=>ClkMuxSt]	28827	1			T1	91		T2	57		T3	79
arcs[ClkMuxSt=>CntIncrSt]	28794	1			T1	91		T2	57		T3	79
arcs[CntIncrSt=>PostTransSt]	1290	1			T3	8		T20	8		T22	14
arcs[CntIncrSt=>CntProgSt]	27440	1			T1	91		T2	57		T3	71
arcs[CntProgSt=>PostTransSt]	3731	1			T3	11		T4	1		T11	5
arcs[CntProgSt=>TransCheckSt]	22736	1			T1	91		T2	57		T3	60
arcs[TransCheckSt=>PostTransSt]	3191	1			T1	47		T2	29		T3	8
arcs[TransCheckSt=>TokenHashSt]	19415	1			T1	44		T2	28		T3	52
arcs[TokenHashSt=>PostTransSt]	8524	1			T1	16		T2	6		T3	32
arcs[TokenHashSt=>FlashRmaSt]	10036	1			T1	28		T2	22		T3	20
arcs[FlashRmaSt=>TokenCheck0St]	9998	1			T1	28		T2	22		T3	20
arcs[TokenCheck0St=>PostTransSt]	2759	1			T1	17		T2	12		T3	8
arcs[TokenCheck0St=>TokenCheck1St]	7177	1			T1	11		T2	10		T3	12
arcs[TokenCheck1St=>PostTransSt]	647	1			T1	11		T2	10		T3	2
arcs[TransProgSt=>PostTransSt]	5764	1			T3	10		T16	9		T5	5
arcs[IdleSt=>EscalateSt]	178	1			T59	10		T55	6		T56	9
arcs[ClkMuxSt=>EscalateSt]	33	1			T55	1		T56	2		T57	2
arcs[CntIncrSt=>EscalateSt]	64	1			T37	2		T58	2		T59	1
arcs[CntProgSt=>EscalateSt]	973	1			T37	10		T58	51		T59	31
arcs[TransCheckSt=>EscalateSt]	130	1			T37	1		T58	1		T59	1
arcs[TokenHashSt=>EscalateSt]	855	1			T37	11		T58	14		T59	11
arcs[FlashRmaSt=>EscalateSt]	38	1			T37	2		T59	2		T55	1
arcs[TokenCheck0St=>EscalateSt]	62	1			T37	1		T59	1		T55	1
arcs[TokenCheck1St=>EscalateSt]	25	1			T37	1		T63	1		T64	2
arcs[TransProgSt=>EscalateSt]	741	1			T37	14		T58	21		T59	26
arcs[PostTransSt=>EscalateSt]	4094	1			T3	11		T4	1		T11	5
arcs[InvalidSt=>EscalateSt]	9260	1			T10	46		T13	48		T45	58

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5087075	1			T1	8372		T2	8739		T3	8140
auto[0]	auto[IdleSt]	16660039	1			T1	9263		T2	5663		T3	6700
auto[0]	auto[ClkMuxSt]	28976	1			T1	91		T2	57		T3	79
auto[0]	auto[CntIncrSt]	28753	1			T1	91		T2	57		T3	79
auto[0]	auto[CntProgSt]	1457843	1			T1	37251		T2	159		T3	531
auto[0]	auto[TransCheckSt]	22645	1			T1	91		T2	57		T3	60
auto[0]	auto[TokenHashSt]	16558489	1			T1	2469		T2	3784		T3	2984
auto[0]	auto[FlashRmaSt]	26934	1			T1	42		T2	42		T3	41
auto[0]	auto[TokenCheck0St]	9958	1			T1	28		T2	22		T3	20
auto[0]	auto[TokenCheck1St]	7160	1			T1	11		T2	10		T3	12
auto[0]	auto[TransProgSt]	346530	1			T3	110		T16	18		T5	72
auto[0]	auto[PostTransSt]	9670435	1			T1	14236		T2	8881		T3	12761
auto[0]	auto[ScrapSt]	121007	1			T16	32		T37	4		T18	415
auto[0]	auto[EscalateSt]	3470015	1			T3	778		T4	327		T10	3275
auto[0]	auto[InvalidSt]	6915365	1			T10	3382		T13	8199		T45	4355
auto[1]	auto[ResetSt]	177	1			T37	5		T58	7		T59	5
auto[1]	auto[IdleSt]	129	1			T59	9		T55	4		T56	5
auto[1]	auto[ClkMuxSt]	24	1			T55	1		T56	2		T57	1
auto[1]	auto[CntIncrSt]	41	1			T37	2		T58	1		T56	1
auto[1]	auto[CntProgSt]	655	1			T37	7		T58	35		T59	20
auto[1]	auto[TransCheckSt]	91	1			T37	1		T55	5		T56	4
auto[1]	auto[TokenHashSt]	570	1			T37	9		T58	5		T59	9
auto[1]	auto[FlashRmaSt]	26	1			T37	1		T59	2		T55	1
auto[1]	auto[TokenCheck0St]	40	1			T37	1		T55	1		T156	1
auto[1]	auto[TokenCheck1St]	17	1			T37	1		T63	1		T64	1
auto[1]	auto[TransProgSt]	471	1			T37	6		T58	12		T59	17
auto[1]	auto[PostTransSt]	2189	1			T3	7		T4	1		T11	2
auto[1]	auto[ScrapSt]	51	1			T58	1		T59	3		T55	2
auto[1]	auto[EscalateSt]	1106508	1			T3	686		T4	97		T10	2450
auto[1]	auto[InvalidSt]	4620	1			T10	25		T13	30		T45	24

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5087081	1			T1	8372		T2	8739		T3	8140
auto[0]	auto[IdleSt]	16660057	1			T1	9263		T2	5663		T3	6700
auto[0]	auto[ClkMuxSt]	28979	1			T1	91		T2	57		T3	79
auto[0]	auto[CntIncrSt]	28749	1			T1	91		T2	57		T3	79
auto[0]	auto[CntProgSt]	1457866	1			T1	37251		T2	159		T3	531
auto[0]	auto[TransCheckSt]	22649	1			T1	91		T2	57		T3	60
auto[0]	auto[TokenHashSt]	16558491	1			T1	2469		T2	3784		T3	2984
auto[0]	auto[FlashRmaSt]	26939	1			T1	42		T2	42		T3	41
auto[0]	auto[TokenCheck0St]	9958	1			T1	28		T2	22		T3	20
auto[0]	auto[TokenCheck1St]	7161	1			T1	11		T2	10		T3	12
auto[0]	auto[TransProgSt]	346504	1			T3	110		T16	18		T5	72
auto[0]	auto[PostTransSt]	9670592	1			T1	14236		T2	8881		T3	12764
auto[0]	auto[ScrapSt]	121011	1			T16	32		T37	3		T18	415
auto[0]	auto[EscalateSt]	3490830	1			T3	1072		T4	424		T10	3667
auto[0]	auto[InvalidSt]	6915345	1			T10	3386		T13	8211		T45	4345
auto[1]	auto[ResetSt]	171	1			T37	5		T58	5		T59	4
auto[1]	auto[IdleSt]	111	1			T59	3		T55	4		T56	6
auto[1]	auto[ClkMuxSt]	21	1			T56	1		T57	1		T63	1
auto[1]	auto[CntIncrSt]	45	1			T37	2		T58	2		T59	1
auto[1]	auto[CntProgSt]	632	1			T37	6		T58	26		T59	21
auto[1]	auto[TransCheckSt]	87	1			T37	1		T58	1		T59	1
auto[1]	auto[TokenHashSt]	568	1			T37	6		T58	11		T59	6
auto[1]	auto[FlashRmaSt]	21	1			T37	2		T59	1		T55	1
auto[1]	auto[TokenCheck0St]	40	1			T37	1		T59	1		T55	1
auto[1]	auto[TokenCheck1St]	16	1			T63	1		T64	1		T200	1
auto[1]	auto[TransProgSt]	497	1			T37	11		T58	14		T59	19
auto[1]	auto[PostTransSt]	2032	1			T3	4		T11	3		T15	1
auto[1]	auto[ScrapSt]	47	1			T37	1		T58	2		T59	2
auto[1]	auto[EscalateSt]	1085693	1			T3	392		T10	2058		T11	294
auto[1]	auto[InvalidSt]	4640	1			T10	21		T13	18		T45	34