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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.29 97.99 96.04 93.40 100.00 98.55 98.76 96.29


Total test records in report: 1000
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T811 /workspace/coverage/default/13.lc_ctrl_jtag_errors.3493804289 Aug 17 04:47:13 PM PDT 24 Aug 17 04:47:51 PM PDT 24 24103195164 ps
T812 /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2201370618 Aug 17 04:47:18 PM PDT 24 Aug 17 04:47:25 PM PDT 24 513067001 ps
T813 /workspace/coverage/default/41.lc_ctrl_state_post_trans.2610702179 Aug 17 04:48:17 PM PDT 24 Aug 17 04:48:26 PM PDT 24 73104087 ps
T814 /workspace/coverage/default/31.lc_ctrl_smoke.2445661424 Aug 17 04:47:55 PM PDT 24 Aug 17 04:47:56 PM PDT 24 19108355 ps
T815 /workspace/coverage/default/24.lc_ctrl_prog_failure.3884461041 Aug 17 04:47:52 PM PDT 24 Aug 17 04:47:55 PM PDT 24 143622192 ps
T816 /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2326052112 Aug 17 04:47:57 PM PDT 24 Aug 17 04:48:04 PM PDT 24 567618916 ps
T817 /workspace/coverage/default/17.lc_ctrl_state_post_trans.1130327398 Aug 17 04:47:27 PM PDT 24 Aug 17 04:47:35 PM PDT 24 115956592 ps
T818 /workspace/coverage/default/32.lc_ctrl_sec_mubi.2136332593 Aug 17 04:48:07 PM PDT 24 Aug 17 04:48:26 PM PDT 24 804011648 ps
T819 /workspace/coverage/default/6.lc_ctrl_jtag_access.625534188 Aug 17 04:46:43 PM PDT 24 Aug 17 04:46:54 PM PDT 24 1799096473 ps
T820 /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2608545527 Aug 17 04:47:03 PM PDT 24 Aug 17 04:47:13 PM PDT 24 311212790 ps
T821 /workspace/coverage/default/18.lc_ctrl_security_escalation.4287401853 Aug 17 04:47:27 PM PDT 24 Aug 17 04:47:38 PM PDT 24 308608843 ps
T822 /workspace/coverage/default/8.lc_ctrl_jtag_priority.897299954 Aug 17 04:46:55 PM PDT 24 Aug 17 04:46:58 PM PDT 24 156206098 ps
T823 /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3091166509 Aug 17 04:46:45 PM PDT 24 Aug 17 04:46:54 PM PDT 24 552426318 ps
T824 /workspace/coverage/default/36.lc_ctrl_prog_failure.2041042382 Aug 17 04:48:17 PM PDT 24 Aug 17 04:48:21 PM PDT 24 274921202 ps
T825 /workspace/coverage/default/30.lc_ctrl_stress_all.3422393959 Aug 17 04:48:00 PM PDT 24 Aug 17 04:49:53 PM PDT 24 5087495953 ps
T826 /workspace/coverage/default/19.lc_ctrl_jtag_smoke.61124458 Aug 17 04:47:25 PM PDT 24 Aug 17 04:47:33 PM PDT 24 513260074 ps
T827 /workspace/coverage/default/27.lc_ctrl_prog_failure.3230984611 Aug 17 04:47:48 PM PDT 24 Aug 17 04:47:52 PM PDT 24 97901043 ps
T828 /workspace/coverage/default/14.lc_ctrl_prog_failure.1219920866 Aug 17 04:47:21 PM PDT 24 Aug 17 04:47:23 PM PDT 24 19632995 ps
T829 /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1849882050 Aug 17 04:47:34 PM PDT 24 Aug 17 04:47:38 PM PDT 24 665401096 ps
T830 /workspace/coverage/default/1.lc_ctrl_regwen_during_op.4290262510 Aug 17 04:46:33 PM PDT 24 Aug 17 04:46:52 PM PDT 24 540198942 ps
T831 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.829911145 Aug 17 04:48:08 PM PDT 24 Aug 17 04:48:18 PM PDT 24 226068073 ps
T832 /workspace/coverage/default/15.lc_ctrl_jtag_access.2185055121 Aug 17 04:47:28 PM PDT 24 Aug 17 04:47:34 PM PDT 24 391506699 ps
T833 /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.4221660385 Aug 17 04:48:06 PM PDT 24 Aug 17 04:48:07 PM PDT 24 36284465 ps
T834 /workspace/coverage/default/25.lc_ctrl_alert_test.3062580609 Aug 17 04:47:56 PM PDT 24 Aug 17 04:47:58 PM PDT 24 103176836 ps
T835 /workspace/coverage/default/16.lc_ctrl_security_escalation.1945411795 Aug 17 04:47:21 PM PDT 24 Aug 17 04:47:30 PM PDT 24 407459253 ps
T836 /workspace/coverage/default/45.lc_ctrl_sec_mubi.2935849277 Aug 17 04:48:32 PM PDT 24 Aug 17 04:48:51 PM PDT 24 635741173 ps
T837 /workspace/coverage/default/8.lc_ctrl_state_post_trans.2418724169 Aug 17 04:47:06 PM PDT 24 Aug 17 04:47:09 PM PDT 24 79956380 ps
T838 /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3818246746 Aug 17 04:47:29 PM PDT 24 Aug 17 04:47:43 PM PDT 24 740545661 ps
T839 /workspace/coverage/default/7.lc_ctrl_jtag_errors.2997256722 Aug 17 04:46:56 PM PDT 24 Aug 17 04:48:14 PM PDT 24 2951371199 ps
T840 /workspace/coverage/default/25.lc_ctrl_errors.3611442635 Aug 17 04:47:45 PM PDT 24 Aug 17 04:48:03 PM PDT 24 1659415161 ps
T841 /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3731270930 Aug 17 04:46:29 PM PDT 24 Aug 17 04:47:01 PM PDT 24 2151794088 ps
T842 /workspace/coverage/default/35.lc_ctrl_stress_all.75571326 Aug 17 04:48:17 PM PDT 24 Aug 17 04:49:25 PM PDT 24 6611657997 ps
T843 /workspace/coverage/default/33.lc_ctrl_stress_all.69654063 Aug 17 04:48:08 PM PDT 24 Aug 17 04:50:33 PM PDT 24 15212879002 ps
T844 /workspace/coverage/default/35.lc_ctrl_sec_mubi.2487975473 Aug 17 04:48:19 PM PDT 24 Aug 17 04:48:34 PM PDT 24 1507058712 ps
T845 /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.718453007 Aug 17 04:46:58 PM PDT 24 Aug 17 04:46:59 PM PDT 24 48312674 ps
T846 /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3569987665 Aug 17 04:46:55 PM PDT 24 Aug 17 04:47:05 PM PDT 24 1018324201 ps
T847 /workspace/coverage/default/6.lc_ctrl_state_post_trans.4181084386 Aug 17 04:47:00 PM PDT 24 Aug 17 04:47:03 PM PDT 24 59213543 ps
T848 /workspace/coverage/default/34.lc_ctrl_stress_all.2257495179 Aug 17 04:48:06 PM PDT 24 Aug 17 04:50:45 PM PDT 24 5693306411 ps
T849 /workspace/coverage/default/35.lc_ctrl_security_escalation.2447196168 Aug 17 04:48:19 PM PDT 24 Aug 17 04:48:26 PM PDT 24 247979859 ps
T850 /workspace/coverage/default/47.lc_ctrl_sec_token_mux.931108402 Aug 17 04:48:47 PM PDT 24 Aug 17 04:48:58 PM PDT 24 889001796 ps
T851 /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.316048273 Aug 17 04:48:13 PM PDT 24 Aug 17 04:48:14 PM PDT 24 28408710 ps
T852 /workspace/coverage/default/18.lc_ctrl_sec_token_mux.586813915 Aug 17 04:47:26 PM PDT 24 Aug 17 04:47:36 PM PDT 24 948586414 ps
T166 /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.2377353112 Aug 17 04:47:36 PM PDT 24 Aug 17 04:49:35 PM PDT 24 4117100750 ps
T853 /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3895648916 Aug 17 04:47:30 PM PDT 24 Aug 17 04:47:35 PM PDT 24 233415009 ps
T854 /workspace/coverage/default/8.lc_ctrl_jtag_access.4197054867 Aug 17 04:47:00 PM PDT 24 Aug 17 04:47:01 PM PDT 24 83367272 ps
T198 /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2832923803 Aug 17 04:46:59 PM PDT 24 Aug 17 04:47:00 PM PDT 24 14232400 ps
T94 /workspace/coverage/default/1.lc_ctrl_sec_cm.2875657729 Aug 17 04:46:35 PM PDT 24 Aug 17 04:47:13 PM PDT 24 231548682 ps
T855 /workspace/coverage/default/1.lc_ctrl_stress_all.2119244519 Aug 17 04:46:32 PM PDT 24 Aug 17 04:49:50 PM PDT 24 98831821918 ps
T856 /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3273996969 Aug 17 04:47:27 PM PDT 24 Aug 17 04:47:40 PM PDT 24 1915064161 ps
T857 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.26340069 Aug 17 04:47:04 PM PDT 24 Aug 17 04:48:17 PM PDT 24 5533008484 ps
T858 /workspace/coverage/default/34.lc_ctrl_errors.113485726 Aug 17 04:48:10 PM PDT 24 Aug 17 04:48:39 PM PDT 24 3020816702 ps
T859 /workspace/coverage/default/37.lc_ctrl_sec_token_mux.638623602 Aug 17 04:48:15 PM PDT 24 Aug 17 04:48:28 PM PDT 24 703235570 ps
T860 /workspace/coverage/default/45.lc_ctrl_prog_failure.3847176082 Aug 17 04:48:25 PM PDT 24 Aug 17 04:48:27 PM PDT 24 81215934 ps
T861 /workspace/coverage/default/7.lc_ctrl_jtag_priority.2522682316 Aug 17 04:46:57 PM PDT 24 Aug 17 04:47:05 PM PDT 24 1702781109 ps
T862 /workspace/coverage/default/23.lc_ctrl_prog_failure.1180703245 Aug 17 04:47:43 PM PDT 24 Aug 17 04:47:45 PM PDT 24 67790567 ps
T863 /workspace/coverage/default/18.lc_ctrl_stress_all.2562862484 Aug 17 04:47:31 PM PDT 24 Aug 17 04:49:07 PM PDT 24 6649790521 ps
T864 /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3492453935 Aug 17 04:46:32 PM PDT 24 Aug 17 04:46:38 PM PDT 24 283834595 ps
T865 /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1675525249 Aug 17 04:46:44 PM PDT 24 Aug 17 04:47:28 PM PDT 24 1500106054 ps
T866 /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3580845861 Aug 17 04:48:46 PM PDT 24 Aug 17 04:48:57 PM PDT 24 1866224041 ps
T867 /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1141671808 Aug 17 04:48:08 PM PDT 24 Aug 17 04:48:09 PM PDT 24 11171833 ps
T868 /workspace/coverage/default/11.lc_ctrl_stress_all.1465161322 Aug 17 04:47:10 PM PDT 24 Aug 17 04:47:36 PM PDT 24 2186767265 ps
T869 /workspace/coverage/default/12.lc_ctrl_prog_failure.766047719 Aug 17 04:47:09 PM PDT 24 Aug 17 04:47:12 PM PDT 24 104299464 ps
T870 /workspace/coverage/default/21.lc_ctrl_errors.4284430027 Aug 17 04:47:45 PM PDT 24 Aug 17 04:48:00 PM PDT 24 3356081103 ps
T871 /workspace/coverage/default/47.lc_ctrl_state_failure.3019757424 Aug 17 04:48:26 PM PDT 24 Aug 17 04:48:53 PM PDT 24 2043220466 ps
T872 /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3930689536 Aug 17 04:48:24 PM PDT 24 Aug 17 04:50:02 PM PDT 24 2464384679 ps
T105 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3158748916 Aug 17 04:34:52 PM PDT 24 Aug 17 04:34:54 PM PDT 24 138245517 ps
T107 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3724733322 Aug 17 04:35:05 PM PDT 24 Aug 17 04:35:06 PM PDT 24 20080459 ps
T106 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3825991040 Aug 17 04:35:17 PM PDT 24 Aug 17 04:35:19 PM PDT 24 56566349 ps
T111 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1563582893 Aug 17 04:34:59 PM PDT 24 Aug 17 04:35:10 PM PDT 24 443627747 ps
T148 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3659364834 Aug 17 04:35:01 PM PDT 24 Aug 17 04:35:03 PM PDT 24 58816178 ps
T112 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.113051331 Aug 17 04:34:59 PM PDT 24 Aug 17 04:35:00 PM PDT 24 137926395 ps
T149 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2505783454 Aug 17 04:34:48 PM PDT 24 Aug 17 04:34:49 PM PDT 24 35876220 ps
T150 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3769772200 Aug 17 04:34:35 PM PDT 24 Aug 17 04:34:36 PM PDT 24 52444616 ps
T102 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.860288436 Aug 17 04:35:06 PM PDT 24 Aug 17 04:35:08 PM PDT 24 136118122 ps
T873 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.38920771 Aug 17 04:34:46 PM PDT 24 Aug 17 04:34:47 PM PDT 24 32905651 ps
T874 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2098183483 Aug 17 04:34:50 PM PDT 24 Aug 17 04:34:52 PM PDT 24 18273461 ps
T103 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1720365622 Aug 17 04:35:07 PM PDT 24 Aug 17 04:35:11 PM PDT 24 105050099 ps
T110 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1559131809 Aug 17 04:35:00 PM PDT 24 Aug 17 04:35:03 PM PDT 24 36926291 ps
T134 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.576547038 Aug 17 04:34:42 PM PDT 24 Aug 17 04:34:44 PM PDT 24 438398063 ps
T180 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.91489286 Aug 17 04:34:46 PM PDT 24 Aug 17 04:34:47 PM PDT 24 29732057 ps
T190 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1178460343 Aug 17 04:34:51 PM PDT 24 Aug 17 04:34:52 PM PDT 24 69981968 ps
T133 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.326653631 Aug 17 04:34:57 PM PDT 24 Aug 17 04:35:04 PM PDT 24 413838460 ps
T104 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1569330333 Aug 17 04:35:09 PM PDT 24 Aug 17 04:35:11 PM PDT 24 224132972 ps
T113 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.126697166 Aug 17 04:35:08 PM PDT 24 Aug 17 04:35:11 PM PDT 24 380927533 ps
T875 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3192111759 Aug 17 04:34:44 PM PDT 24 Aug 17 04:34:45 PM PDT 24 16698723 ps
T135 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2709602617 Aug 17 04:35:01 PM PDT 24 Aug 17 04:35:21 PM PDT 24 1704452371 ps
T181 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.686267349 Aug 17 04:35:07 PM PDT 24 Aug 17 04:35:08 PM PDT 24 14648028 ps
T169 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3091495961 Aug 17 04:35:07 PM PDT 24 Aug 17 04:35:08 PM PDT 24 25066396 ps
T876 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.22204486 Aug 17 04:35:06 PM PDT 24 Aug 17 04:35:07 PM PDT 24 42752259 ps
T131 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3854003694 Aug 17 04:34:58 PM PDT 24 Aug 17 04:35:04 PM PDT 24 657308174 ps
T877 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3309244584 Aug 17 04:34:36 PM PDT 24 Aug 17 04:34:43 PM PDT 24 2010271182 ps
T132 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1272915611 Aug 17 04:34:48 PM PDT 24 Aug 17 04:34:51 PM PDT 24 344238426 ps
T878 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1662189038 Aug 17 04:35:04 PM PDT 24 Aug 17 04:35:05 PM PDT 24 49608309 ps
T117 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1405106374 Aug 17 04:34:53 PM PDT 24 Aug 17 04:34:58 PM PDT 24 1061506777 ps
T191 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1063071249 Aug 17 04:35:07 PM PDT 24 Aug 17 04:35:08 PM PDT 24 35240056 ps
T879 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3873426728 Aug 17 04:34:34 PM PDT 24 Aug 17 04:34:48 PM PDT 24 6165406868 ps
T880 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.410964225 Aug 17 04:34:37 PM PDT 24 Aug 17 04:34:40 PM PDT 24 381678350 ps
T151 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2926085165 Aug 17 04:34:34 PM PDT 24 Aug 17 04:34:36 PM PDT 24 81888274 ps
T881 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1344128694 Aug 17 04:35:06 PM PDT 24 Aug 17 04:35:08 PM PDT 24 19908057 ps
T192 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3557964663 Aug 17 04:35:05 PM PDT 24 Aug 17 04:35:06 PM PDT 24 77400339 ps
T882 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1522731691 Aug 17 04:35:17 PM PDT 24 Aug 17 04:35:19 PM PDT 24 364645072 ps
T883 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3353740693 Aug 17 04:34:36 PM PDT 24 Aug 17 04:34:39 PM PDT 24 477030448 ps
T108 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1455693156 Aug 17 04:34:52 PM PDT 24 Aug 17 04:34:54 PM PDT 24 109944251 ps
T884 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.917750312 Aug 17 04:35:08 PM PDT 24 Aug 17 04:35:09 PM PDT 24 51463406 ps
T885 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1244312746 Aug 17 04:34:45 PM PDT 24 Aug 17 04:34:47 PM PDT 24 50763615 ps
T886 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1732898236 Aug 17 04:34:50 PM PDT 24 Aug 17 04:34:51 PM PDT 24 54107539 ps
T887 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3601284690 Aug 17 04:35:00 PM PDT 24 Aug 17 04:35:02 PM PDT 24 17398656 ps
T888 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1615003679 Aug 17 04:34:58 PM PDT 24 Aug 17 04:35:01 PM PDT 24 1521049817 ps
T889 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3498090604 Aug 17 04:34:56 PM PDT 24 Aug 17 04:34:57 PM PDT 24 67761981 ps
T890 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3945114190 Aug 17 04:34:48 PM PDT 24 Aug 17 04:34:54 PM PDT 24 569522004 ps
T193 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3254618643 Aug 17 04:34:36 PM PDT 24 Aug 17 04:34:37 PM PDT 24 23611571 ps
T152 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.964935870 Aug 17 04:35:01 PM PDT 24 Aug 17 04:35:04 PM PDT 24 753212454 ps
T153 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1145963675 Aug 17 04:35:11 PM PDT 24 Aug 17 04:35:12 PM PDT 24 15513425 ps
T891 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4065493199 Aug 17 04:34:43 PM PDT 24 Aug 17 04:34:48 PM PDT 24 3968181543 ps
T892 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2955744250 Aug 17 04:34:37 PM PDT 24 Aug 17 04:34:39 PM PDT 24 98440224 ps
T893 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.339061428 Aug 17 04:34:51 PM PDT 24 Aug 17 04:34:53 PM PDT 24 30843269 ps
T154 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2448762136 Aug 17 04:34:49 PM PDT 24 Aug 17 04:34:50 PM PDT 24 27656974 ps
T109 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1473516403 Aug 17 04:35:04 PM PDT 24 Aug 17 04:35:08 PM PDT 24 185769153 ps
T894 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3702873285 Aug 17 04:34:41 PM PDT 24 Aug 17 04:34:50 PM PDT 24 479259013 ps
T895 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3488359554 Aug 17 04:34:33 PM PDT 24 Aug 17 04:34:48 PM PDT 24 2344764203 ps
T127 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2162851514 Aug 17 04:34:49 PM PDT 24 Aug 17 04:34:53 PM PDT 24 277026837 ps
T896 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3765725123 Aug 17 04:35:04 PM PDT 24 Aug 17 04:35:05 PM PDT 24 75270744 ps
T897 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.441080468 Aug 17 04:35:00 PM PDT 24 Aug 17 04:35:02 PM PDT 24 249856646 ps
T182 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.671998423 Aug 17 04:34:46 PM PDT 24 Aug 17 04:34:46 PM PDT 24 17579306 ps
T898 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.876590005 Aug 17 04:34:51 PM PDT 24 Aug 17 04:35:12 PM PDT 24 827304643 ps
T194 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.256005304 Aug 17 04:35:03 PM PDT 24 Aug 17 04:35:05 PM PDT 24 25155487 ps
T899 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3504766493 Aug 17 04:35:02 PM PDT 24 Aug 17 04:35:04 PM PDT 24 87060459 ps
T124 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3529374409 Aug 17 04:34:36 PM PDT 24 Aug 17 04:34:40 PM PDT 24 413277616 ps
T183 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2969715153 Aug 17 04:34:58 PM PDT 24 Aug 17 04:34:59 PM PDT 24 56681747 ps
T900 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2973950583 Aug 17 04:34:35 PM PDT 24 Aug 17 04:34:36 PM PDT 24 13445787 ps
T115 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.361990408 Aug 17 04:34:58 PM PDT 24 Aug 17 04:35:02 PM PDT 24 130841523 ps
T901 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1295782459 Aug 17 04:34:34 PM PDT 24 Aug 17 04:34:35 PM PDT 24 167650135 ps
T902 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2130857612 Aug 17 04:34:34 PM PDT 24 Aug 17 04:35:09 PM PDT 24 1515469770 ps
T903 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2090271558 Aug 17 04:34:44 PM PDT 24 Aug 17 04:34:46 PM PDT 24 157473966 ps
T904 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1300171519 Aug 17 04:34:52 PM PDT 24 Aug 17 04:34:53 PM PDT 24 42618640 ps
T905 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4279858612 Aug 17 04:34:50 PM PDT 24 Aug 17 04:34:53 PM PDT 24 265065468 ps
T906 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2538709438 Aug 17 04:34:45 PM PDT 24 Aug 17 04:34:48 PM PDT 24 385892474 ps
T907 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2079457022 Aug 17 04:34:58 PM PDT 24 Aug 17 04:34:59 PM PDT 24 17405324 ps
T908 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4270709606 Aug 17 04:34:43 PM PDT 24 Aug 17 04:34:45 PM PDT 24 318779996 ps
T909 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1850830566 Aug 17 04:34:54 PM PDT 24 Aug 17 04:34:55 PM PDT 24 22562963 ps
T910 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3351122062 Aug 17 04:35:08 PM PDT 24 Aug 17 04:35:12 PM PDT 24 111962665 ps
T911 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2630757912 Aug 17 04:34:58 PM PDT 24 Aug 17 04:35:19 PM PDT 24 3577478646 ps
T912 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.637999787 Aug 17 04:35:00 PM PDT 24 Aug 17 04:35:01 PM PDT 24 100259189 ps
T913 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3427426907 Aug 17 04:34:35 PM PDT 24 Aug 17 04:34:36 PM PDT 24 18912963 ps
T914 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3357824628 Aug 17 04:35:02 PM PDT 24 Aug 17 04:35:03 PM PDT 24 32674987 ps
T915 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3893900677 Aug 17 04:34:58 PM PDT 24 Aug 17 04:35:00 PM PDT 24 450133669 ps
T916 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4175921036 Aug 17 04:34:45 PM PDT 24 Aug 17 04:34:47 PM PDT 24 32797562 ps
T917 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1961811226 Aug 17 04:35:12 PM PDT 24 Aug 17 04:35:13 PM PDT 24 20264963 ps
T184 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2320013413 Aug 17 04:35:05 PM PDT 24 Aug 17 04:35:06 PM PDT 24 23536312 ps
T185 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2521851220 Aug 17 04:34:40 PM PDT 24 Aug 17 04:34:42 PM PDT 24 74114823 ps
T918 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.170976324 Aug 17 04:35:05 PM PDT 24 Aug 17 04:35:07 PM PDT 24 25191877 ps
T919 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1449943724 Aug 17 04:35:01 PM PDT 24 Aug 17 04:35:02 PM PDT 24 60002532 ps
T920 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.927114039 Aug 17 04:34:51 PM PDT 24 Aug 17 04:34:54 PM PDT 24 44515039 ps
T125 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1408744611 Aug 17 04:35:05 PM PDT 24 Aug 17 04:35:07 PM PDT 24 135810016 ps
T921 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3796722581 Aug 17 04:35:05 PM PDT 24 Aug 17 04:35:07 PM PDT 24 75090106 ps
T922 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3683504189 Aug 17 04:34:59 PM PDT 24 Aug 17 04:35:00 PM PDT 24 36809201 ps
T923 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3539058214 Aug 17 04:34:42 PM PDT 24 Aug 17 04:34:47 PM PDT 24 179192649 ps
T924 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2341261489 Aug 17 04:35:06 PM PDT 24 Aug 17 04:35:09 PM PDT 24 33925901 ps
T925 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.567085162 Aug 17 04:35:08 PM PDT 24 Aug 17 04:35:10 PM PDT 24 33702439 ps
T926 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2021608193 Aug 17 04:34:50 PM PDT 24 Aug 17 04:34:51 PM PDT 24 60525142 ps
T927 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3227175781 Aug 17 04:34:43 PM PDT 24 Aug 17 04:34:44 PM PDT 24 60349804 ps
T928 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4069493935 Aug 17 04:35:05 PM PDT 24 Aug 17 04:35:07 PM PDT 24 420740720 ps
T929 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1696891947 Aug 17 04:34:52 PM PDT 24 Aug 17 04:34:53 PM PDT 24 169382236 ps
T128 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2415934831 Aug 17 04:34:42 PM PDT 24 Aug 17 04:34:44 PM PDT 24 62838433 ps
T118 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3882149332 Aug 17 04:34:55 PM PDT 24 Aug 17 04:34:58 PM PDT 24 83891726 ps
T930 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1649570597 Aug 17 04:34:57 PM PDT 24 Aug 17 04:34:59 PM PDT 24 97020903 ps
T931 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2629598239 Aug 17 04:35:05 PM PDT 24 Aug 17 04:35:09 PM PDT 24 118388978 ps
T116 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.998590324 Aug 17 04:34:42 PM PDT 24 Aug 17 04:34:45 PM PDT 24 75820380 ps
T932 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1743071975 Aug 17 04:34:58 PM PDT 24 Aug 17 04:35:09 PM PDT 24 420135589 ps
T186 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1326388259 Aug 17 04:35:04 PM PDT 24 Aug 17 04:35:06 PM PDT 24 16556474 ps
T933 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2370342130 Aug 17 04:35:00 PM PDT 24 Aug 17 04:35:01 PM PDT 24 27279109 ps
T934 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.816295110 Aug 17 04:34:44 PM PDT 24 Aug 17 04:34:48 PM PDT 24 204341050 ps
T935 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2033535343 Aug 17 04:34:55 PM PDT 24 Aug 17 04:34:56 PM PDT 24 135801758 ps
T119 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3647463421 Aug 17 04:35:04 PM PDT 24 Aug 17 04:35:06 PM PDT 24 44124546 ps
T936 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1955755700 Aug 17 04:34:50 PM PDT 24 Aug 17 04:34:57 PM PDT 24 383216618 ps
T129 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2645655211 Aug 17 04:35:05 PM PDT 24 Aug 17 04:35:07 PM PDT 24 69992440 ps
T937 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1637955254 Aug 17 04:35:09 PM PDT 24 Aug 17 04:35:11 PM PDT 24 46482675 ps
T938 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.655851077 Aug 17 04:34:41 PM PDT 24 Aug 17 04:34:44 PM PDT 24 333221288 ps
T939 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3058992534 Aug 17 04:34:41 PM PDT 24 Aug 17 04:34:45 PM PDT 24 110400883 ps
T940 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3595005667 Aug 17 04:34:52 PM PDT 24 Aug 17 04:34:55 PM PDT 24 288598832 ps
T941 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3292872761 Aug 17 04:34:41 PM PDT 24 Aug 17 04:34:43 PM PDT 24 41808236 ps
T122 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1427331984 Aug 17 04:35:07 PM PDT 24 Aug 17 04:35:11 PM PDT 24 172386934 ps
T942 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2125995711 Aug 17 04:34:34 PM PDT 24 Aug 17 04:34:36 PM PDT 24 331665934 ps
T943 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.341855788 Aug 17 04:35:13 PM PDT 24 Aug 17 04:35:14 PM PDT 24 57205424 ps
T944 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1746335100 Aug 17 04:34:57 PM PDT 24 Aug 17 04:34:58 PM PDT 24 29444044 ps
T945 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3633257860 Aug 17 04:34:42 PM PDT 24 Aug 17 04:34:43 PM PDT 24 38866016 ps
T946 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.10322645 Aug 17 04:34:57 PM PDT 24 Aug 17 04:34:59 PM PDT 24 126597290 ps
T947 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1250838836 Aug 17 04:34:58 PM PDT 24 Aug 17 04:35:01 PM PDT 24 880184230 ps
T948 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2707128649 Aug 17 04:34:50 PM PDT 24 Aug 17 04:34:51 PM PDT 24 69628962 ps
T949 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2400412191 Aug 17 04:35:05 PM PDT 24 Aug 17 04:35:06 PM PDT 24 71921212 ps
T120 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2626096930 Aug 17 04:34:59 PM PDT 24 Aug 17 04:35:02 PM PDT 24 117290306 ps
T187 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3607460029 Aug 17 04:34:54 PM PDT 24 Aug 17 04:34:55 PM PDT 24 25761265 ps
T950 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1476098439 Aug 17 04:34:44 PM PDT 24 Aug 17 04:34:45 PM PDT 24 72505065 ps
T951 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1180964195 Aug 17 04:34:49 PM PDT 24 Aug 17 04:34:50 PM PDT 24 42346557 ps
T952 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.433064849 Aug 17 04:34:37 PM PDT 24 Aug 17 04:34:39 PM PDT 24 18412311 ps
T953 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4158385331 Aug 17 04:34:42 PM PDT 24 Aug 17 04:34:43 PM PDT 24 68020731 ps
T954 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2540685643 Aug 17 04:35:05 PM PDT 24 Aug 17 04:35:07 PM PDT 24 27677891 ps
T130 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1507658799 Aug 17 04:35:06 PM PDT 24 Aug 17 04:35:09 PM PDT 24 394906213 ps
T955 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1505622443 Aug 17 04:34:49 PM PDT 24 Aug 17 04:34:51 PM PDT 24 93744854 ps
T956 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1082414711 Aug 17 04:34:36 PM PDT 24 Aug 17 04:34:37 PM PDT 24 31294754 ps
T957 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3120877377 Aug 17 04:34:41 PM PDT 24 Aug 17 04:34:52 PM PDT 24 1114193104 ps
T958 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1329432518 Aug 17 04:34:35 PM PDT 24 Aug 17 04:34:37 PM PDT 24 36518384 ps
T121 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2209250702 Aug 17 04:35:06 PM PDT 24 Aug 17 04:35:09 PM PDT 24 271632335 ps
T959 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3638540373 Aug 17 04:34:50 PM PDT 24 Aug 17 04:34:52 PM PDT 24 255780047 ps
T960 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2797515295 Aug 17 04:35:09 PM PDT 24 Aug 17 04:35:12 PM PDT 24 67464092 ps
T961 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1089125150 Aug 17 04:34:57 PM PDT 24 Aug 17 04:34:59 PM PDT 24 185602443 ps
T962 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.770471237 Aug 17 04:35:00 PM PDT 24 Aug 17 04:35:02 PM PDT 24 37916891 ps
T963 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.892585489 Aug 17 04:35:07 PM PDT 24 Aug 17 04:35:08 PM PDT 24 22405599 ps
T964 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1433102205 Aug 17 04:34:51 PM PDT 24 Aug 17 04:35:02 PM PDT 24 2024894475 ps
T114 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3572675506 Aug 17 04:34:51 PM PDT 24 Aug 17 04:34:55 PM PDT 24 101467507 ps
T965 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2747337457 Aug 17 04:34:49 PM PDT 24 Aug 17 04:34:51 PM PDT 24 148675024 ps
T966 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2403906220 Aug 17 04:34:52 PM PDT 24 Aug 17 04:34:53 PM PDT 24 139712946 ps
T967 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2232509465 Aug 17 04:34:56 PM PDT 24 Aug 17 04:34:57 PM PDT 24 486149370 ps
T968 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3401156233 Aug 17 04:34:58 PM PDT 24 Aug 17 04:35:00 PM PDT 24 42831648 ps
T188 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2116716024 Aug 17 04:34:54 PM PDT 24 Aug 17 04:34:55 PM PDT 24 31210079 ps
T969 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.503281561 Aug 17 04:34:52 PM PDT 24 Aug 17 04:34:59 PM PDT 24 272592498 ps
T970 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.601983413 Aug 17 04:34:41 PM PDT 24 Aug 17 04:34:50 PM PDT 24 3023916138 ps
T971 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1120677805 Aug 17 04:34:48 PM PDT 24 Aug 17 04:34:49 PM PDT 24 157968637 ps
T972 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3911325321 Aug 17 04:35:13 PM PDT 24 Aug 17 04:35:14 PM PDT 24 74866885 ps
T973 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3540642590 Aug 17 04:34:51 PM PDT 24 Aug 17 04:35:07 PM PDT 24 2974804103 ps
T974 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3632370266 Aug 17 04:35:09 PM PDT 24 Aug 17 04:35:10 PM PDT 24 17486549 ps
T975 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2659506807 Aug 17 04:35:06 PM PDT 24 Aug 17 04:35:08 PM PDT 24 58372442 ps
T126 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1795147673 Aug 17 04:35:04 PM PDT 24 Aug 17 04:35:08 PM PDT 24 381971983 ps
T976 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1685153851 Aug 17 04:34:52 PM PDT 24 Aug 17 04:34:54 PM PDT 24 114251123 ps
T977 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.319517631 Aug 17 04:34:40 PM PDT 24 Aug 17 04:34:43 PM PDT 24 576950230 ps
T978 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.315685585 Aug 17 04:34:55 PM PDT 24 Aug 17 04:34:58 PM PDT 24 572087033 ps
T979 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.386702642 Aug 17 04:34:49 PM PDT 24 Aug 17 04:34:53 PM PDT 24 449945635 ps
T980 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.223427473 Aug 17 04:34:43 PM PDT 24 Aug 17 04:34:44 PM PDT 24 43867695 ps
T981 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1884564022 Aug 17 04:34:42 PM PDT 24 Aug 17 04:34:43 PM PDT 24 39281467 ps
T982 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3789693389 Aug 17 04:35:00 PM PDT 24 Aug 17 04:35:05 PM PDT 24 468965089 ps
T983 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4035528797 Aug 17 04:34:51 PM PDT 24 Aug 17 04:34:52 PM PDT 24 46601610 ps
T984 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3125177207 Aug 17 04:34:43 PM PDT 24 Aug 17 04:34:44 PM PDT 24 82662870 ps
T985 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.505028689 Aug 17 04:35:05 PM PDT 24 Aug 17 04:35:09 PM PDT 24 147029873 ps
T986 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3693244499 Aug 17 04:34:44 PM PDT 24 Aug 17 04:34:46 PM PDT 24 89129870 ps
T189 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.509663657 Aug 17 04:35:12 PM PDT 24 Aug 17 04:35:13 PM PDT 24 15156187 ps
T987 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.683394573 Aug 17 04:35:04 PM PDT 24 Aug 17 04:35:06 PM PDT 24 112508991 ps
T988 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1700657128 Aug 17 04:34:42 PM PDT 24 Aug 17 04:34:43 PM PDT 24 12766705 ps
T989 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1834833532 Aug 17 04:34:57 PM PDT 24 Aug 17 04:34:58 PM PDT 24 23700516 ps
T990 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.683781724 Aug 17 04:34:35 PM PDT 24 Aug 17 04:34:37 PM PDT 24 50584402 ps
T123 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4084111215 Aug 17 04:35:01 PM PDT 24 Aug 17 04:35:04 PM PDT 24 407102554 ps
T991 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2976359877 Aug 17 04:34:53 PM PDT 24 Aug 17 04:34:55 PM PDT 24 357527255 ps
T992 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4037088688 Aug 17 04:34:52 PM PDT 24 Aug 17 04:34:57 PM PDT 24 1172890299 ps
T993 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3182013148 Aug 17 04:34:36 PM PDT 24 Aug 17 04:34:38 PM PDT 24 551134717 ps
T994 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2541224960 Aug 17 04:35:00 PM PDT 24 Aug 17 04:35:01 PM PDT 24 27864274 ps
T995 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2622822039 Aug 17 04:34:54 PM PDT 24 Aug 17 04:34:56 PM PDT 24 25799522 ps
T996 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3694055438 Aug 17 04:34:52 PM PDT 24 Aug 17 04:35:00 PM PDT 24 1960153712 ps
T997 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4079418727 Aug 17 04:34:58 PM PDT 24 Aug 17 04:35:00 PM PDT 24 20449218 ps
T998 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.532596545 Aug 17 04:34:50 PM PDT 24 Aug 17 04:34:53 PM PDT 24 786641814 ps
T999 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.91280347 Aug 17 04:35:05 PM PDT 24 Aug 17 04:35:06 PM PDT 24 45563740 ps
T1000 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.4081728547 Aug 17 04:35:00 PM PDT 24 Aug 17 04:35:03 PM PDT 24 451771443 ps

Test location /workspace/coverage/default/4.lc_ctrl_errors.3704972961
Short name T3
Test name
Test status
Simulation time 343662267 ps
CPU time 11.6 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:46:47 PM PDT 24
Peak memory 218256 kb
Host smart-5aaabfc1-a37e-4a57-babf-301b4b958470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704972961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3704972961
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2263667366
Short name T22
Test name
Test status
Simulation time 2693449434 ps
CPU time 72.53 seconds
Started Aug 17 04:47:56 PM PDT 24
Finished Aug 17 04:49:08 PM PDT 24
Peak memory 275616 kb
Host smart-f59e4d08-c1b7-4e20-ab79-45bd486133d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263667366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2263667366
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1192531793
Short name T37
Test name
Test status
Simulation time 974410979 ps
CPU time 5.34 seconds
Started Aug 17 04:48:14 PM PDT 24
Finished Aug 17 04:48:19 PM PDT 24
Peak memory 218328 kb
Host smart-21f848b6-9d8f-4d88-8db0-c6d520ccceb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192531793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1192531793
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1858581578
Short name T245
Test name
Test status
Simulation time 781320051 ps
CPU time 11.53 seconds
Started Aug 17 04:47:28 PM PDT 24
Finished Aug 17 04:47:39 PM PDT 24
Peak memory 218888 kb
Host smart-f9ff1504-5604-4db5-91e8-39000b138091
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858581578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1858581578
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2512393737
Short name T13
Test name
Test status
Simulation time 473542412 ps
CPU time 23.53 seconds
Started Aug 17 04:47:19 PM PDT 24
Finished Aug 17 04:47:43 PM PDT 24
Peak memory 247224 kb
Host smart-afcfa654-85d8-47b4-b769-1007f3584696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512393737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2512393737
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.267297684
Short name T93
Test name
Test status
Simulation time 4729184004 ps
CPU time 121.83 seconds
Started Aug 17 04:46:32 PM PDT 24
Finished Aug 17 04:48:34 PM PDT 24
Peak memory 267432 kb
Host smart-d02b96f0-7162-4db8-9e17-dff979a5c24a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=267297684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.267297684
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3167038393
Short name T200
Test name
Test status
Simulation time 3645434494 ps
CPU time 6.4 seconds
Started Aug 17 04:47:53 PM PDT 24
Finished Aug 17 04:48:00 PM PDT 24
Peak memory 225480 kb
Host smart-06bd3429-f3a4-43b5-8003-6bc2fb8ebb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167038393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3167038393
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.527473432
Short name T40
Test name
Test status
Simulation time 32292249 ps
CPU time 0.76 seconds
Started Aug 17 04:47:46 PM PDT 24
Finished Aug 17 04:47:51 PM PDT 24
Peak memory 208852 kb
Host smart-7b943196-57a9-4a8e-9380-0cea764ff287
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527473432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct
rl_volatile_unlock_smoke.527473432
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3158748916
Short name T105
Test name
Test status
Simulation time 138245517 ps
CPU time 1.27 seconds
Started Aug 17 04:34:52 PM PDT 24
Finished Aug 17 04:34:54 PM PDT 24
Peak memory 218440 kb
Host smart-d9a01255-428a-4fb9-ab24-2490de72d275
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158748916 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3158748916
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1238518594
Short name T6
Test name
Test status
Simulation time 7869866239 ps
CPU time 10.12 seconds
Started Aug 17 04:47:58 PM PDT 24
Finished Aug 17 04:48:08 PM PDT 24
Peak memory 217820 kb
Host smart-e042b1e2-3ab5-4a20-bb6b-2ac496715ca1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238518594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1238518594
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1870737795
Short name T60
Test name
Test status
Simulation time 222163722 ps
CPU time 35.03 seconds
Started Aug 17 04:46:36 PM PDT 24
Finished Aug 17 04:47:11 PM PDT 24
Peak memory 270984 kb
Host smart-f3c38e27-06f6-4c78-96e2-451d6fca0703
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870737795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1870737795
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2350237830
Short name T1
Test name
Test status
Simulation time 5534346075 ps
CPU time 13.33 seconds
Started Aug 17 04:47:34 PM PDT 24
Finished Aug 17 04:47:48 PM PDT 24
Peak memory 226044 kb
Host smart-2a20b8c1-07a6-41fa-a2e5-97ec74459624
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350237830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2350237830
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2222183723
Short name T162
Test name
Test status
Simulation time 50272833965 ps
CPU time 746.76 seconds
Started Aug 17 04:47:23 PM PDT 24
Finished Aug 17 04:59:50 PM PDT 24
Peak memory 267164 kb
Host smart-379df62c-3654-432d-b26f-6852017d0fb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222183723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2222183723
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.361990408
Short name T115
Test name
Test status
Simulation time 130841523 ps
CPU time 4.74 seconds
Started Aug 17 04:34:58 PM PDT 24
Finished Aug 17 04:35:02 PM PDT 24
Peak memory 218228 kb
Host smart-e810ccf6-7848-43f9-89b1-b0bd0332cf1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361990408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.361990408
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.4293731151
Short name T161
Test name
Test status
Simulation time 1440740076 ps
CPU time 9.91 seconds
Started Aug 17 04:48:53 PM PDT 24
Finished Aug 17 04:49:03 PM PDT 24
Peak memory 218304 kb
Host smart-81536387-b2bc-4983-b305-301f43d6fb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293731151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.4293731151
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1244030511
Short name T12
Test name
Test status
Simulation time 41358476 ps
CPU time 0.96 seconds
Started Aug 17 04:47:40 PM PDT 24
Finished Aug 17 04:47:41 PM PDT 24
Peak memory 208920 kb
Host smart-1cec1505-6f75-4fda-9488-937faa820f9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244030511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1244030511
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.686267349
Short name T181
Test name
Test status
Simulation time 14648028 ps
CPU time 0.86 seconds
Started Aug 17 04:35:07 PM PDT 24
Finished Aug 17 04:35:08 PM PDT 24
Peak memory 209980 kb
Host smart-77b232f3-1326-4052-85bc-2933c98af889
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686267349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.686267349
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3138303739
Short name T43
Test name
Test status
Simulation time 10798229295 ps
CPU time 84.12 seconds
Started Aug 17 04:48:20 PM PDT 24
Finished Aug 17 04:49:45 PM PDT 24
Peak memory 273624 kb
Host smart-771fa850-61c1-4d3c-80dd-c85000c2a0fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138303739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3138303739
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.410964225
Short name T880
Test name
Test status
Simulation time 381678350 ps
CPU time 3.39 seconds
Started Aug 17 04:34:37 PM PDT 24
Finished Aug 17 04:34:40 PM PDT 24
Peak memory 219388 kb
Host smart-f8cc5f96-5d97-42e6-ab1f-4d5a0f3b68a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410964
225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.410964225
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2349203878
Short name T144
Test name
Test status
Simulation time 8271632150 ps
CPU time 122.3 seconds
Started Aug 17 04:47:45 PM PDT 24
Finished Aug 17 04:49:48 PM PDT 24
Peak memory 280908 kb
Host smart-61adaa1e-d83d-4cf6-b995-6349cf25bf0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349203878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2349203878
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1720365622
Short name T103
Test name
Test status
Simulation time 105050099 ps
CPU time 4.12 seconds
Started Aug 17 04:35:07 PM PDT 24
Finished Aug 17 04:35:11 PM PDT 24
Peak memory 218256 kb
Host smart-e4cfcaff-562f-4347-ac30-9cecc489cd03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720365622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1720365622
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.964935870
Short name T152
Test name
Test status
Simulation time 753212454 ps
CPU time 2.43 seconds
Started Aug 17 04:35:01 PM PDT 24
Finished Aug 17 04:35:04 PM PDT 24
Peak memory 218328 kb
Host smart-f56caf2d-fb4a-401e-9e36-fa88ade6ee8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964935870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.964935870
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2915267772
Short name T10
Test name
Test status
Simulation time 884094271 ps
CPU time 23.85 seconds
Started Aug 17 04:46:56 PM PDT 24
Finished Aug 17 04:47:20 PM PDT 24
Peak memory 244764 kb
Host smart-d1c94328-b059-45db-a089-aa2e2a1a4842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915267772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2915267772
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3882149332
Short name T118
Test name
Test status
Simulation time 83891726 ps
CPU time 2.63 seconds
Started Aug 17 04:34:55 PM PDT 24
Finished Aug 17 04:34:58 PM PDT 24
Peak memory 222912 kb
Host smart-80b71c6c-baa6-469d-b8cf-a1e47d741a3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882149332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3882149332
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.234623898
Short name T101
Test name
Test status
Simulation time 94668076 ps
CPU time 9.38 seconds
Started Aug 17 04:48:06 PM PDT 24
Finished Aug 17 04:48:16 PM PDT 24
Peak memory 251168 kb
Host smart-5ec89a86-63d4-48e3-944c-a132ab0f821a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234623898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.234623898
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1795147673
Short name T126
Test name
Test status
Simulation time 381971983 ps
CPU time 3.76 seconds
Started Aug 17 04:35:04 PM PDT 24
Finished Aug 17 04:35:08 PM PDT 24
Peak memory 223256 kb
Host smart-e319944f-d1f7-40ea-9f4a-2f21b3308204
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795147673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1795147673
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2209250702
Short name T121
Test name
Test status
Simulation time 271632335 ps
CPU time 3.29 seconds
Started Aug 17 04:35:06 PM PDT 24
Finished Aug 17 04:35:09 PM PDT 24
Peak memory 222904 kb
Host smart-867d9bc3-95eb-41aa-831b-3026bd27919c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209250702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2209250702
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2366942296
Short name T23
Test name
Test status
Simulation time 715570707 ps
CPU time 9.89 seconds
Started Aug 17 04:47:59 PM PDT 24
Finished Aug 17 04:48:09 PM PDT 24
Peak memory 217728 kb
Host smart-4d630227-e956-4c87-9d12-b1452450768a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366942296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2366942296
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1473516403
Short name T109
Test name
Test status
Simulation time 185769153 ps
CPU time 4.38 seconds
Started Aug 17 04:35:04 PM PDT 24
Finished Aug 17 04:35:08 PM PDT 24
Peak memory 218300 kb
Host smart-e172b8ba-7f60-41fa-bb67-c7f1aadb1cd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473516403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1473516403
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3572675506
Short name T114
Test name
Test status
Simulation time 101467507 ps
CPU time 3.09 seconds
Started Aug 17 04:34:51 PM PDT 24
Finished Aug 17 04:34:55 PM PDT 24
Peak memory 223208 kb
Host smart-b0875ce7-43fe-477c-aae9-054cd1364943
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572675506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3572675506
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.932015281
Short name T199
Test name
Test status
Simulation time 39130321 ps
CPU time 0.75 seconds
Started Aug 17 04:46:33 PM PDT 24
Finished Aug 17 04:46:34 PM PDT 24
Peak memory 209064 kb
Host smart-d619b350-2136-449f-9b1c-5d1fc8ec0bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932015281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.932015281
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2538045150
Short name T197
Test name
Test status
Simulation time 26138916 ps
CPU time 0.85 seconds
Started Aug 17 04:46:39 PM PDT 24
Finished Aug 17 04:46:40 PM PDT 24
Peak memory 208648 kb
Host smart-5af5950d-07be-460f-b1d3-72df642c1f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538045150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2538045150
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.209191860
Short name T174
Test name
Test status
Simulation time 23562030 ps
CPU time 0.82 seconds
Started Aug 17 04:46:55 PM PDT 24
Finished Aug 17 04:46:56 PM PDT 24
Peak memory 208576 kb
Host smart-22159bc7-120f-4659-8239-3c32f6395743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209191860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.209191860
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2832923803
Short name T198
Test name
Test status
Simulation time 14232400 ps
CPU time 0.84 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:00 PM PDT 24
Peak memory 208652 kb
Host smart-98effd89-1428-466d-9df6-c99eaf21e9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832923803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2832923803
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3777504303
Short name T85
Test name
Test status
Simulation time 614989815 ps
CPU time 22.46 seconds
Started Aug 17 04:47:13 PM PDT 24
Finished Aug 17 04:47:35 PM PDT 24
Peak memory 250876 kb
Host smart-65c584be-9667-480c-a569-567a073de99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777504303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3777504303
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3058992534
Short name T939
Test name
Test status
Simulation time 110400883 ps
CPU time 3.85 seconds
Started Aug 17 04:34:41 PM PDT 24
Finished Aug 17 04:34:45 PM PDT 24
Peak memory 218188 kb
Host smart-6a611945-6de2-49cc-acd8-90185cc8830a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058992534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3058992534
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1427331984
Short name T122
Test name
Test status
Simulation time 172386934 ps
CPU time 3.65 seconds
Started Aug 17 04:35:07 PM PDT 24
Finished Aug 17 04:35:11 PM PDT 24
Peak memory 218428 kb
Host smart-7c6de295-4bae-41ce-8498-156454910377
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427331984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1427331984
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.998590324
Short name T116
Test name
Test status
Simulation time 75820380 ps
CPU time 3.01 seconds
Started Aug 17 04:34:42 PM PDT 24
Finished Aug 17 04:34:45 PM PDT 24
Peak memory 223352 kb
Host smart-5e2a1ef9-d2cd-4308-8654-4036b127b44a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998590324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.998590324
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2162851514
Short name T127
Test name
Test status
Simulation time 277026837 ps
CPU time 3.63 seconds
Started Aug 17 04:34:49 PM PDT 24
Finished Aug 17 04:34:53 PM PDT 24
Peak memory 218244 kb
Host smart-ddb249cf-7b27-4081-93f5-cd787927a260
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162851514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2162851514
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1455693156
Short name T108
Test name
Test status
Simulation time 109944251 ps
CPU time 2.57 seconds
Started Aug 17 04:34:52 PM PDT 24
Finished Aug 17 04:34:54 PM PDT 24
Peak memory 218216 kb
Host smart-ffd2cdc3-9910-4cff-b088-1d7eb11cd5bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455693156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1455693156
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2626096930
Short name T120
Test name
Test status
Simulation time 117290306 ps
CPU time 3.26 seconds
Started Aug 17 04:34:59 PM PDT 24
Finished Aug 17 04:35:02 PM PDT 24
Peak memory 223188 kb
Host smart-0eda9e8d-2700-41cb-baeb-f8094033080a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626096930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2626096930
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2532214894
Short name T53
Test name
Test status
Simulation time 605970896 ps
CPU time 15.15 seconds
Started Aug 17 04:47:26 PM PDT 24
Finished Aug 17 04:47:41 PM PDT 24
Peak memory 218252 kb
Host smart-0881d759-d9fe-41e3-8919-39b3cb55960e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532214894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2532214894
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3647162643
Short name T2
Test name
Test status
Simulation time 274731040 ps
CPU time 6.92 seconds
Started Aug 17 04:48:06 PM PDT 24
Finished Aug 17 04:48:13 PM PDT 24
Peak memory 218488 kb
Host smart-85ac3531-f9d4-4569-a824-bf53200ae704
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647162643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3647162643
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1082414711
Short name T956
Test name
Test status
Simulation time 31294754 ps
CPU time 1.19 seconds
Started Aug 17 04:34:36 PM PDT 24
Finished Aug 17 04:34:37 PM PDT 24
Peak memory 210104 kb
Host smart-d5b2959b-7213-430e-b4bf-b858484f7539
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082414711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1082414711
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.433064849
Short name T952
Test name
Test status
Simulation time 18412311 ps
CPU time 1.41 seconds
Started Aug 17 04:34:37 PM PDT 24
Finished Aug 17 04:34:39 PM PDT 24
Peak memory 210048 kb
Host smart-3f68ffb8-1dae-4be4-a634-2969111b44ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433064849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.433064849
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3769772200
Short name T150
Test name
Test status
Simulation time 52444616 ps
CPU time 1.17 seconds
Started Aug 17 04:34:35 PM PDT 24
Finished Aug 17 04:34:36 PM PDT 24
Peak memory 210696 kb
Host smart-fea5df6b-b76f-4d7b-91b8-2e41cf95a4c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769772200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3769772200
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3182013148
Short name T993
Test name
Test status
Simulation time 551134717 ps
CPU time 1.33 seconds
Started Aug 17 04:34:36 PM PDT 24
Finished Aug 17 04:34:38 PM PDT 24
Peak memory 218528 kb
Host smart-43377cb3-82b4-4037-baf2-45376a8909d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182013148 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3182013148
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2973950583
Short name T900
Test name
Test status
Simulation time 13445787 ps
CPU time 0.89 seconds
Started Aug 17 04:34:35 PM PDT 24
Finished Aug 17 04:34:36 PM PDT 24
Peak memory 209788 kb
Host smart-3b849b6d-6681-40a6-9eba-6bdf3de990d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973950583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2973950583
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1295782459
Short name T901
Test name
Test status
Simulation time 167650135 ps
CPU time 1.21 seconds
Started Aug 17 04:34:34 PM PDT 24
Finished Aug 17 04:34:35 PM PDT 24
Peak memory 208664 kb
Host smart-a79f3fd3-ee93-428d-9e41-cc63c5e3f5c9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295782459 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1295782459
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3488359554
Short name T895
Test name
Test status
Simulation time 2344764203 ps
CPU time 14.29 seconds
Started Aug 17 04:34:33 PM PDT 24
Finished Aug 17 04:34:48 PM PDT 24
Peak memory 210000 kb
Host smart-33018093-dbdf-4809-8378-d5e79701d1eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488359554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3488359554
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3873426728
Short name T879
Test name
Test status
Simulation time 6165406868 ps
CPU time 13.9 seconds
Started Aug 17 04:34:34 PM PDT 24
Finished Aug 17 04:34:48 PM PDT 24
Peak memory 210156 kb
Host smart-75aa937a-cd1e-4e47-a528-cdf533bf1340
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873426728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3873426728
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2955744250
Short name T892
Test name
Test status
Simulation time 98440224 ps
CPU time 1.36 seconds
Started Aug 17 04:34:37 PM PDT 24
Finished Aug 17 04:34:39 PM PDT 24
Peak memory 211540 kb
Host smart-b998f737-e7b2-4127-b2e5-268065af532a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955744250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2955744250
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2125995711
Short name T942
Test name
Test status
Simulation time 331665934 ps
CPU time 1.42 seconds
Started Aug 17 04:34:34 PM PDT 24
Finished Aug 17 04:34:36 PM PDT 24
Peak memory 210092 kb
Host smart-f1e7cde1-ffa5-48a9-8d10-3551b69bfc29
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125995711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2125995711
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2926085165
Short name T151
Test name
Test status
Simulation time 81888274 ps
CPU time 1.84 seconds
Started Aug 17 04:34:34 PM PDT 24
Finished Aug 17 04:34:36 PM PDT 24
Peak memory 209856 kb
Host smart-364fa212-9585-4024-b6ae-a02137d95fe9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926085165 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2926085165
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3427426907
Short name T913
Test name
Test status
Simulation time 18912963 ps
CPU time 1.23 seconds
Started Aug 17 04:34:35 PM PDT 24
Finished Aug 17 04:34:36 PM PDT 24
Peak memory 210008 kb
Host smart-1920fdd9-ffc3-479e-b941-664bb2432a2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427426907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3427426907
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.683781724
Short name T990
Test name
Test status
Simulation time 50584402 ps
CPU time 1.76 seconds
Started Aug 17 04:34:35 PM PDT 24
Finished Aug 17 04:34:37 PM PDT 24
Peak memory 219216 kb
Host smart-2cf01d95-5e7f-4b0f-b739-00fc83c08462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683781724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.683781724
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3529374409
Short name T124
Test name
Test status
Simulation time 413277616 ps
CPU time 3.98 seconds
Started Aug 17 04:34:36 PM PDT 24
Finished Aug 17 04:34:40 PM PDT 24
Peak memory 218268 kb
Host smart-57186c1f-7608-407d-9e17-66cc741c3ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529374409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3529374409
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3192111759
Short name T875
Test name
Test status
Simulation time 16698723 ps
CPU time 1.01 seconds
Started Aug 17 04:34:44 PM PDT 24
Finished Aug 17 04:34:45 PM PDT 24
Peak memory 209992 kb
Host smart-0490979d-2aa0-48d8-87cf-665659384c72
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192111759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3192111759
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3633257860
Short name T945
Test name
Test status
Simulation time 38866016 ps
CPU time 1.29 seconds
Started Aug 17 04:34:42 PM PDT 24
Finished Aug 17 04:34:43 PM PDT 24
Peak memory 209984 kb
Host smart-b3e31d5d-6fe0-43b6-bc07-7f89079f5bf2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633257860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3633257860
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1700657128
Short name T988
Test name
Test status
Simulation time 12766705 ps
CPU time 1 seconds
Started Aug 17 04:34:42 PM PDT 24
Finished Aug 17 04:34:43 PM PDT 24
Peak memory 210460 kb
Host smart-7ef45d11-b4aa-4b4c-8273-add86234c326
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700657128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1700657128
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3227175781
Short name T927
Test name
Test status
Simulation time 60349804 ps
CPU time 1.29 seconds
Started Aug 17 04:34:43 PM PDT 24
Finished Aug 17 04:34:44 PM PDT 24
Peak memory 218372 kb
Host smart-a54f62da-a2c5-414c-83d3-c76e82552ad5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227175781 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3227175781
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.38920771
Short name T873
Test name
Test status
Simulation time 32905651 ps
CPU time 1.12 seconds
Started Aug 17 04:34:46 PM PDT 24
Finished Aug 17 04:34:47 PM PDT 24
Peak memory 210040 kb
Host smart-9def73f0-6f05-47f5-897f-80bd193e9271
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38920771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.38920771
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.576547038
Short name T134
Test name
Test status
Simulation time 438398063 ps
CPU time 2 seconds
Started Aug 17 04:34:42 PM PDT 24
Finished Aug 17 04:34:44 PM PDT 24
Peak memory 210008 kb
Host smart-6b70a039-0e56-4d41-aa62-b382ce75eb96
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576547038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.576547038
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3309244584
Short name T877
Test name
Test status
Simulation time 2010271182 ps
CPU time 6.45 seconds
Started Aug 17 04:34:36 PM PDT 24
Finished Aug 17 04:34:43 PM PDT 24
Peak memory 209924 kb
Host smart-35aef882-f73f-4adb-9d50-0574490f2f08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309244584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3309244584
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2130857612
Short name T902
Test name
Test status
Simulation time 1515469770 ps
CPU time 35.1 seconds
Started Aug 17 04:34:34 PM PDT 24
Finished Aug 17 04:35:09 PM PDT 24
Peak memory 209856 kb
Host smart-ddefe1dd-e5f6-4898-bef4-5844444b3b32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130857612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2130857612
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3353740693
Short name T883
Test name
Test status
Simulation time 477030448 ps
CPU time 3.06 seconds
Started Aug 17 04:34:36 PM PDT 24
Finished Aug 17 04:34:39 PM PDT 24
Peak memory 211724 kb
Host smart-56463b71-1e96-46ad-bf71-cb3cbdcf386e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353740693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3353740693
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3539058214
Short name T923
Test name
Test status
Simulation time 179192649 ps
CPU time 4.76 seconds
Started Aug 17 04:34:42 PM PDT 24
Finished Aug 17 04:34:47 PM PDT 24
Peak memory 218452 kb
Host smart-8a532981-b04a-482c-b7bd-8d9a7c4a6f8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353905
8214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3539058214
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1329432518
Short name T958
Test name
Test status
Simulation time 36518384 ps
CPU time 1.63 seconds
Started Aug 17 04:34:35 PM PDT 24
Finished Aug 17 04:34:37 PM PDT 24
Peak memory 209996 kb
Host smart-376a5ef4-6003-4e75-aafe-6b4b94a80f05
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329432518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1329432518
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3254618643
Short name T193
Test name
Test status
Simulation time 23611571 ps
CPU time 1.03 seconds
Started Aug 17 04:34:36 PM PDT 24
Finished Aug 17 04:34:37 PM PDT 24
Peak memory 210080 kb
Host smart-42b8c9e9-d9b4-4d60-a3dc-c4a2e31d03ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254618643 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3254618643
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.223427473
Short name T980
Test name
Test status
Simulation time 43867695 ps
CPU time 1.14 seconds
Started Aug 17 04:34:43 PM PDT 24
Finished Aug 17 04:34:44 PM PDT 24
Peak memory 210044 kb
Host smart-975cfb2e-691d-4cd7-b2cc-5419c2ab0e37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223427473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.223427473
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2415934831
Short name T128
Test name
Test status
Simulation time 62838433 ps
CPU time 2.03 seconds
Started Aug 17 04:34:42 PM PDT 24
Finished Aug 17 04:34:44 PM PDT 24
Peak memory 218208 kb
Host smart-81e5a06f-9f32-4e25-82ae-7763a723dbef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415934831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2415934831
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1449943724
Short name T919
Test name
Test status
Simulation time 60002532 ps
CPU time 1.11 seconds
Started Aug 17 04:35:01 PM PDT 24
Finished Aug 17 04:35:02 PM PDT 24
Peak memory 218268 kb
Host smart-74a00652-1ead-4e76-8e73-1a144af5cbbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449943724 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1449943724
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2370342130
Short name T933
Test name
Test status
Simulation time 27279109 ps
CPU time 0.9 seconds
Started Aug 17 04:35:00 PM PDT 24
Finished Aug 17 04:35:01 PM PDT 24
Peak memory 210016 kb
Host smart-0ef49d27-7598-4319-9f85-8ed710e29662
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370342130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2370342130
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3659364834
Short name T148
Test name
Test status
Simulation time 58816178 ps
CPU time 1.18 seconds
Started Aug 17 04:35:01 PM PDT 24
Finished Aug 17 04:35:03 PM PDT 24
Peak memory 210020 kb
Host smart-a664202f-bc3b-46a8-af95-1caa635002f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659364834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3659364834
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3796722581
Short name T921
Test name
Test status
Simulation time 75090106 ps
CPU time 2.21 seconds
Started Aug 17 04:35:05 PM PDT 24
Finished Aug 17 04:35:07 PM PDT 24
Peak memory 218232 kb
Host smart-7603ebd7-77b5-45c1-aaf9-120e82e69485
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796722581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3796722581
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3601284690
Short name T887
Test name
Test status
Simulation time 17398656 ps
CPU time 1.21 seconds
Started Aug 17 04:35:00 PM PDT 24
Finished Aug 17 04:35:02 PM PDT 24
Peak memory 219892 kb
Host smart-a68b1b4b-69e5-4b01-aec7-c08978372073
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601284690 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3601284690
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2079457022
Short name T907
Test name
Test status
Simulation time 17405324 ps
CPU time 0.9 seconds
Started Aug 17 04:34:58 PM PDT 24
Finished Aug 17 04:34:59 PM PDT 24
Peak memory 210096 kb
Host smart-c95bbc6f-870d-4c45-a0b7-a4c7a79e5b86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079457022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2079457022
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.113051331
Short name T112
Test name
Test status
Simulation time 137926395 ps
CPU time 1.49 seconds
Started Aug 17 04:34:59 PM PDT 24
Finished Aug 17 04:35:00 PM PDT 24
Peak memory 211776 kb
Host smart-e869c82a-1156-4371-9e25-25d2ed8d2c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113051331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.113051331
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2341261489
Short name T924
Test name
Test status
Simulation time 33925901 ps
CPU time 2.31 seconds
Started Aug 17 04:35:06 PM PDT 24
Finished Aug 17 04:35:09 PM PDT 24
Peak memory 219348 kb
Host smart-1510593e-f881-40cb-916c-f22cea06b3d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341261489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2341261489
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1408744611
Short name T125
Test name
Test status
Simulation time 135810016 ps
CPU time 2.6 seconds
Started Aug 17 04:35:05 PM PDT 24
Finished Aug 17 04:35:07 PM PDT 24
Peak memory 223136 kb
Host smart-14b0884f-52e9-4396-817f-642af99bde7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408744611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1408744611
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4079418727
Short name T997
Test name
Test status
Simulation time 20449218 ps
CPU time 1.67 seconds
Started Aug 17 04:34:58 PM PDT 24
Finished Aug 17 04:35:00 PM PDT 24
Peak memory 220328 kb
Host smart-df192d71-522f-4797-b2e2-ae7953d83d8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079418727 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.4079418727
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2969715153
Short name T183
Test name
Test status
Simulation time 56681747 ps
CPU time 1.05 seconds
Started Aug 17 04:34:58 PM PDT 24
Finished Aug 17 04:34:59 PM PDT 24
Peak memory 210116 kb
Host smart-d1907ea4-518c-44ce-acac-6e37ebecfb2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969715153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2969715153
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.170976324
Short name T918
Test name
Test status
Simulation time 25191877 ps
CPU time 1.38 seconds
Started Aug 17 04:35:05 PM PDT 24
Finished Aug 17 04:35:07 PM PDT 24
Peak memory 210076 kb
Host smart-3437dbf3-326c-4726-b1a8-4af33be90d84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170976324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.170976324
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.683394573
Short name T987
Test name
Test status
Simulation time 112508991 ps
CPU time 1.8 seconds
Started Aug 17 04:35:04 PM PDT 24
Finished Aug 17 04:35:06 PM PDT 24
Peak memory 218260 kb
Host smart-819c447b-320d-4934-9de4-afc9430abd63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683394573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.683394573
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4084111215
Short name T123
Test name
Test status
Simulation time 407102554 ps
CPU time 3 seconds
Started Aug 17 04:35:01 PM PDT 24
Finished Aug 17 04:35:04 PM PDT 24
Peak memory 222696 kb
Host smart-fcb5e791-29fa-4f93-ba9e-1d1d67e49913
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084111215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.4084111215
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3825991040
Short name T106
Test name
Test status
Simulation time 56566349 ps
CPU time 1.28 seconds
Started Aug 17 04:35:17 PM PDT 24
Finished Aug 17 04:35:19 PM PDT 24
Peak memory 218260 kb
Host smart-eb330775-9e8d-484e-876e-f43562a6617c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825991040 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3825991040
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1326388259
Short name T186
Test name
Test status
Simulation time 16556474 ps
CPU time 0.93 seconds
Started Aug 17 04:35:04 PM PDT 24
Finished Aug 17 04:35:06 PM PDT 24
Peak memory 210052 kb
Host smart-cdcc932d-0e53-4b6c-ae26-4a56cbb08e53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326388259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1326388259
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2541224960
Short name T994
Test name
Test status
Simulation time 27864274 ps
CPU time 1.14 seconds
Started Aug 17 04:35:00 PM PDT 24
Finished Aug 17 04:35:01 PM PDT 24
Peak memory 210084 kb
Host smart-41f1b901-8685-4737-9663-b0d4f4b43450
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541224960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2541224960
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1559131809
Short name T110
Test name
Test status
Simulation time 36926291 ps
CPU time 2.87 seconds
Started Aug 17 04:35:00 PM PDT 24
Finished Aug 17 04:35:03 PM PDT 24
Peak memory 218240 kb
Host smart-c9d50ce7-2dfd-4b9a-8299-627d92a4dd54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559131809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1559131809
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3647463421
Short name T119
Test name
Test status
Simulation time 44124546 ps
CPU time 1.94 seconds
Started Aug 17 04:35:04 PM PDT 24
Finished Aug 17 04:35:06 PM PDT 24
Peak memory 222344 kb
Host smart-b641973f-0f36-45a3-9f03-f611dfaa0638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647463421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3647463421
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1344128694
Short name T881
Test name
Test status
Simulation time 19908057 ps
CPU time 1.08 seconds
Started Aug 17 04:35:06 PM PDT 24
Finished Aug 17 04:35:08 PM PDT 24
Peak memory 218252 kb
Host smart-fab0aeb0-31c4-4cb0-b01b-b4e73556dce6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344128694 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1344128694
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3557964663
Short name T192
Test name
Test status
Simulation time 77400339 ps
CPU time 0.92 seconds
Started Aug 17 04:35:05 PM PDT 24
Finished Aug 17 04:35:06 PM PDT 24
Peak memory 210012 kb
Host smart-81f4cba8-27e5-41bd-ad9c-225b85693a49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557964663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3557964663
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1569330333
Short name T104
Test name
Test status
Simulation time 224132972 ps
CPU time 1.84 seconds
Started Aug 17 04:35:09 PM PDT 24
Finished Aug 17 04:35:11 PM PDT 24
Peak memory 218276 kb
Host smart-86aa5874-3396-4b9d-b53b-e51778c0eedb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569330333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1569330333
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2659506807
Short name T975
Test name
Test status
Simulation time 58372442 ps
CPU time 1.61 seconds
Started Aug 17 04:35:06 PM PDT 24
Finished Aug 17 04:35:08 PM PDT 24
Peak memory 218340 kb
Host smart-995b1676-cdd0-47cf-8552-f9a3c199a3f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659506807 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2659506807
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1961811226
Short name T917
Test name
Test status
Simulation time 20264963 ps
CPU time 0.92 seconds
Started Aug 17 04:35:12 PM PDT 24
Finished Aug 17 04:35:13 PM PDT 24
Peak memory 209976 kb
Host smart-c2816d5a-ce10-4ab1-9a65-04dc318482c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961811226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1961811226
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1063071249
Short name T191
Test name
Test status
Simulation time 35240056 ps
CPU time 1.17 seconds
Started Aug 17 04:35:07 PM PDT 24
Finished Aug 17 04:35:08 PM PDT 24
Peak memory 210048 kb
Host smart-0045fdbe-ed69-4c9d-bddb-b6e0a1dbd7f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063071249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1063071249
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.126697166
Short name T113
Test name
Test status
Simulation time 380927533 ps
CPU time 2.68 seconds
Started Aug 17 04:35:08 PM PDT 24
Finished Aug 17 04:35:11 PM PDT 24
Peak memory 218200 kb
Host smart-6af4e6e6-2c1c-4126-91e2-0fcb9cf22d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126697166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.126697166
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3911325321
Short name T972
Test name
Test status
Simulation time 74866885 ps
CPU time 1.6 seconds
Started Aug 17 04:35:13 PM PDT 24
Finished Aug 17 04:35:14 PM PDT 24
Peak memory 218432 kb
Host smart-3b636024-fa65-46da-b4f1-266b391b36cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911325321 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3911325321
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.917750312
Short name T884
Test name
Test status
Simulation time 51463406 ps
CPU time 0.88 seconds
Started Aug 17 04:35:08 PM PDT 24
Finished Aug 17 04:35:09 PM PDT 24
Peak memory 209828 kb
Host smart-ddf4adba-225e-435e-be9e-49735df88b78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917750312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.917750312
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2400412191
Short name T949
Test name
Test status
Simulation time 71921212 ps
CPU time 1.4 seconds
Started Aug 17 04:35:05 PM PDT 24
Finished Aug 17 04:35:06 PM PDT 24
Peak memory 210048 kb
Host smart-aa011143-8219-46f5-8778-905e44cc20a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400412191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2400412191
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2797515295
Short name T960
Test name
Test status
Simulation time 67464092 ps
CPU time 3.1 seconds
Started Aug 17 04:35:09 PM PDT 24
Finished Aug 17 04:35:12 PM PDT 24
Peak memory 218204 kb
Host smart-5db7e0b7-defe-4c73-8b25-129c077c0870
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797515295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2797515295
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2645655211
Short name T129
Test name
Test status
Simulation time 69992440 ps
CPU time 1.96 seconds
Started Aug 17 04:35:05 PM PDT 24
Finished Aug 17 04:35:07 PM PDT 24
Peak memory 222600 kb
Host smart-61a6b17b-4643-43f4-bcd3-9319a4a37d33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645655211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2645655211
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.22204486
Short name T876
Test name
Test status
Simulation time 42752259 ps
CPU time 1.56 seconds
Started Aug 17 04:35:06 PM PDT 24
Finished Aug 17 04:35:07 PM PDT 24
Peak memory 220556 kb
Host smart-8db58721-39dd-42c2-a860-c407954444d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22204486 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.22204486
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1145963675
Short name T153
Test name
Test status
Simulation time 15513425 ps
CPU time 1.1 seconds
Started Aug 17 04:35:11 PM PDT 24
Finished Aug 17 04:35:12 PM PDT 24
Peak memory 210012 kb
Host smart-6c9684e9-d040-4c2e-abcd-860c69ffba33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145963675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1145963675
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.892585489
Short name T963
Test name
Test status
Simulation time 22405599 ps
CPU time 0.98 seconds
Started Aug 17 04:35:07 PM PDT 24
Finished Aug 17 04:35:08 PM PDT 24
Peak memory 210040 kb
Host smart-3113baac-644a-41c8-822b-84e4fcf1a353
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892585489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.892585489
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3351122062
Short name T910
Test name
Test status
Simulation time 111962665 ps
CPU time 4.64 seconds
Started Aug 17 04:35:08 PM PDT 24
Finished Aug 17 04:35:12 PM PDT 24
Peak memory 218184 kb
Host smart-98634b34-7dd7-45ad-a1f1-af51f704c796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351122062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3351122062
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3091495961
Short name T169
Test name
Test status
Simulation time 25066396 ps
CPU time 1.01 seconds
Started Aug 17 04:35:07 PM PDT 24
Finished Aug 17 04:35:08 PM PDT 24
Peak memory 219428 kb
Host smart-abbcdf1c-7a81-42f6-a560-10025bbd2af2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091495961 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3091495961
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.509663657
Short name T189
Test name
Test status
Simulation time 15156187 ps
CPU time 1.06 seconds
Started Aug 17 04:35:12 PM PDT 24
Finished Aug 17 04:35:13 PM PDT 24
Peak memory 210032 kb
Host smart-bfa28b13-0efb-4b48-b7ab-d6c9213a2bf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509663657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.509663657
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.567085162
Short name T925
Test name
Test status
Simulation time 33702439 ps
CPU time 1.31 seconds
Started Aug 17 04:35:08 PM PDT 24
Finished Aug 17 04:35:10 PM PDT 24
Peak memory 212076 kb
Host smart-7f29e0ff-881b-4f9a-974f-8f891a0a332f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567085162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.567085162
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.860288436
Short name T102
Test name
Test status
Simulation time 136118122 ps
CPU time 2.28 seconds
Started Aug 17 04:35:06 PM PDT 24
Finished Aug 17 04:35:08 PM PDT 24
Peak memory 218424 kb
Host smart-f51a7db9-6df6-463d-85d3-6b0ab11da7a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860288436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.860288436
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1507658799
Short name T130
Test name
Test status
Simulation time 394906213 ps
CPU time 2.71 seconds
Started Aug 17 04:35:06 PM PDT 24
Finished Aug 17 04:35:09 PM PDT 24
Peak memory 222532 kb
Host smart-8eb1aceb-049b-4a38-b536-84033dfdc6b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507658799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1507658799
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.341855788
Short name T943
Test name
Test status
Simulation time 57205424 ps
CPU time 1.26 seconds
Started Aug 17 04:35:13 PM PDT 24
Finished Aug 17 04:35:14 PM PDT 24
Peak memory 219464 kb
Host smart-c9aa750f-7ecd-4b80-9fb1-49e6ebe20524
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341855788 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.341855788
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3632370266
Short name T974
Test name
Test status
Simulation time 17486549 ps
CPU time 1.1 seconds
Started Aug 17 04:35:09 PM PDT 24
Finished Aug 17 04:35:10 PM PDT 24
Peak memory 209980 kb
Host smart-4890a57c-a929-4212-9b2b-15b2463faae4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632370266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3632370266
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1637955254
Short name T937
Test name
Test status
Simulation time 46482675 ps
CPU time 2.08 seconds
Started Aug 17 04:35:09 PM PDT 24
Finished Aug 17 04:35:11 PM PDT 24
Peak memory 212184 kb
Host smart-8742ab3d-a2d1-4994-a699-3ea5c5f43e4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637955254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1637955254
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1522731691
Short name T882
Test name
Test status
Simulation time 364645072 ps
CPU time 1.76 seconds
Started Aug 17 04:35:17 PM PDT 24
Finished Aug 17 04:35:19 PM PDT 24
Peak memory 218124 kb
Host smart-19949db6-81d5-45ef-b4aa-9c7ac6ff52ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522731691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1522731691
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.91489286
Short name T180
Test name
Test status
Simulation time 29732057 ps
CPU time 1.29 seconds
Started Aug 17 04:34:46 PM PDT 24
Finished Aug 17 04:34:47 PM PDT 24
Peak memory 210080 kb
Host smart-8d49ce91-a723-4316-a885-06411580274c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91489286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing.91489286
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4270709606
Short name T908
Test name
Test status
Simulation time 318779996 ps
CPU time 2.01 seconds
Started Aug 17 04:34:43 PM PDT 24
Finished Aug 17 04:34:45 PM PDT 24
Peak memory 209380 kb
Host smart-2c4a5335-0788-4bf5-8ae0-afb6a5abe1d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270709606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.4270709606
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2521851220
Short name T185
Test name
Test status
Simulation time 74114823 ps
CPU time 1.22 seconds
Started Aug 17 04:34:40 PM PDT 24
Finished Aug 17 04:34:42 PM PDT 24
Peak memory 212352 kb
Host smart-518bc472-99f7-48b2-bb2a-220290c2de19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521851220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2521851220
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1244312746
Short name T885
Test name
Test status
Simulation time 50763615 ps
CPU time 2.01 seconds
Started Aug 17 04:34:45 PM PDT 24
Finished Aug 17 04:34:47 PM PDT 24
Peak memory 218324 kb
Host smart-b2d771f2-fde0-4a89-aa0c-730d751c85bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244312746 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1244312746
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.671998423
Short name T182
Test name
Test status
Simulation time 17579306 ps
CPU time 0.83 seconds
Started Aug 17 04:34:46 PM PDT 24
Finished Aug 17 04:34:46 PM PDT 24
Peak memory 209916 kb
Host smart-140b3ae3-5ebf-4f25-80d0-60f4e57d5ec0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671998423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.671998423
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3292872761
Short name T941
Test name
Test status
Simulation time 41808236 ps
CPU time 1.29 seconds
Started Aug 17 04:34:41 PM PDT 24
Finished Aug 17 04:34:43 PM PDT 24
Peak memory 209968 kb
Host smart-750e45a6-3add-42a5-9ef9-81a61a0cee9c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292872761 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3292872761
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.601983413
Short name T970
Test name
Test status
Simulation time 3023916138 ps
CPU time 9.09 seconds
Started Aug 17 04:34:41 PM PDT 24
Finished Aug 17 04:34:50 PM PDT 24
Peak memory 210096 kb
Host smart-eabc8851-3043-4026-9592-45d794881e77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601983413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.601983413
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4065493199
Short name T891
Test name
Test status
Simulation time 3968181543 ps
CPU time 5.15 seconds
Started Aug 17 04:34:43 PM PDT 24
Finished Aug 17 04:34:48 PM PDT 24
Peak memory 210052 kb
Host smart-3bb00ae8-fc5d-4438-8115-0146db736ada
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065493199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4065493199
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4158385331
Short name T953
Test name
Test status
Simulation time 68020731 ps
CPU time 1.35 seconds
Started Aug 17 04:34:42 PM PDT 24
Finished Aug 17 04:34:43 PM PDT 24
Peak memory 211508 kb
Host smart-23b42838-58f3-421c-883b-317ebc6eb131
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158385331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.4158385331
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.655851077
Short name T938
Test name
Test status
Simulation time 333221288 ps
CPU time 2.97 seconds
Started Aug 17 04:34:41 PM PDT 24
Finished Aug 17 04:34:44 PM PDT 24
Peak memory 219868 kb
Host smart-0165dbe4-40e7-4f87-b69b-809bd3e6f577
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655851
077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.655851077
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.319517631
Short name T977
Test name
Test status
Simulation time 576950230 ps
CPU time 3.22 seconds
Started Aug 17 04:34:40 PM PDT 24
Finished Aug 17 04:34:43 PM PDT 24
Peak memory 209972 kb
Host smart-3c1baa96-5927-4999-924c-8cfba2cfd365
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319517631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.319517631
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1884564022
Short name T981
Test name
Test status
Simulation time 39281467 ps
CPU time 1.22 seconds
Started Aug 17 04:34:42 PM PDT 24
Finished Aug 17 04:34:43 PM PDT 24
Peak memory 212316 kb
Host smart-a164db05-f9ce-4a3d-a475-650316078d50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884564022 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1884564022
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2090271558
Short name T903
Test name
Test status
Simulation time 157473966 ps
CPU time 1.41 seconds
Started Aug 17 04:34:44 PM PDT 24
Finished Aug 17 04:34:46 PM PDT 24
Peak memory 210036 kb
Host smart-e2aa8d6c-035e-464c-a94a-98a10f8748f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090271558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2090271558
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3693244499
Short name T986
Test name
Test status
Simulation time 89129870 ps
CPU time 1.73 seconds
Started Aug 17 04:34:44 PM PDT 24
Finished Aug 17 04:34:46 PM PDT 24
Peak memory 218340 kb
Host smart-27c56884-c500-433d-932f-753cf9317e3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693244499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3693244499
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.339061428
Short name T893
Test name
Test status
Simulation time 30843269 ps
CPU time 1.34 seconds
Started Aug 17 04:34:51 PM PDT 24
Finished Aug 17 04:34:53 PM PDT 24
Peak memory 210000 kb
Host smart-35e6ed9e-e8b7-4384-a88e-ff6ccae3baa1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339061428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.339061428
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2098183483
Short name T874
Test name
Test status
Simulation time 18273461 ps
CPU time 1.34 seconds
Started Aug 17 04:34:50 PM PDT 24
Finished Aug 17 04:34:52 PM PDT 24
Peak memory 209984 kb
Host smart-83767f31-ac25-4759-80cf-5faba33cba27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098183483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2098183483
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1300171519
Short name T904
Test name
Test status
Simulation time 42618640 ps
CPU time 1.02 seconds
Started Aug 17 04:34:52 PM PDT 24
Finished Aug 17 04:34:53 PM PDT 24
Peak memory 211260 kb
Host smart-cf810343-bd66-4166-b138-9c2e2d65e919
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300171519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1300171519
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1685153851
Short name T976
Test name
Test status
Simulation time 114251123 ps
CPU time 1.38 seconds
Started Aug 17 04:34:52 PM PDT 24
Finished Aug 17 04:34:54 PM PDT 24
Peak memory 223532 kb
Host smart-284baf21-c3cf-4cba-a46c-bdf7fdd2bcbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685153851 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1685153851
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2448762136
Short name T154
Test name
Test status
Simulation time 27656974 ps
CPU time 0.97 seconds
Started Aug 17 04:34:49 PM PDT 24
Finished Aug 17 04:34:50 PM PDT 24
Peak memory 209996 kb
Host smart-cb428682-5abf-4375-89db-000556f75933
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448762136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2448762136
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3125177207
Short name T984
Test name
Test status
Simulation time 82662870 ps
CPU time 0.89 seconds
Started Aug 17 04:34:43 PM PDT 24
Finished Aug 17 04:34:44 PM PDT 24
Peak memory 210080 kb
Host smart-ddd44ade-0f02-492b-ad37-a873cc76d815
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125177207 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3125177207
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3702873285
Short name T894
Test name
Test status
Simulation time 479259013 ps
CPU time 8.28 seconds
Started Aug 17 04:34:41 PM PDT 24
Finished Aug 17 04:34:50 PM PDT 24
Peak memory 209916 kb
Host smart-48d30c5e-194d-4838-909b-02ce62da6bbe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702873285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3702873285
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3120877377
Short name T957
Test name
Test status
Simulation time 1114193104 ps
CPU time 10.17 seconds
Started Aug 17 04:34:41 PM PDT 24
Finished Aug 17 04:34:52 PM PDT 24
Peak memory 210060 kb
Host smart-7746a382-03e3-4939-8234-cc13b493e313
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120877377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3120877377
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2538709438
Short name T906
Test name
Test status
Simulation time 385892474 ps
CPU time 3.11 seconds
Started Aug 17 04:34:45 PM PDT 24
Finished Aug 17 04:34:48 PM PDT 24
Peak memory 211808 kb
Host smart-512c9adc-e925-462a-8bd2-e71cb33e0c6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538709438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2538709438
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.816295110
Short name T934
Test name
Test status
Simulation time 204341050 ps
CPU time 3.52 seconds
Started Aug 17 04:34:44 PM PDT 24
Finished Aug 17 04:34:48 PM PDT 24
Peak memory 218236 kb
Host smart-d69455bf-47b1-43e3-a0a2-937138ee9eb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816295
110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.816295110
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4175921036
Short name T916
Test name
Test status
Simulation time 32797562 ps
CPU time 1.09 seconds
Started Aug 17 04:34:45 PM PDT 24
Finished Aug 17 04:34:47 PM PDT 24
Peak memory 210048 kb
Host smart-acfd0f5d-060e-4d99-9376-66d2cffee263
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175921036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.4175921036
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1476098439
Short name T950
Test name
Test status
Simulation time 72505065 ps
CPU time 1.18 seconds
Started Aug 17 04:34:44 PM PDT 24
Finished Aug 17 04:34:45 PM PDT 24
Peak memory 210076 kb
Host smart-57673fed-2806-41f2-8061-b009c0c8647f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476098439 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1476098439
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1696891947
Short name T929
Test name
Test status
Simulation time 169382236 ps
CPU time 1.12 seconds
Started Aug 17 04:34:52 PM PDT 24
Finished Aug 17 04:34:53 PM PDT 24
Peak memory 210072 kb
Host smart-2d2a9611-3094-4a7e-b503-3d11966fb1cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696891947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1696891947
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1405106374
Short name T117
Test name
Test status
Simulation time 1061506777 ps
CPU time 4.55 seconds
Started Aug 17 04:34:53 PM PDT 24
Finished Aug 17 04:34:58 PM PDT 24
Peak memory 218192 kb
Host smart-0f047552-89b6-46b2-9ee2-743045cfbd93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405106374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1405106374
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3607460029
Short name T187
Test name
Test status
Simulation time 25761265 ps
CPU time 1.39 seconds
Started Aug 17 04:34:54 PM PDT 24
Finished Aug 17 04:34:55 PM PDT 24
Peak memory 209952 kb
Host smart-4f67a146-b1c4-4eb0-af89-c140de250c55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607460029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.3607460029
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1120677805
Short name T971
Test name
Test status
Simulation time 157968637 ps
CPU time 1.33 seconds
Started Aug 17 04:34:48 PM PDT 24
Finished Aug 17 04:34:49 PM PDT 24
Peak memory 209920 kb
Host smart-591a4b66-ab2e-4764-806d-cf57968eeb05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120677805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1120677805
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4035528797
Short name T983
Test name
Test status
Simulation time 46601610 ps
CPU time 0.9 seconds
Started Aug 17 04:34:51 PM PDT 24
Finished Aug 17 04:34:52 PM PDT 24
Peak memory 210424 kb
Host smart-d7dc15f9-59cc-4922-8056-7eced3f987e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035528797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.4035528797
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2622822039
Short name T995
Test name
Test status
Simulation time 25799522 ps
CPU time 1.24 seconds
Started Aug 17 04:34:54 PM PDT 24
Finished Aug 17 04:34:56 PM PDT 24
Peak memory 218460 kb
Host smart-ee2dc72e-6453-42d3-8e3b-6feb0526e5d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622822039 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2622822039
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2116716024
Short name T188
Test name
Test status
Simulation time 31210079 ps
CPU time 0.96 seconds
Started Aug 17 04:34:54 PM PDT 24
Finished Aug 17 04:34:55 PM PDT 24
Peak memory 210016 kb
Host smart-06b64e01-4651-4992-b26a-c162a390f97d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116716024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2116716024
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1850830566
Short name T909
Test name
Test status
Simulation time 22562963 ps
CPU time 0.82 seconds
Started Aug 17 04:34:54 PM PDT 24
Finished Aug 17 04:34:55 PM PDT 24
Peak memory 209836 kb
Host smart-4c495d42-06dd-42e7-a1ab-9e4c1bf8f148
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850830566 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1850830566
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3945114190
Short name T890
Test name
Test status
Simulation time 569522004 ps
CPU time 6.04 seconds
Started Aug 17 04:34:48 PM PDT 24
Finished Aug 17 04:34:54 PM PDT 24
Peak memory 209908 kb
Host smart-c5e6bc41-b36d-4b39-b4ab-194f9768f84b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945114190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3945114190
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3694055438
Short name T996
Test name
Test status
Simulation time 1960153712 ps
CPU time 7.67 seconds
Started Aug 17 04:34:52 PM PDT 24
Finished Aug 17 04:35:00 PM PDT 24
Peak memory 209392 kb
Host smart-c040b8ab-ba55-4cb4-88e6-2c63b79b4a72
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694055438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3694055438
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.503281561
Short name T969
Test name
Test status
Simulation time 272592498 ps
CPU time 6.59 seconds
Started Aug 17 04:34:52 PM PDT 24
Finished Aug 17 04:34:59 PM PDT 24
Peak memory 211748 kb
Host smart-d5c1c0e1-be94-4f04-aabf-d5b2fcb14837
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503281561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.503281561
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.532596545
Short name T998
Test name
Test status
Simulation time 786641814 ps
CPU time 2.74 seconds
Started Aug 17 04:34:50 PM PDT 24
Finished Aug 17 04:34:53 PM PDT 24
Peak memory 218340 kb
Host smart-e93b7df2-f126-473e-a631-d957a12426e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532596
545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.532596545
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2747337457
Short name T965
Test name
Test status
Simulation time 148675024 ps
CPU time 1.85 seconds
Started Aug 17 04:34:49 PM PDT 24
Finished Aug 17 04:34:51 PM PDT 24
Peak memory 210048 kb
Host smart-35bfe58e-015c-4cfb-ba8d-918329b469c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747337457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2747337457
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1505622443
Short name T955
Test name
Test status
Simulation time 93744854 ps
CPU time 1.32 seconds
Started Aug 17 04:34:49 PM PDT 24
Finished Aug 17 04:34:51 PM PDT 24
Peak memory 210100 kb
Host smart-f215e1fe-6d4a-4bb9-b46b-5ffcd91da1dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505622443 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1505622443
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1178460343
Short name T190
Test name
Test status
Simulation time 69981968 ps
CPU time 1.48 seconds
Started Aug 17 04:34:51 PM PDT 24
Finished Aug 17 04:34:52 PM PDT 24
Peak memory 212040 kb
Host smart-c651a6d5-77a4-4108-80f8-3156528c58f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178460343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1178460343
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.315685585
Short name T978
Test name
Test status
Simulation time 572087033 ps
CPU time 2.89 seconds
Started Aug 17 04:34:55 PM PDT 24
Finished Aug 17 04:34:58 PM PDT 24
Peak memory 218404 kb
Host smart-32baf37e-0af9-44e9-88ab-ef743c080da9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315685585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.315685585
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2505783454
Short name T149
Test name
Test status
Simulation time 35876220 ps
CPU time 0.8 seconds
Started Aug 17 04:34:48 PM PDT 24
Finished Aug 17 04:34:49 PM PDT 24
Peak memory 210036 kb
Host smart-f1bd8fc9-0ad0-4537-9e93-15a5ae074931
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505783454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2505783454
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2403906220
Short name T966
Test name
Test status
Simulation time 139712946 ps
CPU time 1.76 seconds
Started Aug 17 04:34:52 PM PDT 24
Finished Aug 17 04:34:53 PM PDT 24
Peak memory 208760 kb
Host smart-3efd6f8d-483a-43ab-8619-4396e2954d3b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403906220 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2403906220
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4037088688
Short name T992
Test name
Test status
Simulation time 1172890299 ps
CPU time 5.27 seconds
Started Aug 17 04:34:52 PM PDT 24
Finished Aug 17 04:34:57 PM PDT 24
Peak memory 209352 kb
Host smart-b0d845ea-7744-4504-abdd-d5d49b68403c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037088688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.4037088688
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.876590005
Short name T898
Test name
Test status
Simulation time 827304643 ps
CPU time 21.54 seconds
Started Aug 17 04:34:51 PM PDT 24
Finished Aug 17 04:35:12 PM PDT 24
Peak memory 209948 kb
Host smart-6f3abff0-edde-47a5-9465-1fbc339cafa3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876590005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.876590005
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4279858612
Short name T905
Test name
Test status
Simulation time 265065468 ps
CPU time 2.82 seconds
Started Aug 17 04:34:50 PM PDT 24
Finished Aug 17 04:34:53 PM PDT 24
Peak memory 211484 kb
Host smart-3cf5786d-6b6d-4b38-8395-85585c6c23f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279858612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.4279858612
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.386702642
Short name T979
Test name
Test status
Simulation time 449945635 ps
CPU time 3.86 seconds
Started Aug 17 04:34:49 PM PDT 24
Finished Aug 17 04:34:53 PM PDT 24
Peak memory 218456 kb
Host smart-a1ee50d4-e853-403c-b4e5-7326acdf7ea7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386702
642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.386702642
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3498090604
Short name T889
Test name
Test status
Simulation time 67761981 ps
CPU time 1.08 seconds
Started Aug 17 04:34:56 PM PDT 24
Finished Aug 17 04:34:57 PM PDT 24
Peak memory 209960 kb
Host smart-1305a51c-cb9e-4b93-8292-553b188e42b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498090604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3498090604
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2707128649
Short name T948
Test name
Test status
Simulation time 69628962 ps
CPU time 1.02 seconds
Started Aug 17 04:34:50 PM PDT 24
Finished Aug 17 04:34:51 PM PDT 24
Peak memory 210056 kb
Host smart-fe124f1e-a10b-4fde-a4c5-275b95d81816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707128649 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2707128649
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2976359877
Short name T991
Test name
Test status
Simulation time 357527255 ps
CPU time 1.24 seconds
Started Aug 17 04:34:53 PM PDT 24
Finished Aug 17 04:34:55 PM PDT 24
Peak memory 210020 kb
Host smart-5024ed9f-8f4e-44ab-b1e6-bb5e61bd45c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976359877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2976359877
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3638540373
Short name T959
Test name
Test status
Simulation time 255780047 ps
CPU time 2.21 seconds
Started Aug 17 04:34:50 PM PDT 24
Finished Aug 17 04:34:52 PM PDT 24
Peak memory 218220 kb
Host smart-10622ea7-8e27-47bb-a505-b40283160360
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638540373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3638540373
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2021608193
Short name T926
Test name
Test status
Simulation time 60525142 ps
CPU time 1.24 seconds
Started Aug 17 04:34:50 PM PDT 24
Finished Aug 17 04:34:51 PM PDT 24
Peak memory 218348 kb
Host smart-96b61329-165d-4a7b-a521-f7a0716efd0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021608193 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2021608193
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1732898236
Short name T886
Test name
Test status
Simulation time 54107539 ps
CPU time 0.89 seconds
Started Aug 17 04:34:50 PM PDT 24
Finished Aug 17 04:34:51 PM PDT 24
Peak memory 209984 kb
Host smart-4dc84e8b-65ec-48d3-a118-9220e97c7d47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732898236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1732898236
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2232509465
Short name T967
Test name
Test status
Simulation time 486149370 ps
CPU time 1.27 seconds
Started Aug 17 04:34:56 PM PDT 24
Finished Aug 17 04:34:57 PM PDT 24
Peak memory 209964 kb
Host smart-d4e38622-1fc6-480b-98fe-df5e64562bbc
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232509465 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2232509465
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3540642590
Short name T973
Test name
Test status
Simulation time 2974804103 ps
CPU time 16.09 seconds
Started Aug 17 04:34:51 PM PDT 24
Finished Aug 17 04:35:07 PM PDT 24
Peak memory 210180 kb
Host smart-2a4c3494-7038-4432-801b-1517db539ca4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540642590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3540642590
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1433102205
Short name T964
Test name
Test status
Simulation time 2024894475 ps
CPU time 11.45 seconds
Started Aug 17 04:34:51 PM PDT 24
Finished Aug 17 04:35:02 PM PDT 24
Peak memory 209896 kb
Host smart-b47123af-c32e-4511-a3ee-45aedb0bb874
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433102205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1433102205
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3595005667
Short name T940
Test name
Test status
Simulation time 288598832 ps
CPU time 2.68 seconds
Started Aug 17 04:34:52 PM PDT 24
Finished Aug 17 04:34:55 PM PDT 24
Peak memory 211740 kb
Host smart-6fb7d985-88d5-4a60-bf30-d212ad132105
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595005667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3595005667
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1955755700
Short name T936
Test name
Test status
Simulation time 383216618 ps
CPU time 6.52 seconds
Started Aug 17 04:34:50 PM PDT 24
Finished Aug 17 04:34:57 PM PDT 24
Peak memory 219452 kb
Host smart-77146f6e-1984-46ce-a8a2-de4b8c0b89e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195575
5700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1955755700
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1272915611
Short name T132
Test name
Test status
Simulation time 344238426 ps
CPU time 2.89 seconds
Started Aug 17 04:34:48 PM PDT 24
Finished Aug 17 04:34:51 PM PDT 24
Peak memory 210044 kb
Host smart-53e5c0e9-baae-4ec1-a71f-8749b762994d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272915611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1272915611
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2033535343
Short name T935
Test name
Test status
Simulation time 135801758 ps
CPU time 1.34 seconds
Started Aug 17 04:34:55 PM PDT 24
Finished Aug 17 04:34:56 PM PDT 24
Peak memory 210004 kb
Host smart-091df63c-4962-4148-915f-5c684bfa1409
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033535343 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2033535343
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1180964195
Short name T951
Test name
Test status
Simulation time 42346557 ps
CPU time 0.95 seconds
Started Aug 17 04:34:49 PM PDT 24
Finished Aug 17 04:34:50 PM PDT 24
Peak memory 210052 kb
Host smart-e2dae565-6c93-474d-9743-0737a4153179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180964195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1180964195
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.927114039
Short name T920
Test name
Test status
Simulation time 44515039 ps
CPU time 3.24 seconds
Started Aug 17 04:34:51 PM PDT 24
Finished Aug 17 04:34:54 PM PDT 24
Peak memory 218320 kb
Host smart-5717b820-efb1-4e6b-9200-1e1e7788b6bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927114039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.927114039
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1834833532
Short name T989
Test name
Test status
Simulation time 23700516 ps
CPU time 1.1 seconds
Started Aug 17 04:34:57 PM PDT 24
Finished Aug 17 04:34:58 PM PDT 24
Peak memory 218412 kb
Host smart-340cb938-afea-4cf4-9b3c-04910dbb7aae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834833532 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1834833532
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3357824628
Short name T914
Test name
Test status
Simulation time 32674987 ps
CPU time 0.92 seconds
Started Aug 17 04:35:02 PM PDT 24
Finished Aug 17 04:35:03 PM PDT 24
Peak memory 209856 kb
Host smart-9ef1ce81-d2da-483b-a89b-109f0f99cae5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357824628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3357824628
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.770471237
Short name T962
Test name
Test status
Simulation time 37916891 ps
CPU time 1.58 seconds
Started Aug 17 04:35:00 PM PDT 24
Finished Aug 17 04:35:02 PM PDT 24
Peak memory 210052 kb
Host smart-04e1be7c-a65a-4754-9dff-61a271804641
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770471237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.770471237
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1563582893
Short name T111
Test name
Test status
Simulation time 443627747 ps
CPU time 11.07 seconds
Started Aug 17 04:34:59 PM PDT 24
Finished Aug 17 04:35:10 PM PDT 24
Peak memory 209892 kb
Host smart-4e30d93a-33ac-4994-8839-a56cd33b85b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563582893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1563582893
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1743071975
Short name T932
Test name
Test status
Simulation time 420135589 ps
CPU time 11.16 seconds
Started Aug 17 04:34:58 PM PDT 24
Finished Aug 17 04:35:09 PM PDT 24
Peak memory 208876 kb
Host smart-aad2456b-3868-4058-ab70-4621e8dde9a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743071975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1743071975
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1089125150
Short name T961
Test name
Test status
Simulation time 185602443 ps
CPU time 2.13 seconds
Started Aug 17 04:34:57 PM PDT 24
Finished Aug 17 04:34:59 PM PDT 24
Peak memory 211580 kb
Host smart-57f13ca3-bbf5-455c-9e5d-a3426a57d806
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089125150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1089125150
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4069493935
Short name T928
Test name
Test status
Simulation time 420740720 ps
CPU time 2.15 seconds
Started Aug 17 04:35:05 PM PDT 24
Finished Aug 17 04:35:07 PM PDT 24
Peak memory 218384 kb
Host smart-c06634a9-8005-4e32-a578-8eca65792662
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406949
3935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4069493935
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3504766493
Short name T899
Test name
Test status
Simulation time 87060459 ps
CPU time 1.94 seconds
Started Aug 17 04:35:02 PM PDT 24
Finished Aug 17 04:35:04 PM PDT 24
Peak memory 209980 kb
Host smart-8efe3abe-1abd-4e16-af52-e6c421aa4f69
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504766493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3504766493
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1746335100
Short name T944
Test name
Test status
Simulation time 29444044 ps
CPU time 1.09 seconds
Started Aug 17 04:34:57 PM PDT 24
Finished Aug 17 04:34:58 PM PDT 24
Peak memory 210016 kb
Host smart-fb9c8945-9173-45d1-bf26-058aa6d63383
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746335100 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1746335100
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.256005304
Short name T194
Test name
Test status
Simulation time 25155487 ps
CPU time 1.1 seconds
Started Aug 17 04:35:03 PM PDT 24
Finished Aug 17 04:35:05 PM PDT 24
Peak memory 210144 kb
Host smart-8205fe32-1a4f-4e54-863d-c0de953886e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256005304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.256005304
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2540685643
Short name T954
Test name
Test status
Simulation time 27677891 ps
CPU time 2.19 seconds
Started Aug 17 04:35:05 PM PDT 24
Finished Aug 17 04:35:07 PM PDT 24
Peak memory 218400 kb
Host smart-ec2a9e5e-a5ff-4f6b-b216-6c9405a09044
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540685643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2540685643
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.10322645
Short name T946
Test name
Test status
Simulation time 126597290 ps
CPU time 2.07 seconds
Started Aug 17 04:34:57 PM PDT 24
Finished Aug 17 04:34:59 PM PDT 24
Peak memory 222860 kb
Host smart-803fe10e-d9b9-4527-b2b7-1e21d95fa104
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10322645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_er
r.10322645
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3724733322
Short name T107
Test name
Test status
Simulation time 20080459 ps
CPU time 1.19 seconds
Started Aug 17 04:35:05 PM PDT 24
Finished Aug 17 04:35:06 PM PDT 24
Peak memory 218384 kb
Host smart-963ffc7e-db21-4d47-bfe8-c167e2e8be82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724733322 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3724733322
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2320013413
Short name T184
Test name
Test status
Simulation time 23536312 ps
CPU time 0.97 seconds
Started Aug 17 04:35:05 PM PDT 24
Finished Aug 17 04:35:06 PM PDT 24
Peak memory 209748 kb
Host smart-f7f8b9c1-15c8-4ced-8c85-874eefb725c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320013413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2320013413
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1662189038
Short name T878
Test name
Test status
Simulation time 49608309 ps
CPU time 0.99 seconds
Started Aug 17 04:35:04 PM PDT 24
Finished Aug 17 04:35:05 PM PDT 24
Peak memory 208716 kb
Host smart-d95ccf10-5e75-41c8-95b1-490571308fae
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662189038 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1662189038
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.326653631
Short name T133
Test name
Test status
Simulation time 413838460 ps
CPU time 6.63 seconds
Started Aug 17 04:34:57 PM PDT 24
Finished Aug 17 04:35:04 PM PDT 24
Peak memory 209928 kb
Host smart-f2caa6e3-e843-4f59-a244-0b89a454d81c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326653631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.326653631
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2630757912
Short name T911
Test name
Test status
Simulation time 3577478646 ps
CPU time 21.2 seconds
Started Aug 17 04:34:58 PM PDT 24
Finished Aug 17 04:35:19 PM PDT 24
Peak memory 210152 kb
Host smart-345cff71-3b69-4659-8a9a-1a083caae11b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630757912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2630757912
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1615003679
Short name T888
Test name
Test status
Simulation time 1521049817 ps
CPU time 2.89 seconds
Started Aug 17 04:34:58 PM PDT 24
Finished Aug 17 04:35:01 PM PDT 24
Peak memory 211552 kb
Host smart-b6db6792-2810-4009-8a4c-d9f7a586b736
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615003679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1615003679
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2629598239
Short name T931
Test name
Test status
Simulation time 118388978 ps
CPU time 3.38 seconds
Started Aug 17 04:35:05 PM PDT 24
Finished Aug 17 04:35:09 PM PDT 24
Peak memory 223932 kb
Host smart-46e6d757-cfaf-4dd7-a597-406a398ebfa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262959
8239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2629598239
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3765725123
Short name T896
Test name
Test status
Simulation time 75270744 ps
CPU time 1.46 seconds
Started Aug 17 04:35:04 PM PDT 24
Finished Aug 17 04:35:05 PM PDT 24
Peak memory 210020 kb
Host smart-2a24c222-1755-443d-b49e-bd1cb976abfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765725123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3765725123
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1649570597
Short name T930
Test name
Test status
Simulation time 97020903 ps
CPU time 1.11 seconds
Started Aug 17 04:34:57 PM PDT 24
Finished Aug 17 04:34:59 PM PDT 24
Peak memory 210056 kb
Host smart-b445b19d-46cf-4b29-a304-662844d7a9d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649570597 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1649570597
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.91280347
Short name T999
Test name
Test status
Simulation time 45563740 ps
CPU time 1.08 seconds
Started Aug 17 04:35:05 PM PDT 24
Finished Aug 17 04:35:06 PM PDT 24
Peak memory 210020 kb
Host smart-7c59449c-e67d-4f69-8fef-e0d2a4c0166a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91280347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_s
ame_csr_outstanding.91280347
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.505028689
Short name T985
Test name
Test status
Simulation time 147029873 ps
CPU time 3.12 seconds
Started Aug 17 04:35:05 PM PDT 24
Finished Aug 17 04:35:09 PM PDT 24
Peak memory 218244 kb
Host smart-6b9f5444-7fde-4edd-8a4f-cdfd855f6cf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505028689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.505028689
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.441080468
Short name T897
Test name
Test status
Simulation time 249856646 ps
CPU time 1.49 seconds
Started Aug 17 04:35:00 PM PDT 24
Finished Aug 17 04:35:02 PM PDT 24
Peak memory 218376 kb
Host smart-f171acfe-ebdf-4240-aacd-9a42e02279ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441080468 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.441080468
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3683504189
Short name T922
Test name
Test status
Simulation time 36809201 ps
CPU time 0.95 seconds
Started Aug 17 04:34:59 PM PDT 24
Finished Aug 17 04:35:00 PM PDT 24
Peak memory 209612 kb
Host smart-34f0d166-a07b-4c8f-bda2-b89d4978db0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683504189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3683504189
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3893900677
Short name T915
Test name
Test status
Simulation time 450133669 ps
CPU time 1.51 seconds
Started Aug 17 04:34:58 PM PDT 24
Finished Aug 17 04:35:00 PM PDT 24
Peak memory 209992 kb
Host smart-db7e8ea9-049d-45bf-8db6-b973c71238ac
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893900677 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3893900677
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3854003694
Short name T131
Test name
Test status
Simulation time 657308174 ps
CPU time 6.11 seconds
Started Aug 17 04:34:58 PM PDT 24
Finished Aug 17 04:35:04 PM PDT 24
Peak memory 209856 kb
Host smart-2edb1179-635f-4d34-b1ed-ebca89a7b69e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854003694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3854003694
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2709602617
Short name T135
Test name
Test status
Simulation time 1704452371 ps
CPU time 20.3 seconds
Started Aug 17 04:35:01 PM PDT 24
Finished Aug 17 04:35:21 PM PDT 24
Peak memory 209296 kb
Host smart-5a6c5782-49e1-48e9-b34f-42db56d0d780
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709602617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2709602617
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.4081728547
Short name T1000
Test name
Test status
Simulation time 451771443 ps
CPU time 3.26 seconds
Started Aug 17 04:35:00 PM PDT 24
Finished Aug 17 04:35:03 PM PDT 24
Peak memory 211848 kb
Host smart-a514f4ba-2a85-42bf-a3b8-7caab4d29493
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081728547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.4081728547
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3789693389
Short name T982
Test name
Test status
Simulation time 468965089 ps
CPU time 4.32 seconds
Started Aug 17 04:35:00 PM PDT 24
Finished Aug 17 04:35:05 PM PDT 24
Peak memory 219460 kb
Host smart-2e9f7894-ee02-4cf2-8f03-83ddcd759593
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378969
3389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3789693389
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1250838836
Short name T947
Test name
Test status
Simulation time 880184230 ps
CPU time 2.7 seconds
Started Aug 17 04:34:58 PM PDT 24
Finished Aug 17 04:35:01 PM PDT 24
Peak memory 209952 kb
Host smart-634be2f7-86d4-4a88-b52f-ae96a24399c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250838836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1250838836
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3401156233
Short name T968
Test name
Test status
Simulation time 42831648 ps
CPU time 2.01 seconds
Started Aug 17 04:34:58 PM PDT 24
Finished Aug 17 04:35:00 PM PDT 24
Peak memory 212148 kb
Host smart-83c54415-6f36-43cd-ad14-f508c8a0eebd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401156233 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3401156233
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.637999787
Short name T912
Test name
Test status
Simulation time 100259189 ps
CPU time 1.08 seconds
Started Aug 17 04:35:00 PM PDT 24
Finished Aug 17 04:35:01 PM PDT 24
Peak memory 210056 kb
Host smart-5006e2dd-a04e-4ccd-92a6-5538e583c15a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637999787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.637999787
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1803445843
Short name T403
Test name
Test status
Simulation time 15941074 ps
CPU time 1.1 seconds
Started Aug 17 04:46:32 PM PDT 24
Finished Aug 17 04:46:34 PM PDT 24
Peak memory 209044 kb
Host smart-115f13cb-dab8-457d-96e8-997f5219d45e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803445843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1803445843
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1728049122
Short name T510
Test name
Test status
Simulation time 28934214 ps
CPU time 0.79 seconds
Started Aug 17 04:46:28 PM PDT 24
Finished Aug 17 04:46:29 PM PDT 24
Peak memory 208920 kb
Host smart-feeb9004-c9db-4a26-9da5-206e220ff97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728049122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1728049122
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3937166676
Short name T646
Test name
Test status
Simulation time 321645079 ps
CPU time 15.44 seconds
Started Aug 17 04:46:29 PM PDT 24
Finished Aug 17 04:46:45 PM PDT 24
Peak memory 218272 kb
Host smart-ad2b8592-b8d6-42a6-b13f-90f9a68abd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937166676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3937166676
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3122697715
Short name T317
Test name
Test status
Simulation time 3961628587 ps
CPU time 17.33 seconds
Started Aug 17 04:46:32 PM PDT 24
Finished Aug 17 04:46:50 PM PDT 24
Peak memory 217732 kb
Host smart-0e9ea615-3a58-46c9-b6b0-c6602ef50251
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122697715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3122697715
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3237475753
Short name T555
Test name
Test status
Simulation time 3762787655 ps
CPU time 81.68 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:47:57 PM PDT 24
Peak memory 219044 kb
Host smart-8407a190-4a38-45a4-be1f-d712898fd071
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237475753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3237475753
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3957122465
Short name T687
Test name
Test status
Simulation time 1379014112 ps
CPU time 8.4 seconds
Started Aug 17 04:46:32 PM PDT 24
Finished Aug 17 04:46:41 PM PDT 24
Peak memory 217712 kb
Host smart-29df4578-762f-480b-a35b-80a206b4b3f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957122465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
957122465
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2117993395
Short name T518
Test name
Test status
Simulation time 56722113 ps
CPU time 1.96 seconds
Started Aug 17 04:46:34 PM PDT 24
Finished Aug 17 04:46:36 PM PDT 24
Peak memory 218220 kb
Host smart-e7a4aebf-9bb1-477e-ac2e-eea8a99d19e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117993395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2117993395
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.234038168
Short name T789
Test name
Test status
Simulation time 1117926671 ps
CPU time 30.54 seconds
Started Aug 17 04:46:28 PM PDT 24
Finished Aug 17 04:46:59 PM PDT 24
Peak memory 217568 kb
Host smart-f55ace54-4f88-493e-816b-fb1bc1cf8e6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234038168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.234038168
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2280751210
Short name T435
Test name
Test status
Simulation time 676939129 ps
CPU time 2 seconds
Started Aug 17 04:46:29 PM PDT 24
Finished Aug 17 04:46:31 PM PDT 24
Peak memory 217688 kb
Host smart-9b7c15f2-8448-4315-bda3-4dfac04034fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280751210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2280751210
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3509228166
Short name T391
Test name
Test status
Simulation time 8746326261 ps
CPU time 86.52 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:48:01 PM PDT 24
Peak memory 281996 kb
Host smart-a479cfb0-5eb7-4b95-b63e-5f805ec829bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509228166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3509228166
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.504343083
Short name T21
Test name
Test status
Simulation time 786714416 ps
CPU time 11.98 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:46:47 PM PDT 24
Peak memory 250776 kb
Host smart-33cd844b-1dc1-476a-82e3-69ffa61fdbe5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504343083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.504343083
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2380587527
Short name T561
Test name
Test status
Simulation time 97586167 ps
CPU time 3.16 seconds
Started Aug 17 04:46:37 PM PDT 24
Finished Aug 17 04:46:41 PM PDT 24
Peak memory 222468 kb
Host smart-dfbea208-3d71-4ad9-9f9e-a78df1487811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380587527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2380587527
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.301385274
Short name T617
Test name
Test status
Simulation time 580977435 ps
CPU time 19.48 seconds
Started Aug 17 04:46:32 PM PDT 24
Finished Aug 17 04:46:52 PM PDT 24
Peak memory 214148 kb
Host smart-f6768768-65f1-4e0f-bddc-4eae0ee87a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301385274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.301385274
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1438897655
Short name T88
Test name
Test status
Simulation time 255625851 ps
CPU time 23.11 seconds
Started Aug 17 04:46:30 PM PDT 24
Finished Aug 17 04:46:54 PM PDT 24
Peak memory 284324 kb
Host smart-3c34ab62-e906-4a24-992c-f2f45e73ab4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438897655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1438897655
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.862346710
Short name T512
Test name
Test status
Simulation time 276554577 ps
CPU time 12.57 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:46:47 PM PDT 24
Peak memory 218940 kb
Host smart-db01a24b-0413-4086-8847-6268481c82b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862346710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.862346710
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2394651436
Short name T780
Test name
Test status
Simulation time 3313419750 ps
CPU time 13.95 seconds
Started Aug 17 04:46:37 PM PDT 24
Finished Aug 17 04:46:51 PM PDT 24
Peak memory 226128 kb
Host smart-23eb5da0-fd03-40ce-a1cb-1364ea92adf3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394651436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2394651436
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1804618046
Short name T362
Test name
Test status
Simulation time 469869032 ps
CPU time 14.71 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:46:49 PM PDT 24
Peak memory 218112 kb
Host smart-c28ac9ae-b322-4631-9d79-09a8fc8132b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804618046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
804618046
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2934311917
Short name T360
Test name
Test status
Simulation time 666404069 ps
CPU time 7.1 seconds
Started Aug 17 04:46:38 PM PDT 24
Finished Aug 17 04:46:45 PM PDT 24
Peak memory 224632 kb
Host smart-ade1ca40-303d-44ef-b3bb-bd7a8d68c230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934311917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2934311917
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3279256163
Short name T264
Test name
Test status
Simulation time 277589378 ps
CPU time 1.99 seconds
Started Aug 17 04:46:26 PM PDT 24
Finished Aug 17 04:46:28 PM PDT 24
Peak memory 214296 kb
Host smart-6ab26f54-c66d-4413-8c45-a2c0e48b54ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279256163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3279256163
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2176320777
Short name T157
Test name
Test status
Simulation time 3059593278 ps
CPU time 24.51 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:47:00 PM PDT 24
Peak memory 247544 kb
Host smart-dd39c7e4-8fc5-4092-aed3-cf337fe58d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176320777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2176320777
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2644257880
Short name T287
Test name
Test status
Simulation time 229632400 ps
CPU time 3.08 seconds
Started Aug 17 04:46:34 PM PDT 24
Finished Aug 17 04:46:37 PM PDT 24
Peak memory 218240 kb
Host smart-3ba23673-40ae-455c-8736-db5885354935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644257880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2644257880
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.4170136223
Short name T752
Test name
Test status
Simulation time 93454558761 ps
CPU time 369.73 seconds
Started Aug 17 04:46:30 PM PDT 24
Finished Aug 17 04:52:40 PM PDT 24
Peak memory 271940 kb
Host smart-25272c87-d9ae-43b2-bd54-86c3f523ac64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170136223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.4170136223
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2487560493
Short name T484
Test name
Test status
Simulation time 59253942 ps
CPU time 0.83 seconds
Started Aug 17 04:46:32 PM PDT 24
Finished Aug 17 04:46:33 PM PDT 24
Peak memory 209264 kb
Host smart-8e485960-0280-46f0-9cd1-8291859bfe09
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487560493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2487560493
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3218753849
Short name T775
Test name
Test status
Simulation time 29354628 ps
CPU time 0.88 seconds
Started Aug 17 04:46:27 PM PDT 24
Finished Aug 17 04:46:28 PM PDT 24
Peak memory 208880 kb
Host smart-16e5110a-65eb-4162-9a6e-dc5093c81f37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218753849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3218753849
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.313935903
Short name T145
Test name
Test status
Simulation time 392517751 ps
CPU time 11.95 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:46:48 PM PDT 24
Peak memory 218256 kb
Host smart-7033530f-7b70-4564-893b-2b8488bd98c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313935903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.313935903
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.75339639
Short name T709
Test name
Test status
Simulation time 258324700 ps
CPU time 3.73 seconds
Started Aug 17 04:46:36 PM PDT 24
Finished Aug 17 04:46:40 PM PDT 24
Peak memory 217332 kb
Host smart-6f5b2fe4-d419-4b7d-9b7d-b6115834175e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75339639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.75339639
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3119613195
Short name T482
Test name
Test status
Simulation time 4426856509 ps
CPU time 53.77 seconds
Started Aug 17 04:46:29 PM PDT 24
Finished Aug 17 04:47:23 PM PDT 24
Peak memory 220200 kb
Host smart-173921d9-f68f-4e34-a057-aaefcd71d76d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119613195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3119613195
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2626913451
Short name T54
Test name
Test status
Simulation time 243369462 ps
CPU time 6.27 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:46:42 PM PDT 24
Peak memory 217736 kb
Host smart-6046ea8b-6f23-41e1-bd35-7981288d47ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626913451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
626913451
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3124864620
Short name T240
Test name
Test status
Simulation time 290323165 ps
CPU time 9.71 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:46:45 PM PDT 24
Peak memory 223040 kb
Host smart-931b9b53-c6b6-4ec5-9f69-579780ba19b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124864620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3124864620
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.997677231
Short name T331
Test name
Test status
Simulation time 919014980 ps
CPU time 28.84 seconds
Started Aug 17 04:46:29 PM PDT 24
Finished Aug 17 04:46:58 PM PDT 24
Peak memory 217892 kb
Host smart-fdd8bdbe-0e36-463a-9af6-0c0fb13fed85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997677231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.997677231
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3492453935
Short name T864
Test name
Test status
Simulation time 283834595 ps
CPU time 5.65 seconds
Started Aug 17 04:46:32 PM PDT 24
Finished Aug 17 04:46:38 PM PDT 24
Peak memory 217580 kb
Host smart-00890a89-a0a4-4fc6-8b4e-6e75adb2aeac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492453935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3492453935
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.675317467
Short name T776
Test name
Test status
Simulation time 1815013662 ps
CPU time 47.65 seconds
Started Aug 17 04:46:28 PM PDT 24
Finished Aug 17 04:47:16 PM PDT 24
Peak memory 267784 kb
Host smart-bd503075-40dc-4b3c-a834-bc0ce445ad4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675317467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.675317467
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1700927340
Short name T715
Test name
Test status
Simulation time 382923859 ps
CPU time 11.69 seconds
Started Aug 17 04:46:27 PM PDT 24
Finished Aug 17 04:46:39 PM PDT 24
Peak memory 250812 kb
Host smart-22362cbc-0cde-476c-9ae0-3df7b99a586b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700927340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1700927340
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2404266282
Short name T772
Test name
Test status
Simulation time 174543434 ps
CPU time 2.64 seconds
Started Aug 17 04:46:36 PM PDT 24
Finished Aug 17 04:46:39 PM PDT 24
Peak memory 222256 kb
Host smart-a72a4255-ac98-4009-bdfa-e96d6dd33e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404266282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2404266282
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.4290262510
Short name T830
Test name
Test status
Simulation time 540198942 ps
CPU time 18.1 seconds
Started Aug 17 04:46:33 PM PDT 24
Finished Aug 17 04:46:52 PM PDT 24
Peak memory 214636 kb
Host smart-89047d06-d5f0-431b-af2f-81f0e883b17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290262510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.4290262510
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2875657729
Short name T94
Test name
Test status
Simulation time 231548682 ps
CPU time 37.36 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:47:13 PM PDT 24
Peak memory 269116 kb
Host smart-42cdb91d-b21b-47a8-95ba-2cf6b2dcedbf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875657729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2875657729
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1796084917
Short name T236
Test name
Test status
Simulation time 317958243 ps
CPU time 12.92 seconds
Started Aug 17 04:46:33 PM PDT 24
Finished Aug 17 04:46:46 PM PDT 24
Peak memory 219952 kb
Host smart-bd486225-259e-4ccb-8057-ff4b7383adc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796084917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1796084917
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3561533475
Short name T479
Test name
Test status
Simulation time 1093227104 ps
CPU time 19.54 seconds
Started Aug 17 04:46:31 PM PDT 24
Finished Aug 17 04:46:50 PM PDT 24
Peak memory 225908 kb
Host smart-4ac2e157-d492-4e45-90f8-922181d49815
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561533475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3561533475
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.372333556
Short name T394
Test name
Test status
Simulation time 489775149 ps
CPU time 9.83 seconds
Started Aug 17 04:46:30 PM PDT 24
Finished Aug 17 04:46:41 PM PDT 24
Peak memory 218200 kb
Host smart-c313e3fb-3a3b-421f-8ddb-5b3a3efa7746
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372333556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.372333556
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1745646875
Short name T628
Test name
Test status
Simulation time 323309716 ps
CPU time 10.98 seconds
Started Aug 17 04:46:31 PM PDT 24
Finished Aug 17 04:46:42 PM PDT 24
Peak memory 218312 kb
Host smart-00c3f81b-8352-4d7f-a4e8-5014ac9a286b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745646875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1745646875
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.45350519
Short name T597
Test name
Test status
Simulation time 85191066 ps
CPU time 1.91 seconds
Started Aug 17 04:46:28 PM PDT 24
Finished Aug 17 04:46:30 PM PDT 24
Peak memory 214088 kb
Host smart-80073382-1333-48c5-8c09-b54b8c3a9440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45350519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.45350519
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3367829090
Short name T301
Test name
Test status
Simulation time 270562211 ps
CPU time 29.5 seconds
Started Aug 17 04:46:26 PM PDT 24
Finished Aug 17 04:46:56 PM PDT 24
Peak memory 250812 kb
Host smart-54cb4742-5666-4d25-b1c2-62b396265a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367829090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3367829090
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1175235955
Short name T565
Test name
Test status
Simulation time 73896952 ps
CPU time 4.21 seconds
Started Aug 17 04:46:34 PM PDT 24
Finished Aug 17 04:46:38 PM PDT 24
Peak memory 222716 kb
Host smart-8a2517cb-d9eb-49cc-a282-e3cbb84d2073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175235955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1175235955
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2119244519
Short name T855
Test name
Test status
Simulation time 98831821918 ps
CPU time 197.32 seconds
Started Aug 17 04:46:32 PM PDT 24
Finished Aug 17 04:49:50 PM PDT 24
Peak memory 309904 kb
Host smart-efbc03ba-6779-4432-91b3-6ec0722af7a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119244519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2119244519
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.264030639
Short name T138
Test name
Test status
Simulation time 2998970728 ps
CPU time 39.85 seconds
Started Aug 17 04:46:32 PM PDT 24
Finished Aug 17 04:47:12 PM PDT 24
Peak memory 271984 kb
Host smart-5a022b98-2678-4aaa-b7e6-3aa333ef7981
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=264030639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.264030639
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.622035033
Short name T266
Test name
Test status
Simulation time 35555397 ps
CPU time 0.85 seconds
Started Aug 17 04:46:32 PM PDT 24
Finished Aug 17 04:46:33 PM PDT 24
Peak memory 211872 kb
Host smart-5f0fdfa9-594a-4633-826c-7b0a6b980470
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622035033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.622035033
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.278208730
Short name T535
Test name
Test status
Simulation time 37584574 ps
CPU time 1.18 seconds
Started Aug 17 04:47:04 PM PDT 24
Finished Aug 17 04:47:06 PM PDT 24
Peak memory 209244 kb
Host smart-22ef27f5-f933-4b02-93a2-02bc0597d75f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278208730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.278208730
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1780929137
Short name T724
Test name
Test status
Simulation time 1468919506 ps
CPU time 15.46 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:15 PM PDT 24
Peak memory 226092 kb
Host smart-4c214a2b-398f-4819-a7fb-19959b4d9ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780929137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1780929137
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2638475278
Short name T591
Test name
Test status
Simulation time 1029240672 ps
CPU time 6.6 seconds
Started Aug 17 04:47:07 PM PDT 24
Finished Aug 17 04:47:13 PM PDT 24
Peak memory 216196 kb
Host smart-2d59fbf8-bbc0-45f4-b717-20487cbe08be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638475278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2638475278
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.4131389305
Short name T767
Test name
Test status
Simulation time 9913004784 ps
CPU time 40.64 seconds
Started Aug 17 04:46:58 PM PDT 24
Finished Aug 17 04:47:39 PM PDT 24
Peak memory 218884 kb
Host smart-5beb9360-ba22-4e53-818a-ae133a89948e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131389305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.4131389305
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.796971482
Short name T694
Test name
Test status
Simulation time 551259933 ps
CPU time 8.86 seconds
Started Aug 17 04:47:10 PM PDT 24
Finished Aug 17 04:47:19 PM PDT 24
Peak memory 217048 kb
Host smart-19a3c0eb-9bfb-4398-be3e-a18c1e9ce03b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796971482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.796971482
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3050501653
Short name T790
Test name
Test status
Simulation time 1033248017 ps
CPU time 4.51 seconds
Started Aug 17 04:47:03 PM PDT 24
Finished Aug 17 04:47:07 PM PDT 24
Peak memory 217576 kb
Host smart-274c6d11-9971-4779-b355-166a8cf598f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050501653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3050501653
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2646791041
Short name T728
Test name
Test status
Simulation time 5998308252 ps
CPU time 59.02 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:58 PM PDT 24
Peak memory 276740 kb
Host smart-9079b06d-2c31-4537-9ec5-d53cbf7ad15a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646791041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2646791041
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.497813591
Short name T730
Test name
Test status
Simulation time 4212618144 ps
CPU time 15.71 seconds
Started Aug 17 04:47:00 PM PDT 24
Finished Aug 17 04:47:16 PM PDT 24
Peak memory 226292 kb
Host smart-0649b507-6b1e-4ae6-898c-a4978e988db6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497813591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.497813591
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.977161729
Short name T15
Test name
Test status
Simulation time 29129134 ps
CPU time 1.75 seconds
Started Aug 17 04:47:07 PM PDT 24
Finished Aug 17 04:47:09 PM PDT 24
Peak memory 217048 kb
Host smart-69af91ec-c9e5-483e-8294-a2a95e5f361c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977161729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.977161729
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1309146369
Short name T259
Test name
Test status
Simulation time 601313784 ps
CPU time 15.69 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:15 PM PDT 24
Peak memory 218896 kb
Host smart-5135880c-6e4a-4964-91cf-3c0104d251bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309146369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1309146369
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3135495227
Short name T722
Test name
Test status
Simulation time 452676377 ps
CPU time 16.98 seconds
Started Aug 17 04:47:06 PM PDT 24
Finished Aug 17 04:47:23 PM PDT 24
Peak memory 225936 kb
Host smart-937fc9a8-63e9-4105-a1d9-fcf93980c5bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135495227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3135495227
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2914210021
Short name T552
Test name
Test status
Simulation time 317659323 ps
CPU time 8 seconds
Started Aug 17 04:47:00 PM PDT 24
Finished Aug 17 04:47:08 PM PDT 24
Peak memory 226068 kb
Host smart-5eacf40d-0205-45b7-9636-e80d5849b9ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914210021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2914210021
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1503306803
Short name T477
Test name
Test status
Simulation time 578416715 ps
CPU time 12.87 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:12 PM PDT 24
Peak memory 226128 kb
Host smart-0e212b32-66a5-452a-bbea-bf43fde87853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503306803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1503306803
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3481169954
Short name T556
Test name
Test status
Simulation time 66359623 ps
CPU time 1.95 seconds
Started Aug 17 04:47:14 PM PDT 24
Finished Aug 17 04:47:16 PM PDT 24
Peak memory 214216 kb
Host smart-0866cd1f-34af-4824-aa7c-797f101e1a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481169954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3481169954
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2070554270
Short name T460
Test name
Test status
Simulation time 216675620 ps
CPU time 19.34 seconds
Started Aug 17 04:47:08 PM PDT 24
Finished Aug 17 04:47:28 PM PDT 24
Peak memory 250788 kb
Host smart-8e11b1e5-fb32-4af2-b4f9-57e58d1ce07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070554270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2070554270
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.4082125674
Short name T285
Test name
Test status
Simulation time 99587734 ps
CPU time 8.39 seconds
Started Aug 17 04:47:06 PM PDT 24
Finished Aug 17 04:47:14 PM PDT 24
Peak memory 247088 kb
Host smart-b484d91b-bbb3-4cf1-af09-fd0556adfa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082125674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.4082125674
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3698427363
Short name T71
Test name
Test status
Simulation time 42422388760 ps
CPU time 164.83 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:49:44 PM PDT 24
Peak memory 253924 kb
Host smart-f3a94e4a-7b46-477d-bd26-17d99ee78264
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698427363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3698427363
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.935638784
Short name T137
Test name
Test status
Simulation time 17627077584 ps
CPU time 162.78 seconds
Started Aug 17 04:47:08 PM PDT 24
Finished Aug 17 04:49:51 PM PDT 24
Peak memory 276068 kb
Host smart-53047ebe-695b-4acc-b9c3-e5c5e485ce5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=935638784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.935638784
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.4282839771
Short name T629
Test name
Test status
Simulation time 21647109 ps
CPU time 0.87 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:00 PM PDT 24
Peak memory 208312 kb
Host smart-6932a89a-a44c-477b-b02b-fda265a86238
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282839771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.4282839771
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1972981871
Short name T424
Test name
Test status
Simulation time 22889730 ps
CPU time 1.22 seconds
Started Aug 17 04:47:22 PM PDT 24
Finished Aug 17 04:47:24 PM PDT 24
Peak memory 209028 kb
Host smart-260f9e65-44ae-4ac4-ba51-18dc4f8110d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972981871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1972981871
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3088069934
Short name T727
Test name
Test status
Simulation time 534069550 ps
CPU time 16 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:47:25 PM PDT 24
Peak memory 218400 kb
Host smart-7db243ec-d673-4ad7-8dde-451e13b2e07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088069934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3088069934
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3840095951
Short name T548
Test name
Test status
Simulation time 228983544 ps
CPU time 3.5 seconds
Started Aug 17 04:47:14 PM PDT 24
Finished Aug 17 04:47:17 PM PDT 24
Peak memory 217596 kb
Host smart-ea431f63-acd1-4f72-8e57-f12f9daafc93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840095951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3840095951
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1433383514
Short name T216
Test name
Test status
Simulation time 2717835111 ps
CPU time 38.83 seconds
Started Aug 17 04:47:08 PM PDT 24
Finished Aug 17 04:47:47 PM PDT 24
Peak memory 219012 kb
Host smart-af9c2790-2ebf-4ea2-ac67-1cfa39135ea3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433383514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1433383514
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2798642452
Short name T526
Test name
Test status
Simulation time 933747488 ps
CPU time 7.46 seconds
Started Aug 17 04:47:10 PM PDT 24
Finished Aug 17 04:47:18 PM PDT 24
Peak memory 223028 kb
Host smart-ba1935d9-af49-4df5-b280-e9e68b006717
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798642452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2798642452
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3703422744
Short name T497
Test name
Test status
Simulation time 184955534 ps
CPU time 1.96 seconds
Started Aug 17 04:47:16 PM PDT 24
Finished Aug 17 04:47:18 PM PDT 24
Peak memory 217556 kb
Host smart-7f0fb8c2-62d2-4963-bac8-a8c595897662
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703422744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3703422744
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1646145326
Short name T475
Test name
Test status
Simulation time 1281880374 ps
CPU time 46.37 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:47:55 PM PDT 24
Peak memory 269140 kb
Host smart-399cd6a0-12bd-4911-81c6-40db8e4f639c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646145326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1646145326
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3605791539
Short name T681
Test name
Test status
Simulation time 243963445 ps
CPU time 9.81 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:47:19 PM PDT 24
Peak memory 250780 kb
Host smart-3cec6afa-c0b0-4a89-aaaf-b28a834dcefd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605791539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3605791539
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.763478913
Short name T220
Test name
Test status
Simulation time 74241440 ps
CPU time 3.86 seconds
Started Aug 17 04:47:17 PM PDT 24
Finished Aug 17 04:47:21 PM PDT 24
Peak memory 218228 kb
Host smart-cca45b0c-ba61-4c47-90a1-aa2a974e763b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763478913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.763478913
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2292156803
Short name T336
Test name
Test status
Simulation time 241619847 ps
CPU time 10.07 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:47:19 PM PDT 24
Peak memory 226036 kb
Host smart-71db4725-98e2-4968-a34b-caf3b9c4a296
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292156803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2292156803
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.539045677
Short name T416
Test name
Test status
Simulation time 190166991 ps
CPU time 9.47 seconds
Started Aug 17 04:47:16 PM PDT 24
Finished Aug 17 04:47:26 PM PDT 24
Peak memory 225936 kb
Host smart-26f4db53-1ed9-42a0-8352-e445c82255dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539045677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.539045677
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3787368077
Short name T749
Test name
Test status
Simulation time 1466491809 ps
CPU time 14.25 seconds
Started Aug 17 04:47:10 PM PDT 24
Finished Aug 17 04:47:24 PM PDT 24
Peak memory 225972 kb
Host smart-823bb915-ec9f-4861-823d-3d7b24603c40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787368077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3787368077
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2719124728
Short name T474
Test name
Test status
Simulation time 5454346663 ps
CPU time 11.27 seconds
Started Aug 17 04:47:15 PM PDT 24
Finished Aug 17 04:47:26 PM PDT 24
Peak memory 218432 kb
Host smart-d9853383-ee93-490c-9fd4-fdc8ce9d997e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719124728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2719124728
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.4283426725
Short name T252
Test name
Test status
Simulation time 128442133 ps
CPU time 1.62 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:01 PM PDT 24
Peak memory 217640 kb
Host smart-b1127c1c-b63a-42e2-bd96-67860f5a6f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283426725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.4283426725
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1828028229
Short name T419
Test name
Test status
Simulation time 780798434 ps
CPU time 32.69 seconds
Started Aug 17 04:47:08 PM PDT 24
Finished Aug 17 04:47:41 PM PDT 24
Peak memory 250772 kb
Host smart-689d6e56-124b-414e-b7e3-8818bc021397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828028229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1828028229
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.870571795
Short name T509
Test name
Test status
Simulation time 106409528 ps
CPU time 6.69 seconds
Started Aug 17 04:46:58 PM PDT 24
Finished Aug 17 04:47:05 PM PDT 24
Peak memory 247100 kb
Host smart-4815149f-9bbc-4b06-8593-29f7308958e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870571795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.870571795
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1465161322
Short name T868
Test name
Test status
Simulation time 2186767265 ps
CPU time 26.02 seconds
Started Aug 17 04:47:10 PM PDT 24
Finished Aug 17 04:47:36 PM PDT 24
Peak memory 241784 kb
Host smart-48d8ba05-70e9-4cec-b4fc-fd04bd2815e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465161322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1465161322
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2576285286
Short name T256
Test name
Test status
Simulation time 30145999 ps
CPU time 0.87 seconds
Started Aug 17 04:47:07 PM PDT 24
Finished Aug 17 04:47:08 PM PDT 24
Peak memory 208972 kb
Host smart-ab85242f-2e3e-4ad3-9427-af7da65e3df3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576285286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2576285286
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1503632106
Short name T229
Test name
Test status
Simulation time 57454958 ps
CPU time 0.91 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:47:10 PM PDT 24
Peak memory 208920 kb
Host smart-2e94f577-50ff-4b22-8e23-2c1575edda4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503632106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1503632106
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2079278923
Short name T438
Test name
Test status
Simulation time 644701319 ps
CPU time 13.45 seconds
Started Aug 17 04:47:11 PM PDT 24
Finished Aug 17 04:47:24 PM PDT 24
Peak memory 218220 kb
Host smart-68f68fbd-3eec-4462-9330-1b0d7b311bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079278923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2079278923
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2155063989
Short name T26
Test name
Test status
Simulation time 230774121 ps
CPU time 6.57 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:47:16 PM PDT 24
Peak memory 217704 kb
Host smart-d634ba74-5d52-4226-8f41-7904f4135718
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155063989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2155063989
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3496275070
Short name T355
Test name
Test status
Simulation time 996649027 ps
CPU time 19.25 seconds
Started Aug 17 04:47:12 PM PDT 24
Finished Aug 17 04:47:32 PM PDT 24
Peak memory 218312 kb
Host smart-d6b14175-f2bd-4a7a-96b5-0cd37555d099
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496275070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3496275070
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2706243088
Short name T333
Test name
Test status
Simulation time 3427577438 ps
CPU time 12.07 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:47:21 PM PDT 24
Peak memory 226040 kb
Host smart-741abd85-1727-4524-9b58-fdd8b566ae59
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706243088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2706243088
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2429012557
Short name T351
Test name
Test status
Simulation time 222065272 ps
CPU time 4.11 seconds
Started Aug 17 04:47:14 PM PDT 24
Finished Aug 17 04:47:18 PM PDT 24
Peak memory 217552 kb
Host smart-dfff9cb8-eceb-4ba6-8435-bee9f3687c44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429012557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2429012557
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3907551455
Short name T274
Test name
Test status
Simulation time 4283372147 ps
CPU time 44.1 seconds
Started Aug 17 04:47:24 PM PDT 24
Finished Aug 17 04:48:08 PM PDT 24
Peak memory 267348 kb
Host smart-c4424138-2358-43f2-bf89-b75835f69e3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907551455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3907551455
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3629815509
Short name T616
Test name
Test status
Simulation time 1565776537 ps
CPU time 12.71 seconds
Started Aug 17 04:47:10 PM PDT 24
Finished Aug 17 04:47:23 PM PDT 24
Peak memory 250872 kb
Host smart-0c8adc62-be1f-46ec-82f5-a0a71da5bc83
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629815509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3629815509
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.766047719
Short name T869
Test name
Test status
Simulation time 104299464 ps
CPU time 3.03 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:47:12 PM PDT 24
Peak memory 218304 kb
Host smart-06e7597f-628c-45af-b9c2-65ce092a2649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766047719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.766047719
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.695550029
Short name T365
Test name
Test status
Simulation time 264252500 ps
CPU time 8.78 seconds
Started Aug 17 04:47:20 PM PDT 24
Finished Aug 17 04:47:29 PM PDT 24
Peak memory 226100 kb
Host smart-872340ed-1828-4a7c-aad0-be96e65650be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695550029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.695550029
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.608844505
Short name T257
Test name
Test status
Simulation time 263683310 ps
CPU time 11.18 seconds
Started Aug 17 04:47:08 PM PDT 24
Finished Aug 17 04:47:19 PM PDT 24
Peak memory 218172 kb
Host smart-70d1ac3c-9397-4fb0-9add-1aa3bec7af26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608844505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.608844505
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3095866066
Short name T651
Test name
Test status
Simulation time 869575393 ps
CPU time 9.79 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:47:19 PM PDT 24
Peak memory 226072 kb
Host smart-482673c5-f724-4c5b-86e5-80ab8286b9e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095866066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3095866066
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3899098391
Short name T276
Test name
Test status
Simulation time 219488516 ps
CPU time 8.89 seconds
Started Aug 17 04:47:29 PM PDT 24
Finished Aug 17 04:47:38 PM PDT 24
Peak memory 226060 kb
Host smart-2ccbaa47-4a01-45a3-8407-083eccc8033b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899098391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3899098391
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.981002318
Short name T244
Test name
Test status
Simulation time 186652418 ps
CPU time 2.35 seconds
Started Aug 17 04:47:21 PM PDT 24
Finished Aug 17 04:47:23 PM PDT 24
Peak memory 214280 kb
Host smart-9eb5716d-45f9-4aaa-a1a6-67c73c15e7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981002318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.981002318
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2663897837
Short name T449
Test name
Test status
Simulation time 589359563 ps
CPU time 25.45 seconds
Started Aug 17 04:47:14 PM PDT 24
Finished Aug 17 04:47:39 PM PDT 24
Peak memory 245768 kb
Host smart-7a38e393-6bbc-4337-b5aa-7523eefa531a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663897837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2663897837
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.994198667
Short name T397
Test name
Test status
Simulation time 1209535489 ps
CPU time 7.52 seconds
Started Aug 17 04:47:26 PM PDT 24
Finished Aug 17 04:47:33 PM PDT 24
Peak memory 250848 kb
Host smart-b855f746-2f5e-4a65-8b64-2798cc33d72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994198667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.994198667
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.4217404999
Short name T468
Test name
Test status
Simulation time 6686138421 ps
CPU time 66.72 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:48:16 PM PDT 24
Peak memory 250916 kb
Host smart-73bf3afa-ce8f-4720-8764-333feff77473
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217404999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.4217404999
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2616653186
Short name T147
Test name
Test status
Simulation time 23290909038 ps
CPU time 113.14 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:49:02 PM PDT 24
Peak memory 276476 kb
Host smart-bf93414e-762b-4087-a100-d32386c7d0bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2616653186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.2616653186
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3269406571
Short name T357
Test name
Test status
Simulation time 43424432 ps
CPU time 0.87 seconds
Started Aug 17 04:47:10 PM PDT 24
Finished Aug 17 04:47:11 PM PDT 24
Peak memory 208932 kb
Host smart-a58bffe1-e4d1-419d-91b8-f3f788789016
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269406571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3269406571
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2978683952
Short name T599
Test name
Test status
Simulation time 41267955 ps
CPU time 0.95 seconds
Started Aug 17 04:47:17 PM PDT 24
Finished Aug 17 04:47:19 PM PDT 24
Peak memory 209224 kb
Host smart-1980dae1-fcfa-46ba-bc48-d49a10882109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978683952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2978683952
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.918520050
Short name T408
Test name
Test status
Simulation time 1472379674 ps
CPU time 14.7 seconds
Started Aug 17 04:47:15 PM PDT 24
Finished Aug 17 04:47:30 PM PDT 24
Peak memory 218216 kb
Host smart-2a3f8381-1f72-4ed2-9a4e-ca745cdd5ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918520050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.918520050
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2420196707
Short name T804
Test name
Test status
Simulation time 346785135 ps
CPU time 4.91 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:47:14 PM PDT 24
Peak memory 217224 kb
Host smart-1fbf1f0a-d90a-4862-bcbb-5005760a5ad5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420196707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2420196707
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3493804289
Short name T811
Test name
Test status
Simulation time 24103195164 ps
CPU time 37.85 seconds
Started Aug 17 04:47:13 PM PDT 24
Finished Aug 17 04:47:51 PM PDT 24
Peak memory 219048 kb
Host smart-f36ef966-b5dd-4591-ad83-e733523131e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493804289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3493804289
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.599042461
Short name T4
Test name
Test status
Simulation time 224576199 ps
CPU time 2.04 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:47:11 PM PDT 24
Peak memory 218196 kb
Host smart-68828ee7-ccd5-4076-99fa-315494f3be1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599042461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.599042461
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.158541390
Short name T607
Test name
Test status
Simulation time 1217555094 ps
CPU time 10.17 seconds
Started Aug 17 04:47:16 PM PDT 24
Finished Aug 17 04:47:26 PM PDT 24
Peak memory 217552 kb
Host smart-b0a440ec-414e-4e97-ac51-1e7db36c4745
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158541390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
158541390
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3074612671
Short name T418
Test name
Test status
Simulation time 3051038493 ps
CPU time 56.02 seconds
Started Aug 17 04:47:16 PM PDT 24
Finished Aug 17 04:48:12 PM PDT 24
Peak memory 280536 kb
Host smart-182290af-8100-4d87-8dd7-6c14a81dea64
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074612671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3074612671
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3560833562
Short name T462
Test name
Test status
Simulation time 1592509805 ps
CPU time 11.43 seconds
Started Aug 17 04:47:18 PM PDT 24
Finished Aug 17 04:47:30 PM PDT 24
Peak memory 250456 kb
Host smart-31027562-e8b0-46b5-b18f-17a682ae855f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560833562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3560833562
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1666651589
Short name T205
Test name
Test status
Simulation time 213240405 ps
CPU time 3.06 seconds
Started Aug 17 04:47:10 PM PDT 24
Finished Aug 17 04:47:13 PM PDT 24
Peak memory 218240 kb
Host smart-d4951420-b492-4494-b738-5b1553b8d07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666651589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1666651589
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1441566056
Short name T282
Test name
Test status
Simulation time 306340972 ps
CPU time 14.88 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:47:24 PM PDT 24
Peak memory 218968 kb
Host smart-a2451ead-b68f-4f66-846b-95fbc7335db9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441566056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1441566056
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.908437373
Short name T340
Test name
Test status
Simulation time 871519503 ps
CPU time 16.44 seconds
Started Aug 17 04:47:17 PM PDT 24
Finished Aug 17 04:47:33 PM PDT 24
Peak memory 226060 kb
Host smart-075004d6-98a8-4c57-b7ff-df9018e9c6c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908437373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.908437373
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1264829956
Short name T620
Test name
Test status
Simulation time 362526335 ps
CPU time 9.99 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:37 PM PDT 24
Peak memory 218308 kb
Host smart-78f8ef0f-bf36-4dd5-bae9-50287249729d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264829956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1264829956
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3332489214
Short name T680
Test name
Test status
Simulation time 4085534153 ps
CPU time 9.68 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:47:19 PM PDT 24
Peak memory 225380 kb
Host smart-b771b589-68b2-4e67-8ca6-c33cfec289d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332489214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3332489214
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.4204782138
Short name T785
Test name
Test status
Simulation time 497352200 ps
CPU time 3.81 seconds
Started Aug 17 04:47:12 PM PDT 24
Finished Aug 17 04:47:16 PM PDT 24
Peak memory 217976 kb
Host smart-e0f6da02-e669-4b7d-b336-76855719787a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204782138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.4204782138
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1812517580
Short name T222
Test name
Test status
Simulation time 55171046 ps
CPU time 7.52 seconds
Started Aug 17 04:47:10 PM PDT 24
Finished Aug 17 04:47:18 PM PDT 24
Peak memory 250880 kb
Host smart-27b8094e-e3d2-4b3b-a638-7474edf66972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812517580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1812517580
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3696426827
Short name T673
Test name
Test status
Simulation time 13774635811 ps
CPU time 152.24 seconds
Started Aug 17 04:47:16 PM PDT 24
Finished Aug 17 04:49:49 PM PDT 24
Peak memory 259116 kb
Host smart-213bca66-3992-495a-90a2-ce19aaac25a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696426827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3696426827
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.1735097158
Short name T563
Test name
Test status
Simulation time 8491487139 ps
CPU time 72.56 seconds
Started Aug 17 04:47:22 PM PDT 24
Finished Aug 17 04:48:34 PM PDT 24
Peak memory 267412 kb
Host smart-8c294cc9-27e0-4e65-b79c-62cfbe2fb1c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1735097158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.1735097158
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.4203826108
Short name T763
Test name
Test status
Simulation time 15745486 ps
CPU time 0.87 seconds
Started Aug 17 04:47:09 PM PDT 24
Finished Aug 17 04:47:10 PM PDT 24
Peak memory 212004 kb
Host smart-805c5a04-f2dc-4820-87e2-13c8224ac307
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203826108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.4203826108
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.695601025
Short name T209
Test name
Test status
Simulation time 167383872 ps
CPU time 1.02 seconds
Started Aug 17 04:47:20 PM PDT 24
Finished Aug 17 04:47:21 PM PDT 24
Peak memory 209060 kb
Host smart-b934e462-5c4f-4159-af39-a7c37a968e8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695601025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.695601025
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.405913621
Short name T800
Test name
Test status
Simulation time 537289817 ps
CPU time 10.27 seconds
Started Aug 17 04:47:22 PM PDT 24
Finished Aug 17 04:47:33 PM PDT 24
Peak memory 218260 kb
Host smart-5eb5de2f-508f-48ea-bf62-5402864ebfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405913621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.405913621
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.632700394
Short name T24
Test name
Test status
Simulation time 780132839 ps
CPU time 5.67 seconds
Started Aug 17 04:47:22 PM PDT 24
Finished Aug 17 04:47:27 PM PDT 24
Peak memory 217616 kb
Host smart-f98a4539-54f4-49d3-86a7-a250b068a443
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632700394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.632700394
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.4164027890
Short name T779
Test name
Test status
Simulation time 2954174438 ps
CPU time 42.43 seconds
Started Aug 17 04:47:26 PM PDT 24
Finished Aug 17 04:48:08 PM PDT 24
Peak memory 218252 kb
Host smart-649234de-97c9-4622-97d1-952bf581ec17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164027890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.4164027890
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.964634607
Short name T202
Test name
Test status
Simulation time 307684130 ps
CPU time 6.12 seconds
Started Aug 17 04:47:16 PM PDT 24
Finished Aug 17 04:47:22 PM PDT 24
Peak memory 218136 kb
Host smart-b2828d43-77b5-4624-b238-390bcab33164
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964634607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.964634607
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.182249120
Short name T602
Test name
Test status
Simulation time 183104042 ps
CPU time 5.95 seconds
Started Aug 17 04:47:20 PM PDT 24
Finished Aug 17 04:47:26 PM PDT 24
Peak memory 217616 kb
Host smart-1b8197c1-4c97-41ff-8b2a-4ee545a3d803
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182249120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
182249120
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3473240472
Short name T242
Test name
Test status
Simulation time 840436898 ps
CPU time 39.35 seconds
Started Aug 17 04:47:25 PM PDT 24
Finished Aug 17 04:48:04 PM PDT 24
Peak memory 250812 kb
Host smart-81dd9f16-39e4-480f-b56e-8b317fe64ec0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473240472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3473240472
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.643626731
Short name T201
Test name
Test status
Simulation time 712391072 ps
CPU time 15.87 seconds
Started Aug 17 04:47:18 PM PDT 24
Finished Aug 17 04:47:34 PM PDT 24
Peak memory 250764 kb
Host smart-6c2cec57-7d97-405a-aaf5-771942b8f3f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643626731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.643626731
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1219920866
Short name T828
Test name
Test status
Simulation time 19632995 ps
CPU time 1.74 seconds
Started Aug 17 04:47:21 PM PDT 24
Finished Aug 17 04:47:23 PM PDT 24
Peak memory 222080 kb
Host smart-3ba4baa2-75be-47db-9d43-6fb66d95a21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219920866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1219920866
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1539782554
Short name T761
Test name
Test status
Simulation time 1155152591 ps
CPU time 11.07 seconds
Started Aug 17 04:47:23 PM PDT 24
Finished Aug 17 04:47:34 PM PDT 24
Peak memory 226076 kb
Host smart-316f6916-b97c-428c-a413-816a8fb2032e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539782554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1539782554
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2606015333
Short name T726
Test name
Test status
Simulation time 1795297021 ps
CPU time 9.96 seconds
Started Aug 17 04:47:20 PM PDT 24
Finished Aug 17 04:47:30 PM PDT 24
Peak memory 218288 kb
Host smart-07f8b464-50b9-4f77-9b57-5d4c9ea65f74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606015333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2606015333
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2944117917
Short name T754
Test name
Test status
Simulation time 1352922611 ps
CPU time 8.28 seconds
Started Aug 17 04:47:26 PM PDT 24
Finished Aug 17 04:47:34 PM PDT 24
Peak memory 218452 kb
Host smart-8627aec5-9ce7-434b-b03b-a8c5149de750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944117917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2944117917
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3547982892
Short name T684
Test name
Test status
Simulation time 144246393 ps
CPU time 1.51 seconds
Started Aug 17 04:47:18 PM PDT 24
Finished Aug 17 04:47:20 PM PDT 24
Peak memory 213924 kb
Host smart-eb3b9fab-5236-4941-b5c5-2496e9d44387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547982892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3547982892
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2864318265
Short name T660
Test name
Test status
Simulation time 425202916 ps
CPU time 23.44 seconds
Started Aug 17 04:47:22 PM PDT 24
Finished Aug 17 04:47:45 PM PDT 24
Peak memory 250920 kb
Host smart-b8a5539e-79a1-4426-8201-b57c502c806c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864318265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2864318265
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.4230464405
Short name T452
Test name
Test status
Simulation time 48171139 ps
CPU time 5.73 seconds
Started Aug 17 04:47:18 PM PDT 24
Finished Aug 17 04:47:24 PM PDT 24
Peak memory 246800 kb
Host smart-a8005117-2844-40fc-8b35-29bfdccb7947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230464405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.4230464405
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1489213517
Short name T44
Test name
Test status
Simulation time 26448179125 ps
CPU time 270.34 seconds
Started Aug 17 04:47:21 PM PDT 24
Finished Aug 17 04:51:51 PM PDT 24
Peak memory 275760 kb
Host smart-332ffe07-fdab-4c98-bfd9-e6ec6d4539d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489213517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1489213517
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1683405163
Short name T427
Test name
Test status
Simulation time 43299757 ps
CPU time 0.92 seconds
Started Aug 17 04:47:22 PM PDT 24
Finished Aug 17 04:47:23 PM PDT 24
Peak memory 209004 kb
Host smart-0220ec65-7b53-4cd2-b250-c86da83aceba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683405163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1683405163
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.272572325
Short name T89
Test name
Test status
Simulation time 116333701 ps
CPU time 1.18 seconds
Started Aug 17 04:47:29 PM PDT 24
Finished Aug 17 04:47:30 PM PDT 24
Peak memory 209084 kb
Host smart-dd96e058-e3b4-47a0-ac8e-ee87bfc837c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272572325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.272572325
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1127092064
Short name T253
Test name
Test status
Simulation time 1010842310 ps
CPU time 11.45 seconds
Started Aug 17 04:47:18 PM PDT 24
Finished Aug 17 04:47:30 PM PDT 24
Peak memory 218236 kb
Host smart-7c29326e-95d6-4bcd-97af-6e791d2af9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127092064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1127092064
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2185055121
Short name T832
Test name
Test status
Simulation time 391506699 ps
CPU time 5.78 seconds
Started Aug 17 04:47:28 PM PDT 24
Finished Aug 17 04:47:34 PM PDT 24
Peak memory 217208 kb
Host smart-1bdae486-08f5-4d0a-ac50-8fa74b558628
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185055121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2185055121
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1923997870
Short name T425
Test name
Test status
Simulation time 17948391833 ps
CPU time 114.19 seconds
Started Aug 17 04:47:24 PM PDT 24
Finished Aug 17 04:49:18 PM PDT 24
Peak memory 219756 kb
Host smart-b1a512a0-0300-4dee-9343-356030c72fc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923997870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1923997870
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.658981796
Short name T504
Test name
Test status
Simulation time 2439596625 ps
CPU time 8.89 seconds
Started Aug 17 04:47:18 PM PDT 24
Finished Aug 17 04:47:27 PM PDT 24
Peak memory 224472 kb
Host smart-27f92f05-a040-4594-a8f3-6e0634215460
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658981796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.658981796
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1541061293
Short name T636
Test name
Test status
Simulation time 339287378 ps
CPU time 4.3 seconds
Started Aug 17 04:47:20 PM PDT 24
Finished Aug 17 04:47:25 PM PDT 24
Peak memory 217596 kb
Host smart-f44350df-6e09-4c40-9d0d-f6ff3088eace
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541061293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1541061293
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.487302250
Short name T647
Test name
Test status
Simulation time 6765786798 ps
CPU time 52.24 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:48:19 PM PDT 24
Peak memory 267356 kb
Host smart-1065ea8d-b23f-4ec1-800a-1d83246430af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487302250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.487302250
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1738922153
Short name T725
Test name
Test status
Simulation time 882465041 ps
CPU time 29.25 seconds
Started Aug 17 04:47:21 PM PDT 24
Finished Aug 17 04:47:50 PM PDT 24
Peak memory 246920 kb
Host smart-4249bd30-dd77-4a0c-9757-86c068693e4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738922153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1738922153
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.551250679
Short name T538
Test name
Test status
Simulation time 359895277 ps
CPU time 4.05 seconds
Started Aug 17 04:47:18 PM PDT 24
Finished Aug 17 04:47:22 PM PDT 24
Peak memory 222572 kb
Host smart-53002b1f-72cb-45fc-89b6-dadb1d4c7d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551250679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.551250679
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.659489263
Short name T487
Test name
Test status
Simulation time 394289709 ps
CPU time 11.12 seconds
Started Aug 17 04:47:25 PM PDT 24
Finished Aug 17 04:47:36 PM PDT 24
Peak memory 226084 kb
Host smart-629865b8-4ae8-4022-9477-f7ebf7aa49e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659489263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.659489263
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2103874933
Short name T377
Test name
Test status
Simulation time 264100118 ps
CPU time 8.66 seconds
Started Aug 17 04:47:21 PM PDT 24
Finished Aug 17 04:47:29 PM PDT 24
Peak memory 225996 kb
Host smart-0752ae19-243a-43e8-b67d-dd780a5e2a05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103874933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2103874933
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.274372363
Short name T399
Test name
Test status
Simulation time 1723883281 ps
CPU time 11.2 seconds
Started Aug 17 04:47:19 PM PDT 24
Finished Aug 17 04:47:30 PM PDT 24
Peak memory 226000 kb
Host smart-6ce2434b-8154-4300-a05a-7770cc25e0fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274372363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.274372363
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3225487560
Short name T156
Test name
Test status
Simulation time 218572895 ps
CPU time 7.06 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:34 PM PDT 24
Peak memory 226024 kb
Host smart-009c7b97-a275-4d31-88f7-349ca5f413b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225487560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3225487560
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1366754884
Short name T753
Test name
Test status
Simulation time 39162435 ps
CPU time 1.89 seconds
Started Aug 17 04:47:18 PM PDT 24
Finished Aug 17 04:47:20 PM PDT 24
Peak memory 214120 kb
Host smart-a69833f7-c1aa-4e19-b172-5410b170c75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366754884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1366754884
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3130936478
Short name T736
Test name
Test status
Simulation time 317865457 ps
CPU time 19.19 seconds
Started Aug 17 04:47:30 PM PDT 24
Finished Aug 17 04:47:49 PM PDT 24
Peak memory 250868 kb
Host smart-5d115941-6a1e-47b3-9587-f62977aeae41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130936478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3130936478
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.4090937935
Short name T537
Test name
Test status
Simulation time 53643327 ps
CPU time 8.03 seconds
Started Aug 17 04:47:17 PM PDT 24
Finished Aug 17 04:47:25 PM PDT 24
Peak memory 250860 kb
Host smart-14e4a524-866f-4e61-aba6-3c772a7b3b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090937935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.4090937935
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.2231057540
Short name T323
Test name
Test status
Simulation time 59301897128 ps
CPU time 178.2 seconds
Started Aug 17 04:47:22 PM PDT 24
Finished Aug 17 04:50:20 PM PDT 24
Peak memory 242776 kb
Host smart-15785fa5-db8a-4da6-962a-56c719d55edd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231057540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.2231057540
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.3342618307
Short name T141
Test name
Test status
Simulation time 9561468976 ps
CPU time 102.9 seconds
Started Aug 17 04:47:17 PM PDT 24
Finished Aug 17 04:49:00 PM PDT 24
Peak memory 267364 kb
Host smart-e02c379e-698a-4d0a-9696-988d82bc1da1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3342618307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.3342618307
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2050892816
Short name T536
Test name
Test status
Simulation time 40836514 ps
CPU time 0.95 seconds
Started Aug 17 04:47:25 PM PDT 24
Finished Aug 17 04:47:26 PM PDT 24
Peak memory 211892 kb
Host smart-aa2d3f66-2857-4442-9e31-fb7a293b88d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050892816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2050892816
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3103444294
Short name T413
Test name
Test status
Simulation time 14978982 ps
CPU time 0.89 seconds
Started Aug 17 04:47:18 PM PDT 24
Finished Aug 17 04:47:19 PM PDT 24
Peak memory 208948 kb
Host smart-1e794cab-8122-4909-8d39-0bea7bca942a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103444294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3103444294
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.4216173440
Short name T661
Test name
Test status
Simulation time 506231953 ps
CPU time 11.88 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:39 PM PDT 24
Peak memory 218324 kb
Host smart-9f7e94e8-3ef3-496c-94c9-f2c56c091915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216173440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.4216173440
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1577091653
Short name T625
Test name
Test status
Simulation time 2605291880 ps
CPU time 6.97 seconds
Started Aug 17 04:47:28 PM PDT 24
Finished Aug 17 04:47:35 PM PDT 24
Peak memory 217796 kb
Host smart-7a5878a2-9236-4445-9083-c8ddc9435d61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577091653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1577091653
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1571492434
Short name T711
Test name
Test status
Simulation time 5342309454 ps
CPU time 21.87 seconds
Started Aug 17 04:47:28 PM PDT 24
Finished Aug 17 04:47:50 PM PDT 24
Peak memory 218932 kb
Host smart-0033d08e-f041-4e39-91cd-59dbdaa30880
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571492434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1571492434
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3396823826
Short name T634
Test name
Test status
Simulation time 649615999 ps
CPU time 5.35 seconds
Started Aug 17 04:47:28 PM PDT 24
Finished Aug 17 04:47:33 PM PDT 24
Peak memory 218212 kb
Host smart-f99c7eed-01b7-4569-882e-2a614ac8bd12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396823826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3396823826
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2725132842
Short name T18
Test name
Test status
Simulation time 1789702386 ps
CPU time 5.87 seconds
Started Aug 17 04:47:18 PM PDT 24
Finished Aug 17 04:47:24 PM PDT 24
Peak memory 217592 kb
Host smart-74352ffc-cb44-4ba8-b948-e9328dd3315e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725132842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2725132842
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1703347519
Short name T570
Test name
Test status
Simulation time 1114378352 ps
CPU time 43.19 seconds
Started Aug 17 04:47:17 PM PDT 24
Finished Aug 17 04:48:00 PM PDT 24
Peak memory 251944 kb
Host smart-d6a958d2-f905-4151-a4cf-dfd6efecb0cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703347519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1703347519
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3273996969
Short name T856
Test name
Test status
Simulation time 1915064161 ps
CPU time 12.63 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:40 PM PDT 24
Peak memory 250864 kb
Host smart-10edfe27-e23a-4361-8388-f93c87260674
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273996969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3273996969
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2804133016
Short name T210
Test name
Test status
Simulation time 76523857 ps
CPU time 2.44 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:30 PM PDT 24
Peak memory 222468 kb
Host smart-17f77d76-32a2-4216-977a-c2ff55d679ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804133016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2804133016
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.334586299
Short name T783
Test name
Test status
Simulation time 1484525982 ps
CPU time 17.14 seconds
Started Aug 17 04:47:19 PM PDT 24
Finished Aug 17 04:47:36 PM PDT 24
Peak memory 226040 kb
Host smart-2f53439e-b465-4983-9b8f-7948d138b72d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334586299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.334586299
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.379602132
Short name T742
Test name
Test status
Simulation time 589018888 ps
CPU time 11.18 seconds
Started Aug 17 04:47:29 PM PDT 24
Finished Aug 17 04:47:40 PM PDT 24
Peak memory 218216 kb
Host smart-1252a22b-4b67-4353-8721-da5d10135101
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379602132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.379602132
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2201370618
Short name T812
Test name
Test status
Simulation time 513067001 ps
CPU time 7.21 seconds
Started Aug 17 04:47:18 PM PDT 24
Finished Aug 17 04:47:25 PM PDT 24
Peak memory 218328 kb
Host smart-e90b306b-840b-49e6-a532-d518335756f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201370618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2201370618
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1945411795
Short name T835
Test name
Test status
Simulation time 407459253 ps
CPU time 8.28 seconds
Started Aug 17 04:47:21 PM PDT 24
Finished Aug 17 04:47:30 PM PDT 24
Peak memory 218336 kb
Host smart-12c258c6-8e64-46e6-89e4-af74afa1c2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945411795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1945411795
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3496251542
Short name T546
Test name
Test status
Simulation time 27456908 ps
CPU time 2.25 seconds
Started Aug 17 04:47:17 PM PDT 24
Finished Aug 17 04:47:19 PM PDT 24
Peak memory 214064 kb
Host smart-ebd9f7a0-b5f8-4292-8c3e-68fe44bf2eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496251542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3496251542
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.180727097
Short name T747
Test name
Test status
Simulation time 185348909 ps
CPU time 5.62 seconds
Started Aug 17 04:47:30 PM PDT 24
Finished Aug 17 04:47:36 PM PDT 24
Peak memory 246788 kb
Host smart-d98ab5f3-5910-4f1d-9d52-9b0d96aeaed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180727097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.180727097
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3395768408
Short name T439
Test name
Test status
Simulation time 44979255 ps
CPU time 0.78 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:28 PM PDT 24
Peak memory 209184 kb
Host smart-e7e8febf-23fe-47af-8f03-9195781d9ae5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395768408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3395768408
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.4230163403
Short name T263
Test name
Test status
Simulation time 35496347 ps
CPU time 1.03 seconds
Started Aug 17 04:47:39 PM PDT 24
Finished Aug 17 04:47:40 PM PDT 24
Peak memory 208984 kb
Host smart-ad643b8b-d3c4-40c6-a346-907f6a5774a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230163403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.4230163403
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.204033904
Short name T415
Test name
Test status
Simulation time 495031479 ps
CPU time 22.49 seconds
Started Aug 17 04:47:31 PM PDT 24
Finished Aug 17 04:47:54 PM PDT 24
Peak memory 218216 kb
Host smart-5f99e182-300f-4767-85d8-b1c147773a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204033904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.204033904
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3792556765
Short name T176
Test name
Test status
Simulation time 1120530252 ps
CPU time 3.72 seconds
Started Aug 17 04:47:26 PM PDT 24
Finished Aug 17 04:47:30 PM PDT 24
Peak memory 217116 kb
Host smart-686afe54-7279-43cd-9084-9c45ae8c5641
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792556765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3792556765
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3096311151
Short name T558
Test name
Test status
Simulation time 3600723750 ps
CPU time 92.25 seconds
Started Aug 17 04:47:25 PM PDT 24
Finished Aug 17 04:48:57 PM PDT 24
Peak memory 218264 kb
Host smart-46a407e8-d1ae-4571-ad97-ae56f285905c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096311151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3096311151
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1849882050
Short name T829
Test name
Test status
Simulation time 665401096 ps
CPU time 3.54 seconds
Started Aug 17 04:47:34 PM PDT 24
Finished Aug 17 04:47:38 PM PDT 24
Peak memory 218260 kb
Host smart-e37a926c-a267-4bb5-a002-6655f7b92f0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849882050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1849882050
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1827950656
Short name T280
Test name
Test status
Simulation time 797841842 ps
CPU time 5.82 seconds
Started Aug 17 04:47:26 PM PDT 24
Finished Aug 17 04:47:32 PM PDT 24
Peak memory 217600 kb
Host smart-58f6a478-3a46-4d66-8c6e-5c7d1a03e4a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827950656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1827950656
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3242009022
Short name T292
Test name
Test status
Simulation time 8385297022 ps
CPU time 57.16 seconds
Started Aug 17 04:47:31 PM PDT 24
Finished Aug 17 04:48:28 PM PDT 24
Peak memory 267272 kb
Host smart-962a43f4-8468-40b8-8a5d-040493b86ca2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242009022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3242009022
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.4198788807
Short name T409
Test name
Test status
Simulation time 442336059 ps
CPU time 9.72 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:36 PM PDT 24
Peak memory 223168 kb
Host smart-2ef9f22c-15f0-4213-b936-9e8f88f84948
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198788807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.4198788807
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.788590532
Short name T493
Test name
Test status
Simulation time 103091417 ps
CPU time 2.36 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:29 PM PDT 24
Peak memory 218332 kb
Host smart-0db3f09d-ee38-494e-929d-44f159e7a2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788590532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.788590532
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1110775494
Short name T249
Test name
Test status
Simulation time 282196554 ps
CPU time 12.65 seconds
Started Aug 17 04:47:44 PM PDT 24
Finished Aug 17 04:47:57 PM PDT 24
Peak memory 218208 kb
Host smart-6010a844-c0ce-43cd-ae18-2149692f1e9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110775494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1110775494
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3818246746
Short name T838
Test name
Test status
Simulation time 740545661 ps
CPU time 13.97 seconds
Started Aug 17 04:47:29 PM PDT 24
Finished Aug 17 04:47:43 PM PDT 24
Peak memory 225980 kb
Host smart-b2bd43d4-7557-46f5-a2f0-0418e341100c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818246746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3818246746
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2227755675
Short name T354
Test name
Test status
Simulation time 1159854810 ps
CPU time 8.59 seconds
Started Aug 17 04:47:29 PM PDT 24
Finished Aug 17 04:47:38 PM PDT 24
Peak memory 226064 kb
Host smart-300e5bbe-a556-4641-9d93-f20c71ad673a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227755675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2227755675
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3152070280
Short name T376
Test name
Test status
Simulation time 1469941624 ps
CPU time 8.84 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:36 PM PDT 24
Peak memory 218388 kb
Host smart-2cd6abc3-f93a-4f4f-b869-0c89ff2c32aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152070280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3152070280
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1791342384
Short name T705
Test name
Test status
Simulation time 47292389 ps
CPU time 1.02 seconds
Started Aug 17 04:47:20 PM PDT 24
Finished Aug 17 04:47:21 PM PDT 24
Peak memory 212276 kb
Host smart-24a66cf0-266a-4b06-b9c6-2b909d65a3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791342384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1791342384
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3537677847
Short name T45
Test name
Test status
Simulation time 810769601 ps
CPU time 30.91 seconds
Started Aug 17 04:47:19 PM PDT 24
Finished Aug 17 04:47:50 PM PDT 24
Peak memory 250876 kb
Host smart-30fac721-2c64-45fd-b391-3cbb62dc7be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537677847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3537677847
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1130327398
Short name T817
Test name
Test status
Simulation time 115956592 ps
CPU time 7.67 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:35 PM PDT 24
Peak memory 246952 kb
Host smart-ea72a4a3-1cd2-49b2-a62f-454ed0dda0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130327398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1130327398
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.455662351
Short name T659
Test name
Test status
Simulation time 30498941 ps
CPU time 0.72 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:28 PM PDT 24
Peak memory 208832 kb
Host smart-a39139f8-81d0-43b0-be73-0c8cd2a215b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455662351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.455662351
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.4259420104
Short name T676
Test name
Test status
Simulation time 129755244 ps
CPU time 0.98 seconds
Started Aug 17 04:47:47 PM PDT 24
Finished Aug 17 04:47:48 PM PDT 24
Peak memory 208884 kb
Host smart-78928463-4253-406b-8ec9-c628258cfd2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259420104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.4259420104
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2847445168
Short name T393
Test name
Test status
Simulation time 1471534707 ps
CPU time 8.63 seconds
Started Aug 17 04:47:30 PM PDT 24
Finished Aug 17 04:47:38 PM PDT 24
Peak memory 218204 kb
Host smart-e7d32d65-cd49-432c-81bf-ab2a4e1d2194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847445168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2847445168
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3916149424
Short name T784
Test name
Test status
Simulation time 246904314 ps
CPU time 3.73 seconds
Started Aug 17 04:47:45 PM PDT 24
Finished Aug 17 04:47:49 PM PDT 24
Peak memory 217664 kb
Host smart-01a3f79a-0e90-4111-ba34-3575feb537e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916149424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3916149424
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.592256795
Short name T499
Test name
Test status
Simulation time 6694967461 ps
CPU time 46.34 seconds
Started Aug 17 04:47:32 PM PDT 24
Finished Aug 17 04:48:19 PM PDT 24
Peak memory 218616 kb
Host smart-74b0b446-16da-4b80-9d42-01cdc705d910
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592256795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.592256795
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1710946121
Short name T786
Test name
Test status
Simulation time 3295855460 ps
CPU time 4.93 seconds
Started Aug 17 04:47:31 PM PDT 24
Finished Aug 17 04:47:36 PM PDT 24
Peak memory 223512 kb
Host smart-030957a2-9b96-4ff6-9191-a00f8ab5b7ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710946121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1710946121
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.828884301
Short name T81
Test name
Test status
Simulation time 1098697571 ps
CPU time 9.1 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:37 PM PDT 24
Peak memory 217600 kb
Host smart-fb397a2c-b7e3-467b-b1f0-c099751aba18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828884301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
828884301
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.120831315
Short name T613
Test name
Test status
Simulation time 6391672744 ps
CPU time 46.44 seconds
Started Aug 17 04:47:30 PM PDT 24
Finished Aug 17 04:48:16 PM PDT 24
Peak memory 267452 kb
Host smart-3b91988a-487d-4890-b69f-b4251aa0bb2b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120831315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.120831315
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3882673249
Short name T341
Test name
Test status
Simulation time 448357106 ps
CPU time 18.54 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:46 PM PDT 24
Peak memory 247564 kb
Host smart-81bdf05e-dcc5-402b-badc-a2a5542bd7a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882673249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3882673249
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2588394283
Short name T326
Test name
Test status
Simulation time 21989676 ps
CPU time 1.72 seconds
Started Aug 17 04:47:28 PM PDT 24
Finished Aug 17 04:47:30 PM PDT 24
Peak memory 218236 kb
Host smart-cc0d0529-7c39-4916-a913-c2b96b9ed9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588394283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2588394283
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1531038149
Short name T98
Test name
Test status
Simulation time 174803220 ps
CPU time 9.31 seconds
Started Aug 17 04:47:47 PM PDT 24
Finished Aug 17 04:47:57 PM PDT 24
Peak memory 218864 kb
Host smart-7ae0740a-a0b7-4a32-b6a6-fb186206845b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531038149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1531038149
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.9656467
Short name T782
Test name
Test status
Simulation time 1113639869 ps
CPU time 11.17 seconds
Started Aug 17 04:47:26 PM PDT 24
Finished Aug 17 04:47:38 PM PDT 24
Peak memory 226056 kb
Host smart-bce881c6-31ac-4d1c-9164-11ebbf45c165
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9656467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_dige
st.9656467
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.586813915
Short name T852
Test name
Test status
Simulation time 948586414 ps
CPU time 10.24 seconds
Started Aug 17 04:47:26 PM PDT 24
Finished Aug 17 04:47:36 PM PDT 24
Peak memory 218184 kb
Host smart-5e00a3e2-296b-4baa-b6a7-4462d15e4135
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586813915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.586813915
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.4287401853
Short name T821
Test name
Test status
Simulation time 308608843 ps
CPU time 11.77 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:38 PM PDT 24
Peak memory 218400 kb
Host smart-543a96b5-d890-474d-912a-63b3717cac25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287401853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.4287401853
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1653390148
Short name T405
Test name
Test status
Simulation time 256072717 ps
CPU time 6.06 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:33 PM PDT 24
Peak memory 217660 kb
Host smart-c86ad9b5-662d-42f0-9e22-e9200ecabd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653390148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1653390148
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2950591550
Short name T755
Test name
Test status
Simulation time 359800761 ps
CPU time 23.04 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:50 PM PDT 24
Peak memory 250976 kb
Host smart-09d9a83f-ef5d-490d-b8ad-04a06e7b2903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950591550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2950591550
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.4100490038
Short name T683
Test name
Test status
Simulation time 77518347 ps
CPU time 3.51 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:30 PM PDT 24
Peak memory 222820 kb
Host smart-7b68e539-80f6-4050-a074-5c6a1c473edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100490038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.4100490038
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2562862484
Short name T863
Test name
Test status
Simulation time 6649790521 ps
CPU time 95.97 seconds
Started Aug 17 04:47:31 PM PDT 24
Finished Aug 17 04:49:07 PM PDT 24
Peak memory 276860 kb
Host smart-fa6c0046-a654-4f92-8793-ad7250849bef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562862484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2562862484
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.2069823384
Short name T564
Test name
Test status
Simulation time 3568394380 ps
CPU time 71.31 seconds
Started Aug 17 04:47:32 PM PDT 24
Finished Aug 17 04:48:43 PM PDT 24
Peak memory 269492 kb
Host smart-f1297930-73b1-482a-a1ce-16ac399efbb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2069823384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.2069823384
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.565095041
Short name T39
Test name
Test status
Simulation time 44965063 ps
CPU time 0.87 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:28 PM PDT 24
Peak memory 208968 kb
Host smart-b7b33853-2cb3-418a-afd0-234ef6c4e3d1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565095041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.565095041
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2369056972
Short name T386
Test name
Test status
Simulation time 21133814 ps
CPU time 0.98 seconds
Started Aug 17 04:47:56 PM PDT 24
Finished Aug 17 04:47:57 PM PDT 24
Peak memory 208968 kb
Host smart-a7ba19d4-dce7-4f68-a317-ae884fd7669b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369056972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2369056972
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2521392018
Short name T508
Test name
Test status
Simulation time 1356105530 ps
CPU time 4.98 seconds
Started Aug 17 04:47:31 PM PDT 24
Finished Aug 17 04:47:36 PM PDT 24
Peak memory 217672 kb
Host smart-de0767d7-a5ca-4fdd-a837-9313125fb1d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521392018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2521392018
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.395332485
Short name T586
Test name
Test status
Simulation time 2689088668 ps
CPU time 29.62 seconds
Started Aug 17 04:47:30 PM PDT 24
Finished Aug 17 04:47:59 PM PDT 24
Peak memory 218956 kb
Host smart-6bcaa8eb-e93b-427f-9ffe-33d9b57ebc6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395332485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.395332485
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3895648916
Short name T853
Test name
Test status
Simulation time 233415009 ps
CPU time 4.63 seconds
Started Aug 17 04:47:30 PM PDT 24
Finished Aug 17 04:47:35 PM PDT 24
Peak memory 223092 kb
Host smart-40fd206a-a645-41ae-ba74-002968573167
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895648916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3895648916
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.61124458
Short name T826
Test name
Test status
Simulation time 513260074 ps
CPU time 8.33 seconds
Started Aug 17 04:47:25 PM PDT 24
Finished Aug 17 04:47:33 PM PDT 24
Peak memory 217668 kb
Host smart-56088684-1d90-4796-98a1-b86cab305cb2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61124458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.61124458
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.768424525
Short name T430
Test name
Test status
Simulation time 5102094763 ps
CPU time 57.3 seconds
Started Aug 17 04:47:28 PM PDT 24
Finished Aug 17 04:48:26 PM PDT 24
Peak memory 267188 kb
Host smart-9c915842-b6ba-425c-b6bf-1962e984ed46
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768424525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.768424525
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1341146378
Short name T799
Test name
Test status
Simulation time 1557750617 ps
CPU time 12.83 seconds
Started Aug 17 04:47:26 PM PDT 24
Finished Aug 17 04:47:39 PM PDT 24
Peak memory 223888 kb
Host smart-8be24717-b34e-4f7c-b82b-c0c8c9b4267d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341146378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1341146378
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.904827176
Short name T566
Test name
Test status
Simulation time 352482272 ps
CPU time 3.49 seconds
Started Aug 17 04:47:25 PM PDT 24
Finished Aug 17 04:47:29 PM PDT 24
Peak memory 222540 kb
Host smart-0775b21f-5e89-4c5e-8e36-63ad1662fcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904827176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.904827176
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.830528858
Short name T769
Test name
Test status
Simulation time 358729920 ps
CPU time 12.82 seconds
Started Aug 17 04:47:53 PM PDT 24
Finished Aug 17 04:48:06 PM PDT 24
Peak memory 218972 kb
Host smart-b2460028-3af7-4f76-9ad5-0b643d9c28d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830528858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.830528858
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.175849967
Short name T665
Test name
Test status
Simulation time 331930654 ps
CPU time 12.55 seconds
Started Aug 17 04:47:26 PM PDT 24
Finished Aug 17 04:47:38 PM PDT 24
Peak memory 226064 kb
Host smart-a20af5ad-54f8-4657-902c-cfa372368e0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175849967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.175849967
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3564889798
Short name T327
Test name
Test status
Simulation time 516298671 ps
CPU time 15.57 seconds
Started Aug 17 04:47:26 PM PDT 24
Finished Aug 17 04:47:41 PM PDT 24
Peak memory 218188 kb
Host smart-e6f398ba-174c-4b9c-851b-a9820f480806
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564889798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3564889798
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.667769798
Short name T262
Test name
Test status
Simulation time 407936428 ps
CPU time 15.66 seconds
Started Aug 17 04:47:26 PM PDT 24
Finished Aug 17 04:47:41 PM PDT 24
Peak memory 218404 kb
Host smart-1b28487c-3ed6-4c8d-8dd2-f9ff48f10eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667769798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.667769798
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2086001457
Short name T378
Test name
Test status
Simulation time 66342976 ps
CPU time 1.28 seconds
Started Aug 17 04:47:29 PM PDT 24
Finished Aug 17 04:47:31 PM PDT 24
Peak memory 217712 kb
Host smart-4224d88d-336b-4a89-860f-4e90ded1b33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086001457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2086001457
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3310992120
Short name T622
Test name
Test status
Simulation time 248472085 ps
CPU time 23.95 seconds
Started Aug 17 04:47:24 PM PDT 24
Finished Aug 17 04:47:48 PM PDT 24
Peak memory 250872 kb
Host smart-0150c4e0-fa4e-453d-be2e-ba5f00cac61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310992120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3310992120
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2815770632
Short name T456
Test name
Test status
Simulation time 59639851 ps
CPU time 7.46 seconds
Started Aug 17 04:47:26 PM PDT 24
Finished Aug 17 04:47:34 PM PDT 24
Peak memory 250880 kb
Host smart-07cf1865-3992-4c21-a8c5-ab24b3f89b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815770632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2815770632
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1263485126
Short name T412
Test name
Test status
Simulation time 2117359124 ps
CPU time 77.99 seconds
Started Aug 17 04:47:31 PM PDT 24
Finished Aug 17 04:48:49 PM PDT 24
Peak memory 274136 kb
Host smart-46e6f089-99a5-4eb7-994a-5c0c2c17b54d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263485126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1263485126
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2268893366
Short name T136
Test name
Test status
Simulation time 3619914368 ps
CPU time 109.37 seconds
Started Aug 17 04:47:28 PM PDT 24
Finished Aug 17 04:49:17 PM PDT 24
Peak memory 267468 kb
Host smart-8193aded-b65c-460f-a851-f6b2077e0b0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2268893366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2268893366
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.4088477616
Short name T624
Test name
Test status
Simulation time 17201107 ps
CPU time 1.11 seconds
Started Aug 17 04:47:27 PM PDT 24
Finished Aug 17 04:47:28 PM PDT 24
Peak memory 218028 kb
Host smart-50a058d0-1850-40df-b5b4-f4113172b048
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088477616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.4088477616
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1698698838
Short name T515
Test name
Test status
Simulation time 80623298 ps
CPU time 0.91 seconds
Started Aug 17 04:46:33 PM PDT 24
Finished Aug 17 04:46:34 PM PDT 24
Peak memory 208992 kb
Host smart-8a4fab03-b152-4abe-8987-813765a41c57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698698838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1698698838
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1271564561
Short name T642
Test name
Test status
Simulation time 13181525 ps
CPU time 0.79 seconds
Started Aug 17 04:46:41 PM PDT 24
Finished Aug 17 04:46:42 PM PDT 24
Peak memory 208588 kb
Host smart-5e03d047-b364-4867-907a-078d0a911d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271564561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1271564561
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.597628618
Short name T298
Test name
Test status
Simulation time 503881688 ps
CPU time 12.78 seconds
Started Aug 17 04:46:32 PM PDT 24
Finished Aug 17 04:46:45 PM PDT 24
Peak memory 226020 kb
Host smart-6e03482e-794c-4c8c-a3ba-61c3471eec9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597628618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.597628618
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1359585833
Short name T30
Test name
Test status
Simulation time 269710662 ps
CPU time 6.95 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:46:42 PM PDT 24
Peak memory 217280 kb
Host smart-ff4e402c-94f2-47f6-b307-243ed68231d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359585833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1359585833
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2764726047
Short name T49
Test name
Test status
Simulation time 1505272316 ps
CPU time 24.61 seconds
Started Aug 17 04:46:30 PM PDT 24
Finished Aug 17 04:46:55 PM PDT 24
Peak memory 218172 kb
Host smart-37cf7bd4-da57-4fc9-b7b2-1f2d26de7365
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764726047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2764726047
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2401779157
Short name T593
Test name
Test status
Simulation time 2027660674 ps
CPU time 10.65 seconds
Started Aug 17 04:46:32 PM PDT 24
Finished Aug 17 04:46:43 PM PDT 24
Peak memory 217688 kb
Host smart-faeda17c-da55-4c2b-88f6-99e77ef3c60a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401779157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
401779157
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1839944612
Short name T461
Test name
Test status
Simulation time 351474923 ps
CPU time 11.16 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:46:47 PM PDT 24
Peak memory 218284 kb
Host smart-455e7118-53c0-4b75-8aaa-64aa6018a220
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839944612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1839944612
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3731270930
Short name T841
Test name
Test status
Simulation time 2151794088 ps
CPU time 31.31 seconds
Started Aug 17 04:46:29 PM PDT 24
Finished Aug 17 04:47:01 PM PDT 24
Peak memory 217588 kb
Host smart-cda86647-fe95-4cc2-872a-7b1da2651e52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731270930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3731270930
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2214957247
Short name T342
Test name
Test status
Simulation time 1034587386 ps
CPU time 6.79 seconds
Started Aug 17 04:46:40 PM PDT 24
Finished Aug 17 04:46:46 PM PDT 24
Peak memory 217588 kb
Host smart-4e60b3c8-70d9-412a-a464-a7ee9e836ecf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214957247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2214957247
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4107319425
Short name T619
Test name
Test status
Simulation time 1357168291 ps
CPU time 60.09 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:47:35 PM PDT 24
Peak memory 267284 kb
Host smart-583a35c7-594d-44f2-9375-33336743a35d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107319425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.4107319425
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1165540161
Short name T610
Test name
Test status
Simulation time 1775203236 ps
CPU time 19.83 seconds
Started Aug 17 04:46:32 PM PDT 24
Finished Aug 17 04:46:52 PM PDT 24
Peak memory 250812 kb
Host smart-ea94f0e7-7ecd-48cc-8add-5ce256aaa062
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165540161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1165540161
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.426390721
Short name T583
Test name
Test status
Simulation time 249700965 ps
CPU time 2.89 seconds
Started Aug 17 04:46:28 PM PDT 24
Finished Aug 17 04:46:31 PM PDT 24
Peak memory 218292 kb
Host smart-bfba024f-26bf-4af3-8d95-75c951d185b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426390721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.426390721
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.407057446
Short name T643
Test name
Test status
Simulation time 711101206 ps
CPU time 15.98 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:46:51 PM PDT 24
Peak memory 214724 kb
Host smart-683763c8-8d3e-42ec-8b23-548ecfbd501f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407057446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.407057446
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1958655826
Short name T61
Test name
Test status
Simulation time 471299623 ps
CPU time 25.46 seconds
Started Aug 17 04:46:32 PM PDT 24
Finished Aug 17 04:46:58 PM PDT 24
Peak memory 267424 kb
Host smart-a19ff5ec-d324-483b-b89c-7b3273e9adde
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958655826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1958655826
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2692199220
Short name T476
Test name
Test status
Simulation time 843683317 ps
CPU time 21.32 seconds
Started Aug 17 04:46:31 PM PDT 24
Finished Aug 17 04:46:53 PM PDT 24
Peak memory 226144 kb
Host smart-a4cb0872-fd68-46b9-8205-841fafe28be3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692199220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2692199220
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.708380349
Short name T576
Test name
Test status
Simulation time 495941985 ps
CPU time 9.19 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:46:44 PM PDT 24
Peak memory 225932 kb
Host smart-039d05a6-8ea8-4f85-90ab-58f8003b1e1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708380349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.708380349
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3435852005
Short name T217
Test name
Test status
Simulation time 295634787 ps
CPU time 9.62 seconds
Started Aug 17 04:46:31 PM PDT 24
Finished Aug 17 04:46:41 PM PDT 24
Peak memory 225420 kb
Host smart-3ba3fc9f-5325-4ee1-b4b9-42de428968d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435852005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
435852005
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2331868339
Short name T540
Test name
Test status
Simulation time 2514121000 ps
CPU time 15.35 seconds
Started Aug 17 04:46:34 PM PDT 24
Finished Aug 17 04:46:49 PM PDT 24
Peak memory 218320 kb
Host smart-44f5fa3b-391c-4ceb-a662-6c5ec2d192b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331868339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2331868339
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2096561656
Short name T70
Test name
Test status
Simulation time 545043792 ps
CPU time 2.02 seconds
Started Aug 17 04:46:32 PM PDT 24
Finished Aug 17 04:46:35 PM PDT 24
Peak memory 217688 kb
Host smart-de270860-3ca0-45ab-bc27-9c1ce513c444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096561656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2096561656
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3177450395
Short name T97
Test name
Test status
Simulation time 417621517 ps
CPU time 30.68 seconds
Started Aug 17 04:46:37 PM PDT 24
Finished Aug 17 04:47:08 PM PDT 24
Peak memory 250880 kb
Host smart-c1331007-56d9-40f6-aacc-aac8707706d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177450395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3177450395
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.752194211
Short name T600
Test name
Test status
Simulation time 79307719 ps
CPU time 3.52 seconds
Started Aug 17 04:46:33 PM PDT 24
Finished Aug 17 04:46:36 PM PDT 24
Peak memory 226344 kb
Host smart-f86df453-88e2-4348-914a-f9d55eaf0756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752194211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.752194211
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1342140796
Short name T65
Test name
Test status
Simulation time 4452224745 ps
CPU time 74.64 seconds
Started Aug 17 04:46:34 PM PDT 24
Finished Aug 17 04:47:49 PM PDT 24
Peak memory 252484 kb
Host smart-48032899-875d-401e-804c-6798526ca877
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342140796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1342140796
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3411674555
Short name T48
Test name
Test status
Simulation time 37327280 ps
CPU time 0.96 seconds
Started Aug 17 04:46:36 PM PDT 24
Finished Aug 17 04:46:37 PM PDT 24
Peak memory 217708 kb
Host smart-f704a11c-2c31-4233-b839-8f85116a5dea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411674555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3411674555
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.915838955
Short name T90
Test name
Test status
Simulation time 87232624 ps
CPU time 1.19 seconds
Started Aug 17 04:47:44 PM PDT 24
Finished Aug 17 04:47:46 PM PDT 24
Peak memory 208968 kb
Host smart-e9b49d9f-9e09-4f55-804c-f2f8af783e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915838955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.915838955
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.4122049176
Short name T507
Test name
Test status
Simulation time 4133029554 ps
CPU time 13.32 seconds
Started Aug 17 04:47:34 PM PDT 24
Finished Aug 17 04:47:47 PM PDT 24
Peak memory 226092 kb
Host smart-2de54753-f3f2-4f2d-b4c0-02aaa2767407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122049176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.4122049176
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2568966256
Short name T615
Test name
Test status
Simulation time 647572718 ps
CPU time 1.8 seconds
Started Aug 17 04:47:35 PM PDT 24
Finished Aug 17 04:47:37 PM PDT 24
Peak memory 217624 kb
Host smart-57ebeb4b-3737-416a-9543-c50caa2ba749
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568966256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2568966256
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.4151133681
Short name T390
Test name
Test status
Simulation time 294939299 ps
CPU time 2.99 seconds
Started Aug 17 04:47:37 PM PDT 24
Finished Aug 17 04:47:40 PM PDT 24
Peak memory 222300 kb
Host smart-acbf06dc-31cb-48df-8dc7-697c05a623e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151133681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.4151133681
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2595546740
Short name T68
Test name
Test status
Simulation time 590112359 ps
CPU time 19.46 seconds
Started Aug 17 04:47:32 PM PDT 24
Finished Aug 17 04:47:51 PM PDT 24
Peak memory 226136 kb
Host smart-5ceb775d-a1bd-43b9-adcc-a944c8947bb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595546740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2595546740
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1188111489
Short name T511
Test name
Test status
Simulation time 1926654160 ps
CPU time 12.51 seconds
Started Aug 17 04:47:35 PM PDT 24
Finished Aug 17 04:47:47 PM PDT 24
Peak memory 225996 kb
Host smart-4db2b134-6ba9-4691-9537-c50b88a8d14e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188111489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1188111489
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1025882236
Short name T261
Test name
Test status
Simulation time 1628225917 ps
CPU time 7.46 seconds
Started Aug 17 04:47:37 PM PDT 24
Finished Aug 17 04:47:45 PM PDT 24
Peak memory 218316 kb
Host smart-dc123b42-d76c-412d-be95-872265a5ba57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025882236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1025882236
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.291348661
Short name T278
Test name
Test status
Simulation time 69950287 ps
CPU time 2.68 seconds
Started Aug 17 04:47:44 PM PDT 24
Finished Aug 17 04:47:47 PM PDT 24
Peak memory 214408 kb
Host smart-2055e91d-0c40-4f1f-acf8-e8039f5b5143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291348661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.291348661
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3537209442
Short name T777
Test name
Test status
Simulation time 464078643 ps
CPU time 23.82 seconds
Started Aug 17 04:47:36 PM PDT 24
Finished Aug 17 04:48:00 PM PDT 24
Peak memory 245484 kb
Host smart-1aaa9ec0-7753-4fe3-ba00-f87213ceedc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537209442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3537209442
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1799667033
Short name T158
Test name
Test status
Simulation time 68812918 ps
CPU time 8.96 seconds
Started Aug 17 04:47:49 PM PDT 24
Finished Aug 17 04:47:58 PM PDT 24
Peak memory 250892 kb
Host smart-4b8a3303-2116-4e2c-b553-92d8ba69165f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799667033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1799667033
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2473410205
Short name T447
Test name
Test status
Simulation time 12165318477 ps
CPU time 160.87 seconds
Started Aug 17 04:47:43 PM PDT 24
Finished Aug 17 04:50:24 PM PDT 24
Peak memory 273804 kb
Host smart-7c940e80-7223-4fb6-96bf-8e12b9acbc7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473410205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2473410205
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.719555704
Short name T250
Test name
Test status
Simulation time 19264060 ps
CPU time 1.05 seconds
Started Aug 17 04:47:49 PM PDT 24
Finished Aug 17 04:47:50 PM PDT 24
Peak memory 217744 kb
Host smart-603db702-7f21-4915-a1e7-cfae4555a254
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719555704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.719555704
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2940234707
Short name T638
Test name
Test status
Simulation time 20697180 ps
CPU time 1.03 seconds
Started Aug 17 04:47:34 PM PDT 24
Finished Aug 17 04:47:35 PM PDT 24
Peak memory 208916 kb
Host smart-7beca1dd-070f-41ff-917b-b8700a65a7aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940234707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2940234707
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.4284430027
Short name T870
Test name
Test status
Simulation time 3356081103 ps
CPU time 14.44 seconds
Started Aug 17 04:47:45 PM PDT 24
Finished Aug 17 04:48:00 PM PDT 24
Peak memory 219036 kb
Host smart-592b3de2-2ded-4248-873c-1173491a0951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284430027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.4284430027
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3093414635
Short name T495
Test name
Test status
Simulation time 725252703 ps
CPU time 9.7 seconds
Started Aug 17 04:47:35 PM PDT 24
Finished Aug 17 04:47:45 PM PDT 24
Peak memory 217760 kb
Host smart-1d30cddc-afb1-4b9f-8ceb-da9d5acd9e34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093414635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3093414635
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1771128814
Short name T469
Test name
Test status
Simulation time 294939965 ps
CPU time 2.69 seconds
Started Aug 17 04:47:37 PM PDT 24
Finished Aug 17 04:47:40 PM PDT 24
Peak memory 222576 kb
Host smart-9b9efaf1-75ea-466e-b6bf-5f6007deeeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771128814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1771128814
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2037200536
Short name T657
Test name
Test status
Simulation time 989367450 ps
CPU time 12.64 seconds
Started Aug 17 04:47:34 PM PDT 24
Finished Aug 17 04:47:47 PM PDT 24
Peak memory 226084 kb
Host smart-4a09b6c4-9a5d-4e0c-a586-f12c7fa3186e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037200536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2037200536
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.219040033
Short name T618
Test name
Test status
Simulation time 280058317 ps
CPU time 12.77 seconds
Started Aug 17 04:47:51 PM PDT 24
Finished Aug 17 04:48:04 PM PDT 24
Peak memory 225984 kb
Host smart-ac2a9f1e-185f-4133-87c7-216f3030c740
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219040033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.219040033
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.568221263
Short name T658
Test name
Test status
Simulation time 2094718611 ps
CPU time 12.25 seconds
Started Aug 17 04:47:46 PM PDT 24
Finished Aug 17 04:47:58 PM PDT 24
Peak memory 218176 kb
Host smart-88704607-9b64-418a-a300-8c60e4f6764f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568221263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.568221263
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2095723615
Short name T420
Test name
Test status
Simulation time 338996993 ps
CPU time 12.72 seconds
Started Aug 17 04:47:48 PM PDT 24
Finished Aug 17 04:48:01 PM PDT 24
Peak memory 218348 kb
Host smart-142009e4-440f-448f-ab06-5257c923fb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095723615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2095723615
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.619925828
Short name T589
Test name
Test status
Simulation time 126739439 ps
CPU time 1.8 seconds
Started Aug 17 04:47:36 PM PDT 24
Finished Aug 17 04:47:38 PM PDT 24
Peak memory 217884 kb
Host smart-f4a468e3-3017-4bed-8c72-0a134033ff2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619925828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.619925828
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.846224924
Short name T417
Test name
Test status
Simulation time 466196710 ps
CPU time 26.93 seconds
Started Aug 17 04:47:41 PM PDT 24
Finished Aug 17 04:48:08 PM PDT 24
Peak memory 250884 kb
Host smart-ed7f270e-754d-47e1-a9ff-3c0db5f90f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846224924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.846224924
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3282689267
Short name T632
Test name
Test status
Simulation time 202550926 ps
CPU time 2.73 seconds
Started Aug 17 04:47:52 PM PDT 24
Finished Aug 17 04:47:55 PM PDT 24
Peak memory 222508 kb
Host smart-1bfd9540-95bd-4a86-9d65-2ac211de4da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282689267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3282689267
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2319088932
Short name T764
Test name
Test status
Simulation time 3155335748 ps
CPU time 24.46 seconds
Started Aug 17 04:47:36 PM PDT 24
Finished Aug 17 04:48:00 PM PDT 24
Peak memory 218160 kb
Host smart-3c604385-0298-470d-a865-b7939491f122
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319088932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2319088932
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.2377353112
Short name T166
Test name
Test status
Simulation time 4117100750 ps
CPU time 118.85 seconds
Started Aug 17 04:47:36 PM PDT 24
Finished Aug 17 04:49:35 PM PDT 24
Peak memory 272768 kb
Host smart-3fd8944d-b2df-418f-a212-bdcfbfbe2d27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2377353112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.2377353112
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.56767336
Short name T402
Test name
Test status
Simulation time 12184787 ps
CPU time 0.9 seconds
Started Aug 17 04:48:00 PM PDT 24
Finished Aug 17 04:48:01 PM PDT 24
Peak memory 209180 kb
Host smart-4e8ce166-d02b-4ad4-8a50-87ea642b4de6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56767336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctr
l_volatile_unlock_smoke.56767336
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.696587710
Short name T542
Test name
Test status
Simulation time 278549993 ps
CPU time 11.12 seconds
Started Aug 17 04:47:39 PM PDT 24
Finished Aug 17 04:47:50 PM PDT 24
Peak memory 218172 kb
Host smart-7c437e43-ba65-4a21-89a5-8435acf32a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696587710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.696587710
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2046113446
Short name T27
Test name
Test status
Simulation time 4763979774 ps
CPU time 10.38 seconds
Started Aug 17 04:47:36 PM PDT 24
Finished Aug 17 04:47:46 PM PDT 24
Peak memory 217724 kb
Host smart-12ebf8eb-bd3e-4eae-8b9c-3659fcdf56d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046113446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2046113446
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.4284409700
Short name T173
Test name
Test status
Simulation time 250769558 ps
CPU time 2.38 seconds
Started Aug 17 04:47:33 PM PDT 24
Finished Aug 17 04:47:36 PM PDT 24
Peak memory 218188 kb
Host smart-edbf1095-6f40-44d4-828e-d54b9e2e9239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284409700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.4284409700
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3270271726
Short name T801
Test name
Test status
Simulation time 1423058812 ps
CPU time 9.88 seconds
Started Aug 17 04:47:43 PM PDT 24
Finished Aug 17 04:47:53 PM PDT 24
Peak memory 226128 kb
Host smart-15eec793-720b-4df8-a6ad-765f58bb3f40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270271726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3270271726
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3508067634
Short name T33
Test name
Test status
Simulation time 359147527 ps
CPU time 10.44 seconds
Started Aug 17 04:47:35 PM PDT 24
Finished Aug 17 04:47:46 PM PDT 24
Peak memory 226076 kb
Host smart-8cc7d591-3104-41f9-89fa-b92493c5071d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508067634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3508067634
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1358539454
Short name T541
Test name
Test status
Simulation time 504466118 ps
CPU time 10.33 seconds
Started Aug 17 04:47:36 PM PDT 24
Finished Aug 17 04:47:46 PM PDT 24
Peak memory 218200 kb
Host smart-a46487d2-12b6-4af9-b659-15f957509574
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358539454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1358539454
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.693753513
Short name T527
Test name
Test status
Simulation time 577037864 ps
CPU time 12.97 seconds
Started Aug 17 04:47:35 PM PDT 24
Finished Aug 17 04:47:48 PM PDT 24
Peak memory 218320 kb
Host smart-6847319c-9cc2-4358-b8b7-d3892e075fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693753513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.693753513
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1906090272
Short name T446
Test name
Test status
Simulation time 84746050 ps
CPU time 2.65 seconds
Started Aug 17 04:47:39 PM PDT 24
Finished Aug 17 04:47:42 PM PDT 24
Peak memory 217724 kb
Host smart-6daed467-f2ff-4e70-adc1-7878b9c9018d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906090272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1906090272
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1050537386
Short name T544
Test name
Test status
Simulation time 1359738619 ps
CPU time 31.52 seconds
Started Aug 17 04:47:51 PM PDT 24
Finished Aug 17 04:48:23 PM PDT 24
Peak memory 250860 kb
Host smart-1f6653ab-deb5-4aca-a16f-032e050bab45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050537386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1050537386
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1309952242
Short name T645
Test name
Test status
Simulation time 343559228 ps
CPU time 6.36 seconds
Started Aug 17 04:47:37 PM PDT 24
Finished Aug 17 04:47:43 PM PDT 24
Peak memory 246172 kb
Host smart-3de346a0-dade-4532-b067-0062792f27c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309952242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1309952242
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.865511936
Short name T668
Test name
Test status
Simulation time 46178030 ps
CPU time 0.92 seconds
Started Aug 17 04:47:36 PM PDT 24
Finished Aug 17 04:47:37 PM PDT 24
Peak memory 209080 kb
Host smart-36f0114c-55ec-4c6f-8f43-782f9694aa40
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865511936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.865511936
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2652866275
Short name T423
Test name
Test status
Simulation time 55792372 ps
CPU time 0.86 seconds
Started Aug 17 04:47:48 PM PDT 24
Finished Aug 17 04:47:49 PM PDT 24
Peak memory 208836 kb
Host smart-da1c0eb4-80f1-44c7-85cd-3689e29e88d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652866275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2652866275
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1201956695
Short name T598
Test name
Test status
Simulation time 2032469128 ps
CPU time 8.8 seconds
Started Aug 17 04:47:34 PM PDT 24
Finished Aug 17 04:47:43 PM PDT 24
Peak memory 218244 kb
Host smart-c5fe2e6d-9772-4dac-8ca3-d0c13ed05906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201956695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1201956695
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1584881364
Short name T179
Test name
Test status
Simulation time 4652478044 ps
CPU time 24.31 seconds
Started Aug 17 04:47:45 PM PDT 24
Finished Aug 17 04:48:10 PM PDT 24
Peak memory 217728 kb
Host smart-d2042ed8-97eb-4629-8def-16137be9ade8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584881364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1584881364
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1180703245
Short name T862
Test name
Test status
Simulation time 67790567 ps
CPU time 1.55 seconds
Started Aug 17 04:47:43 PM PDT 24
Finished Aug 17 04:47:45 PM PDT 24
Peak memory 218160 kb
Host smart-321cde35-84c0-4628-b0eb-714003ade5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180703245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1180703245
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.783318242
Short name T560
Test name
Test status
Simulation time 903333110 ps
CPU time 21.6 seconds
Started Aug 17 04:47:52 PM PDT 24
Finished Aug 17 04:48:14 PM PDT 24
Peak memory 226056 kb
Host smart-e8d3be8d-013c-4881-8e92-f1d9196619c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783318242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.783318242
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2083922038
Short name T787
Test name
Test status
Simulation time 550743673 ps
CPU time 11.08 seconds
Started Aug 17 04:47:49 PM PDT 24
Finished Aug 17 04:48:00 PM PDT 24
Peak memory 225908 kb
Host smart-aa97168d-cbdb-467a-954e-0847d7368042
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083922038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2083922038
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2488798256
Short name T621
Test name
Test status
Simulation time 204943484 ps
CPU time 6.68 seconds
Started Aug 17 04:47:45 PM PDT 24
Finished Aug 17 04:47:51 PM PDT 24
Peak memory 226088 kb
Host smart-d69f766f-2692-422e-9f90-b1eea1ff7727
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488798256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2488798256
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1561558217
Short name T389
Test name
Test status
Simulation time 737459374 ps
CPU time 12.43 seconds
Started Aug 17 04:47:41 PM PDT 24
Finished Aug 17 04:47:53 PM PDT 24
Peak memory 218312 kb
Host smart-27cf318b-902b-4579-851d-a29d9c0cb078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561558217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1561558217
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1342136120
Short name T543
Test name
Test status
Simulation time 76865833 ps
CPU time 4.04 seconds
Started Aug 17 04:47:35 PM PDT 24
Finished Aug 17 04:47:39 PM PDT 24
Peak memory 217736 kb
Host smart-5a80a1c4-1c4b-473c-bd34-28a08f693301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342136120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1342136120
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1414651254
Short name T809
Test name
Test status
Simulation time 997385092 ps
CPU time 27.8 seconds
Started Aug 17 04:47:34 PM PDT 24
Finished Aug 17 04:48:02 PM PDT 24
Peak memory 250924 kb
Host smart-258ffef0-e03a-47ef-a862-a0e6e664c4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414651254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1414651254
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.991784679
Short name T571
Test name
Test status
Simulation time 124671199 ps
CPU time 7.38 seconds
Started Aug 17 04:47:50 PM PDT 24
Finished Aug 17 04:47:57 PM PDT 24
Peak memory 250900 kb
Host smart-59a12b05-493e-4b62-96a5-73a21b44f5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991784679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.991784679
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1769822006
Short name T771
Test name
Test status
Simulation time 12667487 ps
CPU time 1.06 seconds
Started Aug 17 04:47:36 PM PDT 24
Finished Aug 17 04:47:37 PM PDT 24
Peak memory 211944 kb
Host smart-468d254e-3763-476d-8633-74c5917747f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769822006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1769822006
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1978287788
Short name T478
Test name
Test status
Simulation time 17200743 ps
CPU time 0.83 seconds
Started Aug 17 04:47:45 PM PDT 24
Finished Aug 17 04:47:46 PM PDT 24
Peak memory 208672 kb
Host smart-ca4631b3-38d6-4903-aee6-d04265d9cf4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978287788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1978287788
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3626416587
Short name T290
Test name
Test status
Simulation time 730955363 ps
CPU time 18.74 seconds
Started Aug 17 04:47:45 PM PDT 24
Finished Aug 17 04:48:04 PM PDT 24
Peak memory 226064 kb
Host smart-dc358082-9bd2-40b3-b970-96edd9e11bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626416587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3626416587
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2474217393
Short name T407
Test name
Test status
Simulation time 3690065142 ps
CPU time 9.56 seconds
Started Aug 17 04:47:49 PM PDT 24
Finished Aug 17 04:47:59 PM PDT 24
Peak memory 217808 kb
Host smart-fc7f4de8-58ef-497f-a851-d146c01b1a45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474217393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2474217393
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3884461041
Short name T815
Test name
Test status
Simulation time 143622192 ps
CPU time 3.64 seconds
Started Aug 17 04:47:52 PM PDT 24
Finished Aug 17 04:47:55 PM PDT 24
Peak memory 218260 kb
Host smart-e56abfb0-95d3-41bf-aa2a-0370f0d1c29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884461041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3884461041
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.4119957305
Short name T213
Test name
Test status
Simulation time 922559861 ps
CPU time 11.78 seconds
Started Aug 17 04:47:53 PM PDT 24
Finished Aug 17 04:48:05 PM PDT 24
Peak memory 226020 kb
Host smart-9847ff9e-427d-4c97-ae26-1c9a15d805f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119957305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.4119957305
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3485739284
Short name T502
Test name
Test status
Simulation time 269832593 ps
CPU time 9.18 seconds
Started Aug 17 04:48:07 PM PDT 24
Finished Aug 17 04:48:17 PM PDT 24
Peak memory 225996 kb
Host smart-e59100df-cef5-431c-bf9a-ff9f8f290759
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485739284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3485739284
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2724207892
Short name T304
Test name
Test status
Simulation time 418608595 ps
CPU time 11.21 seconds
Started Aug 17 04:47:43 PM PDT 24
Finished Aug 17 04:47:55 PM PDT 24
Peak memory 226052 kb
Host smart-e780a26e-1dd8-4987-9d9c-98cea039e78a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724207892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2724207892
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.4147500104
Short name T496
Test name
Test status
Simulation time 500498119 ps
CPU time 9.13 seconds
Started Aug 17 04:47:48 PM PDT 24
Finished Aug 17 04:47:57 PM PDT 24
Peak memory 218324 kb
Host smart-c7e1ae5b-d718-4a35-b47b-1b7cfdedae84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147500104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.4147500104
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3095898501
Short name T295
Test name
Test status
Simulation time 42008760 ps
CPU time 1.96 seconds
Started Aug 17 04:47:42 PM PDT 24
Finished Aug 17 04:47:44 PM PDT 24
Peak memory 217660 kb
Host smart-699a6a46-b00f-4a1b-9ef1-34094a4b55ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095898501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3095898501
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.504058870
Short name T410
Test name
Test status
Simulation time 851114602 ps
CPU time 29.93 seconds
Started Aug 17 04:47:49 PM PDT 24
Finished Aug 17 04:48:19 PM PDT 24
Peak memory 250948 kb
Host smart-c9f0b71d-08e9-47e3-948f-e55a2b9d230c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504058870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.504058870
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.99880298
Short name T738
Test name
Test status
Simulation time 141642553 ps
CPU time 3.79 seconds
Started Aug 17 04:47:48 PM PDT 24
Finished Aug 17 04:47:52 PM PDT 24
Peak memory 226308 kb
Host smart-e0c89c5c-718b-4acc-9cf9-eccb04e199a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99880298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.99880298
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2777853449
Short name T309
Test name
Test status
Simulation time 4263659686 ps
CPU time 107.06 seconds
Started Aug 17 04:47:46 PM PDT 24
Finished Aug 17 04:49:33 PM PDT 24
Peak memory 275532 kb
Host smart-6b4de00c-375e-4122-9f93-e435672cd531
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777853449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2777853449
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.4212469579
Short name T142
Test name
Test status
Simulation time 3433920680 ps
CPU time 66.81 seconds
Started Aug 17 04:47:52 PM PDT 24
Finished Aug 17 04:48:59 PM PDT 24
Peak memory 279244 kb
Host smart-0e91036a-ce38-4e3f-b3e4-48048dba2ae8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4212469579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.4212469579
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2943753374
Short name T506
Test name
Test status
Simulation time 32346397 ps
CPU time 0.79 seconds
Started Aug 17 04:47:44 PM PDT 24
Finished Aug 17 04:47:45 PM PDT 24
Peak memory 208932 kb
Host smart-7dee6c0a-4592-4232-9897-1d8c56d4dd7c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943753374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2943753374
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3062580609
Short name T834
Test name
Test status
Simulation time 103176836 ps
CPU time 1 seconds
Started Aug 17 04:47:56 PM PDT 24
Finished Aug 17 04:47:58 PM PDT 24
Peak memory 208908 kb
Host smart-8426e40e-c6dd-44f7-8d17-906bca6c67de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062580609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3062580609
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3611442635
Short name T840
Test name
Test status
Simulation time 1659415161 ps
CPU time 17.95 seconds
Started Aug 17 04:47:45 PM PDT 24
Finished Aug 17 04:48:03 PM PDT 24
Peak memory 218540 kb
Host smart-0a83d4d1-dd45-4d0c-b763-d61929ddc1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611442635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3611442635
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.89565814
Short name T177
Test name
Test status
Simulation time 3952879470 ps
CPU time 5.35 seconds
Started Aug 17 04:47:57 PM PDT 24
Finished Aug 17 04:48:02 PM PDT 24
Peak memory 217764 kb
Host smart-2120edcc-42e1-4a59-8390-85520492afc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89565814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.89565814
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1919528868
Short name T31
Test name
Test status
Simulation time 264315990 ps
CPU time 2.95 seconds
Started Aug 17 04:47:48 PM PDT 24
Finished Aug 17 04:47:51 PM PDT 24
Peak memory 222344 kb
Host smart-2fcd7a4f-b91d-4df9-8608-52be79ffd5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919528868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1919528868
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2264027050
Short name T52
Test name
Test status
Simulation time 964583984 ps
CPU time 15.29 seconds
Started Aug 17 04:47:49 PM PDT 24
Finished Aug 17 04:48:04 PM PDT 24
Peak memory 218204 kb
Host smart-27a6754e-4825-4c16-aa29-7df06b845e55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264027050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2264027050
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1421864519
Short name T792
Test name
Test status
Simulation time 277345048 ps
CPU time 9.71 seconds
Started Aug 17 04:47:55 PM PDT 24
Finished Aug 17 04:48:05 PM PDT 24
Peak memory 225988 kb
Host smart-74df55b4-0511-4bad-85d8-2af4f83de099
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421864519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1421864519
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2116820673
Short name T330
Test name
Test status
Simulation time 936031078 ps
CPU time 9.14 seconds
Started Aug 17 04:47:56 PM PDT 24
Finished Aug 17 04:48:05 PM PDT 24
Peak memory 225928 kb
Host smart-f75a1d62-70b6-416d-b8d2-2718c47c24fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116820673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2116820673
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.7888550
Short name T748
Test name
Test status
Simulation time 622003087 ps
CPU time 10.29 seconds
Started Aug 17 04:47:52 PM PDT 24
Finished Aug 17 04:48:03 PM PDT 24
Peak memory 218388 kb
Host smart-1ba58c6b-b98a-41a9-8a75-af9f24ead15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7888550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.7888550
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3548942933
Short name T143
Test name
Test status
Simulation time 96170149 ps
CPU time 3.06 seconds
Started Aug 17 04:47:59 PM PDT 24
Finished Aug 17 04:48:02 PM PDT 24
Peak memory 217756 kb
Host smart-87a65172-f762-45d2-89af-672bdca24453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548942933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3548942933
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3309465500
Short name T521
Test name
Test status
Simulation time 201636548 ps
CPU time 20.76 seconds
Started Aug 17 04:48:01 PM PDT 24
Finished Aug 17 04:48:22 PM PDT 24
Peak memory 250860 kb
Host smart-236f774f-b4d7-424a-8426-f3e19aa8e1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309465500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3309465500
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1338074848
Short name T283
Test name
Test status
Simulation time 159534537 ps
CPU time 5.87 seconds
Started Aug 17 04:47:50 PM PDT 24
Finished Aug 17 04:47:56 PM PDT 24
Peak memory 250452 kb
Host smart-822cf714-9c6f-4065-97f6-0e4e946f3011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338074848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1338074848
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.253680503
Short name T168
Test name
Test status
Simulation time 4437115932 ps
CPU time 24.59 seconds
Started Aug 17 04:47:54 PM PDT 24
Finished Aug 17 04:48:18 PM PDT 24
Peak memory 250732 kb
Host smart-65110795-8606-4208-8e3b-ccdf1faed6d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253680503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.253680503
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.130631980
Short name T77
Test name
Test status
Simulation time 14099332 ps
CPU time 1.16 seconds
Started Aug 17 04:47:48 PM PDT 24
Finished Aug 17 04:47:50 PM PDT 24
Peak memory 211900 kb
Host smart-77eff8a7-464e-4890-b8a2-0774e7c5e7e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130631980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.130631980
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.3930940420
Short name T700
Test name
Test status
Simulation time 30900515 ps
CPU time 1.16 seconds
Started Aug 17 04:47:50 PM PDT 24
Finished Aug 17 04:47:52 PM PDT 24
Peak memory 209036 kb
Host smart-a2ed048e-896a-4968-a926-3245e535c5f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930940420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3930940420
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.587322143
Short name T483
Test name
Test status
Simulation time 268072489 ps
CPU time 10.14 seconds
Started Aug 17 04:47:49 PM PDT 24
Finished Aug 17 04:47:59 PM PDT 24
Peak memory 218172 kb
Host smart-188de50a-cfa6-42eb-9b0f-974c565ef72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587322143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.587322143
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.818344699
Short name T9
Test name
Test status
Simulation time 2773276909 ps
CPU time 13.15 seconds
Started Aug 17 04:47:51 PM PDT 24
Finished Aug 17 04:48:04 PM PDT 24
Peak memory 217780 kb
Host smart-e8af98c2-43b6-44cf-8789-8b902b2014ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818344699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.818344699
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3689072334
Short name T203
Test name
Test status
Simulation time 239460788 ps
CPU time 2.73 seconds
Started Aug 17 04:47:47 PM PDT 24
Finished Aug 17 04:47:50 PM PDT 24
Peak memory 218356 kb
Host smart-0f54a82c-3183-4cd6-a350-686e529cd1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689072334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3689072334
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.657865401
Short name T606
Test name
Test status
Simulation time 1320261230 ps
CPU time 11.23 seconds
Started Aug 17 04:47:51 PM PDT 24
Finished Aug 17 04:48:02 PM PDT 24
Peak memory 226048 kb
Host smart-52909259-c359-42a8-859c-d0c34a17ded0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657865401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.657865401
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2258736265
Short name T294
Test name
Test status
Simulation time 942817459 ps
CPU time 17.93 seconds
Started Aug 17 04:47:43 PM PDT 24
Finished Aug 17 04:48:01 PM PDT 24
Peak memory 226044 kb
Host smart-ccba5c60-b5e9-43f9-a727-3f6576ff45a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258736265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2258736265
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2104691215
Short name T491
Test name
Test status
Simulation time 310623048 ps
CPU time 9.1 seconds
Started Aug 17 04:47:45 PM PDT 24
Finished Aug 17 04:47:54 PM PDT 24
Peak memory 218148 kb
Host smart-ec1f0323-5f05-40c1-a947-80f60eb63e25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104691215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2104691215
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2216312673
Short name T750
Test name
Test status
Simulation time 2994385962 ps
CPU time 10.14 seconds
Started Aug 17 04:47:48 PM PDT 24
Finished Aug 17 04:47:58 PM PDT 24
Peak memory 218376 kb
Host smart-4c956a43-e50e-4dac-bf55-b14647aea387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216312673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2216312673
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3367826055
Short name T78
Test name
Test status
Simulation time 77056054 ps
CPU time 0.97 seconds
Started Aug 17 04:47:44 PM PDT 24
Finished Aug 17 04:47:45 PM PDT 24
Peak memory 212100 kb
Host smart-3b99474e-c131-437f-af8a-b24ee7f748e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367826055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3367826055
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.116091206
Short name T398
Test name
Test status
Simulation time 687278575 ps
CPU time 26.65 seconds
Started Aug 17 04:47:51 PM PDT 24
Finished Aug 17 04:48:18 PM PDT 24
Peak memory 250836 kb
Host smart-5cc1ddae-92d3-4896-9c9f-16b862d1aad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116091206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.116091206
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1221756776
Short name T505
Test name
Test status
Simulation time 92305611 ps
CPU time 8.89 seconds
Started Aug 17 04:47:42 PM PDT 24
Finished Aug 17 04:47:51 PM PDT 24
Peak memory 250872 kb
Host smart-e322d413-3f73-4f67-8227-ba0206978bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221756776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1221756776
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1942911249
Short name T51
Test name
Test status
Simulation time 20171866673 ps
CPU time 167.54 seconds
Started Aug 17 04:47:56 PM PDT 24
Finished Aug 17 04:50:43 PM PDT 24
Peak memory 220972 kb
Host smart-d4dca631-fb0c-45f1-b2bd-45a1b66ff891
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942911249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1942911249
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.72774046
Short name T47
Test name
Test status
Simulation time 18038152 ps
CPU time 1.09 seconds
Started Aug 17 04:47:44 PM PDT 24
Finished Aug 17 04:47:45 PM PDT 24
Peak memory 217800 kb
Host smart-8b44acde-de8f-4913-8c71-5dc27d9144e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72774046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctr
l_volatile_unlock_smoke.72774046
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3347543879
Short name T559
Test name
Test status
Simulation time 52969840 ps
CPU time 1.01 seconds
Started Aug 17 04:48:10 PM PDT 24
Finished Aug 17 04:48:11 PM PDT 24
Peak memory 208952 kb
Host smart-0fc4083d-ca91-4811-9d8d-c0b738a2a308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347543879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3347543879
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.4123362662
Short name T296
Test name
Test status
Simulation time 862271144 ps
CPU time 8.72 seconds
Started Aug 17 04:47:51 PM PDT 24
Finished Aug 17 04:48:00 PM PDT 24
Peak memory 218328 kb
Host smart-49b08f88-48a4-40ff-9e15-eb6749dc53f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123362662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.4123362662
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.357258652
Short name T791
Test name
Test status
Simulation time 217366091 ps
CPU time 5.74 seconds
Started Aug 17 04:47:55 PM PDT 24
Finished Aug 17 04:48:01 PM PDT 24
Peak memory 217664 kb
Host smart-cc79ef98-8214-4fcb-89a9-9a5a99bf09cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357258652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.357258652
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3230984611
Short name T827
Test name
Test status
Simulation time 97901043 ps
CPU time 4.19 seconds
Started Aug 17 04:47:48 PM PDT 24
Finished Aug 17 04:47:52 PM PDT 24
Peak memory 222632 kb
Host smart-07f13fdb-f14d-4b1f-a619-cc2a3889e7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230984611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3230984611
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3589080328
Short name T299
Test name
Test status
Simulation time 1675648830 ps
CPU time 12.38 seconds
Started Aug 17 04:47:48 PM PDT 24
Finished Aug 17 04:48:01 PM PDT 24
Peak memory 219644 kb
Host smart-61ff39c2-97cf-4307-8260-8451d0ea07d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589080328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3589080328
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2100670261
Short name T802
Test name
Test status
Simulation time 874641402 ps
CPU time 16.47 seconds
Started Aug 17 04:47:44 PM PDT 24
Finished Aug 17 04:48:01 PM PDT 24
Peak memory 225972 kb
Host smart-76e35b15-d3fb-4d17-a30c-1fb6c60e434c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100670261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2100670261
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1264179287
Short name T690
Test name
Test status
Simulation time 386203796 ps
CPU time 10.43 seconds
Started Aug 17 04:47:46 PM PDT 24
Finished Aug 17 04:47:56 PM PDT 24
Peak memory 226080 kb
Host smart-80051585-eb5f-4662-a6d5-a809d695b65e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264179287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1264179287
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.257888187
Short name T223
Test name
Test status
Simulation time 493256249 ps
CPU time 10.79 seconds
Started Aug 17 04:47:48 PM PDT 24
Finished Aug 17 04:47:59 PM PDT 24
Peak memory 218096 kb
Host smart-d1a9f893-abd3-463f-bb38-c976efcfd8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257888187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.257888187
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2865532419
Short name T82
Test name
Test status
Simulation time 81215536 ps
CPU time 0.97 seconds
Started Aug 17 04:47:49 PM PDT 24
Finished Aug 17 04:47:50 PM PDT 24
Peak memory 211960 kb
Host smart-89c60d3b-7bfe-4e53-acfd-07f3f5cb1f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865532419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2865532419
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1847654332
Short name T650
Test name
Test status
Simulation time 309207270 ps
CPU time 16.69 seconds
Started Aug 17 04:47:44 PM PDT 24
Finished Aug 17 04:48:00 PM PDT 24
Peak memory 250960 kb
Host smart-8cc8b9ac-8b16-4abe-bef1-af6a330b2508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847654332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1847654332
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1642684009
Short name T470
Test name
Test status
Simulation time 93517865 ps
CPU time 7.2 seconds
Started Aug 17 04:47:50 PM PDT 24
Finished Aug 17 04:47:57 PM PDT 24
Peak memory 242580 kb
Host smart-5c874fdc-e212-4c9f-9aea-d7b029de923c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642684009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1642684009
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2064243898
Short name T332
Test name
Test status
Simulation time 25771294040 ps
CPU time 103.61 seconds
Started Aug 17 04:47:58 PM PDT 24
Finished Aug 17 04:49:41 PM PDT 24
Peak memory 250600 kb
Host smart-e31f2753-a3ee-4d6a-acaa-53d3238fb2f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064243898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2064243898
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.1647460661
Short name T91
Test name
Test status
Simulation time 25160642268 ps
CPU time 47.62 seconds
Started Aug 17 04:48:06 PM PDT 24
Finished Aug 17 04:48:54 PM PDT 24
Peak memory 259316 kb
Host smart-889c39cf-c64a-47d0-9deb-9864ef63dd65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1647460661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.1647460661
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.810621522
Short name T465
Test name
Test status
Simulation time 12773471 ps
CPU time 0.85 seconds
Started Aug 17 04:48:00 PM PDT 24
Finished Aug 17 04:48:01 PM PDT 24
Peak memory 208716 kb
Host smart-6ed08ef5-c162-4458-92b0-258a398c7c31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810621522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.810621522
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3099190838
Short name T308
Test name
Test status
Simulation time 594769456 ps
CPU time 19.98 seconds
Started Aug 17 04:47:52 PM PDT 24
Finished Aug 17 04:48:12 PM PDT 24
Peak memory 218136 kb
Host smart-e020981a-1f0a-49fc-8a97-a791b71b6cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099190838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3099190838
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3254023713
Short name T652
Test name
Test status
Simulation time 850774665 ps
CPU time 8.13 seconds
Started Aug 17 04:48:06 PM PDT 24
Finished Aug 17 04:48:14 PM PDT 24
Peak memory 217676 kb
Host smart-8b2d2af2-e845-4324-bce3-eab7bc5d3afd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254023713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3254023713
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2597776010
Short name T635
Test name
Test status
Simulation time 95253449 ps
CPU time 1.84 seconds
Started Aug 17 04:47:58 PM PDT 24
Finished Aug 17 04:47:59 PM PDT 24
Peak memory 222208 kb
Host smart-11f9444e-1fae-471d-a906-4086d14c12a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597776010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2597776010
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3665947791
Short name T648
Test name
Test status
Simulation time 171742657 ps
CPU time 7.42 seconds
Started Aug 17 04:47:56 PM PDT 24
Finished Aug 17 04:48:03 PM PDT 24
Peak memory 218344 kb
Host smart-7b0e4076-530a-4863-bde5-3a2eaaac61e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665947791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3665947791
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3110703569
Short name T494
Test name
Test status
Simulation time 897770981 ps
CPU time 7 seconds
Started Aug 17 04:48:05 PM PDT 24
Finished Aug 17 04:48:12 PM PDT 24
Peak memory 226264 kb
Host smart-d62e241b-33c1-42c2-b5ce-46a591aab161
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110703569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3110703569
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2326052112
Short name T816
Test name
Test status
Simulation time 567618916 ps
CPU time 7.29 seconds
Started Aug 17 04:47:57 PM PDT 24
Finished Aug 17 04:48:04 PM PDT 24
Peak memory 218180 kb
Host smart-54899368-71c1-41f8-80dd-ea0552dc30ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326052112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2326052112
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.571489707
Short name T400
Test name
Test status
Simulation time 3108440269 ps
CPU time 13.46 seconds
Started Aug 17 04:48:06 PM PDT 24
Finished Aug 17 04:48:20 PM PDT 24
Peak memory 218412 kb
Host smart-47a4d001-5db7-4870-9a86-4d85e39ead6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571489707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.571489707
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3958188383
Short name T699
Test name
Test status
Simulation time 81292743 ps
CPU time 2.91 seconds
Started Aug 17 04:47:54 PM PDT 24
Finished Aug 17 04:47:57 PM PDT 24
Peak memory 217748 kb
Host smart-a612deb1-679a-4d59-877c-1d6dc3fcc275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958188383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3958188383
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.862554032
Short name T695
Test name
Test status
Simulation time 913718460 ps
CPU time 23.31 seconds
Started Aug 17 04:48:04 PM PDT 24
Finished Aug 17 04:48:28 PM PDT 24
Peak memory 250800 kb
Host smart-91ee33ac-235b-47be-8e78-230d64632cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862554032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.862554032
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2967480648
Short name T534
Test name
Test status
Simulation time 267003807 ps
CPU time 4.62 seconds
Started Aug 17 04:47:57 PM PDT 24
Finished Aug 17 04:48:02 PM PDT 24
Peak memory 222992 kb
Host smart-f9b300a2-df06-415a-93e2-edfb6764e317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967480648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2967480648
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1159431896
Short name T490
Test name
Test status
Simulation time 6423336136 ps
CPU time 194.09 seconds
Started Aug 17 04:47:54 PM PDT 24
Finished Aug 17 04:51:09 PM PDT 24
Peak memory 250848 kb
Host smart-715f701c-2e4c-40f8-96da-7fe3ae4b4bc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159431896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1159431896
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.569792279
Short name T387
Test name
Test status
Simulation time 14471432 ps
CPU time 1.05 seconds
Started Aug 17 04:48:04 PM PDT 24
Finished Aug 17 04:48:06 PM PDT 24
Peak memory 211912 kb
Host smart-028a2980-4596-49ce-bb28-ae68f9332c30
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569792279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.569792279
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.885800367
Short name T498
Test name
Test status
Simulation time 308394412 ps
CPU time 0.99 seconds
Started Aug 17 04:48:03 PM PDT 24
Finished Aug 17 04:48:04 PM PDT 24
Peak memory 208944 kb
Host smart-6f5c8410-b3a5-418e-a5fb-3a112b3b3d4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885800367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.885800367
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3093500520
Short name T569
Test name
Test status
Simulation time 410720095 ps
CPU time 10.4 seconds
Started Aug 17 04:47:50 PM PDT 24
Finished Aug 17 04:48:01 PM PDT 24
Peak memory 218252 kb
Host smart-e515d3a6-e27a-451c-9540-a9f9b98534ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093500520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3093500520
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1230917061
Short name T682
Test name
Test status
Simulation time 282665303 ps
CPU time 4.38 seconds
Started Aug 17 04:48:07 PM PDT 24
Finished Aug 17 04:48:12 PM PDT 24
Peak memory 217696 kb
Host smart-297389ac-4ca3-4f4a-80a7-dc2173231606
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230917061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1230917061
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2841589649
Short name T489
Test name
Test status
Simulation time 81458317 ps
CPU time 3.05 seconds
Started Aug 17 04:47:51 PM PDT 24
Finished Aug 17 04:47:54 PM PDT 24
Peak memory 218240 kb
Host smart-e66fd786-ddee-4d34-9888-2f7cf8408116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841589649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2841589649
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.284940023
Short name T640
Test name
Test status
Simulation time 1137829974 ps
CPU time 15.3 seconds
Started Aug 17 04:47:50 PM PDT 24
Finished Aug 17 04:48:05 PM PDT 24
Peak memory 218984 kb
Host smart-e9a10a03-be72-4472-856e-e46a6a053661
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284940023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.284940023
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1106163315
Short name T381
Test name
Test status
Simulation time 1248487329 ps
CPU time 16.28 seconds
Started Aug 17 04:47:57 PM PDT 24
Finished Aug 17 04:48:13 PM PDT 24
Peak memory 225972 kb
Host smart-c2a2b219-0f1f-48b4-9cc5-c802a7f63e4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106163315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1106163315
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2988873630
Short name T207
Test name
Test status
Simulation time 262500974 ps
CPU time 10.36 seconds
Started Aug 17 04:47:57 PM PDT 24
Finished Aug 17 04:48:07 PM PDT 24
Peak memory 225980 kb
Host smart-97dc244c-0f4a-4832-9a3a-2dce54084dc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988873630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2988873630
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1654720171
Short name T737
Test name
Test status
Simulation time 1078047857 ps
CPU time 8.22 seconds
Started Aug 17 04:47:50 PM PDT 24
Finished Aug 17 04:47:59 PM PDT 24
Peak memory 218316 kb
Host smart-01392c8d-621a-44e2-b97d-24d9a3981d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654720171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1654720171
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.209240461
Short name T315
Test name
Test status
Simulation time 98100719 ps
CPU time 2.31 seconds
Started Aug 17 04:48:01 PM PDT 24
Finished Aug 17 04:48:04 PM PDT 24
Peak memory 214144 kb
Host smart-53380ed8-e485-4837-92dd-9ca0c1dfeb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209240461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.209240461
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.172359039
Short name T631
Test name
Test status
Simulation time 178426982 ps
CPU time 19.74 seconds
Started Aug 17 04:47:59 PM PDT 24
Finished Aug 17 04:48:19 PM PDT 24
Peak memory 250980 kb
Host smart-b0dbda5d-e1e6-4589-8f52-feebab36fbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172359039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.172359039
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2527318527
Short name T795
Test name
Test status
Simulation time 421630310 ps
CPU time 3.1 seconds
Started Aug 17 04:47:56 PM PDT 24
Finished Aug 17 04:47:59 PM PDT 24
Peak memory 218340 kb
Host smart-5173f45d-eb7d-4127-8c8a-0201211dc363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527318527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2527318527
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.2868622635
Short name T664
Test name
Test status
Simulation time 5875999575 ps
CPU time 97 seconds
Started Aug 17 04:47:51 PM PDT 24
Finished Aug 17 04:49:28 PM PDT 24
Peak memory 273976 kb
Host smart-323cb476-028d-4521-9dcd-82ba1a4b2a29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2868622635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.2868622635
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.687663747
Short name T716
Test name
Test status
Simulation time 16435182 ps
CPU time 0.96 seconds
Started Aug 17 04:47:56 PM PDT 24
Finished Aug 17 04:47:57 PM PDT 24
Peak memory 212068 kb
Host smart-e526966c-b9cf-4806-8ff9-df5152a7285e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687663747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.687663747
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2601722721
Short name T677
Test name
Test status
Simulation time 17196808 ps
CPU time 0.87 seconds
Started Aug 17 04:46:37 PM PDT 24
Finished Aug 17 04:46:38 PM PDT 24
Peak memory 208852 kb
Host smart-39c9a1af-7e41-44e2-b259-ac123162a479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601722721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2601722721
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3071075821
Short name T50
Test name
Test status
Simulation time 903842223 ps
CPU time 10.93 seconds
Started Aug 17 04:46:34 PM PDT 24
Finished Aug 17 04:46:45 PM PDT 24
Peak memory 226116 kb
Host smart-e5342910-9d89-4049-8ed9-7386724c1cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071075821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3071075821
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.941287042
Short name T371
Test name
Test status
Simulation time 466711026 ps
CPU time 12 seconds
Started Aug 17 04:46:40 PM PDT 24
Finished Aug 17 04:46:52 PM PDT 24
Peak memory 217708 kb
Host smart-5de40685-02a4-4533-92c6-2c285e346111
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941287042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.941287042
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.968665978
Short name T312
Test name
Test status
Simulation time 5640039675 ps
CPU time 46.86 seconds
Started Aug 17 04:46:44 PM PDT 24
Finished Aug 17 04:47:31 PM PDT 24
Peak memory 218880 kb
Host smart-34bc2118-dfb1-4ad9-9a57-94a5af473add
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968665978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.968665978
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2103632572
Short name T8
Test name
Test status
Simulation time 1550357083 ps
CPU time 5.28 seconds
Started Aug 17 04:46:37 PM PDT 24
Finished Aug 17 04:46:43 PM PDT 24
Peak memory 217712 kb
Host smart-9eff5694-6ddf-42ad-836d-6cce105d8236
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103632572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
103632572
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.377824332
Short name T740
Test name
Test status
Simulation time 614670830 ps
CPU time 6.49 seconds
Started Aug 17 04:46:37 PM PDT 24
Finished Aug 17 04:46:44 PM PDT 24
Peak memory 223252 kb
Host smart-155fde40-3103-4e8a-b501-9367531cf4da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377824332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.377824332
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2248149105
Short name T5
Test name
Test status
Simulation time 1630944350 ps
CPU time 11.08 seconds
Started Aug 17 04:46:34 PM PDT 24
Finished Aug 17 04:46:45 PM PDT 24
Peak memory 217604 kb
Host smart-7d0c21b2-25ee-4d20-a30d-b678895257d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248149105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2248149105
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1646306570
Short name T472
Test name
Test status
Simulation time 639091588 ps
CPU time 5.72 seconds
Started Aug 17 04:46:34 PM PDT 24
Finished Aug 17 04:46:40 PM PDT 24
Peak memory 217608 kb
Host smart-a4bde528-a070-48a7-b8d6-8371e94ad463
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646306570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1646306570
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.721829816
Short name T443
Test name
Test status
Simulation time 1454711194 ps
CPU time 56.63 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:47:32 PM PDT 24
Peak memory 268960 kb
Host smart-19436abc-f9f4-4d40-9bbc-b7f590c6f9d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721829816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.721829816
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2184067575
Short name T99
Test name
Test status
Simulation time 1197090776 ps
CPU time 16.23 seconds
Started Aug 17 04:46:36 PM PDT 24
Finished Aug 17 04:46:52 PM PDT 24
Peak memory 226244 kb
Host smart-ac7183fb-efbb-4e6b-9234-baded7d35b61
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184067575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2184067575
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.881458868
Short name T451
Test name
Test status
Simulation time 121067097 ps
CPU time 3.41 seconds
Started Aug 17 04:46:33 PM PDT 24
Finished Aug 17 04:46:36 PM PDT 24
Peak memory 218092 kb
Host smart-7e21d7e4-2d55-4b7a-aa45-3cd8f23b0b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881458868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.881458868
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3203655265
Short name T79
Test name
Test status
Simulation time 514189386 ps
CPU time 7.27 seconds
Started Aug 17 04:46:33 PM PDT 24
Finished Aug 17 04:46:40 PM PDT 24
Peak memory 217496 kb
Host smart-524dd05d-4d83-4c84-ab04-0ba372f48fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203655265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3203655265
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1959995623
Short name T392
Test name
Test status
Simulation time 984894293 ps
CPU time 8.99 seconds
Started Aug 17 04:46:48 PM PDT 24
Finished Aug 17 04:46:57 PM PDT 24
Peak memory 225788 kb
Host smart-b93488b0-5384-4504-993d-4c15a5c52958
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959995623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1959995623
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.96868196
Short name T532
Test name
Test status
Simulation time 563109205 ps
CPU time 12.3 seconds
Started Aug 17 04:46:52 PM PDT 24
Finished Aug 17 04:47:04 PM PDT 24
Peak memory 226032 kb
Host smart-0785e083-3201-4ba1-8bec-3077057384ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96868196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dige
st.96868196
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3177249865
Short name T574
Test name
Test status
Simulation time 618181344 ps
CPU time 11.36 seconds
Started Aug 17 04:46:34 PM PDT 24
Finished Aug 17 04:46:46 PM PDT 24
Peak memory 218208 kb
Host smart-9fa6b2d6-0a5b-4769-88aa-e3ad319a9c93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177249865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
177249865
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3794028944
Short name T441
Test name
Test status
Simulation time 910593296 ps
CPU time 10.58 seconds
Started Aug 17 04:46:33 PM PDT 24
Finished Aug 17 04:46:43 PM PDT 24
Peak memory 218328 kb
Host smart-b6276d14-502e-4262-9161-9acfc5ebcffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794028944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3794028944
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2853253578
Short name T80
Test name
Test status
Simulation time 88278684 ps
CPU time 2.51 seconds
Started Aug 17 04:46:28 PM PDT 24
Finished Aug 17 04:46:30 PM PDT 24
Peak memory 217660 kb
Host smart-8a5572bc-4d5f-4704-afdd-f4c0fbf8fc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853253578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2853253578
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2000057737
Short name T630
Test name
Test status
Simulation time 231708775 ps
CPU time 25.08 seconds
Started Aug 17 04:46:33 PM PDT 24
Finished Aug 17 04:46:58 PM PDT 24
Peak memory 250964 kb
Host smart-0356c15a-3870-4659-8ac0-b467bf3736b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000057737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2000057737
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.986920228
Short name T375
Test name
Test status
Simulation time 229794813 ps
CPU time 2.89 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:46:38 PM PDT 24
Peak memory 222752 kb
Host smart-87261910-856f-4921-98c5-59c93a291b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986920228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.986920228
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.258746523
Short name T623
Test name
Test status
Simulation time 2479929877 ps
CPU time 60.12 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:47:35 PM PDT 24
Peak memory 276596 kb
Host smart-d495b6d2-3185-4814-8ad4-15960be35eca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258746523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.258746523
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.982108999
Short name T41
Test name
Test status
Simulation time 14671792 ps
CPU time 0.81 seconds
Started Aug 17 04:46:33 PM PDT 24
Finished Aug 17 04:46:34 PM PDT 24
Peak memory 208952 kb
Host smart-5bf468c8-dc18-4b1e-8350-1600e9d079f6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982108999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr
l_volatile_unlock_smoke.982108999
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1209934037
Short name T760
Test name
Test status
Simulation time 65161838 ps
CPU time 0.92 seconds
Started Aug 17 04:47:55 PM PDT 24
Finished Aug 17 04:47:56 PM PDT 24
Peak memory 209000 kb
Host smart-e723a6d4-283e-4410-b483-b1e62e1eb76b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209934037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1209934037
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3047862660
Short name T42
Test name
Test status
Simulation time 1072982843 ps
CPU time 11.68 seconds
Started Aug 17 04:47:57 PM PDT 24
Finished Aug 17 04:48:08 PM PDT 24
Peak memory 218176 kb
Host smart-cf3b5a3c-7afd-481b-b951-5d77ad00d657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047862660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3047862660
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1680047709
Short name T633
Test name
Test status
Simulation time 25799590 ps
CPU time 1.83 seconds
Started Aug 17 04:47:49 PM PDT 24
Finished Aug 17 04:47:51 PM PDT 24
Peak memory 218228 kb
Host smart-b85ce29a-f6e5-410b-a478-4c4e8d0253e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680047709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1680047709
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.386693961
Short name T531
Test name
Test status
Simulation time 324562236 ps
CPU time 12.7 seconds
Started Aug 17 04:47:54 PM PDT 24
Finished Aug 17 04:48:07 PM PDT 24
Peak memory 218880 kb
Host smart-710510de-73f8-436d-9f70-f8a160f11b1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386693961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.386693961
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3665602229
Short name T96
Test name
Test status
Simulation time 1322058398 ps
CPU time 21.84 seconds
Started Aug 17 04:48:00 PM PDT 24
Finished Aug 17 04:48:22 PM PDT 24
Peak memory 226020 kb
Host smart-53cec880-dc76-4e17-a7fe-fa35c3991af3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665602229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3665602229
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2718844258
Short name T226
Test name
Test status
Simulation time 1563025613 ps
CPU time 37.2 seconds
Started Aug 17 04:47:57 PM PDT 24
Finished Aug 17 04:48:34 PM PDT 24
Peak memory 250920 kb
Host smart-3b2888de-0c59-47f1-836e-80e483ee76b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718844258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2718844258
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2189261096
Short name T612
Test name
Test status
Simulation time 60726083 ps
CPU time 7.97 seconds
Started Aug 17 04:47:57 PM PDT 24
Finished Aug 17 04:48:05 PM PDT 24
Peak memory 250832 kb
Host smart-3937ffe9-6758-48e2-9cb2-82a1aa5ac5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189261096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2189261096
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3422393959
Short name T825
Test name
Test status
Simulation time 5087495953 ps
CPU time 113.09 seconds
Started Aug 17 04:48:00 PM PDT 24
Finished Aug 17 04:49:53 PM PDT 24
Peak memory 270256 kb
Host smart-99eaca06-1ef3-418d-8748-0daa5c546b4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422393959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3422393959
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.3980077384
Short name T770
Test name
Test status
Simulation time 1482984942 ps
CPU time 84.73 seconds
Started Aug 17 04:47:57 PM PDT 24
Finished Aug 17 04:49:22 PM PDT 24
Peak memory 250992 kb
Host smart-a7e968d8-5154-4bcb-8869-34fec8dc9da9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3980077384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.3980077384
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1617819942
Short name T708
Test name
Test status
Simulation time 195393002 ps
CPU time 1.01 seconds
Started Aug 17 04:48:02 PM PDT 24
Finished Aug 17 04:48:03 PM PDT 24
Peak memory 212056 kb
Host smart-8a23674a-1436-4d2f-aca5-ffbac9b5d7ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617819942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1617819942
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2942088931
Short name T662
Test name
Test status
Simulation time 98098330 ps
CPU time 1.02 seconds
Started Aug 17 04:48:09 PM PDT 24
Finished Aug 17 04:48:10 PM PDT 24
Peak memory 209016 kb
Host smart-2ccb0f93-ec84-4afe-bd50-5496a6df383d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942088931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2942088931
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2608794889
Short name T528
Test name
Test status
Simulation time 408488250 ps
CPU time 12.33 seconds
Started Aug 17 04:47:54 PM PDT 24
Finished Aug 17 04:48:06 PM PDT 24
Peak memory 218228 kb
Host smart-58d4134c-11d5-409a-94fa-90a558ac1d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608794889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2608794889
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2534998888
Short name T373
Test name
Test status
Simulation time 104741076 ps
CPU time 3.44 seconds
Started Aug 17 04:48:06 PM PDT 24
Finished Aug 17 04:48:10 PM PDT 24
Peak memory 217744 kb
Host smart-898538cb-26e2-49be-be36-05f54aae08e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534998888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2534998888
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.4292460548
Short name T11
Test name
Test status
Simulation time 132672880 ps
CPU time 2.34 seconds
Started Aug 17 04:48:02 PM PDT 24
Finished Aug 17 04:48:05 PM PDT 24
Peak memory 218248 kb
Host smart-b36e257f-c73a-45ce-8f03-75596e0a6e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292460548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.4292460548
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2949835237
Short name T766
Test name
Test status
Simulation time 4381488263 ps
CPU time 15.56 seconds
Started Aug 17 04:48:06 PM PDT 24
Finished Aug 17 04:48:22 PM PDT 24
Peak memory 220040 kb
Host smart-29177e37-3e05-478a-be6d-31ab7e9bbd9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949835237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2949835237
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.829911145
Short name T831
Test name
Test status
Simulation time 226068073 ps
CPU time 9.87 seconds
Started Aug 17 04:48:08 PM PDT 24
Finished Aug 17 04:48:18 PM PDT 24
Peak memory 225568 kb
Host smart-d90064fc-08a3-4ad9-b0d9-93b41d159e75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829911145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.829911145
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1706634427
Short name T463
Test name
Test status
Simulation time 1583738447 ps
CPU time 9.36 seconds
Started Aug 17 04:48:11 PM PDT 24
Finished Aug 17 04:48:20 PM PDT 24
Peak memory 226008 kb
Host smart-0eb2b5dc-d0ec-45a0-b64e-a5248b10a7d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706634427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1706634427
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.444635649
Short name T572
Test name
Test status
Simulation time 409722177 ps
CPU time 7.15 seconds
Started Aug 17 04:48:02 PM PDT 24
Finished Aug 17 04:48:09 PM PDT 24
Peak memory 218324 kb
Host smart-202c8348-0b2b-43ef-b86c-a9e4546a4856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444635649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.444635649
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2445661424
Short name T814
Test name
Test status
Simulation time 19108355 ps
CPU time 1.42 seconds
Started Aug 17 04:47:55 PM PDT 24
Finished Aug 17 04:47:56 PM PDT 24
Peak memory 217636 kb
Host smart-d6f6e3b1-b02b-44ca-b036-d38738529c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445661424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2445661424
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1820987113
Short name T573
Test name
Test status
Simulation time 260007165 ps
CPU time 28.28 seconds
Started Aug 17 04:48:05 PM PDT 24
Finished Aug 17 04:48:33 PM PDT 24
Peak memory 250812 kb
Host smart-892fde29-2cd7-4172-a56f-0cea025d1578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820987113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1820987113
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2248360649
Short name T100
Test name
Test status
Simulation time 4418309281 ps
CPU time 75.11 seconds
Started Aug 17 04:48:08 PM PDT 24
Finished Aug 17 04:49:24 PM PDT 24
Peak memory 283668 kb
Host smart-a21b79e8-85b1-4467-81ad-33d329edb104
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248360649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2248360649
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3269906855
Short name T480
Test name
Test status
Simulation time 14862478 ps
CPU time 1.21 seconds
Started Aug 17 04:47:58 PM PDT 24
Finished Aug 17 04:47:59 PM PDT 24
Peak memory 211944 kb
Host smart-af59d8e2-f40c-476c-93f7-8ebb58723c5c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269906855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3269906855
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2417571241
Short name T436
Test name
Test status
Simulation time 11232203 ps
CPU time 1 seconds
Started Aug 17 04:48:06 PM PDT 24
Finished Aug 17 04:48:08 PM PDT 24
Peak memory 208892 kb
Host smart-dedce474-d5ff-47e9-8208-bddb2e7b37a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417571241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2417571241
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2362652260
Short name T291
Test name
Test status
Simulation time 1184282310 ps
CPU time 23.42 seconds
Started Aug 17 04:48:08 PM PDT 24
Finished Aug 17 04:48:32 PM PDT 24
Peak memory 218248 kb
Host smart-7983b98f-41c8-4b43-b479-1c265ce609b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362652260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2362652260
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.231799528
Short name T7
Test name
Test status
Simulation time 6675906433 ps
CPU time 6.27 seconds
Started Aug 17 04:48:10 PM PDT 24
Finished Aug 17 04:48:17 PM PDT 24
Peak memory 217724 kb
Host smart-ef5426d4-dfa4-4dcc-8f8b-9f95248a931f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231799528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.231799528
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3351969276
Short name T609
Test name
Test status
Simulation time 85683012 ps
CPU time 2.43 seconds
Started Aug 17 04:48:01 PM PDT 24
Finished Aug 17 04:48:04 PM PDT 24
Peak memory 222420 kb
Host smart-52bb2daa-3316-4cb9-ab62-73b1d85696d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351969276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3351969276
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.2136332593
Short name T818
Test name
Test status
Simulation time 804011648 ps
CPU time 18.26 seconds
Started Aug 17 04:48:07 PM PDT 24
Finished Aug 17 04:48:26 PM PDT 24
Peak memory 219972 kb
Host smart-a4edd79e-ed9c-4ab6-aa19-809d995e397c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136332593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2136332593
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1151582492
Short name T35
Test name
Test status
Simulation time 519447095 ps
CPU time 11.13 seconds
Started Aug 17 04:48:00 PM PDT 24
Finished Aug 17 04:48:12 PM PDT 24
Peak memory 225976 kb
Host smart-af1f0eb8-63bb-41ba-8c7a-3e811b6d825d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151582492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1151582492
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2183900619
Short name T428
Test name
Test status
Simulation time 641504724 ps
CPU time 8.96 seconds
Started Aug 17 04:48:07 PM PDT 24
Finished Aug 17 04:48:16 PM PDT 24
Peak memory 218240 kb
Host smart-e9e0b54c-3f3c-41fd-9e1c-be6a62e60979
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183900619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2183900619
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.361805169
Short name T703
Test name
Test status
Simulation time 1562898135 ps
CPU time 11.43 seconds
Started Aug 17 04:48:03 PM PDT 24
Finished Aug 17 04:48:14 PM PDT 24
Peak memory 218332 kb
Host smart-055d3ff4-e505-47e3-93d7-edb64d294b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361805169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.361805169
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.713746103
Short name T549
Test name
Test status
Simulation time 160630148 ps
CPU time 3.26 seconds
Started Aug 17 04:48:02 PM PDT 24
Finished Aug 17 04:48:06 PM PDT 24
Peak memory 217744 kb
Host smart-c3d37d0d-6a18-4c85-9fb0-a6fce32acdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713746103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.713746103
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.4185632669
Short name T234
Test name
Test status
Simulation time 1087799933 ps
CPU time 27.71 seconds
Started Aug 17 04:48:10 PM PDT 24
Finished Aug 17 04:48:38 PM PDT 24
Peak memory 250880 kb
Host smart-6911d30a-116a-4b41-95c8-cf5d32d308f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185632669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.4185632669
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3558871797
Short name T803
Test name
Test status
Simulation time 64009361 ps
CPU time 7.71 seconds
Started Aug 17 04:48:06 PM PDT 24
Finished Aug 17 04:48:14 PM PDT 24
Peak memory 250964 kb
Host smart-dbb7d133-5ef2-426d-8cb7-a7bce58a5911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558871797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3558871797
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2193709346
Short name T284
Test name
Test status
Simulation time 13068353523 ps
CPU time 42.94 seconds
Started Aug 17 04:48:09 PM PDT 24
Finished Aug 17 04:48:52 PM PDT 24
Peak memory 228452 kb
Host smart-d7844aa0-170b-4ea4-8503-68c9b32a9208
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193709346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2193709346
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.3688436892
Short name T165
Test name
Test status
Simulation time 1562533445 ps
CPU time 33.91 seconds
Started Aug 17 04:48:08 PM PDT 24
Finished Aug 17 04:48:43 PM PDT 24
Peak memory 221764 kb
Host smart-e46125f3-ddc8-4957-a5d9-4af5ebaf445b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3688436892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.3688436892
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.4221660385
Short name T833
Test name
Test status
Simulation time 36284465 ps
CPU time 0.79 seconds
Started Aug 17 04:48:06 PM PDT 24
Finished Aug 17 04:48:07 PM PDT 24
Peak memory 208924 kb
Host smart-b9b2154a-525f-4b5b-9f96-2d79493950f1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221660385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.4221660385
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2626932217
Short name T517
Test name
Test status
Simulation time 56753682 ps
CPU time 1.29 seconds
Started Aug 17 04:48:13 PM PDT 24
Finished Aug 17 04:48:15 PM PDT 24
Peak memory 208920 kb
Host smart-e5eb8913-6865-4ddc-90ee-eb9f338a1197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626932217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2626932217
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1339008778
Short name T396
Test name
Test status
Simulation time 326658382 ps
CPU time 10.6 seconds
Started Aug 17 04:48:08 PM PDT 24
Finished Aug 17 04:48:19 PM PDT 24
Peak memory 218540 kb
Host smart-e8075c84-7b5f-450a-8fe2-d74b1b016aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339008778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1339008778
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.300043647
Short name T350
Test name
Test status
Simulation time 2242097168 ps
CPU time 5.87 seconds
Started Aug 17 04:48:11 PM PDT 24
Finished Aug 17 04:48:17 PM PDT 24
Peak memory 217696 kb
Host smart-1d45c0ed-f2cb-495c-8858-b33fad2b8c00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300043647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.300043647
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1826029767
Short name T356
Test name
Test status
Simulation time 679759539 ps
CPU time 2.28 seconds
Started Aug 17 04:48:11 PM PDT 24
Finished Aug 17 04:48:14 PM PDT 24
Peak memory 218404 kb
Host smart-68bc07f8-4081-4108-a1b9-8aaaa73c49a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826029767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1826029767
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1614203719
Short name T523
Test name
Test status
Simulation time 353115490 ps
CPU time 15.65 seconds
Started Aug 17 04:48:07 PM PDT 24
Finished Aug 17 04:48:23 PM PDT 24
Peak memory 219060 kb
Host smart-a92dce7e-d9cd-4d17-9406-61ac4c89ebff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614203719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1614203719
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2482818052
Short name T297
Test name
Test status
Simulation time 2323283064 ps
CPU time 13.73 seconds
Started Aug 17 04:48:08 PM PDT 24
Finished Aug 17 04:48:22 PM PDT 24
Peak memory 226096 kb
Host smart-77933f73-e30d-4b6b-b60c-daa2321e42fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482818052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2482818052
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2236554691
Short name T806
Test name
Test status
Simulation time 893924501 ps
CPU time 7.33 seconds
Started Aug 17 04:48:07 PM PDT 24
Finished Aug 17 04:48:15 PM PDT 24
Peak memory 218188 kb
Host smart-e600b76b-0050-450c-8875-aaff77c2f3ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236554691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2236554691
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1394935046
Short name T55
Test name
Test status
Simulation time 1871635869 ps
CPU time 8.83 seconds
Started Aug 17 04:48:12 PM PDT 24
Finished Aug 17 04:48:21 PM PDT 24
Peak memory 218364 kb
Host smart-c8f6addd-099c-4966-879c-5c99fe9061f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394935046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1394935046
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.373239580
Short name T433
Test name
Test status
Simulation time 599960830 ps
CPU time 2.29 seconds
Started Aug 17 04:48:11 PM PDT 24
Finished Aug 17 04:48:14 PM PDT 24
Peak memory 217452 kb
Host smart-7714ad08-e784-4330-9cef-eee02a2fea64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373239580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.373239580
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1863170661
Short name T743
Test name
Test status
Simulation time 1404810523 ps
CPU time 30.74 seconds
Started Aug 17 04:48:07 PM PDT 24
Finished Aug 17 04:48:37 PM PDT 24
Peak memory 250916 kb
Host smart-1cf03b3f-dee7-4ba7-888e-86521a2155f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863170661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1863170661
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3306234443
Short name T238
Test name
Test status
Simulation time 71828560 ps
CPU time 7.99 seconds
Started Aug 17 04:48:02 PM PDT 24
Finished Aug 17 04:48:10 PM PDT 24
Peak memory 250816 kb
Host smart-71635019-1e57-48a9-a337-cf35dc2c92e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306234443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3306234443
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.69654063
Short name T843
Test name
Test status
Simulation time 15212879002 ps
CPU time 144.68 seconds
Started Aug 17 04:48:08 PM PDT 24
Finished Aug 17 04:50:33 PM PDT 24
Peak memory 272908 kb
Host smart-032399be-90aa-4b36-a74a-3a49b2451e9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69654063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.lc_ctrl_stress_all.69654063
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3710440793
Short name T693
Test name
Test status
Simulation time 21894586 ps
CPU time 0.91 seconds
Started Aug 17 04:48:04 PM PDT 24
Finished Aug 17 04:48:05 PM PDT 24
Peak memory 212064 kb
Host smart-47f706ce-9634-46f6-b508-3afb457388e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710440793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3710440793
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3545453267
Short name T605
Test name
Test status
Simulation time 17485513 ps
CPU time 1.19 seconds
Started Aug 17 04:48:12 PM PDT 24
Finished Aug 17 04:48:14 PM PDT 24
Peak memory 209024 kb
Host smart-fe5782ee-be44-440b-bb22-1eddd7cea0e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545453267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3545453267
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.113485726
Short name T858
Test name
Test status
Simulation time 3020816702 ps
CPU time 28.15 seconds
Started Aug 17 04:48:10 PM PDT 24
Finished Aug 17 04:48:39 PM PDT 24
Peak memory 218936 kb
Host smart-240b9046-87f8-4a03-a5af-fc34d4e96a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113485726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.113485726
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1525510760
Short name T464
Test name
Test status
Simulation time 1448438221 ps
CPU time 9.06 seconds
Started Aug 17 04:48:06 PM PDT 24
Finished Aug 17 04:48:16 PM PDT 24
Peak memory 217660 kb
Host smart-e29cfb35-ad11-4834-8423-a2a3d438a67a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525510760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1525510760
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.393922168
Short name T773
Test name
Test status
Simulation time 207946416 ps
CPU time 2.21 seconds
Started Aug 17 04:48:06 PM PDT 24
Finished Aug 17 04:48:09 PM PDT 24
Peak memory 218248 kb
Host smart-020a062e-6868-45ee-9bcb-76df1fe92b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393922168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.393922168
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2153466272
Short name T666
Test name
Test status
Simulation time 253733014 ps
CPU time 10.64 seconds
Started Aug 17 04:48:08 PM PDT 24
Finished Aug 17 04:48:19 PM PDT 24
Peak memory 226028 kb
Host smart-491d99cc-e3e4-4a51-951f-13071979d4c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153466272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2153466272
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.999792361
Short name T172
Test name
Test status
Simulation time 281004376 ps
CPU time 11.22 seconds
Started Aug 17 04:48:11 PM PDT 24
Finished Aug 17 04:48:22 PM PDT 24
Peak memory 225912 kb
Host smart-8be15428-de36-499a-b783-9eabff7f9d8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999792361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.999792361
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3692987783
Short name T781
Test name
Test status
Simulation time 1770972320 ps
CPU time 9.81 seconds
Started Aug 17 04:48:08 PM PDT 24
Finished Aug 17 04:48:18 PM PDT 24
Peak memory 218284 kb
Host smart-934151c7-1c7f-427d-8849-d24c25c25bb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692987783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3692987783
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3931133844
Short name T59
Test name
Test status
Simulation time 366974734 ps
CPU time 14.01 seconds
Started Aug 17 04:48:00 PM PDT 24
Finished Aug 17 04:48:14 PM PDT 24
Peak memory 218332 kb
Host smart-83411c2b-fcd0-4a62-8dd1-ab2890c3be87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931133844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3931133844
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2569185271
Short name T488
Test name
Test status
Simulation time 64516954 ps
CPU time 3.18 seconds
Started Aug 17 04:48:10 PM PDT 24
Finished Aug 17 04:48:13 PM PDT 24
Peak memory 214828 kb
Host smart-37153fdc-b7ed-40a5-af95-440e6964e642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569185271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2569185271
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1163024369
Short name T553
Test name
Test status
Simulation time 1020360458 ps
CPU time 35.96 seconds
Started Aug 17 04:48:06 PM PDT 24
Finished Aug 17 04:48:42 PM PDT 24
Peak memory 250952 kb
Host smart-bc18a976-1544-48c3-ac4e-f47930b9d351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163024369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1163024369
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2979478670
Short name T594
Test name
Test status
Simulation time 257748427 ps
CPU time 9.73 seconds
Started Aug 17 04:48:02 PM PDT 24
Finished Aug 17 04:48:11 PM PDT 24
Peak memory 250960 kb
Host smart-e540aa55-aaf5-405f-962b-aace00209922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979478670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2979478670
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2257495179
Short name T848
Test name
Test status
Simulation time 5693306411 ps
CPU time 158.53 seconds
Started Aug 17 04:48:06 PM PDT 24
Finished Aug 17 04:50:45 PM PDT 24
Peak memory 227800 kb
Host smart-6938533f-44b7-48d5-8dac-bfb89420415f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257495179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2257495179
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1728291393
Short name T473
Test name
Test status
Simulation time 107066560 ps
CPU time 0.88 seconds
Started Aug 17 04:48:04 PM PDT 24
Finished Aug 17 04:48:05 PM PDT 24
Peak memory 211912 kb
Host smart-33353758-a957-472d-b927-e2fc8661fddd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728291393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1728291393
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1868578940
Short name T434
Test name
Test status
Simulation time 136819811 ps
CPU time 1.04 seconds
Started Aug 17 04:48:20 PM PDT 24
Finished Aug 17 04:48:21 PM PDT 24
Peak memory 208972 kb
Host smart-600bf907-5e8d-4472-a648-8a24d46e04ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868578940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1868578940
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.936143621
Short name T614
Test name
Test status
Simulation time 1123555167 ps
CPU time 12.71 seconds
Started Aug 17 04:48:09 PM PDT 24
Finished Aug 17 04:48:22 PM PDT 24
Peak memory 218340 kb
Host smart-db5448c0-9cbe-417a-8716-59891ec6539f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936143621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.936143621
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.399293374
Short name T522
Test name
Test status
Simulation time 585738934 ps
CPU time 4.26 seconds
Started Aug 17 04:48:15 PM PDT 24
Finished Aug 17 04:48:20 PM PDT 24
Peak memory 217324 kb
Host smart-cb985a29-682e-4998-aaf4-cb25e75f8fac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399293374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.399293374
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2630115866
Short name T414
Test name
Test status
Simulation time 74827282 ps
CPU time 2.1 seconds
Started Aug 17 04:48:11 PM PDT 24
Finished Aug 17 04:48:13 PM PDT 24
Peak memory 218248 kb
Host smart-28bf4c10-2d75-455d-a7d3-575a382262b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630115866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2630115866
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2487975473
Short name T844
Test name
Test status
Simulation time 1507058712 ps
CPU time 15.07 seconds
Started Aug 17 04:48:19 PM PDT 24
Finished Aug 17 04:48:34 PM PDT 24
Peak memory 219940 kb
Host smart-b93cffbb-6983-4c3b-b9ad-0bba9c3b12d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487975473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2487975473
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3625924719
Short name T719
Test name
Test status
Simulation time 1007222708 ps
CPU time 21.34 seconds
Started Aug 17 04:48:13 PM PDT 24
Finished Aug 17 04:48:34 PM PDT 24
Peak memory 225984 kb
Host smart-9e2208dc-c7d7-4204-a106-e430c6426187
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625924719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3625924719
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3923522315
Short name T346
Test name
Test status
Simulation time 2398696089 ps
CPU time 13.02 seconds
Started Aug 17 04:48:11 PM PDT 24
Finished Aug 17 04:48:24 PM PDT 24
Peak memory 218256 kb
Host smart-3168ff9a-c9ad-4d24-813d-b287f2c0ae37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923522315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3923522315
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2447196168
Short name T849
Test name
Test status
Simulation time 247979859 ps
CPU time 7.42 seconds
Started Aug 17 04:48:19 PM PDT 24
Finished Aug 17 04:48:26 PM PDT 24
Peak memory 225416 kb
Host smart-08ad341c-7ec9-4e45-840c-7527480f7af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447196168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2447196168
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3938411059
Short name T34
Test name
Test status
Simulation time 29042046 ps
CPU time 1.44 seconds
Started Aug 17 04:48:10 PM PDT 24
Finished Aug 17 04:48:12 PM PDT 24
Peak memory 213676 kb
Host smart-54e15961-831f-4e59-98cd-e6079b54b85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938411059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3938411059
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2539856721
Short name T361
Test name
Test status
Simulation time 217250356 ps
CPU time 33.05 seconds
Started Aug 17 04:48:02 PM PDT 24
Finished Aug 17 04:48:35 PM PDT 24
Peak memory 247412 kb
Host smart-8f5b3793-4466-49d0-9e7d-9ed2a57fc909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539856721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2539856721
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2569876912
Short name T383
Test name
Test status
Simulation time 45518140 ps
CPU time 7.9 seconds
Started Aug 17 04:47:59 PM PDT 24
Finished Aug 17 04:48:07 PM PDT 24
Peak memory 250880 kb
Host smart-e3b868f9-04b9-4266-99b5-86d7e455fd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569876912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2569876912
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.75571326
Short name T842
Test name
Test status
Simulation time 6611657997 ps
CPU time 68.09 seconds
Started Aug 17 04:48:17 PM PDT 24
Finished Aug 17 04:49:25 PM PDT 24
Peak memory 274480 kb
Host smart-cc304a4b-dc72-47b9-99a6-6a80569670b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75571326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.lc_ctrl_stress_all.75571326
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1141671808
Short name T867
Test name
Test status
Simulation time 11171833 ps
CPU time 0.92 seconds
Started Aug 17 04:48:08 PM PDT 24
Finished Aug 17 04:48:09 PM PDT 24
Peak memory 209116 kb
Host smart-7a634997-d57a-4204-a878-321bd4510d5c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141671808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1141671808
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.107705602
Short name T739
Test name
Test status
Simulation time 14013501 ps
CPU time 0.83 seconds
Started Aug 17 04:48:12 PM PDT 24
Finished Aug 17 04:48:13 PM PDT 24
Peak memory 208796 kb
Host smart-9cbbca67-618e-4646-87c1-f938f6a02ff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107705602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.107705602
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3516493308
Short name T366
Test name
Test status
Simulation time 358756396 ps
CPU time 15.68 seconds
Started Aug 17 04:48:22 PM PDT 24
Finished Aug 17 04:48:37 PM PDT 24
Peak memory 218408 kb
Host smart-110f4e4b-54ac-4956-88ff-2434b9fbbf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516493308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3516493308
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1978843244
Short name T29
Test name
Test status
Simulation time 6747406311 ps
CPU time 8.29 seconds
Started Aug 17 04:48:08 PM PDT 24
Finished Aug 17 04:48:17 PM PDT 24
Peak memory 217724 kb
Host smart-ecf6cb2f-1873-4669-a033-942ecb7f9f8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978843244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1978843244
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2041042382
Short name T824
Test name
Test status
Simulation time 274921202 ps
CPU time 3.45 seconds
Started Aug 17 04:48:17 PM PDT 24
Finished Aug 17 04:48:21 PM PDT 24
Peak memory 218252 kb
Host smart-2ab9f7eb-5c21-438f-b7e4-a5a90e2a38f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041042382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2041042382
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.675084567
Short name T337
Test name
Test status
Simulation time 2984460455 ps
CPU time 13.19 seconds
Started Aug 17 04:48:17 PM PDT 24
Finished Aug 17 04:48:30 PM PDT 24
Peak memory 226064 kb
Host smart-01c1bf88-2c1d-4e6c-814d-5fc2867e06ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675084567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.675084567
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3436348287
Short name T230
Test name
Test status
Simulation time 1232860286 ps
CPU time 13.44 seconds
Started Aug 17 04:48:12 PM PDT 24
Finished Aug 17 04:48:26 PM PDT 24
Peak memory 226036 kb
Host smart-b342d2de-1688-4608-a698-c02b74f4ceb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436348287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3436348287
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3296897025
Short name T751
Test name
Test status
Simulation time 335529046 ps
CPU time 11.74 seconds
Started Aug 17 04:48:13 PM PDT 24
Finished Aug 17 04:48:25 PM PDT 24
Peak memory 226268 kb
Host smart-32a5bcc9-93f5-4fa2-aed3-94fac7ccd6d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296897025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3296897025
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.4118914082
Short name T656
Test name
Test status
Simulation time 203142548 ps
CPU time 9.45 seconds
Started Aug 17 04:48:13 PM PDT 24
Finished Aug 17 04:48:22 PM PDT 24
Peak memory 226112 kb
Host smart-5c529404-85b2-4624-af23-38ad38be23b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118914082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.4118914082
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.656274019
Short name T319
Test name
Test status
Simulation time 33157274 ps
CPU time 2.35 seconds
Started Aug 17 04:48:12 PM PDT 24
Finished Aug 17 04:48:14 PM PDT 24
Peak memory 217680 kb
Host smart-0ca5edb2-d490-4e17-abbd-749bbe8e721c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656274019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.656274019
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1308457600
Short name T486
Test name
Test status
Simulation time 1071941743 ps
CPU time 22.95 seconds
Started Aug 17 04:48:11 PM PDT 24
Finished Aug 17 04:48:34 PM PDT 24
Peak memory 250856 kb
Host smart-31a437eb-58c4-4570-8c14-f812a2c374ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308457600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1308457600
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2029044207
Short name T32
Test name
Test status
Simulation time 141342534 ps
CPU time 7.95 seconds
Started Aug 17 04:48:10 PM PDT 24
Finished Aug 17 04:48:18 PM PDT 24
Peak memory 242852 kb
Host smart-5bed3a4b-f810-4941-bc51-4156f7c321a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029044207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2029044207
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.352743201
Short name T334
Test name
Test status
Simulation time 58660211374 ps
CPU time 112.5 seconds
Started Aug 17 04:48:20 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 283784 kb
Host smart-1eb6a6b6-b7b0-4982-a89a-cb8c545e7d9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352743201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.352743201
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.316048273
Short name T851
Test name
Test status
Simulation time 28408710 ps
CPU time 0.77 seconds
Started Aug 17 04:48:13 PM PDT 24
Finished Aug 17 04:48:14 PM PDT 24
Peak memory 209096 kb
Host smart-87bd1bd2-ed6f-4d28-b427-4d1f6c0d84a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316048273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.316048273
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3346064106
Short name T167
Test name
Test status
Simulation time 23936109 ps
CPU time 0.94 seconds
Started Aug 17 04:48:12 PM PDT 24
Finished Aug 17 04:48:13 PM PDT 24
Peak memory 208932 kb
Host smart-8df5f195-52d8-43a5-aa5e-ebbc317b663f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346064106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3346064106
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2065024596
Short name T307
Test name
Test status
Simulation time 200954682 ps
CPU time 10.32 seconds
Started Aug 17 04:48:16 PM PDT 24
Finished Aug 17 04:48:26 PM PDT 24
Peak memory 218248 kb
Host smart-8bdc1d8f-4d89-4e47-905c-f676798818da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065024596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2065024596
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3022319181
Short name T794
Test name
Test status
Simulation time 591187126 ps
CPU time 6.28 seconds
Started Aug 17 04:48:15 PM PDT 24
Finished Aug 17 04:48:21 PM PDT 24
Peak memory 217676 kb
Host smart-e21b9ef6-4708-4cb9-a4ca-19ab5a2d466f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022319181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3022319181
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2076909825
Short name T596
Test name
Test status
Simulation time 41489068 ps
CPU time 2.78 seconds
Started Aug 17 04:48:10 PM PDT 24
Finished Aug 17 04:48:13 PM PDT 24
Peak memory 222404 kb
Host smart-c3dbde3d-1357-4c76-a3d7-90d88b56818a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076909825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2076909825
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3211998954
Short name T349
Test name
Test status
Simulation time 407315379 ps
CPU time 17.05 seconds
Started Aug 17 04:48:11 PM PDT 24
Finished Aug 17 04:48:28 PM PDT 24
Peak memory 226140 kb
Host smart-08b19e8c-ddc8-4d92-8665-0bf23480ef5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211998954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3211998954
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1081589781
Short name T639
Test name
Test status
Simulation time 536305136 ps
CPU time 18.86 seconds
Started Aug 17 04:48:20 PM PDT 24
Finished Aug 17 04:48:38 PM PDT 24
Peak memory 226048 kb
Host smart-fad8b1eb-450e-4c2a-9f1c-f49aa92854e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081589781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1081589781
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.638623602
Short name T859
Test name
Test status
Simulation time 703235570 ps
CPU time 12.87 seconds
Started Aug 17 04:48:15 PM PDT 24
Finished Aug 17 04:48:28 PM PDT 24
Peak memory 226048 kb
Host smart-af1121e4-e996-4986-b413-265b36faecbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638623602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.638623602
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3928498875
Short name T530
Test name
Test status
Simulation time 325296716 ps
CPU time 12.42 seconds
Started Aug 17 04:48:13 PM PDT 24
Finished Aug 17 04:48:25 PM PDT 24
Peak memory 226068 kb
Host smart-6f751855-420e-4fd2-b2d3-0ebaac219749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928498875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3928498875
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1441475116
Short name T587
Test name
Test status
Simulation time 166416158 ps
CPU time 6.88 seconds
Started Aug 17 04:48:08 PM PDT 24
Finished Aug 17 04:48:15 PM PDT 24
Peak memory 217632 kb
Host smart-ffed0d22-f8c2-448c-87e4-c846a3953cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441475116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1441475116
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.4120187323
Short name T654
Test name
Test status
Simulation time 3775257897 ps
CPU time 22.33 seconds
Started Aug 17 04:48:09 PM PDT 24
Finished Aug 17 04:48:32 PM PDT 24
Peak memory 250916 kb
Host smart-c88ac4ec-97a1-4ded-b755-33fb000c116f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120187323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.4120187323
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1380979017
Short name T714
Test name
Test status
Simulation time 593843564 ps
CPU time 9.62 seconds
Started Aug 17 04:48:14 PM PDT 24
Finished Aug 17 04:48:24 PM PDT 24
Peak memory 250832 kb
Host smart-c077d3ff-9a97-433d-8fbd-0d6d71a0f99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380979017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1380979017
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2108088053
Short name T533
Test name
Test status
Simulation time 56270018817 ps
CPU time 278.42 seconds
Started Aug 17 04:48:09 PM PDT 24
Finished Aug 17 04:52:47 PM PDT 24
Peak memory 282524 kb
Host smart-a6f9ba4f-7dcd-437c-a630-ebbca86ca49d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108088053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2108088053
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1613309283
Short name T768
Test name
Test status
Simulation time 4272055630 ps
CPU time 37.08 seconds
Started Aug 17 04:48:12 PM PDT 24
Finished Aug 17 04:48:50 PM PDT 24
Peak memory 259000 kb
Host smart-561584d6-0555-4e3c-816d-fab47d811d08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1613309283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.1613309283
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1765791727
Short name T797
Test name
Test status
Simulation time 14068126 ps
CPU time 1.11 seconds
Started Aug 17 04:48:12 PM PDT 24
Finished Aug 17 04:48:13 PM PDT 24
Peak memory 212064 kb
Host smart-dac29025-05b2-4df5-b06e-f44d6c58a24e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765791727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1765791727
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1602852531
Short name T73
Test name
Test status
Simulation time 18905985 ps
CPU time 1.15 seconds
Started Aug 17 04:48:17 PM PDT 24
Finished Aug 17 04:48:18 PM PDT 24
Peak memory 208892 kb
Host smart-108d7169-5685-49b4-a9a4-91a5f310be95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602852531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1602852531
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1729625523
Short name T338
Test name
Test status
Simulation time 9054209961 ps
CPU time 17.03 seconds
Started Aug 17 04:48:11 PM PDT 24
Finished Aug 17 04:48:28 PM PDT 24
Peak memory 218376 kb
Host smart-e054a36c-7cf2-4bed-89b3-77477a69f2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729625523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1729625523
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3015482892
Short name T388
Test name
Test status
Simulation time 476293972 ps
CPU time 6.42 seconds
Started Aug 17 04:48:12 PM PDT 24
Finished Aug 17 04:48:19 PM PDT 24
Peak memory 217664 kb
Host smart-9a6101ff-8c0b-45bf-8c0c-e39de336352c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015482892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3015482892
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1003378048
Short name T231
Test name
Test status
Simulation time 141684381 ps
CPU time 3.4 seconds
Started Aug 17 04:48:16 PM PDT 24
Finished Aug 17 04:48:19 PM PDT 24
Peak memory 218324 kb
Host smart-12da9b3d-31a4-41cd-8a6f-4d80e689f6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003378048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1003378048
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1086045718
Short name T603
Test name
Test status
Simulation time 846051392 ps
CPU time 9.83 seconds
Started Aug 17 04:48:13 PM PDT 24
Finished Aug 17 04:48:23 PM PDT 24
Peak memory 218472 kb
Host smart-bdcfd38d-a91d-4533-85f4-fa1ce3a7c54a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086045718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1086045718
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.4005249243
Short name T248
Test name
Test status
Simulation time 497008539 ps
CPU time 9.14 seconds
Started Aug 17 04:48:13 PM PDT 24
Finished Aug 17 04:48:22 PM PDT 24
Peak memory 226040 kb
Host smart-4a84b1be-6904-4e33-b87e-e8bc9831a703
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005249243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.4005249243
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3562960117
Short name T271
Test name
Test status
Simulation time 651972610 ps
CPU time 11.85 seconds
Started Aug 17 04:48:21 PM PDT 24
Finished Aug 17 04:48:33 PM PDT 24
Peak memory 218216 kb
Host smart-0bdc19ec-5ee8-4f4e-a494-a6f1c4d969fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562960117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3562960117
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2154955959
Short name T56
Test name
Test status
Simulation time 370820947 ps
CPU time 8.84 seconds
Started Aug 17 04:48:13 PM PDT 24
Finished Aug 17 04:48:22 PM PDT 24
Peak memory 218308 kb
Host smart-6e807f8c-fbd4-435f-87fb-2b8b3805975f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154955959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2154955959
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.415134638
Short name T170
Test name
Test status
Simulation time 24476467 ps
CPU time 1.4 seconds
Started Aug 17 04:48:12 PM PDT 24
Finished Aug 17 04:48:14 PM PDT 24
Peak memory 217656 kb
Host smart-a07853b0-7615-42b3-be41-cb3b38a2fab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415134638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.415134638
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2734897709
Short name T545
Test name
Test status
Simulation time 241663673 ps
CPU time 23.63 seconds
Started Aug 17 04:48:16 PM PDT 24
Finished Aug 17 04:48:40 PM PDT 24
Peak memory 250912 kb
Host smart-6d94a5ba-2717-4e91-ac84-21de151399aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734897709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2734897709
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3961263384
Short name T406
Test name
Test status
Simulation time 573182504 ps
CPU time 6.14 seconds
Started Aug 17 04:48:10 PM PDT 24
Finished Aug 17 04:48:16 PM PDT 24
Peak memory 246676 kb
Host smart-8faabb7e-7a41-4678-a54a-0183bfd0a6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961263384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3961263384
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.35391241
Short name T314
Test name
Test status
Simulation time 24898933631 ps
CPU time 99.09 seconds
Started Aug 17 04:48:16 PM PDT 24
Finished Aug 17 04:49:56 PM PDT 24
Peak memory 250940 kb
Host smart-dba09814-b25d-4e4a-a68d-de6309aec613
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35391241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.lc_ctrl_stress_all.35391241
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.1895504079
Short name T744
Test name
Test status
Simulation time 2459544206 ps
CPU time 78.79 seconds
Started Aug 17 04:48:17 PM PDT 24
Finished Aug 17 04:49:36 PM PDT 24
Peak memory 276216 kb
Host smart-afab55cf-f25f-4efe-9f0b-29b408cd7271
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1895504079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.1895504079
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3984579924
Short name T321
Test name
Test status
Simulation time 13613709 ps
CPU time 0.98 seconds
Started Aug 17 04:48:17 PM PDT 24
Finished Aug 17 04:48:18 PM PDT 24
Peak memory 209004 kb
Host smart-645a5f5b-7f3d-4698-a381-67e52fbda67b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984579924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3984579924
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1099383003
Short name T675
Test name
Test status
Simulation time 15175989 ps
CPU time 0.84 seconds
Started Aug 17 04:48:23 PM PDT 24
Finished Aug 17 04:48:24 PM PDT 24
Peak memory 208716 kb
Host smart-31ce4160-1a96-40f2-89e1-266ffcb6c3b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099383003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1099383003
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.4109309505
Short name T374
Test name
Test status
Simulation time 568174993 ps
CPU time 23.61 seconds
Started Aug 17 04:48:13 PM PDT 24
Finished Aug 17 04:48:36 PM PDT 24
Peak memory 226340 kb
Host smart-687d82d8-8e73-40ad-8caf-e31648853c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109309505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.4109309505
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2682845774
Short name T601
Test name
Test status
Simulation time 409892269 ps
CPU time 4.87 seconds
Started Aug 17 04:48:14 PM PDT 24
Finished Aug 17 04:48:19 PM PDT 24
Peak memory 217100 kb
Host smart-096a1c16-27a0-4ae3-a2b4-b450bbe8ca78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682845774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2682845774
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.4288100605
Short name T604
Test name
Test status
Simulation time 83416817 ps
CPU time 2.37 seconds
Started Aug 17 04:48:17 PM PDT 24
Finished Aug 17 04:48:20 PM PDT 24
Peak memory 217596 kb
Host smart-0c3cf1aa-d722-405b-824a-192917a08848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288100605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.4288100605
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1144617100
Short name T745
Test name
Test status
Simulation time 616087904 ps
CPU time 15.42 seconds
Started Aug 17 04:48:21 PM PDT 24
Finished Aug 17 04:48:36 PM PDT 24
Peak memory 219064 kb
Host smart-2e2a0561-7d69-4da1-bd23-bac5783661e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144617100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1144617100
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.975848672
Short name T759
Test name
Test status
Simulation time 379112078 ps
CPU time 14.75 seconds
Started Aug 17 04:48:19 PM PDT 24
Finished Aug 17 04:48:34 PM PDT 24
Peak memory 226064 kb
Host smart-9f790dd5-7042-4d46-81a1-47fbb9766ff1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975848672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.975848672
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1720767346
Short name T671
Test name
Test status
Simulation time 988049385 ps
CPU time 9.15 seconds
Started Aug 17 04:48:17 PM PDT 24
Finished Aug 17 04:48:26 PM PDT 24
Peak memory 218196 kb
Host smart-28a5b81a-54f3-4949-a62b-a312e75eaa6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720767346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1720767346
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3232666294
Short name T440
Test name
Test status
Simulation time 96018544 ps
CPU time 1.88 seconds
Started Aug 17 04:48:26 PM PDT 24
Finished Aug 17 04:48:28 PM PDT 24
Peak memory 214024 kb
Host smart-3e1efd1c-7c58-4bcb-94e4-dbb8388b5d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232666294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3232666294
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3865343084
Short name T232
Test name
Test status
Simulation time 1168228791 ps
CPU time 29.39 seconds
Started Aug 17 04:48:17 PM PDT 24
Finished Aug 17 04:48:46 PM PDT 24
Peak memory 250792 kb
Host smart-6f1ac478-dc0d-488c-b4cb-8c79a8c89cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865343084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3865343084
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2944759342
Short name T547
Test name
Test status
Simulation time 209792404 ps
CPU time 10.49 seconds
Started Aug 17 04:48:14 PM PDT 24
Finished Aug 17 04:48:25 PM PDT 24
Peak memory 250872 kb
Host smart-aa48a8f4-23fa-430b-a6bb-acf5561d28a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944759342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2944759342
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3166655450
Short name T501
Test name
Test status
Simulation time 26704836610 ps
CPU time 247.9 seconds
Started Aug 17 04:48:20 PM PDT 24
Finished Aug 17 04:52:28 PM PDT 24
Peak memory 278308 kb
Host smart-352012fc-eecf-4213-bde7-d2c33723cf8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166655450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3166655450
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3930689536
Short name T872
Test name
Test status
Simulation time 2464384679 ps
CPU time 98.2 seconds
Started Aug 17 04:48:24 PM PDT 24
Finished Aug 17 04:50:02 PM PDT 24
Peak memory 277716 kb
Host smart-fe973676-ffb7-431b-981e-d267cca14d16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3930689536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.3930689536
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1098411891
Short name T358
Test name
Test status
Simulation time 13223246 ps
CPU time 0.8 seconds
Started Aug 17 04:48:12 PM PDT 24
Finished Aug 17 04:48:13 PM PDT 24
Peak memory 208928 kb
Host smart-e96673b9-ac30-406e-b014-2cc6925618d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098411891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1098411891
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.911370629
Short name T241
Test name
Test status
Simulation time 75038507 ps
CPU time 0.99 seconds
Started Aug 17 04:46:48 PM PDT 24
Finished Aug 17 04:46:49 PM PDT 24
Peak memory 208652 kb
Host smart-6eb925a7-a916-477a-a710-236c8519d358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911370629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.911370629
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3188901594
Short name T637
Test name
Test status
Simulation time 13618341 ps
CPU time 0.95 seconds
Started Aug 17 04:46:36 PM PDT 24
Finished Aug 17 04:46:37 PM PDT 24
Peak memory 208708 kb
Host smart-b37bbc04-5ee4-4e31-b8d1-46f434b9d79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188901594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3188901594
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1948705478
Short name T519
Test name
Test status
Simulation time 1299870598 ps
CPU time 3.7 seconds
Started Aug 17 04:46:38 PM PDT 24
Finished Aug 17 04:46:42 PM PDT 24
Peak memory 217672 kb
Host smart-45baeced-de16-45dc-9126-e33530f1da60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948705478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1948705478
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.106408757
Short name T513
Test name
Test status
Simulation time 9718698583 ps
CPU time 67.65 seconds
Started Aug 17 04:46:42 PM PDT 24
Finished Aug 17 04:47:50 PM PDT 24
Peak memory 218304 kb
Host smart-e731af7f-9449-45eb-adbc-1217c5ebaeac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106408757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.106408757
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1428394621
Short name T300
Test name
Test status
Simulation time 733421158 ps
CPU time 5.31 seconds
Started Aug 17 04:46:33 PM PDT 24
Finished Aug 17 04:46:39 PM PDT 24
Peak memory 217820 kb
Host smart-77171f82-652b-4f19-87ae-9f91fc814132
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428394621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
428394621
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1308275813
Short name T345
Test name
Test status
Simulation time 95500017 ps
CPU time 2.35 seconds
Started Aug 17 04:46:39 PM PDT 24
Finished Aug 17 04:46:41 PM PDT 24
Peak memory 218176 kb
Host smart-0d8ad2b8-66ec-4f86-b3ac-29f5fe786339
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308275813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1308275813
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.471650777
Short name T75
Test name
Test status
Simulation time 584773386 ps
CPU time 9.05 seconds
Started Aug 17 04:46:38 PM PDT 24
Finished Aug 17 04:46:47 PM PDT 24
Peak memory 217588 kb
Host smart-4157197c-2b60-4802-a267-156b28caa93e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471650777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.471650777
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.609959570
Short name T655
Test name
Test status
Simulation time 373302079 ps
CPU time 4.14 seconds
Started Aug 17 04:46:36 PM PDT 24
Finished Aug 17 04:46:40 PM PDT 24
Peak memory 217608 kb
Host smart-2572d3e9-2b76-446e-a6dd-3b1e8ede983f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609959570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.609959570
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1079634330
Short name T704
Test name
Test status
Simulation time 26129004916 ps
CPU time 60.91 seconds
Started Aug 17 04:46:37 PM PDT 24
Finished Aug 17 04:47:38 PM PDT 24
Peak memory 283612 kb
Host smart-15fa6b16-59a5-4b38-9d3a-f2330967158a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079634330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1079634330
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1283658488
Short name T359
Test name
Test status
Simulation time 336618925 ps
CPU time 7.17 seconds
Started Aug 17 04:46:33 PM PDT 24
Finished Aug 17 04:46:40 PM PDT 24
Peak memory 222804 kb
Host smart-00fc03b5-9231-4dc4-8c90-de32251e9898
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283658488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1283658488
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.4164194026
Short name T678
Test name
Test status
Simulation time 42908501 ps
CPU time 2.73 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:46:37 PM PDT 24
Peak memory 218248 kb
Host smart-d8ccbb83-73b7-42f1-b61a-a28bdbd24a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164194026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.4164194026
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2622815777
Short name T175
Test name
Test status
Simulation time 1471006915 ps
CPU time 8.5 seconds
Started Aug 17 04:46:52 PM PDT 24
Finished Aug 17 04:47:01 PM PDT 24
Peak memory 217756 kb
Host smart-0c359946-060b-4028-8384-3376309bf0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622815777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2622815777
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3561456603
Short name T62
Test name
Test status
Simulation time 258339413 ps
CPU time 39.05 seconds
Started Aug 17 04:46:38 PM PDT 24
Finished Aug 17 04:47:17 PM PDT 24
Peak memory 282444 kb
Host smart-82e5840a-a366-4e14-8bb2-ce2f3736ee5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561456603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3561456603
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1992491084
Short name T514
Test name
Test status
Simulation time 278801181 ps
CPU time 14.1 seconds
Started Aug 17 04:46:36 PM PDT 24
Finished Aug 17 04:46:51 PM PDT 24
Peak memory 218996 kb
Host smart-8e328ae2-4b1a-4c42-9cc1-7f8390531ddb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992491084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1992491084
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.699029575
Short name T363
Test name
Test status
Simulation time 248656472 ps
CPU time 11.07 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:46:46 PM PDT 24
Peak memory 225980 kb
Host smart-d44755d2-ff9a-43e3-bce1-6e7b4b38c566
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699029575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.699029575
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.15939713
Short name T14
Test name
Test status
Simulation time 3783156620 ps
CPU time 9.26 seconds
Started Aug 17 04:46:36 PM PDT 24
Finished Aug 17 04:46:45 PM PDT 24
Peak memory 218204 kb
Host smart-c5d2c9c2-3abd-4926-a6a2-44990b204f46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15939713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.15939713
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2577194049
Short name T807
Test name
Test status
Simulation time 471963443 ps
CPU time 7.01 seconds
Started Aug 17 04:46:42 PM PDT 24
Finished Aug 17 04:46:49 PM PDT 24
Peak memory 226044 kb
Host smart-7a2cf046-716e-47d5-bed7-8ededd9a6552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577194049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2577194049
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3029834358
Short name T492
Test name
Test status
Simulation time 108538298 ps
CPU time 3.27 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:46:39 PM PDT 24
Peak memory 217712 kb
Host smart-c360e81c-e2cb-4a28-bfa3-d142e4618ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029834358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3029834358
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3560897849
Short name T644
Test name
Test status
Simulation time 296580476 ps
CPU time 22.49 seconds
Started Aug 17 04:46:34 PM PDT 24
Finished Aug 17 04:46:57 PM PDT 24
Peak memory 250984 kb
Host smart-644c56e5-1522-46b5-9142-8c65d6619d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560897849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3560897849
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3032381277
Short name T667
Test name
Test status
Simulation time 46654824 ps
CPU time 3.3 seconds
Started Aug 17 04:46:37 PM PDT 24
Finished Aug 17 04:46:40 PM PDT 24
Peak memory 226288 kb
Host smart-1440b090-4067-432c-8a79-c74436d3a4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032381277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3032381277
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3311228051
Short name T322
Test name
Test status
Simulation time 3527736684 ps
CPU time 105.78 seconds
Started Aug 17 04:46:48 PM PDT 24
Finished Aug 17 04:48:34 PM PDT 24
Peak memory 276988 kb
Host smart-83d8eb52-7f54-488d-8224-3fd47305d4e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311228051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3311228051
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3155630007
Short name T788
Test name
Test status
Simulation time 43320843 ps
CPU time 0.93 seconds
Started Aug 17 04:46:39 PM PDT 24
Finished Aug 17 04:46:40 PM PDT 24
Peak memory 209268 kb
Host smart-3c52e1f8-898b-46e1-8763-6b2ebe3960c4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155630007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.3155630007
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1708950734
Short name T450
Test name
Test status
Simulation time 18059096 ps
CPU time 1.15 seconds
Started Aug 17 04:48:18 PM PDT 24
Finished Aug 17 04:48:19 PM PDT 24
Peak memory 208908 kb
Host smart-9eb6343a-d778-4945-ab77-6ccaa635a850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708950734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1708950734
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3081352098
Short name T731
Test name
Test status
Simulation time 2461952748 ps
CPU time 13.76 seconds
Started Aug 17 04:48:18 PM PDT 24
Finished Aug 17 04:48:32 PM PDT 24
Peak memory 218256 kb
Host smart-65cf40a3-b9f9-4bbc-8a0b-64aadf10c756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081352098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3081352098
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.664141012
Short name T316
Test name
Test status
Simulation time 281475853 ps
CPU time 7.14 seconds
Started Aug 17 04:48:22 PM PDT 24
Finished Aug 17 04:48:29 PM PDT 24
Peak memory 217664 kb
Host smart-a6d73c28-b55b-4280-90a5-cc6143f1f86e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664141012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.664141012
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1312277704
Short name T320
Test name
Test status
Simulation time 176544666 ps
CPU time 2.18 seconds
Started Aug 17 04:48:21 PM PDT 24
Finished Aug 17 04:48:23 PM PDT 24
Peak memory 218216 kb
Host smart-38ce5650-087b-4be6-9086-35edaadbaf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312277704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1312277704
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3205306609
Short name T672
Test name
Test status
Simulation time 385967269 ps
CPU time 15.95 seconds
Started Aug 17 04:48:17 PM PDT 24
Finished Aug 17 04:48:33 PM PDT 24
Peak memory 218372 kb
Host smart-eaa2340c-2775-4a9e-bdbd-9d4c0efee04c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205306609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3205306609
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1839995113
Short name T421
Test name
Test status
Simulation time 325942819 ps
CPU time 10.22 seconds
Started Aug 17 04:48:23 PM PDT 24
Finished Aug 17 04:48:33 PM PDT 24
Peak memory 225928 kb
Host smart-5d8d99c0-ed0b-4c10-9469-14890699987b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839995113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1839995113
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2366921875
Short name T734
Test name
Test status
Simulation time 283349843 ps
CPU time 7.28 seconds
Started Aug 17 04:48:19 PM PDT 24
Finished Aug 17 04:48:27 PM PDT 24
Peak memory 225972 kb
Host smart-243d0dbe-bd22-45ae-98a8-ad97d1366b34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366921875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2366921875
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1744780891
Short name T720
Test name
Test status
Simulation time 976563487 ps
CPU time 7.94 seconds
Started Aug 17 04:48:16 PM PDT 24
Finished Aug 17 04:48:24 PM PDT 24
Peak memory 218304 kb
Host smart-7c5638f6-b7d5-4895-9689-fd79a87c7bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744780891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1744780891
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2365413663
Short name T595
Test name
Test status
Simulation time 87592649 ps
CPU time 2.64 seconds
Started Aug 17 04:48:17 PM PDT 24
Finished Aug 17 04:48:20 PM PDT 24
Peak memory 217624 kb
Host smart-002ef133-26a9-490d-9d70-be3d641553b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365413663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2365413663
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2206875516
Short name T212
Test name
Test status
Simulation time 430949447 ps
CPU time 19.83 seconds
Started Aug 17 04:48:22 PM PDT 24
Finished Aug 17 04:48:42 PM PDT 24
Peak memory 250904 kb
Host smart-dcee8654-b920-44bf-8d9e-0aa17535ca05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206875516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2206875516
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1583971782
Short name T254
Test name
Test status
Simulation time 89480779 ps
CPU time 8.74 seconds
Started Aug 17 04:48:21 PM PDT 24
Finished Aug 17 04:48:30 PM PDT 24
Peak memory 250892 kb
Host smart-1c4f0f04-e5e1-4e3e-bc5e-3aa6cdfc81ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583971782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1583971782
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.335481286
Short name T485
Test name
Test status
Simulation time 7009226663 ps
CPU time 88.53 seconds
Started Aug 17 04:48:19 PM PDT 24
Finished Aug 17 04:49:47 PM PDT 24
Peak memory 278852 kb
Host smart-b46f0549-5c3c-443f-b7e7-02057a6e9aed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335481286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.335481286
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3751586953
Short name T139
Test name
Test status
Simulation time 2332240210 ps
CPU time 109.08 seconds
Started Aug 17 04:48:18 PM PDT 24
Finished Aug 17 04:50:08 PM PDT 24
Peak memory 276880 kb
Host smart-2c9e7260-a365-4107-a99b-bb1b6dd05fb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3751586953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.3751586953
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1191180013
Short name T578
Test name
Test status
Simulation time 27014393 ps
CPU time 1.09 seconds
Started Aug 17 04:48:29 PM PDT 24
Finished Aug 17 04:48:30 PM PDT 24
Peak memory 211940 kb
Host smart-f3e796f7-b7c2-4176-a986-901118805aa7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191180013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1191180013
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2269493066
Short name T670
Test name
Test status
Simulation time 58861558 ps
CPU time 0.91 seconds
Started Aug 17 04:48:22 PM PDT 24
Finished Aug 17 04:48:23 PM PDT 24
Peak memory 208876 kb
Host smart-78844f20-4ea3-44d5-8dde-eef045daca5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269493066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2269493066
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2958842445
Short name T303
Test name
Test status
Simulation time 540064648 ps
CPU time 13.25 seconds
Started Aug 17 04:48:18 PM PDT 24
Finished Aug 17 04:48:32 PM PDT 24
Peak memory 218164 kb
Host smart-96a15ab6-689c-4bd3-8159-8c3acb5993fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958842445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2958842445
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3874351872
Short name T688
Test name
Test status
Simulation time 1117055829 ps
CPU time 7.26 seconds
Started Aug 17 04:48:21 PM PDT 24
Finished Aug 17 04:48:28 PM PDT 24
Peak memory 217720 kb
Host smart-67510c42-a151-45f2-b3c5-4800d35f336e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874351872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3874351872
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3775542784
Short name T221
Test name
Test status
Simulation time 25709194 ps
CPU time 2.08 seconds
Started Aug 17 04:48:21 PM PDT 24
Finished Aug 17 04:48:23 PM PDT 24
Peak memory 222092 kb
Host smart-429c2027-083f-4f20-b547-9573e7cd64c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775542784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3775542784
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1077901469
Short name T66
Test name
Test status
Simulation time 1078247945 ps
CPU time 24.6 seconds
Started Aug 17 04:48:22 PM PDT 24
Finished Aug 17 04:48:46 PM PDT 24
Peak memory 226040 kb
Host smart-08c9e8b4-b4d3-420c-a23a-17663756ba91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077901469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1077901469
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.790086155
Short name T171
Test name
Test status
Simulation time 601013613 ps
CPU time 12.99 seconds
Started Aug 17 04:48:21 PM PDT 24
Finished Aug 17 04:48:34 PM PDT 24
Peak memory 226076 kb
Host smart-6adce640-ecf9-4398-abf9-22f78b5429cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790086155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.790086155
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2418278191
Short name T758
Test name
Test status
Simulation time 486026947 ps
CPU time 11.45 seconds
Started Aug 17 04:48:18 PM PDT 24
Finished Aug 17 04:48:29 PM PDT 24
Peak memory 226016 kb
Host smart-0c1e9cd4-eb7b-4320-9863-381e51d065e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418278191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2418278191
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.873354171
Short name T746
Test name
Test status
Simulation time 324474869 ps
CPU time 12.51 seconds
Started Aug 17 04:48:19 PM PDT 24
Finished Aug 17 04:48:32 PM PDT 24
Peak memory 218316 kb
Host smart-1cd5de90-44b5-43d9-9e25-1946b53276e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873354171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.873354171
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2324936090
Short name T516
Test name
Test status
Simulation time 314679800 ps
CPU time 2.7 seconds
Started Aug 17 04:48:29 PM PDT 24
Finished Aug 17 04:48:32 PM PDT 24
Peak memory 214820 kb
Host smart-04531ab5-fac0-4b4d-883b-49482207240b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324936090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2324936090
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1227946806
Short name T86
Test name
Test status
Simulation time 1257842017 ps
CPU time 22.99 seconds
Started Aug 17 04:48:19 PM PDT 24
Finished Aug 17 04:48:42 PM PDT 24
Peak memory 250856 kb
Host smart-268a8b16-4857-4523-a708-6d972b29a5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227946806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1227946806
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2610702179
Short name T813
Test name
Test status
Simulation time 73104087 ps
CPU time 8.18 seconds
Started Aug 17 04:48:17 PM PDT 24
Finished Aug 17 04:48:26 PM PDT 24
Peak memory 250876 kb
Host smart-02a6c8ba-1bbb-4d39-a99a-22e23ef9e014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610702179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2610702179
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1070779057
Short name T87
Test name
Test status
Simulation time 6624888282 ps
CPU time 166.33 seconds
Started Aug 17 04:48:25 PM PDT 24
Finished Aug 17 04:51:11 PM PDT 24
Peak memory 249172 kb
Host smart-24561008-f93c-49ac-ad05-87a839fde51c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070779057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1070779057
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2818204762
Short name T140
Test name
Test status
Simulation time 16022321928 ps
CPU time 106.3 seconds
Started Aug 17 04:48:24 PM PDT 24
Finished Aug 17 04:50:10 PM PDT 24
Peak memory 267944 kb
Host smart-046ff3b3-f01c-43e8-8045-9777cc9b8922
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2818204762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2818204762
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1082597855
Short name T706
Test name
Test status
Simulation time 22384008 ps
CPU time 0.94 seconds
Started Aug 17 04:48:28 PM PDT 24
Finished Aug 17 04:48:29 PM PDT 24
Peak memory 209148 kb
Host smart-da94e88f-dc64-45c8-b2ee-cb5e533e6829
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082597855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1082597855
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.787893790
Short name T204
Test name
Test status
Simulation time 54470219 ps
CPU time 1.02 seconds
Started Aug 17 04:48:23 PM PDT 24
Finished Aug 17 04:48:24 PM PDT 24
Peak memory 208936 kb
Host smart-64296c74-b1f6-44e5-9fa0-c5368f1f178b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787893790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.787893790
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3815574243
Short name T384
Test name
Test status
Simulation time 286798368 ps
CPU time 7.9 seconds
Started Aug 17 04:48:22 PM PDT 24
Finished Aug 17 04:48:30 PM PDT 24
Peak memory 218192 kb
Host smart-505027bc-4f68-4944-9503-04b7315ffc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815574243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3815574243
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1222789352
Short name T466
Test name
Test status
Simulation time 2440734142 ps
CPU time 7.02 seconds
Started Aug 17 04:48:24 PM PDT 24
Finished Aug 17 04:48:31 PM PDT 24
Peak memory 217800 kb
Host smart-ee2041e3-7383-46f2-bef8-dda558a70b47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222789352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1222789352
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2408293089
Short name T343
Test name
Test status
Simulation time 171405613 ps
CPU time 3.18 seconds
Started Aug 17 04:48:24 PM PDT 24
Finished Aug 17 04:48:27 PM PDT 24
Peak memory 218400 kb
Host smart-eb512b0f-475e-429a-bc32-b52ddd889172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408293089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2408293089
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3444789544
Short name T275
Test name
Test status
Simulation time 7237143975 ps
CPU time 14.81 seconds
Started Aug 17 04:48:28 PM PDT 24
Finished Aug 17 04:48:43 PM PDT 24
Peak memory 226088 kb
Host smart-7f0b6b4d-14e6-49dc-9bad-67e788ab3d43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444789544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3444789544
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2308694270
Short name T808
Test name
Test status
Simulation time 825961861 ps
CPU time 8.48 seconds
Started Aug 17 04:48:38 PM PDT 24
Finished Aug 17 04:48:46 PM PDT 24
Peak memory 226084 kb
Host smart-e03f429c-8841-4f79-8b67-8617b2eb8475
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308694270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2308694270
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.65427195
Short name T437
Test name
Test status
Simulation time 1488951002 ps
CPU time 9.95 seconds
Started Aug 17 04:48:22 PM PDT 24
Finished Aug 17 04:48:32 PM PDT 24
Peak memory 218272 kb
Host smart-09908a05-f15d-458c-b1c4-a276b79e283d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65427195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.65427195
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.721350636
Short name T247
Test name
Test status
Simulation time 762972615 ps
CPU time 13.47 seconds
Started Aug 17 04:48:21 PM PDT 24
Finished Aug 17 04:48:35 PM PDT 24
Peak memory 218300 kb
Host smart-c04fa8de-30e1-48a0-8f45-1d2cde18983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721350636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.721350636
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2766767488
Short name T306
Test name
Test status
Simulation time 136631425 ps
CPU time 2.88 seconds
Started Aug 17 04:48:29 PM PDT 24
Finished Aug 17 04:48:32 PM PDT 24
Peak memory 214540 kb
Host smart-eed7551b-27c1-46c9-894e-dc86d2645660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766767488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2766767488
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3005590666
Short name T305
Test name
Test status
Simulation time 511373967 ps
CPU time 24.41 seconds
Started Aug 17 04:48:29 PM PDT 24
Finished Aug 17 04:48:53 PM PDT 24
Peak memory 250932 kb
Host smart-473e4fd7-f697-4d86-861b-3fc02a32d36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005590666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3005590666
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2724885516
Short name T265
Test name
Test status
Simulation time 794885490 ps
CPU time 8.63 seconds
Started Aug 17 04:48:20 PM PDT 24
Finished Aug 17 04:48:28 PM PDT 24
Peak memory 244880 kb
Host smart-9da4fe96-045c-493f-926c-5fdd890894d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724885516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2724885516
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.450255286
Short name T707
Test name
Test status
Simulation time 69894191548 ps
CPU time 193.98 seconds
Started Aug 17 04:48:22 PM PDT 24
Finished Aug 17 04:51:36 PM PDT 24
Peak memory 250996 kb
Host smart-b8284ad9-8859-48d0-8372-3eca8fea2e5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450255286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.450255286
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2142571062
Short name T272
Test name
Test status
Simulation time 15774065 ps
CPU time 1.02 seconds
Started Aug 17 04:48:23 PM PDT 24
Finished Aug 17 04:48:24 PM PDT 24
Peak memory 209024 kb
Host smart-7a745cb1-4b18-409f-a75e-b5326d9047eb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142571062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2142571062
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3244391573
Short name T539
Test name
Test status
Simulation time 61222844 ps
CPU time 0.94 seconds
Started Aug 17 04:48:26 PM PDT 24
Finished Aug 17 04:48:27 PM PDT 24
Peak memory 208932 kb
Host smart-fdaba547-3b60-4a83-b145-1422d5a281c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244391573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3244391573
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.239572812
Short name T225
Test name
Test status
Simulation time 665072397 ps
CPU time 18.47 seconds
Started Aug 17 04:48:19 PM PDT 24
Finished Aug 17 04:48:38 PM PDT 24
Peak memory 225996 kb
Host smart-5a4fae8a-f9ce-4255-aeca-bbc923cabfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239572812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.239572812
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3535234635
Short name T592
Test name
Test status
Simulation time 2512706292 ps
CPU time 15.55 seconds
Started Aug 17 04:48:18 PM PDT 24
Finished Aug 17 04:48:33 PM PDT 24
Peak memory 217708 kb
Host smart-1d9691e9-c53c-4701-9c1d-33abe19a0a87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535234635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3535234635
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2270003906
Short name T710
Test name
Test status
Simulation time 58239065 ps
CPU time 2.58 seconds
Started Aug 17 04:48:17 PM PDT 24
Finished Aug 17 04:48:20 PM PDT 24
Peak memory 217636 kb
Host smart-23100f2e-7b59-439b-80b2-36bf3666d0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270003906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2270003906
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2786331401
Short name T219
Test name
Test status
Simulation time 365767715 ps
CPU time 11.86 seconds
Started Aug 17 04:48:17 PM PDT 24
Finished Aug 17 04:48:29 PM PDT 24
Peak memory 226132 kb
Host smart-be0394de-0673-4f0d-9709-7f501eb79ea2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786331401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2786331401
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3788576823
Short name T379
Test name
Test status
Simulation time 255285547 ps
CPU time 7.94 seconds
Started Aug 17 04:48:23 PM PDT 24
Finished Aug 17 04:48:31 PM PDT 24
Peak memory 226128 kb
Host smart-06bba9a1-f0a2-48ad-8a6d-4f9036c3257e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788576823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3788576823
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2971929022
Short name T567
Test name
Test status
Simulation time 965037197 ps
CPU time 9.53 seconds
Started Aug 17 04:48:25 PM PDT 24
Finished Aug 17 04:48:34 PM PDT 24
Peak memory 226000 kb
Host smart-b87949da-26c5-4be2-897c-dba52f2b9e3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971929022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2971929022
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1361510313
Short name T798
Test name
Test status
Simulation time 947265495 ps
CPU time 11.68 seconds
Started Aug 17 04:48:20 PM PDT 24
Finished Aug 17 04:48:31 PM PDT 24
Peak memory 218320 kb
Host smart-404b220f-8ca7-45dd-a36d-296938e2fd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361510313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1361510313
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1567469858
Short name T562
Test name
Test status
Simulation time 968550972 ps
CPU time 9.71 seconds
Started Aug 17 04:48:22 PM PDT 24
Finished Aug 17 04:48:31 PM PDT 24
Peak memory 217800 kb
Host smart-1801a132-110b-4516-8a7f-5415c46296ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567469858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1567469858
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.58402421
Short name T649
Test name
Test status
Simulation time 188279037 ps
CPU time 22.34 seconds
Started Aug 17 04:48:25 PM PDT 24
Finished Aug 17 04:48:48 PM PDT 24
Peak memory 245700 kb
Host smart-69ebc933-e207-4f8b-bd6d-3289fbc3fee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58402421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.58402421
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.795019497
Short name T228
Test name
Test status
Simulation time 272083848 ps
CPU time 7.11 seconds
Started Aug 17 04:48:22 PM PDT 24
Finished Aug 17 04:48:30 PM PDT 24
Peak memory 242756 kb
Host smart-505b1842-1cfa-4110-a001-05c0612af067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795019497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.795019497
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1107617570
Short name T352
Test name
Test status
Simulation time 75632013 ps
CPU time 1.26 seconds
Started Aug 17 04:48:21 PM PDT 24
Finished Aug 17 04:48:23 PM PDT 24
Peak memory 212976 kb
Host smart-e607e3c3-5b74-49ab-90cd-4868b9c26190
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107617570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1107617570
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.837204643
Short name T246
Test name
Test status
Simulation time 50613299 ps
CPU time 1.33 seconds
Started Aug 17 04:48:38 PM PDT 24
Finished Aug 17 04:48:39 PM PDT 24
Peak memory 209108 kb
Host smart-b4410699-fce2-4e3a-98b9-bf1695f28c9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837204643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.837204643
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3016088214
Short name T385
Test name
Test status
Simulation time 811223020 ps
CPU time 10.19 seconds
Started Aug 17 04:48:38 PM PDT 24
Finished Aug 17 04:48:48 PM PDT 24
Peak memory 218352 kb
Host smart-27909e58-82c7-4c93-9220-bc190c285359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016088214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3016088214
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.602756340
Short name T364
Test name
Test status
Simulation time 3545965127 ps
CPU time 21.31 seconds
Started Aug 17 04:48:38 PM PDT 24
Finished Aug 17 04:49:00 PM PDT 24
Peak memory 217844 kb
Host smart-fc5b55e4-fd00-46cc-9e0c-8e310ab4c2f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602756340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.602756340
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3895029068
Short name T344
Test name
Test status
Simulation time 2044466513 ps
CPU time 3.29 seconds
Started Aug 17 04:48:20 PM PDT 24
Finished Aug 17 04:48:24 PM PDT 24
Peak memory 218236 kb
Host smart-9a00781e-6dda-4604-9565-a0376e6e2204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895029068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3895029068
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2175505897
Short name T67
Test name
Test status
Simulation time 1388900751 ps
CPU time 10.06 seconds
Started Aug 17 04:48:24 PM PDT 24
Finished Aug 17 04:48:34 PM PDT 24
Peak memory 218920 kb
Host smart-5a4eaa76-ab1b-4a05-b8c5-5c6eefc2b785
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175505897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2175505897
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.216478890
Short name T653
Test name
Test status
Simulation time 397371319 ps
CPU time 10.05 seconds
Started Aug 17 04:48:22 PM PDT 24
Finished Aug 17 04:48:32 PM PDT 24
Peak memory 225824 kb
Host smart-0f6cd034-7a16-4af1-b5aa-9cf42c684685
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216478890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.216478890
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3637163306
Short name T335
Test name
Test status
Simulation time 1841191250 ps
CPU time 9.82 seconds
Started Aug 17 04:48:28 PM PDT 24
Finished Aug 17 04:48:38 PM PDT 24
Peak memory 218164 kb
Host smart-0d84ad50-aa5f-49c9-92b5-0ab94da305bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637163306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3637163306
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.120539303
Short name T58
Test name
Test status
Simulation time 363137449 ps
CPU time 13.95 seconds
Started Aug 17 04:48:40 PM PDT 24
Finished Aug 17 04:48:54 PM PDT 24
Peak memory 218380 kb
Host smart-726e5aad-58fa-4b3b-904a-142aec2165e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120539303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.120539303
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.1818963912
Short name T810
Test name
Test status
Simulation time 257107229 ps
CPU time 2.84 seconds
Started Aug 17 04:48:36 PM PDT 24
Finished Aug 17 04:48:39 PM PDT 24
Peak memory 214352 kb
Host smart-6291f715-44fc-4ddc-813a-a0c47e311722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818963912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1818963912
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2434770642
Short name T36
Test name
Test status
Simulation time 237987214 ps
CPU time 21.69 seconds
Started Aug 17 04:48:20 PM PDT 24
Finished Aug 17 04:48:42 PM PDT 24
Peak memory 250956 kb
Host smart-42faca6e-164c-4e6c-81e6-a580ad7f363d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434770642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2434770642
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.291464414
Short name T339
Test name
Test status
Simulation time 199127342 ps
CPU time 5.65 seconds
Started Aug 17 04:48:38 PM PDT 24
Finished Aug 17 04:48:44 PM PDT 24
Peak memory 247296 kb
Host smart-bf784800-acf2-4ac2-b67f-70dbf927b79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291464414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.291464414
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2765306913
Short name T444
Test name
Test status
Simulation time 7817637837 ps
CPU time 271.07 seconds
Started Aug 17 04:48:28 PM PDT 24
Finished Aug 17 04:52:59 PM PDT 24
Peak memory 332800 kb
Host smart-aefafa84-0aa8-4852-96a8-038351042a91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765306913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2765306913
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3799868568
Short name T757
Test name
Test status
Simulation time 12679356 ps
CPU time 1.09 seconds
Started Aug 17 04:48:24 PM PDT 24
Finished Aug 17 04:48:25 PM PDT 24
Peak memory 212084 kb
Host smart-5626f5cd-4530-424e-bd8f-69b534a4e22d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799868568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3799868568
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2785718829
Short name T329
Test name
Test status
Simulation time 283788708 ps
CPU time 1.13 seconds
Started Aug 17 04:48:26 PM PDT 24
Finished Aug 17 04:48:27 PM PDT 24
Peak memory 209008 kb
Host smart-2ca99335-cff6-4515-91ee-f5f702fb92cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785718829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2785718829
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3459368706
Short name T457
Test name
Test status
Simulation time 1341806745 ps
CPU time 8.62 seconds
Started Aug 17 04:48:26 PM PDT 24
Finished Aug 17 04:48:35 PM PDT 24
Peak memory 226140 kb
Host smart-d652c8f4-e299-40b4-985e-a33d3f2c07cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459368706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3459368706
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3599706974
Short name T267
Test name
Test status
Simulation time 2063469365 ps
CPU time 4.5 seconds
Started Aug 17 04:48:30 PM PDT 24
Finished Aug 17 04:48:34 PM PDT 24
Peak memory 217712 kb
Host smart-44e6e272-073f-4c0d-b120-8e6c01dde404
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599706974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3599706974
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3847176082
Short name T860
Test name
Test status
Simulation time 81215934 ps
CPU time 2.2 seconds
Started Aug 17 04:48:25 PM PDT 24
Finished Aug 17 04:48:27 PM PDT 24
Peak memory 222120 kb
Host smart-01cd171e-631d-4621-bd04-c94a857dc7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847176082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3847176082
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2935849277
Short name T836
Test name
Test status
Simulation time 635741173 ps
CPU time 19.08 seconds
Started Aug 17 04:48:32 PM PDT 24
Finished Aug 17 04:48:51 PM PDT 24
Peak memory 218896 kb
Host smart-7a953d92-c6ce-495e-8439-1c927fa87095
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935849277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2935849277
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2857030701
Short name T347
Test name
Test status
Simulation time 968149967 ps
CPU time 18.16 seconds
Started Aug 17 04:48:28 PM PDT 24
Finished Aug 17 04:48:46 PM PDT 24
Peak memory 225972 kb
Host smart-41f079d4-ac9e-48f6-bd9c-65433693021e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857030701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2857030701
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1954191564
Short name T735
Test name
Test status
Simulation time 643653403 ps
CPU time 9.56 seconds
Started Aug 17 04:48:26 PM PDT 24
Finished Aug 17 04:48:36 PM PDT 24
Peak memory 218200 kb
Host smart-d55c41a6-18ea-49e8-87ab-85e79ef54161
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954191564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1954191564
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2293513747
Short name T445
Test name
Test status
Simulation time 179958445 ps
CPU time 8.21 seconds
Started Aug 17 04:48:26 PM PDT 24
Finished Aug 17 04:48:35 PM PDT 24
Peak memory 226032 kb
Host smart-aa069b6f-e651-43c2-909f-9e5284e3f940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293513747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2293513747
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.63505653
Short name T524
Test name
Test status
Simulation time 68672967 ps
CPU time 2.27 seconds
Started Aug 17 04:48:27 PM PDT 24
Finished Aug 17 04:48:29 PM PDT 24
Peak memory 222624 kb
Host smart-661fd31e-138c-4719-b6f9-a0ffde404232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63505653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.63505653
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.13868531
Short name T557
Test name
Test status
Simulation time 211893107 ps
CPU time 27.22 seconds
Started Aug 17 04:48:25 PM PDT 24
Finished Aug 17 04:48:52 PM PDT 24
Peak memory 246048 kb
Host smart-5132421b-7ecf-4729-a722-e114598b7ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13868531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.13868531
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2118715042
Short name T685
Test name
Test status
Simulation time 346954759 ps
CPU time 7.77 seconds
Started Aug 17 04:48:25 PM PDT 24
Finished Aug 17 04:48:33 PM PDT 24
Peak memory 250840 kb
Host smart-dc196166-48d3-4c05-8333-d883a2363db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118715042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2118715042
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3385128885
Short name T163
Test name
Test status
Simulation time 10317723322 ps
CPU time 171.83 seconds
Started Aug 17 04:48:26 PM PDT 24
Finished Aug 17 04:51:18 PM PDT 24
Peak memory 283152 kb
Host smart-4c1339ef-7f99-4afa-9066-84e79259c4b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385128885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3385128885
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3101743044
Short name T224
Test name
Test status
Simulation time 31310877 ps
CPU time 0.85 seconds
Started Aug 17 04:48:26 PM PDT 24
Finished Aug 17 04:48:27 PM PDT 24
Peak memory 208952 kb
Host smart-19e308e1-6cb8-41c9-83d1-2020453961de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101743044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3101743044
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2359307117
Short name T554
Test name
Test status
Simulation time 60748835 ps
CPU time 0.88 seconds
Started Aug 17 04:48:26 PM PDT 24
Finished Aug 17 04:48:28 PM PDT 24
Peak memory 208948 kb
Host smart-d7f53ab7-8590-4f0e-9988-be133dbec33c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359307117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2359307117
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2061690731
Short name T211
Test name
Test status
Simulation time 2033989268 ps
CPU time 15.37 seconds
Started Aug 17 04:48:25 PM PDT 24
Finished Aug 17 04:48:40 PM PDT 24
Peak memory 218256 kb
Host smart-f82be659-7531-481a-8095-5c44cbb8252a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061690731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2061690731
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2046450834
Short name T765
Test name
Test status
Simulation time 349204392 ps
CPU time 9.7 seconds
Started Aug 17 04:48:28 PM PDT 24
Finished Aug 17 04:48:38 PM PDT 24
Peak memory 217788 kb
Host smart-d339fd60-e195-4d17-bd25-1a814de6b4a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046450834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2046450834
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2506456548
Short name T732
Test name
Test status
Simulation time 195462182 ps
CPU time 7.2 seconds
Started Aug 17 04:48:26 PM PDT 24
Finished Aug 17 04:48:34 PM PDT 24
Peak memory 218244 kb
Host smart-c54cfce6-6b4d-4a28-ae14-876fea72b82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506456548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2506456548
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3117123252
Short name T733
Test name
Test status
Simulation time 359635344 ps
CPU time 11.55 seconds
Started Aug 17 04:48:31 PM PDT 24
Finished Aug 17 04:48:43 PM PDT 24
Peak memory 218944 kb
Host smart-6e3d9bf5-3ba8-4ebe-996e-44d74608792c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117123252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3117123252
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1140893675
Short name T370
Test name
Test status
Simulation time 305022302 ps
CPU time 8.81 seconds
Started Aug 17 04:48:32 PM PDT 24
Finished Aug 17 04:48:41 PM PDT 24
Peak memory 225940 kb
Host smart-5ce75c99-9531-427a-9ae5-a1b49fdbd284
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140893675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1140893675
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.848877127
Short name T273
Test name
Test status
Simulation time 1375272834 ps
CPU time 11.41 seconds
Started Aug 17 04:48:38 PM PDT 24
Finished Aug 17 04:48:49 PM PDT 24
Peak memory 218292 kb
Host smart-0c24cbae-9a51-4145-beeb-f2e055dc9061
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848877127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.848877127
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1206513395
Short name T227
Test name
Test status
Simulation time 206347436 ps
CPU time 8.32 seconds
Started Aug 17 04:48:27 PM PDT 24
Finished Aug 17 04:48:35 PM PDT 24
Peak memory 218348 kb
Host smart-207717b6-df36-42d7-8cdf-4cc491c84156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206513395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1206513395
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2559120742
Short name T206
Test name
Test status
Simulation time 67310750 ps
CPU time 1.11 seconds
Started Aug 17 04:48:28 PM PDT 24
Finished Aug 17 04:48:29 PM PDT 24
Peak memory 212280 kb
Host smart-f6aaf299-5aef-4b13-99c1-2f889b3dcd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559120742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2559120742
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2577061182
Short name T404
Test name
Test status
Simulation time 693283342 ps
CPU time 33.6 seconds
Started Aug 17 04:48:26 PM PDT 24
Finished Aug 17 04:49:00 PM PDT 24
Peak memory 250888 kb
Host smart-64759067-b794-4b33-9693-baafe29dd4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577061182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2577061182
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.4056353828
Short name T692
Test name
Test status
Simulation time 256482322 ps
CPU time 3.49 seconds
Started Aug 17 04:48:32 PM PDT 24
Finished Aug 17 04:48:40 PM PDT 24
Peak memory 218168 kb
Host smart-99ef3259-9bd3-4212-b117-33cd8708e36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056353828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.4056353828
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1317140192
Short name T691
Test name
Test status
Simulation time 52325092937 ps
CPU time 496.93 seconds
Started Aug 17 04:48:27 PM PDT 24
Finished Aug 17 04:56:44 PM PDT 24
Peak memory 281520 kb
Host smart-43673a37-ae35-4ead-81da-760fbc4590fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317140192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1317140192
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.4292696712
Short name T83
Test name
Test status
Simulation time 41979562 ps
CPU time 1.03 seconds
Started Aug 17 04:48:30 PM PDT 24
Finished Aug 17 04:48:31 PM PDT 24
Peak memory 211960 kb
Host smart-7030a88c-5f77-478b-a6cb-f34f1dd81d28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292696712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.4292696712
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.451472822
Short name T235
Test name
Test status
Simulation time 23135793 ps
CPU time 0.97 seconds
Started Aug 17 04:48:42 PM PDT 24
Finished Aug 17 04:48:43 PM PDT 24
Peak memory 208956 kb
Host smart-a48aa02e-2765-4d32-bbec-824a19c2a3c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451472822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.451472822
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2800903033
Short name T286
Test name
Test status
Simulation time 242689705 ps
CPU time 11.24 seconds
Started Aug 17 04:48:26 PM PDT 24
Finished Aug 17 04:48:38 PM PDT 24
Peak memory 226048 kb
Host smart-aaf9ff31-1baa-4cb3-b217-2d3f87e95b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800903033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2800903033
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3570816414
Short name T277
Test name
Test status
Simulation time 6772284233 ps
CPU time 11.61 seconds
Started Aug 17 04:48:46 PM PDT 24
Finished Aug 17 04:48:57 PM PDT 24
Peak memory 217716 kb
Host smart-051b8de2-4324-4da9-8a55-2c2ad22d7c61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570816414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3570816414
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1459081900
Short name T288
Test name
Test status
Simulation time 81255538 ps
CPU time 3.39 seconds
Started Aug 17 04:48:28 PM PDT 24
Finished Aug 17 04:48:31 PM PDT 24
Peak memory 218252 kb
Host smart-f413541a-9120-47d9-a0f4-3abb7db879dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459081900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1459081900
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.547940134
Short name T674
Test name
Test status
Simulation time 508804263 ps
CPU time 14.69 seconds
Started Aug 17 04:48:50 PM PDT 24
Finished Aug 17 04:49:05 PM PDT 24
Peak memory 218632 kb
Host smart-494a3cc7-6c56-49d7-b431-2f60c30ed943
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547940134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.547940134
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.796609688
Short name T270
Test name
Test status
Simulation time 308969372 ps
CPU time 8.57 seconds
Started Aug 17 04:48:46 PM PDT 24
Finished Aug 17 04:48:55 PM PDT 24
Peak memory 225948 kb
Host smart-16d2d6ad-0ae1-4206-a980-81607c1b9f12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796609688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.796609688
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.931108402
Short name T850
Test name
Test status
Simulation time 889001796 ps
CPU time 10.37 seconds
Started Aug 17 04:48:47 PM PDT 24
Finished Aug 17 04:48:58 PM PDT 24
Peak memory 226092 kb
Host smart-2fca3646-2687-4258-a4de-cc8db55ae59d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931108402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.931108402
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.144351659
Short name T64
Test name
Test status
Simulation time 267997989 ps
CPU time 8.35 seconds
Started Aug 17 04:48:59 PM PDT 24
Finished Aug 17 04:49:08 PM PDT 24
Peak memory 226052 kb
Host smart-a83ab7c4-55c2-4d06-9ba5-b45782894547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144351659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.144351659
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1747895460
Short name T353
Test name
Test status
Simulation time 61995805 ps
CPU time 3.19 seconds
Started Aug 17 04:48:26 PM PDT 24
Finished Aug 17 04:48:31 PM PDT 24
Peak memory 217696 kb
Host smart-4b199849-dca4-4786-ba71-214ec54a79f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747895460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1747895460
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3019757424
Short name T871
Test name
Test status
Simulation time 2043220466 ps
CPU time 25.57 seconds
Started Aug 17 04:48:26 PM PDT 24
Finished Aug 17 04:48:53 PM PDT 24
Peak memory 250924 kb
Host smart-7bcd8d7b-611c-48e3-b2d2-d0a78afb93ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019757424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3019757424
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2191825943
Short name T368
Test name
Test status
Simulation time 64492962 ps
CPU time 3.65 seconds
Started Aug 17 04:48:26 PM PDT 24
Finished Aug 17 04:48:29 PM PDT 24
Peak memory 226304 kb
Host smart-261b751f-f811-4759-8857-b57f0963a91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191825943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2191825943
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2219031778
Short name T20
Test name
Test status
Simulation time 9987128443 ps
CPU time 335.92 seconds
Started Aug 17 04:48:55 PM PDT 24
Finished Aug 17 04:54:31 PM PDT 24
Peak memory 269676 kb
Host smart-b0effdec-0dae-4cef-a29e-fa3e45e73f19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219031778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2219031778
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.2536475188
Short name T146
Test name
Test status
Simulation time 5561465103 ps
CPU time 108.68 seconds
Started Aug 17 04:48:45 PM PDT 24
Finished Aug 17 04:50:34 PM PDT 24
Peak memory 267740 kb
Host smart-04d06c5a-30c7-4626-98dc-fd6bc4906d73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2536475188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.2536475188
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2493775233
Short name T159
Test name
Test status
Simulation time 23969139 ps
CPU time 0.78 seconds
Started Aug 17 04:48:37 PM PDT 24
Finished Aug 17 04:48:38 PM PDT 24
Peak memory 208864 kb
Host smart-b261403d-0c4f-4e87-9831-67c8674768fc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493775233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2493775233
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.441421505
Short name T260
Test name
Test status
Simulation time 17607216 ps
CPU time 0.93 seconds
Started Aug 17 04:48:39 PM PDT 24
Finished Aug 17 04:48:40 PM PDT 24
Peak memory 208880 kb
Host smart-8d5bcdd4-804d-4d20-b79f-c7b43e82798b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441421505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.441421505
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1343852355
Short name T580
Test name
Test status
Simulation time 383620601 ps
CPU time 12.84 seconds
Started Aug 17 04:48:46 PM PDT 24
Finished Aug 17 04:48:59 PM PDT 24
Peak memory 226040 kb
Host smart-0bd882ad-b390-4341-bbfe-3c4b93fe6db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343852355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1343852355
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.638621148
Short name T663
Test name
Test status
Simulation time 195030513 ps
CPU time 5.83 seconds
Started Aug 17 04:48:49 PM PDT 24
Finished Aug 17 04:48:55 PM PDT 24
Peak memory 217672 kb
Host smart-2d8138e4-bc81-4cca-afa7-89524e849c11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638621148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.638621148
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1238625507
Short name T453
Test name
Test status
Simulation time 357451998 ps
CPU time 3.17 seconds
Started Aug 17 04:48:45 PM PDT 24
Finished Aug 17 04:48:49 PM PDT 24
Peak memory 222580 kb
Host smart-ba4670c2-5300-4322-8dbf-2b78ac03d83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238625507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1238625507
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3547997443
Short name T324
Test name
Test status
Simulation time 1275987273 ps
CPU time 13.58 seconds
Started Aug 17 04:48:48 PM PDT 24
Finished Aug 17 04:49:01 PM PDT 24
Peak memory 218884 kb
Host smart-5955cf08-3f5e-4bed-9098-0ae69fcc0cd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547997443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3547997443
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3580845861
Short name T866
Test name
Test status
Simulation time 1866224041 ps
CPU time 11.28 seconds
Started Aug 17 04:48:46 PM PDT 24
Finished Aug 17 04:48:57 PM PDT 24
Peak memory 225976 kb
Host smart-19cef905-a4d4-4290-9b97-c6b2ef7fedd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580845861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3580845861
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3864495900
Short name T701
Test name
Test status
Simulation time 946317255 ps
CPU time 9.39 seconds
Started Aug 17 04:48:45 PM PDT 24
Finished Aug 17 04:48:54 PM PDT 24
Peak memory 225972 kb
Host smart-18542216-8cb8-4191-ae57-e8df615f1f86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864495900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3864495900
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1616028585
Short name T422
Test name
Test status
Simulation time 1598010977 ps
CPU time 7.79 seconds
Started Aug 17 04:48:47 PM PDT 24
Finished Aug 17 04:48:55 PM PDT 24
Peak memory 218312 kb
Host smart-7328b553-a1ed-40a5-954c-79a5fe029fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616028585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1616028585
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2912947064
Short name T426
Test name
Test status
Simulation time 58458098 ps
CPU time 2.8 seconds
Started Aug 17 04:48:53 PM PDT 24
Finished Aug 17 04:48:56 PM PDT 24
Peak memory 214724 kb
Host smart-81672985-fc9a-4052-ae19-ac042e7627ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912947064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2912947064
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3997207918
Short name T503
Test name
Test status
Simulation time 377356227 ps
CPU time 19.26 seconds
Started Aug 17 04:48:52 PM PDT 24
Finished Aug 17 04:49:12 PM PDT 24
Peak memory 250876 kb
Host smart-9ea10a5c-ca34-41b7-be20-c7ec4a326662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997207918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3997207918
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.839466332
Short name T585
Test name
Test status
Simulation time 273452221 ps
CPU time 3.42 seconds
Started Aug 17 04:48:47 PM PDT 24
Finished Aug 17 04:48:51 PM PDT 24
Peak memory 226236 kb
Host smart-9b0305e4-6234-4b8e-b356-b475c5b19179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839466332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.839466332
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3711619245
Short name T293
Test name
Test status
Simulation time 6989802034 ps
CPU time 131.56 seconds
Started Aug 17 04:48:47 PM PDT 24
Finished Aug 17 04:50:58 PM PDT 24
Peak memory 274736 kb
Host smart-0d3caef3-937f-4ec6-8233-eb53bb5eb6df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711619245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3711619245
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.4131889774
Short name T164
Test name
Test status
Simulation time 17102988511 ps
CPU time 144.93 seconds
Started Aug 17 04:48:44 PM PDT 24
Finished Aug 17 04:51:09 PM PDT 24
Peak memory 283828 kb
Host smart-2f56f378-2731-445a-b0b0-ecf0439caf52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4131889774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.4131889774
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3365166347
Short name T215
Test name
Test status
Simulation time 26977560 ps
CPU time 1.05 seconds
Started Aug 17 04:48:51 PM PDT 24
Finished Aug 17 04:48:52 PM PDT 24
Peak memory 212064 kb
Host smart-4e4a9d9f-3ab8-4eab-b8b1-0095a0125e88
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365166347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3365166347
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2487434193
Short name T411
Test name
Test status
Simulation time 15826578 ps
CPU time 0.91 seconds
Started Aug 17 04:48:40 PM PDT 24
Finished Aug 17 04:48:41 PM PDT 24
Peak memory 208852 kb
Host smart-ed5c1a69-0300-487c-963d-9df7bb360ca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487434193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2487434193
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.732419206
Short name T697
Test name
Test status
Simulation time 821285341 ps
CPU time 10.83 seconds
Started Aug 17 04:48:50 PM PDT 24
Finished Aug 17 04:49:01 PM PDT 24
Peak memory 218312 kb
Host smart-df7f9513-d7ad-48f8-84d6-3d9ea7988f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732419206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.732419206
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1816095234
Short name T28
Test name
Test status
Simulation time 1602502383 ps
CPU time 10.94 seconds
Started Aug 17 04:48:58 PM PDT 24
Finished Aug 17 04:49:09 PM PDT 24
Peak memory 217948 kb
Host smart-052a8cd3-e257-45fe-af8a-8237c3b81a27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816095234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1816095234
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1461061027
Short name T577
Test name
Test status
Simulation time 35981164 ps
CPU time 2.02 seconds
Started Aug 17 04:48:47 PM PDT 24
Finished Aug 17 04:48:50 PM PDT 24
Peak memory 218240 kb
Host smart-164c11b2-923f-453d-9895-d12993a93d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461061027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1461061027
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1322901890
Short name T689
Test name
Test status
Simulation time 1192670839 ps
CPU time 10.97 seconds
Started Aug 17 04:48:44 PM PDT 24
Finished Aug 17 04:48:55 PM PDT 24
Peak memory 219008 kb
Host smart-4618bd45-1064-4425-8d33-8b73a4db9fd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322901890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1322901890
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2555039661
Short name T442
Test name
Test status
Simulation time 4088412641 ps
CPU time 21.91 seconds
Started Aug 17 04:48:49 PM PDT 24
Finished Aug 17 04:49:11 PM PDT 24
Peak memory 226000 kb
Host smart-9dcb5693-a434-474b-9e8f-8f67abf43fe7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555039661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2555039661
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.409287361
Short name T500
Test name
Test status
Simulation time 531013916 ps
CPU time 6.79 seconds
Started Aug 17 04:48:52 PM PDT 24
Finished Aug 17 04:48:59 PM PDT 24
Peak memory 218140 kb
Host smart-6f46fa9f-3cb9-4f3b-b632-31cb0d9f7b8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409287361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.409287361
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.4286511947
Short name T160
Test name
Test status
Simulation time 498741011 ps
CPU time 5.26 seconds
Started Aug 17 04:48:50 PM PDT 24
Finished Aug 17 04:48:56 PM PDT 24
Peak memory 217668 kb
Host smart-47330bbb-4b75-458c-9395-e009a9618424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286511947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.4286511947
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2419910165
Short name T550
Test name
Test status
Simulation time 220605819 ps
CPU time 31.6 seconds
Started Aug 17 04:48:39 PM PDT 24
Finished Aug 17 04:49:11 PM PDT 24
Peak memory 250888 kb
Host smart-b9786d6b-04fc-4490-995a-49e11b175c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419910165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2419910165
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2514015215
Short name T774
Test name
Test status
Simulation time 59707148 ps
CPU time 6.31 seconds
Started Aug 17 04:48:39 PM PDT 24
Finished Aug 17 04:48:45 PM PDT 24
Peak memory 246940 kb
Host smart-fa477c04-8296-4106-bb1c-cdd8dddc397f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514015215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2514015215
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1179517858
Short name T588
Test name
Test status
Simulation time 1179551819 ps
CPU time 9.59 seconds
Started Aug 17 04:48:51 PM PDT 24
Finished Aug 17 04:49:01 PM PDT 24
Peak memory 226140 kb
Host smart-a383410e-e1c2-4f51-8743-30eb0606d09d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179517858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1179517858
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.621602167
Short name T380
Test name
Test status
Simulation time 29393582 ps
CPU time 0.95 seconds
Started Aug 17 04:48:47 PM PDT 24
Finished Aug 17 04:48:48 PM PDT 24
Peak memory 213044 kb
Host smart-1b7f6138-a025-4ddd-93a7-82ad9850ff27
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621602167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.621602167
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3852847749
Short name T448
Test name
Test status
Simulation time 38746025 ps
CPU time 0.86 seconds
Started Aug 17 04:46:42 PM PDT 24
Finished Aug 17 04:46:43 PM PDT 24
Peak memory 208836 kb
Host smart-9e2fedb1-d195-4ed2-8f35-3bb633f59cf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852847749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3852847749
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3280699664
Short name T455
Test name
Test status
Simulation time 30729738 ps
CPU time 0.85 seconds
Started Aug 17 04:46:43 PM PDT 24
Finished Aug 17 04:46:44 PM PDT 24
Peak memory 208720 kb
Host smart-57106bc9-583d-4eff-866c-d9f1274f277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280699664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3280699664
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.3942917668
Short name T258
Test name
Test status
Simulation time 695493358 ps
CPU time 24.94 seconds
Started Aug 17 04:46:41 PM PDT 24
Finished Aug 17 04:47:07 PM PDT 24
Peak memory 226140 kb
Host smart-0b322537-6506-4f11-9970-0b0560fa5763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942917668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3942917668
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3104460574
Short name T395
Test name
Test status
Simulation time 194790237 ps
CPU time 5.57 seconds
Started Aug 17 04:46:53 PM PDT 24
Finished Aug 17 04:46:59 PM PDT 24
Peak memory 217376 kb
Host smart-f9695c25-63b0-488f-9ed7-a780018f1c77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104460574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3104460574
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1996802455
Short name T431
Test name
Test status
Simulation time 2949601151 ps
CPU time 28.03 seconds
Started Aug 17 04:46:54 PM PDT 24
Finished Aug 17 04:47:22 PM PDT 24
Peak memory 219256 kb
Host smart-1e8484a3-6200-4abf-922b-eba0e14faddb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996802455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1996802455
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.917361014
Short name T17
Test name
Test status
Simulation time 364221995 ps
CPU time 3.41 seconds
Started Aug 17 04:46:55 PM PDT 24
Finished Aug 17 04:46:59 PM PDT 24
Peak memory 217724 kb
Host smart-a56f2b5b-a959-4771-897a-478ef3b6a4c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917361014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.917361014
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3091166509
Short name T823
Test name
Test status
Simulation time 552426318 ps
CPU time 8.82 seconds
Started Aug 17 04:46:45 PM PDT 24
Finished Aug 17 04:46:54 PM PDT 24
Peak memory 218184 kb
Host smart-27320bbb-1cde-4b60-9145-744ea1b0fffe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091166509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3091166509
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1367547151
Short name T372
Test name
Test status
Simulation time 13531321603 ps
CPU time 11.73 seconds
Started Aug 17 04:46:44 PM PDT 24
Finished Aug 17 04:46:56 PM PDT 24
Peak memory 217692 kb
Host smart-6a70021b-3ec5-4a15-8f5b-fe7ff8c1e73f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367547151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1367547151
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1441793932
Short name T741
Test name
Test status
Simulation time 1474781505 ps
CPU time 7 seconds
Started Aug 17 04:46:43 PM PDT 24
Finished Aug 17 04:46:50 PM PDT 24
Peak memory 217588 kb
Host smart-76fee239-717a-4d99-a499-d5415096fe53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441793932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1441793932
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1675525249
Short name T865
Test name
Test status
Simulation time 1500106054 ps
CPU time 44.19 seconds
Started Aug 17 04:46:44 PM PDT 24
Finished Aug 17 04:47:28 PM PDT 24
Peak memory 267868 kb
Host smart-f509959a-64c8-4e89-ad06-d3ea666bf031
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675525249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1675525249
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.500315881
Short name T243
Test name
Test status
Simulation time 313299245 ps
CPU time 10.54 seconds
Started Aug 17 04:46:55 PM PDT 24
Finished Aug 17 04:47:06 PM PDT 24
Peak memory 250648 kb
Host smart-92c110fa-0e17-407a-8b5e-af139f3c77d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500315881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.500315881
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3814968530
Short name T208
Test name
Test status
Simulation time 75279780 ps
CPU time 1.72 seconds
Started Aug 17 04:46:34 PM PDT 24
Finished Aug 17 04:46:36 PM PDT 24
Peak memory 218236 kb
Host smart-551aac76-aa86-4bcb-9038-b3acdd08d8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814968530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3814968530
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3461110099
Short name T69
Test name
Test status
Simulation time 1538862216 ps
CPU time 15.58 seconds
Started Aug 17 04:46:53 PM PDT 24
Finished Aug 17 04:47:08 PM PDT 24
Peak memory 214808 kb
Host smart-e2e3e153-76de-4e19-8ee8-a1e50f9fe7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461110099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3461110099
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3005086154
Short name T289
Test name
Test status
Simulation time 813077486 ps
CPU time 12.64 seconds
Started Aug 17 04:46:43 PM PDT 24
Finished Aug 17 04:46:56 PM PDT 24
Peak memory 218312 kb
Host smart-0226cf47-ba52-4e85-8058-270ebc963bc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005086154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3005086154
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3569987665
Short name T846
Test name
Test status
Simulation time 1018324201 ps
CPU time 10.17 seconds
Started Aug 17 04:46:55 PM PDT 24
Finished Aug 17 04:47:05 PM PDT 24
Peak memory 225948 kb
Host smart-9e4443f3-abb4-44a5-a4fd-57cc4efc3d03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569987665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3569987665
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.4272147987
Short name T582
Test name
Test status
Simulation time 214971217 ps
CPU time 9.2 seconds
Started Aug 17 04:46:44 PM PDT 24
Finished Aug 17 04:46:53 PM PDT 24
Peak memory 218132 kb
Host smart-1c9ccc03-95cd-4e20-ac8f-b0b050a483f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272147987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.4
272147987
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.4038990519
Short name T369
Test name
Test status
Simulation time 333171847 ps
CPU time 13.96 seconds
Started Aug 17 04:46:48 PM PDT 24
Finished Aug 17 04:47:02 PM PDT 24
Peak memory 226092 kb
Host smart-79960087-dfb3-4d5b-9c09-da22c9fbaac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038990519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.4038990519
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2793082529
Short name T382
Test name
Test status
Simulation time 43283302 ps
CPU time 2.07 seconds
Started Aug 17 04:46:54 PM PDT 24
Finished Aug 17 04:46:56 PM PDT 24
Peak memory 217672 kb
Host smart-5f976f94-675d-4d6f-97bb-bb15e28e3127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793082529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2793082529
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1656076455
Short name T793
Test name
Test status
Simulation time 647285976 ps
CPU time 25.19 seconds
Started Aug 17 04:46:35 PM PDT 24
Finished Aug 17 04:47:00 PM PDT 24
Peak memory 250940 kb
Host smart-764e3388-31b5-4245-867a-fc62c5c309d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656076455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1656076455
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.4236271438
Short name T239
Test name
Test status
Simulation time 540574680 ps
CPU time 4.89 seconds
Started Aug 17 04:46:34 PM PDT 24
Finished Aug 17 04:46:39 PM PDT 24
Peak memory 222932 kb
Host smart-6626a733-8d53-4d86-9961-40a7bd42e1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236271438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.4236271438
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.4178599580
Short name T520
Test name
Test status
Simulation time 18632161048 ps
CPU time 77.29 seconds
Started Aug 17 04:46:55 PM PDT 24
Finished Aug 17 04:48:13 PM PDT 24
Peak memory 254464 kb
Host smart-fb5fd992-cacc-4524-be3f-ae68bdbc1e7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178599580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.4178599580
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3442912397
Short name T214
Test name
Test status
Simulation time 24746150 ps
CPU time 0.9 seconds
Started Aug 17 04:46:38 PM PDT 24
Finished Aug 17 04:46:39 PM PDT 24
Peak memory 212072 kb
Host smart-c13b2455-ccb1-4dd1-a0e9-c311206f539b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442912397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3442912397
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1791891233
Short name T698
Test name
Test status
Simulation time 71575184 ps
CPU time 0.99 seconds
Started Aug 17 04:47:05 PM PDT 24
Finished Aug 17 04:47:06 PM PDT 24
Peak memory 208992 kb
Host smart-7b2e7356-09c0-4907-a150-c9b14c3d1bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791891233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1791891233
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.389514132
Short name T196
Test name
Test status
Simulation time 109367767 ps
CPU time 0.77 seconds
Started Aug 17 04:46:48 PM PDT 24
Finished Aug 17 04:46:49 PM PDT 24
Peak memory 209000 kb
Host smart-1335efa3-57a0-4b30-aeee-e73c3de7912e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389514132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.389514132
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2721795108
Short name T432
Test name
Test status
Simulation time 645462466 ps
CPU time 14.44 seconds
Started Aug 17 04:46:45 PM PDT 24
Finished Aug 17 04:46:59 PM PDT 24
Peak memory 226068 kb
Host smart-19937c99-3b1d-4458-9b10-f2f13525953c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721795108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2721795108
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.625534188
Short name T819
Test name
Test status
Simulation time 1799096473 ps
CPU time 11.35 seconds
Started Aug 17 04:46:43 PM PDT 24
Finished Aug 17 04:46:54 PM PDT 24
Peak memory 217740 kb
Host smart-1217ba31-eacf-4413-b285-6b1916724779
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625534188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.625534188
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3532855666
Short name T627
Test name
Test status
Simulation time 5240034527 ps
CPU time 39.47 seconds
Started Aug 17 04:46:57 PM PDT 24
Finished Aug 17 04:47:37 PM PDT 24
Peak memory 218340 kb
Host smart-2ce9a022-89e1-4408-9a6f-db7afde2d5b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532855666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3532855666
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1144421990
Short name T310
Test name
Test status
Simulation time 2654157656 ps
CPU time 12.19 seconds
Started Aug 17 04:46:51 PM PDT 24
Finished Aug 17 04:47:03 PM PDT 24
Peak memory 217800 kb
Host smart-de81308f-0b38-4c99-a994-84d073ba7a8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144421990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
144421990
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2342395693
Short name T281
Test name
Test status
Simulation time 378082254 ps
CPU time 2.68 seconds
Started Aug 17 04:46:57 PM PDT 24
Finished Aug 17 04:46:59 PM PDT 24
Peak memory 218212 kb
Host smart-68297760-1126-4f7e-98d6-2336f0fb191d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342395693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2342395693
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1858745803
Short name T471
Test name
Test status
Simulation time 1180490712 ps
CPU time 14.82 seconds
Started Aug 17 04:46:48 PM PDT 24
Finished Aug 17 04:47:03 PM PDT 24
Peak memory 217608 kb
Host smart-8ec4fd51-4c04-44da-aafd-9985c1434dc5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858745803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1858745803
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2702910149
Short name T19
Test name
Test status
Simulation time 3607591426 ps
CPU time 9.6 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:09 PM PDT 24
Peak memory 217608 kb
Host smart-931573d7-360e-4c47-82fd-32c38c9e4a2d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702910149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2702910149
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2534673502
Short name T454
Test name
Test status
Simulation time 17178707038 ps
CPU time 62 seconds
Started Aug 17 04:46:45 PM PDT 24
Finished Aug 17 04:47:47 PM PDT 24
Peak memory 275440 kb
Host smart-36c00808-7b34-4f53-b88d-307bb10db328
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534673502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2534673502
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2305131799
Short name T679
Test name
Test status
Simulation time 254085252 ps
CPU time 13.34 seconds
Started Aug 17 04:46:48 PM PDT 24
Finished Aug 17 04:47:02 PM PDT 24
Peak memory 250924 kb
Host smart-6faa1a61-7146-4671-b6b6-a170e5cbf2fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305131799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2305131799
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.4028167344
Short name T590
Test name
Test status
Simulation time 56935817 ps
CPU time 2.51 seconds
Started Aug 17 04:46:44 PM PDT 24
Finished Aug 17 04:46:47 PM PDT 24
Peak memory 218348 kb
Host smart-c385a708-81ee-44c9-aca2-1889360db439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028167344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.4028167344
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.330469293
Short name T84
Test name
Test status
Simulation time 765767340 ps
CPU time 5.17 seconds
Started Aug 17 04:46:56 PM PDT 24
Finished Aug 17 04:47:01 PM PDT 24
Peak memory 213940 kb
Host smart-558c03be-0059-4c48-b6f5-b8296e19ced3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330469293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.330469293
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1451482062
Short name T717
Test name
Test status
Simulation time 1137843428 ps
CPU time 10.92 seconds
Started Aug 17 04:46:54 PM PDT 24
Finished Aug 17 04:47:05 PM PDT 24
Peak memory 219024 kb
Host smart-2a29d148-86f6-4acf-9a3b-c2995931f74d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451482062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1451482062
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3019282521
Short name T251
Test name
Test status
Simulation time 748851039 ps
CPU time 11.87 seconds
Started Aug 17 04:46:56 PM PDT 24
Finished Aug 17 04:47:08 PM PDT 24
Peak memory 226064 kb
Host smart-fdefb991-06d8-42f3-be04-d42df5918a85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019282521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3019282521
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3898628543
Short name T38
Test name
Test status
Simulation time 1003556213 ps
CPU time 7.24 seconds
Started Aug 17 04:46:55 PM PDT 24
Finished Aug 17 04:47:02 PM PDT 24
Peak memory 218012 kb
Host smart-26bcb395-99f7-48b0-9516-f2e4941f9f6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898628543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
898628543
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3284732130
Short name T57
Test name
Test status
Simulation time 1124358588 ps
CPU time 8.35 seconds
Started Aug 17 04:46:44 PM PDT 24
Finished Aug 17 04:46:53 PM PDT 24
Peak memory 226120 kb
Host smart-d2f29412-8f24-4516-8394-e77491427879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284732130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3284732130
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3303180031
Short name T74
Test name
Test status
Simulation time 95571405 ps
CPU time 1.75 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:00 PM PDT 24
Peak memory 214096 kb
Host smart-68a0d58d-de5c-4ade-80be-ac8a4c7e9a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303180031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3303180031
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.948030342
Short name T702
Test name
Test status
Simulation time 273852479 ps
CPU time 25.95 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:25 PM PDT 24
Peak memory 250924 kb
Host smart-55f36e69-f5e6-413c-a855-246b74049c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948030342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.948030342
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.4181084386
Short name T847
Test name
Test status
Simulation time 59213543 ps
CPU time 3.72 seconds
Started Aug 17 04:47:00 PM PDT 24
Finished Aug 17 04:47:03 PM PDT 24
Peak memory 222852 kb
Host smart-9de0d768-fbc9-42e7-83ca-19fc064b09d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181084386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.4181084386
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2073353163
Short name T778
Test name
Test status
Simulation time 5678486843 ps
CPU time 176.13 seconds
Started Aug 17 04:46:45 PM PDT 24
Finished Aug 17 04:49:42 PM PDT 24
Peak memory 274224 kb
Host smart-3b057669-0b57-407c-9a19-604d8d7cc37e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073353163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2073353163
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.167326326
Short name T459
Test name
Test status
Simulation time 18063600 ps
CPU time 1.03 seconds
Started Aug 17 04:46:47 PM PDT 24
Finished Aug 17 04:46:48 PM PDT 24
Peak memory 211944 kb
Host smart-93f44e55-ad6c-4edd-9fec-1d99b334f14d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167326326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.167326326
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2002813905
Short name T279
Test name
Test status
Simulation time 15588497 ps
CPU time 0.91 seconds
Started Aug 17 04:47:00 PM PDT 24
Finished Aug 17 04:47:01 PM PDT 24
Peak memory 208928 kb
Host smart-1cfcb842-2aa3-4c7f-9bd8-1402e82ed493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002813905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2002813905
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.4141679178
Short name T696
Test name
Test status
Simulation time 417796056 ps
CPU time 15.07 seconds
Started Aug 17 04:47:03 PM PDT 24
Finished Aug 17 04:47:18 PM PDT 24
Peak memory 226028 kb
Host smart-0e4046c3-6c96-4d52-9c98-b1046747a0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141679178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.4141679178
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.153779545
Short name T25
Test name
Test status
Simulation time 226701485 ps
CPU time 6.68 seconds
Started Aug 17 04:47:06 PM PDT 24
Finished Aug 17 04:47:13 PM PDT 24
Peak memory 217656 kb
Host smart-a086aa7c-7399-40b9-9fff-8223cb418349
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153779545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.153779545
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2997256722
Short name T839
Test name
Test status
Simulation time 2951371199 ps
CPU time 77.77 seconds
Started Aug 17 04:46:56 PM PDT 24
Finished Aug 17 04:48:14 PM PDT 24
Peak memory 219908 kb
Host smart-ce1838ab-2d09-49f6-9540-e261e592fb0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997256722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2997256722
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2522682316
Short name T861
Test name
Test status
Simulation time 1702781109 ps
CPU time 7.58 seconds
Started Aug 17 04:46:57 PM PDT 24
Finished Aug 17 04:47:05 PM PDT 24
Peak memory 217724 kb
Host smart-e53dd51d-917a-494f-9a03-27616072ddb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522682316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
522682316
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3270081660
Short name T429
Test name
Test status
Simulation time 132089388 ps
CPU time 3.36 seconds
Started Aug 17 04:47:02 PM PDT 24
Finished Aug 17 04:47:05 PM PDT 24
Peak memory 218196 kb
Host smart-ea54aa51-9f10-43bc-a23d-ef338b0c850a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270081660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3270081660
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3073486983
Short name T155
Test name
Test status
Simulation time 1585857335 ps
CPU time 32.39 seconds
Started Aug 17 04:46:54 PM PDT 24
Finished Aug 17 04:47:27 PM PDT 24
Peak memory 217656 kb
Host smart-70ff455b-ef7c-4184-b3f4-b91e31190119
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073486983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3073486983
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3897001150
Short name T72
Test name
Test status
Simulation time 288271366 ps
CPU time 4.55 seconds
Started Aug 17 04:47:00 PM PDT 24
Finished Aug 17 04:47:04 PM PDT 24
Peak memory 217564 kb
Host smart-7a942042-e2ce-49ce-9471-f9ea0fd2222c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897001150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3897001150
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2120684373
Short name T268
Test name
Test status
Simulation time 2107613359 ps
CPU time 68.63 seconds
Started Aug 17 04:47:01 PM PDT 24
Finished Aug 17 04:48:10 PM PDT 24
Peak memory 276816 kb
Host smart-8e9e01b3-5350-43aa-8b21-3604df569231
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120684373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2120684373
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3296680380
Short name T367
Test name
Test status
Simulation time 3289345162 ps
CPU time 23.84 seconds
Started Aug 17 04:47:01 PM PDT 24
Finished Aug 17 04:47:24 PM PDT 24
Peak memory 250740 kb
Host smart-0f0d742d-e97b-4cb9-8d4d-623b37fa42d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296680380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3296680380
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3083170884
Short name T237
Test name
Test status
Simulation time 48547484 ps
CPU time 2.15 seconds
Started Aug 17 04:46:53 PM PDT 24
Finished Aug 17 04:46:56 PM PDT 24
Peak memory 222248 kb
Host smart-ddb95ab5-f6ec-4742-82f3-2eb928b360cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083170884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3083170884
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1879788668
Short name T178
Test name
Test status
Simulation time 924933198 ps
CPU time 7.18 seconds
Started Aug 17 04:47:00 PM PDT 24
Finished Aug 17 04:47:08 PM PDT 24
Peak memory 217672 kb
Host smart-f3f5ba0b-cc34-46fd-a4f0-7752200fe111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879788668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1879788668
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.600926644
Short name T608
Test name
Test status
Simulation time 565517123 ps
CPU time 9.74 seconds
Started Aug 17 04:47:04 PM PDT 24
Finished Aug 17 04:47:14 PM PDT 24
Peak memory 218900 kb
Host smart-3aa8f629-295f-41ab-8d8e-f48f0ee1dbd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600926644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.600926644
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.4184253924
Short name T796
Test name
Test status
Simulation time 2835865156 ps
CPU time 28.24 seconds
Started Aug 17 04:47:00 PM PDT 24
Finished Aug 17 04:47:28 PM PDT 24
Peak memory 226052 kb
Host smart-68fcc787-3d32-4fde-9a1d-e36dbd4dd9f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184253924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.4184253924
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1842282155
Short name T584
Test name
Test status
Simulation time 689645664 ps
CPU time 6.66 seconds
Started Aug 17 04:46:58 PM PDT 24
Finished Aug 17 04:47:05 PM PDT 24
Peak memory 218172 kb
Host smart-3dda6e35-11bd-4355-bac1-253bb5b5f624
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842282155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
842282155
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.232896674
Short name T348
Test name
Test status
Simulation time 1819028803 ps
CPU time 14.67 seconds
Started Aug 17 04:46:55 PM PDT 24
Finished Aug 17 04:47:10 PM PDT 24
Peak memory 218384 kb
Host smart-8eb51161-5b83-4f42-b4a2-c09a257631f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232896674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.232896674
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2772746958
Short name T721
Test name
Test status
Simulation time 33236408 ps
CPU time 2.16 seconds
Started Aug 17 04:46:57 PM PDT 24
Finished Aug 17 04:46:59 PM PDT 24
Peak memory 217788 kb
Host smart-65d74288-016e-4053-b0d8-a302c4e88512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772746958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2772746958
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1624145733
Short name T611
Test name
Test status
Simulation time 97176423 ps
CPU time 9.01 seconds
Started Aug 17 04:46:55 PM PDT 24
Finished Aug 17 04:47:04 PM PDT 24
Peak memory 250876 kb
Host smart-da313ffc-06ff-4610-b97f-7c6671c72638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624145733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1624145733
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.485361911
Short name T269
Test name
Test status
Simulation time 14928944919 ps
CPU time 66.26 seconds
Started Aug 17 04:47:03 PM PDT 24
Finished Aug 17 04:48:09 PM PDT 24
Peak memory 226112 kb
Host smart-f76ba1ce-f004-4049-81b7-0262e9b09ac1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485361911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.485361911
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.4204743904
Short name T92
Test name
Test status
Simulation time 9536896163 ps
CPU time 97.15 seconds
Started Aug 17 04:46:57 PM PDT 24
Finished Aug 17 04:48:34 PM PDT 24
Peak memory 283828 kb
Host smart-23fa6933-7160-452c-96f7-e7ce26fbc823
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4204743904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.4204743904
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.593710331
Short name T723
Test name
Test status
Simulation time 25723919 ps
CPU time 0.84 seconds
Started Aug 17 04:47:10 PM PDT 24
Finished Aug 17 04:47:16 PM PDT 24
Peak memory 209136 kb
Host smart-c9adb4be-9688-4065-aa75-dd7a186db742
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593710331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.593710331
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1046085461
Short name T318
Test name
Test status
Simulation time 46391353 ps
CPU time 0.96 seconds
Started Aug 17 04:47:06 PM PDT 24
Finished Aug 17 04:47:07 PM PDT 24
Peak memory 207724 kb
Host smart-bb63a18d-7237-4df9-a3ac-f07ca161a501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046085461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1046085461
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.139465007
Short name T401
Test name
Test status
Simulation time 340309765 ps
CPU time 10.48 seconds
Started Aug 17 04:47:06 PM PDT 24
Finished Aug 17 04:47:17 PM PDT 24
Peak memory 225956 kb
Host smart-537b8372-50d0-4922-9d4b-cfd19965b356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139465007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.139465007
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.4197054867
Short name T854
Test name
Test status
Simulation time 83367272 ps
CPU time 1.62 seconds
Started Aug 17 04:47:00 PM PDT 24
Finished Aug 17 04:47:01 PM PDT 24
Peak memory 217716 kb
Host smart-0d5f9e24-618e-4526-b297-f97be3da1aac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197054867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.4197054867
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1437727209
Short name T325
Test name
Test status
Simulation time 8260783573 ps
CPU time 63.07 seconds
Started Aug 17 04:46:54 PM PDT 24
Finished Aug 17 04:47:58 PM PDT 24
Peak memory 218892 kb
Host smart-ca98aa46-976a-45ee-9bd4-a3585924afe4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437727209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1437727209
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.897299954
Short name T822
Test name
Test status
Simulation time 156206098 ps
CPU time 2.82 seconds
Started Aug 17 04:46:55 PM PDT 24
Finished Aug 17 04:46:58 PM PDT 24
Peak memory 217708 kb
Host smart-41c1ee95-e7ca-43cf-9264-f087eff696d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897299954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.897299954
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.997094447
Short name T95
Test name
Test status
Simulation time 506108767 ps
CPU time 7.39 seconds
Started Aug 17 04:46:57 PM PDT 24
Finished Aug 17 04:47:05 PM PDT 24
Peak memory 218408 kb
Host smart-55adf32e-ec8e-41ed-8891-c863ae42f722
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997094447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.997094447
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.772759709
Short name T467
Test name
Test status
Simulation time 4727405768 ps
CPU time 19.76 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:18 PM PDT 24
Peak memory 217752 kb
Host smart-74ce5a11-5a9d-47ee-b39d-374b945578c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772759709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.772759709
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2483414181
Short name T575
Test name
Test status
Simulation time 623938880 ps
CPU time 7.79 seconds
Started Aug 17 04:47:06 PM PDT 24
Finished Aug 17 04:47:14 PM PDT 24
Peak memory 217692 kb
Host smart-82e630e3-e976-4aac-933e-322684f073cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483414181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2483414181
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.650526355
Short name T669
Test name
Test status
Simulation time 849534159 ps
CPU time 28.78 seconds
Started Aug 17 04:47:03 PM PDT 24
Finished Aug 17 04:47:32 PM PDT 24
Peak memory 250832 kb
Host smart-563796df-6713-4a2c-9b6c-e9194f02e230
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650526355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.650526355
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1265020293
Short name T762
Test name
Test status
Simulation time 507243257 ps
CPU time 13.14 seconds
Started Aug 17 04:46:57 PM PDT 24
Finished Aug 17 04:47:10 PM PDT 24
Peak memory 250360 kb
Host smart-27c8bc5c-f3fd-4dde-980d-d4f53d1fcdb2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265020293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1265020293
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3459940985
Short name T311
Test name
Test status
Simulation time 74753086 ps
CPU time 2.81 seconds
Started Aug 17 04:46:54 PM PDT 24
Finished Aug 17 04:46:57 PM PDT 24
Peak memory 218348 kb
Host smart-54648e2e-ecfc-4c62-9f23-80bf4da539e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459940985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3459940985
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3635691006
Short name T756
Test name
Test status
Simulation time 673305759 ps
CPU time 16.49 seconds
Started Aug 17 04:47:04 PM PDT 24
Finished Aug 17 04:47:21 PM PDT 24
Peak memory 217676 kb
Host smart-eb8137b2-7d54-4c1e-8c91-5a1844e66162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635691006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3635691006
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1512275560
Short name T551
Test name
Test status
Simulation time 2074559585 ps
CPU time 21.99 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:21 PM PDT 24
Peak memory 226040 kb
Host smart-aa15c539-0f8c-475d-9803-aa3df4be3506
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512275560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1512275560
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2378948365
Short name T529
Test name
Test status
Simulation time 437397504 ps
CPU time 11.38 seconds
Started Aug 17 04:47:00 PM PDT 24
Finished Aug 17 04:47:11 PM PDT 24
Peak memory 225956 kb
Host smart-e3d4d7ac-82b4-4075-8179-b49e2d38a2f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378948365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2378948365
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1437029803
Short name T458
Test name
Test status
Simulation time 1400411798 ps
CPU time 13.55 seconds
Started Aug 17 04:47:02 PM PDT 24
Finished Aug 17 04:47:16 PM PDT 24
Peak memory 218196 kb
Host smart-33c85c82-9792-4fd1-bb44-70c448095d18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437029803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
437029803
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2233957227
Short name T626
Test name
Test status
Simulation time 307250667 ps
CPU time 8.9 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:08 PM PDT 24
Peak memory 218340 kb
Host smart-0e9fc144-832e-455d-8569-b476f24d6ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233957227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2233957227
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3555521772
Short name T729
Test name
Test status
Simulation time 90466753 ps
CPU time 1.55 seconds
Started Aug 17 04:46:56 PM PDT 24
Finished Aug 17 04:46:57 PM PDT 24
Peak memory 213772 kb
Host smart-9fe0d3ab-96b6-4d53-ab11-1a82434d309c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555521772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3555521772
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1309523803
Short name T525
Test name
Test status
Simulation time 803426660 ps
CPU time 38.16 seconds
Started Aug 17 04:46:56 PM PDT 24
Finished Aug 17 04:47:34 PM PDT 24
Peak memory 250828 kb
Host smart-288faba7-daa1-4d4f-b405-b9ab0ff5b153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309523803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1309523803
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2418724169
Short name T837
Test name
Test status
Simulation time 79956380 ps
CPU time 3.54 seconds
Started Aug 17 04:47:06 PM PDT 24
Finished Aug 17 04:47:09 PM PDT 24
Peak memory 226392 kb
Host smart-cc59e603-4ea8-497e-a76f-7109d502fb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418724169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2418724169
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3224110582
Short name T481
Test name
Test status
Simulation time 143303322219 ps
CPU time 264.35 seconds
Started Aug 17 04:47:00 PM PDT 24
Finished Aug 17 04:51:24 PM PDT 24
Peak memory 251508 kb
Host smart-91ceb093-ad4d-46eb-9817-7d9913288db0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224110582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3224110582
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.718453007
Short name T845
Test name
Test status
Simulation time 48312674 ps
CPU time 0.92 seconds
Started Aug 17 04:46:58 PM PDT 24
Finished Aug 17 04:46:59 PM PDT 24
Peak memory 212040 kb
Host smart-05d40d9d-faab-46f6-9568-83f208884afe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718453007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.718453007
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.197373248
Short name T76
Test name
Test status
Simulation time 95694912 ps
CPU time 1.07 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:00 PM PDT 24
Peak memory 208928 kb
Host smart-76d5e2d3-8e80-4ffe-95c4-5c249babbca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197373248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.197373248
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2954119747
Short name T195
Test name
Test status
Simulation time 10576994 ps
CPU time 0.83 seconds
Started Aug 17 04:47:08 PM PDT 24
Finished Aug 17 04:47:09 PM PDT 24
Peak memory 208632 kb
Host smart-bc8e8904-d363-4f92-82c9-13abef3eff0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954119747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2954119747
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3512948966
Short name T718
Test name
Test status
Simulation time 2752707125 ps
CPU time 19.05 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:18 PM PDT 24
Peak memory 218296 kb
Host smart-434fb92f-e380-4d0a-9c9c-2e690c8aa4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512948966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3512948966
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2179500989
Short name T302
Test name
Test status
Simulation time 357842045 ps
CPU time 9.34 seconds
Started Aug 17 04:47:01 PM PDT 24
Finished Aug 17 04:47:11 PM PDT 24
Peak memory 217672 kb
Host smart-05774642-9b9a-4b3e-b915-22a3689a7c80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179500989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2179500989
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1397034920
Short name T581
Test name
Test status
Simulation time 12752504911 ps
CPU time 54.93 seconds
Started Aug 17 04:47:01 PM PDT 24
Finished Aug 17 04:47:56 PM PDT 24
Peak memory 218876 kb
Host smart-3a51e6d7-f31a-4509-a845-68d411870693
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397034920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1397034920
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2091337710
Short name T313
Test name
Test status
Simulation time 1215566735 ps
CPU time 3.84 seconds
Started Aug 17 04:47:13 PM PDT 24
Finished Aug 17 04:47:17 PM PDT 24
Peak memory 217732 kb
Host smart-d8ab5602-f5d3-4a75-ae75-9effcfb13d1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091337710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
091337710
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.869689475
Short name T579
Test name
Test status
Simulation time 2096473341 ps
CPU time 14.95 seconds
Started Aug 17 04:47:06 PM PDT 24
Finished Aug 17 04:47:22 PM PDT 24
Peak memory 218200 kb
Host smart-2c9b40ae-da78-4169-aab5-8f7e9d8ce53e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869689475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.869689475
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.794647089
Short name T255
Test name
Test status
Simulation time 1887785235 ps
CPU time 27.35 seconds
Started Aug 17 04:47:00 PM PDT 24
Finished Aug 17 04:47:27 PM PDT 24
Peak memory 217608 kb
Host smart-2490802f-b2cf-416f-b19b-7552f0f79980
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794647089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.794647089
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3852399826
Short name T328
Test name
Test status
Simulation time 113249750 ps
CPU time 4.36 seconds
Started Aug 17 04:47:06 PM PDT 24
Finished Aug 17 04:47:10 PM PDT 24
Peak memory 217724 kb
Host smart-32e989c0-5cf6-4801-b7e2-2e8a4f0568c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852399826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3852399826
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.26340069
Short name T857
Test name
Test status
Simulation time 5533008484 ps
CPU time 73.35 seconds
Started Aug 17 04:47:04 PM PDT 24
Finished Aug 17 04:48:17 PM PDT 24
Peak memory 250920 kb
Host smart-e568ce4f-09d1-415a-a0b4-8d269a39d541
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26340069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
state_failure.26340069
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1189806832
Short name T686
Test name
Test status
Simulation time 670502292 ps
CPU time 23.73 seconds
Started Aug 17 04:47:00 PM PDT 24
Finished Aug 17 04:47:24 PM PDT 24
Peak memory 250412 kb
Host smart-f5687782-c369-4441-ab40-689c581f6c35
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189806832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1189806832
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1173562005
Short name T805
Test name
Test status
Simulation time 87945654 ps
CPU time 3.16 seconds
Started Aug 17 04:47:08 PM PDT 24
Finished Aug 17 04:47:12 PM PDT 24
Peak memory 218272 kb
Host smart-0ac5b40d-69e7-4988-a245-cae570856dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173562005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1173562005
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3511179874
Short name T568
Test name
Test status
Simulation time 693831677 ps
CPU time 6.15 seconds
Started Aug 17 04:47:04 PM PDT 24
Finished Aug 17 04:47:11 PM PDT 24
Peak memory 217956 kb
Host smart-84228dae-0dbb-4207-a0df-3491c880b338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511179874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3511179874
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1438974907
Short name T712
Test name
Test status
Simulation time 1696330196 ps
CPU time 13.06 seconds
Started Aug 17 04:47:01 PM PDT 24
Finished Aug 17 04:47:14 PM PDT 24
Peak memory 226044 kb
Host smart-6cdd3826-a66b-4ef4-88e9-67f08c74f08f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438974907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1438974907
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2608545527
Short name T820
Test name
Test status
Simulation time 311212790 ps
CPU time 9.85 seconds
Started Aug 17 04:47:03 PM PDT 24
Finished Aug 17 04:47:13 PM PDT 24
Peak memory 225940 kb
Host smart-276ccf26-584c-4240-a1f2-e1c662b407b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608545527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2608545527
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3646083485
Short name T218
Test name
Test status
Simulation time 434734122 ps
CPU time 9.26 seconds
Started Aug 17 04:47:10 PM PDT 24
Finished Aug 17 04:47:20 PM PDT 24
Peak memory 217000 kb
Host smart-02a0da5d-99f0-49c5-960b-6443f3a46c41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646083485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
646083485
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2101034468
Short name T63
Test name
Test status
Simulation time 314448469 ps
CPU time 11.75 seconds
Started Aug 17 04:47:01 PM PDT 24
Finished Aug 17 04:47:13 PM PDT 24
Peak memory 218340 kb
Host smart-aa015486-c399-4840-a853-6e65cb2a8e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101034468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2101034468
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.971153040
Short name T16
Test name
Test status
Simulation time 37775736 ps
CPU time 2.25 seconds
Started Aug 17 04:47:02 PM PDT 24
Finished Aug 17 04:47:04 PM PDT 24
Peak memory 217668 kb
Host smart-ef73d528-14c9-4898-9cf0-9e8cab0aedef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971153040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.971153040
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1140956279
Short name T713
Test name
Test status
Simulation time 2787215212 ps
CPU time 25.39 seconds
Started Aug 17 04:47:04 PM PDT 24
Finished Aug 17 04:47:30 PM PDT 24
Peak memory 251240 kb
Host smart-ed606de4-dffc-4653-9052-ff4d72e647dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140956279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1140956279
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1859175600
Short name T641
Test name
Test status
Simulation time 321975858 ps
CPU time 6.1 seconds
Started Aug 17 04:46:59 PM PDT 24
Finished Aug 17 04:47:05 PM PDT 24
Peak memory 246820 kb
Host smart-33404835-e306-48c8-ac6c-9c0982a5d26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859175600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1859175600
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.4194592293
Short name T233
Test name
Test status
Simulation time 4078389241 ps
CPU time 99.23 seconds
Started Aug 17 04:47:01 PM PDT 24
Finished Aug 17 04:48:40 PM PDT 24
Peak memory 271352 kb
Host smart-226f852b-2fa7-45c9-ae7f-d4e11728cf75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194592293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.4194592293
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1136515126
Short name T46
Test name
Test status
Simulation time 87138393 ps
CPU time 0.86 seconds
Started Aug 17 04:47:03 PM PDT 24
Finished Aug 17 04:47:04 PM PDT 24
Peak memory 208984 kb
Host smart-86075e77-3995-448f-8955-d85195c6a2a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136515126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1136515126
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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