Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38680 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[1] |
1313 |
1 |
|
|
T17 |
2 |
|
T18 |
10 |
|
T33 |
9 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39237 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[1] |
756 |
1 |
|
|
T10 |
18 |
|
T42 |
10 |
|
T43 |
20 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38855 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
56 |
auto[1] |
1138 |
1 |
|
|
T3 |
7 |
|
T11 |
7 |
|
T55 |
6 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38809 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
54 |
auto[1] |
1184 |
1 |
|
|
T3 |
9 |
|
T11 |
6 |
|
T55 |
6 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38822 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
56 |
auto[1] |
1171 |
1 |
|
|
T3 |
7 |
|
T11 |
11 |
|
T15 |
2 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
36794 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
no_err_inj |
3199 |
1 |
|
|
T4 |
20 |
|
T14 |
15 |
|
T15 |
7 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38784 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[1] |
1209 |
1 |
|
|
T17 |
4 |
|
T18 |
13 |
|
T33 |
10 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39236 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[1] |
757 |
1 |
|
|
T10 |
16 |
|
T42 |
15 |
|
T43 |
16 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
30515 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T10 |
70 |
auto[1] |
9478 |
1 |
|
|
T3 |
63 |
|
T4 |
20 |
|
T5 |
6 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38885 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
56 |
auto[1] |
1108 |
1 |
|
|
T3 |
7 |
|
T11 |
14 |
|
T55 |
14 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38924 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
54 |
auto[1] |
1069 |
1 |
|
|
T3 |
9 |
|
T11 |
8 |
|
T55 |
8 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38869 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
1124 |
1 |
|
|
T3 |
5 |
|
T11 |
12 |
|
T15 |
1 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38687 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[1] |
1306 |
1 |
|
|
T17 |
1 |
|
T18 |
12 |
|
T33 |
6 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38551 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[1] |
1442 |
1 |
|
|
T16 |
14 |
|
T17 |
5 |
|
T70 |
2 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39275 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[1] |
718 |
1 |
|
|
T10 |
12 |
|
T42 |
12 |
|
T43 |
10 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39225 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[1] |
768 |
1 |
|
|
T10 |
10 |
|
T42 |
23 |
|
T43 |
17 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39251 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[1] |
742 |
1 |
|
|
T10 |
14 |
|
T42 |
10 |
|
T43 |
15 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38340 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[1] |
1653 |
1 |
|
|
T15 |
11 |
|
T18 |
23 |
|
T227 |
10 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36294 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[1] |
3699 |
1 |
|
|
T45 |
84 |
|
T59 |
52 |
|
T44 |
87 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38882 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
56 |
auto[1] |
1111 |
1 |
|
|
T3 |
7 |
|
T11 |
12 |
|
T15 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38862 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
56 |
auto[1] |
1131 |
1 |
|
|
T3 |
7 |
|
T11 |
5 |
|
T55 |
13 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38855 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
1138 |
1 |
|
|
T3 |
5 |
|
T11 |
10 |
|
T55 |
11 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38700 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[1] |
1293 |
1 |
|
|
T17 |
2 |
|
T18 |
15 |
|
T33 |
11 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
34859 |
1 |
|
|
T2 |
82 |
|
T3 |
63 |
|
T10 |
70 |
auto[1] |
5134 |
1 |
|
|
T1 |
65 |
|
T17 |
4 |
|
T154 |
75 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36269 |
1 |
|
|
T1 |
65 |
|
T3 |
63 |
|
T10 |
70 |
auto[1] |
3724 |
1 |
|
|
T2 |
82 |
|
T56 |
58 |
|
T57 |
70 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39993 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38734 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[1] |
1259 |
1 |
|
|
T17 |
4 |
|
T18 |
15 |
|
T33 |
12 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38732 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[1] |
1261 |
1 |
|
|
T17 |
3 |
|
T18 |
6 |
|
T33 |
6 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38754 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[1] |
1239 |
1 |
|
|
T17 |
2 |
|
T18 |
16 |
|
T33 |
6 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
35959 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
63 |
auto[0] |
no_err_inj |
2381 |
1 |
|
|
T4 |
20 |
|
T14 |
15 |
|
T5 |
6 |
auto[1] |
err_inj |
835 |
1 |
|
|
T15 |
4 |
|
T18 |
15 |
|
T227 |
5 |
auto[1] |
no_err_inj |
818 |
1 |
|
|
T15 |
7 |
|
T18 |
8 |
|
T227 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37292 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
56 |
auto[0] |
auto[1] |
1048 |
1 |
|
|
T3 |
7 |
|
T11 |
5 |
|
T55 |
13 |
auto[1] |
auto[0] |
1570 |
1 |
|
|
T15 |
11 |
|
T18 |
22 |
|
T227 |
7 |
auto[1] |
auto[1] |
83 |
1 |
|
|
T18 |
1 |
|
T227 |
3 |
|
T20 |
3 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37354 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
54 |
auto[0] |
auto[1] |
986 |
1 |
|
|
T3 |
9 |
|
T11 |
8 |
|
T55 |
8 |
auto[1] |
auto[0] |
1570 |
1 |
|
|
T15 |
11 |
|
T18 |
22 |
|
T227 |
10 |
auto[1] |
auto[1] |
83 |
1 |
|
|
T18 |
1 |
|
T228 |
1 |
|
T229 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37288 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
58 |
auto[0] |
auto[1] |
1052 |
1 |
|
|
T3 |
5 |
|
T11 |
10 |
|
T55 |
11 |
auto[1] |
auto[0] |
1567 |
1 |
|
|
T15 |
11 |
|
T18 |
22 |
|
T227 |
10 |
auto[1] |
auto[1] |
86 |
1 |
|
|
T18 |
1 |
|
T228 |
1 |
|
T21 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37259 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
54 |
auto[0] |
auto[1] |
1081 |
1 |
|
|
T3 |
9 |
|
T11 |
6 |
|
T55 |
6 |
auto[1] |
auto[0] |
1550 |
1 |
|
|
T15 |
11 |
|
T18 |
22 |
|
T227 |
10 |
auto[1] |
auto[1] |
103 |
1 |
|
|
T18 |
1 |
|
T20 |
2 |
|
T228 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37267 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
56 |
auto[0] |
auto[1] |
1073 |
1 |
|
|
T3 |
7 |
|
T11 |
11 |
|
T55 |
14 |
auto[1] |
auto[0] |
1555 |
1 |
|
|
T15 |
9 |
|
T18 |
21 |
|
T227 |
9 |
auto[1] |
auto[1] |
98 |
1 |
|
|
T15 |
2 |
|
T18 |
2 |
|
T227 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37298 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T3 |
56 |
auto[0] |
auto[1] |
1042 |
1 |
|
|
T3 |
7 |
|
T11 |
7 |
|
T55 |
6 |
auto[1] |
auto[0] |
1557 |
1 |
|
|
T15 |
11 |
|
T18 |
21 |
|
T227 |
10 |
auto[1] |
auto[1] |
96 |
1 |
|
|
T18 |
2 |
|
T20 |
1 |
|
T21 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29722 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T10 |
70 |
auto[0] |
auto[1] |
793 |
1 |
|
|
T18 |
10 |
|
T33 |
9 |
|
T19 |
12 |
auto[1] |
auto[0] |
8958 |
1 |
|
|
T3 |
63 |
|
T4 |
20 |
|
T5 |
6 |
auto[1] |
auto[1] |
520 |
1 |
|
|
T17 |
2 |
|
T19 |
7 |
|
T97 |
11 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29792 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T10 |
70 |
auto[0] |
auto[1] |
723 |
1 |
|
|
T18 |
13 |
|
T33 |
10 |
|
T19 |
17 |
auto[1] |
auto[0] |
8992 |
1 |
|
|
T3 |
63 |
|
T4 |
20 |
|
T5 |
6 |
auto[1] |
auto[1] |
486 |
1 |
|
|
T17 |
4 |
|
T19 |
6 |
|
T97 |
10 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29623 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T10 |
70 |
auto[0] |
auto[1] |
892 |
1 |
|
|
T16 |
14 |
|
T70 |
2 |
|
T214 |
6 |
auto[1] |
auto[0] |
8928 |
1 |
|
|
T3 |
63 |
|
T4 |
20 |
|
T5 |
6 |
auto[1] |
auto[1] |
550 |
1 |
|
|
T17 |
5 |
|
T230 |
18 |
|
T231 |
13 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29695 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T10 |
70 |
auto[0] |
auto[1] |
820 |
1 |
|
|
T18 |
12 |
|
T33 |
6 |
|
T19 |
19 |
auto[1] |
auto[0] |
8992 |
1 |
|
|
T3 |
63 |
|
T4 |
20 |
|
T5 |
6 |
auto[1] |
auto[1] |
486 |
1 |
|
|
T17 |
1 |
|
T19 |
7 |
|
T97 |
10 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
25930 |
1 |
|
|
T2 |
82 |
|
T10 |
70 |
|
T11 |
85 |
auto[0] |
auto[1] |
4585 |
1 |
|
|
T1 |
65 |
|
T154 |
75 |
|
T18 |
7 |
auto[1] |
auto[0] |
8929 |
1 |
|
|
T3 |
63 |
|
T4 |
20 |
|
T5 |
6 |
auto[1] |
auto[1] |
549 |
1 |
|
|
T17 |
4 |
|
T19 |
7 |
|
T97 |
8 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29806 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T10 |
70 |
auto[0] |
auto[1] |
709 |
1 |
|
|
T11 |
5 |
|
T55 |
13 |
|
T95 |
6 |
auto[1] |
auto[0] |
9056 |
1 |
|
|
T3 |
56 |
|
T4 |
20 |
|
T5 |
6 |
auto[1] |
auto[1] |
422 |
1 |
|
|
T3 |
7 |
|
T18 |
8 |
|
T20 |
3 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29798 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T10 |
70 |
auto[0] |
auto[1] |
717 |
1 |
|
|
T11 |
12 |
|
T15 |
1 |
|
T55 |
5 |
auto[1] |
auto[0] |
9084 |
1 |
|
|
T3 |
56 |
|
T4 |
20 |
|
T5 |
6 |
auto[1] |
auto[1] |
394 |
1 |
|
|
T3 |
7 |
|
T18 |
9 |
|
T20 |
1 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29836 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T10 |
70 |
auto[0] |
auto[1] |
679 |
1 |
|
|
T11 |
8 |
|
T55 |
8 |
|
T95 |
5 |
auto[1] |
auto[0] |
9088 |
1 |
|
|
T3 |
54 |
|
T4 |
20 |
|
T5 |
6 |
auto[1] |
auto[1] |
390 |
1 |
|
|
T3 |
9 |
|
T18 |
4 |
|
T229 |
2 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29784 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T10 |
70 |
auto[0] |
auto[1] |
731 |
1 |
|
|
T11 |
14 |
|
T55 |
14 |
|
T95 |
9 |
auto[1] |
auto[0] |
9101 |
1 |
|
|
T3 |
56 |
|
T4 |
20 |
|
T5 |
6 |
auto[1] |
auto[1] |
377 |
1 |
|
|
T3 |
7 |
|
T18 |
7 |
|
T21 |
2 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29787 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T10 |
70 |
auto[0] |
auto[1] |
728 |
1 |
|
|
T11 |
6 |
|
T55 |
6 |
|
T95 |
8 |
auto[1] |
auto[0] |
9022 |
1 |
|
|
T3 |
54 |
|
T4 |
20 |
|
T5 |
6 |
auto[1] |
auto[1] |
456 |
1 |
|
|
T3 |
9 |
|
T18 |
6 |
|
T20 |
2 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29770 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T10 |
70 |
auto[0] |
auto[1] |
745 |
1 |
|
|
T11 |
7 |
|
T55 |
6 |
|
T95 |
10 |
auto[1] |
auto[0] |
9085 |
1 |
|
|
T3 |
56 |
|
T4 |
20 |
|
T5 |
6 |
auto[1] |
auto[1] |
393 |
1 |
|
|
T3 |
7 |
|
T18 |
4 |
|
T20 |
1 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29737 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T10 |
70 |
auto[0] |
auto[1] |
778 |
1 |
|
|
T18 |
16 |
|
T33 |
6 |
|
T19 |
22 |
auto[1] |
auto[0] |
9017 |
1 |
|
|
T3 |
63 |
|
T4 |
20 |
|
T5 |
6 |
auto[1] |
auto[1] |
461 |
1 |
|
|
T17 |
2 |
|
T19 |
5 |
|
T97 |
17 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29753 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T10 |
70 |
auto[0] |
auto[1] |
762 |
1 |
|
|
T17 |
1 |
|
T18 |
6 |
|
T33 |
6 |
auto[1] |
auto[0] |
8979 |
1 |
|
|
T3 |
63 |
|
T4 |
20 |
|
T5 |
6 |
auto[1] |
auto[1] |
499 |
1 |
|
|
T17 |
2 |
|
T19 |
6 |
|
T97 |
9 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29475 |
1 |
|
|
T1 |
65 |
|
T2 |
82 |
|
T10 |
70 |
auto[0] |
auto[1] |
1040 |
1 |
|
|
T15 |
11 |
|
T18 |
13 |
|
T227 |
10 |
auto[1] |
auto[0] |
8865 |
1 |
|
|
T3 |
63 |
|
T4 |
20 |
|
T5 |
6 |
auto[1] |
auto[1] |
613 |
1 |
|
|
T18 |
10 |
|
T20 |
13 |
|
T21 |
13 |