Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67333598

1

T1

38270

T2

28230

T3

125686

auto[1]

1060177

1

T3

2842

T10

1386

T11

3366

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67335123

1

T1

38270

T2

28230

T3

126176

auto[1]

1058652

1

T3

2352

T10

1386

T11

2871

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5158999	1			T1	5830		T2	7173		T3	14896
auto[IdleSt]	16685965	1			T1	5441		T2	2414		T3	7960
auto[ClkMuxSt]	28673	1			T1	65		T2	82		T10	60
auto[CntIncrSt]	28471	1			T1	65		T2	82		T10	60
auto[CntProgSt]	1345566	1			T1	14442		T2	2313		T10	1177
auto[TransCheckSt]	22659	1			T1	65		T2	82		T10	42
auto[TokenHashSt]	24042380	1			T1	1304		T2	3123		T10	962
auto[FlashRmaSt]	28995	1			T2	83		T10	110		T4	36
auto[TokenCheck0St]	10043	1			T2	30		T10	36		T4	18
auto[TokenCheck1St]	7264	1			T2	9		T10	22		T4	18
auto[TransProgSt]	360576	1			T10	577		T4	1885		T14	128
auto[PostTransSt]	9335771	1			T1	11058		T2	12839		T10	7489
auto[ScrapSt]	189457	1			T4	1934		T17	11		T45	12
auto[EscalateSt]	4407806	1			T3	24327		T10	3398		T11	7937
auto[InvalidSt]	6740008	1			T3	81336		T10	750		T11	4728

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1142	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6740008	1			T3	81336		T10	750		T11	4728
EscalateSt	4407806	1			T3	24327		T10	3398		T11	7937
ScrapSt	189457	1			T4	1934		T17	11		T45	12
PostTransSt	9335771	1			T1	11058		T2	12839		T10	7489
TransProgSt	360576	1			T10	577		T4	1885		T14	128
TokenCheck1St	7264	1			T2	9		T10	22		T4	18
TokenCheck0St	10043	1			T2	30		T10	36		T4	18
FlashRmaSt	28995	1			T2	83		T10	110		T4	36
TokenHashSt	24042380	1			T1	1304		T2	3123		T10	962
TransCheckSt	22659	1			T1	65		T2	82		T10	42
CntProgSt	1345566	1			T1	14442		T2	2313		T10	1177
CntIncrSt	28471	1			T1	65		T2	82		T10	60
ClkMuxSt	28673	1			T1	65		T2	82		T10	60
IdleSt	16685965	1			T1	5441		T2	2414		T3	7960
ResetSt	5158999	1			T1	5830		T2	7173		T3	14896
arcs[ResetSt=>IdleSt]	40764	1			T1	66		T2	83		T3	59
arcs[IdleSt=>ScrapSt]	255	1			T4	2		T17	2		T45	3
arcs[IdleSt=>ClkMuxSt]	28509	1			T1	65		T2	82		T10	60
arcs[ClkMuxSt=>CntIncrSt]	28471	1			T1	65		T2	82		T10	60
arcs[CntIncrSt=>PostTransSt]	1262	1			T17	3		T18	6		T33	6
arcs[CntIncrSt=>CntProgSt]	27150	1			T1	65		T2	82		T10	60
arcs[CntProgSt=>PostTransSt]	3478	1			T10	18		T16	14		T42	10
arcs[CntProgSt=>TransCheckSt]	22659	1			T1	65		T2	82		T10	42
arcs[TransCheckSt=>PostTransSt]	3130	1			T2	45		T17	3		T56	31
arcs[TransCheckSt=>TokenHashSt]	19442	1			T1	65		T2	37		T10	42
arcs[TokenHashSt=>PostTransSt]	8556	1			T1	65		T2	7		T10	6
arcs[TokenHashSt=>FlashRmaSt]	10080	1			T2	30		T10	36		T4	18
arcs[FlashRmaSt=>TokenCheck0St]	10043	1			T2	30		T10	36		T4	18
arcs[TokenCheck0St=>PostTransSt]	2712	1			T2	21		T10	14		T42	15
arcs[TokenCheck0St=>TokenCheck1St]	7264	1			T2	9		T10	22		T4	18
arcs[TokenCheck1St=>PostTransSt]	593	1			T2	9		T10	2		T43	1
arcs[TransProgSt=>PostTransSt]	5865	1			T10	20		T4	18		T14	15
arcs[IdleSt=>EscalateSt]	170	1			T45	8		T59	9		T44	7
arcs[ClkMuxSt=>EscalateSt]	38	1			T45	1		T44	2		T30	1
arcs[CntIncrSt=>EscalateSt]	59	1			T44	1		T30	1		T58	2
arcs[CntProgSt=>EscalateSt]	1013	1			T45	29		T59	1		T44	25
arcs[TransCheckSt=>EscalateSt]	87	1			T59	2		T44	1		T64	4
arcs[TokenHashSt=>EscalateSt]	806	1			T45	7		T59	11		T44	5
arcs[FlashRmaSt=>EscalateSt]	37	1			T45	1		T58	1		T60	2
arcs[TokenCheck0St=>EscalateSt]	67	1			T45	3		T44	1		T30	1
arcs[TokenCheck1St=>EscalateSt]	32	1			T45	1		T59	1		T30	2
arcs[TransProgSt=>EscalateSt]	774	1			T45	24		T59	6		T44	29
arcs[PostTransSt=>EscalateSt]	3820	1			T10	18		T16	14		T42	10
arcs[InvalidSt=>EscalateSt]	8695	1			T3	53		T10	10		T11	63

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5158840	1			T1	5830		T2	7173		T3	14896
auto[0]	auto[IdleSt]	16685841	1			T1	5441		T2	2414		T3	7960
auto[0]	auto[ClkMuxSt]	28654	1			T1	65		T2	82		T10	60
auto[0]	auto[CntIncrSt]	28435	1			T1	65		T2	82		T10	60
auto[0]	auto[CntProgSt]	1344876	1			T1	14442		T2	2313		T10	1177
auto[0]	auto[TransCheckSt]	22606	1			T1	65		T2	82		T10	42
auto[0]	auto[TokenHashSt]	24041846	1			T1	1304		T2	3123		T10	962
auto[0]	auto[FlashRmaSt]	28972	1			T2	83		T10	110		T4	36
auto[0]	auto[TokenCheck0St]	9997	1			T2	30		T10	36		T4	18
auto[0]	auto[TokenCheck1St]	7239	1			T2	9		T10	22		T4	18
auto[0]	auto[TransProgSt]	360054	1			T10	577		T4	1885		T14	128
auto[0]	auto[PostTransSt]	9333828	1			T1	11058		T2	12839		T10	7482
auto[0]	auto[ScrapSt]	189400	1			T4	1934		T17	11		T45	9
auto[0]	auto[EscalateSt]	3356244	1			T3	21514		T10	2026		T11	4605
auto[0]	auto[InvalidSt]	6735624	1			T3	81307		T10	743		T11	4694
auto[1]	auto[ResetSt]	159	1			T45	5		T59	1		T44	5
auto[1]	auto[IdleSt]	124	1			T45	6		T59	6		T44	5
auto[1]	auto[ClkMuxSt]	19	1			T45	1		T30	1		T224	1
auto[1]	auto[CntIncrSt]	36	1			T44	1		T58	2		T60	2
auto[1]	auto[CntProgSt]	690	1			T45	19		T44	20		T30	18
auto[1]	auto[TransCheckSt]	53	1			T59	2		T64	2		T60	2
auto[1]	auto[TokenHashSt]	534	1			T45	6		T59	7		T44	4
auto[1]	auto[FlashRmaSt]	23	1			T45	1		T58	1		T60	2
auto[1]	auto[TokenCheck0St]	46	1			T45	2		T58	1		T224	1
auto[1]	auto[TokenCheck1St]	25	1			T45	1		T59	1		T30	2
auto[1]	auto[TransProgSt]	522	1			T45	17		T59	5		T44	20
auto[1]	auto[PostTransSt]	1943	1			T10	7		T16	6		T42	3
auto[1]	auto[ScrapSt]	57	1			T45	3		T44	2		T64	1
auto[1]	auto[EscalateSt]	1051562	1			T3	2813		T10	1372		T11	3332
auto[1]	auto[InvalidSt]	4384	1			T3	29		T10	7		T11	34

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5158842	1			T1	5830		T2	7173		T3	14896
auto[0]	auto[IdleSt]	16685858	1			T1	5441		T2	2414		T3	7960
auto[0]	auto[ClkMuxSt]	28641	1			T1	65		T2	82		T10	60
auto[0]	auto[CntIncrSt]	28428	1			T1	65		T2	82		T10	60
auto[0]	auto[CntProgSt]	1344894	1			T1	14442		T2	2313		T10	1177
auto[0]	auto[TransCheckSt]	22597	1			T1	65		T2	82		T10	42
auto[0]	auto[TokenHashSt]	24041845	1			T1	1304		T2	3123		T10	962
auto[0]	auto[FlashRmaSt]	28968	1			T2	83		T10	110		T4	36
auto[0]	auto[TokenCheck0St]	9995	1			T2	30		T10	36		T4	18
auto[0]	auto[TokenCheck1St]	7245	1			T2	9		T10	22		T4	18
auto[0]	auto[TransProgSt]	360052	1			T10	577		T4	1885		T14	128
auto[0]	auto[PostTransSt]	9333787	1			T1	11058		T2	12839		T10	7478
auto[0]	auto[ScrapSt]	189405	1			T4	1934		T17	11		T45	9
auto[0]	auto[EscalateSt]	3357727	1			T3	21999		T10	2026		T11	5095
auto[0]	auto[InvalidSt]	6735697	1			T3	81312		T10	747		T11	4699
auto[1]	auto[ResetSt]	157	1			T45	5		T59	5		T44	6
auto[1]	auto[IdleSt]	107	1			T45	4		T59	7		T44	5
auto[1]	auto[ClkMuxSt]	32	1			T45	1		T44	2		T30	1
auto[1]	auto[CntIncrSt]	43	1			T30	1		T58	1		T60	2
auto[1]	auto[CntProgSt]	672	1			T45	16		T59	1		T44	16
auto[1]	auto[TransCheckSt]	62	1			T59	1		T44	1		T64	3
auto[1]	auto[TokenHashSt]	535	1			T45	2		T59	8		T44	2
auto[1]	auto[FlashRmaSt]	27	1			T60	1		T225	1		T226	1
auto[1]	auto[TokenCheck0St]	48	1			T45	3		T44	1		T30	1
auto[1]	auto[TokenCheck1St]	19	1			T45	1		T59	1		T30	1
auto[1]	auto[TransProgSt]	524	1			T45	19		T59	4		T44	17
auto[1]	auto[PostTransSt]	1984	1			T10	11		T16	8		T42	7
auto[1]	auto[ScrapSt]	52	1			T45	3		T59	2		T44	3
auto[1]	auto[EscalateSt]	1050079	1			T3	2328		T10	1372		T11	2842
auto[1]	auto[InvalidSt]	4311	1			T3	24		T10	3		T11	29