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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.15 97.99 95.23 93.40 100.00 98.55 98.76 96.11


Total test records in report: 997
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T813 /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2342373152 Aug 19 04:40:08 PM PDT 24 Aug 19 04:40:09 PM PDT 24 14619932 ps
T814 /workspace/coverage/default/41.lc_ctrl_state_failure.1124636199 Aug 19 04:41:15 PM PDT 24 Aug 19 04:41:44 PM PDT 24 3239374107 ps
T815 /workspace/coverage/default/34.lc_ctrl_sec_mubi.3077931677 Aug 19 04:41:04 PM PDT 24 Aug 19 04:41:21 PM PDT 24 822565737 ps
T816 /workspace/coverage/default/16.lc_ctrl_prog_failure.1460298754 Aug 19 04:40:00 PM PDT 24 Aug 19 04:40:02 PM PDT 24 210643959 ps
T817 /workspace/coverage/default/27.lc_ctrl_state_post_trans.986606943 Aug 19 04:40:22 PM PDT 24 Aug 19 04:40:30 PM PDT 24 91654007 ps
T818 /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3786718831 Aug 19 04:40:04 PM PDT 24 Aug 19 04:40:15 PM PDT 24 3021384010 ps
T819 /workspace/coverage/default/40.lc_ctrl_state_failure.952872174 Aug 19 04:41:22 PM PDT 24 Aug 19 04:41:45 PM PDT 24 584272184 ps
T82 /workspace/coverage/default/45.lc_ctrl_alert_test.2610086238 Aug 19 04:41:50 PM PDT 24 Aug 19 04:41:51 PM PDT 24 29710839 ps
T820 /workspace/coverage/default/3.lc_ctrl_jtag_access.2502471789 Aug 19 04:38:58 PM PDT 24 Aug 19 04:38:59 PM PDT 24 132185607 ps
T821 /workspace/coverage/default/9.lc_ctrl_stress_all.2542535413 Aug 19 04:39:25 PM PDT 24 Aug 19 04:40:13 PM PDT 24 10787395625 ps
T822 /workspace/coverage/default/49.lc_ctrl_jtag_access.4253831817 Aug 19 04:42:02 PM PDT 24 Aug 19 04:42:20 PM PDT 24 718406251 ps
T823 /workspace/coverage/default/19.lc_ctrl_sec_token_digest.404936539 Aug 19 04:40:11 PM PDT 24 Aug 19 04:40:22 PM PDT 24 2889469242 ps
T824 /workspace/coverage/default/5.lc_ctrl_regwen_during_op.760401444 Aug 19 04:39:04 PM PDT 24 Aug 19 04:39:10 PM PDT 24 1245487536 ps
T825 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.925051529 Aug 19 04:39:24 PM PDT 24 Aug 19 04:39:35 PM PDT 24 777653425 ps
T826 /workspace/coverage/default/40.lc_ctrl_alert_test.3986850024 Aug 19 04:41:17 PM PDT 24 Aug 19 04:41:19 PM PDT 24 205887629 ps
T827 /workspace/coverage/default/34.lc_ctrl_stress_all.667783204 Aug 19 04:41:04 PM PDT 24 Aug 19 04:45:33 PM PDT 24 25901927501 ps
T828 /workspace/coverage/default/11.lc_ctrl_errors.2809386050 Aug 19 04:39:28 PM PDT 24 Aug 19 04:39:45 PM PDT 24 1653887858 ps
T829 /workspace/coverage/default/42.lc_ctrl_errors.3381568810 Aug 19 04:41:25 PM PDT 24 Aug 19 04:41:35 PM PDT 24 441425161 ps
T830 /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3077459854 Aug 19 04:42:03 PM PDT 24 Aug 19 04:42:12 PM PDT 24 198488174 ps
T831 /workspace/coverage/default/21.lc_ctrl_stress_all.2094141125 Aug 19 04:40:17 PM PDT 24 Aug 19 04:42:40 PM PDT 24 60911888333 ps
T832 /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1932585401 Aug 19 04:40:47 PM PDT 24 Aug 19 04:41:00 PM PDT 24 1508469724 ps
T833 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2822806346 Aug 19 04:39:13 PM PDT 24 Aug 19 04:39:14 PM PDT 24 51805061 ps
T173 /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.2334514032 Aug 19 04:40:08 PM PDT 24 Aug 19 04:42:18 PM PDT 24 2987898096 ps
T834 /workspace/coverage/default/11.lc_ctrl_smoke.258717215 Aug 19 04:39:29 PM PDT 24 Aug 19 04:39:30 PM PDT 24 28197367 ps
T835 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.302268585 Aug 19 04:41:10 PM PDT 24 Aug 19 04:41:21 PM PDT 24 513440437 ps
T836 /workspace/coverage/default/39.lc_ctrl_prog_failure.156752640 Aug 19 04:41:17 PM PDT 24 Aug 19 04:41:20 PM PDT 24 137177086 ps
T837 /workspace/coverage/default/38.lc_ctrl_sec_mubi.3449072275 Aug 19 04:41:05 PM PDT 24 Aug 19 04:41:16 PM PDT 24 516258957 ps
T838 /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3443061872 Aug 19 04:40:03 PM PDT 24 Aug 19 04:40:06 PM PDT 24 394149590 ps
T839 /workspace/coverage/default/1.lc_ctrl_jtag_errors.942419342 Aug 19 04:38:54 PM PDT 24 Aug 19 04:39:26 PM PDT 24 4418006370 ps
T840 /workspace/coverage/default/21.lc_ctrl_state_post_trans.2026589881 Aug 19 04:40:15 PM PDT 24 Aug 19 04:40:23 PM PDT 24 101316748 ps
T841 /workspace/coverage/default/29.lc_ctrl_smoke.1565712678 Aug 19 04:40:47 PM PDT 24 Aug 19 04:40:53 PM PDT 24 141047787 ps
T842 /workspace/coverage/default/47.lc_ctrl_stress_all.2411957564 Aug 19 04:42:04 PM PDT 24 Aug 19 04:46:41 PM PDT 24 7907840425 ps
T843 /workspace/coverage/default/23.lc_ctrl_prog_failure.598355902 Aug 19 04:40:18 PM PDT 24 Aug 19 04:40:21 PM PDT 24 175036909 ps
T844 /workspace/coverage/default/25.lc_ctrl_prog_failure.1707723159 Aug 19 04:40:21 PM PDT 24 Aug 19 04:40:24 PM PDT 24 70718492 ps
T845 /workspace/coverage/default/48.lc_ctrl_security_escalation.1627902898 Aug 19 04:42:00 PM PDT 24 Aug 19 04:42:13 PM PDT 24 1178390714 ps
T846 /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.4231816356 Aug 19 04:39:12 PM PDT 24 Aug 19 04:39:35 PM PDT 24 3404984164 ps
T847 /workspace/coverage/default/9.lc_ctrl_sec_mubi.2259506439 Aug 19 04:39:26 PM PDT 24 Aug 19 04:39:39 PM PDT 24 1913450643 ps
T848 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2146260251 Aug 19 04:41:49 PM PDT 24 Aug 19 04:42:01 PM PDT 24 378628628 ps
T849 /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3867435372 Aug 19 04:42:04 PM PDT 24 Aug 19 04:42:14 PM PDT 24 5446565735 ps
T850 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1275999793 Aug 19 04:40:04 PM PDT 24 Aug 19 04:40:11 PM PDT 24 1058354690 ps
T851 /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.969612077 Aug 19 04:39:07 PM PDT 24 Aug 19 04:41:10 PM PDT 24 3700488224 ps
T852 /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2919119499 Aug 19 04:38:56 PM PDT 24 Aug 19 04:38:57 PM PDT 24 12968026 ps
T853 /workspace/coverage/default/18.lc_ctrl_errors.91050320 Aug 19 04:40:07 PM PDT 24 Aug 19 04:40:17 PM PDT 24 249525908 ps
T854 /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2817266732 Aug 19 04:38:55 PM PDT 24 Aug 19 04:39:12 PM PDT 24 1029806065 ps
T855 /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1741494990 Aug 19 04:39:21 PM PDT 24 Aug 19 04:39:22 PM PDT 24 71897423 ps
T856 /workspace/coverage/default/45.lc_ctrl_state_failure.2305164345 Aug 19 04:41:54 PM PDT 24 Aug 19 04:42:13 PM PDT 24 1296375887 ps
T857 /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1117157438 Aug 19 04:40:53 PM PDT 24 Aug 19 04:40:54 PM PDT 24 13384474 ps
T858 /workspace/coverage/default/14.lc_ctrl_state_post_trans.612393874 Aug 19 04:39:57 PM PDT 24 Aug 19 04:40:07 PM PDT 24 83653488 ps
T859 /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1114754272 Aug 19 04:41:17 PM PDT 24 Aug 19 04:41:43 PM PDT 24 1000373329 ps
T860 /workspace/coverage/default/29.lc_ctrl_errors.1748643655 Aug 19 04:40:56 PM PDT 24 Aug 19 04:41:08 PM PDT 24 449840512 ps
T861 /workspace/coverage/default/1.lc_ctrl_alert_test.3872878360 Aug 19 04:38:54 PM PDT 24 Aug 19 04:38:56 PM PDT 24 35665565 ps
T862 /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2187219791 Aug 19 04:42:01 PM PDT 24 Aug 19 04:42:12 PM PDT 24 958725451 ps
T863 /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2011620126 Aug 19 04:40:02 PM PDT 24 Aug 19 04:40:49 PM PDT 24 1027904726 ps
T864 /workspace/coverage/default/32.lc_ctrl_smoke.3622853799 Aug 19 04:40:54 PM PDT 24 Aug 19 04:40:56 PM PDT 24 24141053 ps
T865 /workspace/coverage/default/6.lc_ctrl_alert_test.2419051797 Aug 19 04:39:16 PM PDT 24 Aug 19 04:39:17 PM PDT 24 72262694 ps
T866 /workspace/coverage/default/7.lc_ctrl_jtag_priority.167826760 Aug 19 04:39:26 PM PDT 24 Aug 19 04:39:33 PM PDT 24 3844865458 ps
T867 /workspace/coverage/default/15.lc_ctrl_sec_mubi.3450698624 Aug 19 04:40:03 PM PDT 24 Aug 19 04:40:19 PM PDT 24 789552830 ps
T868 /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3325575579 Aug 19 04:41:10 PM PDT 24 Aug 19 04:41:22 PM PDT 24 1759900022 ps
T869 /workspace/coverage/default/29.lc_ctrl_state_post_trans.1194696219 Aug 19 04:40:41 PM PDT 24 Aug 19 04:40:48 PM PDT 24 293251012 ps
T83 /workspace/coverage/default/22.lc_ctrl_alert_test.3264054747 Aug 19 04:40:13 PM PDT 24 Aug 19 04:40:14 PM PDT 24 96806043 ps
T870 /workspace/coverage/default/46.lc_ctrl_state_post_trans.4198028840 Aug 19 04:41:50 PM PDT 24 Aug 19 04:41:57 PM PDT 24 250307688 ps
T871 /workspace/coverage/default/4.lc_ctrl_state_failure.1758736848 Aug 19 04:40:06 PM PDT 24 Aug 19 04:40:33 PM PDT 24 1080524603 ps
T118 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2622134785 Aug 19 04:27:13 PM PDT 24 Aug 19 04:27:15 PM PDT 24 27322807 ps
T125 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4203001176 Aug 19 04:27:58 PM PDT 24 Aug 19 04:27:59 PM PDT 24 51591122 ps
T126 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1160330979 Aug 19 04:27:16 PM PDT 24 Aug 19 04:27:17 PM PDT 24 348196769 ps
T142 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.814240992 Aug 19 04:27:15 PM PDT 24 Aug 19 04:27:16 PM PDT 24 45127307 ps
T119 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3543926961 Aug 19 04:27:33 PM PDT 24 Aug 19 04:27:34 PM PDT 24 18549558 ps
T208 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3408380403 Aug 19 04:27:47 PM PDT 24 Aug 19 04:27:48 PM PDT 24 91317275 ps
T209 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3123742982 Aug 19 04:27:14 PM PDT 24 Aug 19 04:27:15 PM PDT 24 123040889 ps
T210 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3638732009 Aug 19 04:27:04 PM PDT 24 Aug 19 04:27:06 PM PDT 24 154360399 ps
T146 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3286241017 Aug 19 04:27:17 PM PDT 24 Aug 19 04:27:19 PM PDT 24 76537751 ps
T115 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4151996247 Aug 19 04:27:30 PM PDT 24 Aug 19 04:27:36 PM PDT 24 686430652 ps
T116 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.761132947 Aug 19 04:27:15 PM PDT 24 Aug 19 04:27:18 PM PDT 24 65434490 ps
T117 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2178032957 Aug 19 04:27:41 PM PDT 24 Aug 19 04:27:44 PM PDT 24 87175966 ps
T127 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.933659304 Aug 19 04:27:57 PM PDT 24 Aug 19 04:27:59 PM PDT 24 132533217 ps
T130 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2769336671 Aug 19 04:27:33 PM PDT 24 Aug 19 04:27:37 PM PDT 24 430194914 ps
T123 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2791935048 Aug 19 04:27:33 PM PDT 24 Aug 19 04:27:35 PM PDT 24 288432960 ps
T147 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.796826763 Aug 19 04:27:13 PM PDT 24 Aug 19 04:27:15 PM PDT 24 406155878 ps
T124 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2592412511 Aug 19 04:27:25 PM PDT 24 Aug 19 04:27:26 PM PDT 24 16808313 ps
T158 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4254588847 Aug 19 04:27:33 PM PDT 24 Aug 19 04:27:34 PM PDT 24 17398294 ps
T120 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.588016385 Aug 19 04:27:15 PM PDT 24 Aug 19 04:27:17 PM PDT 24 43229101 ps
T216 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.650571680 Aug 19 04:27:10 PM PDT 24 Aug 19 04:27:13 PM PDT 24 98151700 ps
T872 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2088620788 Aug 19 04:27:31 PM PDT 24 Aug 19 04:27:32 PM PDT 24 15682261 ps
T873 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3003260181 Aug 19 04:27:39 PM PDT 24 Aug 19 04:27:41 PM PDT 24 42134035 ps
T121 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1505709287 Aug 19 04:27:14 PM PDT 24 Aug 19 04:27:18 PM PDT 24 74160919 ps
T874 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.371124755 Aug 19 04:27:15 PM PDT 24 Aug 19 04:27:19 PM PDT 24 349407262 ps
T875 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.4094121742 Aug 19 04:27:30 PM PDT 24 Aug 19 04:27:31 PM PDT 24 219246337 ps
T876 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3809322819 Aug 19 04:27:23 PM PDT 24 Aug 19 04:27:28 PM PDT 24 669873712 ps
T217 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2579777832 Aug 19 04:27:25 PM PDT 24 Aug 19 04:27:27 PM PDT 24 151043616 ps
T877 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2511368661 Aug 19 04:27:27 PM PDT 24 Aug 19 04:27:29 PM PDT 24 52013287 ps
T878 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1582696290 Aug 19 04:28:07 PM PDT 24 Aug 19 04:28:09 PM PDT 24 419072466 ps
T211 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2397472012 Aug 19 04:27:37 PM PDT 24 Aug 19 04:27:38 PM PDT 24 18396371 ps
T143 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1448999629 Aug 19 04:27:14 PM PDT 24 Aug 19 04:27:19 PM PDT 24 270973435 ps
T212 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3071781284 Aug 19 04:27:39 PM PDT 24 Aug 19 04:27:41 PM PDT 24 16999425 ps
T213 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4239771698 Aug 19 04:27:12 PM PDT 24 Aug 19 04:27:18 PM PDT 24 16126253 ps
T879 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1791109792 Aug 19 04:27:58 PM PDT 24 Aug 19 04:28:00 PM PDT 24 16349483 ps
T195 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4016865240 Aug 19 04:27:12 PM PDT 24 Aug 19 04:27:13 PM PDT 24 34368505 ps
T122 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1735803877 Aug 19 04:27:47 PM PDT 24 Aug 19 04:27:51 PM PDT 24 1097859298 ps
T159 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4268204511 Aug 19 04:27:26 PM PDT 24 Aug 19 04:27:27 PM PDT 24 42210882 ps
T160 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3940458332 Aug 19 04:27:23 PM PDT 24 Aug 19 04:27:24 PM PDT 24 235514556 ps
T196 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.405200186 Aug 19 04:27:28 PM PDT 24 Aug 19 04:27:29 PM PDT 24 15343119 ps
T197 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4246745236 Aug 19 04:27:49 PM PDT 24 Aug 19 04:27:50 PM PDT 24 17349456 ps
T880 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.260638547 Aug 19 04:27:14 PM PDT 24 Aug 19 04:27:18 PM PDT 24 177932516 ps
T881 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3674292279 Aug 19 04:27:14 PM PDT 24 Aug 19 04:27:17 PM PDT 24 307329134 ps
T198 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2616300463 Aug 19 04:27:14 PM PDT 24 Aug 19 04:27:15 PM PDT 24 34006485 ps
T882 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3778601060 Aug 19 04:27:23 PM PDT 24 Aug 19 04:27:24 PM PDT 24 43637524 ps
T137 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.590357403 Aug 19 04:27:52 PM PDT 24 Aug 19 04:27:54 PM PDT 24 210427598 ps
T883 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.216669709 Aug 19 04:28:08 PM PDT 24 Aug 19 04:28:09 PM PDT 24 14015846 ps
T884 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1908457850 Aug 19 04:27:08 PM PDT 24 Aug 19 04:27:10 PM PDT 24 194526503 ps
T885 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2332989946 Aug 19 04:27:58 PM PDT 24 Aug 19 04:28:09 PM PDT 24 919329667 ps
T886 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2370049527 Aug 19 04:27:05 PM PDT 24 Aug 19 04:27:07 PM PDT 24 50388747 ps
T199 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3922116416 Aug 19 04:27:21 PM PDT 24 Aug 19 04:27:22 PM PDT 24 53926709 ps
T887 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2026950349 Aug 19 04:27:17 PM PDT 24 Aug 19 04:27:19 PM PDT 24 57166770 ps
T200 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3481401245 Aug 19 04:27:16 PM PDT 24 Aug 19 04:27:17 PM PDT 24 104775074 ps
T888 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2807578021 Aug 19 04:27:13 PM PDT 24 Aug 19 04:27:15 PM PDT 24 39707146 ps
T201 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.128697337 Aug 19 04:27:29 PM PDT 24 Aug 19 04:27:30 PM PDT 24 22939120 ps
T222 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1224796037 Aug 19 04:27:12 PM PDT 24 Aug 19 04:27:15 PM PDT 24 251778849 ps
T889 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1382695368 Aug 19 04:27:38 PM PDT 24 Aug 19 04:27:39 PM PDT 24 83749542 ps
T890 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.202566585 Aug 19 04:27:53 PM PDT 24 Aug 19 04:27:54 PM PDT 24 82285115 ps
T891 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.4002365332 Aug 19 04:27:07 PM PDT 24 Aug 19 04:27:09 PM PDT 24 19486527 ps
T892 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1354991596 Aug 19 04:27:26 PM PDT 24 Aug 19 04:27:28 PM PDT 24 75628713 ps
T893 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3035933428 Aug 19 04:27:16 PM PDT 24 Aug 19 04:27:18 PM PDT 24 59509070 ps
T894 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.603717474 Aug 19 04:27:25 PM PDT 24 Aug 19 04:27:26 PM PDT 24 61551404 ps
T895 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1175339145 Aug 19 04:27:46 PM PDT 24 Aug 19 04:27:48 PM PDT 24 25764150 ps
T129 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.4187800257 Aug 19 04:27:06 PM PDT 24 Aug 19 04:27:08 PM PDT 24 56922932 ps
T896 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.969819932 Aug 19 04:27:22 PM PDT 24 Aug 19 04:27:23 PM PDT 24 84468459 ps
T897 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4105938411 Aug 19 04:27:47 PM PDT 24 Aug 19 04:27:50 PM PDT 24 162513303 ps
T898 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2943452223 Aug 19 04:27:53 PM PDT 24 Aug 19 04:28:04 PM PDT 24 422076339 ps
T899 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.52030525 Aug 19 04:27:39 PM PDT 24 Aug 19 04:27:40 PM PDT 24 28955008 ps
T900 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.721453721 Aug 19 04:27:11 PM PDT 24 Aug 19 04:27:13 PM PDT 24 48382559 ps
T901 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2204269782 Aug 19 04:27:22 PM PDT 24 Aug 19 04:27:24 PM PDT 24 343963186 ps
T902 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3098281294 Aug 19 04:27:12 PM PDT 24 Aug 19 04:27:14 PM PDT 24 49713835 ps
T903 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2473101894 Aug 19 04:27:14 PM PDT 24 Aug 19 04:27:15 PM PDT 24 50461800 ps
T128 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3052870523 Aug 19 04:27:12 PM PDT 24 Aug 19 04:27:15 PM PDT 24 267247421 ps
T904 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4270592280 Aug 19 04:27:08 PM PDT 24 Aug 19 04:27:28 PM PDT 24 3334527617 ps
T905 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2537080728 Aug 19 04:27:36 PM PDT 24 Aug 19 04:27:37 PM PDT 24 888244778 ps
T906 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.417293315 Aug 19 04:27:31 PM PDT 24 Aug 19 04:27:36 PM PDT 24 1690464605 ps
T907 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3057772564 Aug 19 04:27:43 PM PDT 24 Aug 19 04:27:45 PM PDT 24 77077464 ps
T908 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2503092570 Aug 19 04:27:24 PM PDT 24 Aug 19 04:27:26 PM PDT 24 97858206 ps
T144 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2135967242 Aug 19 04:27:38 PM PDT 24 Aug 19 04:27:39 PM PDT 24 79749322 ps
T909 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3157866453 Aug 19 04:27:40 PM PDT 24 Aug 19 04:27:41 PM PDT 24 31596714 ps
T910 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2167887412 Aug 19 04:27:43 PM PDT 24 Aug 19 04:27:45 PM PDT 24 96915998 ps
T911 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2597477182 Aug 19 04:27:15 PM PDT 24 Aug 19 04:27:34 PM PDT 24 4288319206 ps
T145 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.686812589 Aug 19 04:27:15 PM PDT 24 Aug 19 04:27:17 PM PDT 24 55104194 ps
T912 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3141130699 Aug 19 04:27:45 PM PDT 24 Aug 19 04:27:46 PM PDT 24 216571128 ps
T913 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.345527264 Aug 19 04:27:35 PM PDT 24 Aug 19 04:27:56 PM PDT 24 3058605242 ps
T202 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3128486391 Aug 19 04:27:51 PM PDT 24 Aug 19 04:27:52 PM PDT 24 19641226 ps
T914 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1772192617 Aug 19 04:27:18 PM PDT 24 Aug 19 04:27:19 PM PDT 24 132773901 ps
T136 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3905756622 Aug 19 04:27:24 PM PDT 24 Aug 19 04:27:27 PM PDT 24 80509162 ps
T915 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2630388171 Aug 19 04:27:58 PM PDT 24 Aug 19 04:28:02 PM PDT 24 1175514215 ps
T916 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4080612471 Aug 19 04:27:11 PM PDT 24 Aug 19 04:27:13 PM PDT 24 21055765 ps
T917 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.77239068 Aug 19 04:27:37 PM PDT 24 Aug 19 04:27:39 PM PDT 24 33639495 ps
T918 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2279075712 Aug 19 04:27:06 PM PDT 24 Aug 19 04:27:07 PM PDT 24 14671877 ps
T919 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.849337425 Aug 19 04:27:21 PM PDT 24 Aug 19 04:27:22 PM PDT 24 1470046617 ps
T920 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2168483439 Aug 19 04:27:19 PM PDT 24 Aug 19 04:27:21 PM PDT 24 198869463 ps
T921 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2245857629 Aug 19 04:28:07 PM PDT 24 Aug 19 04:28:08 PM PDT 24 78397914 ps
T140 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3654177414 Aug 19 04:27:22 PM PDT 24 Aug 19 04:27:24 PM PDT 24 180856523 ps
T922 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.4136935664 Aug 19 04:27:43 PM PDT 24 Aug 19 04:27:46 PM PDT 24 171901580 ps
T923 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.192176886 Aug 19 04:27:24 PM PDT 24 Aug 19 04:27:25 PM PDT 24 145129254 ps
T924 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3299148159 Aug 19 04:27:15 PM PDT 24 Aug 19 04:27:18 PM PDT 24 97923298 ps
T925 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3899678304 Aug 19 04:27:18 PM PDT 24 Aug 19 04:27:19 PM PDT 24 325501557 ps
T926 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1261637759 Aug 19 04:27:13 PM PDT 24 Aug 19 04:27:15 PM PDT 24 54899267 ps
T927 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2053478728 Aug 19 04:27:09 PM PDT 24 Aug 19 04:27:13 PM PDT 24 1090174105 ps
T928 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1158962226 Aug 19 04:27:13 PM PDT 24 Aug 19 04:27:17 PM PDT 24 143419888 ps
T929 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2894361200 Aug 19 04:27:11 PM PDT 24 Aug 19 04:27:18 PM PDT 24 729804284 ps
T139 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2047366684 Aug 19 04:27:26 PM PDT 24 Aug 19 04:27:30 PM PDT 24 399118665 ps
T930 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1612289711 Aug 19 04:27:21 PM PDT 24 Aug 19 04:27:22 PM PDT 24 41555477 ps
T931 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1268267415 Aug 19 04:27:38 PM PDT 24 Aug 19 04:27:40 PM PDT 24 26324502 ps
T932 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.619898281 Aug 19 04:27:09 PM PDT 24 Aug 19 04:27:32 PM PDT 24 2182327556 ps
T933 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3647903139 Aug 19 04:27:21 PM PDT 24 Aug 19 04:27:22 PM PDT 24 89392723 ps
T934 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1380067635 Aug 19 04:27:12 PM PDT 24 Aug 19 04:27:21 PM PDT 24 160708884 ps
T935 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2851962942 Aug 19 04:27:47 PM PDT 24 Aug 19 04:27:50 PM PDT 24 584258450 ps
T936 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1282639278 Aug 19 04:27:06 PM PDT 24 Aug 19 04:27:08 PM PDT 24 20911379 ps
T141 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4268057631 Aug 19 04:27:22 PM PDT 24 Aug 19 04:27:24 PM PDT 24 53242025 ps
T937 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1945847468 Aug 19 04:27:11 PM PDT 24 Aug 19 04:27:12 PM PDT 24 102621622 ps
T938 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.954398837 Aug 19 04:27:11 PM PDT 24 Aug 19 04:27:21 PM PDT 24 843508859 ps
T939 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3213729475 Aug 19 04:27:15 PM PDT 24 Aug 19 04:27:18 PM PDT 24 240973454 ps
T940 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1503697643 Aug 19 04:27:15 PM PDT 24 Aug 19 04:27:21 PM PDT 24 1222394317 ps
T941 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1040360146 Aug 19 04:27:11 PM PDT 24 Aug 19 04:27:12 PM PDT 24 100776185 ps
T942 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3404210130 Aug 19 04:27:12 PM PDT 24 Aug 19 04:27:13 PM PDT 24 65638137 ps
T943 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1825171722 Aug 19 04:27:49 PM PDT 24 Aug 19 04:27:50 PM PDT 24 56850852 ps
T944 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4041537441 Aug 19 04:27:48 PM PDT 24 Aug 19 04:27:49 PM PDT 24 17170314 ps
T945 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3417881840 Aug 19 04:27:50 PM PDT 24 Aug 19 04:27:51 PM PDT 24 80274505 ps
T946 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1873688993 Aug 19 04:28:00 PM PDT 24 Aug 19 04:28:09 PM PDT 24 3939408128 ps
T947 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2205202278 Aug 19 04:27:16 PM PDT 24 Aug 19 04:27:18 PM PDT 24 105855685 ps
T948 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3711285866 Aug 19 04:27:13 PM PDT 24 Aug 19 04:27:14 PM PDT 24 27825286 ps
T131 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2760009350 Aug 19 04:27:56 PM PDT 24 Aug 19 04:27:58 PM PDT 24 76570019 ps
T949 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3596469944 Aug 19 04:27:19 PM PDT 24 Aug 19 04:27:20 PM PDT 24 18248646 ps
T950 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4182934484 Aug 19 04:27:18 PM PDT 24 Aug 19 04:27:20 PM PDT 24 361940222 ps
T951 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3525190341 Aug 19 04:27:06 PM PDT 24 Aug 19 04:27:09 PM PDT 24 38962493 ps
T952 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1116272502 Aug 19 04:27:11 PM PDT 24 Aug 19 04:27:15 PM PDT 24 110730183 ps
T953 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1006725260 Aug 19 04:27:21 PM PDT 24 Aug 19 04:27:22 PM PDT 24 92567534 ps
T954 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2609749393 Aug 19 04:27:15 PM PDT 24 Aug 19 04:27:17 PM PDT 24 271929585 ps
T133 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2738713725 Aug 19 04:27:37 PM PDT 24 Aug 19 04:27:42 PM PDT 24 1648967717 ps
T955 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1364404424 Aug 19 04:27:22 PM PDT 24 Aug 19 04:27:23 PM PDT 24 132849381 ps
T956 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4032349196 Aug 19 04:27:11 PM PDT 24 Aug 19 04:27:18 PM PDT 24 51228663 ps
T957 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4177300532 Aug 19 04:27:12 PM PDT 24 Aug 19 04:27:18 PM PDT 24 440657747 ps
T958 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1617286354 Aug 19 04:27:31 PM PDT 24 Aug 19 04:27:33 PM PDT 24 27187658 ps
T959 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3434225424 Aug 19 04:28:02 PM PDT 24 Aug 19 04:28:03 PM PDT 24 16050755 ps
T960 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.995923635 Aug 19 04:27:07 PM PDT 24 Aug 19 04:27:24 PM PDT 24 3277854786 ps
T961 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.116202121 Aug 19 04:26:59 PM PDT 24 Aug 19 04:27:02 PM PDT 24 317752099 ps
T962 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1970932731 Aug 19 04:27:11 PM PDT 24 Aug 19 04:27:22 PM PDT 24 440362356 ps
T963 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2232655545 Aug 19 04:27:07 PM PDT 24 Aug 19 04:27:08 PM PDT 24 100679876 ps
T223 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1400090238 Aug 19 04:27:15 PM PDT 24 Aug 19 04:27:17 PM PDT 24 140283807 ps
T964 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3197159270 Aug 19 04:27:13 PM PDT 24 Aug 19 04:27:20 PM PDT 24 159622242 ps
T203 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.47204392 Aug 19 04:27:14 PM PDT 24 Aug 19 04:27:15 PM PDT 24 29382740 ps
T965 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.978741446 Aug 19 04:27:35 PM PDT 24 Aug 19 04:27:36 PM PDT 24 21834363 ps
T204 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1087952910 Aug 19 04:27:10 PM PDT 24 Aug 19 04:27:11 PM PDT 24 51900874 ps
T966 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1526769522 Aug 19 04:27:22 PM PDT 24 Aug 19 04:27:34 PM PDT 24 1831150410 ps
T967 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1988592866 Aug 19 04:27:02 PM PDT 24 Aug 19 04:27:09 PM PDT 24 2188774471 ps
T968 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1417403256 Aug 19 04:27:19 PM PDT 24 Aug 19 04:27:21 PM PDT 24 72646657 ps
T969 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3785498973 Aug 19 04:27:15 PM PDT 24 Aug 19 04:27:16 PM PDT 24 362539127 ps
T970 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.41996548 Aug 19 04:27:27 PM PDT 24 Aug 19 04:27:29 PM PDT 24 37060024 ps
T205 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1798995353 Aug 19 04:27:22 PM PDT 24 Aug 19 04:27:23 PM PDT 24 38648342 ps
T971 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3010909900 Aug 19 04:28:42 PM PDT 24 Aug 19 04:28:43 PM PDT 24 15978501 ps
T972 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1589973207 Aug 19 04:27:03 PM PDT 24 Aug 19 04:27:05 PM PDT 24 92238386 ps
T138 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3782260837 Aug 19 04:28:01 PM PDT 24 Aug 19 04:28:04 PM PDT 24 82492596 ps
T973 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4234817764 Aug 19 04:27:14 PM PDT 24 Aug 19 04:27:23 PM PDT 24 1684362620 ps
T974 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1532933429 Aug 19 04:27:07 PM PDT 24 Aug 19 04:27:09 PM PDT 24 50732181 ps
T206 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1242441894 Aug 19 04:27:15 PM PDT 24 Aug 19 04:27:16 PM PDT 24 134189963 ps
T975 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3242162556 Aug 19 04:27:44 PM PDT 24 Aug 19 04:27:46 PM PDT 24 279404240 ps
T976 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3550183635 Aug 19 04:27:14 PM PDT 24 Aug 19 04:27:20 PM PDT 24 791369516 ps
T977 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.845367104 Aug 19 04:27:11 PM PDT 24 Aug 19 04:27:13 PM PDT 24 107948956 ps
T135 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1967873982 Aug 19 04:27:24 PM PDT 24 Aug 19 04:27:27 PM PDT 24 465658316 ps
T978 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.105273382 Aug 19 04:27:17 PM PDT 24 Aug 19 04:27:23 PM PDT 24 194204080 ps
T979 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4236633150 Aug 19 04:27:01 PM PDT 24 Aug 19 04:27:10 PM PDT 24 1108928968 ps
T207 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2285239613 Aug 19 04:27:16 PM PDT 24 Aug 19 04:27:17 PM PDT 24 13125572 ps
T980 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3462839711 Aug 19 04:27:12 PM PDT 24 Aug 19 04:27:13 PM PDT 24 103946745 ps
T981 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1424339052 Aug 19 04:27:15 PM PDT 24 Aug 19 04:27:16 PM PDT 24 104974436 ps
T982 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.585283438 Aug 19 04:27:57 PM PDT 24 Aug 19 04:27:59 PM PDT 24 54947793 ps
T983 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2465709460 Aug 19 04:27:14 PM PDT 24 Aug 19 04:27:16 PM PDT 24 32831893 ps
T984 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3387997475 Aug 19 04:27:13 PM PDT 24 Aug 19 04:27:14 PM PDT 24 38178105 ps
T985 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1692228690 Aug 19 04:27:22 PM PDT 24 Aug 19 04:27:23 PM PDT 24 18765268 ps
T134 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2596188313 Aug 19 04:27:37 PM PDT 24 Aug 19 04:27:39 PM PDT 24 90113706 ps
T986 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3061129718 Aug 19 04:27:11 PM PDT 24 Aug 19 04:27:15 PM PDT 24 235288108 ps
T987 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1901939996 Aug 19 04:27:53 PM PDT 24 Aug 19 04:27:54 PM PDT 24 30363728 ps
T988 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.4153099523 Aug 19 04:27:22 PM PDT 24 Aug 19 04:27:25 PM PDT 24 413937132 ps
T989 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2775914986 Aug 19 04:27:07 PM PDT 24 Aug 19 04:27:08 PM PDT 24 319174029 ps
T990 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3968560339 Aug 19 04:27:02 PM PDT 24 Aug 19 04:27:04 PM PDT 24 138807697 ps
T991 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.102769820 Aug 19 04:27:14 PM PDT 24 Aug 19 04:27:15 PM PDT 24 74952179 ps
T992 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.257627024 Aug 19 04:27:11 PM PDT 24 Aug 19 04:27:12 PM PDT 24 14065642 ps
T132 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2109403406 Aug 19 04:27:20 PM PDT 24 Aug 19 04:27:28 PM PDT 24 68498225 ps
T993 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2040572040 Aug 19 04:27:38 PM PDT 24 Aug 19 04:27:57 PM PDT 24 3252129898 ps
T994 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2579700736 Aug 19 04:27:21 PM PDT 24 Aug 19 04:27:22 PM PDT 24 556660045 ps
T995 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1378763638 Aug 19 04:27:14 PM PDT 24 Aug 19 04:27:18 PM PDT 24 115280301 ps
T996 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1962497054 Aug 19 04:27:50 PM PDT 24 Aug 19 04:27:58 PM PDT 24 340801911 ps
T997 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.511129294 Aug 19 04:27:18 PM PDT 24 Aug 19 04:27:20 PM PDT 24 20441265 ps

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2149852308
Short name T10
Test name
Test status
Simulation time 255459966 ps
CPU time 12.12 seconds
Started Aug 19 04:41:14 PM PDT 24
Finished Aug 19 04:41:27 PM PDT 24
Peak memory 218592 kb
Host smart-fb14c05c-9a99-4138-9471-89120f1b2dbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149852308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2149852308
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1620465735
Short name T18
Test name
Test status
Simulation time 16239950565 ps
CPU time 150.91 seconds
Started Aug 19 04:39:25 PM PDT 24
Finished Aug 19 04:41:56 PM PDT 24
Peak memory 281748 kb
Host smart-3bf91649-0430-4aea-9a57-e6d0ac789e64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620465735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1620465735
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2230231798
Short name T45
Test name
Test status
Simulation time 419712909 ps
CPU time 9.56 seconds
Started Aug 19 04:40:59 PM PDT 24
Finished Aug 19 04:41:09 PM PDT 24
Peak memory 218372 kb
Host smart-d815f62d-d0b1-4e6e-91c9-971b454d46f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230231798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2230231798
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2137411160
Short name T148
Test name
Test status
Simulation time 2672290408 ps
CPU time 103.51 seconds
Started Aug 19 04:40:17 PM PDT 24
Finished Aug 19 04:42:01 PM PDT 24
Peak memory 267556 kb
Host smart-d6bf0877-27df-4b84-b963-a340be532346
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2137411160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2137411160
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2326471956
Short name T225
Test name
Test status
Simulation time 488908858 ps
CPU time 7.84 seconds
Started Aug 19 04:40:20 PM PDT 24
Finished Aug 19 04:40:28 PM PDT 24
Peak memory 218380 kb
Host smart-7f677d4a-8548-4195-9b3f-cfaed5a18b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326471956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2326471956
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.518248481
Short name T38
Test name
Test status
Simulation time 34326618 ps
CPU time 0.78 seconds
Started Aug 19 04:40:00 PM PDT 24
Finished Aug 19 04:40:01 PM PDT 24
Peak memory 209200 kb
Host smart-4bd17236-475a-4844-9b9e-08b2511ddb63
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518248481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.518248481
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1942298483
Short name T65
Test name
Test status
Simulation time 2002612310 ps
CPU time 10.69 seconds
Started Aug 19 04:40:27 PM PDT 24
Finished Aug 19 04:40:37 PM PDT 24
Peak memory 226092 kb
Host smart-e2e9a960-5e45-4b3a-9d3b-a39d8d913cdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942298483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1942298483
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2760439599
Short name T62
Test name
Test status
Simulation time 129200461 ps
CPU time 24.87 seconds
Started Aug 19 04:38:45 PM PDT 24
Finished Aug 19 04:39:10 PM PDT 24
Peak memory 282272 kb
Host smart-da6761b0-a628-43d4-9e33-b5914fcc1f7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760439599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2760439599
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.233573845
Short name T17
Test name
Test status
Simulation time 1605353437 ps
CPU time 50.24 seconds
Started Aug 19 04:41:53 PM PDT 24
Finished Aug 19 04:42:43 PM PDT 24
Peak memory 226268 kb
Host smart-1a6c833b-a401-44eb-b1e5-8e2926e797e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=233573845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.233573845
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4151996247
Short name T115
Test name
Test status
Simulation time 686430652 ps
CPU time 5.8 seconds
Started Aug 19 04:27:30 PM PDT 24
Finished Aug 19 04:27:36 PM PDT 24
Peak memory 218224 kb
Host smart-448e503c-536d-4ef1-97fe-4c8f5f8f8e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151996247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.4151996247
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2865352976
Short name T170
Test name
Test status
Simulation time 15724813236 ps
CPU time 405.64 seconds
Started Aug 19 04:40:25 PM PDT 24
Finished Aug 19 04:47:11 PM PDT 24
Peak memory 283796 kb
Host smart-6d1c2b22-699f-4699-9d6d-1995c378ceaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865352976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2865352976
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.588016385
Short name T120
Test name
Test status
Simulation time 43229101 ps
CPU time 2.22 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:17 PM PDT 24
Peak memory 222796 kb
Host smart-356f0267-8ee4-41af-af36-80e5eab0f96f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588016385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.588016385
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.600886553
Short name T13
Test name
Test status
Simulation time 88475215 ps
CPU time 0.86 seconds
Started Aug 19 04:38:58 PM PDT 24
Finished Aug 19 04:38:59 PM PDT 24
Peak memory 209024 kb
Host smart-d0fc0f6b-45b4-431f-880a-2ab53bec4c8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600886553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.600886553
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3668323503
Short name T169
Test name
Test status
Simulation time 321539995 ps
CPU time 9.54 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:41:05 PM PDT 24
Peak memory 218356 kb
Host smart-67d68405-cce2-4e15-953a-7291f4b18dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668323503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3668323503
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3287785692
Short name T24
Test name
Test status
Simulation time 2543646744 ps
CPU time 12.93 seconds
Started Aug 19 04:39:33 PM PDT 24
Finished Aug 19 04:39:46 PM PDT 24
Peak memory 217824 kb
Host smart-74a19b51-30e6-4def-b06d-e4dbacda97ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287785692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3287785692
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.405200186
Short name T196
Test name
Test status
Simulation time 15343119 ps
CPU time 1.02 seconds
Started Aug 19 04:27:28 PM PDT 24
Finished Aug 19 04:27:29 PM PDT 24
Peak memory 210104 kb
Host smart-0d4b9d32-38bd-455b-b128-62a23f451bc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405200186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.405200186
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2579777832
Short name T217
Test name
Test status
Simulation time 151043616 ps
CPU time 1.59 seconds
Started Aug 19 04:27:25 PM PDT 24
Finished Aug 19 04:27:27 PM PDT 24
Peak memory 219492 kb
Host smart-b5595a76-53b6-4f61-a625-f95a0ad708b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257977
7832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2579777832
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3353464153
Short name T19
Test name
Test status
Simulation time 10690898908 ps
CPU time 216.4 seconds
Started Aug 19 04:40:11 PM PDT 24
Finished Aug 19 04:43:47 PM PDT 24
Peak memory 251032 kb
Host smart-428fe148-c470-451d-83fb-3eaaa85bb6a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353464153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3353464153
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1730306567
Short name T15
Test name
Test status
Simulation time 76832772 ps
CPU time 6.69 seconds
Started Aug 19 04:41:00 PM PDT 24
Finished Aug 19 04:41:06 PM PDT 24
Peak memory 247144 kb
Host smart-5831de3b-728a-4824-8374-20bc767bbcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730306567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1730306567
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.4187800257
Short name T129
Test name
Test status
Simulation time 56922932 ps
CPU time 1.96 seconds
Started Aug 19 04:27:06 PM PDT 24
Finished Aug 19 04:27:08 PM PDT 24
Peak memory 222844 kb
Host smart-60e783eb-edff-4bd7-9fa5-8fd6d707304f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187800257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.4187800257
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.484199074
Short name T55
Test name
Test status
Simulation time 292122361 ps
CPU time 25.62 seconds
Started Aug 19 04:40:14 PM PDT 24
Finished Aug 19 04:40:40 PM PDT 24
Peak memory 250920 kb
Host smart-2a183353-d880-4990-aec2-393d7d99c583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484199074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.484199074
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2760009350
Short name T131
Test name
Test status
Simulation time 76570019 ps
CPU time 2.48 seconds
Started Aug 19 04:27:56 PM PDT 24
Finished Aug 19 04:27:58 PM PDT 24
Peak memory 222952 kb
Host smart-1e7b49a1-27d1-41c4-aa57-bec6d47e2ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760009350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2760009350
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3905756622
Short name T136
Test name
Test status
Simulation time 80509162 ps
CPU time 2.69 seconds
Started Aug 19 04:27:24 PM PDT 24
Finished Aug 19 04:27:27 PM PDT 24
Peak memory 223068 kb
Host smart-c889b88d-e3f6-4eda-a4af-8f18c6f4756b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905756622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3905756622
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.957851443
Short name T113
Test name
Test status
Simulation time 9885627309 ps
CPU time 70.95 seconds
Started Aug 19 04:40:19 PM PDT 24
Finished Aug 19 04:41:30 PM PDT 24
Peak memory 248848 kb
Host smart-4f3ae576-adfd-442e-be55-8b09e70f025d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957851443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.957851443
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.337763429
Short name T16
Test name
Test status
Simulation time 693807095 ps
CPU time 2.88 seconds
Started Aug 19 04:41:07 PM PDT 24
Finished Aug 19 04:41:10 PM PDT 24
Peak memory 218344 kb
Host smart-2efa1208-d6b6-4965-b86f-5276f8a5b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337763429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.337763429
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3052870523
Short name T128
Test name
Test status
Simulation time 267247421 ps
CPU time 2.99 seconds
Started Aug 19 04:27:12 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 222920 kb
Host smart-1948d238-22f8-4c52-a104-1e09bea74dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052870523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3052870523
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1967873982
Short name T135
Test name
Test status
Simulation time 465658316 ps
CPU time 2.88 seconds
Started Aug 19 04:27:24 PM PDT 24
Finished Aug 19 04:27:27 PM PDT 24
Peak memory 222864 kb
Host smart-5a27be4e-2ec3-46ac-bb88-d2dc4f749c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967873982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1967873982
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4268204511
Short name T159
Test name
Test status
Simulation time 42210882 ps
CPU time 1.23 seconds
Started Aug 19 04:27:26 PM PDT 24
Finished Aug 19 04:27:27 PM PDT 24
Peak memory 218296 kb
Host smart-1cdbe5f3-c702-473e-b1c0-f81096595bd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268204511 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.4268204511
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2861988475
Short name T12
Test name
Test status
Simulation time 13607296 ps
CPU time 0.8 seconds
Started Aug 19 04:39:15 PM PDT 24
Finished Aug 19 04:39:15 PM PDT 24
Peak memory 208684 kb
Host smart-33fc72fe-d8db-4dff-b35b-bb4a6eb93829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861988475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2861988475
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1505709287
Short name T121
Test name
Test status
Simulation time 74160919 ps
CPU time 3.31 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 223272 kb
Host smart-0325a4f4-7f85-4a54-bf17-e756dac385d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505709287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1505709287
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2714759692
Short name T220
Test name
Test status
Simulation time 11455281 ps
CPU time 0.8 seconds
Started Aug 19 04:38:58 PM PDT 24
Finished Aug 19 04:38:59 PM PDT 24
Peak memory 209020 kb
Host smart-7ea85c49-5203-4d1e-ba2b-b069f3b1d4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714759692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2714759692
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2134857726
Short name T164
Test name
Test status
Simulation time 12724549 ps
CPU time 0.81 seconds
Started Aug 19 04:38:58 PM PDT 24
Finished Aug 19 04:38:59 PM PDT 24
Peak memory 208624 kb
Host smart-6574afe9-0a35-4b6a-be39-09b6143a5e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134857726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2134857726
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1503697643
Short name T940
Test name
Test status
Simulation time 1222394317 ps
CPU time 5.79 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:21 PM PDT 24
Peak memory 220108 kb
Host smart-dd44f9ec-67e7-40d9-af06-9441937fcb27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150369
7643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1503697643
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3654177414
Short name T140
Test name
Test status
Simulation time 180856523 ps
CPU time 1.85 seconds
Started Aug 19 04:27:22 PM PDT 24
Finished Aug 19 04:27:24 PM PDT 24
Peak memory 222344 kb
Host smart-dd653ecf-9351-47f9-94c6-a35177747813
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654177414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3654177414
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1735803877
Short name T122
Test name
Test status
Simulation time 1097859298 ps
CPU time 3.82 seconds
Started Aug 19 04:27:47 PM PDT 24
Finished Aug 19 04:27:51 PM PDT 24
Peak memory 218260 kb
Host smart-be008943-0a09-4593-be0a-5b1d883a88ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735803877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1735803877
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3782260837
Short name T138
Test name
Test status
Simulation time 82492596 ps
CPU time 3.25 seconds
Started Aug 19 04:28:01 PM PDT 24
Finished Aug 19 04:28:04 PM PDT 24
Peak memory 218224 kb
Host smart-1c0f7cf8-d5c8-4732-a37e-3d924945f42e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782260837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3782260837
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2738713725
Short name T133
Test name
Test status
Simulation time 1648967717 ps
CPU time 4.32 seconds
Started Aug 19 04:27:37 PM PDT 24
Finished Aug 19 04:27:42 PM PDT 24
Peak memory 218384 kb
Host smart-22b5d28f-ca93-4e69-8af3-39a05926cbd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738713725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2738713725
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1426403616
Short name T11
Test name
Test status
Simulation time 275244025 ps
CPU time 27.67 seconds
Started Aug 19 04:39:34 PM PDT 24
Finished Aug 19 04:40:02 PM PDT 24
Peak memory 251004 kb
Host smart-95ebf787-2b93-4da2-a3c3-2c717a740cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426403616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1426403616
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.216606300
Short name T154
Test name
Test status
Simulation time 1596673234 ps
CPU time 13.02 seconds
Started Aug 19 04:40:07 PM PDT 24
Finished Aug 19 04:40:20 PM PDT 24
Peak memory 226076 kb
Host smart-22ba3ed9-27e7-4dc3-a565-d8d3976d29c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216606300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.216606300
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1424339052
Short name T981
Test name
Test status
Simulation time 104974436 ps
CPU time 1.14 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:16 PM PDT 24
Peak memory 210156 kb
Host smart-ecced389-002b-44f7-b5ba-a616bf41e29d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424339052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1424339052
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.116202121
Short name T961
Test name
Test status
Simulation time 317752099 ps
CPU time 2.1 seconds
Started Aug 19 04:26:59 PM PDT 24
Finished Aug 19 04:27:02 PM PDT 24
Peak memory 208752 kb
Host smart-935bde48-bcb6-446c-b325-10ba784bdb80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116202121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.116202121
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3596469944
Short name T949
Test name
Test status
Simulation time 18248646 ps
CPU time 0.98 seconds
Started Aug 19 04:27:19 PM PDT 24
Finished Aug 19 04:27:20 PM PDT 24
Peak memory 212172 kb
Host smart-d1f91ba5-8649-4ed4-8c6d-e68228b9bebb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596469944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3596469944
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1908457850
Short name T884
Test name
Test status
Simulation time 194526503 ps
CPU time 1.65 seconds
Started Aug 19 04:27:08 PM PDT 24
Finished Aug 19 04:27:10 PM PDT 24
Peak memory 219404 kb
Host smart-8afd34ff-67b1-408b-b284-0aab2a740ac2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908457850 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1908457850
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.257627024
Short name T992
Test name
Test status
Simulation time 14065642 ps
CPU time 0.91 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:12 PM PDT 24
Peak memory 210056 kb
Host smart-c4256025-0835-414c-9783-5961b707ba77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257627024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.257627024
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2232655545
Short name T963
Test name
Test status
Simulation time 100679876 ps
CPU time 1.18 seconds
Started Aug 19 04:27:07 PM PDT 24
Finished Aug 19 04:27:08 PM PDT 24
Peak memory 208728 kb
Host smart-ad42954a-7c6d-4050-9066-db9ea18977b0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232655545 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2232655545
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2894361200
Short name T929
Test name
Test status
Simulation time 729804284 ps
CPU time 6.7 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 209360 kb
Host smart-b4ccc925-a372-433d-9a80-041db4f31089
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894361200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2894361200
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2597477182
Short name T911
Test name
Test status
Simulation time 4288319206 ps
CPU time 18.95 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:34 PM PDT 24
Peak memory 210068 kb
Host smart-93a4a5b9-00cf-4505-bf16-4d66466de9fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597477182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2597477182
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1589973207
Short name T972
Test name
Test status
Simulation time 92238386 ps
CPU time 1.86 seconds
Started Aug 19 04:27:03 PM PDT 24
Finished Aug 19 04:27:05 PM PDT 24
Peak memory 211656 kb
Host smart-c4707020-f81e-4b2a-b154-c98f03932f02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589973207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1589973207
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1380067635
Short name T934
Test name
Test status
Simulation time 160708884 ps
CPU time 3.86 seconds
Started Aug 19 04:27:12 PM PDT 24
Finished Aug 19 04:27:21 PM PDT 24
Peak memory 209960 kb
Host smart-f4dd066f-e433-4d83-acfd-c5943cf264d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380067635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1380067635
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1417403256
Short name T968
Test name
Test status
Simulation time 72646657 ps
CPU time 1.21 seconds
Started Aug 19 04:27:19 PM PDT 24
Finished Aug 19 04:27:21 PM PDT 24
Peak memory 210028 kb
Host smart-007c526f-e941-499f-a93d-e5263b7e717d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417403256 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1417403256
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1382695368
Short name T889
Test name
Test status
Simulation time 83749542 ps
CPU time 1 seconds
Started Aug 19 04:27:38 PM PDT 24
Finished Aug 19 04:27:39 PM PDT 24
Peak memory 210208 kb
Host smart-090ef232-9415-4a0c-8825-bcc424d724a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382695368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1382695368
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3197159270
Short name T964
Test name
Test status
Simulation time 159622242 ps
CPU time 6.06 seconds
Started Aug 19 04:27:13 PM PDT 24
Finished Aug 19 04:27:20 PM PDT 24
Peak memory 218216 kb
Host smart-b891ccb0-1eea-4887-bde5-c41fe788a7ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197159270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3197159270
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1242441894
Short name T206
Test name
Test status
Simulation time 134189963 ps
CPU time 1.22 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:16 PM PDT 24
Peak memory 210052 kb
Host smart-59a3b6ad-dc54-48e3-a066-83819950064b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242441894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1242441894
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.4002365332
Short name T891
Test name
Test status
Simulation time 19486527 ps
CPU time 1.16 seconds
Started Aug 19 04:27:07 PM PDT 24
Finished Aug 19 04:27:09 PM PDT 24
Peak memory 209000 kb
Host smart-45c76b51-0cc5-4f5f-9253-01cac5af9b13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002365332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.4002365332
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3462839711
Short name T980
Test name
Test status
Simulation time 103946745 ps
CPU time 0.95 seconds
Started Aug 19 04:27:12 PM PDT 24
Finished Aug 19 04:27:13 PM PDT 24
Peak memory 211376 kb
Host smart-07aa2d02-1267-41e1-80a2-10eabfaa16fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462839711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3462839711
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2622134785
Short name T118
Test name
Test status
Simulation time 27322807 ps
CPU time 1.6 seconds
Started Aug 19 04:27:13 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 219292 kb
Host smart-8f572e03-61ad-4e31-8ff7-94a761d6a677
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622134785 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2622134785
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3481401245
Short name T200
Test name
Test status
Simulation time 104775074 ps
CPU time 1.08 seconds
Started Aug 19 04:27:16 PM PDT 24
Finished Aug 19 04:27:17 PM PDT 24
Peak memory 210108 kb
Host smart-52b74608-a587-49fa-b23a-a3d31c9fa60e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481401245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3481401245
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2026950349
Short name T887
Test name
Test status
Simulation time 57166770 ps
CPU time 1.76 seconds
Started Aug 19 04:27:17 PM PDT 24
Finished Aug 19 04:27:19 PM PDT 24
Peak memory 210092 kb
Host smart-ed603469-2b47-4789-b18a-761da75b97bd
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026950349 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2026950349
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4234817764
Short name T973
Test name
Test status
Simulation time 1684362620 ps
CPU time 9.16 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:23 PM PDT 24
Peak memory 209948 kb
Host smart-f7f8075a-a860-400e-82ec-5d55f1c5b8cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234817764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.4234817764
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.995923635
Short name T960
Test name
Test status
Simulation time 3277854786 ps
CPU time 17.31 seconds
Started Aug 19 04:27:07 PM PDT 24
Finished Aug 19 04:27:24 PM PDT 24
Peak memory 209372 kb
Host smart-4a1d7832-d1d6-435c-80bc-db1cdaf11dd5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995923635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.995923635
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3785498973
Short name T969
Test name
Test status
Simulation time 362539127 ps
CPU time 1.46 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:16 PM PDT 24
Peak memory 211484 kb
Host smart-92236d73-3f3e-48b6-b1ec-b8ae93fa7c10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785498973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3785498973
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1040360146
Short name T941
Test name
Test status
Simulation time 100776185 ps
CPU time 1.6 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:12 PM PDT 24
Peak memory 210036 kb
Host smart-89ce1a84-355c-42d6-860b-b5103df843ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040360146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1040360146
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1261637759
Short name T926
Test name
Test status
Simulation time 54899267 ps
CPU time 1.18 seconds
Started Aug 19 04:27:13 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 209376 kb
Host smart-1aece56d-e247-4b2d-8486-fb54a520ceab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261637759 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1261637759
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3638732009
Short name T210
Test name
Test status
Simulation time 154360399 ps
CPU time 1.15 seconds
Started Aug 19 04:27:04 PM PDT 24
Finished Aug 19 04:27:06 PM PDT 24
Peak memory 209680 kb
Host smart-74dab776-9174-4b40-98b4-8c3b11f18943
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638732009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3638732009
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.761132947
Short name T116
Test name
Test status
Simulation time 65434490 ps
CPU time 2.8 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 218224 kb
Host smart-af1f8c4f-e103-4bdd-b511-e7c7a2f7d296
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761132947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.761132947
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1400090238
Short name T223
Test name
Test status
Simulation time 140283807 ps
CPU time 2.66 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:17 PM PDT 24
Peak memory 223164 kb
Host smart-ed64eaa2-6026-46ad-9a66-c282778c9b74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400090238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1400090238
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.969819932
Short name T896
Test name
Test status
Simulation time 84468459 ps
CPU time 1.09 seconds
Started Aug 19 04:27:22 PM PDT 24
Finished Aug 19 04:27:23 PM PDT 24
Peak memory 218476 kb
Host smart-fc450386-b42b-41c8-92d8-bfdbaabfe0e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969819932 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.969819932
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.192176886
Short name T923
Test name
Test status
Simulation time 145129254 ps
CPU time 0.84 seconds
Started Aug 19 04:27:24 PM PDT 24
Finished Aug 19 04:27:25 PM PDT 24
Peak memory 210092 kb
Host smart-734ecf4d-ce9d-4f19-ad95-e1825ae84ef5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192176886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.192176886
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2579700736
Short name T994
Test name
Test status
Simulation time 556660045 ps
CPU time 1.47 seconds
Started Aug 19 04:27:21 PM PDT 24
Finished Aug 19 04:27:22 PM PDT 24
Peak memory 210096 kb
Host smart-b5c7ebbf-fc77-4c9a-b3d3-8fbb0e1fe8db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579700736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2579700736
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3299148159
Short name T924
Test name
Test status
Simulation time 97923298 ps
CPU time 2.59 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 220040 kb
Host smart-b69d741b-0af5-4fb3-9552-e1549fbf7e48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299148159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3299148159
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2047366684
Short name T139
Test name
Test status
Simulation time 399118665 ps
CPU time 3.97 seconds
Started Aug 19 04:27:26 PM PDT 24
Finished Aug 19 04:27:30 PM PDT 24
Peak memory 218364 kb
Host smart-5bdd403a-56af-4c5f-89f0-3b4c3965bb4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047366684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2047366684
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3711285866
Short name T948
Test name
Test status
Simulation time 27825286 ps
CPU time 0.94 seconds
Started Aug 19 04:27:13 PM PDT 24
Finished Aug 19 04:27:14 PM PDT 24
Peak memory 210020 kb
Host smart-03c71875-5baa-4fd5-82f7-4437d44664c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711285866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3711285866
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4203001176
Short name T125
Test name
Test status
Simulation time 51591122 ps
CPU time 1.52 seconds
Started Aug 19 04:27:58 PM PDT 24
Finished Aug 19 04:27:59 PM PDT 24
Peak memory 218248 kb
Host smart-245fcbe8-dcda-497a-b21f-225d292aeb23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203001176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.4203001176
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2178032957
Short name T117
Test name
Test status
Simulation time 87175966 ps
CPU time 3.57 seconds
Started Aug 19 04:27:41 PM PDT 24
Finished Aug 19 04:27:44 PM PDT 24
Peak memory 218308 kb
Host smart-6dbe8552-560a-4aaf-af61-36cfb1f63a67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178032957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2178032957
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1901939996
Short name T987
Test name
Test status
Simulation time 30363728 ps
CPU time 1.34 seconds
Started Aug 19 04:27:53 PM PDT 24
Finished Aug 19 04:27:54 PM PDT 24
Peak memory 218336 kb
Host smart-27d43525-6ddd-482c-bf42-89aaa8a24d51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901939996 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1901939996
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1798995353
Short name T205
Test name
Test status
Simulation time 38648342 ps
CPU time 1.02 seconds
Started Aug 19 04:27:22 PM PDT 24
Finished Aug 19 04:27:23 PM PDT 24
Peak memory 209864 kb
Host smart-3cf7498a-55e8-4e9c-9095-7e085aa590bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798995353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1798995353
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.202566585
Short name T890
Test name
Test status
Simulation time 82285115 ps
CPU time 1.27 seconds
Started Aug 19 04:27:53 PM PDT 24
Finished Aug 19 04:27:54 PM PDT 24
Peak memory 218264 kb
Host smart-2d423e7b-f13b-42c5-a637-c3483ed672b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202566585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.202566585
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.260638547
Short name T880
Test name
Test status
Simulation time 177932516 ps
CPU time 3.27 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 218236 kb
Host smart-3d182059-1ced-4db3-93e4-1bd7562be6b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260638547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.260638547
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3003260181
Short name T873
Test name
Test status
Simulation time 42134035 ps
CPU time 1.35 seconds
Started Aug 19 04:27:39 PM PDT 24
Finished Aug 19 04:27:41 PM PDT 24
Peak memory 218148 kb
Host smart-65a8d445-595c-411f-bc6f-15f63d4fe2b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003260181 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3003260181
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4246745236
Short name T197
Test name
Test status
Simulation time 17349456 ps
CPU time 0.92 seconds
Started Aug 19 04:27:49 PM PDT 24
Finished Aug 19 04:27:50 PM PDT 24
Peak memory 209992 kb
Host smart-3496ed50-30e5-4aff-a609-1b20d5c2fb2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246745236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.4246745236
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3071781284
Short name T212
Test name
Test status
Simulation time 16999425 ps
CPU time 1.2 seconds
Started Aug 19 04:27:39 PM PDT 24
Finished Aug 19 04:27:41 PM PDT 24
Peak memory 209988 kb
Host smart-5dfb8a9f-354b-48a0-8a0a-1c31fe556e51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071781284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3071781284
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.585283438
Short name T982
Test name
Test status
Simulation time 54947793 ps
CPU time 1.92 seconds
Started Aug 19 04:27:57 PM PDT 24
Finished Aug 19 04:27:59 PM PDT 24
Peak memory 219404 kb
Host smart-16611f75-8f7c-480c-a691-f54aca65e335
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585283438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.585283438
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2109403406
Short name T132
Test name
Test status
Simulation time 68498225 ps
CPU time 2.55 seconds
Started Aug 19 04:27:20 PM PDT 24
Finished Aug 19 04:27:28 PM PDT 24
Peak memory 223056 kb
Host smart-c0be7b80-c93a-4d3d-92dd-382ed1a65d95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109403406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2109403406
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.41996548
Short name T970
Test name
Test status
Simulation time 37060024 ps
CPU time 1.63 seconds
Started Aug 19 04:27:27 PM PDT 24
Finished Aug 19 04:27:29 PM PDT 24
Peak memory 223420 kb
Host smart-5827a5d7-3c19-4197-ba4b-1ba9c7b45c35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41996548 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.41996548
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4254588847
Short name T158
Test name
Test status
Simulation time 17398294 ps
CPU time 1.09 seconds
Started Aug 19 04:27:33 PM PDT 24
Finished Aug 19 04:27:34 PM PDT 24
Peak memory 210116 kb
Host smart-adbfc811-44af-4273-8490-9ca32b30c9a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254588847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.4254588847
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2465709460
Short name T983
Test name
Test status
Simulation time 32831893 ps
CPU time 1.01 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:16 PM PDT 24
Peak memory 210028 kb
Host smart-5ffc4959-34e5-45a0-bcc2-ebadd35057a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465709460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2465709460
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2053478728
Short name T927
Test name
Test status
Simulation time 1090174105 ps
CPU time 3.34 seconds
Started Aug 19 04:27:09 PM PDT 24
Finished Aug 19 04:27:13 PM PDT 24
Peak memory 218216 kb
Host smart-8bd7a8e9-a00c-44d1-8a2b-f882e1c50e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053478728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2053478728
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2168483439
Short name T920
Test name
Test status
Simulation time 198869463 ps
CPU time 2.14 seconds
Started Aug 19 04:27:19 PM PDT 24
Finished Aug 19 04:27:21 PM PDT 24
Peak memory 222472 kb
Host smart-44692254-ae39-45ef-8a30-82253d4f6c2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168483439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2168483439
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.102769820
Short name T991
Test name
Test status
Simulation time 74952179 ps
CPU time 1.09 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 220072 kb
Host smart-daf7829e-5367-4431-9342-a25fd52c3a1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102769820 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.102769820
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.128697337
Short name T201
Test name
Test status
Simulation time 22939120 ps
CPU time 1.01 seconds
Started Aug 19 04:27:29 PM PDT 24
Finished Aug 19 04:27:30 PM PDT 24
Peak memory 210056 kb
Host smart-3c34a76c-8e4c-4dc7-b98d-fe94627328a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128697337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.128697337
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2807578021
Short name T888
Test name
Test status
Simulation time 39707146 ps
CPU time 1.81 seconds
Started Aug 19 04:27:13 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 212048 kb
Host smart-330bb1a0-2875-44c5-a9a1-76d98fdddd93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807578021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2807578021
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3940458332
Short name T160
Test name
Test status
Simulation time 235514556 ps
CPU time 1.47 seconds
Started Aug 19 04:27:23 PM PDT 24
Finished Aug 19 04:27:24 PM PDT 24
Peak memory 218388 kb
Host smart-a1484cbf-0f2a-42ca-aa25-b71c9961eadc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940458332 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3940458332
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3778601060
Short name T882
Test name
Test status
Simulation time 43637524 ps
CPU time 0.87 seconds
Started Aug 19 04:27:23 PM PDT 24
Finished Aug 19 04:27:24 PM PDT 24
Peak memory 210040 kb
Host smart-0fa015ba-4590-4370-b3cb-607fb28b044b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778601060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3778601060
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2245857629
Short name T921
Test name
Test status
Simulation time 78397914 ps
CPU time 1.28 seconds
Started Aug 19 04:28:07 PM PDT 24
Finished Aug 19 04:28:08 PM PDT 24
Peak memory 210112 kb
Host smart-19955301-1830-477e-b89e-ef54cd32ded5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245857629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2245857629
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3809322819
Short name T876
Test name
Test status
Simulation time 669873712 ps
CPU time 5.73 seconds
Started Aug 19 04:27:23 PM PDT 24
Finished Aug 19 04:27:28 PM PDT 24
Peak memory 218248 kb
Host smart-3b97417b-5f99-4fb9-93ef-6047517961fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809322819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3809322819
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.978741446
Short name T965
Test name
Test status
Simulation time 21834363 ps
CPU time 1.54 seconds
Started Aug 19 04:27:35 PM PDT 24
Finished Aug 19 04:27:36 PM PDT 24
Peak memory 218356 kb
Host smart-e1226d8e-4da7-460e-a4df-8b02f874f337
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978741446 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.978741446
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.511129294
Short name T997
Test name
Test status
Simulation time 20441265 ps
CPU time 1.11 seconds
Started Aug 19 04:27:18 PM PDT 24
Finished Aug 19 04:27:20 PM PDT 24
Peak memory 209772 kb
Host smart-f242c014-ba06-449e-b7b0-50b16d7021f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511129294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.511129294
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.216669709
Short name T883
Test name
Test status
Simulation time 14015846 ps
CPU time 1.06 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:09 PM PDT 24
Peak memory 210136 kb
Host smart-3ae3214b-36cc-48b1-9932-1f9702e44b93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216669709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.216669709
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4105938411
Short name T897
Test name
Test status
Simulation time 162513303 ps
CPU time 2.82 seconds
Started Aug 19 04:27:47 PM PDT 24
Finished Aug 19 04:27:50 PM PDT 24
Peak memory 218284 kb
Host smart-3c4a3a4c-59e7-4e12-bb0f-efbb95932e13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105938411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.4105938411
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.77239068
Short name T917
Test name
Test status
Simulation time 33639495 ps
CPU time 2.1 seconds
Started Aug 19 04:27:37 PM PDT 24
Finished Aug 19 04:27:39 PM PDT 24
Peak memory 220436 kb
Host smart-8e856dbb-fd5f-4a62-9c40-0b8722051a26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77239068 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.77239068
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2616300463
Short name T198
Test name
Test status
Simulation time 34006485 ps
CPU time 0.94 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 209984 kb
Host smart-1c91c270-0b1e-46f1-9f47-5b3eafc44670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616300463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2616300463
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4182934484
Short name T950
Test name
Test status
Simulation time 361940222 ps
CPU time 1.29 seconds
Started Aug 19 04:27:18 PM PDT 24
Finished Aug 19 04:27:20 PM PDT 24
Peak memory 210028 kb
Host smart-d658e82b-e730-4ab6-9342-5f4c6119862a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182934484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.4182934484
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.52030525
Short name T899
Test name
Test status
Simulation time 28955008 ps
CPU time 1.87 seconds
Started Aug 19 04:27:39 PM PDT 24
Finished Aug 19 04:27:40 PM PDT 24
Peak memory 219336 kb
Host smart-69a8db65-1262-4152-86b5-295ad559367a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52030525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.52030525
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2596188313
Short name T134
Test name
Test status
Simulation time 90113706 ps
CPU time 2.31 seconds
Started Aug 19 04:27:37 PM PDT 24
Finished Aug 19 04:27:39 PM PDT 24
Peak memory 218240 kb
Host smart-6376f820-2503-4458-8c76-69ceb84854ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596188313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2596188313
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1582696290
Short name T878
Test name
Test status
Simulation time 419072466 ps
CPU time 2.04 seconds
Started Aug 19 04:28:07 PM PDT 24
Finished Aug 19 04:28:09 PM PDT 24
Peak memory 220124 kb
Host smart-f9b153b4-a0ed-492f-abf8-94486930b6d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582696290 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1582696290
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3010909900
Short name T971
Test name
Test status
Simulation time 15978501 ps
CPU time 1.17 seconds
Started Aug 19 04:28:42 PM PDT 24
Finished Aug 19 04:28:43 PM PDT 24
Peak memory 210120 kb
Host smart-f84e6fbe-cd85-4d67-9ca4-fce43e314f8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010909900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3010909900
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3242162556
Short name T975
Test name
Test status
Simulation time 279404240 ps
CPU time 1.96 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:27:46 PM PDT 24
Peak memory 219092 kb
Host smart-60b04f28-8de9-40d1-ae8d-4716253dc868
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242162556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3242162556
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.47204392
Short name T203
Test name
Test status
Simulation time 29382740 ps
CPU time 1.15 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 210092 kb
Host smart-e36c65dc-1f91-4fa2-9e3a-623e2efaeac0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47204392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing.47204392
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3098281294
Short name T902
Test name
Test status
Simulation time 49713835 ps
CPU time 1.49 seconds
Started Aug 19 04:27:12 PM PDT 24
Finished Aug 19 04:27:14 PM PDT 24
Peak memory 210056 kb
Host smart-2e352eeb-fdd5-461c-94eb-2a1706048763
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098281294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3098281294
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3434225424
Short name T959
Test name
Test status
Simulation time 16050755 ps
CPU time 0.96 seconds
Started Aug 19 04:28:02 PM PDT 24
Finished Aug 19 04:28:03 PM PDT 24
Peak memory 210612 kb
Host smart-a2010829-c550-4627-a2cb-c22ae66786d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434225424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3434225424
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1006725260
Short name T953
Test name
Test status
Simulation time 92567534 ps
CPU time 1.59 seconds
Started Aug 19 04:27:21 PM PDT 24
Finished Aug 19 04:27:22 PM PDT 24
Peak memory 218308 kb
Host smart-e235946e-8e5e-4374-be4a-47a5fb420bb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006725260 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1006725260
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.814240992
Short name T142
Test name
Test status
Simulation time 45127307 ps
CPU time 0.83 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:16 PM PDT 24
Peak memory 210088 kb
Host smart-f6590707-9f93-4c0b-92fb-5becc0aa445e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814240992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.814240992
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.849337425
Short name T919
Test name
Test status
Simulation time 1470046617 ps
CPU time 1.52 seconds
Started Aug 19 04:27:21 PM PDT 24
Finished Aug 19 04:27:22 PM PDT 24
Peak memory 210016 kb
Host smart-f0448333-105c-427f-9e95-a487a2028e7a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849337425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.849337425
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1970932731
Short name T962
Test name
Test status
Simulation time 440362356 ps
CPU time 10.86 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:22 PM PDT 24
Peak memory 210040 kb
Host smart-765fb55a-8604-4d2d-a53a-fa0ea1e4ddc1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970932731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1970932731
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1988592866
Short name T967
Test name
Test status
Simulation time 2188774471 ps
CPU time 6.71 seconds
Started Aug 19 04:27:02 PM PDT 24
Finished Aug 19 04:27:09 PM PDT 24
Peak memory 209472 kb
Host smart-c1b59567-d743-4444-9bf7-a3d91a986c8a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988592866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1988592866
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1354991596
Short name T892
Test name
Test status
Simulation time 75628713 ps
CPU time 2.2 seconds
Started Aug 19 04:27:26 PM PDT 24
Finished Aug 19 04:27:28 PM PDT 24
Peak memory 211612 kb
Host smart-a4e16e4a-b029-4c97-a148-7f6b21c9e90b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354991596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1354991596
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.796826763
Short name T147
Test name
Test status
Simulation time 406155878 ps
CPU time 1.72 seconds
Started Aug 19 04:27:13 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 221924 kb
Host smart-0b54b551-cbef-4c35-9e10-9727d54a1260
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796826
763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.796826763
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3387997475
Short name T984
Test name
Test status
Simulation time 38178105 ps
CPU time 1.02 seconds
Started Aug 19 04:27:13 PM PDT 24
Finished Aug 19 04:27:14 PM PDT 24
Peak memory 210068 kb
Host smart-8925a9e9-6169-44cc-a373-893c420650a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387997475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3387997475
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4080612471
Short name T916
Test name
Test status
Simulation time 21055765 ps
CPU time 1.43 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:13 PM PDT 24
Peak memory 210236 kb
Host smart-7b0a9ca1-43fa-4783-a57a-5848ff7e6ea4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080612471 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4080612471
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4239771698
Short name T213
Test name
Test status
Simulation time 16126253 ps
CPU time 0.96 seconds
Started Aug 19 04:27:12 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 210112 kb
Host smart-0a17ae02-eca4-4bcc-85fe-b3a1eaaae8f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239771698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.4239771698
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.933659304
Short name T127
Test name
Test status
Simulation time 132533217 ps
CPU time 2.76 seconds
Started Aug 19 04:27:57 PM PDT 24
Finished Aug 19 04:27:59 PM PDT 24
Peak memory 218300 kb
Host smart-85f3fd6c-564b-4526-aba3-3dc8024c9495
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933659304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.933659304
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1224796037
Short name T222
Test name
Test status
Simulation time 251778849 ps
CPU time 2.59 seconds
Started Aug 19 04:27:12 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 222644 kb
Host smart-afce2905-42a1-44d8-9237-12a3b10f46cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224796037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1224796037
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3647903139
Short name T933
Test name
Test status
Simulation time 89392723 ps
CPU time 1.01 seconds
Started Aug 19 04:27:21 PM PDT 24
Finished Aug 19 04:27:22 PM PDT 24
Peak memory 209128 kb
Host smart-b0b55271-f4ca-42c1-b562-9a1291ad23b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647903139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3647903139
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3404210130
Short name T942
Test name
Test status
Simulation time 65638137 ps
CPU time 1.13 seconds
Started Aug 19 04:27:12 PM PDT 24
Finished Aug 19 04:27:13 PM PDT 24
Peak memory 210060 kb
Host smart-87b321fc-9654-49fb-bb75-be71c3fffb3f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404210130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3404210130
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1087952910
Short name T204
Test name
Test status
Simulation time 51900874 ps
CPU time 1.01 seconds
Started Aug 19 04:27:10 PM PDT 24
Finished Aug 19 04:27:11 PM PDT 24
Peak memory 210316 kb
Host smart-4162810d-79a6-4748-92c3-26f5dd1dad52
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087952910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1087952910
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2279075712
Short name T918
Test name
Test status
Simulation time 14671877 ps
CPU time 0.97 seconds
Started Aug 19 04:27:06 PM PDT 24
Finished Aug 19 04:27:07 PM PDT 24
Peak memory 219928 kb
Host smart-f4d42a6d-08cf-45b8-bfec-e09021cdb9c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279075712 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2279075712
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3128486391
Short name T202
Test name
Test status
Simulation time 19641226 ps
CPU time 1.14 seconds
Started Aug 19 04:27:51 PM PDT 24
Finished Aug 19 04:27:52 PM PDT 24
Peak memory 209972 kb
Host smart-6e929474-3fa6-4b94-bef4-f9889634b60b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128486391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3128486391
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1612289711
Short name T930
Test name
Test status
Simulation time 41555477 ps
CPU time 1.56 seconds
Started Aug 19 04:27:21 PM PDT 24
Finished Aug 19 04:27:22 PM PDT 24
Peak memory 209784 kb
Host smart-7ea01664-b620-4d5c-95ed-7c536a578756
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612289711 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1612289711
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3550183635
Short name T976
Test name
Test status
Simulation time 791369516 ps
CPU time 5.39 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:20 PM PDT 24
Peak memory 209928 kb
Host smart-e615e6a4-5a33-4a21-82a4-ce4dc130aa42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550183635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3550183635
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4236633150
Short name T979
Test name
Test status
Simulation time 1108928968 ps
CPU time 8.56 seconds
Started Aug 19 04:27:01 PM PDT 24
Finished Aug 19 04:27:10 PM PDT 24
Peak memory 209820 kb
Host smart-5b654b0c-64e9-4518-9685-07884191cb72
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236633150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.4236633150
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.650571680
Short name T216
Test name
Test status
Simulation time 98151700 ps
CPU time 2.72 seconds
Started Aug 19 04:27:10 PM PDT 24
Finished Aug 19 04:27:13 PM PDT 24
Peak memory 211628 kb
Host smart-57ce1272-370c-4e07-8c16-6cd4919d3d23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650571680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.650571680
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2370049527
Short name T886
Test name
Test status
Simulation time 50388747 ps
CPU time 1.81 seconds
Started Aug 19 04:27:05 PM PDT 24
Finished Aug 19 04:27:07 PM PDT 24
Peak memory 219872 kb
Host smart-46b15a77-63a3-4841-a2f9-2f4d4d1e37d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237004
9527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2370049527
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3899678304
Short name T925
Test name
Test status
Simulation time 325501557 ps
CPU time 1.31 seconds
Started Aug 19 04:27:18 PM PDT 24
Finished Aug 19 04:27:19 PM PDT 24
Peak memory 209996 kb
Host smart-b0acd55b-eda5-4a19-9fbd-f0a32da696c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899678304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3899678304
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1532933429
Short name T974
Test name
Test status
Simulation time 50732181 ps
CPU time 1.08 seconds
Started Aug 19 04:27:07 PM PDT 24
Finished Aug 19 04:27:09 PM PDT 24
Peak memory 210080 kb
Host smart-04fe9547-e305-4919-8dc8-3931772ba96b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532933429 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1532933429
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3057772564
Short name T907
Test name
Test status
Simulation time 77077464 ps
CPU time 1.85 seconds
Started Aug 19 04:27:43 PM PDT 24
Finished Aug 19 04:27:45 PM PDT 24
Peak memory 218228 kb
Host smart-c901f312-9077-4478-93e4-027488f7ff9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057772564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3057772564
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2769336671
Short name T130
Test name
Test status
Simulation time 430194914 ps
CPU time 3.41 seconds
Started Aug 19 04:27:33 PM PDT 24
Finished Aug 19 04:27:37 PM PDT 24
Peak memory 218492 kb
Host smart-4e938005-d764-4056-bad0-8238033244c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769336671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2769336671
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2592412511
Short name T124
Test name
Test status
Simulation time 16808313 ps
CPU time 0.97 seconds
Started Aug 19 04:27:25 PM PDT 24
Finished Aug 19 04:27:26 PM PDT 24
Peak memory 210028 kb
Host smart-4460981f-2bfd-4d23-a017-718127a4edf6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592412511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2592412511
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1282639278
Short name T936
Test name
Test status
Simulation time 20911379 ps
CPU time 1.42 seconds
Started Aug 19 04:27:06 PM PDT 24
Finished Aug 19 04:27:08 PM PDT 24
Peak memory 208992 kb
Host smart-ff2a6b28-7dd0-4240-802a-66d157d0024d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282639278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1282639278
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4016865240
Short name T195
Test name
Test status
Simulation time 34368505 ps
CPU time 0.93 seconds
Started Aug 19 04:27:12 PM PDT 24
Finished Aug 19 04:27:13 PM PDT 24
Peak memory 209992 kb
Host smart-3556d1ed-d452-4bbb-b4b0-f2a845f6d21c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016865240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.4016865240
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3543926961
Short name T119
Test name
Test status
Simulation time 18549558 ps
CPU time 1.06 seconds
Started Aug 19 04:27:33 PM PDT 24
Finished Aug 19 04:27:34 PM PDT 24
Peak memory 218416 kb
Host smart-d80da221-8bc4-4f94-9617-8ce2b10e7189
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543926961 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3543926961
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2397472012
Short name T211
Test name
Test status
Simulation time 18396371 ps
CPU time 0.95 seconds
Started Aug 19 04:27:37 PM PDT 24
Finished Aug 19 04:27:38 PM PDT 24
Peak memory 210012 kb
Host smart-1f09f1c0-f915-4312-9aec-96eee96215e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397472012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2397472012
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.4136935664
Short name T922
Test name
Test status
Simulation time 171901580 ps
CPU time 2.62 seconds
Started Aug 19 04:27:43 PM PDT 24
Finished Aug 19 04:27:46 PM PDT 24
Peak memory 210004 kb
Host smart-61f4499e-d76d-438f-ac58-d6a5f0a19d92
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136935664 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.4136935664
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.954398837
Short name T938
Test name
Test status
Simulation time 843508859 ps
CPU time 9.67 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:21 PM PDT 24
Peak memory 209836 kb
Host smart-f68804ae-4ce8-4f25-8f5f-036072a362d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954398837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.954398837
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.619898281
Short name T932
Test name
Test status
Simulation time 2182327556 ps
CPU time 23.49 seconds
Started Aug 19 04:27:09 PM PDT 24
Finished Aug 19 04:27:32 PM PDT 24
Peak memory 209964 kb
Host smart-abe014be-4456-4609-9159-4ffd14224c19
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619898281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.619898281
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1160330979
Short name T126
Test name
Test status
Simulation time 348196769 ps
CPU time 1.33 seconds
Started Aug 19 04:27:16 PM PDT 24
Finished Aug 19 04:27:17 PM PDT 24
Peak memory 211660 kb
Host smart-65ba1cd9-4fdd-485d-9913-7eb8a74c1302
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160330979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1160330979
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1448999629
Short name T143
Test name
Test status
Simulation time 270973435 ps
CPU time 4.45 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:19 PM PDT 24
Peak memory 223316 kb
Host smart-9a8aae0d-647a-47fe-a6de-190319c862c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144899
9629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1448999629
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2775914986
Short name T989
Test name
Test status
Simulation time 319174029 ps
CPU time 1.32 seconds
Started Aug 19 04:27:07 PM PDT 24
Finished Aug 19 04:27:08 PM PDT 24
Peak memory 210028 kb
Host smart-f7c6a957-1d01-4122-a46a-d02eb5f03d6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775914986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2775914986
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3968560339
Short name T990
Test name
Test status
Simulation time 138807697 ps
CPU time 1.73 seconds
Started Aug 19 04:27:02 PM PDT 24
Finished Aug 19 04:27:04 PM PDT 24
Peak memory 218184 kb
Host smart-88fd11dc-8453-494f-b6ea-b9e052572ba7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968560339 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3968560339
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1268267415
Short name T931
Test name
Test status
Simulation time 26324502 ps
CPU time 1.17 seconds
Started Aug 19 04:27:38 PM PDT 24
Finished Aug 19 04:27:40 PM PDT 24
Peak memory 210108 kb
Host smart-a611bc39-7503-4bfd-955c-d945916bdfde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268267415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1268267415
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3525190341
Short name T951
Test name
Test status
Simulation time 38962493 ps
CPU time 2.54 seconds
Started Aug 19 04:27:06 PM PDT 24
Finished Aug 19 04:27:09 PM PDT 24
Peak memory 218392 kb
Host smart-ab8d00e8-18b9-4815-8d13-945b50b3198a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525190341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3525190341
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1378763638
Short name T995
Test name
Test status
Simulation time 115280301 ps
CPU time 4.1 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 218216 kb
Host smart-72b6fa09-cda0-4ac7-be57-3b0ebfda8fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378763638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1378763638
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2167887412
Short name T910
Test name
Test status
Simulation time 96915998 ps
CPU time 1.76 seconds
Started Aug 19 04:27:43 PM PDT 24
Finished Aug 19 04:27:45 PM PDT 24
Peak memory 220476 kb
Host smart-b7f5a43f-ad13-4665-bdf3-a809b38edcfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167887412 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2167887412
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3922116416
Short name T199
Test name
Test status
Simulation time 53926709 ps
CPU time 1.02 seconds
Started Aug 19 04:27:21 PM PDT 24
Finished Aug 19 04:27:22 PM PDT 24
Peak memory 209888 kb
Host smart-3b8d3a0b-fdb5-4b00-aa4c-b82b0b3f4b1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922116416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3922116416
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2511368661
Short name T877
Test name
Test status
Simulation time 52013287 ps
CPU time 1.19 seconds
Started Aug 19 04:27:27 PM PDT 24
Finished Aug 19 04:27:29 PM PDT 24
Peak memory 208760 kb
Host smart-c7e545f3-d28e-4655-b784-faa0942b3b8e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511368661 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2511368661
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4177300532
Short name T957
Test name
Test status
Simulation time 440657747 ps
CPU time 5.36 seconds
Started Aug 19 04:27:12 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 209840 kb
Host smart-a6710247-f2df-45c0-a052-ce84d989a021
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177300532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.4177300532
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4270592280
Short name T904
Test name
Test status
Simulation time 3334527617 ps
CPU time 20.46 seconds
Started Aug 19 04:27:08 PM PDT 24
Finished Aug 19 04:27:28 PM PDT 24
Peak memory 210148 kb
Host smart-0ff91605-7c17-46bc-b27a-49e35e88225b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270592280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4270592280
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1945847468
Short name T937
Test name
Test status
Simulation time 102621622 ps
CPU time 1.27 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:12 PM PDT 24
Peak memory 211460 kb
Host smart-37d7fd7b-2bf7-4348-ae05-6ec4ef6aa8ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945847468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1945847468
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3213729475
Short name T939
Test name
Test status
Simulation time 240973454 ps
CPU time 3.23 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 218400 kb
Host smart-63fc370f-028f-4c41-bc95-fbd7c3c369a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321372
9475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3213729475
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.686812589
Short name T145
Test name
Test status
Simulation time 55104194 ps
CPU time 1.95 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:17 PM PDT 24
Peak memory 210044 kb
Host smart-6e7be209-b361-4d14-9b6c-8ab09769f696
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686812589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.686812589
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4032349196
Short name T956
Test name
Test status
Simulation time 51228663 ps
CPU time 1.91 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 210236 kb
Host smart-96561538-7fcd-4c9b-b90d-03589d905a69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032349196 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.4032349196
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3123742982
Short name T209
Test name
Test status
Simulation time 123040889 ps
CPU time 1.07 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 210124 kb
Host smart-315a8b84-7d86-4596-a5f9-42dcfd3e564f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123742982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3123742982
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.721453721
Short name T900
Test name
Test status
Simulation time 48382559 ps
CPU time 1.69 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:13 PM PDT 24
Peak memory 218216 kb
Host smart-053c5815-a17e-4e64-9d57-6300158abb8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721453721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.721453721
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2205202278
Short name T947
Test name
Test status
Simulation time 105855685 ps
CPU time 1.14 seconds
Started Aug 19 04:27:16 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 218300 kb
Host smart-f26921cf-6e1e-4998-a1cd-80da5ff14e36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205202278 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2205202278
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1692228690
Short name T985
Test name
Test status
Simulation time 18765268 ps
CPU time 1.09 seconds
Started Aug 19 04:27:22 PM PDT 24
Finished Aug 19 04:27:23 PM PDT 24
Peak memory 209884 kb
Host smart-f603b17e-4281-4dfb-820c-a7076e1342ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692228690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1692228690
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2609749393
Short name T954
Test name
Test status
Simulation time 271929585 ps
CPU time 2.06 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:17 PM PDT 24
Peak memory 210012 kb
Host smart-dfc232a4-548c-4ba7-b7bd-322a4a0080b3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609749393 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2609749393
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.417293315
Short name T906
Test name
Test status
Simulation time 1690464605 ps
CPU time 5.21 seconds
Started Aug 19 04:27:31 PM PDT 24
Finished Aug 19 04:27:36 PM PDT 24
Peak memory 210028 kb
Host smart-5bb07210-3e57-408a-ab63-b2cd13a75883
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417293315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.417293315
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.345527264
Short name T913
Test name
Test status
Simulation time 3058605242 ps
CPU time 19.96 seconds
Started Aug 19 04:27:35 PM PDT 24
Finished Aug 19 04:27:56 PM PDT 24
Peak memory 209300 kb
Host smart-fdfe2411-a6bf-4c9e-a12f-0d00888b781b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345527264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.345527264
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2204269782
Short name T901
Test name
Test status
Simulation time 343963186 ps
CPU time 1.73 seconds
Started Aug 19 04:27:22 PM PDT 24
Finished Aug 19 04:27:24 PM PDT 24
Peak memory 211700 kb
Host smart-45f5fdcb-2026-449e-8177-22f6fb063179
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204269782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2204269782
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2630388171
Short name T915
Test name
Test status
Simulation time 1175514215 ps
CPU time 3.91 seconds
Started Aug 19 04:27:58 PM PDT 24
Finished Aug 19 04:28:02 PM PDT 24
Peak memory 219560 kb
Host smart-4881ce54-5ce2-4de9-b6b9-13dbd9e745a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263038
8171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2630388171
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1158962226
Short name T928
Test name
Test status
Simulation time 143419888 ps
CPU time 3.62 seconds
Started Aug 19 04:27:13 PM PDT 24
Finished Aug 19 04:27:17 PM PDT 24
Peak memory 210084 kb
Host smart-f5c87d31-a953-45c6-804d-49552089f292
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158962226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1158962226
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4041537441
Short name T944
Test name
Test status
Simulation time 17170314 ps
CPU time 0.98 seconds
Started Aug 19 04:27:48 PM PDT 24
Finished Aug 19 04:27:49 PM PDT 24
Peak memory 210084 kb
Host smart-916fa274-bebc-4eb4-9761-15575ca16564
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041537441 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.4041537441
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2791935048
Short name T123
Test name
Test status
Simulation time 288432960 ps
CPU time 1.78 seconds
Started Aug 19 04:27:33 PM PDT 24
Finished Aug 19 04:27:35 PM PDT 24
Peak memory 210064 kb
Host smart-35dbb605-02c2-47b7-8ac0-9bfe32bba7d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791935048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2791935048
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3035933428
Short name T893
Test name
Test status
Simulation time 59509070 ps
CPU time 2.07 seconds
Started Aug 19 04:27:16 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 218304 kb
Host smart-49a9d839-9c1c-4067-aa07-4920e4e6347b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035933428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3035933428
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4268057631
Short name T141
Test name
Test status
Simulation time 53242025 ps
CPU time 1.99 seconds
Started Aug 19 04:27:22 PM PDT 24
Finished Aug 19 04:27:24 PM PDT 24
Peak memory 222664 kb
Host smart-b2b00845-9152-4928-8b27-c54775601d75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268057631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.4268057631
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1175339145
Short name T895
Test name
Test status
Simulation time 25764150 ps
CPU time 1.53 seconds
Started Aug 19 04:27:46 PM PDT 24
Finished Aug 19 04:27:48 PM PDT 24
Peak memory 222188 kb
Host smart-b020dcbe-c8dd-4f9e-babb-3bceaff8a0c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175339145 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1175339145
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2088620788
Short name T872
Test name
Test status
Simulation time 15682261 ps
CPU time 1.12 seconds
Started Aug 19 04:27:31 PM PDT 24
Finished Aug 19 04:27:32 PM PDT 24
Peak memory 210000 kb
Host smart-1ebe60e7-e829-4a64-9965-fe381cf44452
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088620788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2088620788
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3141130699
Short name T912
Test name
Test status
Simulation time 216571128 ps
CPU time 1.23 seconds
Started Aug 19 04:27:45 PM PDT 24
Finished Aug 19 04:27:46 PM PDT 24
Peak memory 210128 kb
Host smart-ff376d28-6855-40f3-84f9-f61ec1d897b0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141130699 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3141130699
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2040572040
Short name T993
Test name
Test status
Simulation time 3252129898 ps
CPU time 19.17 seconds
Started Aug 19 04:27:38 PM PDT 24
Finished Aug 19 04:27:57 PM PDT 24
Peak memory 210228 kb
Host smart-300addff-6f8d-436b-872f-a83764e42143
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040572040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2040572040
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2943452223
Short name T898
Test name
Test status
Simulation time 422076339 ps
CPU time 11.15 seconds
Started Aug 19 04:27:53 PM PDT 24
Finished Aug 19 04:28:04 PM PDT 24
Peak memory 209860 kb
Host smart-1b2e42f9-2acd-401e-ad54-e87ba41ada4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943452223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2943452223
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.4153099523
Short name T988
Test name
Test status
Simulation time 413937132 ps
CPU time 3.06 seconds
Started Aug 19 04:27:22 PM PDT 24
Finished Aug 19 04:27:25 PM PDT 24
Peak memory 211724 kb
Host smart-921eac1f-4e28-4a79-9509-1ce6c4066559
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153099523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.4153099523
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1364404424
Short name T955
Test name
Test status
Simulation time 132849381 ps
CPU time 1.29 seconds
Started Aug 19 04:27:22 PM PDT 24
Finished Aug 19 04:27:23 PM PDT 24
Peak memory 219468 kb
Host smart-a843a8be-0aca-438b-85df-5eb4b16d9961
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136440
4424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1364404424
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1116272502
Short name T952
Test name
Test status
Simulation time 110730183 ps
CPU time 3.1 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 210116 kb
Host smart-73763b83-534b-465d-beac-e47eaa2a89f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116272502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1116272502
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1617286354
Short name T958
Test name
Test status
Simulation time 27187658 ps
CPU time 1.46 seconds
Started Aug 19 04:27:31 PM PDT 24
Finished Aug 19 04:27:33 PM PDT 24
Peak memory 210104 kb
Host smart-dd67791d-ef71-483c-a173-901a61a15503
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617286354 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1617286354
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3157866453
Short name T909
Test name
Test status
Simulation time 31596714 ps
CPU time 1.12 seconds
Started Aug 19 04:27:40 PM PDT 24
Finished Aug 19 04:27:41 PM PDT 24
Peak memory 210128 kb
Host smart-cab1222b-b628-4372-9491-a60f7168a2ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157866453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3157866453
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3674292279
Short name T881
Test name
Test status
Simulation time 307329134 ps
CPU time 3.4 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:17 PM PDT 24
Peak memory 218312 kb
Host smart-b9a2f6f1-95e2-4d40-be02-bb796519b93d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674292279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3674292279
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3417881840
Short name T945
Test name
Test status
Simulation time 80274505 ps
CPU time 1.44 seconds
Started Aug 19 04:27:50 PM PDT 24
Finished Aug 19 04:27:51 PM PDT 24
Peak memory 218836 kb
Host smart-d1bda603-f920-494d-a09d-2668c4fd6c2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417881840 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3417881840
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2285239613
Short name T207
Test name
Test status
Simulation time 13125572 ps
CPU time 0.82 seconds
Started Aug 19 04:27:16 PM PDT 24
Finished Aug 19 04:27:17 PM PDT 24
Peak memory 209968 kb
Host smart-a11ed026-cec9-4003-a949-3be68491af1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285239613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2285239613
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2537080728
Short name T905
Test name
Test status
Simulation time 888244778 ps
CPU time 1.68 seconds
Started Aug 19 04:27:36 PM PDT 24
Finished Aug 19 04:27:37 PM PDT 24
Peak memory 208844 kb
Host smart-a867bc2b-22cf-4587-8504-b2c808aa5f88
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537080728 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2537080728
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.105273382
Short name T978
Test name
Test status
Simulation time 194204080 ps
CPU time 5.21 seconds
Started Aug 19 04:27:17 PM PDT 24
Finished Aug 19 04:27:23 PM PDT 24
Peak memory 210028 kb
Host smart-3bfad2e6-f67e-458b-847e-baaa0231c487
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105273382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.105273382
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2332989946
Short name T885
Test name
Test status
Simulation time 919329667 ps
CPU time 10.72 seconds
Started Aug 19 04:27:58 PM PDT 24
Finished Aug 19 04:28:09 PM PDT 24
Peak memory 209312 kb
Host smart-df83c3cc-2036-41b8-affc-9fc68c07147d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332989946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2332989946
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3061129718
Short name T986
Test name
Test status
Simulation time 235288108 ps
CPU time 3.02 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 211612 kb
Host smart-2da2fde3-bac3-4a08-bc7c-be77105e9cf9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061129718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3061129718
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1962497054
Short name T996
Test name
Test status
Simulation time 340801911 ps
CPU time 7.18 seconds
Started Aug 19 04:27:50 PM PDT 24
Finished Aug 19 04:27:58 PM PDT 24
Peak memory 218376 kb
Host smart-687668d7-3cfd-4b6c-9522-fa2381485ebb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196249
7054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1962497054
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2135967242
Short name T144
Test name
Test status
Simulation time 79749322 ps
CPU time 1.14 seconds
Started Aug 19 04:27:38 PM PDT 24
Finished Aug 19 04:27:39 PM PDT 24
Peak memory 209980 kb
Host smart-9d1a2e7e-0da0-4155-861e-4fa267bef7a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135967242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2135967242
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.603717474
Short name T894
Test name
Test status
Simulation time 61551404 ps
CPU time 1.26 seconds
Started Aug 19 04:27:25 PM PDT 24
Finished Aug 19 04:27:26 PM PDT 24
Peak memory 209896 kb
Host smart-c7b77629-89b6-4a28-a084-15cf5ebccd1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603717474 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.603717474
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.845367104
Short name T977
Test name
Test status
Simulation time 107948956 ps
CPU time 1.47 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:13 PM PDT 24
Peak memory 210024 kb
Host smart-b6e30cdb-ecb7-4292-b678-0fa27354c06f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845367104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.845367104
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2503092570
Short name T908
Test name
Test status
Simulation time 97858206 ps
CPU time 1.72 seconds
Started Aug 19 04:27:24 PM PDT 24
Finished Aug 19 04:27:26 PM PDT 24
Peak memory 219408 kb
Host smart-7588fcec-ad18-4f4e-965f-5fd02fab765d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503092570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2503092570
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1791109792
Short name T879
Test name
Test status
Simulation time 16349483 ps
CPU time 1.25 seconds
Started Aug 19 04:27:58 PM PDT 24
Finished Aug 19 04:28:00 PM PDT 24
Peak memory 219988 kb
Host smart-0dc20098-0eae-43ef-a039-f28b4e6eb62a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791109792 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1791109792
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1772192617
Short name T914
Test name
Test status
Simulation time 132773901 ps
CPU time 0.94 seconds
Started Aug 19 04:27:18 PM PDT 24
Finished Aug 19 04:27:19 PM PDT 24
Peak memory 210028 kb
Host smart-c6ea93a8-4194-477c-9294-c3490488d603
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772192617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1772192617
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1825171722
Short name T943
Test name
Test status
Simulation time 56850852 ps
CPU time 1.3 seconds
Started Aug 19 04:27:49 PM PDT 24
Finished Aug 19 04:27:50 PM PDT 24
Peak memory 208808 kb
Host smart-fbc02656-eb14-4d0a-ab0c-730c645157b1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825171722 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1825171722
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1526769522
Short name T966
Test name
Test status
Simulation time 1831150410 ps
CPU time 11.38 seconds
Started Aug 19 04:27:22 PM PDT 24
Finished Aug 19 04:27:34 PM PDT 24
Peak memory 209384 kb
Host smart-73bdaa96-108c-4cd9-9376-54081de4c4c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526769522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1526769522
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1873688993
Short name T946
Test name
Test status
Simulation time 3939408128 ps
CPU time 9.04 seconds
Started Aug 19 04:28:00 PM PDT 24
Finished Aug 19 04:28:09 PM PDT 24
Peak memory 210144 kb
Host smart-0954c619-8763-4c0d-be59-215772be1611
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873688993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1873688993
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2851962942
Short name T935
Test name
Test status
Simulation time 584258450 ps
CPU time 2.11 seconds
Started Aug 19 04:27:47 PM PDT 24
Finished Aug 19 04:27:50 PM PDT 24
Peak memory 211664 kb
Host smart-ff445973-04ef-4995-8c30-07d1145d9a53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851962942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2851962942
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3286241017
Short name T146
Test name
Test status
Simulation time 76537751 ps
CPU time 2.47 seconds
Started Aug 19 04:27:17 PM PDT 24
Finished Aug 19 04:27:19 PM PDT 24
Peak memory 218380 kb
Host smart-49c9be01-b63b-40db-8244-735ed1c5b0bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328624
1017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3286241017
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.4094121742
Short name T875
Test name
Test status
Simulation time 219246337 ps
CPU time 1.22 seconds
Started Aug 19 04:27:30 PM PDT 24
Finished Aug 19 04:27:31 PM PDT 24
Peak memory 209984 kb
Host smart-f3ae8401-2b10-4786-9c2d-c3c5a18d4740
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094121742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.4094121742
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3408380403
Short name T208
Test name
Test status
Simulation time 91317275 ps
CPU time 1.12 seconds
Started Aug 19 04:27:47 PM PDT 24
Finished Aug 19 04:27:48 PM PDT 24
Peak memory 209820 kb
Host smart-8333dc90-c59a-412d-a103-5010de33061c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408380403 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3408380403
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2473101894
Short name T903
Test name
Test status
Simulation time 50461800 ps
CPU time 1.09 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 210348 kb
Host smart-e1c81418-bb62-4e8e-b028-efb909e3aab9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473101894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2473101894
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.371124755
Short name T874
Test name
Test status
Simulation time 349407262 ps
CPU time 3.53 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:19 PM PDT 24
Peak memory 218316 kb
Host smart-ddaa1415-42cc-41c2-8926-d729cbc0f318
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371124755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.371124755
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.590357403
Short name T137
Test name
Test status
Simulation time 210427598 ps
CPU time 1.96 seconds
Started Aug 19 04:27:52 PM PDT 24
Finished Aug 19 04:27:54 PM PDT 24
Peak memory 213724 kb
Host smart-fe40cc15-d4bc-414c-93c0-d43513379d8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590357403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.590357403
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3688524606
Short name T763
Test name
Test status
Simulation time 36485961 ps
CPU time 1.03 seconds
Started Aug 19 04:38:44 PM PDT 24
Finished Aug 19 04:38:45 PM PDT 24
Peak memory 209016 kb
Host smart-2137f8a1-cd21-406c-b76c-1fb2fcf4143d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688524606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3688524606
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3346281596
Short name T312
Test name
Test status
Simulation time 32406792 ps
CPU time 0.85 seconds
Started Aug 19 04:38:53 PM PDT 24
Finished Aug 19 04:38:54 PM PDT 24
Peak memory 208720 kb
Host smart-f8cde8b4-b74b-48fe-8b80-a152eebb6fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346281596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3346281596
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3025358959
Short name T412
Test name
Test status
Simulation time 387068960 ps
CPU time 14.97 seconds
Started Aug 19 04:38:43 PM PDT 24
Finished Aug 19 04:38:58 PM PDT 24
Peak memory 218376 kb
Host smart-dcf8e67d-45d2-44cc-b9b7-decc45046a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025358959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3025358959
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.363333948
Short name T426
Test name
Test status
Simulation time 112196992 ps
CPU time 2.06 seconds
Started Aug 19 04:38:42 PM PDT 24
Finished Aug 19 04:38:45 PM PDT 24
Peak memory 217776 kb
Host smart-c32ed928-4949-40b2-9193-cbcb2874ef53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363333948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.363333948
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.4272172029
Short name T551
Test name
Test status
Simulation time 8461915346 ps
CPU time 31.73 seconds
Started Aug 19 04:38:46 PM PDT 24
Finished Aug 19 04:39:18 PM PDT 24
Peak memory 219092 kb
Host smart-e6a2a9af-4601-499d-8f1e-b2ca8fc037e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272172029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.4272172029
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2754995415
Short name T593
Test name
Test status
Simulation time 2418693513 ps
CPU time 2.56 seconds
Started Aug 19 04:38:48 PM PDT 24
Finished Aug 19 04:38:50 PM PDT 24
Peak memory 217880 kb
Host smart-b6171d78-8b2f-485d-9af3-c9fa1ca45b8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754995415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
754995415
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.893393850
Short name T658
Test name
Test status
Simulation time 760633756 ps
CPU time 7.46 seconds
Started Aug 19 04:38:47 PM PDT 24
Finished Aug 19 04:38:54 PM PDT 24
Peak memory 223264 kb
Host smart-e629f7ad-c819-4027-a811-ea741ea24a9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893393850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.893393850
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2223302593
Short name T288
Test name
Test status
Simulation time 1011703125 ps
CPU time 27.98 seconds
Started Aug 19 04:38:44 PM PDT 24
Finished Aug 19 04:39:12 PM PDT 24
Peak memory 217704 kb
Host smart-065feaf3-0528-486a-b266-6eb30a9f66e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223302593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2223302593
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2797107500
Short name T292
Test name
Test status
Simulation time 95527942 ps
CPU time 3.39 seconds
Started Aug 19 04:38:49 PM PDT 24
Finished Aug 19 04:38:52 PM PDT 24
Peak memory 217672 kb
Host smart-7c46a887-c133-4f90-85cb-7aa0c45547a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797107500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2797107500
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2795268528
Short name T589
Test name
Test status
Simulation time 1921518217 ps
CPU time 33.98 seconds
Started Aug 19 04:38:45 PM PDT 24
Finished Aug 19 04:39:19 PM PDT 24
Peak memory 272332 kb
Host smart-f8482d93-187c-42ed-ab4a-bf2f47995e81
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795268528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2795268528
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1417463620
Short name T274
Test name
Test status
Simulation time 1515057190 ps
CPU time 8.48 seconds
Started Aug 19 04:38:49 PM PDT 24
Finished Aug 19 04:38:57 PM PDT 24
Peak memory 223084 kb
Host smart-0da60d8d-a733-4c33-b055-701775075111
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417463620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1417463620
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1466609686
Short name T214
Test name
Test status
Simulation time 123237846 ps
CPU time 2.19 seconds
Started Aug 19 04:38:40 PM PDT 24
Finished Aug 19 04:38:42 PM PDT 24
Peak memory 218348 kb
Host smart-ab61bdb0-a850-43b4-8a37-fd68308ed992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466609686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1466609686
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.4051326603
Short name T190
Test name
Test status
Simulation time 1481918154 ps
CPU time 24.19 seconds
Started Aug 19 04:38:43 PM PDT 24
Finished Aug 19 04:39:07 PM PDT 24
Peak memory 214976 kb
Host smart-7e751e10-ed9c-4333-b81a-842b64f785a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051326603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.4051326603
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2804524831
Short name T655
Test name
Test status
Simulation time 3671787193 ps
CPU time 21.11 seconds
Started Aug 19 04:38:45 PM PDT 24
Finished Aug 19 04:39:06 PM PDT 24
Peak memory 219632 kb
Host smart-e3bb83eb-dda5-4c5e-b4b2-5c7d47c7cb7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804524831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2804524831
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1155776833
Short name T687
Test name
Test status
Simulation time 613253541 ps
CPU time 15.05 seconds
Started Aug 19 04:38:47 PM PDT 24
Finished Aug 19 04:39:02 PM PDT 24
Peak memory 226076 kb
Host smart-33a03eb5-de17-49af-a760-6bbbcb8c3d87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155776833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1155776833
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1582761760
Short name T506
Test name
Test status
Simulation time 380662896 ps
CPU time 7.82 seconds
Started Aug 19 04:38:44 PM PDT 24
Finished Aug 19 04:38:52 PM PDT 24
Peak memory 218304 kb
Host smart-209c6496-996b-4084-a519-69c9b6a57c2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582761760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
582761760
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1700454758
Short name T686
Test name
Test status
Simulation time 362272779 ps
CPU time 8.61 seconds
Started Aug 19 04:38:45 PM PDT 24
Finished Aug 19 04:38:53 PM PDT 24
Peak memory 218536 kb
Host smart-df3b9405-35fa-434d-bf6d-9b678ffca337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700454758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1700454758
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1873469546
Short name T448
Test name
Test status
Simulation time 44077793 ps
CPU time 2.66 seconds
Started Aug 19 04:38:39 PM PDT 24
Finished Aug 19 04:38:41 PM PDT 24
Peak memory 217764 kb
Host smart-524c7c3c-1d4b-4114-9eac-81f2e56042d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873469546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1873469546
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3819505230
Short name T177
Test name
Test status
Simulation time 333083727 ps
CPU time 24.3 seconds
Started Aug 19 04:38:35 PM PDT 24
Finished Aug 19 04:39:00 PM PDT 24
Peak memory 251008 kb
Host smart-348c7bce-eb6a-42cc-be58-0dab15e1d91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819505230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3819505230
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2657820330
Short name T699
Test name
Test status
Simulation time 87998939 ps
CPU time 6.05 seconds
Started Aug 19 04:38:40 PM PDT 24
Finished Aug 19 04:38:46 PM PDT 24
Peak memory 247040 kb
Host smart-2debfe90-13d9-46e9-a6bf-03dc1c091d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657820330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2657820330
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1651974422
Short name T571
Test name
Test status
Simulation time 9708056574 ps
CPU time 161.04 seconds
Started Aug 19 04:38:45 PM PDT 24
Finished Aug 19 04:41:26 PM PDT 24
Peak memory 270212 kb
Host smart-331c12da-94b3-46eb-96f4-9d338f4c7acb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651974422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1651974422
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2207114463
Short name T243
Test name
Test status
Simulation time 69446468 ps
CPU time 0.98 seconds
Started Aug 19 04:38:40 PM PDT 24
Finished Aug 19 04:38:41 PM PDT 24
Peak memory 212096 kb
Host smart-fb7a9065-f784-4859-bd0e-96ff03af8167
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207114463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2207114463
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3872878360
Short name T861
Test name
Test status
Simulation time 35665565 ps
CPU time 1.09 seconds
Started Aug 19 04:38:54 PM PDT 24
Finished Aug 19 04:38:56 PM PDT 24
Peak memory 209136 kb
Host smart-492797be-d248-49d6-8783-149eeadb61bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872878360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3872878360
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.260979509
Short name T607
Test name
Test status
Simulation time 29358832 ps
CPU time 0.78 seconds
Started Aug 19 04:38:58 PM PDT 24
Finished Aug 19 04:38:59 PM PDT 24
Peak memory 209028 kb
Host smart-61e8a717-6dcb-42a9-8d29-d9e6f90e3b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260979509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.260979509
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.368825829
Short name T501
Test name
Test status
Simulation time 1817636045 ps
CPU time 17.98 seconds
Started Aug 19 04:38:45 PM PDT 24
Finished Aug 19 04:39:03 PM PDT 24
Peak memory 218356 kb
Host smart-c28ce6b6-55af-442f-93e9-b7b279a9cd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368825829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.368825829
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2017154178
Short name T801
Test name
Test status
Simulation time 1134629371 ps
CPU time 6.4 seconds
Started Aug 19 04:38:58 PM PDT 24
Finished Aug 19 04:39:05 PM PDT 24
Peak memory 217768 kb
Host smart-a3b83779-d4d6-4bb9-a206-b8d4d3a15f1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017154178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2017154178
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.942419342
Short name T839
Test name
Test status
Simulation time 4418006370 ps
CPU time 31.76 seconds
Started Aug 19 04:38:54 PM PDT 24
Finished Aug 19 04:39:26 PM PDT 24
Peak memory 219076 kb
Host smart-d440ef1b-16c9-4eef-b5b9-f6dd23defa76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942419342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.942419342
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3525364179
Short name T475
Test name
Test status
Simulation time 281675842 ps
CPU time 1.73 seconds
Started Aug 19 04:39:00 PM PDT 24
Finished Aug 19 04:39:01 PM PDT 24
Peak memory 217828 kb
Host smart-5c5ed198-ca36-48e9-a66d-5e4584f580ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525364179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
525364179
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1800846476
Short name T230
Test name
Test status
Simulation time 1777063215 ps
CPU time 8.97 seconds
Started Aug 19 04:38:58 PM PDT 24
Finished Aug 19 04:39:07 PM PDT 24
Peak memory 218316 kb
Host smart-bbafb3cb-25ee-4d96-8587-71e66f57e5d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800846476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1800846476
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1422693818
Short name T335
Test name
Test status
Simulation time 1481538633 ps
CPU time 38.54 seconds
Started Aug 19 04:38:55 PM PDT 24
Finished Aug 19 04:39:34 PM PDT 24
Peak memory 217680 kb
Host smart-42df4c6e-6cb4-4eef-923d-37ee5267bbd2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422693818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1422693818
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2177046992
Short name T78
Test name
Test status
Simulation time 124677552 ps
CPU time 3.85 seconds
Started Aug 19 04:38:54 PM PDT 24
Finished Aug 19 04:38:58 PM PDT 24
Peak memory 217688 kb
Host smart-9e745e10-cb2e-4c2d-a9f7-a47f40b68c19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177046992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2177046992
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2803318292
Short name T3
Test name
Test status
Simulation time 1285297442 ps
CPU time 35.15 seconds
Started Aug 19 04:38:58 PM PDT 24
Finished Aug 19 04:39:33 PM PDT 24
Peak memory 275496 kb
Host smart-df3ea499-1b3e-4071-b63d-30286fb870da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803318292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2803318292
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2231385543
Short name T679
Test name
Test status
Simulation time 2561517298 ps
CPU time 23.72 seconds
Started Aug 19 04:40:18 PM PDT 24
Finished Aug 19 04:40:42 PM PDT 24
Peak memory 249820 kb
Host smart-c6007156-e16e-465e-a5ad-cebad854c926
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231385543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2231385543
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3070381365
Short name T705
Test name
Test status
Simulation time 50794926 ps
CPU time 2.29 seconds
Started Aug 19 04:38:46 PM PDT 24
Finished Aug 19 04:38:49 PM PDT 24
Peak memory 222432 kb
Host smart-a05c8156-7238-4822-824c-0f8197a0b5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070381365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3070381365
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3866706266
Short name T393
Test name
Test status
Simulation time 386572100 ps
CPU time 14.21 seconds
Started Aug 19 04:38:44 PM PDT 24
Finished Aug 19 04:38:58 PM PDT 24
Peak memory 217792 kb
Host smart-bb24740d-32db-467f-ba83-f74a706a504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866706266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3866706266
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1946981732
Short name T61
Test name
Test status
Simulation time 921680451 ps
CPU time 39.09 seconds
Started Aug 19 04:38:58 PM PDT 24
Finished Aug 19 04:39:37 PM PDT 24
Peak memory 284416 kb
Host smart-f27b2c9c-5934-4e1f-b48f-834cda3cd440
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946981732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1946981732
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3852819575
Short name T310
Test name
Test status
Simulation time 2050198453 ps
CPU time 22.54 seconds
Started Aug 19 04:38:53 PM PDT 24
Finished Aug 19 04:39:16 PM PDT 24
Peak memory 226148 kb
Host smart-2a4cff72-5fdd-4581-965c-4bffa2df9b4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852819575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3852819575
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3267942948
Short name T264
Test name
Test status
Simulation time 888650484 ps
CPU time 11.39 seconds
Started Aug 19 04:38:57 PM PDT 24
Finished Aug 19 04:39:08 PM PDT 24
Peak memory 226064 kb
Host smart-f378c66c-273d-4b93-ae14-9db6b6915c3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267942948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3267942948
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1554090390
Short name T373
Test name
Test status
Simulation time 2557367407 ps
CPU time 11.39 seconds
Started Aug 19 04:38:53 PM PDT 24
Finished Aug 19 04:39:04 PM PDT 24
Peak memory 218364 kb
Host smart-4698d6d3-facc-4ac5-a9ef-5f80b63e1a40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554090390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
554090390
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3191020287
Short name T315
Test name
Test status
Simulation time 1974954101 ps
CPU time 7.27 seconds
Started Aug 19 04:38:45 PM PDT 24
Finished Aug 19 04:38:53 PM PDT 24
Peak memory 218388 kb
Host smart-06a7cedf-a3db-41c5-a84a-125d225b3af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191020287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3191020287
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3686407947
Short name T81
Test name
Test status
Simulation time 76305879 ps
CPU time 2.91 seconds
Started Aug 19 04:38:47 PM PDT 24
Finished Aug 19 04:38:50 PM PDT 24
Peak memory 217876 kb
Host smart-b11eeb3e-5ed9-4b80-864d-9beefb8fc911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686407947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3686407947
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.243656501
Short name T809
Test name
Test status
Simulation time 225699024 ps
CPU time 31.2 seconds
Started Aug 19 04:38:44 PM PDT 24
Finished Aug 19 04:39:15 PM PDT 24
Peak memory 251020 kb
Host smart-440009a8-5d1f-4ae2-9133-3050b9ed4f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243656501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.243656501
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1607505436
Short name T276
Test name
Test status
Simulation time 47144468 ps
CPU time 2.98 seconds
Started Aug 19 04:38:44 PM PDT 24
Finished Aug 19 04:38:47 PM PDT 24
Peak memory 222340 kb
Host smart-daf8c217-1870-4a29-9766-29816c50a400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607505436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1607505436
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2229529830
Short name T745
Test name
Test status
Simulation time 5356833489 ps
CPU time 35.12 seconds
Started Aug 19 04:38:59 PM PDT 24
Finished Aug 19 04:39:34 PM PDT 24
Peak memory 226184 kb
Host smart-bdb925af-ba0d-4fc8-b55a-8f6863ce7f77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229529830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2229529830
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2005942891
Short name T538
Test name
Test status
Simulation time 1194668564 ps
CPU time 26.22 seconds
Started Aug 19 04:38:55 PM PDT 24
Finished Aug 19 04:39:21 PM PDT 24
Peak memory 226284 kb
Host smart-4d3e5c5e-452e-4884-91e2-b03e7f264fc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2005942891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.2005942891
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3475345998
Short name T493
Test name
Test status
Simulation time 33476507 ps
CPU time 0.77 seconds
Started Aug 19 04:38:44 PM PDT 24
Finished Aug 19 04:38:45 PM PDT 24
Peak memory 208852 kb
Host smart-0fd0936e-9a47-4c61-8ece-77a3603b7da5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475345998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3475345998
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.49905277
Short name T583
Test name
Test status
Simulation time 61655623 ps
CPU time 1.1 seconds
Started Aug 19 04:39:32 PM PDT 24
Finished Aug 19 04:39:33 PM PDT 24
Peak memory 209060 kb
Host smart-be99ddca-4bc7-4950-ab3d-a6d75e0a2948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49905277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.49905277
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3561700473
Short name T49
Test name
Test status
Simulation time 408555115 ps
CPU time 12.36 seconds
Started Aug 19 04:39:37 PM PDT 24
Finished Aug 19 04:39:50 PM PDT 24
Peak memory 218316 kb
Host smart-c246f806-534d-482f-8654-ad5e70be0b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561700473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3561700473
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.749223588
Short name T366
Test name
Test status
Simulation time 6098080123 ps
CPU time 7.61 seconds
Started Aug 19 04:39:32 PM PDT 24
Finished Aug 19 04:39:39 PM PDT 24
Peak memory 217832 kb
Host smart-d4cf8d81-9eda-45f1-9987-739cf2f07258
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749223588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.749223588
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2570426500
Short name T317
Test name
Test status
Simulation time 1296775490 ps
CPU time 37.56 seconds
Started Aug 19 04:39:29 PM PDT 24
Finished Aug 19 04:40:07 PM PDT 24
Peak memory 218312 kb
Host smart-1b3919f1-10d4-4034-98dd-abca5dd903e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570426500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2570426500
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1744096265
Short name T231
Test name
Test status
Simulation time 494851456 ps
CPU time 4.85 seconds
Started Aug 19 04:39:38 PM PDT 24
Finished Aug 19 04:39:43 PM PDT 24
Peak memory 218260 kb
Host smart-83016532-9bf1-4e15-9819-7f2c52f8fb5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744096265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1744096265
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.26503441
Short name T93
Test name
Test status
Simulation time 70750039 ps
CPU time 1.64 seconds
Started Aug 19 04:39:29 PM PDT 24
Finished Aug 19 04:39:31 PM PDT 24
Peak memory 217732 kb
Host smart-d045a59c-fbca-4391-9db7-a01b5b6e4ee9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26503441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.26503441
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3903214191
Short name T303
Test name
Test status
Simulation time 8724053462 ps
CPU time 59.48 seconds
Started Aug 19 04:39:29 PM PDT 24
Finished Aug 19 04:40:28 PM PDT 24
Peak memory 275592 kb
Host smart-df91d896-1800-41be-a3bd-c64c4170c205
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903214191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3903214191
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2829332801
Short name T486
Test name
Test status
Simulation time 1564664546 ps
CPU time 22.87 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:39:48 PM PDT 24
Peak memory 226108 kb
Host smart-288867dc-9997-409e-b821-4c50da74f854
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829332801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2829332801
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.4063187581
Short name T305
Test name
Test status
Simulation time 67151491 ps
CPU time 3.45 seconds
Started Aug 19 04:39:38 PM PDT 24
Finished Aug 19 04:39:42 PM PDT 24
Peak memory 218312 kb
Host smart-24f810c6-c61d-4307-8323-f3ff5a240b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063187581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.4063187581
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2025708972
Short name T357
Test name
Test status
Simulation time 589160328 ps
CPU time 20.31 seconds
Started Aug 19 04:39:29 PM PDT 24
Finished Aug 19 04:39:49 PM PDT 24
Peak memory 220068 kb
Host smart-e76421ad-975b-418e-81c0-0ea825bd985b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025708972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2025708972
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2248233185
Short name T511
Test name
Test status
Simulation time 547154550 ps
CPU time 17.77 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:39:42 PM PDT 24
Peak memory 225944 kb
Host smart-6a6860c9-3886-4f70-be78-459a957dd738
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248233185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.2248233185
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1567945374
Short name T603
Test name
Test status
Simulation time 650139593 ps
CPU time 8.09 seconds
Started Aug 19 04:39:31 PM PDT 24
Finished Aug 19 04:39:39 PM PDT 24
Peak memory 226084 kb
Host smart-71efc7d2-e199-4872-8829-2376514586c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567945374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1567945374
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2564983128
Short name T657
Test name
Test status
Simulation time 455556238 ps
CPU time 10 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:39:35 PM PDT 24
Peak memory 218532 kb
Host smart-3d16a6d2-a541-4d88-9c26-7a666d6e387a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564983128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2564983128
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3056377117
Short name T401
Test name
Test status
Simulation time 52055539 ps
CPU time 1.63 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:39:26 PM PDT 24
Peak memory 217868 kb
Host smart-a60bf63e-bc0e-4c91-a2f2-bd2d43980ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056377117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3056377117
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1940009723
Short name T416
Test name
Test status
Simulation time 1616707923 ps
CPU time 24.46 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:39:48 PM PDT 24
Peak memory 246412 kb
Host smart-87e2d3d3-14a6-4735-8f46-1029b192a052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940009723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1940009723
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.953735520
Short name T384
Test name
Test status
Simulation time 59680177 ps
CPU time 5.87 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:39:32 PM PDT 24
Peak memory 250572 kb
Host smart-306644d5-75c4-4c8f-8d80-3bb2174d9ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953735520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.953735520
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3505700761
Short name T86
Test name
Test status
Simulation time 8983285939 ps
CPU time 131.09 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:41:36 PM PDT 24
Peak memory 283828 kb
Host smart-694bf7e8-a4ed-4425-8466-4cf5fe44c106
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505700761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3505700761
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.4209087835
Short name T358
Test name
Test status
Simulation time 107648400 ps
CPU time 0.84 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:39:25 PM PDT 24
Peak memory 208392 kb
Host smart-48a5f204-6ff5-409d-88d1-bb760bcdc4c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209087835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.4209087835
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3404220311
Short name T348
Test name
Test status
Simulation time 55739094 ps
CPU time 1 seconds
Started Aug 19 04:39:33 PM PDT 24
Finished Aug 19 04:39:34 PM PDT 24
Peak memory 209032 kb
Host smart-9ec1e2b2-e34c-4a2c-b7d2-2354f66b965a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404220311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3404220311
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2809386050
Short name T828
Test name
Test status
Simulation time 1653887858 ps
CPU time 16.81 seconds
Started Aug 19 04:39:28 PM PDT 24
Finished Aug 19 04:39:45 PM PDT 24
Peak memory 218320 kb
Host smart-053c1f9e-c149-4a96-a4d8-9bd1a5690521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809386050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2809386050
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.311825157
Short name T364
Test name
Test status
Simulation time 35164218 ps
CPU time 1.09 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:39:27 PM PDT 24
Peak memory 217656 kb
Host smart-f74e01de-31e9-4fd2-a69e-58b35430bb68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311825157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.311825157
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2127690374
Short name T536
Test name
Test status
Simulation time 8141812733 ps
CPU time 55.99 seconds
Started Aug 19 04:39:37 PM PDT 24
Finished Aug 19 04:40:33 PM PDT 24
Peak memory 218956 kb
Host smart-5c9a7984-1d96-409e-a99e-a130e8bd76d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127690374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2127690374
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2399340170
Short name T597
Test name
Test status
Simulation time 444319142 ps
CPU time 12.89 seconds
Started Aug 19 04:39:38 PM PDT 24
Finished Aug 19 04:39:51 PM PDT 24
Peak memory 218264 kb
Host smart-30b78759-ea99-42e1-bc2b-a4314b19d5c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399340170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2399340170
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2595868800
Short name T175
Test name
Test status
Simulation time 558511793 ps
CPU time 2.64 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:39:27 PM PDT 24
Peak memory 217724 kb
Host smart-cbc47b4d-bea5-457b-a82b-efea3b3365c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595868800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2595868800
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3180873464
Short name T662
Test name
Test status
Simulation time 4661564726 ps
CPU time 56.24 seconds
Started Aug 19 04:39:37 PM PDT 24
Finished Aug 19 04:40:33 PM PDT 24
Peak memory 283404 kb
Host smart-38d9da67-cc53-4b58-b31a-554ac96b6a73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180873464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3180873464
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.925051529
Short name T825
Test name
Test status
Simulation time 777653425 ps
CPU time 10.82 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:39:35 PM PDT 24
Peak memory 249444 kb
Host smart-e982d30a-487c-4a47-ae7c-08967a005f5f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925051529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.925051529
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1295332768
Short name T281
Test name
Test status
Simulation time 182278032 ps
CPU time 3.92 seconds
Started Aug 19 04:39:30 PM PDT 24
Finished Aug 19 04:39:34 PM PDT 24
Peak memory 222712 kb
Host smart-0a610d0d-5c3f-47f8-94f6-5ebdd641e6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295332768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1295332768
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2655934352
Short name T570
Test name
Test status
Simulation time 1292026749 ps
CPU time 9.95 seconds
Started Aug 19 04:39:38 PM PDT 24
Finished Aug 19 04:39:48 PM PDT 24
Peak memory 218964 kb
Host smart-5fc7c4cb-cf62-42f5-8168-22c626ef6073
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655934352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2655934352
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2280538645
Short name T579
Test name
Test status
Simulation time 543416897 ps
CPU time 9.94 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:39:36 PM PDT 24
Peak memory 226076 kb
Host smart-5a689573-5faf-424d-a13a-934e0b709b30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280538645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2280538645
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2095469541
Short name T696
Test name
Test status
Simulation time 205665179 ps
CPU time 5.79 seconds
Started Aug 19 04:39:38 PM PDT 24
Finished Aug 19 04:39:44 PM PDT 24
Peak memory 218268 kb
Host smart-2f58750b-b55c-4a55-8be1-94253593943f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095469541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2095469541
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3585238702
Short name T30
Test name
Test status
Simulation time 299069055 ps
CPU time 7.82 seconds
Started Aug 19 04:39:29 PM PDT 24
Finished Aug 19 04:39:37 PM PDT 24
Peak memory 218428 kb
Host smart-14e8a891-623a-40b2-a612-fd3474c059a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585238702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3585238702
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.258717215
Short name T834
Test name
Test status
Simulation time 28197367 ps
CPU time 1.43 seconds
Started Aug 19 04:39:29 PM PDT 24
Finished Aug 19 04:39:30 PM PDT 24
Peak memory 213944 kb
Host smart-d6c92b22-6870-4589-a7a5-af581526fc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258717215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.258717215
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.4142654605
Short name T345
Test name
Test status
Simulation time 506983882 ps
CPU time 29.23 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:39:56 PM PDT 24
Peak memory 250980 kb
Host smart-473d86f2-c7a6-4281-bfd5-c6f964f9807d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142654605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.4142654605
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1896456539
Short name T671
Test name
Test status
Simulation time 216209714 ps
CPU time 3.94 seconds
Started Aug 19 04:39:23 PM PDT 24
Finished Aug 19 04:39:27 PM PDT 24
Peak memory 222804 kb
Host smart-ae4b0a3f-ebfd-496a-a4fb-80f43b298382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896456539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1896456539
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.1772473472
Short name T156
Test name
Test status
Simulation time 4062828149 ps
CPU time 75.04 seconds
Started Aug 19 04:39:25 PM PDT 24
Finished Aug 19 04:40:40 PM PDT 24
Peak memory 270912 kb
Host smart-48f8587e-a24f-4603-8e63-c40d6162f050
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1772473472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.1772473472
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.773242383
Short name T635
Test name
Test status
Simulation time 33691251 ps
CPU time 0.96 seconds
Started Aug 19 04:39:25 PM PDT 24
Finished Aug 19 04:39:26 PM PDT 24
Peak memory 211984 kb
Host smart-94431615-8c8f-4b98-9713-f0325bddfa88
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773242383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.773242383
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3141187541
Short name T777
Test name
Test status
Simulation time 48403963 ps
CPU time 0.96 seconds
Started Aug 19 04:39:37 PM PDT 24
Finished Aug 19 04:39:38 PM PDT 24
Peak memory 209040 kb
Host smart-4b756545-1c92-4124-a584-6a2721556288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141187541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3141187541
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.967536484
Short name T163
Test name
Test status
Simulation time 1263213508 ps
CPU time 9.14 seconds
Started Aug 19 04:39:41 PM PDT 24
Finished Aug 19 04:39:51 PM PDT 24
Peak memory 218448 kb
Host smart-e68272dc-d3d5-4633-82e0-8e3d3e6337b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967536484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.967536484
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3123681080
Short name T685
Test name
Test status
Simulation time 3491194844 ps
CPU time 42.66 seconds
Started Aug 19 04:39:34 PM PDT 24
Finished Aug 19 04:40:17 PM PDT 24
Peak memory 220408 kb
Host smart-92d21477-8978-4e8e-887d-9691ab5ddbb8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123681080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3123681080
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3425949338
Short name T385
Test name
Test status
Simulation time 3066530321 ps
CPU time 12.45 seconds
Started Aug 19 04:39:35 PM PDT 24
Finished Aug 19 04:39:48 PM PDT 24
Peak memory 224924 kb
Host smart-1dd8b1c9-62dd-4a94-85ad-014c3602a6eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425949338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3425949338
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2196544807
Short name T698
Test name
Test status
Simulation time 765477391 ps
CPU time 11.04 seconds
Started Aug 19 04:39:34 PM PDT 24
Finished Aug 19 04:39:46 PM PDT 24
Peak memory 217708 kb
Host smart-5030380a-8339-46b9-898d-eec5918d1e0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196544807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2196544807
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.326288672
Short name T804
Test name
Test status
Simulation time 10400580667 ps
CPU time 58.77 seconds
Started Aug 19 04:39:33 PM PDT 24
Finished Aug 19 04:40:32 PM PDT 24
Peak memory 275552 kb
Host smart-6cb35c93-6b87-4f23-bac1-88f71b9195ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326288672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.326288672
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3933211268
Short name T747
Test name
Test status
Simulation time 1354722679 ps
CPU time 20.27 seconds
Started Aug 19 04:39:33 PM PDT 24
Finished Aug 19 04:39:54 PM PDT 24
Peak memory 250940 kb
Host smart-43d7eab1-f95e-4d76-91a3-10de672a1cf3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933211268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3933211268
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2256788860
Short name T319
Test name
Test status
Simulation time 105923175 ps
CPU time 2.47 seconds
Started Aug 19 04:39:37 PM PDT 24
Finished Aug 19 04:39:40 PM PDT 24
Peak memory 218316 kb
Host smart-f8ddc742-5640-4a22-ac5d-3796c2b6b44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256788860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2256788860
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2178809023
Short name T637
Test name
Test status
Simulation time 777087254 ps
CPU time 10.84 seconds
Started Aug 19 04:39:35 PM PDT 24
Finished Aug 19 04:39:46 PM PDT 24
Peak memory 218564 kb
Host smart-76ebbc08-9acd-4620-8f6b-25b2239eb9d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178809023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2178809023
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.730801864
Short name T353
Test name
Test status
Simulation time 1161288194 ps
CPU time 17.3 seconds
Started Aug 19 04:39:35 PM PDT 24
Finished Aug 19 04:39:53 PM PDT 24
Peak memory 226064 kb
Host smart-a4db766a-0fd9-47e8-b3a5-e4638c6b4fe9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730801864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.730801864
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3610557787
Short name T182
Test name
Test status
Simulation time 673678590 ps
CPU time 8.81 seconds
Started Aug 19 04:39:36 PM PDT 24
Finished Aug 19 04:39:45 PM PDT 24
Peak memory 218304 kb
Host smart-09a0ff15-0c2e-4569-9029-43be933081cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610557787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3610557787
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2289350087
Short name T467
Test name
Test status
Simulation time 423961035 ps
CPU time 11.13 seconds
Started Aug 19 04:39:37 PM PDT 24
Finished Aug 19 04:39:48 PM PDT 24
Peak memory 218504 kb
Host smart-900ddbe7-03dc-45aa-b35c-b1ae2b534f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289350087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2289350087
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.197911611
Short name T392
Test name
Test status
Simulation time 147863799 ps
CPU time 2.97 seconds
Started Aug 19 04:39:34 PM PDT 24
Finished Aug 19 04:39:37 PM PDT 24
Peak memory 217788 kb
Host smart-e4b6b8ed-91b7-4acc-9146-1436cfa7fc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197911611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.197911611
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.4026908628
Short name T791
Test name
Test status
Simulation time 122063696 ps
CPU time 3.07 seconds
Started Aug 19 04:39:36 PM PDT 24
Finished Aug 19 04:39:39 PM PDT 24
Peak memory 222596 kb
Host smart-9a4e59b7-3b75-498d-8036-f1604f18b42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026908628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.4026908628
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1003896958
Short name T413
Test name
Test status
Simulation time 47670520 ps
CPU time 0.84 seconds
Started Aug 19 04:39:37 PM PDT 24
Finished Aug 19 04:39:38 PM PDT 24
Peak memory 209004 kb
Host smart-3e82bdfd-0175-4d3d-97e7-d84015bbe7ec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003896958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1003896958
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.4086373838
Short name T620
Test name
Test status
Simulation time 17263015 ps
CPU time 1.14 seconds
Started Aug 19 04:39:54 PM PDT 24
Finished Aug 19 04:39:55 PM PDT 24
Peak memory 209104 kb
Host smart-107ef27e-6875-48f0-b84e-87e24d1d5589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086373838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.4086373838
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2753056239
Short name T639
Test name
Test status
Simulation time 442895558 ps
CPU time 14.89 seconds
Started Aug 19 04:39:54 PM PDT 24
Finished Aug 19 04:40:09 PM PDT 24
Peak memory 218356 kb
Host smart-80effc22-b43e-4a28-9053-34a0081fbac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753056239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2753056239
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1295915129
Short name T634
Test name
Test status
Simulation time 1190662947 ps
CPU time 15.22 seconds
Started Aug 19 04:39:54 PM PDT 24
Finished Aug 19 04:40:10 PM PDT 24
Peak memory 217796 kb
Host smart-6eba972b-f4c2-43ac-b07a-25203d85036a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295915129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1295915129
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3601781068
Short name T764
Test name
Test status
Simulation time 1901711699 ps
CPU time 31.73 seconds
Started Aug 19 04:39:54 PM PDT 24
Finished Aug 19 04:40:26 PM PDT 24
Peak memory 218964 kb
Host smart-421a50ea-10ab-4662-8bd4-8199a3a54a55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601781068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3601781068
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2868901452
Short name T649
Test name
Test status
Simulation time 368789104 ps
CPU time 9.97 seconds
Started Aug 19 04:39:51 PM PDT 24
Finished Aug 19 04:40:01 PM PDT 24
Peak memory 222096 kb
Host smart-ae21db6d-356d-427f-81fc-5c7ed1bff097
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868901452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2868901452
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.4099569607
Short name T652
Test name
Test status
Simulation time 497685371 ps
CPU time 6.47 seconds
Started Aug 19 04:39:51 PM PDT 24
Finished Aug 19 04:39:58 PM PDT 24
Peak memory 217704 kb
Host smart-0de74a3e-8f63-4ab2-ad1b-49bf6b02792d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099569607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.4099569607
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2313443439
Short name T318
Test name
Test status
Simulation time 1024108154 ps
CPU time 50.41 seconds
Started Aug 19 04:39:55 PM PDT 24
Finished Aug 19 04:40:45 PM PDT 24
Peak memory 252812 kb
Host smart-a7e0ceb5-5683-4cdb-b6bf-392b80d521d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313443439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2313443439
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.539416690
Short name T410
Test name
Test status
Simulation time 965535780 ps
CPU time 25.26 seconds
Started Aug 19 04:39:55 PM PDT 24
Finished Aug 19 04:40:20 PM PDT 24
Peak memory 250784 kb
Host smart-6f24e57d-4a7c-4988-ac34-045928a8cfa7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539416690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.539416690
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3808627598
Short name T238
Test name
Test status
Simulation time 98987313 ps
CPU time 1.91 seconds
Started Aug 19 04:39:55 PM PDT 24
Finished Aug 19 04:39:57 PM PDT 24
Peak memory 218392 kb
Host smart-7ad4556e-dbe9-407b-890e-ce9b56fd85ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808627598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3808627598
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3072041676
Short name T726
Test name
Test status
Simulation time 351442841 ps
CPU time 16.2 seconds
Started Aug 19 04:39:57 PM PDT 24
Finished Aug 19 04:40:14 PM PDT 24
Peak memory 226188 kb
Host smart-f86577a0-c41d-41c0-bbe2-6cb1660e6207
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072041676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3072041676
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2979907062
Short name T261
Test name
Test status
Simulation time 2678583008 ps
CPU time 13.22 seconds
Started Aug 19 04:39:53 PM PDT 24
Finished Aug 19 04:40:06 PM PDT 24
Peak memory 226148 kb
Host smart-03d48134-578c-4a0c-8495-44fbd6673b81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979907062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2979907062
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1540383523
Short name T296
Test name
Test status
Simulation time 227564496 ps
CPU time 6.42 seconds
Started Aug 19 04:39:51 PM PDT 24
Finished Aug 19 04:39:58 PM PDT 24
Peak memory 218204 kb
Host smart-0ff216ef-a379-4ae7-8aa5-ff93557c0b4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540383523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1540383523
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1864557666
Short name T343
Test name
Test status
Simulation time 370386096 ps
CPU time 9.3 seconds
Started Aug 19 04:39:56 PM PDT 24
Finished Aug 19 04:40:06 PM PDT 24
Peak memory 218408 kb
Host smart-3bf31b1b-60c2-46a2-b1c2-98fb7fad3e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864557666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1864557666
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2458015513
Short name T68
Test name
Test status
Simulation time 29025717 ps
CPU time 2.19 seconds
Started Aug 19 04:39:37 PM PDT 24
Finished Aug 19 04:39:39 PM PDT 24
Peak memory 214076 kb
Host smart-dfe442e1-dcc2-4286-ad05-51859394fd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458015513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2458015513
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1756212617
Short name T280
Test name
Test status
Simulation time 345596308 ps
CPU time 31.48 seconds
Started Aug 19 04:39:38 PM PDT 24
Finished Aug 19 04:40:09 PM PDT 24
Peak memory 250956 kb
Host smart-16b3e640-13c1-4192-a055-4f74fe541fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756212617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1756212617
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3969542295
Short name T795
Test name
Test status
Simulation time 232118346 ps
CPU time 4 seconds
Started Aug 19 04:39:55 PM PDT 24
Finished Aug 19 04:39:59 PM PDT 24
Peak memory 218360 kb
Host smart-39b47c93-c8e0-4f47-bbba-835744782d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969542295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3969542295
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.2426602446
Short name T508
Test name
Test status
Simulation time 27063419688 ps
CPU time 628.93 seconds
Started Aug 19 04:39:55 PM PDT 24
Finished Aug 19 04:50:24 PM PDT 24
Peak memory 278048 kb
Host smart-6524e62c-cde1-467f-8b99-66fca9284364
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426602446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.2426602446
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.849585462
Short name T183
Test name
Test status
Simulation time 25193837 ps
CPU time 1 seconds
Started Aug 19 04:39:33 PM PDT 24
Finished Aug 19 04:39:35 PM PDT 24
Peak memory 212060 kb
Host smart-7dd9fdcd-b1d0-42cd-a042-9e60916601d8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849585462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.849585462
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.4188684651
Short name T99
Test name
Test status
Simulation time 17211397 ps
CPU time 0.86 seconds
Started Aug 19 04:40:02 PM PDT 24
Finished Aug 19 04:40:03 PM PDT 24
Peak memory 208972 kb
Host smart-b21016bf-bc69-46c8-b0c2-31893eba6837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188684651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.4188684651
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2955285285
Short name T53
Test name
Test status
Simulation time 588568458 ps
CPU time 14.18 seconds
Started Aug 19 04:39:57 PM PDT 24
Finished Aug 19 04:40:11 PM PDT 24
Peak memory 218340 kb
Host smart-505a4d1b-a9f0-4def-a4b8-d95ff04be227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955285285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2955285285
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3931915791
Short name T787
Test name
Test status
Simulation time 182706393 ps
CPU time 2.77 seconds
Started Aug 19 04:39:58 PM PDT 24
Finished Aug 19 04:40:01 PM PDT 24
Peak memory 217792 kb
Host smart-a548de7a-801b-4939-aa19-1f01355de220
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931915791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3931915791
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3750358957
Short name T728
Test name
Test status
Simulation time 20070045903 ps
CPU time 61.83 seconds
Started Aug 19 04:39:59 PM PDT 24
Finished Aug 19 04:41:01 PM PDT 24
Peak memory 219012 kb
Host smart-dd260e87-92a4-49d9-bd95-f597fe99ea0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750358957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3750358957
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3011063419
Short name T498
Test name
Test status
Simulation time 3007361578 ps
CPU time 9.39 seconds
Started Aug 19 04:39:55 PM PDT 24
Finished Aug 19 04:40:05 PM PDT 24
Peak memory 218360 kb
Host smart-f56796bc-3b6b-4585-b67c-056477af1a74
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011063419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3011063419
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3222940574
Short name T5
Test name
Test status
Simulation time 142628959 ps
CPU time 4.39 seconds
Started Aug 19 04:39:58 PM PDT 24
Finished Aug 19 04:40:02 PM PDT 24
Peak memory 217692 kb
Host smart-d9f76483-ae33-437c-a363-9f8d7be2b0b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222940574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3222940574
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2385934786
Short name T520
Test name
Test status
Simulation time 19720377150 ps
CPU time 72.11 seconds
Started Aug 19 04:40:00 PM PDT 24
Finished Aug 19 04:41:12 PM PDT 24
Peak memory 267320 kb
Host smart-07d7b940-4ee1-4b36-a16e-0b22310a7821
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385934786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2385934786
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.3821456389
Short name T229
Test name
Test status
Simulation time 494279234 ps
CPU time 18.65 seconds
Started Aug 19 04:39:56 PM PDT 24
Finished Aug 19 04:40:14 PM PDT 24
Peak memory 246292 kb
Host smart-38aa04e2-9a72-4cae-829a-3a94e2ec3258
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821456389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.3821456389
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1465064553
Short name T429
Test name
Test status
Simulation time 92828309 ps
CPU time 2.15 seconds
Started Aug 19 04:39:59 PM PDT 24
Finished Aug 19 04:40:01 PM PDT 24
Peak memory 218364 kb
Host smart-49028a78-ed77-4b4a-bc05-568ca64ec0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465064553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1465064553
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1760411257
Short name T42
Test name
Test status
Simulation time 2057868494 ps
CPU time 12.88 seconds
Started Aug 19 04:40:00 PM PDT 24
Finished Aug 19 04:40:13 PM PDT 24
Peak memory 218508 kb
Host smart-57673b7e-b474-404a-9d60-7b6a5623a166
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760411257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1760411257
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3168830805
Short name T645
Test name
Test status
Simulation time 582019062 ps
CPU time 12.34 seconds
Started Aug 19 04:39:59 PM PDT 24
Finished Aug 19 04:40:11 PM PDT 24
Peak memory 226104 kb
Host smart-5b4cbcf6-4094-4247-b0da-8bc4bbef02d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168830805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3168830805
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.617617242
Short name T235
Test name
Test status
Simulation time 2596423293 ps
CPU time 10.76 seconds
Started Aug 19 04:40:04 PM PDT 24
Finished Aug 19 04:40:15 PM PDT 24
Peak memory 218356 kb
Host smart-fc030bd7-12e7-4e69-8717-d6754851ba51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617617242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.617617242
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2996131160
Short name T708
Test name
Test status
Simulation time 1395774569 ps
CPU time 10.78 seconds
Started Aug 19 04:39:59 PM PDT 24
Finished Aug 19 04:40:10 PM PDT 24
Peak memory 218440 kb
Host smart-0598f9b8-5867-4d5f-a27c-f52c9cc5cc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996131160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2996131160
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2371834546
Short name T670
Test name
Test status
Simulation time 120855166 ps
CPU time 1.59 seconds
Started Aug 19 04:39:59 PM PDT 24
Finished Aug 19 04:40:01 PM PDT 24
Peak memory 217796 kb
Host smart-0d8c2819-cf38-4969-aa84-1c9646d6d232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371834546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2371834546
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3411331870
Short name T286
Test name
Test status
Simulation time 251954962 ps
CPU time 27.89 seconds
Started Aug 19 04:39:59 PM PDT 24
Finished Aug 19 04:40:26 PM PDT 24
Peak memory 251012 kb
Host smart-dabfbeb3-3c54-457f-b354-4fd9fdece7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411331870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3411331870
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.612393874
Short name T858
Test name
Test status
Simulation time 83653488 ps
CPU time 9.77 seconds
Started Aug 19 04:39:57 PM PDT 24
Finished Aug 19 04:40:07 PM PDT 24
Peak memory 243792 kb
Host smart-b6a2a19b-c6fc-4643-be3a-041c332d7223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612393874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.612393874
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.608881
Short name T250
Test name
Test status
Simulation time 23155120490 ps
CPU time 127.43 seconds
Started Aug 19 04:40:01 PM PDT 24
Finished Aug 19 04:42:08 PM PDT 24
Peak memory 226216 kb
Host smart-0a2398c7-0f08-46d5-b408-c1d89d9fcc20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TES
T_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
lc_ctrl_stress_all.608881
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1340829273
Short name T446
Test name
Test status
Simulation time 14317666 ps
CPU time 1.16 seconds
Started Aug 19 04:39:56 PM PDT 24
Finished Aug 19 04:39:57 PM PDT 24
Peak memory 211940 kb
Host smart-f16d838f-1f2d-4366-8bd0-eb9995f55412
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340829273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1340829273
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3450460031
Short name T628
Test name
Test status
Simulation time 150807165 ps
CPU time 1.12 seconds
Started Aug 19 04:40:02 PM PDT 24
Finished Aug 19 04:40:04 PM PDT 24
Peak memory 209196 kb
Host smart-b80a65d4-bdee-4bf7-90fe-982b8c8b6acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450460031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3450460031
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.4002711210
Short name T186
Test name
Test status
Simulation time 519003807 ps
CPU time 8.99 seconds
Started Aug 19 04:40:01 PM PDT 24
Finished Aug 19 04:40:10 PM PDT 24
Peak memory 218336 kb
Host smart-5dbdec49-2012-4d15-92b5-080348aff40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002711210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.4002711210
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1741631157
Short name T615
Test name
Test status
Simulation time 2577273885 ps
CPU time 11.05 seconds
Started Aug 19 04:40:02 PM PDT 24
Finished Aug 19 04:40:13 PM PDT 24
Peak memory 217820 kb
Host smart-3a1bf01a-d49b-4e7d-b2b4-5201d553c22b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741631157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1741631157
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2503095427
Short name T302
Test name
Test status
Simulation time 16687956046 ps
CPU time 35.28 seconds
Started Aug 19 04:40:01 PM PDT 24
Finished Aug 19 04:40:37 PM PDT 24
Peak memory 218824 kb
Host smart-2249de5c-22e6-4e24-bd38-aaf0e2b18f1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503095427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2503095427
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3443061872
Short name T838
Test name
Test status
Simulation time 394149590 ps
CPU time 3.53 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:40:06 PM PDT 24
Peak memory 221788 kb
Host smart-e99da486-1833-4a8c-b974-38b4f1cd0cf5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443061872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3443061872
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3032099569
Short name T786
Test name
Test status
Simulation time 250940235 ps
CPU time 5.49 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:40:08 PM PDT 24
Peak memory 217704 kb
Host smart-3e82aa63-7389-4446-973d-f5c5503a7d5f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032099569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3032099569
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2011620126
Short name T863
Test name
Test status
Simulation time 1027904726 ps
CPU time 47.39 seconds
Started Aug 19 04:40:02 PM PDT 24
Finished Aug 19 04:40:49 PM PDT 24
Peak memory 267344 kb
Host smart-fdf36c19-9567-4d65-a715-6967d6a14104
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011620126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2011620126
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3138308453
Short name T241
Test name
Test status
Simulation time 1627174176 ps
CPU time 16.34 seconds
Started Aug 19 04:40:06 PM PDT 24
Finished Aug 19 04:40:23 PM PDT 24
Peak memory 250936 kb
Host smart-72e1d9af-b336-4080-a51b-84a76a791170
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138308453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3138308453
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3448887442
Short name T70
Test name
Test status
Simulation time 46742961 ps
CPU time 1.72 seconds
Started Aug 19 04:39:59 PM PDT 24
Finished Aug 19 04:40:00 PM PDT 24
Peak memory 218348 kb
Host smart-0dc8a11f-0c0c-4139-bf55-f9ba73536205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448887442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3448887442
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3450698624
Short name T867
Test name
Test status
Simulation time 789552830 ps
CPU time 15.43 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:40:19 PM PDT 24
Peak memory 226172 kb
Host smart-b717b736-5591-48cc-93fa-e4a5385e5948
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450698624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3450698624
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1275999793
Short name T850
Test name
Test status
Simulation time 1058354690 ps
CPU time 7.19 seconds
Started Aug 19 04:40:04 PM PDT 24
Finished Aug 19 04:40:11 PM PDT 24
Peak memory 224888 kb
Host smart-311e6685-3703-425b-adc1-c53d8e831668
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275999793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1275999793
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2118120040
Short name T591
Test name
Test status
Simulation time 409415685 ps
CPU time 9.69 seconds
Started Aug 19 04:40:02 PM PDT 24
Finished Aug 19 04:40:12 PM PDT 24
Peak memory 218524 kb
Host smart-fa5eb7dc-ef9f-4a7d-8722-ff8a24794020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118120040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2118120040
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.4189740424
Short name T262
Test name
Test status
Simulation time 63634028 ps
CPU time 1.31 seconds
Started Aug 19 04:39:57 PM PDT 24
Finished Aug 19 04:39:59 PM PDT 24
Peak memory 217784 kb
Host smart-700bf4f4-aaa0-4636-8cf7-2e0d32ec9e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189740424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.4189740424
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.4018397250
Short name T630
Test name
Test status
Simulation time 360635539 ps
CPU time 28.19 seconds
Started Aug 19 04:40:05 PM PDT 24
Finished Aug 19 04:40:33 PM PDT 24
Peak memory 250640 kb
Host smart-1f3ba4ff-4a53-4b6f-80b9-70d62462fdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018397250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.4018397250
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2241589847
Short name T799
Test name
Test status
Simulation time 213921377 ps
CPU time 7.01 seconds
Started Aug 19 04:40:02 PM PDT 24
Finished Aug 19 04:40:09 PM PDT 24
Peak memory 250380 kb
Host smart-0fb57201-620c-420d-ad19-fb78c0bb5079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241589847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2241589847
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.841516266
Short name T263
Test name
Test status
Simulation time 39653804207 ps
CPU time 105.15 seconds
Started Aug 19 04:40:02 PM PDT 24
Finished Aug 19 04:41:48 PM PDT 24
Peak memory 250988 kb
Host smart-855e943d-e1fd-42dd-9093-fb620ed37a7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841516266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.841516266
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.352604531
Short name T760
Test name
Test status
Simulation time 8805724515 ps
CPU time 66.92 seconds
Started Aug 19 04:40:04 PM PDT 24
Finished Aug 19 04:41:11 PM PDT 24
Peak memory 269008 kb
Host smart-796879fd-8e9b-4728-8d2d-1acb3c668fc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=352604531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.352604531
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.4184936372
Short name T187
Test name
Test status
Simulation time 21506859 ps
CPU time 0.95 seconds
Started Aug 19 04:40:07 PM PDT 24
Finished Aug 19 04:40:08 PM PDT 24
Peak memory 209080 kb
Host smart-891a7f91-4f9a-4936-9e09-c34f3cafb00d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184936372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.4184936372
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3287557748
Short name T753
Test name
Test status
Simulation time 80865811 ps
CPU time 0.99 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:40:04 PM PDT 24
Peak memory 209064 kb
Host smart-f12e402c-b0ff-4b75-ae7e-5248a28b039b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287557748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3287557748
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2705558531
Short name T577
Test name
Test status
Simulation time 355526744 ps
CPU time 10.88 seconds
Started Aug 19 04:40:02 PM PDT 24
Finished Aug 19 04:40:13 PM PDT 24
Peak memory 218348 kb
Host smart-79acecdf-95e8-4408-9a8a-b30afe06eb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705558531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2705558531
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3473591820
Short name T193
Test name
Test status
Simulation time 775110553 ps
CPU time 2.27 seconds
Started Aug 19 04:40:07 PM PDT 24
Finished Aug 19 04:40:09 PM PDT 24
Peak memory 217776 kb
Host smart-6b411a02-dd97-4c90-8ed9-4457cd295295
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473591820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3473591820
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1871147828
Short name T592
Test name
Test status
Simulation time 9501650538 ps
CPU time 56.84 seconds
Started Aug 19 04:40:02 PM PDT 24
Finished Aug 19 04:40:59 PM PDT 24
Peak memory 219032 kb
Host smart-4098b3cc-2ca4-4284-ba6c-dd708205aa06
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871147828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1871147828
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.4274219374
Short name T293
Test name
Test status
Simulation time 548064891 ps
CPU time 13.46 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:40:16 PM PDT 24
Peak memory 217824 kb
Host smart-44c9104f-a581-4468-98e6-eb0a4bad4055
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274219374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.4274219374
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3372332216
Short name T408
Test name
Test status
Simulation time 367309312 ps
CPU time 3.25 seconds
Started Aug 19 04:40:02 PM PDT 24
Finished Aug 19 04:40:06 PM PDT 24
Peak memory 217720 kb
Host smart-5389c37c-490b-4d5c-b375-deab7d550f75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372332216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3372332216
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2670383556
Short name T548
Test name
Test status
Simulation time 1639824780 ps
CPU time 45.64 seconds
Started Aug 19 04:40:02 PM PDT 24
Finished Aug 19 04:40:47 PM PDT 24
Peak memory 275528 kb
Host smart-ce0d346b-459a-4ee8-8763-a5c4ae6366a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670383556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2670383556
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.719237183
Short name T21
Test name
Test status
Simulation time 3924926282 ps
CPU time 20.27 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:40:23 PM PDT 24
Peak memory 250972 kb
Host smart-9b11f9f6-e364-485d-9319-89d3339483b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719237183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.719237183
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1460298754
Short name T816
Test name
Test status
Simulation time 210643959 ps
CPU time 2.41 seconds
Started Aug 19 04:40:00 PM PDT 24
Finished Aug 19 04:40:02 PM PDT 24
Peak memory 218348 kb
Host smart-a78fbf78-d233-45e4-aa08-63d34b9798cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460298754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1460298754
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3721732739
Short name T41
Test name
Test status
Simulation time 1289592079 ps
CPU time 10.36 seconds
Started Aug 19 04:40:05 PM PDT 24
Finished Aug 19 04:40:16 PM PDT 24
Peak memory 226156 kb
Host smart-4a5577c5-9437-4d0e-a9f5-922dba313102
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721732739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3721732739
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3786718831
Short name T818
Test name
Test status
Simulation time 3021384010 ps
CPU time 10.14 seconds
Started Aug 19 04:40:04 PM PDT 24
Finished Aug 19 04:40:15 PM PDT 24
Peak memory 226148 kb
Host smart-175026d8-3c5f-4fa8-ab80-750a1b712d3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786718831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3786718831
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2904967746
Short name T738
Test name
Test status
Simulation time 175250846 ps
CPU time 6.16 seconds
Started Aug 19 04:40:04 PM PDT 24
Finished Aug 19 04:40:10 PM PDT 24
Peak memory 226092 kb
Host smart-fb7dc146-3ff7-402b-aded-d6659f014eca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904967746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2904967746
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.861620463
Short name T684
Test name
Test status
Simulation time 275772929 ps
CPU time 11.62 seconds
Started Aug 19 04:40:05 PM PDT 24
Finished Aug 19 04:40:17 PM PDT 24
Peak memory 218476 kb
Host smart-e27a9c92-ec84-4699-8d78-3460ca580325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861620463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.861620463
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.671639554
Short name T557
Test name
Test status
Simulation time 126311360 ps
CPU time 1.56 seconds
Started Aug 19 04:40:00 PM PDT 24
Finished Aug 19 04:40:02 PM PDT 24
Peak memory 214096 kb
Host smart-4e3b6a8a-a85a-4fb4-ba45-d80ab860556c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671639554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.671639554
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3027404337
Short name T249
Test name
Test status
Simulation time 2208814434 ps
CPU time 21.9 seconds
Started Aug 19 04:40:05 PM PDT 24
Finished Aug 19 04:40:27 PM PDT 24
Peak memory 250676 kb
Host smart-57d869d5-6c9a-4141-b05b-e531e023a0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027404337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3027404337
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1418020729
Short name T228
Test name
Test status
Simulation time 341569870 ps
CPU time 3.61 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:40:07 PM PDT 24
Peak memory 226388 kb
Host smart-25c1b8e7-51d4-4e83-8d1d-b1a1207850d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418020729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1418020729
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1374911980
Short name T52
Test name
Test status
Simulation time 55788975143 ps
CPU time 437.65 seconds
Started Aug 19 04:40:01 PM PDT 24
Finished Aug 19 04:47:19 PM PDT 24
Peak memory 277748 kb
Host smart-c07311de-340c-4754-b3bd-8b76c3b86b01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374911980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1374911980
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2334882194
Short name T812
Test name
Test status
Simulation time 27362147 ps
CPU time 1.02 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:40:04 PM PDT 24
Peak memory 208864 kb
Host smart-5a0ebd1f-f969-4fe3-aeac-8f8bfc53d3f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334882194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2334882194
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1278166883
Short name T669
Test name
Test status
Simulation time 412805268 ps
CPU time 10.41 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:40:13 PM PDT 24
Peak memory 218352 kb
Host smart-fe6c9226-4ec9-4c93-bebe-63a895e6b5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278166883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1278166883
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2031900426
Short name T563
Test name
Test status
Simulation time 158447395 ps
CPU time 2.57 seconds
Started Aug 19 04:40:04 PM PDT 24
Finished Aug 19 04:40:06 PM PDT 24
Peak memory 217752 kb
Host smart-df0493bf-4fcf-4459-95ee-9ac4c771236b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031900426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2031900426
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.436929722
Short name T596
Test name
Test status
Simulation time 1632970503 ps
CPU time 48.54 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:40:52 PM PDT 24
Peak memory 218932 kb
Host smart-37cc9e49-0d25-48ce-8a64-001b47f8b08c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436929722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.436929722
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.495739586
Short name T337
Test name
Test status
Simulation time 6242670783 ps
CPU time 8.2 seconds
Started Aug 19 04:40:11 PM PDT 24
Finished Aug 19 04:40:19 PM PDT 24
Peak memory 218420 kb
Host smart-0ceb168f-7a65-4eb7-8e21-807edbe03766
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495739586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.495739586
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3472182007
Short name T724
Test name
Test status
Simulation time 243313426 ps
CPU time 6.15 seconds
Started Aug 19 04:40:01 PM PDT 24
Finished Aug 19 04:40:07 PM PDT 24
Peak memory 217724 kb
Host smart-c1a22213-88ae-4a92-9f18-ab6efccd1d94
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472182007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3472182007
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.586818267
Short name T756
Test name
Test status
Simulation time 4606326753 ps
CPU time 73.22 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:41:17 PM PDT 24
Peak memory 275536 kb
Host smart-534a5cd7-1043-4ae8-a561-60bac1115a7e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586818267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.586818267
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3485933479
Short name T306
Test name
Test status
Simulation time 921116056 ps
CPU time 30.62 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:40:33 PM PDT 24
Peak memory 250940 kb
Host smart-6c6b072d-9369-4586-b6a7-e57f52d5fe43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485933479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3485933479
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3726329198
Short name T533
Test name
Test status
Simulation time 50835144 ps
CPU time 2.99 seconds
Started Aug 19 04:40:05 PM PDT 24
Finished Aug 19 04:40:08 PM PDT 24
Peak memory 218352 kb
Host smart-3a6dc172-2745-4ae9-ab87-c635988750c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726329198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3726329198
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2284169637
Short name T725
Test name
Test status
Simulation time 1090229453 ps
CPU time 9.2 seconds
Started Aug 19 04:40:07 PM PDT 24
Finished Aug 19 04:40:17 PM PDT 24
Peak memory 219004 kb
Host smart-e12b6ec9-edcc-47e7-9181-3830b508e6e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284169637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2284169637
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1798844940
Short name T180
Test name
Test status
Simulation time 767530344 ps
CPU time 8.24 seconds
Started Aug 19 04:40:06 PM PDT 24
Finished Aug 19 04:40:15 PM PDT 24
Peak memory 226108 kb
Host smart-0b9503ea-92f0-463b-8245-6f465b7ad70f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798844940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1798844940
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2267627291
Short name T788
Test name
Test status
Simulation time 1541435495 ps
CPU time 13.49 seconds
Started Aug 19 04:40:02 PM PDT 24
Finished Aug 19 04:40:16 PM PDT 24
Peak memory 226084 kb
Host smart-9ea542e8-8529-4a0b-a3ff-1570d1f9d73d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267627291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2267627291
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.4053988677
Short name T334
Test name
Test status
Simulation time 1632083175 ps
CPU time 10.01 seconds
Started Aug 19 04:40:06 PM PDT 24
Finished Aug 19 04:40:16 PM PDT 24
Peak memory 218548 kb
Host smart-291c2621-08fc-4b4c-84ea-f5e0c348b2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053988677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.4053988677
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.198675476
Short name T444
Test name
Test status
Simulation time 614474903 ps
CPU time 2.98 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:40:06 PM PDT 24
Peak memory 217768 kb
Host smart-37e76bee-1c44-4ccd-94d6-9dfa7e3e2e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198675476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.198675476
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3436801720
Short name T659
Test name
Test status
Simulation time 1539412593 ps
CPU time 36.24 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:40:39 PM PDT 24
Peak memory 250980 kb
Host smart-afb3d5ce-81dd-4127-bb81-cbcbfdc0cd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436801720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3436801720
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3583930061
Short name T479
Test name
Test status
Simulation time 110024106 ps
CPU time 8.75 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:40:11 PM PDT 24
Peak memory 250592 kb
Host smart-6a5b39ae-a56c-4c9a-a919-9d85040e7099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583930061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3583930061
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.862831748
Short name T507
Test name
Test status
Simulation time 16683465620 ps
CPU time 155.14 seconds
Started Aug 19 04:40:04 PM PDT 24
Finished Aug 19 04:42:39 PM PDT 24
Peak memory 283636 kb
Host smart-af49c2c3-30a1-4b23-ae88-7b0d6c6c2331
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862831748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.862831748
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.2334514032
Short name T173
Test name
Test status
Simulation time 2987898096 ps
CPU time 130.69 seconds
Started Aug 19 04:40:08 PM PDT 24
Finished Aug 19 04:42:18 PM PDT 24
Peak memory 277748 kb
Host smart-3b0a60e3-1472-493b-a335-6b3a269d86b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2334514032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.2334514032
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.4269254765
Short name T91
Test name
Test status
Simulation time 26858148 ps
CPU time 0.89 seconds
Started Aug 19 04:40:06 PM PDT 24
Finished Aug 19 04:40:07 PM PDT 24
Peak memory 212004 kb
Host smart-5f3dafbe-2bb0-44c6-8ed4-16e7350faa51
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269254765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.4269254765
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.4239090736
Short name T623
Test name
Test status
Simulation time 171114500 ps
CPU time 0.93 seconds
Started Aug 19 04:40:08 PM PDT 24
Finished Aug 19 04:40:09 PM PDT 24
Peak memory 208992 kb
Host smart-3376cf15-bb47-4b85-8bfe-4bc05d8d3312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239090736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.4239090736
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.91050320
Short name T853
Test name
Test status
Simulation time 249525908 ps
CPU time 9.64 seconds
Started Aug 19 04:40:07 PM PDT 24
Finished Aug 19 04:40:17 PM PDT 24
Peak memory 218344 kb
Host smart-1340be9f-ccfd-4882-a32e-98c1bf34b09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91050320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.91050320
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2792234877
Short name T785
Test name
Test status
Simulation time 402297539 ps
CPU time 5.16 seconds
Started Aug 19 04:40:08 PM PDT 24
Finished Aug 19 04:40:14 PM PDT 24
Peak memory 217768 kb
Host smart-06917257-8d82-47f5-bf68-6af97cb09c43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792234877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2792234877
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1146074589
Short name T618
Test name
Test status
Simulation time 10940500353 ps
CPU time 73.74 seconds
Started Aug 19 04:40:05 PM PDT 24
Finished Aug 19 04:41:19 PM PDT 24
Peak memory 219016 kb
Host smart-4f46aa10-6afc-4f66-a359-cfe06bbfa09d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146074589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1146074589
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1509744132
Short name T402
Test name
Test status
Simulation time 344153968 ps
CPU time 6.92 seconds
Started Aug 19 04:40:06 PM PDT 24
Finished Aug 19 04:40:13 PM PDT 24
Peak memory 222224 kb
Host smart-10b3030a-7f9c-4caf-9642-f866fab7ef44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509744132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1509744132
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1797227437
Short name T678
Test name
Test status
Simulation time 554775776 ps
CPU time 7.72 seconds
Started Aug 19 04:40:08 PM PDT 24
Finished Aug 19 04:40:16 PM PDT 24
Peak memory 217708 kb
Host smart-399cf61a-d1ab-4656-b400-4f3eac734977
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797227437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1797227437
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.673755399
Short name T414
Test name
Test status
Simulation time 1179267931 ps
CPU time 51.9 seconds
Started Aug 19 04:40:08 PM PDT 24
Finished Aug 19 04:41:00 PM PDT 24
Peak memory 251736 kb
Host smart-4fbaba7e-e37a-4cc0-8cb8-3f00e5a02874
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673755399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.673755399
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.948841252
Short name T174
Test name
Test status
Simulation time 1191584234 ps
CPU time 37.25 seconds
Started Aug 19 04:40:11 PM PDT 24
Finished Aug 19 04:40:48 PM PDT 24
Peak memory 250936 kb
Host smart-655c7f70-dc76-475f-8e30-5f4f9e013a9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948841252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.948841252
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2801143601
Short name T265
Test name
Test status
Simulation time 120758027 ps
CPU time 1.91 seconds
Started Aug 19 04:40:07 PM PDT 24
Finished Aug 19 04:40:09 PM PDT 24
Peak memory 222364 kb
Host smart-c4c46849-837a-4bbe-b7a6-b7db25f40b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801143601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2801143601
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.305819773
Short name T569
Test name
Test status
Simulation time 1639794202 ps
CPU time 19.49 seconds
Started Aug 19 04:40:10 PM PDT 24
Finished Aug 19 04:40:30 PM PDT 24
Peak memory 226176 kb
Host smart-55f2cadf-a589-41a4-b163-1a8b17339205
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305819773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.305819773
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1617971379
Short name T360
Test name
Test status
Simulation time 2032194271 ps
CPU time 13.03 seconds
Started Aug 19 04:40:07 PM PDT 24
Finished Aug 19 04:40:20 PM PDT 24
Peak memory 226108 kb
Host smart-425c1db0-7c25-4477-9bb8-d71b7165eaba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617971379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1617971379
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2611728895
Short name T285
Test name
Test status
Simulation time 2925266299 ps
CPU time 21.22 seconds
Started Aug 19 04:40:10 PM PDT 24
Finished Aug 19 04:40:32 PM PDT 24
Peak memory 226164 kb
Host smart-1b628b3a-0fcd-4b3e-83c6-4f53ecb5c636
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611728895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2611728895
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2117746294
Short name T64
Test name
Test status
Simulation time 358502729 ps
CPU time 13.35 seconds
Started Aug 19 04:40:06 PM PDT 24
Finished Aug 19 04:40:20 PM PDT 24
Peak memory 218424 kb
Host smart-befcff02-2a6b-46fa-beca-407918f946de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117746294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2117746294
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3113155180
Short name T423
Test name
Test status
Simulation time 189791157 ps
CPU time 6.13 seconds
Started Aug 19 04:40:05 PM PDT 24
Finished Aug 19 04:40:11 PM PDT 24
Peak memory 217840 kb
Host smart-df2df251-74d2-4962-be6b-cd01a2c12e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113155180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3113155180
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2625419629
Short name T614
Test name
Test status
Simulation time 196943836 ps
CPU time 19.8 seconds
Started Aug 19 04:40:05 PM PDT 24
Finished Aug 19 04:40:25 PM PDT 24
Peak memory 246036 kb
Host smart-bb8aa53d-debe-4d54-9bc7-bef060676e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625419629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2625419629
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2593742415
Short name T240
Test name
Test status
Simulation time 72249488 ps
CPU time 2.74 seconds
Started Aug 19 04:40:05 PM PDT 24
Finished Aug 19 04:40:08 PM PDT 24
Peak memory 222444 kb
Host smart-ab4815ec-30b5-4bc4-82c0-adcac361e521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593742415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2593742415
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.265490718
Short name T750
Test name
Test status
Simulation time 215626122668 ps
CPU time 889.46 seconds
Started Aug 19 04:40:07 PM PDT 24
Finished Aug 19 04:54:57 PM PDT 24
Peak memory 249816 kb
Host smart-46ad33f7-76ae-4c65-a0ae-f2a4bf755398
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265490718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.265490718
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1092579647
Short name T421
Test name
Test status
Simulation time 14078246 ps
CPU time 0.82 seconds
Started Aug 19 04:40:03 PM PDT 24
Finished Aug 19 04:40:04 PM PDT 24
Peak memory 209196 kb
Host smart-70cbb24a-6c6b-4b5f-b6e3-7066871f4952
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092579647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1092579647
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1108883479
Short name T9
Test name
Test status
Simulation time 17313322 ps
CPU time 0.9 seconds
Started Aug 19 04:40:13 PM PDT 24
Finished Aug 19 04:40:14 PM PDT 24
Peak memory 209056 kb
Host smart-dbef1040-03c6-4de9-b0b8-b0f2a6ca951b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108883479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1108883479
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2583875565
Short name T67
Test name
Test status
Simulation time 1334987648 ps
CPU time 12.5 seconds
Started Aug 19 04:40:10 PM PDT 24
Finished Aug 19 04:40:23 PM PDT 24
Peak memory 218344 kb
Host smart-6cc1ec2f-4630-4ae2-bb89-a89f46ea59d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583875565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2583875565
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.4233611295
Short name T28
Test name
Test status
Simulation time 1820382301 ps
CPU time 2.84 seconds
Started Aug 19 04:40:13 PM PDT 24
Finished Aug 19 04:40:16 PM PDT 24
Peak memory 217720 kb
Host smart-3723d1f9-5fd2-4d9d-84af-fc168cbe6735
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233611295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.4233611295
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.129343433
Short name T97
Test name
Test status
Simulation time 11124924576 ps
CPU time 117.36 seconds
Started Aug 19 04:40:11 PM PDT 24
Finished Aug 19 04:42:08 PM PDT 24
Peak memory 220104 kb
Host smart-b449642c-1f23-4c62-ae40-8c633957964b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129343433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.129343433
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1938839741
Short name T295
Test name
Test status
Simulation time 379189203 ps
CPU time 3.85 seconds
Started Aug 19 04:40:10 PM PDT 24
Finished Aug 19 04:40:14 PM PDT 24
Peak memory 218296 kb
Host smart-c7cd6068-e7de-4c30-b530-62a344c46771
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938839741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1938839741
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.4075397227
Short name T562
Test name
Test status
Simulation time 107089929 ps
CPU time 3.88 seconds
Started Aug 19 04:40:14 PM PDT 24
Finished Aug 19 04:40:18 PM PDT 24
Peak memory 217688 kb
Host smart-88b7f30d-70bc-48bc-94b2-30f32e9a2144
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075397227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.4075397227
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.4088762597
Short name T523
Test name
Test status
Simulation time 5340090588 ps
CPU time 48.94 seconds
Started Aug 19 04:40:11 PM PDT 24
Finished Aug 19 04:41:00 PM PDT 24
Peak memory 252176 kb
Host smart-146f7daa-a294-4347-9525-09ff385b438d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088762597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.4088762597
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.419781806
Short name T746
Test name
Test status
Simulation time 308741588 ps
CPU time 13.96 seconds
Started Aug 19 04:40:13 PM PDT 24
Finished Aug 19 04:40:27 PM PDT 24
Peak memory 250492 kb
Host smart-4f914894-edcc-4602-8755-8ec4c91ba49b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419781806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.419781806
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1552481481
Short name T236
Test name
Test status
Simulation time 231629214 ps
CPU time 2.71 seconds
Started Aug 19 04:40:13 PM PDT 24
Finished Aug 19 04:40:16 PM PDT 24
Peak memory 218304 kb
Host smart-b5f6a23e-cfec-4b00-87a1-42048f7f6829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552481481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1552481481
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1656415056
Short name T239
Test name
Test status
Simulation time 2687188509 ps
CPU time 17.86 seconds
Started Aug 19 04:40:17 PM PDT 24
Finished Aug 19 04:40:35 PM PDT 24
Peak memory 226208 kb
Host smart-9ac2f96f-8d7a-43f0-a376-4908a699cd36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656415056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1656415056
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.404936539
Short name T823
Test name
Test status
Simulation time 2889469242 ps
CPU time 11.65 seconds
Started Aug 19 04:40:11 PM PDT 24
Finished Aug 19 04:40:22 PM PDT 24
Peak memory 226144 kb
Host smart-3ff30c61-ad54-4f6f-979c-da7a892c9d4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404936539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.404936539
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.881455601
Short name T424
Test name
Test status
Simulation time 1769782745 ps
CPU time 7.07 seconds
Started Aug 19 04:40:11 PM PDT 24
Finished Aug 19 04:40:18 PM PDT 24
Peak memory 226228 kb
Host smart-31fed498-bede-4ba8-a6b6-76873c69ca85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881455601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.881455601
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1558717287
Short name T279
Test name
Test status
Simulation time 373304319 ps
CPU time 7.35 seconds
Started Aug 19 04:40:13 PM PDT 24
Finished Aug 19 04:40:20 PM PDT 24
Peak memory 218424 kb
Host smart-93f74716-7895-4fa2-9040-77259e08760c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558717287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1558717287
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.199050546
Short name T34
Test name
Test status
Simulation time 131119246 ps
CPU time 2.4 seconds
Started Aug 19 04:40:09 PM PDT 24
Finished Aug 19 04:40:12 PM PDT 24
Peak memory 214520 kb
Host smart-170492e4-c62c-4d3f-8fbb-5173fd89b47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199050546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.199050546
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1912898194
Short name T253
Test name
Test status
Simulation time 224828414 ps
CPU time 20.35 seconds
Started Aug 19 04:40:10 PM PDT 24
Finished Aug 19 04:40:30 PM PDT 24
Peak memory 250984 kb
Host smart-8a315186-1dcb-4d82-bcae-28a02ee4b7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912898194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1912898194
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3724817672
Short name T313
Test name
Test status
Simulation time 228832177 ps
CPU time 5.81 seconds
Started Aug 19 04:40:11 PM PDT 24
Finished Aug 19 04:40:17 PM PDT 24
Peak memory 244596 kb
Host smart-7b99a6f5-16d0-4656-98f2-2aae9f4d0873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724817672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3724817672
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.49297574
Short name T87
Test name
Test status
Simulation time 3621742444 ps
CPU time 93.42 seconds
Started Aug 19 04:40:11 PM PDT 24
Finished Aug 19 04:41:45 PM PDT 24
Peak memory 226184 kb
Host smart-7a50902a-24a4-427d-92ed-d978a5d34354
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49297574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.lc_ctrl_stress_all.49297574
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2342373152
Short name T813
Test name
Test status
Simulation time 14619932 ps
CPU time 0.96 seconds
Started Aug 19 04:40:08 PM PDT 24
Finished Aug 19 04:40:09 PM PDT 24
Peak memory 209356 kb
Host smart-55ec4d49-e80c-49c3-9aa6-09a71140563b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342373152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2342373152
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2215765687
Short name T465
Test name
Test status
Simulation time 19839184 ps
CPU time 1 seconds
Started Aug 19 04:38:56 PM PDT 24
Finished Aug 19 04:38:57 PM PDT 24
Peak memory 209044 kb
Host smart-3eb6adeb-4dd4-4e3e-86d7-f0f06f9e7d6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215765687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2215765687
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1398281222
Short name T602
Test name
Test status
Simulation time 233894410 ps
CPU time 9.75 seconds
Started Aug 19 04:38:56 PM PDT 24
Finished Aug 19 04:39:05 PM PDT 24
Peak memory 218276 kb
Host smart-6f7c8ce8-386f-4b08-b0d5-be01bb07ab69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398281222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1398281222
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3877124814
Short name T811
Test name
Test status
Simulation time 718313663 ps
CPU time 17.6 seconds
Started Aug 19 04:38:53 PM PDT 24
Finished Aug 19 04:39:11 PM PDT 24
Peak memory 217776 kb
Host smart-f08a77fb-2838-43b7-9d09-d2391f4a0e5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877124814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3877124814
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2714008122
Short name T359
Test name
Test status
Simulation time 2236673543 ps
CPU time 18.45 seconds
Started Aug 19 04:38:57 PM PDT 24
Finished Aug 19 04:39:16 PM PDT 24
Peak memory 218972 kb
Host smart-fe8f60c6-e3ab-43e4-84b3-912ca23d73a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714008122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2714008122
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2839724841
Short name T549
Test name
Test status
Simulation time 869348090 ps
CPU time 2.79 seconds
Started Aug 19 04:38:53 PM PDT 24
Finished Aug 19 04:38:56 PM PDT 24
Peak memory 217840 kb
Host smart-4a23d401-a6a0-4ded-b66d-79b1f1741a8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839724841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
839724841
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2480141995
Short name T437
Test name
Test status
Simulation time 151138514 ps
CPU time 5.19 seconds
Started Aug 19 04:38:54 PM PDT 24
Finished Aug 19 04:39:00 PM PDT 24
Peak memory 218252 kb
Host smart-979c54f3-f80f-411b-b160-3d2aaf731510
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480141995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2480141995
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.4251636967
Short name T574
Test name
Test status
Simulation time 2576266833 ps
CPU time 10.44 seconds
Started Aug 19 04:38:55 PM PDT 24
Finished Aug 19 04:39:06 PM PDT 24
Peak memory 217764 kb
Host smart-7f376920-6c11-49f7-b307-8c43abccd2ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251636967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.4251636967
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1607039987
Short name T706
Test name
Test status
Simulation time 248005191 ps
CPU time 2.38 seconds
Started Aug 19 04:38:53 PM PDT 24
Finished Aug 19 04:38:55 PM PDT 24
Peak memory 217704 kb
Host smart-0d86d4e1-8e9d-4fac-8d5a-6f16297b34fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607039987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1607039987
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.867955655
Short name T449
Test name
Test status
Simulation time 4684677486 ps
CPU time 32.65 seconds
Started Aug 19 04:38:56 PM PDT 24
Finished Aug 19 04:39:29 PM PDT 24
Peak memory 250976 kb
Host smart-e8df27b1-ae87-4c4d-b8c6-36d481993327
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867955655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.867955655
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1245212228
Short name T666
Test name
Test status
Simulation time 1596841517 ps
CPU time 22.18 seconds
Started Aug 19 04:38:55 PM PDT 24
Finished Aug 19 04:39:17 PM PDT 24
Peak memory 224144 kb
Host smart-90b8d05c-52a3-41c6-bda0-c7437a190c22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245212228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1245212228
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1162227723
Short name T727
Test name
Test status
Simulation time 41432094 ps
CPU time 2.3 seconds
Started Aug 19 04:38:53 PM PDT 24
Finished Aug 19 04:38:55 PM PDT 24
Peak memory 222444 kb
Host smart-abe1c47c-b156-4562-9821-6faa63d5c604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162227723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1162227723
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2817266732
Short name T854
Test name
Test status
Simulation time 1029806065 ps
CPU time 17.31 seconds
Started Aug 19 04:38:55 PM PDT 24
Finished Aug 19 04:39:12 PM PDT 24
Peak memory 214792 kb
Host smart-142b23f6-17d0-4966-83c1-3fd6c213960d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817266732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2817266732
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1624126151
Short name T63
Test name
Test status
Simulation time 222704694 ps
CPU time 35.89 seconds
Started Aug 19 04:38:59 PM PDT 24
Finished Aug 19 04:39:35 PM PDT 24
Peak memory 282296 kb
Host smart-e5a0f856-7979-47bd-aaf9-fd5598778562
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624126151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1624126151
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.568753608
Short name T51
Test name
Test status
Simulation time 749132732 ps
CPU time 15.27 seconds
Started Aug 19 04:38:55 PM PDT 24
Finished Aug 19 04:39:10 PM PDT 24
Peak memory 225932 kb
Host smart-2c7eb761-cf1b-4401-9997-e366f18a2f1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568753608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.568753608
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.4087614325
Short name T387
Test name
Test status
Simulation time 916620132 ps
CPU time 8.82 seconds
Started Aug 19 04:38:56 PM PDT 24
Finished Aug 19 04:39:04 PM PDT 24
Peak memory 226084 kb
Host smart-3bcaf7f2-c33b-4175-9715-e4d82e4d0b3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087614325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.4087614325
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.4123090112
Short name T564
Test name
Test status
Simulation time 1795330152 ps
CPU time 9.1 seconds
Started Aug 19 04:38:57 PM PDT 24
Finished Aug 19 04:39:06 PM PDT 24
Peak memory 218312 kb
Host smart-3709453d-4dce-4855-a410-38d0f85f8ee8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123090112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.4
123090112
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.95483098
Short name T324
Test name
Test status
Simulation time 2298795372 ps
CPU time 7.85 seconds
Started Aug 19 04:39:00 PM PDT 24
Finished Aug 19 04:39:08 PM PDT 24
Peak memory 226224 kb
Host smart-a5311b91-0a76-40b0-b1e9-d26c6df4778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95483098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.95483098
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.304330117
Short name T701
Test name
Test status
Simulation time 71747460 ps
CPU time 3.92 seconds
Started Aug 19 04:38:54 PM PDT 24
Finished Aug 19 04:38:58 PM PDT 24
Peak memory 217848 kb
Host smart-8ea87be1-6e28-4882-b074-f426dbf8018c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304330117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.304330117
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1462026110
Short name T489
Test name
Test status
Simulation time 1393893630 ps
CPU time 21.85 seconds
Started Aug 19 04:38:56 PM PDT 24
Finished Aug 19 04:39:18 PM PDT 24
Peak memory 245660 kb
Host smart-cbe6bbe5-f1c4-4490-ab4f-fcea451cd8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462026110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1462026110
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2026229484
Short name T259
Test name
Test status
Simulation time 85983435 ps
CPU time 3.02 seconds
Started Aug 19 04:38:53 PM PDT 24
Finished Aug 19 04:38:56 PM PDT 24
Peak memory 226148 kb
Host smart-f77b6de8-4b28-4af4-a01b-aa13f9f6899d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026229484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2026229484
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2180855909
Short name T503
Test name
Test status
Simulation time 9078223511 ps
CPU time 99.3 seconds
Started Aug 19 04:40:18 PM PDT 24
Finished Aug 19 04:41:57 PM PDT 24
Peak memory 273880 kb
Host smart-4301c237-100f-4686-83a6-3235814d848e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180855909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2180855909
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2825154527
Short name T656
Test name
Test status
Simulation time 4798661017 ps
CPU time 182.16 seconds
Started Aug 19 04:40:18 PM PDT 24
Finished Aug 19 04:43:20 PM PDT 24
Peak memory 277808 kb
Host smart-874e4414-31c7-4670-886f-63ef12e534e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2825154527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.2825154527
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2919119499
Short name T852
Test name
Test status
Simulation time 12968026 ps
CPU time 0.84 seconds
Started Aug 19 04:38:56 PM PDT 24
Finished Aug 19 04:38:57 PM PDT 24
Peak memory 209016 kb
Host smart-d535f2e5-8bdb-46dd-a275-513081c0e4de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919119499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2919119499
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.4046908339
Short name T797
Test name
Test status
Simulation time 23027261 ps
CPU time 1.18 seconds
Started Aug 19 04:40:14 PM PDT 24
Finished Aug 19 04:40:16 PM PDT 24
Peak memory 209036 kb
Host smart-4f20087c-fd62-451e-b984-6fd4ac973cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046908339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.4046908339
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.4103494852
Short name T648
Test name
Test status
Simulation time 1037119893 ps
CPU time 8.64 seconds
Started Aug 19 04:40:14 PM PDT 24
Finished Aug 19 04:40:23 PM PDT 24
Peak memory 218312 kb
Host smart-b05e6b10-ad99-40e6-b029-a3f8037b2d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103494852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.4103494852
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3687392668
Short name T626
Test name
Test status
Simulation time 268638254 ps
CPU time 6.88 seconds
Started Aug 19 04:40:09 PM PDT 24
Finished Aug 19 04:40:16 PM PDT 24
Peak memory 217784 kb
Host smart-dd617d36-5451-4759-96a4-093cb1b2a5bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687392668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3687392668
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.4174895119
Short name T485
Test name
Test status
Simulation time 212172348 ps
CPU time 2.97 seconds
Started Aug 19 04:40:16 PM PDT 24
Finished Aug 19 04:40:19 PM PDT 24
Peak memory 218332 kb
Host smart-520ec9aa-6bf0-456f-a9c1-817eb3971901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174895119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.4174895119
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.990019393
Short name T161
Test name
Test status
Simulation time 408432415 ps
CPU time 16.58 seconds
Started Aug 19 04:40:13 PM PDT 24
Finished Aug 19 04:40:30 PM PDT 24
Peak memory 219004 kb
Host smart-7eba37a9-0564-41ab-b1b4-d8e8092d0324
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990019393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.990019393
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.144089311
Short name T609
Test name
Test status
Simulation time 426516905 ps
CPU time 9.25 seconds
Started Aug 19 04:40:17 PM PDT 24
Finished Aug 19 04:40:26 PM PDT 24
Peak memory 226068 kb
Host smart-4481dcb8-67a5-421b-bb63-fcf8ba57782d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144089311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.144089311
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3673182022
Short name T233
Test name
Test status
Simulation time 843221501 ps
CPU time 14.91 seconds
Started Aug 19 04:40:14 PM PDT 24
Finished Aug 19 04:40:29 PM PDT 24
Peak memory 218324 kb
Host smart-3fdbdc9b-1c8b-4755-8b96-598815e661e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673182022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3673182022
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3017896987
Short name T434
Test name
Test status
Simulation time 494479945 ps
CPU time 8.72 seconds
Started Aug 19 04:40:13 PM PDT 24
Finished Aug 19 04:40:21 PM PDT 24
Peak memory 218420 kb
Host smart-bcf9266f-1bdd-4afc-aded-ccb9944183ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017896987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3017896987
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2591392772
Short name T542
Test name
Test status
Simulation time 238152259 ps
CPU time 2.05 seconds
Started Aug 19 04:40:12 PM PDT 24
Finished Aug 19 04:40:15 PM PDT 24
Peak memory 217768 kb
Host smart-33a60724-b2bc-45eb-b9ed-d20669d866db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591392772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2591392772
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1600678027
Short name T721
Test name
Test status
Simulation time 177085648 ps
CPU time 15.81 seconds
Started Aug 19 04:40:15 PM PDT 24
Finished Aug 19 04:40:31 PM PDT 24
Peak memory 244728 kb
Host smart-af1c764b-acd7-4251-81d4-75bf19bea97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600678027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1600678027
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1026999397
Short name T749
Test name
Test status
Simulation time 187348759 ps
CPU time 9.04 seconds
Started Aug 19 04:40:13 PM PDT 24
Finished Aug 19 04:40:22 PM PDT 24
Peak memory 250928 kb
Host smart-13ce07d4-95fa-4544-923f-67eeab44ff0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026999397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1026999397
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.3322893337
Short name T150
Test name
Test status
Simulation time 10353145927 ps
CPU time 135.63 seconds
Started Aug 19 04:40:15 PM PDT 24
Finished Aug 19 04:42:30 PM PDT 24
Peak memory 257240 kb
Host smart-29995290-b883-4ef9-a204-64846487d637
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3322893337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.3322893337
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1216057655
Short name T37
Test name
Test status
Simulation time 13265816 ps
CPU time 0.91 seconds
Started Aug 19 04:40:13 PM PDT 24
Finished Aug 19 04:40:14 PM PDT 24
Peak memory 212076 kb
Host smart-d392e97b-06e9-47b0-8793-ea8009852fc9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216057655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1216057655
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2403986429
Short name T181
Test name
Test status
Simulation time 118402575 ps
CPU time 1.19 seconds
Started Aug 19 04:40:15 PM PDT 24
Finished Aug 19 04:40:16 PM PDT 24
Peak memory 209112 kb
Host smart-e3c9186f-de1e-40ac-9c3b-4ea3a00e30cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403986429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2403986429
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.4015293624
Short name T438
Test name
Test status
Simulation time 1049725976 ps
CPU time 9.53 seconds
Started Aug 19 04:40:15 PM PDT 24
Finished Aug 19 04:40:25 PM PDT 24
Peak memory 218360 kb
Host smart-02ef28a6-8461-4b39-8335-a0d85b87edff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015293624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.4015293624
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3460982277
Short name T471
Test name
Test status
Simulation time 12796750608 ps
CPU time 9.27 seconds
Started Aug 19 04:40:18 PM PDT 24
Finished Aug 19 04:40:27 PM PDT 24
Peak memory 217832 kb
Host smart-b1eeab53-92b0-4e67-b959-01e32a261b28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460982277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3460982277
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.956242477
Short name T773
Test name
Test status
Simulation time 139358173 ps
CPU time 4.4 seconds
Started Aug 19 04:40:13 PM PDT 24
Finished Aug 19 04:40:18 PM PDT 24
Peak memory 218344 kb
Host smart-4c111110-414a-4cdf-bf2c-687da1b50ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956242477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.956242477
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.4136575481
Short name T588
Test name
Test status
Simulation time 1603377084 ps
CPU time 16.43 seconds
Started Aug 19 04:40:13 PM PDT 24
Finished Aug 19 04:40:29 PM PDT 24
Peak memory 219012 kb
Host smart-1ee0eabd-0971-4723-9a5f-ffbf3a7f1c11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136575481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.4136575481
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1197835403
Short name T383
Test name
Test status
Simulation time 462078655 ps
CPU time 9.4 seconds
Started Aug 19 04:40:13 PM PDT 24
Finished Aug 19 04:40:22 PM PDT 24
Peak memory 226080 kb
Host smart-ace3f2e9-5286-4f0b-9957-5b3e453137d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197835403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1197835403
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3180032408
Short name T66
Test name
Test status
Simulation time 1511785046 ps
CPU time 9.22 seconds
Started Aug 19 04:40:14 PM PDT 24
Finished Aug 19 04:40:24 PM PDT 24
Peak memory 226080 kb
Host smart-52293ee7-b1ed-4f94-8ea7-c55fb3f58a80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180032408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3180032408
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1696215459
Short name T495
Test name
Test status
Simulation time 451162065 ps
CPU time 7.08 seconds
Started Aug 19 04:40:14 PM PDT 24
Finished Aug 19 04:40:21 PM PDT 24
Peak memory 218372 kb
Host smart-e19ea62f-4fa5-44b6-9ec7-acd73dc716dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696215459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1696215459
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1112138220
Short name T314
Test name
Test status
Simulation time 134969664 ps
CPU time 2.45 seconds
Started Aug 19 04:40:14 PM PDT 24
Finished Aug 19 04:40:17 PM PDT 24
Peak memory 217796 kb
Host smart-a7a38a44-d5fa-4a7e-83c1-92f224cc9272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112138220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1112138220
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2875755222
Short name T751
Test name
Test status
Simulation time 1193977357 ps
CPU time 29.04 seconds
Started Aug 19 04:40:16 PM PDT 24
Finished Aug 19 04:40:46 PM PDT 24
Peak memory 251080 kb
Host smart-02859006-b668-4866-8837-b44c5927df9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875755222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2875755222
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2026589881
Short name T840
Test name
Test status
Simulation time 101316748 ps
CPU time 7.46 seconds
Started Aug 19 04:40:15 PM PDT 24
Finished Aug 19 04:40:23 PM PDT 24
Peak memory 250992 kb
Host smart-3f4a5e99-ac22-4069-89f0-82e207f1dcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026589881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2026589881
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2094141125
Short name T831
Test name
Test status
Simulation time 60911888333 ps
CPU time 143.2 seconds
Started Aug 19 04:40:17 PM PDT 24
Finished Aug 19 04:42:40 PM PDT 24
Peak memory 283888 kb
Host smart-5cdeca29-c442-4ebb-a52b-7b4cd057c7ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094141125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2094141125
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1107728267
Short name T526
Test name
Test status
Simulation time 27767155 ps
CPU time 0.89 seconds
Started Aug 19 04:40:17 PM PDT 24
Finished Aug 19 04:40:18 PM PDT 24
Peak memory 209084 kb
Host smart-0e786f53-958c-418a-bf21-948176567106
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107728267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1107728267
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3264054747
Short name T83
Test name
Test status
Simulation time 96806043 ps
CPU time 0.94 seconds
Started Aug 19 04:40:13 PM PDT 24
Finished Aug 19 04:40:14 PM PDT 24
Peak memory 209084 kb
Host smart-ea7aa6d8-0cf1-4769-ae8c-4deffd46f08c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264054747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3264054747
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1550336588
Short name T342
Test name
Test status
Simulation time 1358640843 ps
CPU time 11.55 seconds
Started Aug 19 04:40:18 PM PDT 24
Finished Aug 19 04:40:29 PM PDT 24
Peak memory 226176 kb
Host smart-3944084c-4e65-4346-9ff5-6abb586d8f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550336588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1550336588
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3562542736
Short name T762
Test name
Test status
Simulation time 7078925059 ps
CPU time 12.22 seconds
Started Aug 19 04:40:14 PM PDT 24
Finished Aug 19 04:40:27 PM PDT 24
Peak memory 217908 kb
Host smart-6f1aae87-aaea-4483-9308-08a6a739a803
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562542736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3562542736
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.383665367
Short name T257
Test name
Test status
Simulation time 46781338 ps
CPU time 2.89 seconds
Started Aug 19 04:40:13 PM PDT 24
Finished Aug 19 04:40:16 PM PDT 24
Peak memory 222340 kb
Host smart-7723407f-5dac-40d8-9c2b-bb55685f3111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383665367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.383665367
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3939506868
Short name T266
Test name
Test status
Simulation time 610957415 ps
CPU time 13.28 seconds
Started Aug 19 04:40:14 PM PDT 24
Finished Aug 19 04:40:28 PM PDT 24
Peak memory 219056 kb
Host smart-e66ab9da-4a8e-4ffd-9d13-a365f6b06c70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939506868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3939506868
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1448573004
Short name T248
Test name
Test status
Simulation time 1417691918 ps
CPU time 21.99 seconds
Started Aug 19 04:40:09 PM PDT 24
Finished Aug 19 04:40:31 PM PDT 24
Peak memory 226088 kb
Host smart-4824930f-4f82-4958-8ab5-e935cf5ce405
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448573004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1448573004
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3564612011
Short name T519
Test name
Test status
Simulation time 489255772 ps
CPU time 8.99 seconds
Started Aug 19 04:40:17 PM PDT 24
Finished Aug 19 04:40:26 PM PDT 24
Peak memory 218324 kb
Host smart-b805fa55-2dff-409c-89fa-ef28420671b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564612011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3564612011
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.622633417
Short name T803
Test name
Test status
Simulation time 954642956 ps
CPU time 6.2 seconds
Started Aug 19 04:40:10 PM PDT 24
Finished Aug 19 04:40:17 PM PDT 24
Peak memory 218420 kb
Host smart-5280de02-5b2a-4725-9859-ce1a9872b121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622633417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.622633417
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3671573397
Short name T398
Test name
Test status
Simulation time 51472332 ps
CPU time 3.43 seconds
Started Aug 19 04:40:14 PM PDT 24
Finished Aug 19 04:40:18 PM PDT 24
Peak memory 217768 kb
Host smart-37285650-b299-45ab-b0cf-90b5e9088d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671573397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3671573397
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.244700449
Short name T415
Test name
Test status
Simulation time 120193762 ps
CPU time 6.99 seconds
Started Aug 19 04:40:16 PM PDT 24
Finished Aug 19 04:40:23 PM PDT 24
Peak memory 246772 kb
Host smart-aea9d74c-bc71-46b7-a36f-2c1652e98313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244700449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.244700449
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.704338629
Short name T215
Test name
Test status
Simulation time 6544807849 ps
CPU time 163.91 seconds
Started Aug 19 04:40:17 PM PDT 24
Finished Aug 19 04:43:01 PM PDT 24
Peak memory 275128 kb
Host smart-68f3319c-93f7-4e34-a62d-784c48638b5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704338629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.704338629
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.894583337
Short name T155
Test name
Test status
Simulation time 1513781797 ps
CPU time 38.84 seconds
Started Aug 19 04:40:15 PM PDT 24
Finished Aug 19 04:40:54 PM PDT 24
Peak memory 275732 kb
Host smart-9bc9b3f2-06d9-4c59-8ba6-85ed846ca413
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=894583337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.894583337
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3757197430
Short name T719
Test name
Test status
Simulation time 13205048 ps
CPU time 1.07 seconds
Started Aug 19 04:40:14 PM PDT 24
Finished Aug 19 04:40:15 PM PDT 24
Peak memory 211984 kb
Host smart-ef199a65-ceab-4eaf-909d-d2746f915a53
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757197430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3757197430
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1065220250
Short name T77
Test name
Test status
Simulation time 24158454 ps
CPU time 1.05 seconds
Started Aug 19 04:40:25 PM PDT 24
Finished Aug 19 04:40:26 PM PDT 24
Peak memory 208988 kb
Host smart-05c31184-17f0-4d28-b422-77f67cba1598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065220250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1065220250
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1224791354
Short name T325
Test name
Test status
Simulation time 586596404 ps
CPU time 18.15 seconds
Started Aug 19 04:40:27 PM PDT 24
Finished Aug 19 04:40:45 PM PDT 24
Peak memory 218384 kb
Host smart-732d3aaf-ce04-4515-ad91-ed4a17098d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224791354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1224791354
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3948928385
Short name T380
Test name
Test status
Simulation time 188839669 ps
CPU time 2.6 seconds
Started Aug 19 04:40:24 PM PDT 24
Finished Aug 19 04:40:27 PM PDT 24
Peak memory 217232 kb
Host smart-ae1b87bc-eeee-4328-98eb-6ef516f271a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948928385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3948928385
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.598355902
Short name T843
Test name
Test status
Simulation time 175036909 ps
CPU time 2.71 seconds
Started Aug 19 04:40:18 PM PDT 24
Finished Aug 19 04:40:21 PM PDT 24
Peak memory 222484 kb
Host smart-18d9917a-2721-4b9b-952a-875af8739b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598355902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.598355902
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3533801810
Short name T474
Test name
Test status
Simulation time 273774474 ps
CPU time 13.01 seconds
Started Aug 19 04:40:25 PM PDT 24
Finished Aug 19 04:40:38 PM PDT 24
Peak memory 226264 kb
Host smart-4e134dd9-16ec-4311-8ce5-a33b53be5594
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533801810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3533801810
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3500543586
Short name T800
Test name
Test status
Simulation time 259189892 ps
CPU time 7.3 seconds
Started Aug 19 04:40:17 PM PDT 24
Finished Aug 19 04:40:24 PM PDT 24
Peak memory 226080 kb
Host smart-7575f9c3-7005-4a8f-9bd5-3007725656e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500543586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3500543586
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3440554093
Short name T57
Test name
Test status
Simulation time 573237300 ps
CPU time 10.24 seconds
Started Aug 19 04:40:32 PM PDT 24
Finished Aug 19 04:40:43 PM PDT 24
Peak memory 218280 kb
Host smart-73ba1a60-d601-4424-bca1-fba69ef35ffd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440554093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3440554093
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2569602771
Short name T311
Test name
Test status
Simulation time 522274130 ps
CPU time 9.44 seconds
Started Aug 19 04:40:23 PM PDT 24
Finished Aug 19 04:40:33 PM PDT 24
Peak memory 218440 kb
Host smart-0ff515d5-10e2-476a-bc44-6ca8832a5eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569602771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2569602771
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1442259300
Short name T107
Test name
Test status
Simulation time 693790578 ps
CPU time 2.81 seconds
Started Aug 19 04:40:12 PM PDT 24
Finished Aug 19 04:40:15 PM PDT 24
Peak memory 214536 kb
Host smart-810039bb-46ab-43e8-b04f-39571e95e76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442259300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1442259300
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3192830490
Short name T554
Test name
Test status
Simulation time 2971927493 ps
CPU time 25.36 seconds
Started Aug 19 04:40:10 PM PDT 24
Finished Aug 19 04:40:35 PM PDT 24
Peak memory 251052 kb
Host smart-1f9e2ce1-7359-4d05-b117-ceda92ae7747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192830490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3192830490
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.1929360504
Short name T599
Test name
Test status
Simulation time 176457177 ps
CPU time 6.74 seconds
Started Aug 19 04:40:12 PM PDT 24
Finished Aug 19 04:40:19 PM PDT 24
Peak memory 242760 kb
Host smart-861da8da-4e56-49b6-acf0-542a45e708b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929360504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1929360504
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1199224440
Short name T761
Test name
Test status
Simulation time 5695817757 ps
CPU time 122.23 seconds
Started Aug 19 04:40:25 PM PDT 24
Finished Aug 19 04:42:27 PM PDT 24
Peak memory 260964 kb
Host smart-d7c12b7e-4383-423e-b328-9c8761c0317d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199224440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1199224440
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3569281819
Short name T741
Test name
Test status
Simulation time 13684736 ps
CPU time 0.93 seconds
Started Aug 19 04:40:14 PM PDT 24
Finished Aug 19 04:40:15 PM PDT 24
Peak memory 209100 kb
Host smart-7f49156d-ef3a-4d26-8e06-4cd47401fa7c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569281819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3569281819
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.4073906379
Short name T339
Test name
Test status
Simulation time 21779594 ps
CPU time 0.96 seconds
Started Aug 19 04:40:27 PM PDT 24
Finished Aug 19 04:40:28 PM PDT 24
Peak memory 209012 kb
Host smart-6080c2fe-ac3c-4efc-b31a-4a987810240f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073906379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.4073906379
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.421711723
Short name T675
Test name
Test status
Simulation time 1058199805 ps
CPU time 11.07 seconds
Started Aug 19 04:40:18 PM PDT 24
Finished Aug 19 04:40:29 PM PDT 24
Peak memory 218384 kb
Host smart-82760e2c-80a3-405b-b45e-51d4640b0224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421711723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.421711723
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2239804487
Short name T580
Test name
Test status
Simulation time 2009424096 ps
CPU time 6.14 seconds
Started Aug 19 04:40:27 PM PDT 24
Finished Aug 19 04:40:33 PM PDT 24
Peak memory 217772 kb
Host smart-5d50352b-4f3c-4be8-90c5-1a2c817f998c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239804487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2239804487
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2993217726
Short name T543
Test name
Test status
Simulation time 184219137 ps
CPU time 4.01 seconds
Started Aug 19 04:40:24 PM PDT 24
Finished Aug 19 04:40:28 PM PDT 24
Peak memory 218356 kb
Host smart-c9ed574a-59f5-433c-b2d3-f1a3866fdcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993217726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2993217726
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1705487039
Short name T352
Test name
Test status
Simulation time 1007348244 ps
CPU time 13.14 seconds
Started Aug 19 04:40:32 PM PDT 24
Finished Aug 19 04:40:45 PM PDT 24
Peak memory 218984 kb
Host smart-b43e94b7-ea2d-455a-af5b-c51b9d13b2ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705487039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1705487039
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3110341895
Short name T188
Test name
Test status
Simulation time 381828979 ps
CPU time 11.75 seconds
Started Aug 19 04:40:21 PM PDT 24
Finished Aug 19 04:40:33 PM PDT 24
Peak memory 226120 kb
Host smart-28c5d116-a5fe-48ec-ba82-9ea3421c18c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110341895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3110341895
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2256820001
Short name T388
Test name
Test status
Simulation time 633754170 ps
CPU time 9.37 seconds
Started Aug 19 04:40:21 PM PDT 24
Finished Aug 19 04:40:30 PM PDT 24
Peak memory 218272 kb
Host smart-6edd07aa-e74b-48da-a934-1449df7d8da9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256820001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2256820001
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2869415006
Short name T478
Test name
Test status
Simulation time 3549361406 ps
CPU time 11.63 seconds
Started Aug 19 04:40:22 PM PDT 24
Finished Aug 19 04:40:34 PM PDT 24
Peak memory 218496 kb
Host smart-0a98ab52-0c83-4159-8427-f83d55d24e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869415006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2869415006
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2869755934
Short name T601
Test name
Test status
Simulation time 135244678 ps
CPU time 5.13 seconds
Started Aug 19 04:40:27 PM PDT 24
Finished Aug 19 04:40:32 PM PDT 24
Peak memory 217796 kb
Host smart-fbba752f-25e1-46c3-9759-7b5e1514ae52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869755934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2869755934
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.65781060
Short name T428
Test name
Test status
Simulation time 222324568 ps
CPU time 17.24 seconds
Started Aug 19 04:40:24 PM PDT 24
Finished Aug 19 04:40:42 PM PDT 24
Peak memory 250944 kb
Host smart-4ae6a8a4-a2ab-44c4-9cb8-bcab81316328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65781060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.65781060
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.763565144
Short name T616
Test name
Test status
Simulation time 53992834 ps
CPU time 7.75 seconds
Started Aug 19 04:40:19 PM PDT 24
Finished Aug 19 04:40:27 PM PDT 24
Peak memory 250984 kb
Host smart-f8e8d006-dbc8-4603-a1d5-cef10444c936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763565144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.763565144
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2791133268
Short name T514
Test name
Test status
Simulation time 6651223515 ps
CPU time 88.03 seconds
Started Aug 19 04:40:22 PM PDT 24
Finished Aug 19 04:41:51 PM PDT 24
Peak memory 270500 kb
Host smart-fb53743c-7974-418f-b20e-5efafc1499a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791133268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2791133268
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3675694031
Short name T101
Test name
Test status
Simulation time 2849504961 ps
CPU time 87.58 seconds
Started Aug 19 04:40:31 PM PDT 24
Finished Aug 19 04:41:59 PM PDT 24
Peak memory 226300 kb
Host smart-d27aa966-b57a-4947-8b54-961248416e71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3675694031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3675694031
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1736088734
Short name T641
Test name
Test status
Simulation time 96711626 ps
CPU time 0.81 seconds
Started Aug 19 04:40:18 PM PDT 24
Finished Aug 19 04:40:19 PM PDT 24
Peak memory 208992 kb
Host smart-be0eee64-63a1-4f4e-b0e4-e3e6aeeb5dbc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736088734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1736088734
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.133228928
Short name T361
Test name
Test status
Simulation time 38566912 ps
CPU time 0.9 seconds
Started Aug 19 04:40:21 PM PDT 24
Finished Aug 19 04:40:22 PM PDT 24
Peak memory 208928 kb
Host smart-0a3b82aa-034a-46ff-8346-23cf8ea0ad86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133228928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.133228928
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1080574761
Short name T33
Test name
Test status
Simulation time 498524229 ps
CPU time 10.73 seconds
Started Aug 19 04:40:24 PM PDT 24
Finished Aug 19 04:40:35 PM PDT 24
Peak memory 218344 kb
Host smart-c14104a8-1cc6-4024-beaa-6b67e95f84ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080574761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1080574761
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3431413278
Short name T8
Test name
Test status
Simulation time 366114731 ps
CPU time 5.73 seconds
Started Aug 19 04:40:32 PM PDT 24
Finished Aug 19 04:40:37 PM PDT 24
Peak memory 217744 kb
Host smart-d7b60d66-67b9-47ff-8dc0-30f6356812b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431413278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3431413278
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1707723159
Short name T844
Test name
Test status
Simulation time 70718492 ps
CPU time 2.81 seconds
Started Aug 19 04:40:21 PM PDT 24
Finished Aug 19 04:40:24 PM PDT 24
Peak memory 218316 kb
Host smart-abc60c4e-b381-461f-bec1-0ebb099ceffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707723159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1707723159
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1497522066
Short name T810
Test name
Test status
Simulation time 482653834 ps
CPU time 8.21 seconds
Started Aug 19 04:40:31 PM PDT 24
Finished Aug 19 04:40:39 PM PDT 24
Peak memory 226132 kb
Host smart-46f1c19b-ea30-4d26-80ed-9e269575456e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497522066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1497522066
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1598849331
Short name T779
Test name
Test status
Simulation time 545246927 ps
CPU time 20.1 seconds
Started Aug 19 04:40:21 PM PDT 24
Finished Aug 19 04:40:42 PM PDT 24
Peak memory 226112 kb
Host smart-ff87e14e-9b02-413a-8d0a-c1b3680fc973
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598849331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1598849331
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2243554215
Short name T781
Test name
Test status
Simulation time 678272353 ps
CPU time 7.41 seconds
Started Aug 19 04:40:20 PM PDT 24
Finished Aug 19 04:40:27 PM PDT 24
Peak memory 217172 kb
Host smart-15d34c1b-2dbe-411d-ae2b-ce0e317f0a34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243554215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2243554215
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1384658223
Short name T14
Test name
Test status
Simulation time 50128691 ps
CPU time 2.97 seconds
Started Aug 19 04:40:25 PM PDT 24
Finished Aug 19 04:40:28 PM PDT 24
Peak memory 217760 kb
Host smart-f17cef8c-3cc8-4fea-a574-0593fc364d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384658223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1384658223
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.816024766
Short name T734
Test name
Test status
Simulation time 219102538 ps
CPU time 20.87 seconds
Started Aug 19 04:40:17 PM PDT 24
Finished Aug 19 04:40:38 PM PDT 24
Peak memory 251000 kb
Host smart-57b52f34-aa76-4a31-9923-62f703994ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816024766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.816024766
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3536080353
Short name T258
Test name
Test status
Simulation time 515004153 ps
CPU time 6.74 seconds
Started Aug 19 04:40:33 PM PDT 24
Finished Aug 19 04:40:40 PM PDT 24
Peak memory 246652 kb
Host smart-b13f16d8-748f-4cc0-bd9e-dd2440033a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536080353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3536080353
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.3166499840
Short name T631
Test name
Test status
Simulation time 2607078069 ps
CPU time 36.16 seconds
Started Aug 19 04:40:21 PM PDT 24
Finished Aug 19 04:40:57 PM PDT 24
Peak memory 242976 kb
Host smart-2c878297-5cac-4e01-b52a-e338fd7ab3ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3166499840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.3166499840
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.194709955
Short name T553
Test name
Test status
Simulation time 89194516 ps
CPU time 0.78 seconds
Started Aug 19 04:40:33 PM PDT 24
Finished Aug 19 04:40:34 PM PDT 24
Peak memory 209040 kb
Host smart-d17ec418-6e4d-47ef-8e58-8944000f8ea6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194709955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.194709955
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.597770648
Short name T711
Test name
Test status
Simulation time 31792112 ps
CPU time 0.84 seconds
Started Aug 19 04:40:27 PM PDT 24
Finished Aug 19 04:40:28 PM PDT 24
Peak memory 208840 kb
Host smart-786ca62e-da76-4766-9b38-29d31f992deb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597770648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.597770648
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2970287234
Short name T694
Test name
Test status
Simulation time 483350026 ps
CPU time 11.13 seconds
Started Aug 19 04:40:24 PM PDT 24
Finished Aug 19 04:40:36 PM PDT 24
Peak memory 218376 kb
Host smart-b42a72fe-1be4-41be-a1fd-911c21e71c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970287234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2970287234
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.415354248
Short name T748
Test name
Test status
Simulation time 502874219 ps
CPU time 1.99 seconds
Started Aug 19 04:40:18 PM PDT 24
Finished Aug 19 04:40:20 PM PDT 24
Peak memory 217788 kb
Host smart-296d2258-058b-4e1c-af61-88f26cda0f70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415354248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.415354248
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.259119679
Short name T767
Test name
Test status
Simulation time 184370615 ps
CPU time 1.96 seconds
Started Aug 19 04:40:23 PM PDT 24
Finished Aug 19 04:40:25 PM PDT 24
Peak memory 222264 kb
Host smart-50ca8ffa-4f5e-45b4-a5ca-970436954492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259119679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.259119679
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2774671590
Short name T776
Test name
Test status
Simulation time 410265130 ps
CPU time 13.51 seconds
Started Aug 19 04:40:20 PM PDT 24
Finished Aug 19 04:40:33 PM PDT 24
Peak memory 218628 kb
Host smart-b2bbd2a5-d8c0-4568-ae40-ee5a869ca959
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774671590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2774671590
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.4198970434
Short name T405
Test name
Test status
Simulation time 1318474915 ps
CPU time 9.07 seconds
Started Aug 19 04:40:18 PM PDT 24
Finished Aug 19 04:40:27 PM PDT 24
Peak memory 226084 kb
Host smart-a03c2c59-40c6-4e8b-a0fc-b4da0c7a977e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198970434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.4198970434
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1128803346
Short name T755
Test name
Test status
Simulation time 274891669 ps
CPU time 10.53 seconds
Started Aug 19 04:40:19 PM PDT 24
Finished Aug 19 04:40:30 PM PDT 24
Peak memory 218508 kb
Host smart-9da35a44-d299-4bdd-b4f3-53c2b713ad87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128803346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1128803346
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1730842485
Short name T715
Test name
Test status
Simulation time 70164523 ps
CPU time 1.47 seconds
Started Aug 19 04:40:19 PM PDT 24
Finished Aug 19 04:40:21 PM PDT 24
Peak memory 213844 kb
Host smart-00b616aa-2096-48cf-b7f3-bdb4adc3e8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730842485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1730842485
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.782444838
Short name T585
Test name
Test status
Simulation time 359312609 ps
CPU time 19.72 seconds
Started Aug 19 04:40:18 PM PDT 24
Finished Aug 19 04:40:38 PM PDT 24
Peak memory 250964 kb
Host smart-661e99d7-2ccd-44cf-8c40-99c71d6a123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782444838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.782444838
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1135838252
Short name T447
Test name
Test status
Simulation time 155171390 ps
CPU time 7.34 seconds
Started Aug 19 04:40:32 PM PDT 24
Finished Aug 19 04:40:39 PM PDT 24
Peak memory 247424 kb
Host smart-a5ac0701-e892-4042-8dc1-a97ebe938034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135838252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1135838252
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.77742787
Short name T102
Test name
Test status
Simulation time 6083996017 ps
CPU time 72.68 seconds
Started Aug 19 04:40:20 PM PDT 24
Finished Aug 19 04:41:32 PM PDT 24
Peak memory 283848 kb
Host smart-98929fa6-2663-4b8c-9a38-b37c6510efc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=77742787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.77742787
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1811964387
Short name T780
Test name
Test status
Simulation time 28152850 ps
CPU time 0.84 seconds
Started Aug 19 04:40:19 PM PDT 24
Finished Aug 19 04:40:20 PM PDT 24
Peak memory 209028 kb
Host smart-b7aa5a67-6f41-4227-bcb6-a4c044f51b52
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811964387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1811964387
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.211655594
Short name T555
Test name
Test status
Simulation time 18642241 ps
CPU time 1.15 seconds
Started Aug 19 04:40:47 PM PDT 24
Finished Aug 19 04:40:49 PM PDT 24
Peak memory 209092 kb
Host smart-993b4f62-9a2e-47d2-8d72-9d1fc04b156d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211655594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.211655594
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.549675480
Short name T632
Test name
Test status
Simulation time 1799880884 ps
CPU time 12.11 seconds
Started Aug 19 04:40:50 PM PDT 24
Finished Aug 19 04:41:02 PM PDT 24
Peak memory 218360 kb
Host smart-0ec07ed4-b57d-4d0b-97de-1824853f0452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549675480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.549675480
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1242632818
Short name T6
Test name
Test status
Simulation time 1925072105 ps
CPU time 4.89 seconds
Started Aug 19 04:40:46 PM PDT 24
Finished Aug 19 04:40:51 PM PDT 24
Peak memory 217792 kb
Host smart-e9115ee6-018b-43a9-be4c-c50d9de0f4c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242632818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1242632818
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1761590239
Short name T664
Test name
Test status
Simulation time 14620275 ps
CPU time 1.54 seconds
Started Aug 19 04:40:33 PM PDT 24
Finished Aug 19 04:40:35 PM PDT 24
Peak memory 218188 kb
Host smart-2924dd68-d1c5-43ec-9a38-b45773e38ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761590239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1761590239
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2045735394
Short name T500
Test name
Test status
Simulation time 659419998 ps
CPU time 11.56 seconds
Started Aug 19 04:40:43 PM PDT 24
Finished Aug 19 04:40:55 PM PDT 24
Peak memory 226152 kb
Host smart-221f009c-e44d-4ede-ac76-78e213a465ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045735394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2045735394
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1975159005
Short name T769
Test name
Test status
Simulation time 1001543411 ps
CPU time 19.34 seconds
Started Aug 19 04:40:45 PM PDT 24
Finished Aug 19 04:41:05 PM PDT 24
Peak memory 226100 kb
Host smart-8c828bcf-fbc0-44ed-a4d8-437b426f5360
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975159005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1975159005
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1932585401
Short name T832
Test name
Test status
Simulation time 1508469724 ps
CPU time 13.02 seconds
Started Aug 19 04:40:47 PM PDT 24
Finished Aug 19 04:41:00 PM PDT 24
Peak memory 218340 kb
Host smart-a51d5b4d-8cd8-4128-98c4-1d9b841ac279
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932585401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1932585401
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2970257955
Short name T595
Test name
Test status
Simulation time 1144776588 ps
CPU time 8.61 seconds
Started Aug 19 04:40:47 PM PDT 24
Finished Aug 19 04:40:56 PM PDT 24
Peak memory 218456 kb
Host smart-ac1afe36-9ffb-44f5-8b85-5f2ee9a56c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970257955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2970257955
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3203345118
Short name T582
Test name
Test status
Simulation time 55841884 ps
CPU time 1.18 seconds
Started Aug 19 04:40:24 PM PDT 24
Finished Aug 19 04:40:25 PM PDT 24
Peak memory 217788 kb
Host smart-9a0991dc-cbf6-4825-89ea-7c639320ed11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203345118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3203345118
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.860261704
Short name T436
Test name
Test status
Simulation time 143686942 ps
CPU time 24.06 seconds
Started Aug 19 04:40:26 PM PDT 24
Finished Aug 19 04:40:51 PM PDT 24
Peak memory 250968 kb
Host smart-feb6902a-0850-4af6-87b1-e5c13f8ee287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860261704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.860261704
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.986606943
Short name T817
Test name
Test status
Simulation time 91654007 ps
CPU time 8.24 seconds
Started Aug 19 04:40:22 PM PDT 24
Finished Aug 19 04:40:30 PM PDT 24
Peak memory 250924 kb
Host smart-37d5c6a4-da2b-4874-afcb-46081ce3d8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986606943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.986606943
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3301103894
Short name T80
Test name
Test status
Simulation time 35170276152 ps
CPU time 47.16 seconds
Started Aug 19 04:40:45 PM PDT 24
Finished Aug 19 04:41:33 PM PDT 24
Peak memory 250796 kb
Host smart-911fbf7b-cfb2-47ba-be2b-7a1b868db50c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301103894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3301103894
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1374499569
Short name T36
Test name
Test status
Simulation time 52461029 ps
CPU time 1.01 seconds
Started Aug 19 04:40:18 PM PDT 24
Finished Aug 19 04:40:19 PM PDT 24
Peak memory 217968 kb
Host smart-5bd29a91-510b-4dbb-91e6-c91193b33498
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374499569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1374499569
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1412742296
Short name T586
Test name
Test status
Simulation time 45299390 ps
CPU time 0.99 seconds
Started Aug 19 04:40:49 PM PDT 24
Finished Aug 19 04:40:50 PM PDT 24
Peak memory 208996 kb
Host smart-a41cbdb3-d1e2-4ffb-8a8d-16c267c547fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412742296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1412742296
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3392131109
Short name T54
Test name
Test status
Simulation time 2022309725 ps
CPU time 21.9 seconds
Started Aug 19 04:40:47 PM PDT 24
Finished Aug 19 04:41:09 PM PDT 24
Peak memory 218336 kb
Host smart-0a58e4cb-0bfa-470e-9e7b-32c4465f2252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392131109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3392131109
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1982183440
Short name T192
Test name
Test status
Simulation time 2204102003 ps
CPU time 5.75 seconds
Started Aug 19 04:40:47 PM PDT 24
Finished Aug 19 04:40:53 PM PDT 24
Peak memory 217828 kb
Host smart-d53794ae-2993-420d-9ebe-8989014cc4a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982183440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1982183440
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3853911895
Short name T390
Test name
Test status
Simulation time 197994763 ps
CPU time 4.57 seconds
Started Aug 19 04:40:45 PM PDT 24
Finished Aug 19 04:40:50 PM PDT 24
Peak memory 218368 kb
Host smart-0d077f14-36df-4cee-9109-ed7677dd390d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853911895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3853911895
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2413058609
Short name T743
Test name
Test status
Simulation time 428308219 ps
CPU time 10.28 seconds
Started Aug 19 04:40:47 PM PDT 24
Finished Aug 19 04:40:58 PM PDT 24
Peak memory 218988 kb
Host smart-fa9cc8eb-0d51-4856-85f0-57e0fc8ce1ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413058609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2413058609
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.206485505
Short name T513
Test name
Test status
Simulation time 826034685 ps
CPU time 8.97 seconds
Started Aug 19 04:40:44 PM PDT 24
Finished Aug 19 04:40:53 PM PDT 24
Peak memory 226084 kb
Host smart-a693eee1-5e49-46c9-8401-b570dbd2023a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206485505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.206485505
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2110408058
Short name T379
Test name
Test status
Simulation time 1403157240 ps
CPU time 7.11 seconds
Started Aug 19 04:40:46 PM PDT 24
Finished Aug 19 04:40:54 PM PDT 24
Peak memory 218328 kb
Host smart-85228552-76ed-4410-bb3a-1a15e7da8e90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110408058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2110408058
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.4270955570
Short name T683
Test name
Test status
Simulation time 998621175 ps
CPU time 11.45 seconds
Started Aug 19 04:40:46 PM PDT 24
Finished Aug 19 04:40:57 PM PDT 24
Peak memory 225764 kb
Host smart-87070c4b-1fe7-490e-836f-2afe1ad9f95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270955570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.4270955570
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.737688189
Short name T704
Test name
Test status
Simulation time 287217813 ps
CPU time 5.43 seconds
Started Aug 19 04:40:47 PM PDT 24
Finished Aug 19 04:40:53 PM PDT 24
Peak memory 223132 kb
Host smart-720aca43-e6b0-4ef1-b479-312ae11006fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737688189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.737688189
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3088858878
Short name T717
Test name
Test status
Simulation time 307779785 ps
CPU time 28.48 seconds
Started Aug 19 04:40:47 PM PDT 24
Finished Aug 19 04:41:15 PM PDT 24
Peak memory 250980 kb
Host smart-657e3957-6e89-455f-b1be-15625d583dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088858878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3088858878
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3440290540
Short name T768
Test name
Test status
Simulation time 64373322 ps
CPU time 8.28 seconds
Started Aug 19 04:40:41 PM PDT 24
Finished Aug 19 04:40:49 PM PDT 24
Peak memory 250904 kb
Host smart-0578c327-89dc-4b1d-8698-185b9a4978fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440290540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3440290540
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2328377962
Short name T171
Test name
Test status
Simulation time 23093031742 ps
CPU time 711.16 seconds
Started Aug 19 04:40:47 PM PDT 24
Finished Aug 19 04:52:39 PM PDT 24
Peak memory 247680 kb
Host smart-bca1c310-3c82-4a0f-9643-51d822311cfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328377962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2328377962
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2729470849
Short name T84
Test name
Test status
Simulation time 50174884 ps
CPU time 1.58 seconds
Started Aug 19 04:40:43 PM PDT 24
Finished Aug 19 04:40:45 PM PDT 24
Peak memory 217976 kb
Host smart-55a48268-40b5-4415-b0ba-c0bce0decfc5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729470849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2729470849
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2315546019
Short name T29
Test name
Test status
Simulation time 22294292 ps
CPU time 1.17 seconds
Started Aug 19 04:40:56 PM PDT 24
Finished Aug 19 04:40:58 PM PDT 24
Peak memory 209020 kb
Host smart-7b45b890-a291-4468-b5a5-aac2bf676791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315546019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2315546019
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1748643655
Short name T860
Test name
Test status
Simulation time 449840512 ps
CPU time 11.87 seconds
Started Aug 19 04:40:56 PM PDT 24
Finished Aug 19 04:41:08 PM PDT 24
Peak memory 226136 kb
Host smart-9e93f330-2acd-457b-a024-16e0c21b3df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748643655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1748643655
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3845837784
Short name T7
Test name
Test status
Simulation time 465489607 ps
CPU time 6.2 seconds
Started Aug 19 04:41:00 PM PDT 24
Finished Aug 19 04:41:06 PM PDT 24
Peak memory 217124 kb
Host smart-b2dfacf4-7df8-4fda-b63f-caf7b28eed70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845837784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3845837784
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.5147227
Short name T732
Test name
Test status
Simulation time 16393177 ps
CPU time 1.64 seconds
Started Aug 19 04:40:48 PM PDT 24
Finished Aug 19 04:40:49 PM PDT 24
Peak memory 222004 kb
Host smart-9ef39a18-7a34-4ea2-9d02-9c8fb488abaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5147227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.5147227
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3515181724
Short name T255
Test name
Test status
Simulation time 582158318 ps
CPU time 11.68 seconds
Started Aug 19 04:41:02 PM PDT 24
Finished Aug 19 04:41:14 PM PDT 24
Peak memory 218532 kb
Host smart-3ca4f4e7-ea1f-41d7-ba74-ae96265397fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515181724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3515181724
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3692922712
Short name T291
Test name
Test status
Simulation time 1075240418 ps
CPU time 9.09 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:41:04 PM PDT 24
Peak memory 226108 kb
Host smart-f2e7d8a0-f01e-4199-8b4a-785758e4ff97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692922712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3692922712
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3520592009
Short name T237
Test name
Test status
Simulation time 275356510 ps
CPU time 10.03 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:41:05 PM PDT 24
Peak memory 218304 kb
Host smart-b991c0f1-6100-4e4d-870e-fb6d2e2c08a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520592009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3520592009
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3190236849
Short name T453
Test name
Test status
Simulation time 1687824062 ps
CPU time 15.51 seconds
Started Aug 19 04:40:54 PM PDT 24
Finished Aug 19 04:41:09 PM PDT 24
Peak memory 226108 kb
Host smart-b23d4832-4a4a-4853-8a60-b6b6920c1714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190236849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3190236849
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1565712678
Short name T841
Test name
Test status
Simulation time 141047787 ps
CPU time 5.19 seconds
Started Aug 19 04:40:47 PM PDT 24
Finished Aug 19 04:40:53 PM PDT 24
Peak memory 214692 kb
Host smart-91b129f4-01d9-4096-83ff-7da090620baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565712678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1565712678
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.879596808
Short name T96
Test name
Test status
Simulation time 353408021 ps
CPU time 20.03 seconds
Started Aug 19 04:40:47 PM PDT 24
Finished Aug 19 04:41:07 PM PDT 24
Peak memory 251004 kb
Host smart-b01b672b-76d9-4c75-9cb1-38830b600c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879596808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.879596808
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1194696219
Short name T869
Test name
Test status
Simulation time 293251012 ps
CPU time 7.35 seconds
Started Aug 19 04:40:41 PM PDT 24
Finished Aug 19 04:40:48 PM PDT 24
Peak memory 250816 kb
Host smart-92991b27-3988-4152-9655-5d5ed7058c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194696219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1194696219
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.26972110
Short name T316
Test name
Test status
Simulation time 42735605951 ps
CPU time 184.18 seconds
Started Aug 19 04:40:53 PM PDT 24
Finished Aug 19 04:43:57 PM PDT 24
Peak memory 284184 kb
Host smart-da287ded-4756-428e-8c08-8e407222d84c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26972110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.lc_ctrl_stress_all.26972110
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.896578602
Short name T477
Test name
Test status
Simulation time 13957988 ps
CPU time 0.96 seconds
Started Aug 19 04:40:41 PM PDT 24
Finished Aug 19 04:40:42 PM PDT 24
Peak memory 208648 kb
Host smart-50e7c5fa-7853-4905-b3b8-0376ab7e3b6a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896578602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.896578602
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2821380225
Short name T329
Test name
Test status
Simulation time 460163311 ps
CPU time 13.11 seconds
Started Aug 19 04:38:55 PM PDT 24
Finished Aug 19 04:39:08 PM PDT 24
Peak memory 218344 kb
Host smart-f236249b-dc04-4a51-a421-7f89c66c9dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821380225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2821380225
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2502471789
Short name T820
Test name
Test status
Simulation time 132185607 ps
CPU time 1.12 seconds
Started Aug 19 04:38:58 PM PDT 24
Finished Aug 19 04:38:59 PM PDT 24
Peak memory 217792 kb
Host smart-a27cd4c8-be39-4a6e-8053-b3c1c794a66f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502471789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2502471789
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3970902433
Short name T469
Test name
Test status
Simulation time 5618549176 ps
CPU time 22.87 seconds
Started Aug 19 04:38:56 PM PDT 24
Finished Aug 19 04:39:19 PM PDT 24
Peak memory 226120 kb
Host smart-e7b017c5-3af4-4cc9-979a-939bd95e92e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970902433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3970902433
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3949114505
Short name T270
Test name
Test status
Simulation time 2128180892 ps
CPU time 6.78 seconds
Started Aug 19 04:40:18 PM PDT 24
Finished Aug 19 04:40:25 PM PDT 24
Peak memory 216736 kb
Host smart-d55fca37-ee1f-41c3-ab02-47d6ddb307a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949114505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
949114505
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3912091312
Short name T256
Test name
Test status
Simulation time 531153861 ps
CPU time 8.23 seconds
Started Aug 19 04:38:59 PM PDT 24
Finished Aug 19 04:39:07 PM PDT 24
Peak memory 224324 kb
Host smart-9c5b60e6-491f-4a84-ac16-66e59ea962c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912091312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3912091312
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1795601458
Short name T268
Test name
Test status
Simulation time 17742864526 ps
CPU time 22.6 seconds
Started Aug 19 04:40:06 PM PDT 24
Finished Aug 19 04:40:30 PM PDT 24
Peak memory 216216 kb
Host smart-f0efe4c9-c3f4-46fd-92c8-72abdd07d013
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795601458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1795601458
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1821847676
Short name T462
Test name
Test status
Simulation time 1015603067 ps
CPU time 4.63 seconds
Started Aug 19 04:38:57 PM PDT 24
Finished Aug 19 04:39:01 PM PDT 24
Peak memory 217752 kb
Host smart-6c5be68a-ec62-4af0-94f6-3353f26fc0ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821847676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1821847676
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2569661369
Short name T298
Test name
Test status
Simulation time 17712846397 ps
CPU time 112.49 seconds
Started Aug 19 04:38:58 PM PDT 24
Finished Aug 19 04:40:50 PM PDT 24
Peak memory 283232 kb
Host smart-016e7e49-1148-40fa-bd64-d54079028dd1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569661369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2569661369
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.607248949
Short name T568
Test name
Test status
Simulation time 1219294389 ps
CPU time 13.98 seconds
Started Aug 19 04:38:56 PM PDT 24
Finished Aug 19 04:39:10 PM PDT 24
Peak memory 250972 kb
Host smart-098f75eb-3fdd-4695-b224-19b0682a6a2b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607248949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.607248949
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2272403077
Short name T808
Test name
Test status
Simulation time 27370869 ps
CPU time 1.55 seconds
Started Aug 19 04:38:54 PM PDT 24
Finished Aug 19 04:38:55 PM PDT 24
Peak memory 218348 kb
Host smart-55674c52-7fb1-4776-bf50-2a36a6fcffb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272403077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2272403077
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.719752943
Short name T94
Test name
Test status
Simulation time 1746085149 ps
CPU time 9.66 seconds
Started Aug 19 04:38:57 PM PDT 24
Finished Aug 19 04:39:07 PM PDT 24
Peak memory 217788 kb
Host smart-62ea6a73-bca9-4caf-b735-3db0b13867ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719752943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.719752943
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1832852035
Short name T98
Test name
Test status
Simulation time 258514930 ps
CPU time 24.46 seconds
Started Aug 19 04:40:06 PM PDT 24
Finished Aug 19 04:40:32 PM PDT 24
Peak memory 281032 kb
Host smart-2211899b-bc40-43dd-969f-bc1e0140e9b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832852035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1832852035
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3052510783
Short name T510
Test name
Test status
Simulation time 959263216 ps
CPU time 12.27 seconds
Started Aug 19 04:38:57 PM PDT 24
Finished Aug 19 04:39:09 PM PDT 24
Peak memory 226204 kb
Host smart-e6fcd6d6-2702-4be2-bdaf-53becd8f16c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052510783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3052510783
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3399282405
Short name T433
Test name
Test status
Simulation time 1407390626 ps
CPU time 14.28 seconds
Started Aug 19 04:38:57 PM PDT 24
Finished Aug 19 04:39:11 PM PDT 24
Peak memory 226084 kb
Host smart-8720895d-4c9a-4afa-989a-0a69c3afc1aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399282405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3399282405
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1008426746
Short name T56
Test name
Test status
Simulation time 285793998 ps
CPU time 7.56 seconds
Started Aug 19 04:38:58 PM PDT 24
Finished Aug 19 04:39:05 PM PDT 24
Peak memory 218332 kb
Host smart-d53fb622-5c11-48ec-86b2-d59de5ee132b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008426746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
008426746
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1697488478
Short name T457
Test name
Test status
Simulation time 454458602 ps
CPU time 15.08 seconds
Started Aug 19 04:38:59 PM PDT 24
Finished Aug 19 04:39:14 PM PDT 24
Peak memory 218436 kb
Host smart-620f2c1d-3a02-48da-94ff-70c42df577ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697488478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1697488478
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1512820726
Short name T71
Test name
Test status
Simulation time 239536940 ps
CPU time 3.08 seconds
Started Aug 19 04:38:59 PM PDT 24
Finished Aug 19 04:39:03 PM PDT 24
Peak memory 217748 kb
Host smart-35764aba-a785-4d2a-8ba3-e59c73b65668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512820726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1512820726
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1745821500
Short name T480
Test name
Test status
Simulation time 2258987489 ps
CPU time 20.2 seconds
Started Aug 19 04:38:54 PM PDT 24
Finished Aug 19 04:39:14 PM PDT 24
Peak memory 251152 kb
Host smart-db27faa1-3f64-459e-9745-a08579e28c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745821500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1745821500
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.711760605
Short name T321
Test name
Test status
Simulation time 256794202 ps
CPU time 7.55 seconds
Started Aug 19 04:38:59 PM PDT 24
Finished Aug 19 04:39:07 PM PDT 24
Peak memory 250964 kb
Host smart-9bdc2aa9-7efe-4a50-bf0c-227dd245ae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711760605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.711760605
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3165958921
Short name T409
Test name
Test status
Simulation time 4234789090 ps
CPU time 115.15 seconds
Started Aug 19 04:38:58 PM PDT 24
Finished Aug 19 04:40:53 PM PDT 24
Peak memory 251068 kb
Host smart-b59ff93a-7e65-4ebc-a5ff-c8d903642aec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165958921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3165958921
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3432919904
Short name T149
Test name
Test status
Simulation time 3808814809 ps
CPU time 78.44 seconds
Started Aug 19 04:40:06 PM PDT 24
Finished Aug 19 04:41:26 PM PDT 24
Peak memory 249256 kb
Host smart-975e0f16-79c2-40fa-a71a-a383c4e7e0e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3432919904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.3432919904
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2153582995
Short name T39
Test name
Test status
Simulation time 43433649 ps
CPU time 0.87 seconds
Started Aug 19 04:38:59 PM PDT 24
Finished Aug 19 04:39:00 PM PDT 24
Peak memory 209068 kb
Host smart-b55ef27f-d853-4534-85f6-2ee39af3d563
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153582995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2153582995
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1228938089
Short name T807
Test name
Test status
Simulation time 65914236 ps
CPU time 0.87 seconds
Started Aug 19 04:40:59 PM PDT 24
Finished Aug 19 04:41:00 PM PDT 24
Peak memory 209000 kb
Host smart-d168afc4-a015-42f8-8d72-ab99081f96e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228938089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1228938089
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1729947491
Short name T759
Test name
Test status
Simulation time 1150496531 ps
CPU time 4 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:40:59 PM PDT 24
Peak memory 217828 kb
Host smart-e258ab69-da46-465d-86bf-233f9080cf80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729947491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1729947491
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2278402227
Short name T244
Test name
Test status
Simulation time 39080771 ps
CPU time 2.52 seconds
Started Aug 19 04:40:57 PM PDT 24
Finished Aug 19 04:41:00 PM PDT 24
Peak memory 218376 kb
Host smart-b71e4207-1d6c-4ef3-80c5-6cc6b16d210b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278402227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2278402227
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.749353684
Short name T527
Test name
Test status
Simulation time 492912108 ps
CPU time 14.92 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:41:10 PM PDT 24
Peak memory 218844 kb
Host smart-f90610a2-4047-4ab0-ba3d-6c2351f3d370
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749353684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.749353684
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3912475054
Short name T581
Test name
Test status
Simulation time 421607135 ps
CPU time 13.15 seconds
Started Aug 19 04:40:57 PM PDT 24
Finished Aug 19 04:41:10 PM PDT 24
Peak memory 226112 kb
Host smart-8cc2425c-31b5-41a6-a235-95ef9c580068
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912475054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3912475054
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.221261552
Short name T744
Test name
Test status
Simulation time 270487762 ps
CPU time 10.9 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:41:06 PM PDT 24
Peak memory 218328 kb
Host smart-bf8cd736-4602-40fe-8fe9-656fec4f2249
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221261552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.221261552
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1573223095
Short name T354
Test name
Test status
Simulation time 317684396 ps
CPU time 8.71 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:41:03 PM PDT 24
Peak memory 225640 kb
Host smart-7136f4ef-153f-46ca-8a65-5d1b1a3b711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573223095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1573223095
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1473148042
Short name T112
Test name
Test status
Simulation time 26484858 ps
CPU time 1.36 seconds
Started Aug 19 04:40:56 PM PDT 24
Finished Aug 19 04:40:58 PM PDT 24
Peak memory 217780 kb
Host smart-57c09ac0-59fb-44ff-bb0e-fa22886fc62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473148042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1473148042
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2159915043
Short name T692
Test name
Test status
Simulation time 335420447 ps
CPU time 27.83 seconds
Started Aug 19 04:40:59 PM PDT 24
Finished Aug 19 04:41:27 PM PDT 24
Peak memory 250940 kb
Host smart-78fdb153-03da-4000-bc1c-3e6409a42f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159915043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2159915043
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3347276492
Short name T297
Test name
Test status
Simulation time 881093606 ps
CPU time 7.56 seconds
Started Aug 19 04:40:54 PM PDT 24
Finished Aug 19 04:41:02 PM PDT 24
Peak memory 250968 kb
Host smart-0fd291b4-ba1d-4f88-b856-6ca7e517c036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347276492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3347276492
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.920619012
Short name T168
Test name
Test status
Simulation time 27854224418 ps
CPU time 111.43 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:42:47 PM PDT 24
Peak memory 277576 kb
Host smart-fa8bb816-bb15-43a5-9c40-b095421ef256
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920619012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.920619012
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1117157438
Short name T857
Test name
Test status
Simulation time 13384474 ps
CPU time 0.99 seconds
Started Aug 19 04:40:53 PM PDT 24
Finished Aug 19 04:40:54 PM PDT 24
Peak memory 213016 kb
Host smart-d2243feb-0110-4a2c-9dcb-3890fdcf9c51
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117157438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1117157438
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2714871331
Short name T232
Test name
Test status
Simulation time 27703335 ps
CPU time 1.03 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:40:56 PM PDT 24
Peak memory 209032 kb
Host smart-56d03e7d-a540-4703-9ba7-9d437e2b964a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714871331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2714871331
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3995761822
Short name T688
Test name
Test status
Simulation time 353422819 ps
CPU time 9.27 seconds
Started Aug 19 04:40:57 PM PDT 24
Finished Aug 19 04:41:06 PM PDT 24
Peak memory 218340 kb
Host smart-2255f19b-16ec-482c-b535-4e04c20c5cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995761822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3995761822
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.4040683571
Short name T697
Test name
Test status
Simulation time 411299239 ps
CPU time 4.38 seconds
Started Aug 19 04:40:53 PM PDT 24
Finished Aug 19 04:40:58 PM PDT 24
Peak memory 217796 kb
Host smart-49bc10c7-c5d2-488b-a546-ef4916ab8e9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040683571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.4040683571
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.712657845
Short name T242
Test name
Test status
Simulation time 185967037 ps
CPU time 3.42 seconds
Started Aug 19 04:40:54 PM PDT 24
Finished Aug 19 04:40:58 PM PDT 24
Peak memory 222916 kb
Host smart-5612adde-d22b-4507-bfc0-c2c0d0f40269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712657845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.712657845
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2532156461
Short name T290
Test name
Test status
Simulation time 552486306 ps
CPU time 14.38 seconds
Started Aug 19 04:40:56 PM PDT 24
Finished Aug 19 04:41:10 PM PDT 24
Peak memory 225872 kb
Host smart-d8c959d9-dc7e-4abd-8cc3-c4be9952279e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532156461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2532156461
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2043744557
Short name T674
Test name
Test status
Simulation time 844020707 ps
CPU time 13.26 seconds
Started Aug 19 04:40:59 PM PDT 24
Finished Aug 19 04:41:12 PM PDT 24
Peak memory 226076 kb
Host smart-d139f59e-6052-4057-9778-c2e8caf544da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043744557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2043744557
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3463244042
Short name T502
Test name
Test status
Simulation time 1723856564 ps
CPU time 8.18 seconds
Started Aug 19 04:40:59 PM PDT 24
Finished Aug 19 04:41:07 PM PDT 24
Peak memory 226040 kb
Host smart-3fd67252-6418-4bf8-acdd-baba442bb4c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463244042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3463244042
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1088264858
Short name T88
Test name
Test status
Simulation time 60482759 ps
CPU time 3.21 seconds
Started Aug 19 04:40:56 PM PDT 24
Finished Aug 19 04:40:59 PM PDT 24
Peak memory 217776 kb
Host smart-8bee004c-6a3e-460d-8676-8faf96b72b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088264858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1088264858
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3370843349
Short name T775
Test name
Test status
Simulation time 293127320 ps
CPU time 27.19 seconds
Started Aug 19 04:40:57 PM PDT 24
Finished Aug 19 04:41:24 PM PDT 24
Peak memory 250964 kb
Host smart-ce14f866-f600-415a-bd6c-ce69ab04209f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370843349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3370843349
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3331377223
Short name T432
Test name
Test status
Simulation time 178220063 ps
CPU time 4.03 seconds
Started Aug 19 04:40:56 PM PDT 24
Finished Aug 19 04:41:00 PM PDT 24
Peak memory 222860 kb
Host smart-f71fb8a7-ac74-4833-8bf2-5061711b031b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331377223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3331377223
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3671412617
Short name T252
Test name
Test status
Simulation time 60835451623 ps
CPU time 165.26 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:43:41 PM PDT 24
Peak memory 248152 kb
Host smart-34cbb4f5-a419-4d4c-a003-59de3ce0a21d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671412617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3671412617
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3340608336
Short name T32
Test name
Test status
Simulation time 14604678 ps
CPU time 1.1 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:40:56 PM PDT 24
Peak memory 217940 kb
Host smart-398e0450-9684-454c-917c-f2e1f8826e8e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340608336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3340608336
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2597261275
Short name T309
Test name
Test status
Simulation time 50157834 ps
CPU time 0.99 seconds
Started Aug 19 04:40:57 PM PDT 24
Finished Aug 19 04:40:58 PM PDT 24
Peak memory 209044 kb
Host smart-be659542-0cc2-4e53-9a1c-e1fcd4af372f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597261275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2597261275
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.4077431992
Short name T691
Test name
Test status
Simulation time 5841996389 ps
CPU time 16.05 seconds
Started Aug 19 04:40:57 PM PDT 24
Finished Aug 19 04:41:13 PM PDT 24
Peak memory 218400 kb
Host smart-84cd36f1-5e72-423f-be8b-01078ff54fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077431992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.4077431992
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1347941704
Short name T629
Test name
Test status
Simulation time 1667223507 ps
CPU time 4.88 seconds
Started Aug 19 04:41:02 PM PDT 24
Finished Aug 19 04:41:07 PM PDT 24
Peak memory 217764 kb
Host smart-21a6df9c-b33f-4ca4-bb25-50affc413e30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347941704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1347941704
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3435667450
Short name T362
Test name
Test status
Simulation time 96658150 ps
CPU time 4 seconds
Started Aug 19 04:40:59 PM PDT 24
Finished Aug 19 04:41:04 PM PDT 24
Peak memory 218312 kb
Host smart-f04a2580-5bce-4c2f-b06c-25d84f02cc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435667450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3435667450
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3984858970
Short name T539
Test name
Test status
Simulation time 469557643 ps
CPU time 15.48 seconds
Started Aug 19 04:40:56 PM PDT 24
Finished Aug 19 04:41:11 PM PDT 24
Peak memory 219988 kb
Host smart-bf868d24-76d4-43a8-a870-4c234cd3a4de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984858970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3984858970
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2120715001
Short name T653
Test name
Test status
Simulation time 1343293232 ps
CPU time 11.36 seconds
Started Aug 19 04:40:54 PM PDT 24
Finished Aug 19 04:41:05 PM PDT 24
Peak memory 226084 kb
Host smart-3635ccd2-5f44-4e39-af26-617248c78bed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120715001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2120715001
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2077886912
Short name T404
Test name
Test status
Simulation time 659454477 ps
CPU time 11.94 seconds
Started Aug 19 04:40:57 PM PDT 24
Finished Aug 19 04:41:09 PM PDT 24
Peak memory 218300 kb
Host smart-358b6396-8fd4-4de8-85e7-92026d89e9be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077886912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2077886912
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3098795492
Short name T59
Test name
Test status
Simulation time 1174143825 ps
CPU time 6.3 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:41:01 PM PDT 24
Peak memory 225196 kb
Host smart-ac201561-83ab-4466-aa8c-ffbf644dc3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098795492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3098795492
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3622853799
Short name T864
Test name
Test status
Simulation time 24141053 ps
CPU time 1.66 seconds
Started Aug 19 04:40:54 PM PDT 24
Finished Aug 19 04:40:56 PM PDT 24
Peak memory 217844 kb
Host smart-70c64168-6e2a-4533-9dff-6c22b75c5cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622853799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3622853799
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2342127771
Short name T391
Test name
Test status
Simulation time 2543167238 ps
CPU time 28.18 seconds
Started Aug 19 04:41:00 PM PDT 24
Finished Aug 19 04:41:28 PM PDT 24
Peak memory 251044 kb
Host smart-3a8bbe3f-d120-40e6-8a6d-4528ae1ae5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342127771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2342127771
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2249214811
Short name T695
Test name
Test status
Simulation time 11350536326 ps
CPU time 100.32 seconds
Started Aug 19 04:40:59 PM PDT 24
Finished Aug 19 04:42:39 PM PDT 24
Peak memory 276832 kb
Host smart-337db848-ac8e-49f2-ae7c-d6ce68418349
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249214811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2249214811
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3344491835
Short name T48
Test name
Test status
Simulation time 44125276 ps
CPU time 0.89 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:40:56 PM PDT 24
Peak memory 209080 kb
Host smart-0ed60a43-09b0-4773-b60a-ab08edf3e916
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344491835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3344491835
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1031813991
Short name T604
Test name
Test status
Simulation time 87395396 ps
CPU time 0.99 seconds
Started Aug 19 04:40:57 PM PDT 24
Finished Aug 19 04:40:58 PM PDT 24
Peak memory 209152 kb
Host smart-04a412f1-4e9e-4135-b7d8-b33bc9285d1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031813991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1031813991
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2660515132
Short name T271
Test name
Test status
Simulation time 889203342 ps
CPU time 10.55 seconds
Started Aug 19 04:40:56 PM PDT 24
Finished Aug 19 04:41:07 PM PDT 24
Peak memory 226168 kb
Host smart-1d583e50-51f4-4c96-8f62-361f2f915b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660515132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2660515132
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3113911694
Short name T576
Test name
Test status
Simulation time 939337649 ps
CPU time 9.11 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:41:05 PM PDT 24
Peak memory 217548 kb
Host smart-57f2bf0f-e052-4fdd-90da-10982113cdac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113911694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3113911694
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2113637256
Short name T482
Test name
Test status
Simulation time 53304192 ps
CPU time 2.93 seconds
Started Aug 19 04:40:58 PM PDT 24
Finished Aug 19 04:41:01 PM PDT 24
Peak memory 218364 kb
Host smart-b2149ec1-6c78-43b5-a08b-496cb504944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113637256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2113637256
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1536405853
Short name T43
Test name
Test status
Simulation time 315036202 ps
CPU time 11.99 seconds
Started Aug 19 04:40:57 PM PDT 24
Finished Aug 19 04:41:09 PM PDT 24
Peak memory 219092 kb
Host smart-55282526-d8db-4ab8-8701-ea825ca65e2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536405853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1536405853
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2298187295
Short name T370
Test name
Test status
Simulation time 333371514 ps
CPU time 11.55 seconds
Started Aug 19 04:40:57 PM PDT 24
Finished Aug 19 04:41:08 PM PDT 24
Peak memory 226080 kb
Host smart-c91feffb-f219-44e6-a206-948f58b4b0ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298187295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2298187295
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1431913906
Short name T2
Test name
Test status
Simulation time 2823140603 ps
CPU time 8.98 seconds
Started Aug 19 04:41:03 PM PDT 24
Finished Aug 19 04:41:13 PM PDT 24
Peak memory 226172 kb
Host smart-594ceb00-4ca2-4ba7-8b89-5fb7c99b3bb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431913906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1431913906
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.848260287
Short name T399
Test name
Test status
Simulation time 1440308399 ps
CPU time 14.08 seconds
Started Aug 19 04:41:01 PM PDT 24
Finished Aug 19 04:41:15 PM PDT 24
Peak memory 218428 kb
Host smart-80b1f4ab-ab2c-4a4c-9df7-030bbfdf3ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848260287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.848260287
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.56731943
Short name T75
Test name
Test status
Simulation time 100187840 ps
CPU time 1.89 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:40:57 PM PDT 24
Peak memory 214556 kb
Host smart-4a258ea6-bcb1-4c8e-a2c8-c3fcfa0583f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56731943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.56731943
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.4171360461
Short name T608
Test name
Test status
Simulation time 1088610113 ps
CPU time 26.9 seconds
Started Aug 19 04:40:55 PM PDT 24
Finished Aug 19 04:41:22 PM PDT 24
Peak memory 247216 kb
Host smart-e39c4988-67e1-46e5-b361-a5e4ccd7fbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171360461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.4171360461
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.957226788
Short name T476
Test name
Test status
Simulation time 255442572 ps
CPU time 9 seconds
Started Aug 19 04:40:56 PM PDT 24
Finished Aug 19 04:41:05 PM PDT 24
Peak memory 250976 kb
Host smart-1fb584ba-5180-4434-95ee-a041394e9564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957226788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.957226788
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1834650114
Short name T714
Test name
Test status
Simulation time 39205690555 ps
CPU time 332.17 seconds
Started Aug 19 04:40:58 PM PDT 24
Finished Aug 19 04:46:30 PM PDT 24
Peak memory 250956 kb
Host smart-720e534e-3ac2-49e6-b9ba-64d52f384ab0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834650114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1834650114
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.908187280
Short name T425
Test name
Test status
Simulation time 13788389 ps
CPU time 0.77 seconds
Started Aug 19 04:40:59 PM PDT 24
Finished Aug 19 04:41:00 PM PDT 24
Peak memory 209012 kb
Host smart-0a998df7-2e50-463c-83fc-d23ae75bc4c6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908187280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.908187280
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3445183778
Short name T778
Test name
Test status
Simulation time 16585945 ps
CPU time 0.98 seconds
Started Aug 19 04:41:01 PM PDT 24
Finished Aug 19 04:41:02 PM PDT 24
Peak memory 208220 kb
Host smart-d33576d6-3289-420c-b9e0-6a500531d27d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445183778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3445183778
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.498439865
Short name T278
Test name
Test status
Simulation time 237832411 ps
CPU time 10.62 seconds
Started Aug 19 04:40:59 PM PDT 24
Finished Aug 19 04:41:09 PM PDT 24
Peak memory 218332 kb
Host smart-5c334dca-d0d8-40d3-a92e-ad25d93cbdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498439865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.498439865
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3973673712
Short name T367
Test name
Test status
Simulation time 2110529690 ps
CPU time 15.49 seconds
Started Aug 19 04:41:02 PM PDT 24
Finished Aug 19 04:41:18 PM PDT 24
Peak memory 217764 kb
Host smart-2cfac5be-78ef-491a-bf9b-c7c83ea54674
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973673712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3973673712
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3225141731
Short name T752
Test name
Test status
Simulation time 265064623 ps
CPU time 2.88 seconds
Started Aug 19 04:41:00 PM PDT 24
Finished Aug 19 04:41:03 PM PDT 24
Peak memory 218304 kb
Host smart-3ad6763f-9866-42d6-8cdd-ecc6b306990b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225141731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3225141731
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3077931677
Short name T815
Test name
Test status
Simulation time 822565737 ps
CPU time 17.58 seconds
Started Aug 19 04:41:04 PM PDT 24
Finished Aug 19 04:41:21 PM PDT 24
Peak memory 226156 kb
Host smart-90b88ad4-d13c-49a7-a6c2-ebf5941c0123
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077931677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3077931677
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3591550690
Short name T323
Test name
Test status
Simulation time 327804888 ps
CPU time 11.74 seconds
Started Aug 19 04:41:01 PM PDT 24
Finished Aug 19 04:41:13 PM PDT 24
Peak memory 226088 kb
Host smart-d2828c94-43d4-4f83-9494-9d0f1baef1e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591550690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3591550690
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2099362736
Short name T560
Test name
Test status
Simulation time 1663501979 ps
CPU time 9.32 seconds
Started Aug 19 04:41:04 PM PDT 24
Finished Aug 19 04:41:13 PM PDT 24
Peak memory 226116 kb
Host smart-202cf5b3-8933-48f4-adfe-e30f84a9b192
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099362736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2099362736
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1982878383
Short name T224
Test name
Test status
Simulation time 514716582 ps
CPU time 7.88 seconds
Started Aug 19 04:41:01 PM PDT 24
Finished Aug 19 04:41:08 PM PDT 24
Peak memory 217720 kb
Host smart-24dec3b5-b9dd-4787-9ad8-4bf6af174671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982878383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1982878383
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1767267892
Short name T544
Test name
Test status
Simulation time 43355970 ps
CPU time 2.56 seconds
Started Aug 19 04:41:02 PM PDT 24
Finished Aug 19 04:41:04 PM PDT 24
Peak memory 222604 kb
Host smart-bf0d7c08-b99d-4baa-8b28-a6ac4c0b6d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767267892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1767267892
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1039633381
Short name T95
Test name
Test status
Simulation time 400472516 ps
CPU time 29.16 seconds
Started Aug 19 04:41:00 PM PDT 24
Finished Aug 19 04:41:29 PM PDT 24
Peak memory 251008 kb
Host smart-21c8b031-50b2-477d-ad0f-76de8af005fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039633381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1039633381
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2744774514
Short name T798
Test name
Test status
Simulation time 1453849222 ps
CPU time 4.32 seconds
Started Aug 19 04:41:02 PM PDT 24
Finished Aug 19 04:41:06 PM PDT 24
Peak memory 226412 kb
Host smart-57083aa6-9e68-48e2-87ae-d124f864c218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744774514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2744774514
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.667783204
Short name T827
Test name
Test status
Simulation time 25901927501 ps
CPU time 269.2 seconds
Started Aug 19 04:41:04 PM PDT 24
Finished Aug 19 04:45:33 PM PDT 24
Peak memory 251056 kb
Host smart-2de3c45a-5367-43ac-990a-c80fdfb5f493
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667783204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.667783204
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1534893193
Short name T47
Test name
Test status
Simulation time 15472032 ps
CPU time 1.17 seconds
Started Aug 19 04:41:00 PM PDT 24
Finished Aug 19 04:41:01 PM PDT 24
Peak memory 212044 kb
Host smart-724ba118-66a9-4f58-bc45-e9bc95a4a551
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534893193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1534893193
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3093741557
Short name T521
Test name
Test status
Simulation time 19718488 ps
CPU time 1.16 seconds
Started Aug 19 04:41:11 PM PDT 24
Finished Aug 19 04:41:12 PM PDT 24
Peak memory 209136 kb
Host smart-27de5b42-87ab-41bb-bad0-22ea3d2465f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093741557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3093741557
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.723148197
Short name T483
Test name
Test status
Simulation time 779200108 ps
CPU time 12.06 seconds
Started Aug 19 04:41:03 PM PDT 24
Finished Aug 19 04:41:15 PM PDT 24
Peak memory 218360 kb
Host smart-4b43e61b-9af0-4499-9776-10f6c635b2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723148197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.723148197
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.899039422
Short name T567
Test name
Test status
Simulation time 1594527171 ps
CPU time 4.05 seconds
Started Aug 19 04:41:00 PM PDT 24
Finished Aug 19 04:41:05 PM PDT 24
Peak memory 217772 kb
Host smart-042b1528-7d97-41fb-9eff-834edbe5f4e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899039422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.899039422
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1388010720
Short name T534
Test name
Test status
Simulation time 266560549 ps
CPU time 3.04 seconds
Started Aug 19 04:41:00 PM PDT 24
Finished Aug 19 04:41:04 PM PDT 24
Peak memory 218340 kb
Host smart-6c58dc8f-b2c4-4ad0-8330-69d1d1556178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388010720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1388010720
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2492761932
Short name T451
Test name
Test status
Simulation time 1395071049 ps
CPU time 17.37 seconds
Started Aug 19 04:41:04 PM PDT 24
Finished Aug 19 04:41:22 PM PDT 24
Peak memory 218596 kb
Host smart-81411fdc-da33-4ce3-8bb4-cf116e6b528c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492761932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2492761932
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3702596991
Short name T805
Test name
Test status
Simulation time 496742461 ps
CPU time 10.71 seconds
Started Aug 19 04:41:06 PM PDT 24
Finished Aug 19 04:41:16 PM PDT 24
Peak memory 226112 kb
Host smart-3267514c-7c82-4c73-9bd5-21b54c7d1608
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702596991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3702596991
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3439174303
Short name T417
Test name
Test status
Simulation time 1377596097 ps
CPU time 12.72 seconds
Started Aug 19 04:41:05 PM PDT 24
Finished Aug 19 04:41:18 PM PDT 24
Peak memory 218228 kb
Host smart-2e997787-69f7-4eb8-8523-7da0fe80e9a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439174303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3439174303
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3761502785
Short name T179
Test name
Test status
Simulation time 375709892 ps
CPU time 9.31 seconds
Started Aug 19 04:41:05 PM PDT 24
Finished Aug 19 04:41:15 PM PDT 24
Peak memory 218424 kb
Host smart-70bd74b7-5f70-4d74-8532-52238a522ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761502785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3761502785
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2018428737
Short name T497
Test name
Test status
Simulation time 131970769 ps
CPU time 2.99 seconds
Started Aug 19 04:41:01 PM PDT 24
Finished Aug 19 04:41:04 PM PDT 24
Peak memory 215012 kb
Host smart-2c10c138-f299-4e96-89b1-6ec4b6046c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018428737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2018428737
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.4199140918
Short name T490
Test name
Test status
Simulation time 805501241 ps
CPU time 19.22 seconds
Started Aug 19 04:41:05 PM PDT 24
Finished Aug 19 04:41:24 PM PDT 24
Peak memory 246160 kb
Host smart-8322c033-6b1d-4687-abb9-aade9420f705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199140918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.4199140918
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.373105188
Short name T178
Test name
Test status
Simulation time 336277172 ps
CPU time 7.33 seconds
Started Aug 19 04:41:00 PM PDT 24
Finished Aug 19 04:41:07 PM PDT 24
Peak memory 250936 kb
Host smart-c82a046e-3fc5-43b8-8b62-b3f8df531ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373105188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.373105188
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.717914146
Short name T435
Test name
Test status
Simulation time 11367893296 ps
CPU time 316.5 seconds
Started Aug 19 04:41:17 PM PDT 24
Finished Aug 19 04:46:34 PM PDT 24
Peak memory 282216 kb
Host smart-dfb9a50f-cf2f-4540-86b7-31cc4eb69de6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717914146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.717914146
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.692756222
Short name T151
Test name
Test status
Simulation time 2128674673 ps
CPU time 70.4 seconds
Started Aug 19 04:41:05 PM PDT 24
Finished Aug 19 04:42:16 PM PDT 24
Peak memory 272548 kb
Host smart-0038221c-87e4-4fb7-a017-bf4d9e9314ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=692756222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.692756222
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2063615951
Short name T185
Test name
Test status
Simulation time 45256259 ps
CPU time 0.79 seconds
Started Aug 19 04:41:02 PM PDT 24
Finished Aug 19 04:41:02 PM PDT 24
Peak memory 209016 kb
Host smart-39f03503-a872-438e-95ee-4eba4015f0a1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063615951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2063615951
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.741888633
Short name T389
Test name
Test status
Simulation time 30782434 ps
CPU time 0.91 seconds
Started Aug 19 04:41:06 PM PDT 24
Finished Aug 19 04:41:07 PM PDT 24
Peak memory 208968 kb
Host smart-28f068f9-7977-4edb-b339-86fab3c2fe8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741888633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.741888633
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2831769570
Short name T394
Test name
Test status
Simulation time 635206030 ps
CPU time 12.79 seconds
Started Aug 19 04:41:08 PM PDT 24
Finished Aug 19 04:41:21 PM PDT 24
Peak memory 218280 kb
Host smart-e3d2c15a-aecb-4a74-958e-4bc6b886c46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831769570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2831769570
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3459794247
Short name T395
Test name
Test status
Simulation time 3413582827 ps
CPU time 18.06 seconds
Started Aug 19 04:41:05 PM PDT 24
Finished Aug 19 04:41:23 PM PDT 24
Peak memory 217840 kb
Host smart-98e00428-dfec-4cc5-9a36-1e98904e1c76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459794247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3459794247
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3739289387
Short name T450
Test name
Test status
Simulation time 122370981 ps
CPU time 3.1 seconds
Started Aug 19 04:41:08 PM PDT 24
Finished Aug 19 04:41:11 PM PDT 24
Peak memory 218340 kb
Host smart-e2ebb0ec-10ad-4bd0-95b7-5e9c1d566de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739289387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3739289387
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.93557620
Short name T707
Test name
Test status
Simulation time 626796151 ps
CPU time 10.25 seconds
Started Aug 19 04:41:02 PM PDT 24
Finished Aug 19 04:41:12 PM PDT 24
Peak memory 219016 kb
Host smart-f6cbb4ad-e09c-4c14-a769-23cf6d2ec78d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93557620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.93557620
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.4027611905
Short name T559
Test name
Test status
Simulation time 538239408 ps
CPU time 15.21 seconds
Started Aug 19 04:41:08 PM PDT 24
Finished Aug 19 04:41:23 PM PDT 24
Peak memory 226076 kb
Host smart-7de5d425-7a34-4b55-a905-6b624eefbf17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027611905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.4027611905
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2694872313
Short name T31
Test name
Test status
Simulation time 1432307687 ps
CPU time 10.76 seconds
Started Aug 19 04:41:11 PM PDT 24
Finished Aug 19 04:41:22 PM PDT 24
Peak memory 218260 kb
Host smart-9c9131a8-7749-4202-b228-27051312ad54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694872313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2694872313
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.501574876
Short name T44
Test name
Test status
Simulation time 1538957911 ps
CPU time 9.95 seconds
Started Aug 19 04:41:10 PM PDT 24
Finished Aug 19 04:41:20 PM PDT 24
Peak memory 218384 kb
Host smart-fc71fbbe-4256-407d-aa60-2dcf863ee0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501574876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.501574876
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1097135722
Short name T73
Test name
Test status
Simulation time 66169911 ps
CPU time 2.54 seconds
Started Aug 19 04:41:04 PM PDT 24
Finished Aug 19 04:41:06 PM PDT 24
Peak memory 214744 kb
Host smart-43538dc4-23ef-44af-97dd-4933db0bf23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097135722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1097135722
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2149475332
Short name T492
Test name
Test status
Simulation time 226889682 ps
CPU time 25.18 seconds
Started Aug 19 04:41:09 PM PDT 24
Finished Aug 19 04:41:35 PM PDT 24
Peak memory 251004 kb
Host smart-ab67545e-5e8f-4cad-8d21-a4dd4678c552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149475332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2149475332
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2837237676
Short name T740
Test name
Test status
Simulation time 72682166 ps
CPU time 3.31 seconds
Started Aug 19 04:41:07 PM PDT 24
Finished Aug 19 04:41:11 PM PDT 24
Peak memory 222432 kb
Host smart-75568d34-5c52-4f98-afce-10270f52a613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837237676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2837237676
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2614855836
Short name T460
Test name
Test status
Simulation time 10919504796 ps
CPU time 87.48 seconds
Started Aug 19 04:41:05 PM PDT 24
Finished Aug 19 04:42:32 PM PDT 24
Peak memory 252324 kb
Host smart-b47c6e56-9002-434f-a836-8fcc3414d89e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614855836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2614855836
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2120495060
Short name T108
Test name
Test status
Simulation time 23139071 ps
CPU time 1.03 seconds
Started Aug 19 04:41:05 PM PDT 24
Finished Aug 19 04:41:06 PM PDT 24
Peak memory 212040 kb
Host smart-19ba8665-d0db-47e5-a030-5517ce71dca6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120495060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2120495060
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.755238914
Short name T331
Test name
Test status
Simulation time 171811059 ps
CPU time 1.08 seconds
Started Aug 19 04:41:10 PM PDT 24
Finished Aug 19 04:41:11 PM PDT 24
Peak memory 209028 kb
Host smart-784972f1-31be-43dc-b63c-cdce03a17ed2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755238914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.755238914
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.887866078
Short name T806
Test name
Test status
Simulation time 527951456 ps
CPU time 9.31 seconds
Started Aug 19 04:41:06 PM PDT 24
Finished Aug 19 04:41:15 PM PDT 24
Peak memory 218456 kb
Host smart-cb2346de-8b97-4de3-9561-a45601eae740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887866078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.887866078
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.4261820222
Short name T573
Test name
Test status
Simulation time 1951325857 ps
CPU time 5.14 seconds
Started Aug 19 04:41:08 PM PDT 24
Finished Aug 19 04:41:13 PM PDT 24
Peak memory 217764 kb
Host smart-2ca95fce-820b-48d1-8563-7013462879ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261820222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.4261820222
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1114754272
Short name T859
Test name
Test status
Simulation time 1000373329 ps
CPU time 25.85 seconds
Started Aug 19 04:41:17 PM PDT 24
Finished Aug 19 04:41:43 PM PDT 24
Peak memory 226084 kb
Host smart-fbd42170-2b1c-433b-9208-638ce0235b27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114754272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1114754272
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2489292157
Short name T552
Test name
Test status
Simulation time 1306053099 ps
CPU time 8.78 seconds
Started Aug 19 04:41:15 PM PDT 24
Finished Aug 19 04:41:24 PM PDT 24
Peak memory 226104 kb
Host smart-fb22a922-ce2e-4d37-8743-a97c4d0358ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489292157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2489292157
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.411191113
Short name T60
Test name
Test status
Simulation time 345157939 ps
CPU time 6.41 seconds
Started Aug 19 04:41:09 PM PDT 24
Finished Aug 19 04:41:15 PM PDT 24
Peak memory 218440 kb
Host smart-94cfbde4-7aaf-44e4-929a-36d2547d1cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411191113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.411191113
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.37528737
Short name T680
Test name
Test status
Simulation time 32507932 ps
CPU time 2.46 seconds
Started Aug 19 04:41:08 PM PDT 24
Finished Aug 19 04:41:10 PM PDT 24
Peak memory 223712 kb
Host smart-a7316d5f-dfd0-450b-b8d6-60351d473c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37528737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.37528737
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2665751344
Short name T636
Test name
Test status
Simulation time 671165320 ps
CPU time 29.04 seconds
Started Aug 19 04:41:09 PM PDT 24
Finished Aug 19 04:41:38 PM PDT 24
Peak memory 250996 kb
Host smart-d3cc27aa-597a-4dbf-a941-f2889e347980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665751344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2665751344
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1326060527
Short name T494
Test name
Test status
Simulation time 373082827 ps
CPU time 8.47 seconds
Started Aug 19 04:41:07 PM PDT 24
Finished Aug 19 04:41:15 PM PDT 24
Peak memory 250996 kb
Host smart-3ad05b73-fdb2-403a-9b1f-70e02c6e398d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326060527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1326060527
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.4144676645
Short name T517
Test name
Test status
Simulation time 2956118898 ps
CPU time 93.84 seconds
Started Aug 19 04:41:08 PM PDT 24
Finished Aug 19 04:42:42 PM PDT 24
Peak memory 251020 kb
Host smart-550ab656-c5c3-4aa4-a404-3a7036edc870
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144676645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.4144676645
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1873613070
Short name T275
Test name
Test status
Simulation time 24537068 ps
CPU time 0.91 seconds
Started Aug 19 04:41:05 PM PDT 24
Finished Aug 19 04:41:06 PM PDT 24
Peak memory 212068 kb
Host smart-281e7a75-b9c4-45bc-bcab-e672ea333f35
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873613070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1873613070
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3846513050
Short name T713
Test name
Test status
Simulation time 51592380 ps
CPU time 0.85 seconds
Started Aug 19 04:41:05 PM PDT 24
Finished Aug 19 04:41:06 PM PDT 24
Peak memory 208868 kb
Host smart-2d53de78-1154-4072-919f-5d9319549ff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846513050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3846513050
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2116327959
Short name T590
Test name
Test status
Simulation time 3364751772 ps
CPU time 21.35 seconds
Started Aug 19 04:41:17 PM PDT 24
Finished Aug 19 04:41:39 PM PDT 24
Peak memory 218464 kb
Host smart-86715386-b541-4d64-a271-d8f8a544f396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116327959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2116327959
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.478102438
Short name T27
Test name
Test status
Simulation time 1575761203 ps
CPU time 8.51 seconds
Started Aug 19 04:41:06 PM PDT 24
Finished Aug 19 04:41:15 PM PDT 24
Peak memory 217344 kb
Host smart-9de5710a-187c-4c4a-bfbb-000eb2b0e859
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478102438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.478102438
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1178860731
Short name T610
Test name
Test status
Simulation time 39274468 ps
CPU time 2.06 seconds
Started Aug 19 04:41:04 PM PDT 24
Finished Aug 19 04:41:06 PM PDT 24
Peak memory 218188 kb
Host smart-132e79af-5674-4037-85b3-7dda865d2be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178860731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1178860731
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3449072275
Short name T837
Test name
Test status
Simulation time 516258957 ps
CPU time 11.41 seconds
Started Aug 19 04:41:05 PM PDT 24
Finished Aug 19 04:41:16 PM PDT 24
Peak memory 226156 kb
Host smart-3688e957-878e-4015-902e-330d233f9239
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449072275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3449072275
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3325575579
Short name T868
Test name
Test status
Simulation time 1759900022 ps
CPU time 11.75 seconds
Started Aug 19 04:41:10 PM PDT 24
Finished Aug 19 04:41:22 PM PDT 24
Peak memory 226060 kb
Host smart-9860db65-6605-458d-b335-9edfd7de4a57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325575579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3325575579
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1083404421
Short name T547
Test name
Test status
Simulation time 346863513 ps
CPU time 12.98 seconds
Started Aug 19 04:41:17 PM PDT 24
Finished Aug 19 04:41:31 PM PDT 24
Peak memory 218260 kb
Host smart-18706f8f-febd-448a-b844-aeb2f95b283a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083404421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1083404421
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.760815704
Short name T347
Test name
Test status
Simulation time 365952060 ps
CPU time 12.49 seconds
Started Aug 19 04:41:08 PM PDT 24
Finished Aug 19 04:41:20 PM PDT 24
Peak memory 218308 kb
Host smart-3187941e-11ec-45aa-b1f3-854ec6d76534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760815704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.760815704
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.522462003
Short name T613
Test name
Test status
Simulation time 51913538 ps
CPU time 1.92 seconds
Started Aug 19 04:41:04 PM PDT 24
Finished Aug 19 04:41:06 PM PDT 24
Peak memory 217768 kb
Host smart-93703e73-60b8-4c6e-8796-f4a1f8685f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522462003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.522462003
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.693610576
Short name T463
Test name
Test status
Simulation time 970864921 ps
CPU time 23.98 seconds
Started Aug 19 04:41:04 PM PDT 24
Finished Aug 19 04:41:28 PM PDT 24
Peak memory 251020 kb
Host smart-f8200fe6-29e0-49ba-b3d4-6b5e52c372d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693610576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.693610576
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1958601875
Short name T647
Test name
Test status
Simulation time 54871695 ps
CPU time 7.19 seconds
Started Aug 19 04:41:05 PM PDT 24
Finished Aug 19 04:41:12 PM PDT 24
Peak memory 250988 kb
Host smart-b1eb33b4-d438-43b0-af7f-fc1b21f940e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958601875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1958601875
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1636596559
Short name T111
Test name
Test status
Simulation time 14560467139 ps
CPU time 133.58 seconds
Started Aug 19 04:41:04 PM PDT 24
Finished Aug 19 04:43:18 PM PDT 24
Peak memory 224992 kb
Host smart-5c3ebe9d-28e5-4243-a75b-ab8cf90eb975
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636596559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1636596559
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2307637601
Short name T466
Test name
Test status
Simulation time 15030674 ps
CPU time 1.13 seconds
Started Aug 19 04:41:10 PM PDT 24
Finished Aug 19 04:41:11 PM PDT 24
Peak memory 212088 kb
Host smart-fae9fa5e-2b81-42d6-9a0e-266a67de52b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307637601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2307637601
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2650516222
Short name T386
Test name
Test status
Simulation time 12574348 ps
CPU time 0.83 seconds
Started Aug 19 04:41:20 PM PDT 24
Finished Aug 19 04:41:21 PM PDT 24
Peak memory 208828 kb
Host smart-0d995116-6edf-43bb-ae37-22ecf3d8c580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650516222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2650516222
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2302275843
Short name T458
Test name
Test status
Simulation time 390050963 ps
CPU time 10.67 seconds
Started Aug 19 04:41:06 PM PDT 24
Finished Aug 19 04:41:17 PM PDT 24
Peak memory 218336 kb
Host smart-4c76c919-7e05-4d19-a1e2-89dddfec16f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302275843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2302275843
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.610007915
Short name T735
Test name
Test status
Simulation time 13838703208 ps
CPU time 13.15 seconds
Started Aug 19 04:41:08 PM PDT 24
Finished Aug 19 04:41:21 PM PDT 24
Peak memory 217860 kb
Host smart-bf45bf18-5117-44bc-9e8e-cd2ca1f66bfd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610007915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.610007915
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.156752640
Short name T836
Test name
Test status
Simulation time 137177086 ps
CPU time 2.34 seconds
Started Aug 19 04:41:17 PM PDT 24
Finished Aug 19 04:41:20 PM PDT 24
Peak memory 218340 kb
Host smart-29883233-895b-4dea-ba16-ce01d2bf2993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156752640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.156752640
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.4035481632
Short name T689
Test name
Test status
Simulation time 420772385 ps
CPU time 10.74 seconds
Started Aug 19 04:41:10 PM PDT 24
Finished Aug 19 04:41:21 PM PDT 24
Peak memory 218380 kb
Host smart-deca39ab-1006-41e5-8be9-286ce24ab7ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035481632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.4035481632
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.302268585
Short name T835
Test name
Test status
Simulation time 513440437 ps
CPU time 10.97 seconds
Started Aug 19 04:41:10 PM PDT 24
Finished Aug 19 04:41:21 PM PDT 24
Peak memory 226096 kb
Host smart-41e97aaf-5c7e-4ef8-9a27-e5404d1147ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302268585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.302268585
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3584497393
Short name T338
Test name
Test status
Simulation time 234632600 ps
CPU time 8.52 seconds
Started Aug 19 04:41:06 PM PDT 24
Finished Aug 19 04:41:14 PM PDT 24
Peak memory 226056 kb
Host smart-3c27e772-0825-42e8-8bd4-d59e1e79aa2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584497393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3584497393
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2587752587
Short name T742
Test name
Test status
Simulation time 2708809245 ps
CPU time 13.27 seconds
Started Aug 19 04:41:09 PM PDT 24
Finished Aug 19 04:41:22 PM PDT 24
Peak memory 226200 kb
Host smart-0c8c317b-44ab-49d4-b536-b8be06511ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587752587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2587752587
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.4224017966
Short name T406
Test name
Test status
Simulation time 52600485 ps
CPU time 1.48 seconds
Started Aug 19 04:41:05 PM PDT 24
Finished Aug 19 04:41:07 PM PDT 24
Peak memory 213948 kb
Host smart-19f59626-995f-41f0-9d90-f93e6733581b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224017966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.4224017966
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1579644337
Short name T473
Test name
Test status
Simulation time 293270018 ps
CPU time 27.93 seconds
Started Aug 19 04:41:15 PM PDT 24
Finished Aug 19 04:41:43 PM PDT 24
Peak memory 251000 kb
Host smart-f077fe50-d3a5-461c-8cad-072ca1c70c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579644337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1579644337
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2874354296
Short name T575
Test name
Test status
Simulation time 133706641 ps
CPU time 8.1 seconds
Started Aug 19 04:41:15 PM PDT 24
Finished Aug 19 04:41:24 PM PDT 24
Peak memory 250996 kb
Host smart-d2b62e52-d0d4-4856-8e10-422a74352837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874354296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2874354296
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3512912083
Short name T802
Test name
Test status
Simulation time 2146465660 ps
CPU time 72.59 seconds
Started Aug 19 04:41:11 PM PDT 24
Finished Aug 19 04:42:24 PM PDT 24
Peak memory 275592 kb
Host smart-2b0c7f5e-2f01-4219-8476-2741eb857552
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512912083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3512912083
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2554542870
Short name T730
Test name
Test status
Simulation time 12609503 ps
CPU time 0.92 seconds
Started Aug 19 04:41:04 PM PDT 24
Finished Aug 19 04:41:05 PM PDT 24
Peak memory 209080 kb
Host smart-c51923f1-eedf-45ea-bba5-a9190ccaeb35
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554542870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2554542870
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.119551813
Short name T665
Test name
Test status
Simulation time 118821288 ps
CPU time 0.78 seconds
Started Aug 19 04:39:05 PM PDT 24
Finished Aug 19 04:39:06 PM PDT 24
Peak memory 208820 kb
Host smart-426a95a9-68ad-43f9-a8af-835acaeaf17f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119551813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.119551813
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.4174147521
Short name T218
Test name
Test status
Simulation time 39017553 ps
CPU time 0.76 seconds
Started Aug 19 04:39:04 PM PDT 24
Finished Aug 19 04:39:05 PM PDT 24
Peak memory 209020 kb
Host smart-613c8ff3-ea72-4e5a-91db-87382a6db9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174147521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.4174147521
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.548764815
Short name T468
Test name
Test status
Simulation time 184180846 ps
CPU time 9.16 seconds
Started Aug 19 04:39:14 PM PDT 24
Finished Aug 19 04:39:23 PM PDT 24
Peak memory 226184 kb
Host smart-8e74f444-46af-4d32-933b-02a458c9091d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548764815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.548764815
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.389348547
Short name T25
Test name
Test status
Simulation time 1026238508 ps
CPU time 11.86 seconds
Started Aug 19 04:39:05 PM PDT 24
Finished Aug 19 04:39:16 PM PDT 24
Peak memory 217168 kb
Host smart-5d3d0f19-3d6d-48c8-aa50-8f2eba7d6c58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389348547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.389348547
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3646049796
Short name T320
Test name
Test status
Simulation time 3471555689 ps
CPU time 51.46 seconds
Started Aug 19 04:39:07 PM PDT 24
Finished Aug 19 04:39:58 PM PDT 24
Peak memory 219020 kb
Host smart-811614a6-c890-4ac1-9d0d-d40b9489e917
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646049796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3646049796
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.717132282
Short name T723
Test name
Test status
Simulation time 508449156 ps
CPU time 3.94 seconds
Started Aug 19 04:39:14 PM PDT 24
Finished Aug 19 04:39:18 PM PDT 24
Peak memory 217772 kb
Host smart-4948dc9d-e72d-4275-9f4d-59c0f41420d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717132282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.717132282
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.329192491
Short name T378
Test name
Test status
Simulation time 904131246 ps
CPU time 6.79 seconds
Started Aug 19 04:39:08 PM PDT 24
Finished Aug 19 04:39:15 PM PDT 24
Peak memory 218256 kb
Host smart-9187fb94-29a3-48c1-8ee2-c023ed23ded8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329192491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.329192491
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3915840891
Short name T300
Test name
Test status
Simulation time 6307037715 ps
CPU time 17.45 seconds
Started Aug 19 04:39:13 PM PDT 24
Finished Aug 19 04:39:31 PM PDT 24
Peak memory 217760 kb
Host smart-8a7a5c8c-2712-49b8-a61e-a04a02a64d12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915840891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3915840891
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3370835612
Short name T72
Test name
Test status
Simulation time 1177688659 ps
CPU time 5.07 seconds
Started Aug 19 04:39:04 PM PDT 24
Finished Aug 19 04:39:09 PM PDT 24
Peak memory 217668 kb
Host smart-c4005bdb-2add-43a8-90cf-0c2581b14baa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370835612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3370835612
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2882251815
Short name T703
Test name
Test status
Simulation time 7731863097 ps
CPU time 57.88 seconds
Started Aug 19 04:39:06 PM PDT 24
Finished Aug 19 04:40:04 PM PDT 24
Peak memory 267612 kb
Host smart-f82ed549-3361-490d-80fa-88fd4841573f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882251815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2882251815
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.4231816356
Short name T846
Test name
Test status
Simulation time 3404984164 ps
CPU time 23.37 seconds
Started Aug 19 04:39:12 PM PDT 24
Finished Aug 19 04:39:35 PM PDT 24
Peak memory 250452 kb
Host smart-758b39b1-e0f0-4c5a-8d73-22852e389fa6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231816356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.4231816356
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.4171490732
Short name T545
Test name
Test status
Simulation time 48783166 ps
CPU time 2.26 seconds
Started Aug 19 04:39:11 PM PDT 24
Finished Aug 19 04:39:14 PM PDT 24
Peak memory 218352 kb
Host smart-cb389e4c-6d6d-4ea4-a6e8-6a8a064cdf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171490732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.4171490732
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3661713753
Short name T191
Test name
Test status
Simulation time 753485790 ps
CPU time 12.94 seconds
Started Aug 19 04:39:08 PM PDT 24
Finished Aug 19 04:39:21 PM PDT 24
Peak memory 217708 kb
Host smart-a95a63aa-db09-46b9-9d69-a1bafad98b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661713753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3661713753
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2814078786
Short name T104
Test name
Test status
Simulation time 119295596 ps
CPU time 23.06 seconds
Started Aug 19 04:39:12 PM PDT 24
Finished Aug 19 04:39:35 PM PDT 24
Peak memory 269136 kb
Host smart-7ca5d296-61f1-4bcc-9550-3daa0580e9be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814078786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2814078786
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2724999177
Short name T625
Test name
Test status
Simulation time 1200505106 ps
CPU time 10.99 seconds
Started Aug 19 04:39:04 PM PDT 24
Finished Aug 19 04:39:15 PM PDT 24
Peak memory 219012 kb
Host smart-282b13c4-5650-4d58-9616-cc3836c23ef8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724999177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2724999177
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.989953813
Short name T277
Test name
Test status
Simulation time 2541257605 ps
CPU time 7.59 seconds
Started Aug 19 04:39:09 PM PDT 24
Finished Aug 19 04:39:17 PM PDT 24
Peak memory 226168 kb
Host smart-c350856b-454d-45c8-bbc2-3018b7e976e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989953813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.989953813
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3337148537
Short name T299
Test name
Test status
Simulation time 331238031 ps
CPU time 12 seconds
Started Aug 19 04:39:03 PM PDT 24
Finished Aug 19 04:39:15 PM PDT 24
Peak memory 218296 kb
Host smart-5f48d0a5-b2fc-4b0a-ba34-92fe251332ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337148537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
337148537
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3882924687
Short name T709
Test name
Test status
Simulation time 992722638 ps
CPU time 10.05 seconds
Started Aug 19 04:39:06 PM PDT 24
Finished Aug 19 04:39:16 PM PDT 24
Peak memory 218408 kb
Host smart-68e36ab1-72a7-4509-9aa9-847d97170993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882924687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3882924687
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3489695653
Short name T85
Test name
Test status
Simulation time 154371012 ps
CPU time 3.07 seconds
Started Aug 19 04:38:58 PM PDT 24
Finished Aug 19 04:39:01 PM PDT 24
Peak memory 217800 kb
Host smart-c618bbd1-668a-4b8b-a722-5fdfdfa70e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489695653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3489695653
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1758736848
Short name T871
Test name
Test status
Simulation time 1080524603 ps
CPU time 25.43 seconds
Started Aug 19 04:40:06 PM PDT 24
Finished Aug 19 04:40:33 PM PDT 24
Peak memory 249072 kb
Host smart-052156dc-8e44-408c-892d-d8b527aea98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758736848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1758736848
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3297743028
Short name T487
Test name
Test status
Simulation time 249181522 ps
CPU time 6.93 seconds
Started Aug 19 04:39:06 PM PDT 24
Finished Aug 19 04:39:13 PM PDT 24
Peak memory 251004 kb
Host smart-34af1e83-0623-44c2-8a4d-7b0274bba422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297743028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3297743028
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.4056332254
Short name T375
Test name
Test status
Simulation time 63634547273 ps
CPU time 148.18 seconds
Started Aug 19 04:39:13 PM PDT 24
Finished Aug 19 04:41:42 PM PDT 24
Peak memory 226232 kb
Host smart-34ec1503-9ee0-4ef6-9a8c-fbb7fc1c2fcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056332254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.4056332254
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3631966154
Short name T100
Test name
Test status
Simulation time 2014304508 ps
CPU time 13.13 seconds
Started Aug 19 04:39:08 PM PDT 24
Finished Aug 19 04:39:21 PM PDT 24
Peak memory 226212 kb
Host smart-dc858c2d-d12e-491e-a0d8-9af4461a1804
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3631966154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.3631966154
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3796693474
Short name T587
Test name
Test status
Simulation time 17703100 ps
CPU time 0.99 seconds
Started Aug 19 04:38:59 PM PDT 24
Finished Aug 19 04:39:00 PM PDT 24
Peak memory 213032 kb
Host smart-1390b359-1356-4ba4-849d-fa7311889098
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796693474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.3796693474
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3986850024
Short name T826
Test name
Test status
Simulation time 205887629 ps
CPU time 0.93 seconds
Started Aug 19 04:41:17 PM PDT 24
Finished Aug 19 04:41:19 PM PDT 24
Peak memory 209032 kb
Host smart-0e2e9fd1-f070-45f5-bfd0-2da1de5074cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986850024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3986850024
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1334886103
Short name T682
Test name
Test status
Simulation time 443670429 ps
CPU time 14.45 seconds
Started Aug 19 04:41:28 PM PDT 24
Finished Aug 19 04:41:43 PM PDT 24
Peak memory 218372 kb
Host smart-777e63e8-78f5-4d20-8dd1-da514981bc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334886103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1334886103
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.759263846
Short name T681
Test name
Test status
Simulation time 1336373127 ps
CPU time 5.39 seconds
Started Aug 19 04:41:21 PM PDT 24
Finished Aug 19 04:41:26 PM PDT 24
Peak memory 217776 kb
Host smart-7c3fe574-994f-4d93-87f4-ad8bc8ccf6b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759263846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.759263846
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.4277796601
Short name T301
Test name
Test status
Simulation time 462898630 ps
CPU time 2.02 seconds
Started Aug 19 04:41:19 PM PDT 24
Finished Aug 19 04:41:21 PM PDT 24
Peak memory 218424 kb
Host smart-0727dab1-e8fb-4030-9a0e-84aa58712a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277796601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.4277796601
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2016911234
Short name T784
Test name
Test status
Simulation time 617548896 ps
CPU time 9.37 seconds
Started Aug 19 04:41:16 PM PDT 24
Finished Aug 19 04:41:26 PM PDT 24
Peak memory 218372 kb
Host smart-4eb02690-c5c0-4e2d-bfba-12f62fa97d4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016911234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2016911234
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2651823646
Short name T1
Test name
Test status
Simulation time 7654270140 ps
CPU time 13.9 seconds
Started Aug 19 04:41:15 PM PDT 24
Finished Aug 19 04:41:29 PM PDT 24
Peak memory 226164 kb
Host smart-4cd95d3a-ab75-43e4-81d6-df799d7694bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651823646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2651823646
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3763748574
Short name T294
Test name
Test status
Simulation time 989730066 ps
CPU time 9.28 seconds
Started Aug 19 04:41:17 PM PDT 24
Finished Aug 19 04:41:27 PM PDT 24
Peak memory 218324 kb
Host smart-6f586435-5944-4087-a625-e5f3132bcbe0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763748574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3763748574
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2044924142
Short name T226
Test name
Test status
Simulation time 3316563433 ps
CPU time 11.52 seconds
Started Aug 19 04:41:16 PM PDT 24
Finished Aug 19 04:41:28 PM PDT 24
Peak memory 226212 kb
Host smart-c51b78ab-38ab-4a24-a66e-5a9b5d75b618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044924142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2044924142
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.338097195
Short name T106
Test name
Test status
Simulation time 111783133 ps
CPU time 3.25 seconds
Started Aug 19 04:41:14 PM PDT 24
Finished Aug 19 04:41:18 PM PDT 24
Peak memory 215116 kb
Host smart-3676d335-f85d-4b42-8937-d70dabd5f501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338097195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.338097195
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.952872174
Short name T819
Test name
Test status
Simulation time 584272184 ps
CPU time 23.02 seconds
Started Aug 19 04:41:22 PM PDT 24
Finished Aug 19 04:41:45 PM PDT 24
Peak memory 250616 kb
Host smart-ab6fc6c2-eb75-4b50-8287-545349036ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952872174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.952872174
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2286126117
Short name T254
Test name
Test status
Simulation time 48408326 ps
CPU time 8.66 seconds
Started Aug 19 04:41:16 PM PDT 24
Finished Aug 19 04:41:25 PM PDT 24
Peak memory 250992 kb
Host smart-e13e0ec2-0db4-43e7-b6ce-103a012dc20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286126117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2286126117
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1929198052
Short name T92
Test name
Test status
Simulation time 39851313585 ps
CPU time 187.68 seconds
Started Aug 19 04:41:15 PM PDT 24
Finished Aug 19 04:44:23 PM PDT 24
Peak memory 222832 kb
Host smart-4d518d98-2166-4eed-9e19-b0e3ffd9fe85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929198052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1929198052
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1907466097
Short name T578
Test name
Test status
Simulation time 14731289 ps
CPU time 1 seconds
Started Aug 19 04:41:17 PM PDT 24
Finished Aug 19 04:41:18 PM PDT 24
Peak memory 209116 kb
Host smart-6aaa0e19-60a5-4906-829c-08f7696e2771
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907466097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1907466097
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1178041155
Short name T381
Test name
Test status
Simulation time 42430495 ps
CPU time 1.04 seconds
Started Aug 19 04:41:22 PM PDT 24
Finished Aug 19 04:41:23 PM PDT 24
Peak memory 208960 kb
Host smart-3e4cdff5-eaa2-45a5-9614-3c79aaceb8fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178041155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1178041155
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3759938573
Short name T561
Test name
Test status
Simulation time 1383580467 ps
CPU time 9.95 seconds
Started Aug 19 04:41:16 PM PDT 24
Finished Aug 19 04:41:26 PM PDT 24
Peak memory 218380 kb
Host smart-305a74cf-b98a-4ac6-b962-0173c0eb606d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759938573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3759938573
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.216078704
Short name T594
Test name
Test status
Simulation time 1131854220 ps
CPU time 14.12 seconds
Started Aug 19 04:41:18 PM PDT 24
Finished Aug 19 04:41:33 PM PDT 24
Peak memory 217780 kb
Host smart-2fc91ec0-ba90-45d6-ace5-2671e0149ef8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216078704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.216078704
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1883238987
Short name T716
Test name
Test status
Simulation time 25244947 ps
CPU time 1.52 seconds
Started Aug 19 04:41:13 PM PDT 24
Finished Aug 19 04:41:15 PM PDT 24
Peak memory 218372 kb
Host smart-5286d344-7def-4842-9352-c1a331ce6a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883238987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1883238987
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.994985280
Short name T546
Test name
Test status
Simulation time 268958910 ps
CPU time 14.4 seconds
Started Aug 19 04:41:20 PM PDT 24
Finished Aug 19 04:41:34 PM PDT 24
Peak memory 219020 kb
Host smart-6fd71287-ffab-4fca-9c7f-0cd529cec29a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994985280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.994985280
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.333728068
Short name T530
Test name
Test status
Simulation time 1615389197 ps
CPU time 11.66 seconds
Started Aug 19 04:41:21 PM PDT 24
Finished Aug 19 04:41:33 PM PDT 24
Peak memory 226084 kb
Host smart-f33e376d-ac65-41fb-9478-563b9f81023b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333728068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.333728068
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1742703029
Short name T651
Test name
Test status
Simulation time 256789545 ps
CPU time 8.41 seconds
Started Aug 19 04:41:20 PM PDT 24
Finished Aug 19 04:41:28 PM PDT 24
Peak memory 218304 kb
Host smart-7c7aace7-7ba1-4208-a380-4c1314a1829d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742703029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1742703029
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.585954858
Short name T522
Test name
Test status
Simulation time 2378119832 ps
CPU time 11.54 seconds
Started Aug 19 04:41:22 PM PDT 24
Finished Aug 19 04:41:33 PM PDT 24
Peak memory 218480 kb
Host smart-b6f96bc3-1fb2-4794-8036-a56a69893ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585954858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.585954858
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.645034586
Short name T667
Test name
Test status
Simulation time 141800849 ps
CPU time 2.43 seconds
Started Aug 19 04:41:16 PM PDT 24
Finished Aug 19 04:41:18 PM PDT 24
Peak memory 217776 kb
Host smart-6f90dd4d-c456-4b3a-9d0d-52b2495626ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645034586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.645034586
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1124636199
Short name T814
Test name
Test status
Simulation time 3239374107 ps
CPU time 28.21 seconds
Started Aug 19 04:41:15 PM PDT 24
Finished Aug 19 04:41:44 PM PDT 24
Peak memory 251076 kb
Host smart-697c02dc-e0fc-448b-9992-96c50190ddfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124636199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1124636199
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3061991142
Short name T654
Test name
Test status
Simulation time 88668938 ps
CPU time 7.15 seconds
Started Aug 19 04:41:17 PM PDT 24
Finished Aug 19 04:41:25 PM PDT 24
Peak memory 251056 kb
Host smart-cf680475-7142-4f69-9273-4cbba89cbf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061991142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3061991142
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1939329885
Short name T418
Test name
Test status
Simulation time 7073770054 ps
CPU time 210 seconds
Started Aug 19 04:41:17 PM PDT 24
Finished Aug 19 04:44:47 PM PDT 24
Peak memory 251048 kb
Host smart-d358b3d3-202b-4d9a-a549-8d6ce25eadbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939329885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1939329885
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1069997984
Short name T40
Test name
Test status
Simulation time 12107134 ps
CPU time 0.93 seconds
Started Aug 19 04:41:15 PM PDT 24
Finished Aug 19 04:41:16 PM PDT 24
Peak memory 209052 kb
Host smart-50f31086-1e5b-49da-854c-775f58c2ea3a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069997984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1069997984
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3614878193
Short name T528
Test name
Test status
Simulation time 59832504 ps
CPU time 1.09 seconds
Started Aug 19 04:41:24 PM PDT 24
Finished Aug 19 04:41:25 PM PDT 24
Peak memory 209048 kb
Host smart-2b7af6bc-bde9-41cb-a7c1-3e91c8dc0701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614878193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3614878193
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3381568810
Short name T829
Test name
Test status
Simulation time 441425161 ps
CPU time 9.44 seconds
Started Aug 19 04:41:25 PM PDT 24
Finished Aug 19 04:41:35 PM PDT 24
Peak memory 226344 kb
Host smart-ee74b4dc-f55f-4c87-bc0f-866f85884094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381568810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3381568810
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.957357017
Short name T22
Test name
Test status
Simulation time 1065730675 ps
CPU time 6.01 seconds
Started Aug 19 04:41:24 PM PDT 24
Finished Aug 19 04:41:30 PM PDT 24
Peak memory 217492 kb
Host smart-db44b158-3f31-45f0-b1e5-4e4c4699959f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957357017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.957357017
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2949914647
Short name T356
Test name
Test status
Simulation time 50960722 ps
CPU time 2.34 seconds
Started Aug 19 04:41:26 PM PDT 24
Finished Aug 19 04:41:28 PM PDT 24
Peak memory 218348 kb
Host smart-71da7afe-fea6-49b9-a7e3-6b6def3d6287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949914647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2949914647
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3302675316
Short name T287
Test name
Test status
Simulation time 1440381340 ps
CPU time 15.94 seconds
Started Aug 19 04:41:33 PM PDT 24
Finished Aug 19 04:41:49 PM PDT 24
Peak memory 226172 kb
Host smart-0272bf01-ff60-40d7-bcf3-6ea5eda9970f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302675316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3302675316
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3052285596
Short name T377
Test name
Test status
Simulation time 2567969559 ps
CPU time 12.12 seconds
Started Aug 19 04:41:31 PM PDT 24
Finished Aug 19 04:41:43 PM PDT 24
Peak memory 226156 kb
Host smart-8eb5b527-6340-45c9-befa-5182de7df707
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052285596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3052285596
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.4084988645
Short name T350
Test name
Test status
Simulation time 599414441 ps
CPU time 7.99 seconds
Started Aug 19 04:41:32 PM PDT 24
Finished Aug 19 04:41:40 PM PDT 24
Peak memory 218320 kb
Host smart-a8c78e62-29cd-480d-bfd9-1c8c4c0d47fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084988645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
4084988645
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.335846529
Short name T765
Test name
Test status
Simulation time 1634844759 ps
CPU time 9.07 seconds
Started Aug 19 04:41:24 PM PDT 24
Finished Aug 19 04:41:33 PM PDT 24
Peak memory 218432 kb
Host smart-f666162c-c3fb-407e-88cd-8af6b6f3c78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335846529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.335846529
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1127482030
Short name T731
Test name
Test status
Simulation time 205513493 ps
CPU time 2.37 seconds
Started Aug 19 04:41:15 PM PDT 24
Finished Aug 19 04:41:18 PM PDT 24
Peak memory 217788 kb
Host smart-11c7f863-dee6-47aa-9273-4f19c8c58c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127482030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1127482030
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3277627219
Short name T400
Test name
Test status
Simulation time 284357592 ps
CPU time 22.27 seconds
Started Aug 19 04:41:32 PM PDT 24
Finished Aug 19 04:41:54 PM PDT 24
Peak memory 250972 kb
Host smart-5e2d29ab-7769-4591-84ca-45a6fc553aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277627219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3277627219
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2705050285
Short name T455
Test name
Test status
Simulation time 98572169 ps
CPU time 8.89 seconds
Started Aug 19 04:41:26 PM PDT 24
Finished Aug 19 04:41:35 PM PDT 24
Peak memory 250976 kb
Host smart-b3d38b5d-efa4-458f-84a0-51480ce97d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705050285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2705050285
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1622987653
Short name T739
Test name
Test status
Simulation time 11635884090 ps
CPU time 259.03 seconds
Started Aug 19 04:41:31 PM PDT 24
Finished Aug 19 04:45:50 PM PDT 24
Peak memory 250728 kb
Host smart-93624bf4-48dd-48e8-85e4-c05f61b08e01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622987653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1622987653
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3192402384
Short name T157
Test name
Test status
Simulation time 2596882736 ps
CPU time 33.55 seconds
Started Aug 19 04:41:34 PM PDT 24
Finished Aug 19 04:42:08 PM PDT 24
Peak memory 258972 kb
Host smart-2864f7d4-7549-49a0-8c4f-918a071c915c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3192402384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3192402384
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1071787742
Short name T272
Test name
Test status
Simulation time 33520342 ps
CPU time 0.82 seconds
Started Aug 19 04:41:26 PM PDT 24
Finished Aug 19 04:41:27 PM PDT 24
Peak memory 208880 kb
Host smart-a1bd1281-344c-498c-b695-2e0fd87bebcd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071787742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1071787742
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3661020527
Short name T729
Test name
Test status
Simulation time 49297807 ps
CPU time 1.1 seconds
Started Aug 19 04:41:37 PM PDT 24
Finished Aug 19 04:41:38 PM PDT 24
Peak memory 209044 kb
Host smart-339a2978-9800-4b11-bd19-269c8c73a690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661020527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3661020527
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1776005211
Short name T504
Test name
Test status
Simulation time 1705926575 ps
CPU time 14.27 seconds
Started Aug 19 04:41:36 PM PDT 24
Finished Aug 19 04:41:51 PM PDT 24
Peak memory 218352 kb
Host smart-3976459e-99b8-4f09-939f-db013f810fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776005211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1776005211
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.72602432
Short name T529
Test name
Test status
Simulation time 104297346 ps
CPU time 1.55 seconds
Started Aug 19 04:41:36 PM PDT 24
Finished Aug 19 04:41:37 PM PDT 24
Peak memory 217800 kb
Host smart-d9a4e54f-36df-441a-8347-58dee516ac88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72602432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.72602432
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.260269801
Short name T789
Test name
Test status
Simulation time 214145252 ps
CPU time 2.68 seconds
Started Aug 19 04:41:32 PM PDT 24
Finished Aug 19 04:41:35 PM PDT 24
Peak memory 222624 kb
Host smart-89cdaf99-ef4c-4235-9fa8-2e3f41212ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260269801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.260269801
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.387389521
Short name T472
Test name
Test status
Simulation time 1584722027 ps
CPU time 13.14 seconds
Started Aug 19 04:41:36 PM PDT 24
Finished Aug 19 04:41:49 PM PDT 24
Peak memory 226160 kb
Host smart-4b1b9d37-f50c-46ae-9e86-5fa271324fcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387389521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.387389521
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2631364871
Short name T537
Test name
Test status
Simulation time 784716595 ps
CPU time 17.67 seconds
Started Aug 19 04:41:34 PM PDT 24
Finished Aug 19 04:41:52 PM PDT 24
Peak memory 226060 kb
Host smart-5ff0f881-c3b0-4f7b-b141-d41bc4601243
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631364871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2631364871
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3433090830
Short name T442
Test name
Test status
Simulation time 1356510216 ps
CPU time 9.38 seconds
Started Aug 19 04:41:37 PM PDT 24
Finished Aug 19 04:41:46 PM PDT 24
Peak memory 226124 kb
Host smart-e2124150-d263-4b47-9c64-54345a68b122
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433090830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3433090830
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.179244547
Short name T372
Test name
Test status
Simulation time 1771628232 ps
CPU time 14.66 seconds
Started Aug 19 04:41:33 PM PDT 24
Finished Aug 19 04:41:47 PM PDT 24
Peak memory 218444 kb
Host smart-bbaf7cc1-161c-4b5a-a54c-e5369a131abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179244547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.179244547
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.8584153
Short name T661
Test name
Test status
Simulation time 217339005 ps
CPU time 1.72 seconds
Started Aug 19 04:41:25 PM PDT 24
Finished Aug 19 04:41:27 PM PDT 24
Peak memory 214252 kb
Host smart-7430e917-1b6d-43ef-9353-b987c12e2270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8584153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.8584153
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.503922160
Short name T427
Test name
Test status
Simulation time 256302981 ps
CPU time 33.35 seconds
Started Aug 19 04:41:26 PM PDT 24
Finished Aug 19 04:41:59 PM PDT 24
Peak memory 251012 kb
Host smart-60431f01-a972-404e-938f-e6d50503247d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503922160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.503922160
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1623417477
Short name T247
Test name
Test status
Simulation time 121839583 ps
CPU time 8.18 seconds
Started Aug 19 04:41:33 PM PDT 24
Finished Aug 19 04:41:41 PM PDT 24
Peak memory 250992 kb
Host smart-1fce4c84-98d2-4a51-915f-85e0faf5e29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623417477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1623417477
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2071680232
Short name T351
Test name
Test status
Simulation time 32755834608 ps
CPU time 126.81 seconds
Started Aug 19 04:41:36 PM PDT 24
Finished Aug 19 04:43:43 PM PDT 24
Peak memory 277832 kb
Host smart-adb3c43b-f63e-44a9-8b69-1c13d8685be0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071680232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2071680232
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1959872533
Short name T74
Test name
Test status
Simulation time 11788835 ps
CPU time 0.94 seconds
Started Aug 19 04:41:24 PM PDT 24
Finished Aug 19 04:41:25 PM PDT 24
Peak memory 212016 kb
Host smart-9ba9fdab-2026-4d5c-b48a-d37a65624599
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959872533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1959872533
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2276296900
Short name T509
Test name
Test status
Simulation time 13853633 ps
CPU time 1.06 seconds
Started Aug 19 04:41:51 PM PDT 24
Finished Aug 19 04:41:52 PM PDT 24
Peak memory 209016 kb
Host smart-a03ff99b-63f6-4ef5-9379-b115f370cf32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276296900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2276296900
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.872735559
Short name T330
Test name
Test status
Simulation time 1299629479 ps
CPU time 14.19 seconds
Started Aug 19 04:41:35 PM PDT 24
Finished Aug 19 04:41:50 PM PDT 24
Peak memory 218344 kb
Host smart-6fbfd997-762c-458d-a920-f062f0b53d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872735559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.872735559
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2765318834
Short name T26
Test name
Test status
Simulation time 863754878 ps
CPU time 5.77 seconds
Started Aug 19 04:41:50 PM PDT 24
Finished Aug 19 04:41:56 PM PDT 24
Peak memory 217836 kb
Host smart-f64e4066-546d-4a84-be29-7bf27bff1676
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765318834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2765318834
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1798255426
Short name T176
Test name
Test status
Simulation time 298262537 ps
CPU time 3.79 seconds
Started Aug 19 04:41:35 PM PDT 24
Finished Aug 19 04:41:39 PM PDT 24
Peak memory 218368 kb
Host smart-6e13341f-0ecc-41da-b8ce-5bcfbcf435dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798255426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1798255426
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3433731749
Short name T627
Test name
Test status
Simulation time 330571232 ps
CPU time 14.55 seconds
Started Aug 19 04:41:52 PM PDT 24
Finished Aug 19 04:42:06 PM PDT 24
Peak memory 219100 kb
Host smart-699ad0eb-b8c3-4748-bef0-6cb7b23be83b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433731749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3433731749
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1590568162
Short name T644
Test name
Test status
Simulation time 1186343286 ps
CPU time 8.66 seconds
Started Aug 19 04:41:50 PM PDT 24
Finished Aug 19 04:41:59 PM PDT 24
Peak memory 226076 kb
Host smart-3bc7b153-b66d-4fde-a494-b88dce0d6b7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590568162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1590568162
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3740659321
Short name T676
Test name
Test status
Simulation time 1780258819 ps
CPU time 10.82 seconds
Started Aug 19 04:41:50 PM PDT 24
Finished Aug 19 04:42:01 PM PDT 24
Peak memory 226032 kb
Host smart-320805a7-dca7-4fb3-9b4e-1ed731d53c9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740659321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3740659321
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.711055245
Short name T499
Test name
Test status
Simulation time 479264801 ps
CPU time 6.09 seconds
Started Aug 19 04:41:35 PM PDT 24
Finished Aug 19 04:41:41 PM PDT 24
Peak memory 218488 kb
Host smart-46d95c76-99cb-40e9-9441-76a7b3ca746e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711055245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.711055245
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.4149468257
Short name T326
Test name
Test status
Simulation time 126949085 ps
CPU time 3 seconds
Started Aug 19 04:41:35 PM PDT 24
Finished Aug 19 04:41:38 PM PDT 24
Peak memory 224132 kb
Host smart-5503d8d5-5324-465d-b952-fafe7eba4975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149468257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.4149468257
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3206237668
Short name T234
Test name
Test status
Simulation time 192378931 ps
CPU time 27.74 seconds
Started Aug 19 04:41:39 PM PDT 24
Finished Aug 19 04:42:07 PM PDT 24
Peak memory 246732 kb
Host smart-be207c7f-4618-47b3-beb1-0a091c9ce15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206237668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3206237668
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2710455588
Short name T572
Test name
Test status
Simulation time 778731796 ps
CPU time 8.31 seconds
Started Aug 19 04:41:34 PM PDT 24
Finished Aug 19 04:41:42 PM PDT 24
Peak memory 250832 kb
Host smart-1e19682f-e2be-4237-ad01-86cab2d00e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710455588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2710455588
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.369104966
Short name T397
Test name
Test status
Simulation time 5998075234 ps
CPU time 112.7 seconds
Started Aug 19 04:41:48 PM PDT 24
Finished Aug 19 04:43:41 PM PDT 24
Peak memory 222208 kb
Host smart-8c498b72-5606-4c60-9dab-0cf7c1978f8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369104966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.369104966
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2437286562
Short name T396
Test name
Test status
Simulation time 12733878 ps
CPU time 0.99 seconds
Started Aug 19 04:41:34 PM PDT 24
Finished Aug 19 04:41:35 PM PDT 24
Peak memory 209104 kb
Host smart-9e62f03e-abc0-4618-831c-ffb8b4b0fb3b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437286562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2437286562
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2610086238
Short name T82
Test name
Test status
Simulation time 29710839 ps
CPU time 0.87 seconds
Started Aug 19 04:41:50 PM PDT 24
Finished Aug 19 04:41:51 PM PDT 24
Peak memory 209012 kb
Host smart-8edc61e3-449f-41c4-8c74-0473d0d4117f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610086238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2610086238
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2759322996
Short name T668
Test name
Test status
Simulation time 1333208099 ps
CPU time 12.24 seconds
Started Aug 19 04:41:50 PM PDT 24
Finished Aug 19 04:42:03 PM PDT 24
Peak memory 218364 kb
Host smart-de27ddcb-f6fc-494e-a0e6-0dbacd9cee6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759322996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2759322996
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.744870406
Short name T619
Test name
Test status
Simulation time 346068988 ps
CPU time 4.75 seconds
Started Aug 19 04:41:51 PM PDT 24
Finished Aug 19 04:41:56 PM PDT 24
Peak memory 217320 kb
Host smart-12bff525-15cf-433d-b000-4fbb54338a94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744870406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.744870406
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.839368298
Short name T518
Test name
Test status
Simulation time 21511530 ps
CPU time 1.91 seconds
Started Aug 19 04:41:53 PM PDT 24
Finished Aug 19 04:41:55 PM PDT 24
Peak memory 218372 kb
Host smart-5668b3f1-e060-4f50-8a59-b92b42cd43cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839368298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.839368298
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3573229540
Short name T431
Test name
Test status
Simulation time 1330147761 ps
CPU time 11.45 seconds
Started Aug 19 04:41:49 PM PDT 24
Finished Aug 19 04:42:00 PM PDT 24
Peak memory 218584 kb
Host smart-43a898eb-a975-4f4c-bafa-fc0368bd2273
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573229540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3573229540
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3398634492
Short name T341
Test name
Test status
Simulation time 247107747 ps
CPU time 10.61 seconds
Started Aug 19 04:41:49 PM PDT 24
Finished Aug 19 04:42:00 PM PDT 24
Peak memory 226112 kb
Host smart-cc6c4d66-97d8-4f6a-babb-0ebfe79c6731
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398634492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3398634492
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2146260251
Short name T848
Test name
Test status
Simulation time 378628628 ps
CPU time 11.67 seconds
Started Aug 19 04:41:49 PM PDT 24
Finished Aug 19 04:42:01 PM PDT 24
Peak memory 218324 kb
Host smart-34b82a33-4531-49fe-bdf9-db5ff7266dd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146260251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2146260251
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3725681766
Short name T403
Test name
Test status
Simulation time 503313076 ps
CPU time 11.01 seconds
Started Aug 19 04:41:50 PM PDT 24
Finished Aug 19 04:42:01 PM PDT 24
Peak memory 218440 kb
Host smart-94cc9407-aabd-4909-ab58-f5b0ebc6942d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725681766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3725681766
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.203008706
Short name T355
Test name
Test status
Simulation time 126044036 ps
CPU time 2.1 seconds
Started Aug 19 04:41:54 PM PDT 24
Finished Aug 19 04:41:56 PM PDT 24
Peak memory 217768 kb
Host smart-e5910005-f846-4333-ba17-d31a90bfa833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203008706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.203008706
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2305164345
Short name T856
Test name
Test status
Simulation time 1296375887 ps
CPU time 19.12 seconds
Started Aug 19 04:41:54 PM PDT 24
Finished Aug 19 04:42:13 PM PDT 24
Peak memory 245644 kb
Host smart-377df5c1-2846-4040-8810-f74fbb21553b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305164345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2305164345
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.4013182639
Short name T227
Test name
Test status
Simulation time 204982811 ps
CPU time 3.07 seconds
Started Aug 19 04:41:52 PM PDT 24
Finished Aug 19 04:41:55 PM PDT 24
Peak memory 226428 kb
Host smart-cee4667e-2243-4ab9-b5f3-3d49de299900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013182639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.4013182639
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.115891749
Short name T114
Test name
Test status
Simulation time 95052732843 ps
CPU time 443.63 seconds
Started Aug 19 04:41:52 PM PDT 24
Finished Aug 19 04:49:16 PM PDT 24
Peak memory 277000 kb
Host smart-d27488b0-b50c-4fae-a994-5588193c085e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115891749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.115891749
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2660595869
Short name T153
Test name
Test status
Simulation time 3010289644 ps
CPU time 29.68 seconds
Started Aug 19 04:41:55 PM PDT 24
Finished Aug 19 04:42:24 PM PDT 24
Peak memory 267568 kb
Host smart-4b5d0339-425e-4c3e-ab02-91684d2e65f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2660595869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.2660595869
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.205197157
Short name T110
Test name
Test status
Simulation time 40053772 ps
CPU time 0.91 seconds
Started Aug 19 04:41:53 PM PDT 24
Finished Aug 19 04:41:54 PM PDT 24
Peak memory 212040 kb
Host smart-b016380b-ce3a-45f9-8d46-e1ba1d25097c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205197157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.205197157
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.406298225
Short name T793
Test name
Test status
Simulation time 13878403 ps
CPU time 0.84 seconds
Started Aug 19 04:41:53 PM PDT 24
Finished Aug 19 04:41:54 PM PDT 24
Peak memory 208816 kb
Host smart-9936e7d7-988c-4178-b5ca-876670ee214a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406298225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.406298225
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2936872101
Short name T461
Test name
Test status
Simulation time 3962491543 ps
CPU time 16.17 seconds
Started Aug 19 04:41:51 PM PDT 24
Finished Aug 19 04:42:07 PM PDT 24
Peak memory 226228 kb
Host smart-8063ad07-3619-419e-be18-6f1b6e5e62c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936872101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2936872101
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1410369447
Short name T464
Test name
Test status
Simulation time 3919751669 ps
CPU time 16.94 seconds
Started Aug 19 04:41:53 PM PDT 24
Finished Aug 19 04:42:10 PM PDT 24
Peak memory 217848 kb
Host smart-331eb5d0-3b42-42f1-9105-512b29335430
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410369447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1410369447
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2686753972
Short name T525
Test name
Test status
Simulation time 456977825 ps
CPU time 4.66 seconds
Started Aug 19 04:41:53 PM PDT 24
Finished Aug 19 04:41:58 PM PDT 24
Peak memory 218372 kb
Host smart-4a64180b-825e-4012-bae0-c5657fb5bd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686753972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2686753972
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3751046296
Short name T702
Test name
Test status
Simulation time 685896508 ps
CPU time 11.24 seconds
Started Aug 19 04:41:53 PM PDT 24
Finished Aug 19 04:42:05 PM PDT 24
Peak memory 219016 kb
Host smart-711b7510-d33c-4796-92e0-1de61cdf7f68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751046296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3751046296
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.798734061
Short name T368
Test name
Test status
Simulation time 559491424 ps
CPU time 9.29 seconds
Started Aug 19 04:41:51 PM PDT 24
Finished Aug 19 04:42:00 PM PDT 24
Peak memory 226068 kb
Host smart-ee1076c8-e986-4fa4-b4a2-85026cced715
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798734061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.798734061
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.230009458
Short name T771
Test name
Test status
Simulation time 749504177 ps
CPU time 9.31 seconds
Started Aug 19 04:41:50 PM PDT 24
Finished Aug 19 04:42:00 PM PDT 24
Peak memory 226092 kb
Host smart-334898b8-3eb9-43cd-ad40-9066bec89704
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230009458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.230009458
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2125759030
Short name T782
Test name
Test status
Simulation time 435869505 ps
CPU time 6.86 seconds
Started Aug 19 04:41:53 PM PDT 24
Finished Aug 19 04:42:00 PM PDT 24
Peak memory 218424 kb
Host smart-ae41ef51-2cd5-4f8e-91bf-0aeb97fc7909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125759030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2125759030
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.706436270
Short name T166
Test name
Test status
Simulation time 690044027 ps
CPU time 3.1 seconds
Started Aug 19 04:41:50 PM PDT 24
Finished Aug 19 04:41:53 PM PDT 24
Peak memory 217796 kb
Host smart-f4160a46-6c5c-4af2-a2d0-504b2f805c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706436270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.706436270
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3100869664
Short name T515
Test name
Test status
Simulation time 979986650 ps
CPU time 23.92 seconds
Started Aug 19 04:41:52 PM PDT 24
Finished Aug 19 04:42:16 PM PDT 24
Peak memory 250980 kb
Host smart-9c5b3266-13b7-4867-9764-575c1c494c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100869664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3100869664
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.4198028840
Short name T870
Test name
Test status
Simulation time 250307688 ps
CPU time 6.44 seconds
Started Aug 19 04:41:50 PM PDT 24
Finished Aug 19 04:41:57 PM PDT 24
Peak memory 250408 kb
Host smart-d0ed7b46-2820-489b-87ca-4bc1d3dffda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198028840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.4198028840
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2917226645
Short name T660
Test name
Test status
Simulation time 77673028183 ps
CPU time 98.48 seconds
Started Aug 19 04:41:55 PM PDT 24
Finished Aug 19 04:43:34 PM PDT 24
Peak memory 251040 kb
Host smart-8a25e024-3c08-4d6d-bae7-7942cc263583
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917226645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2917226645
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.814710654
Short name T481
Test name
Test status
Simulation time 70474725 ps
CPU time 1.09 seconds
Started Aug 19 04:41:50 PM PDT 24
Finished Aug 19 04:41:51 PM PDT 24
Peak memory 217988 kb
Host smart-1ba75731-f8e7-4863-8ef1-dfe9a54deaa1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814710654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.814710654
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.4101256399
Short name T422
Test name
Test status
Simulation time 40338244 ps
CPU time 0.93 seconds
Started Aug 19 04:41:59 PM PDT 24
Finished Aug 19 04:42:00 PM PDT 24
Peak memory 208972 kb
Host smart-6fd52a93-5348-4270-87d1-ee42b14416be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101256399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.4101256399
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2917487814
Short name T758
Test name
Test status
Simulation time 514540285 ps
CPU time 15.05 seconds
Started Aug 19 04:41:55 PM PDT 24
Finished Aug 19 04:42:10 PM PDT 24
Peak memory 218380 kb
Host smart-f68c9695-c4a4-467d-b4cd-e0c1b301c57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917487814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2917487814
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2065645073
Short name T565
Test name
Test status
Simulation time 415155079 ps
CPU time 1.92 seconds
Started Aug 19 04:42:08 PM PDT 24
Finished Aug 19 04:42:10 PM PDT 24
Peak memory 217468 kb
Host smart-7209a1a4-e490-4da3-a0ea-ce44103f12c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065645073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2065645073
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3973213672
Short name T736
Test name
Test status
Simulation time 140445131 ps
CPU time 5.54 seconds
Started Aug 19 04:41:56 PM PDT 24
Finished Aug 19 04:42:01 PM PDT 24
Peak memory 218344 kb
Host smart-1fe3f1d2-63ab-4d09-abba-36e643adeaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973213672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3973213672
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3463303069
Short name T766
Test name
Test status
Simulation time 827739740 ps
CPU time 11.23 seconds
Started Aug 19 04:42:01 PM PDT 24
Finished Aug 19 04:42:13 PM PDT 24
Peak memory 226032 kb
Host smart-3e56408a-a839-46cc-b6da-e183e6f01cc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463303069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3463303069
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2187219791
Short name T862
Test name
Test status
Simulation time 958725451 ps
CPU time 10.67 seconds
Started Aug 19 04:42:01 PM PDT 24
Finished Aug 19 04:42:12 PM PDT 24
Peak memory 225960 kb
Host smart-46011dab-a423-45d0-852b-987608b528f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187219791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2187219791
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1655503112
Short name T794
Test name
Test status
Simulation time 730138301 ps
CPU time 11.79 seconds
Started Aug 19 04:42:03 PM PDT 24
Finished Aug 19 04:42:15 PM PDT 24
Peak memory 226088 kb
Host smart-4402b3d7-ad9d-4bb2-b13b-68bdaf4a3779
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655503112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1655503112
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.83446143
Short name T772
Test name
Test status
Simulation time 1735986572 ps
CPU time 9.87 seconds
Started Aug 19 04:42:02 PM PDT 24
Finished Aug 19 04:42:12 PM PDT 24
Peak memory 218424 kb
Host smart-973ba9b2-60a7-48fb-9b75-04b8044376ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83446143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.83446143
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.757232116
Short name T245
Test name
Test status
Simulation time 215421293 ps
CPU time 3.3 seconds
Started Aug 19 04:41:55 PM PDT 24
Finished Aug 19 04:41:58 PM PDT 24
Peak memory 217764 kb
Host smart-44a153db-3f91-4dea-a111-8b3fa043d3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757232116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.757232116
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1900225493
Short name T531
Test name
Test status
Simulation time 316048145 ps
CPU time 23.45 seconds
Started Aug 19 04:41:54 PM PDT 24
Finished Aug 19 04:42:17 PM PDT 24
Peak memory 251000 kb
Host smart-7bf2c46c-fcba-409c-b1e4-294dbc32c14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900225493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1900225493
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2052714420
Short name T304
Test name
Test status
Simulation time 98216106 ps
CPU time 10.09 seconds
Started Aug 19 04:41:51 PM PDT 24
Finished Aug 19 04:42:01 PM PDT 24
Peak memory 251012 kb
Host smart-75ad93fe-9669-4f93-902e-1f7e94ca930c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052714420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2052714420
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2411957564
Short name T842
Test name
Test status
Simulation time 7907840425 ps
CPU time 276.89 seconds
Started Aug 19 04:42:04 PM PDT 24
Finished Aug 19 04:46:41 PM PDT 24
Peak memory 220328 kb
Host smart-ed0b8de0-ccd6-45f7-96b3-ff3d159ca6f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411957564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2411957564
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2222642418
Short name T677
Test name
Test status
Simulation time 22024679 ps
CPU time 0.94 seconds
Started Aug 19 04:41:55 PM PDT 24
Finished Aug 19 04:41:56 PM PDT 24
Peak memory 208724 kb
Host smart-f6337c17-679c-4bfd-80f1-e5ade08dca71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222642418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2222642418
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.4261632165
Short name T456
Test name
Test status
Simulation time 23600629 ps
CPU time 1.18 seconds
Started Aug 19 04:42:04 PM PDT 24
Finished Aug 19 04:42:06 PM PDT 24
Peak memory 209076 kb
Host smart-b0d2ea91-afcd-44d9-86ba-2eeb648eeb0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261632165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.4261632165
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1338209138
Short name T550
Test name
Test status
Simulation time 418451775 ps
CPU time 9.7 seconds
Started Aug 19 04:42:02 PM PDT 24
Finished Aug 19 04:42:11 PM PDT 24
Peak memory 226160 kb
Host smart-475dc8d4-58fe-4635-9a81-25506a1b8504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338209138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1338209138
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1001405076
Short name T642
Test name
Test status
Simulation time 263937774 ps
CPU time 1.46 seconds
Started Aug 19 04:42:02 PM PDT 24
Finished Aug 19 04:42:04 PM PDT 24
Peak memory 217748 kb
Host smart-43cf4570-c9e7-4b75-b198-94eece020713
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001405076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1001405076
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3247984288
Short name T308
Test name
Test status
Simulation time 128123166 ps
CPU time 2.9 seconds
Started Aug 19 04:42:05 PM PDT 24
Finished Aug 19 04:42:08 PM PDT 24
Peak memory 218352 kb
Host smart-c8b7adfe-59fc-4183-9d62-cddacbc36609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247984288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3247984288
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1392769340
Short name T50
Test name
Test status
Simulation time 2236998827 ps
CPU time 10.98 seconds
Started Aug 19 04:42:05 PM PDT 24
Finished Aug 19 04:42:16 PM PDT 24
Peak memory 218360 kb
Host smart-67a43223-9a3c-4184-a6ed-42ac3590bbe4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392769340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1392769340
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3077459854
Short name T830
Test name
Test status
Simulation time 198488174 ps
CPU time 9.08 seconds
Started Aug 19 04:42:03 PM PDT 24
Finished Aug 19 04:42:12 PM PDT 24
Peak memory 225636 kb
Host smart-4562343b-1d3b-42e2-be15-d3f4384ada1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077459854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3077459854
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1890653384
Short name T445
Test name
Test status
Simulation time 625664671 ps
CPU time 9.31 seconds
Started Aug 19 04:42:02 PM PDT 24
Finished Aug 19 04:42:12 PM PDT 24
Peak memory 218312 kb
Host smart-2466f92d-5956-4336-932c-297d90ee4929
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890653384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1890653384
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1627902898
Short name T845
Test name
Test status
Simulation time 1178390714 ps
CPU time 12.71 seconds
Started Aug 19 04:42:00 PM PDT 24
Finished Aug 19 04:42:13 PM PDT 24
Peak memory 218460 kb
Host smart-30d53763-1403-46d3-abb2-834b6e0da1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627902898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1627902898
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1915497858
Short name T737
Test name
Test status
Simulation time 234369885 ps
CPU time 2.41 seconds
Started Aug 19 04:41:59 PM PDT 24
Finished Aug 19 04:42:02 PM PDT 24
Peak memory 217788 kb
Host smart-b503b645-ef2c-4154-9550-8b6d2035c9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915497858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1915497858
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1548909497
Short name T605
Test name
Test status
Simulation time 297293569 ps
CPU time 28.85 seconds
Started Aug 19 04:42:00 PM PDT 24
Finished Aug 19 04:42:29 PM PDT 24
Peak memory 250976 kb
Host smart-b3656c53-9ffb-4654-96bb-048d0932a184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548909497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1548909497
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.781616992
Short name T606
Test name
Test status
Simulation time 111742266 ps
CPU time 8.16 seconds
Started Aug 19 04:42:00 PM PDT 24
Finished Aug 19 04:42:08 PM PDT 24
Peak memory 246676 kb
Host smart-9bc3f0a3-8e62-47e8-ada8-2324f2eb5ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781616992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.781616992
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.750100181
Short name T470
Test name
Test status
Simulation time 2842472199 ps
CPU time 89.58 seconds
Started Aug 19 04:42:00 PM PDT 24
Finished Aug 19 04:43:29 PM PDT 24
Peak memory 250952 kb
Host smart-79f75af6-3d9e-433f-a163-f46d2be66ea3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750100181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.750100181
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3990994339
Short name T46
Test name
Test status
Simulation time 11888695 ps
CPU time 0.83 seconds
Started Aug 19 04:42:00 PM PDT 24
Finished Aug 19 04:42:01 PM PDT 24
Peak memory 209016 kb
Host smart-149b70ad-b6b4-49f2-a212-d92a862372b4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990994339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3990994339
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2174855233
Short name T754
Test name
Test status
Simulation time 23224037 ps
CPU time 1.24 seconds
Started Aug 19 04:42:03 PM PDT 24
Finished Aug 19 04:42:04 PM PDT 24
Peak memory 209132 kb
Host smart-817445f3-3672-47bc-88d5-0e76a55e8608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174855233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2174855233
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2502652366
Short name T646
Test name
Test status
Simulation time 226931821 ps
CPU time 10.83 seconds
Started Aug 19 04:42:02 PM PDT 24
Finished Aug 19 04:42:13 PM PDT 24
Peak memory 218376 kb
Host smart-947b39da-1766-4012-af08-758fa8943dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502652366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2502652366
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.4253831817
Short name T822
Test name
Test status
Simulation time 718406251 ps
CPU time 17.83 seconds
Started Aug 19 04:42:02 PM PDT 24
Finished Aug 19 04:42:20 PM PDT 24
Peak memory 217752 kb
Host smart-09b0d832-9406-4bc4-8119-922653f3ffc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253831817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.4253831817
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1129242765
Short name T322
Test name
Test status
Simulation time 140436132 ps
CPU time 2.6 seconds
Started Aug 19 04:41:58 PM PDT 24
Finished Aug 19 04:42:01 PM PDT 24
Peak memory 218520 kb
Host smart-0108a596-0e8d-431a-9f93-fbee28334675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129242765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1129242765
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.606895980
Short name T712
Test name
Test status
Simulation time 1237247046 ps
CPU time 16.31 seconds
Started Aug 19 04:42:01 PM PDT 24
Finished Aug 19 04:42:17 PM PDT 24
Peak memory 226036 kb
Host smart-f141a12f-af85-444a-8d64-24f9ce639cf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606895980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.606895980
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2632079503
Short name T430
Test name
Test status
Simulation time 1717564459 ps
CPU time 12.91 seconds
Started Aug 19 04:42:08 PM PDT 24
Finished Aug 19 04:42:21 PM PDT 24
Peak memory 226064 kb
Host smart-289a8780-4b53-440b-8c96-afea30a41bca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632079503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2632079503
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3867435372
Short name T849
Test name
Test status
Simulation time 5446565735 ps
CPU time 9.8 seconds
Started Aug 19 04:42:04 PM PDT 24
Finished Aug 19 04:42:14 PM PDT 24
Peak memory 218356 kb
Host smart-ab247036-ca3f-4661-bb67-f306f28cc8ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867435372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
3867435372
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2805109823
Short name T58
Test name
Test status
Simulation time 198967765 ps
CPU time 6.32 seconds
Started Aug 19 04:42:00 PM PDT 24
Finished Aug 19 04:42:06 PM PDT 24
Peak memory 224828 kb
Host smart-1ea418e7-cd73-40e7-aa12-ef463bd7995a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805109823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2805109823
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2680137782
Short name T89
Test name
Test status
Simulation time 59116956 ps
CPU time 2.57 seconds
Started Aug 19 04:42:03 PM PDT 24
Finished Aug 19 04:42:05 PM PDT 24
Peak memory 214744 kb
Host smart-08b46a0c-c6b1-43ce-a429-c4110975d0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680137782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2680137782
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3328097800
Short name T516
Test name
Test status
Simulation time 301929868 ps
CPU time 24.21 seconds
Started Aug 19 04:42:04 PM PDT 24
Finished Aug 19 04:42:29 PM PDT 24
Peak memory 250744 kb
Host smart-d6054eb2-693a-45ad-b85b-8688acea0a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328097800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3328097800
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1312503672
Short name T273
Test name
Test status
Simulation time 246060550 ps
CPU time 6.9 seconds
Started Aug 19 04:42:19 PM PDT 24
Finished Aug 19 04:42:26 PM PDT 24
Peak memory 242576 kb
Host smart-7b71b7bc-c18b-4d02-b721-6aeff7b2f79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312503672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1312503672
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3710216569
Short name T556
Test name
Test status
Simulation time 176663642860 ps
CPU time 319.94 seconds
Started Aug 19 04:42:08 PM PDT 24
Finished Aug 19 04:47:28 PM PDT 24
Peak memory 250324 kb
Host smart-038a0120-d7e4-49bd-9e28-929fefb0e843
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710216569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3710216569
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.877725390
Short name T172
Test name
Test status
Simulation time 2771542630 ps
CPU time 107.12 seconds
Started Aug 19 04:42:02 PM PDT 24
Finished Aug 19 04:43:50 PM PDT 24
Peak memory 278224 kb
Host smart-558e6123-6538-46fe-b2e6-82c4e03cc77f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=877725390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.877725390
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.213664078
Short name T162
Test name
Test status
Simulation time 44617426 ps
CPU time 0.91 seconds
Started Aug 19 04:42:00 PM PDT 24
Finished Aug 19 04:42:01 PM PDT 24
Peak memory 209068 kb
Host smart-b6bd14ab-acea-4160-b69a-10f69ea016fd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213664078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.213664078
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3872772034
Short name T76
Test name
Test status
Simulation time 48218973 ps
CPU time 1.09 seconds
Started Aug 19 04:39:13 PM PDT 24
Finished Aug 19 04:39:14 PM PDT 24
Peak memory 209052 kb
Host smart-ea95ae7c-751c-423b-bfe6-fd435c60c37a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872772034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3872772034
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3269299122
Short name T219
Test name
Test status
Simulation time 23196237 ps
CPU time 0.97 seconds
Started Aug 19 04:39:14 PM PDT 24
Finished Aug 19 04:39:15 PM PDT 24
Peak memory 208864 kb
Host smart-20e15bc8-ba11-4b36-9719-0bf38b18c62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269299122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3269299122
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.4016022660
Short name T332
Test name
Test status
Simulation time 219299673 ps
CPU time 10.07 seconds
Started Aug 19 04:39:06 PM PDT 24
Finished Aug 19 04:39:16 PM PDT 24
Peak memory 226176 kb
Host smart-7550fa13-5dd6-4c72-94b4-8cb999b89633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016022660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.4016022660
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2887250307
Short name T369
Test name
Test status
Simulation time 2512738430 ps
CPU time 4.76 seconds
Started Aug 19 04:39:06 PM PDT 24
Finished Aug 19 04:39:11 PM PDT 24
Peak memory 217884 kb
Host smart-a43c3e2d-9b15-4898-a8b5-f48da44f8d3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887250307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2887250307
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2502030790
Short name T720
Test name
Test status
Simulation time 6585139733 ps
CPU time 46.09 seconds
Started Aug 19 04:39:07 PM PDT 24
Finished Aug 19 04:39:53 PM PDT 24
Peak memory 218992 kb
Host smart-2a760034-6429-4b3f-ad4b-0189d9e73207
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502030790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2502030790
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2512512199
Short name T718
Test name
Test status
Simulation time 3862477731 ps
CPU time 17.84 seconds
Started Aug 19 04:39:10 PM PDT 24
Finished Aug 19 04:39:28 PM PDT 24
Peak memory 217904 kb
Host smart-62c18f25-2273-43e9-9af6-859e85de8e44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512512199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
512512199
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.283294453
Short name T419
Test name
Test status
Simulation time 656996139 ps
CPU time 9.8 seconds
Started Aug 19 04:39:09 PM PDT 24
Finished Aug 19 04:39:19 PM PDT 24
Peak memory 218304 kb
Host smart-6ad84aa9-a124-4990-a811-63dd97347e54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283294453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.283294453
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1187616509
Short name T90
Test name
Test status
Simulation time 976912892 ps
CPU time 16.38 seconds
Started Aug 19 04:39:06 PM PDT 24
Finished Aug 19 04:39:23 PM PDT 24
Peak memory 217684 kb
Host smart-7d80b53b-1b24-4f0e-874e-b4a8e749334b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187616509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1187616509
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.4289900752
Short name T488
Test name
Test status
Simulation time 772117636 ps
CPU time 10.86 seconds
Started Aug 19 04:39:05 PM PDT 24
Finished Aug 19 04:39:16 PM PDT 24
Peak memory 217712 kb
Host smart-27b53584-8e6f-4bc9-9f9c-5d8d88909912
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289900752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
4289900752
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1136857056
Short name T374
Test name
Test status
Simulation time 2226821868 ps
CPU time 30.6 seconds
Started Aug 19 04:39:05 PM PDT 24
Finished Aug 19 04:39:35 PM PDT 24
Peak memory 250832 kb
Host smart-682fa289-5fe7-473a-9785-702d0c6e99ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136857056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1136857056
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3284685529
Short name T20
Test name
Test status
Simulation time 1617988726 ps
CPU time 27.66 seconds
Started Aug 19 04:39:12 PM PDT 24
Finished Aug 19 04:39:40 PM PDT 24
Peak memory 250932 kb
Host smart-8c820c2a-cf59-4330-a9b1-844b6c6388fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284685529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3284685529
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2424463626
Short name T484
Test name
Test status
Simulation time 410348900 ps
CPU time 3 seconds
Started Aug 19 04:39:08 PM PDT 24
Finished Aug 19 04:39:11 PM PDT 24
Peak memory 222464 kb
Host smart-205d69db-2c67-401f-8b97-aea626eced26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424463626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2424463626
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.760401444
Short name T824
Test name
Test status
Simulation time 1245487536 ps
CPU time 5.73 seconds
Started Aug 19 04:39:04 PM PDT 24
Finished Aug 19 04:39:10 PM PDT 24
Peak memory 217808 kb
Host smart-08be2e0f-56f8-43dd-b2d3-6fc5855ccccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760401444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.760401444
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.667407360
Short name T165
Test name
Test status
Simulation time 280674449 ps
CPU time 9.07 seconds
Started Aug 19 04:39:03 PM PDT 24
Finished Aug 19 04:39:12 PM PDT 24
Peak memory 219012 kb
Host smart-91192bda-d610-4526-a05b-c1fdff75e29d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667407360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.667407360
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.493011443
Short name T411
Test name
Test status
Simulation time 384442056 ps
CPU time 15.08 seconds
Started Aug 19 04:39:07 PM PDT 24
Finished Aug 19 04:39:22 PM PDT 24
Peak memory 226084 kb
Host smart-b3310e44-288a-4315-ab3c-adb2f76d1a2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493011443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.493011443
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.745507677
Short name T774
Test name
Test status
Simulation time 2450923703 ps
CPU time 11.18 seconds
Started Aug 19 04:39:10 PM PDT 24
Finished Aug 19 04:39:21 PM PDT 24
Peak memory 218372 kb
Host smart-a3d51330-08f1-4ed4-8641-94d484385803
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745507677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.745507677
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1718495741
Short name T558
Test name
Test status
Simulation time 351090036 ps
CPU time 9 seconds
Started Aug 19 04:39:13 PM PDT 24
Finished Aug 19 04:39:22 PM PDT 24
Peak memory 226188 kb
Host smart-4e365e8b-2a01-4243-bcd0-351cd6914251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718495741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1718495741
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.899434610
Short name T260
Test name
Test status
Simulation time 76410236 ps
CPU time 4.25 seconds
Started Aug 19 04:39:14 PM PDT 24
Finished Aug 19 04:39:18 PM PDT 24
Peak memory 217760 kb
Host smart-770e876b-8b59-4a0c-8517-865119503edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899434610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.899434610
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1550369137
Short name T512
Test name
Test status
Simulation time 1136343530 ps
CPU time 18.19 seconds
Started Aug 19 04:39:05 PM PDT 24
Finished Aug 19 04:39:23 PM PDT 24
Peak memory 250960 kb
Host smart-a842d454-3948-4d1e-acfa-b60d8962450d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550369137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1550369137
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2511579032
Short name T611
Test name
Test status
Simulation time 85935820 ps
CPU time 3.12 seconds
Started Aug 19 04:39:09 PM PDT 24
Finished Aug 19 04:39:12 PM PDT 24
Peak memory 222404 kb
Host smart-d94a2d5e-3b7a-43b9-b3e3-c51ecaca7412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511579032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2511579032
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2081329250
Short name T103
Test name
Test status
Simulation time 4470649702 ps
CPU time 14.96 seconds
Started Aug 19 04:39:07 PM PDT 24
Finished Aug 19 04:39:22 PM PDT 24
Peak memory 250228 kb
Host smart-6bd2d7b8-583f-47c4-9d23-b2d2eb59d0e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081329250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2081329250
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3202647060
Short name T673
Test name
Test status
Simulation time 40529397 ps
CPU time 0.89 seconds
Started Aug 19 04:39:06 PM PDT 24
Finished Aug 19 04:39:07 PM PDT 24
Peak memory 212080 kb
Host smart-f1e167c5-c4aa-44e9-859a-c45f7798f3a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202647060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3202647060
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2419051797
Short name T865
Test name
Test status
Simulation time 72262694 ps
CPU time 0.94 seconds
Started Aug 19 04:39:16 PM PDT 24
Finished Aug 19 04:39:17 PM PDT 24
Peak memory 209032 kb
Host smart-96f7547c-d0ed-4a5d-af76-5f5f6ae9a69b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419051797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2419051797
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2822806346
Short name T833
Test name
Test status
Simulation time 51805061 ps
CPU time 0.82 seconds
Started Aug 19 04:39:13 PM PDT 24
Finished Aug 19 04:39:14 PM PDT 24
Peak memory 208336 kb
Host smart-ca5f2bb5-d289-4888-b32f-8bc5dd81515d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822806346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2822806346
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2063526066
Short name T491
Test name
Test status
Simulation time 1548853199 ps
CPU time 12.61 seconds
Started Aug 19 04:39:11 PM PDT 24
Finished Aug 19 04:39:24 PM PDT 24
Peak memory 218360 kb
Host smart-5176b9f4-c6aa-46e8-aab1-db6dbe9200ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063526066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2063526066
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2637589940
Short name T344
Test name
Test status
Simulation time 1211065234 ps
CPU time 6.95 seconds
Started Aug 19 04:39:07 PM PDT 24
Finished Aug 19 04:39:14 PM PDT 24
Peak memory 217396 kb
Host smart-8149b7ef-8d36-4e34-a1d6-8ca7afb67874
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637589940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2637589940
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.565819433
Short name T640
Test name
Test status
Simulation time 1178497695 ps
CPU time 20.52 seconds
Started Aug 19 04:39:08 PM PDT 24
Finished Aug 19 04:39:29 PM PDT 24
Peak memory 218356 kb
Host smart-93001c40-d2c0-42e4-81c7-e6dfac0b01f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565819433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.565819433
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3374272539
Short name T710
Test name
Test status
Simulation time 3655283179 ps
CPU time 9.14 seconds
Started Aug 19 04:39:13 PM PDT 24
Finished Aug 19 04:39:22 PM PDT 24
Peak memory 217872 kb
Host smart-e7893deb-b3bb-4bcf-9da5-6d78b689c52b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374272539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
374272539
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.664713183
Short name T663
Test name
Test status
Simulation time 606645076 ps
CPU time 10.35 seconds
Started Aug 19 04:39:12 PM PDT 24
Finished Aug 19 04:39:22 PM PDT 24
Peak memory 218320 kb
Host smart-0202b734-d2eb-4ece-afb0-4455a5b6bebb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664713183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.664713183
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3295845473
Short name T420
Test name
Test status
Simulation time 12167404433 ps
CPU time 18.96 seconds
Started Aug 19 04:39:17 PM PDT 24
Finished Aug 19 04:39:36 PM PDT 24
Peak memory 217792 kb
Host smart-3891d06f-ff84-4f37-92c9-c6966acfb587
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295845473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3295845473
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.342206132
Short name T251
Test name
Test status
Simulation time 355840586 ps
CPU time 8.06 seconds
Started Aug 19 04:39:13 PM PDT 24
Finished Aug 19 04:39:21 PM PDT 24
Peak memory 217720 kb
Host smart-f2a15ee7-44c5-472f-8c6a-c07c87477591
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342206132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.342206132
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.969612077
Short name T851
Test name
Test status
Simulation time 3700488224 ps
CPU time 122.93 seconds
Started Aug 19 04:39:07 PM PDT 24
Finished Aug 19 04:41:10 PM PDT 24
Peak memory 283704 kb
Host smart-90edef2e-51a1-4803-b49c-8349441b24c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969612077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.969612077
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1300715624
Short name T382
Test name
Test status
Simulation time 606279340 ps
CPU time 14.56 seconds
Started Aug 19 04:39:13 PM PDT 24
Finished Aug 19 04:39:28 PM PDT 24
Peak memory 250936 kb
Host smart-d81a80ee-34a5-4e31-978d-7df0b55b783e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300715624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1300715624
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1806404068
Short name T796
Test name
Test status
Simulation time 234320129 ps
CPU time 3.25 seconds
Started Aug 19 04:39:07 PM PDT 24
Finished Aug 19 04:39:10 PM PDT 24
Peak memory 218340 kb
Host smart-85eccc2a-d6b2-4fbd-a56a-835575c1cbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806404068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1806404068
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1925975587
Short name T69
Test name
Test status
Simulation time 226880416 ps
CPU time 12.58 seconds
Started Aug 19 04:39:13 PM PDT 24
Finished Aug 19 04:39:26 PM PDT 24
Peak memory 214044 kb
Host smart-6ffe2f8b-e5bb-466a-a6b9-856fa4b29fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925975587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1925975587
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.48068361
Short name T452
Test name
Test status
Simulation time 714150261 ps
CPU time 12.89 seconds
Started Aug 19 04:39:22 PM PDT 24
Finished Aug 19 04:39:35 PM PDT 24
Peak memory 219232 kb
Host smart-330df77b-6d03-4d5a-b916-aad46ba31bdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48068361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.48068361
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2658452120
Short name T282
Test name
Test status
Simulation time 1330825615 ps
CPU time 11.43 seconds
Started Aug 19 04:39:23 PM PDT 24
Finished Aug 19 04:39:35 PM PDT 24
Peak memory 226036 kb
Host smart-5dee3e16-ef2c-4dad-aded-7942689b2514
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658452120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2658452120
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1585346852
Short name T612
Test name
Test status
Simulation time 269462362 ps
CPU time 8.21 seconds
Started Aug 19 04:39:17 PM PDT 24
Finished Aug 19 04:39:26 PM PDT 24
Peak memory 218296 kb
Host smart-ac0c0a7d-c900-440f-8fbd-a4366fcd4e5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585346852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
585346852
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.140920494
Short name T349
Test name
Test status
Simulation time 608599174 ps
CPU time 8.76 seconds
Started Aug 19 04:39:07 PM PDT 24
Finished Aug 19 04:39:16 PM PDT 24
Peak memory 218408 kb
Host smart-977fbba9-b734-4bb5-8473-57a1d22f8712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140920494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.140920494
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.455196262
Short name T79
Test name
Test status
Simulation time 75607101 ps
CPU time 2.66 seconds
Started Aug 19 04:39:13 PM PDT 24
Finished Aug 19 04:39:16 PM PDT 24
Peak memory 214760 kb
Host smart-9234f072-7e77-426a-b363-c2bf49661d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455196262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.455196262
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2648646859
Short name T792
Test name
Test status
Simulation time 583385043 ps
CPU time 24.47 seconds
Started Aug 19 04:39:08 PM PDT 24
Finished Aug 19 04:39:33 PM PDT 24
Peak memory 250980 kb
Host smart-b7a3d35a-38cc-40e8-b0ee-17f29163d6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648646859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2648646859
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3315103860
Short name T535
Test name
Test status
Simulation time 401565575 ps
CPU time 6.52 seconds
Started Aug 19 04:39:12 PM PDT 24
Finished Aug 19 04:39:19 PM PDT 24
Peak memory 250360 kb
Host smart-ec0a9786-debe-47fe-8393-02bd0ce9b135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315103860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3315103860
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.700878063
Short name T643
Test name
Test status
Simulation time 82257824512 ps
CPU time 477.14 seconds
Started Aug 19 04:39:15 PM PDT 24
Finished Aug 19 04:47:12 PM PDT 24
Peak memory 283204 kb
Host smart-d69a5fa9-27f0-45e8-adb6-44f6475e91ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700878063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.700878063
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2942240142
Short name T690
Test name
Test status
Simulation time 26015911 ps
CPU time 0.8 seconds
Started Aug 19 04:39:07 PM PDT 24
Finished Aug 19 04:39:08 PM PDT 24
Peak memory 209008 kb
Host smart-daa6b0f5-e535-44ff-88a0-2b6f6be22d13
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942240142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2942240142
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.38027079
Short name T184
Test name
Test status
Simulation time 98737885 ps
CPU time 0.93 seconds
Started Aug 19 04:39:19 PM PDT 24
Finished Aug 19 04:39:20 PM PDT 24
Peak memory 209096 kb
Host smart-2520ca6c-665a-457a-8885-4877a1a084cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38027079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.38027079
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2134286963
Short name T783
Test name
Test status
Simulation time 1355329627 ps
CPU time 11.55 seconds
Started Aug 19 04:39:17 PM PDT 24
Finished Aug 19 04:39:28 PM PDT 24
Peak memory 218372 kb
Host smart-a8ea9cdd-955e-4495-9096-235a2776ba89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134286963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2134286963
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2995576299
Short name T617
Test name
Test status
Simulation time 58137543 ps
CPU time 1.45 seconds
Started Aug 19 04:39:22 PM PDT 24
Finished Aug 19 04:39:24 PM PDT 24
Peak memory 217840 kb
Host smart-02aacef5-fa11-453c-b0c4-fafdea13b984
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995576299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2995576299
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1970290544
Short name T622
Test name
Test status
Simulation time 3724525444 ps
CPU time 30.9 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:39:56 PM PDT 24
Peak memory 218984 kb
Host smart-e2ed7cc7-0e58-433a-9870-12aad0739e96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970290544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1970290544
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.167826760
Short name T866
Test name
Test status
Simulation time 3844865458 ps
CPU time 7.57 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:39:33 PM PDT 24
Peak memory 217916 kb
Host smart-efe7daa6-416e-45b6-8876-7bb7020e5ff4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167826760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.167826760
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.762521178
Short name T189
Test name
Test status
Simulation time 113533377 ps
CPU time 2.76 seconds
Started Aug 19 04:39:21 PM PDT 24
Finished Aug 19 04:39:24 PM PDT 24
Peak memory 221816 kb
Host smart-9772fc4b-10f5-427d-b8fb-7b7d11568baf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762521178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.762521178
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3670008521
Short name T532
Test name
Test status
Simulation time 717900262 ps
CPU time 11.39 seconds
Started Aug 19 04:39:25 PM PDT 24
Finished Aug 19 04:39:36 PM PDT 24
Peak memory 217692 kb
Host smart-c692fc07-7413-452e-ba94-f9f60159029d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670008521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3670008521
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2304703906
Short name T4
Test name
Test status
Simulation time 1329905990 ps
CPU time 21.9 seconds
Started Aug 19 04:39:15 PM PDT 24
Finished Aug 19 04:39:37 PM PDT 24
Peak memory 216480 kb
Host smart-5f05c86a-c935-43cd-aa0a-7e4bfa38cb80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304703906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2304703906
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1682544101
Short name T407
Test name
Test status
Simulation time 1357537383 ps
CPU time 57.57 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:40:22 PM PDT 24
Peak memory 266656 kb
Host smart-3e82525f-3eb5-4ee7-b3ed-0fb88d81cc95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682544101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1682544101
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.549553232
Short name T524
Test name
Test status
Simulation time 475558458 ps
CPU time 13.25 seconds
Started Aug 19 04:39:16 PM PDT 24
Finished Aug 19 04:39:30 PM PDT 24
Peak memory 251024 kb
Host smart-da9e1377-62e4-4e64-80c4-afe4d172cd87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549553232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.549553232
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2543643349
Short name T269
Test name
Test status
Simulation time 98078896 ps
CPU time 4.13 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:39:30 PM PDT 24
Peak memory 218372 kb
Host smart-5d7b1631-f19b-470b-8c72-390dbe6f5afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543643349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2543643349
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.438570088
Short name T459
Test name
Test status
Simulation time 234785171 ps
CPU time 6.9 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:39:33 PM PDT 24
Peak memory 214716 kb
Host smart-e2f59958-e64f-4b56-b0db-28eaf7029523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438570088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.438570088
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3297498412
Short name T289
Test name
Test status
Simulation time 515277649 ps
CPU time 8.7 seconds
Started Aug 19 04:39:16 PM PDT 24
Finished Aug 19 04:39:25 PM PDT 24
Peak memory 218612 kb
Host smart-d5f4891d-644a-468c-aef6-91f05ba7af68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297498412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3297498412
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.318116280
Short name T328
Test name
Test status
Simulation time 1614020152 ps
CPU time 10.78 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:39:35 PM PDT 24
Peak memory 226076 kb
Host smart-92b81f7a-37e0-4bb3-bd40-d84df81d08ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318116280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.318116280
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2171983454
Short name T600
Test name
Test status
Simulation time 870847136 ps
CPU time 11.09 seconds
Started Aug 19 04:39:18 PM PDT 24
Finished Aug 19 04:39:29 PM PDT 24
Peak memory 218288 kb
Host smart-049f048e-e129-4018-a778-dffb7cb86407
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171983454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
171983454
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2203287420
Short name T541
Test name
Test status
Simulation time 1269571603 ps
CPU time 8.02 seconds
Started Aug 19 04:39:18 PM PDT 24
Finished Aug 19 04:39:26 PM PDT 24
Peak memory 218420 kb
Host smart-a21d0b66-919f-4949-8ea0-50592f1b9690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203287420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2203287420
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3704078580
Short name T638
Test name
Test status
Simulation time 34297860 ps
CPU time 1.33 seconds
Started Aug 19 04:39:20 PM PDT 24
Finished Aug 19 04:39:21 PM PDT 24
Peak memory 217788 kb
Host smart-c4eb948f-8f5b-4eaf-b349-700a35cb95be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704078580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3704078580
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.91907822
Short name T363
Test name
Test status
Simulation time 340395657 ps
CPU time 24.38 seconds
Started Aug 19 04:39:22 PM PDT 24
Finished Aug 19 04:39:47 PM PDT 24
Peak memory 251060 kb
Host smart-930004d9-6f28-4983-bda0-ef36ed493af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91907822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.91907822
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.157972940
Short name T376
Test name
Test status
Simulation time 118567005 ps
CPU time 7.41 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:39:32 PM PDT 24
Peak memory 241960 kb
Host smart-16d04c3a-1097-4ca9-aa84-069a8d3aeb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157972940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.157972940
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2912637460
Short name T439
Test name
Test status
Simulation time 9878457713 ps
CPU time 74.79 seconds
Started Aug 19 04:39:16 PM PDT 24
Finished Aug 19 04:40:31 PM PDT 24
Peak memory 223696 kb
Host smart-2b4a32d1-e18f-40b7-ba6f-8d538e585e03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912637460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2912637460
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1741494990
Short name T855
Test name
Test status
Simulation time 71897423 ps
CPU time 1.02 seconds
Started Aug 19 04:39:21 PM PDT 24
Finished Aug 19 04:39:22 PM PDT 24
Peak memory 212060 kb
Host smart-cb107741-3a71-4d26-b07b-5567d2dc209c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741494990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1741494990
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3143482749
Short name T340
Test name
Test status
Simulation time 72276699 ps
CPU time 0.78 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:39:25 PM PDT 24
Peak memory 208800 kb
Host smart-cfce83c5-b48e-4f49-b4bb-7c82eb9fec06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143482749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3143482749
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1814064227
Short name T221
Test name
Test status
Simulation time 38466623 ps
CPU time 0.85 seconds
Started Aug 19 04:39:17 PM PDT 24
Finished Aug 19 04:39:18 PM PDT 24
Peak memory 209084 kb
Host smart-f52b937b-5185-4f41-b13b-51de0cf760e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814064227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1814064227
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.344095800
Short name T333
Test name
Test status
Simulation time 5172592233 ps
CPU time 21.84 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:39:46 PM PDT 24
Peak memory 226204 kb
Host smart-ce624351-fba1-4c2a-8fdc-e54f1c8e8347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344095800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.344095800
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1497597328
Short name T633
Test name
Test status
Simulation time 505185751 ps
CPU time 6.6 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:39:33 PM PDT 24
Peak memory 217792 kb
Host smart-a264929d-5947-4cf1-9bbc-fab220e1a6fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497597328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1497597328
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1500021604
Short name T505
Test name
Test status
Simulation time 5915679243 ps
CPU time 24.9 seconds
Started Aug 19 04:39:22 PM PDT 24
Finished Aug 19 04:39:47 PM PDT 24
Peak memory 219004 kb
Host smart-093715e9-ecd9-4b92-a758-81b3c4b3e32b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500021604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1500021604
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1480969039
Short name T733
Test name
Test status
Simulation time 1234235012 ps
CPU time 6.96 seconds
Started Aug 19 04:39:18 PM PDT 24
Finished Aug 19 04:39:25 PM PDT 24
Peak memory 217836 kb
Host smart-69be8d88-6e5d-4a30-b428-c5c8c7da5c95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480969039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
480969039
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1828347009
Short name T365
Test name
Test status
Simulation time 2468078061 ps
CPU time 11.42 seconds
Started Aug 19 04:39:20 PM PDT 24
Finished Aug 19 04:39:32 PM PDT 24
Peak memory 225908 kb
Host smart-0d099ee4-84ab-4f95-894d-4f8e4f1c1b02
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828347009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1828347009
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3074791806
Short name T284
Test name
Test status
Simulation time 5657364460 ps
CPU time 36.14 seconds
Started Aug 19 04:39:23 PM PDT 24
Finished Aug 19 04:39:59 PM PDT 24
Peak memory 217776 kb
Host smart-ac94beb1-e702-49ca-94de-b490aa6eec71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074791806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3074791806
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1653111546
Short name T336
Test name
Test status
Simulation time 1905190765 ps
CPU time 6.56 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:39:33 PM PDT 24
Peak memory 217724 kb
Host smart-d11e10a1-d6a2-4919-a053-fbd6e5f0d574
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653111546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1653111546
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3596817804
Short name T440
Test name
Test status
Simulation time 2896253875 ps
CPU time 45.5 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:40:12 PM PDT 24
Peak memory 267340 kb
Host smart-4266bca2-7b5b-4213-bfbc-3e901ca58ab1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596817804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3596817804
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.304478288
Short name T167
Test name
Test status
Simulation time 1973491324 ps
CPU time 13.42 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:39:38 PM PDT 24
Peak memory 250904 kb
Host smart-34fdc858-d319-456e-a8db-91b63c89c64a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304478288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.304478288
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2910278913
Short name T346
Test name
Test status
Simulation time 496487102 ps
CPU time 3.89 seconds
Started Aug 19 04:39:20 PM PDT 24
Finished Aug 19 04:39:24 PM PDT 24
Peak memory 218364 kb
Host smart-c98f523f-94a7-45ab-82e5-92198065cd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910278913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2910278913
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2994182420
Short name T621
Test name
Test status
Simulation time 2191595354 ps
CPU time 8.07 seconds
Started Aug 19 04:39:17 PM PDT 24
Finished Aug 19 04:39:25 PM PDT 24
Peak memory 217840 kb
Host smart-ac134752-cae7-4ef0-b14a-0a2b145a1125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994182420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2994182420
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3876778
Short name T566
Test name
Test status
Simulation time 1031141708 ps
CPU time 11.67 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:39:38 PM PDT 24
Peak memory 219028 kb
Host smart-fb51f451-ddec-410d-8efc-869e28d44daa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3876778
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3432036501
Short name T650
Test name
Test status
Simulation time 2436407810 ps
CPU time 10.45 seconds
Started Aug 19 04:39:18 PM PDT 24
Finished Aug 19 04:39:28 PM PDT 24
Peak memory 225844 kb
Host smart-94275a31-1e55-420f-ac44-6d68e9a01d58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432036501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3432036501
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.427296371
Short name T443
Test name
Test status
Simulation time 1368372053 ps
CPU time 9 seconds
Started Aug 19 04:39:25 PM PDT 24
Finished Aug 19 04:39:34 PM PDT 24
Peak memory 226080 kb
Host smart-9f81e5b7-2d9f-4983-b35b-6d86ee502882
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427296371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.427296371
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3045322028
Short name T584
Test name
Test status
Simulation time 912325081 ps
CPU time 12.47 seconds
Started Aug 19 04:39:23 PM PDT 24
Finished Aug 19 04:39:36 PM PDT 24
Peak memory 226176 kb
Host smart-42d1c9e6-6672-4580-b896-99df63a5ac38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045322028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3045322028
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2692700935
Short name T283
Test name
Test status
Simulation time 61717348 ps
CPU time 3.29 seconds
Started Aug 19 04:39:16 PM PDT 24
Finished Aug 19 04:39:19 PM PDT 24
Peak memory 217800 kb
Host smart-6effdac9-a125-4d6e-913d-0fea0b9d5857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692700935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2692700935
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1049143311
Short name T35
Test name
Test status
Simulation time 213347080 ps
CPU time 21.33 seconds
Started Aug 19 04:39:16 PM PDT 24
Finished Aug 19 04:39:38 PM PDT 24
Peak memory 251132 kb
Host smart-c3d9b197-52e5-4d66-84b3-bf164b8e1013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049143311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1049143311
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3559911464
Short name T441
Test name
Test status
Simulation time 332729506 ps
CPU time 8.68 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:39:35 PM PDT 24
Peak memory 251012 kb
Host smart-3787ad82-b3ab-4377-9828-5f8603331f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559911464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3559911464
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2770366273
Short name T194
Test name
Test status
Simulation time 14498058464 ps
CPU time 112.3 seconds
Started Aug 19 04:39:17 PM PDT 24
Finished Aug 19 04:41:10 PM PDT 24
Peak memory 275492 kb
Host smart-a6891a56-eb95-46de-a4be-a3984f564afc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770366273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2770366273
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3503660035
Short name T152
Test name
Test status
Simulation time 2172280976 ps
CPU time 40.98 seconds
Started Aug 19 04:39:31 PM PDT 24
Finished Aug 19 04:40:12 PM PDT 24
Peak memory 251144 kb
Host smart-2d21de64-e559-414f-a245-1d59c351d198
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3503660035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3503660035
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.579600453
Short name T790
Test name
Test status
Simulation time 42543916 ps
CPU time 1.11 seconds
Started Aug 19 04:39:16 PM PDT 24
Finished Aug 19 04:39:17 PM PDT 24
Peak memory 217904 kb
Host smart-88f86d99-35b7-421b-b6e1-c35a1b1adf43
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579600453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.579600453
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3796372033
Short name T496
Test name
Test status
Simulation time 80865862 ps
CPU time 0.96 seconds
Started Aug 19 04:39:32 PM PDT 24
Finished Aug 19 04:39:33 PM PDT 24
Peak memory 209000 kb
Host smart-107286d8-0246-42b1-b2b1-974ac7212ce9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796372033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3796372033
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.576456148
Short name T598
Test name
Test status
Simulation time 12588581 ps
CPU time 0.86 seconds
Started Aug 19 04:39:25 PM PDT 24
Finished Aug 19 04:39:26 PM PDT 24
Peak memory 208892 kb
Host smart-3053d4d9-9f62-42b6-bde4-991fdc8b9370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576456148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.576456148
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.303943503
Short name T757
Test name
Test status
Simulation time 216545893 ps
CPU time 8.04 seconds
Started Aug 19 04:39:16 PM PDT 24
Finished Aug 19 04:39:24 PM PDT 24
Peak memory 226128 kb
Host smart-b26d72c6-f30e-4980-b210-b5d5dc6b8f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303943503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.303943503
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3186022888
Short name T23
Test name
Test status
Simulation time 2456918538 ps
CPU time 10.84 seconds
Started Aug 19 04:39:17 PM PDT 24
Finished Aug 19 04:39:28 PM PDT 24
Peak memory 217644 kb
Host smart-c3348184-2d8e-40b6-ba67-ff62f2b7f1d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186022888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3186022888
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2089718427
Short name T722
Test name
Test status
Simulation time 2138294323 ps
CPU time 25.59 seconds
Started Aug 19 04:39:18 PM PDT 24
Finished Aug 19 04:39:44 PM PDT 24
Peak memory 218368 kb
Host smart-58b9e5f7-525f-4d84-bbe6-a66aae1549fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089718427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2089718427
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3013381084
Short name T693
Test name
Test status
Simulation time 2101755437 ps
CPU time 49.14 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:40:15 PM PDT 24
Peak memory 217860 kb
Host smart-da642a15-72f0-4867-87a7-a3c0c3fb5c07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013381084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
013381084
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1861086546
Short name T327
Test name
Test status
Simulation time 750168041 ps
CPU time 5.38 seconds
Started Aug 19 04:39:25 PM PDT 24
Finished Aug 19 04:39:31 PM PDT 24
Peak memory 223060 kb
Host smart-29c0c9f3-7a00-4625-8b7b-4c794f6c7eea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861086546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1861086546
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2965032438
Short name T454
Test name
Test status
Simulation time 1203933059 ps
CPU time 17.63 seconds
Started Aug 19 04:39:25 PM PDT 24
Finished Aug 19 04:39:43 PM PDT 24
Peak memory 217696 kb
Host smart-8c0fd823-756e-47a1-b2e7-e13158b37c2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965032438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2965032438
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2668948335
Short name T267
Test name
Test status
Simulation time 1090895519 ps
CPU time 8.07 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:39:35 PM PDT 24
Peak memory 217664 kb
Host smart-0cc29003-6b02-426b-8c22-8ef3218c9e8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668948335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2668948335
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2383696578
Short name T371
Test name
Test status
Simulation time 1616124465 ps
CPU time 39.84 seconds
Started Aug 19 04:39:18 PM PDT 24
Finished Aug 19 04:39:57 PM PDT 24
Peak memory 267308 kb
Host smart-95a57213-9584-4e8a-ba9d-4d5977168cea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383696578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2383696578
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1159003398
Short name T672
Test name
Test status
Simulation time 457684034 ps
CPU time 18.21 seconds
Started Aug 19 04:39:15 PM PDT 24
Finished Aug 19 04:39:34 PM PDT 24
Peak memory 250016 kb
Host smart-cbd1fee5-b2e1-4a16-9629-5e59a65158ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159003398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1159003398
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2757310635
Short name T770
Test name
Test status
Simulation time 407302259 ps
CPU time 3.34 seconds
Started Aug 19 04:39:16 PM PDT 24
Finished Aug 19 04:39:20 PM PDT 24
Peak memory 218364 kb
Host smart-082a091f-60a7-4776-b51a-2a082f9fd59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757310635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2757310635
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3576368879
Short name T307
Test name
Test status
Simulation time 242314672 ps
CPU time 9.29 seconds
Started Aug 19 04:39:15 PM PDT 24
Finished Aug 19 04:39:25 PM PDT 24
Peak memory 217780 kb
Host smart-22079d42-190d-48b9-a9b1-0ed8780d893e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576368879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3576368879
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2259506439
Short name T847
Test name
Test status
Simulation time 1913450643 ps
CPU time 12.53 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:39:39 PM PDT 24
Peak memory 218436 kb
Host smart-308aa18a-77cb-4052-b6bc-1f61c33dbc9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259506439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2259506439
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1692147761
Short name T109
Test name
Test status
Simulation time 1755772278 ps
CPU time 14.78 seconds
Started Aug 19 04:39:26 PM PDT 24
Finished Aug 19 04:39:41 PM PDT 24
Peak memory 226108 kb
Host smart-627ea50a-cecd-47d9-87c7-8630508f88cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692147761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1692147761
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3401453935
Short name T540
Test name
Test status
Simulation time 269572200 ps
CPU time 9.24 seconds
Started Aug 19 04:39:27 PM PDT 24
Finished Aug 19 04:39:36 PM PDT 24
Peak memory 218304 kb
Host smart-47ef5287-8b97-4005-b6d7-932440f09528
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401453935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
401453935
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2057643114
Short name T624
Test name
Test status
Simulation time 239708974 ps
CPU time 9.42 seconds
Started Aug 19 04:39:24 PM PDT 24
Finished Aug 19 04:39:33 PM PDT 24
Peak memory 226152 kb
Host smart-fee974c0-d4fd-4c2c-938f-a4f494bb10d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057643114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2057643114
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1877462908
Short name T105
Test name
Test status
Simulation time 52086000 ps
CPU time 2.87 seconds
Started Aug 19 04:39:22 PM PDT 24
Finished Aug 19 04:39:25 PM PDT 24
Peak memory 217784 kb
Host smart-bc3bed38-ba22-427c-b33d-310845feca78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877462908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1877462908
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.778732136
Short name T700
Test name
Test status
Simulation time 833821532 ps
CPU time 24.06 seconds
Started Aug 19 04:39:28 PM PDT 24
Finished Aug 19 04:39:52 PM PDT 24
Peak memory 250960 kb
Host smart-343a45c5-0991-4201-9479-979dd31bcda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778732136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.778732136
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3182293164
Short name T246
Test name
Test status
Simulation time 75613507 ps
CPU time 8.55 seconds
Started Aug 19 04:39:17 PM PDT 24
Finished Aug 19 04:39:25 PM PDT 24
Peak memory 250984 kb
Host smart-09764355-64a5-4024-8e22-772a302f848f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182293164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3182293164
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2542535413
Short name T821
Test name
Test status
Simulation time 10787395625 ps
CPU time 48.18 seconds
Started Aug 19 04:39:25 PM PDT 24
Finished Aug 19 04:40:13 PM PDT 24
Peak memory 251216 kb
Host smart-52a3cdef-0b25-47eb-9d8b-392a3efbee5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542535413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2542535413
Directory /workspace/9.lc_ctrl_stress_all/latest
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