Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55388281

1

T1

3154

T2

944

T3

1299

auto[1]

1056148

1

T4

891

T5

99

T12

7774

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55385406

1

T1

3154

T2

944

T3

1299

auto[1]

1059023

1

T4

495

T5

198

T12

7492

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5088426	1			T1	704		T2	67		T3	99
auto[IdleSt]	16684099	1			T1	755		T2	52		T3	1200
auto[ClkMuxSt]	29938	1			T1	8		T2	1		T4	14
auto[CntIncrSt]	29752	1			T1	8		T2	1		T4	14
auto[CntProgSt]	1247491	1			T1	141		T2	2		T4	189
auto[TransCheckSt]	23437	1			T1	8		T2	1		T5	5
auto[TokenHashSt]	12977443	1			T1	206		T2	115		T5	56
auto[FlashRmaSt]	29518	1			T1	8		T2	1		T5	27
auto[TokenCheck0St]	10539	1			T1	8		T2	1		T5	5
auto[TokenCheck1St]	7566	1			T1	8		T2	1		T5	5
auto[TransProgSt]	280365	1			T1	140		T2	2		T5	408
auto[PostTransSt]	9340687	1			T1	1160		T2	700		T4	1028
auto[ScrapSt]	271213	1			T12	4		T48	193		T17	745
auto[EscalateSt]	4297984	1			T4	1855		T5	418		T12	12161
auto[InvalidSt]	6124761	1			T5	259		T13	3850		T16	4190

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1210	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6124761	1			T5	259		T13	3850		T16	4190
EscalateSt	4297984	1			T4	1855		T5	418		T12	12161
ScrapSt	271213	1			T12	4		T48	193		T17	745
PostTransSt	9340687	1			T1	1160		T2	700		T4	1028
TransProgSt	280365	1			T1	140		T2	2		T5	408
TokenCheck1St	7566	1			T1	8		T2	1		T5	5
TokenCheck0St	10539	1			T1	8		T2	1		T5	5
FlashRmaSt	29518	1			T1	8		T2	1		T5	27
TokenHashSt	12977443	1			T1	206		T2	115		T5	56
TransCheckSt	23437	1			T1	8		T2	1		T5	5
CntProgSt	1247491	1			T1	141		T2	2		T4	189
CntIncrSt	29752	1			T1	8		T2	1		T4	14
ClkMuxSt	29938	1			T1	8		T2	1		T4	14
IdleSt	16684099	1			T1	755		T2	52		T3	1200
ResetSt	5088426	1			T1	704		T2	67		T3	99
arcs[ResetSt=>IdleSt]	42215	1			T1	8		T2	1		T3	1
arcs[IdleSt=>ScrapSt]	245	1			T12	1		T48	3		T17	1
arcs[IdleSt=>ClkMuxSt]	29774	1			T1	8		T2	1		T4	14
arcs[ClkMuxSt=>CntIncrSt]	29752	1			T1	8		T2	1		T4	14
arcs[CntIncrSt=>PostTransSt]	1410	1			T14	11		T40	14		T47	11
arcs[CntIncrSt=>CntProgSt]	28291	1			T1	8		T2	1		T4	14
arcs[CntProgSt=>PostTransSt]	3679	1			T4	14		T7	10		T14	8
arcs[CntProgSt=>TransCheckSt]	23437	1			T1	8		T2	1		T5	5
arcs[TransCheckSt=>PostTransSt]	3259	1			T14	7		T23	30		T40	12
arcs[TransCheckSt=>TokenHashSt]	20084	1			T1	8		T2	1		T5	5
arcs[TokenHashSt=>PostTransSt]	8767	1			T14	25		T16	8		T23	11
arcs[TokenHashSt=>FlashRmaSt]	10576	1			T1	8		T2	1		T5	5
arcs[FlashRmaSt=>TokenCheck0St]	10539	1			T1	8		T2	1		T5	5
arcs[TokenCheck0St=>PostTransSt]	2921	1			T14	11		T16	17		T23	13
arcs[TokenCheck0St=>TokenCheck1St]	7566	1			T1	8		T2	1		T5	5
arcs[TokenCheck1St=>PostTransSt]	595	1			T16	1		T23	9		T46	10
arcs[TransProgSt=>PostTransSt]	6089	1			T1	8		T2	1		T5	5
arcs[IdleSt=>EscalateSt]	128	1			T69	7		T64	3		T65	3
arcs[ClkMuxSt=>EscalateSt]	22	1			T64	2		T65	1		T66	1
arcs[CntIncrSt=>EscalateSt]	51	1			T64	1		T67	2		T68	1
arcs[CntProgSt=>EscalateSt]	1175	1			T12	6		T45	42		T69	14
arcs[TransCheckSt=>EscalateSt]	94	1			T12	6		T69	2		T65	1
arcs[TokenHashSt=>EscalateSt]	741	1			T12	28		T45	9		T69	10
arcs[FlashRmaSt=>EscalateSt]	37	1			T45	3		T69	1		T70	1
arcs[TokenCheck0St=>EscalateSt]	52	1			T12	1		T45	1		T69	1
arcs[TokenCheck1St=>EscalateSt]	36	1			T12	1		T69	2		T72	2
arcs[TransProgSt=>EscalateSt]	846	1			T12	13		T45	22		T69	19
arcs[PostTransSt=>EscalateSt]	3949	1			T4	14		T12	11		T7	10
arcs[InvalidSt=>EscalateSt]	8859	1			T5	3		T13	53		T16	29

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5088278	1			T1	704		T2	67		T3	99
auto[0]	auto[IdleSt]	16684016	1			T1	755		T2	52		T3	1200
auto[0]	auto[ClkMuxSt]	29923	1			T1	8		T2	1		T4	14
auto[0]	auto[CntIncrSt]	29719	1			T1	8		T2	1		T4	14
auto[0]	auto[CntProgSt]	1246680	1			T1	141		T2	2		T4	189
auto[0]	auto[TransCheckSt]	23368	1			T1	8		T2	1		T5	5
auto[0]	auto[TokenHashSt]	12976963	1			T1	206		T2	115		T5	56
auto[0]	auto[FlashRmaSt]	29494	1			T1	8		T2	1		T5	27
auto[0]	auto[TokenCheck0St]	10503	1			T1	8		T2	1		T5	5
auto[0]	auto[TokenCheck1St]	7544	1			T1	8		T2	1		T5	5
auto[0]	auto[TransProgSt]	279819	1			T1	140		T2	2		T5	408
auto[0]	auto[PostTransSt]	9338677	1			T1	1160		T2	700		T4	1019
auto[0]	auto[ScrapSt]	271176	1			T12	4		T48	193		T17	745
auto[0]	auto[EscalateSt]	3250545	1			T4	973		T5	320		T12	4433
auto[0]	auto[InvalidSt]	6120366	1			T5	258		T13	3831		T16	4181
auto[1]	auto[ResetSt]	148	1			T12	6		T45	4		T70	1
auto[1]	auto[IdleSt]	83	1			T69	6		T64	2		T65	1
auto[1]	auto[ClkMuxSt]	15	1			T64	1		T65	1		T66	1
auto[1]	auto[CntIncrSt]	33	1			T64	1		T68	1		T72	1
auto[1]	auto[CntProgSt]	811	1			T12	5		T45	28		T69	9
auto[1]	auto[TransCheckSt]	69	1			T12	5		T69	2		T65	1
auto[1]	auto[TokenHashSt]	480	1			T12	15		T45	5		T69	10
auto[1]	auto[FlashRmaSt]	24	1			T45	1		T70	1		T67	1
auto[1]	auto[TokenCheck0St]	36	1			T12	1		T69	1		T64	1
auto[1]	auto[TokenCheck1St]	22	1			T12	1		T69	2		T72	2
auto[1]	auto[TransProgSt]	546	1			T12	8		T45	12		T69	10
auto[1]	auto[PostTransSt]	2010	1			T4	9		T12	5		T7	4
auto[1]	auto[ScrapSt]	37	1			T69	1		T64	1		T68	1
auto[1]	auto[EscalateSt]	1047439	1			T4	882		T5	98		T12	7728
auto[1]	auto[InvalidSt]	4395	1			T5	1		T13	19		T16	9

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5088287	1			T1	704		T2	67		T3	99
auto[0]	auto[IdleSt]	16684010	1			T1	755		T2	52		T3	1200
auto[0]	auto[ClkMuxSt]	29923	1			T1	8		T2	1		T4	14
auto[0]	auto[CntIncrSt]	29717	1			T1	8		T2	1		T4	14
auto[0]	auto[CntProgSt]	1246719	1			T1	141		T2	2		T4	189
auto[0]	auto[TransCheckSt]	23379	1			T1	8		T2	1		T5	5
auto[0]	auto[TokenHashSt]	12976962	1			T1	206		T2	115		T5	56
auto[0]	auto[FlashRmaSt]	29493	1			T1	8		T2	1		T5	27
auto[0]	auto[TokenCheck0St]	10507	1			T1	8		T2	1		T5	5
auto[0]	auto[TokenCheck1St]	7544	1			T1	8		T2	1		T5	5
auto[0]	auto[TransProgSt]	279788	1			T1	140		T2	2		T5	408
auto[0]	auto[PostTransSt]	9338673	1			T1	1160		T2	700		T4	1023
auto[0]	auto[ScrapSt]	271177	1			T12	3		T48	193		T17	745
auto[0]	auto[EscalateSt]	3247720	1			T4	1365		T5	222		T12	4715
auto[0]	auto[InvalidSt]	6120297	1			T5	257		T13	3816		T16	4170
auto[1]	auto[ResetSt]	139	1			T12	4		T45	5		T69	1
auto[1]	auto[IdleSt]	89	1			T69	3		T64	1		T65	2
auto[1]	auto[ClkMuxSt]	15	1			T64	2		T72	2		T229	1
auto[1]	auto[CntIncrSt]	35	1			T67	2		T68	1		T72	1
auto[1]	auto[CntProgSt]	772	1			T12	2		T45	26		T69	12
auto[1]	auto[TransCheckSt]	58	1			T12	1		T69	2		T65	1
auto[1]	auto[TokenHashSt]	481	1			T12	20		T45	6		T69	5
auto[1]	auto[FlashRmaSt]	25	1			T45	3		T69	1		T70	1
auto[1]	auto[TokenCheck0St]	32	1			T12	1		T45	1		T69	1
auto[1]	auto[TokenCheck1St]	22	1			T69	2		T72	2		T230	1
auto[1]	auto[TransProgSt]	577	1			T12	9		T45	16		T69	14
auto[1]	auto[PostTransSt]	2014	1			T4	5		T12	8		T7	6
auto[1]	auto[ScrapSt]	36	1			T12	1		T69	1		T64	2
auto[1]	auto[EscalateSt]	1050264	1			T4	490		T5	196		T12	7446
auto[1]	auto[InvalidSt]	4464	1			T5	2		T13	34		T16	20