Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62273820

1

T1

1103

T2

7663

T3

13457

auto[1]

1089586

1

T3

198

T4

99

T15

396

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62280850

1

T1

1103

T2

7663

T3

13556

auto[1]

1082556

1

T3

99

T5

98

T15

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5237238	1			T1	99		T2	1761		T3	1347
auto[IdleSt]	17051527	1			T1	209		T2	2364		T3	2103
auto[ClkMuxSt]	29279	1			T1	1		T2	18		T3	9
auto[CntIncrSt]	29108	1			T1	1		T2	18		T3	9
auto[CntProgSt]	1293759	1			T1	2		T2	264		T3	267
auto[TransCheckSt]	23240	1			T1	1		T2	18		T3	9
auto[TokenHashSt]	17587186	1			T1	49		T2	1858		T3	6360
auto[FlashRmaSt]	29218	1			T1	1		T2	34		T3	9
auto[TokenCheck0St]	10190	1			T1	1		T2	18		T3	9
auto[TokenCheck1St]	7262	1			T1	1		T2	18		T3	9
auto[TransProgSt]	340240	1			T1	2		T2	265		T3	275
auto[PostTransSt]	9882654	1			T1	736		T2	986		T3	2227
auto[ScrapSt]	335202	1			T2	41		T7	377		T16	15
auto[EscalateSt]	4532493	1			T3	633		T4	141		T5	533
auto[InvalidSt]	6973499	1			T3	388		T44	3142		T45	144

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1311	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6973499	1			T3	388		T44	3142		T45	144
EscalateSt	4532493	1			T3	633		T4	141		T5	533
ScrapSt	335202	1			T2	41		T7	377		T16	15
PostTransSt	9882654	1			T1	736		T2	986		T3	2227
TransProgSt	340240	1			T1	2		T2	265		T3	275
TokenCheck1St	7262	1			T1	1		T2	18		T3	9
TokenCheck0St	10190	1			T1	1		T2	18		T3	9
FlashRmaSt	29218	1			T1	1		T2	34		T3	9
TokenHashSt	17587186	1			T1	49		T2	1858		T3	6360
TransCheckSt	23240	1			T1	1		T2	18		T3	9
CntProgSt	1293759	1			T1	2		T2	264		T3	267
CntIncrSt	29108	1			T1	1		T2	18		T3	9
ClkMuxSt	29279	1			T1	1		T2	18		T3	9
IdleSt	17051527	1			T1	209		T2	2364		T3	2103
ResetSt	5237238	1			T1	99		T2	1761		T3	1347
arcs[ResetSt=>IdleSt]	42360	1			T1	1		T2	19		T3	13
arcs[IdleSt=>ScrapSt]	219	1			T2	1		T7	1		T16	1
arcs[IdleSt=>ClkMuxSt]	29140	1			T1	1		T2	18		T3	9
arcs[ClkMuxSt=>CntIncrSt]	29108	1			T1	1		T2	18		T3	9
arcs[CntIncrSt=>PostTransSt]	1352	1			T15	10		T43	5		T37	13
arcs[CntIncrSt=>CntProgSt]	27704	1			T1	1		T2	18		T3	9
arcs[CntProgSt=>PostTransSt]	3482	1			T4	1		T5	1		T15	7
arcs[CntProgSt=>TransCheckSt]	23240	1			T1	1		T2	18		T3	9
arcs[TransCheckSt=>PostTransSt]	3224	1			T15	10		T17	28		T43	10
arcs[TransCheckSt=>TokenHashSt]	19911	1			T1	1		T2	18		T3	9
arcs[TokenHashSt=>PostTransSt]	8903	1			T14	56		T15	30		T17	12
arcs[TokenHashSt=>FlashRmaSt]	10232	1			T1	1		T2	18		T3	9
arcs[FlashRmaSt=>TokenCheck0St]	10190	1			T1	1		T2	18		T3	9
arcs[TokenCheck0St=>PostTransSt]	2878	1			T15	4		T17	16		T42	17
arcs[TokenCheck0St=>TokenCheck1St]	7262	1			T1	1		T2	18		T3	9
arcs[TokenCheck1St=>PostTransSt]	604	1			T15	3		T17	8		T42	2
arcs[TransProgSt=>PostTransSt]	5887	1			T1	1		T2	18		T3	9
arcs[IdleSt=>EscalateSt]	124	1			T18	5		T62	3		T41	6
arcs[ClkMuxSt=>EscalateSt]	32	1			T62	1		T41	1		T63	3
arcs[CntIncrSt=>EscalateSt]	52	1			T18	1		T62	2		T64	1
arcs[CntProgSt=>EscalateSt]	982	1			T18	34		T62	21		T41	23
arcs[TransCheckSt=>EscalateSt]	105	1			T62	1		T41	2		T65	7
arcs[TokenHashSt=>EscalateSt]	776	1			T18	5		T62	13		T41	4
arcs[FlashRmaSt=>EscalateSt]	42	1			T18	1		T65	1		T64	1
arcs[TokenCheck0St=>EscalateSt]	50	1			T18	2		T41	4		T65	2
arcs[TokenCheck1St=>EscalateSt]	33	1			T18	1		T69	2		T70	1
arcs[TransProgSt=>EscalateSt]	738	1			T18	29		T62	15		T41	10
arcs[PostTransSt=>EscalateSt]	3826	1			T4	1		T5	1		T15	7
arcs[InvalidSt=>EscalateSt]	9489	1			T3	3		T44	42		T45	2

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5237065	1			T1	99		T2	1761		T3	1347
auto[0]	auto[IdleSt]	17051445	1			T1	209		T2	2364		T3	2103
auto[0]	auto[ClkMuxSt]	29259	1			T1	1		T2	18		T3	9
auto[0]	auto[CntIncrSt]	29076	1			T1	1		T2	18		T3	9
auto[0]	auto[CntProgSt]	1293085	1			T1	2		T2	264		T3	267
auto[0]	auto[TransCheckSt]	23169	1			T1	1		T2	18		T3	9
auto[0]	auto[TokenHashSt]	17586661	1			T1	49		T2	1858		T3	6360
auto[0]	auto[FlashRmaSt]	29190	1			T1	1		T2	34		T3	9
auto[0]	auto[TokenCheck0St]	10150	1			T1	1		T2	18		T3	9
auto[0]	auto[TokenCheck1St]	7239	1			T1	1		T2	18		T3	9
auto[0]	auto[TransProgSt]	339758	1			T1	2		T2	265		T3	275
auto[0]	auto[PostTransSt]	9880651	1			T1	736		T2	986		T3	2227
auto[0]	auto[ScrapSt]	335166	1			T2	41		T7	377		T16	15
auto[0]	auto[EscalateSt]	3451822	1			T3	437		T4	43		T5	533
auto[0]	auto[InvalidSt]	6968773	1			T3	386		T44	3118		T45	142
auto[1]	auto[ResetSt]	173	1			T18	3		T62	7		T41	2
auto[1]	auto[IdleSt]	82	1			T18	3		T62	2		T41	6
auto[1]	auto[ClkMuxSt]	20	1			T62	1		T41	1		T63	3
auto[1]	auto[CntIncrSt]	32	1			T18	1		T62	2		T64	1
auto[1]	auto[CntProgSt]	674	1			T18	26		T62	17		T41	15
auto[1]	auto[TransCheckSt]	71	1			T62	1		T65	5		T69	2
auto[1]	auto[TokenHashSt]	525	1			T18	4		T62	9		T41	4
auto[1]	auto[FlashRmaSt]	28	1			T64	1		T69	3		T70	1
auto[1]	auto[TokenCheck0St]	40	1			T18	2		T41	3		T65	2
auto[1]	auto[TokenCheck1St]	23	1			T69	1		T70	1		T222	1
auto[1]	auto[TransProgSt]	482	1			T18	22		T62	9		T41	8
auto[1]	auto[PostTransSt]	2003	1			T4	1		T15	4		T18	2
auto[1]	auto[ScrapSt]	36	1			T18	1		T62	1		T65	2
auto[1]	auto[EscalateSt]	1080671	1			T3	196		T4	98		T15	392
auto[1]	auto[InvalidSt]	4726	1			T3	2		T44	24		T45	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5237056	1			T1	99		T2	1761		T3	1347
auto[0]	auto[IdleSt]	17051433	1			T1	209		T2	2364		T3	2103
auto[0]	auto[ClkMuxSt]	29258	1			T1	1		T2	18		T3	9
auto[0]	auto[CntIncrSt]	29065	1			T1	1		T2	18		T3	9
auto[0]	auto[CntProgSt]	1293120	1			T1	2		T2	264		T3	267
auto[0]	auto[TransCheckSt]	23174	1			T1	1		T2	18		T3	9
auto[0]	auto[TokenHashSt]	17586669	1			T1	49		T2	1858		T3	6360
auto[0]	auto[FlashRmaSt]	29191	1			T1	1		T2	34		T3	9
auto[0]	auto[TokenCheck0St]	10160	1			T1	1		T2	18		T3	9
auto[0]	auto[TokenCheck1St]	7242	1			T1	1		T2	18		T3	9
auto[0]	auto[TransProgSt]	339754	1			T1	2		T2	265		T3	275
auto[0]	auto[PostTransSt]	9880727	1			T1	736		T2	986		T3	2227
auto[0]	auto[ScrapSt]	335157	1			T2	41		T7	377		T16	15
auto[0]	auto[EscalateSt]	3458797	1			T3	535		T4	141		T5	436
auto[0]	auto[InvalidSt]	6968736	1			T3	387		T44	3124		T45	144
auto[1]	auto[ResetSt]	182	1			T18	5		T62	6		T41	4
auto[1]	auto[IdleSt]	94	1			T18	4		T62	2		T41	3
auto[1]	auto[ClkMuxSt]	21	1			T41	1		T63	1		T70	1
auto[1]	auto[CntIncrSt]	43	1			T64	1		T63	1		T70	2
auto[1]	auto[CntProgSt]	639	1			T18	18		T62	17		T41	16
auto[1]	auto[TransCheckSt]	66	1			T62	1		T41	2		T65	5
auto[1]	auto[TokenHashSt]	517	1			T18	4		T62	10		T41	1
auto[1]	auto[FlashRmaSt]	27	1			T18	1		T65	1		T69	2
auto[1]	auto[TokenCheck0St]	30	1			T41	3		T65	1		T69	2
auto[1]	auto[TokenCheck1St]	20	1			T18	1		T69	1		T70	1
auto[1]	auto[TransProgSt]	486	1			T18	17		T62	12		T41	4
auto[1]	auto[PostTransSt]	1927	1			T5	1		T15	3		T18	2
auto[1]	auto[ScrapSt]	45	1			T18	1		T62	3		T65	1
auto[1]	auto[EscalateSt]	1073696	1			T3	98		T5	97		T15	294
auto[1]	auto[InvalidSt]	4763	1			T3	1		T44	18		T42	12