Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

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Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_q	8	0	8	100.00	100	1	1	0

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_states[ClkMuxSt]	444	1			T17	7		T40	6		T46	7
fsm_states[CntIncrSt]	460	1			T17	5		T40	8		T46	10
fsm_states[CntProgSt]	437	1			T17	9		T40	8		T46	8
fsm_states[TransCheckSt]	446	1			T17	7		T40	6		T46	8
fsm_states[FlashRmaSt]	456	1			T17	9		T40	6		T46	6
fsm_states[TokenHashSt]	446	1			T17	12		T40	7		T46	5
fsm_states[TokenCheck0St]	461	1			T17	7		T40	11		T46	10
fsm_states[TokenCheck1St]	461	1			T17	8		T40	5		T46	10