Unified Coverage Report :: Module :: lc_ctrl

Module : lc_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.52	100.00	81.94	98.16		100.00	87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.10	100.00	83.10	99.89		100.00	87.50

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.10	100.00	83.10	99.89		100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.00	97.97	95.41	93.40	97.67	98.53	99.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_alert_tx[2].u_prim_alert_sender	100.00			100.00
lc_ctrl_csr_assert	100.00						100.00
tlul_assert_device	100.00						100.00
u_dmi_jtag	80.46			80.46
u_lc_ctrl_fsm	97.38	99.39	89.84		100.00	97.67	100.00
u_lc_ctrl_kmac_if	96.03	99.10	100.00		83.33	97.73	100.00
u_prim_clock_mux2	85.19	100.00	55.56				100.00
u_prim_esc_receiver0	16.07			16.07
u_prim_esc_receiver1	16.07			16.07
u_prim_flop_2sync_init	100.00	100.00				100.00
u_prim_lc_sync	100.00	100.00					100.00
u_prim_mubi4_dec	0.00	0.00
u_prim_rst_n_mux2	85.19	100.00	55.56				100.00
u_reg	99.10	97.79	97.70	100.00		100.00	100.00
u_reg_tap	93.90	97.36	98.54	73.61		100.00	100.00
u_tap_tlul_host	81.19	98.00	92.86	15.09		100.00	100.00

Line Coverage for Module : lc_ctrl

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
ALWAYS	318	41	41	100.00
ALWAYS	369	41	41	100.00
ALWAYS	467	33	33	100.00
ALWAYS	526	3	3	100.00
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	583	1	1	100.00
ALWAYS	669	5	5	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	679	1	1	100.00

212                       logic req_ready;
213        1/1            assign req_ready = dmi_req_ready & dmi_resp_ready;
           Tests:       T1 T2 T3 
214                       dmi_jtag #(
215                         .IdcodeValue(IdcodeValue),
216                         .NumDmiWordAbits(7)
217                       ) u_dmi_jtag (
218                         .clk_i,
219                         .rst_ni,
220                         .testmode_i       ( scanmode          ),
221                         .test_rst_ni      ( scan_rst_ni       ),
222                         .dmi_rst_no       (                   ), // unused
223                         .dmi_req_o        ( dmi_req           ),
224                         .dmi_req_valid_o  ( dmi_req_valid     ),
225                         // unless there is room for response, stall
226                         .dmi_req_ready_i  ( req_ready         ),
227                         .dmi_resp_i       ( dmi_resp          ),
228                         .dmi_resp_ready_o ( dmi_resp_ready    ),
229                         .dmi_resp_valid_i ( dmi_resp_valid    ),
230                         .tck_i            ( tck_muxed         ),
231                         .tms_i            ( jtag_i.tms        ),
232                         .trst_ni          ( trst_n_muxed      ),
233                         .td_i             ( jtag_i.tdi        ),
234                         .td_o             ( jtag_o.tdo        ),
235                         .tdo_oe_o         ( jtag_o.tdo_oe     )
236                       );
237                     
238                       // DMI to TL-UL transducing
239                       tlul_adapter_host #(
240                         .EnableDataIntgGen(1)
241                       ) u_tap_tlul_host (
242                         .clk_i,
243                         .rst_ni,
244                         // do not make a request unless there is room for the response
245                         .req_i        ( dmi_req_valid & dmi_resp_ready         ),
246                         .gnt_o        ( dmi_req_ready                          ),
247                         .addr_i       ( top_pkg::TL_AW'({dmi_req.addr, 2'b00}) ),
248                         .we_i         ( dmi_req.op == dm::DTM_WRITE            ),
249                         .wdata_i      ( dmi_req.data                           ),
250                         .wdata_intg_i ('0                                      ),
251                         .be_i         ( {top_pkg::TL_DBW{1'b1}}                ),
252                         .user_rsvd_i  ('0                                      ),
253                         .instr_type_i ( prim_mubi_pkg::MuBi4False              ),
254                         .valid_o      ( dmi_resp_valid                         ),
255                         .rdata_o      ( dmi_resp.data                          ),
256                         .rdata_intg_o (                                        ),
257                         .err_o        (                                        ),
258                         .intg_err_o   (                                        ),
259                         .tl_o         ( tap_tl_h2d                             ),
260                         .tl_i         ( tap_tl_d2h                             )
261                       );
262                     
263                       // TL-UL to DMI transducing
264                       assign dmi_resp.resp = '0; // unused inside dmi_jtag
265                     
266                       // These signals are unused
267                       logic unused_tap_tl_d2h;
268        1/1            assign unused_tap_tl_d2h = ^{
           Tests:       T1 T2 T3 
269                         dmi_req.addr[31:30],
270                         tap_tl_d2h.d_opcode,
271                         tap_tl_d2h.d_param,
272                         tap_tl_d2h.d_size,
273                         tap_tl_d2h.d_source,
274                         tap_tl_d2h.d_sink,
275                         tap_tl_d2h.d_user,
276                         tap_tl_d2h.d_error
277                       };
278                     
279                       ///////////////////////////////////////
280                       // Transition Interface and HW Mutex //
281                       ///////////////////////////////////////
282                     
283                       // All registers are HWext
284                       logic          trans_success_d, trans_success_q;
285                       logic          trans_cnt_oflw_error_d, trans_cnt_oflw_error_q;
286                       logic          trans_invalid_error_d, trans_invalid_error_q;
287                       logic          token_invalid_error_d, token_invalid_error_q;
288                       logic          flash_rma_error_d, flash_rma_error_q;
289                       logic          otp_prog_error_d, fatal_prog_error_q;
290                       logic          state_invalid_error_d, fatal_state_error_q;
291                       logic          otp_part_error_q;
292                       mubi8_t        sw_claim_transition_if_d, sw_claim_transition_if_q;
293                       mubi8_t        tap_claim_transition_if_d, tap_claim_transition_if_q;
294                       logic          transition_cmd;
295                       lc_token_t     transition_token_d, transition_token_q;
296                       ext_dec_lc_state_t transition_target_d, transition_target_q;
297                       // No need to register these.
298                       ext_dec_lc_state_t dec_lc_state;
299                       dec_lc_cnt_t       dec_lc_cnt;
300                       dec_lc_id_state_e  dec_lc_id_state;
301                     
302                       logic lc_idle_d, lc_done_d;
303                     
304                       // Assign hardware revision output
305                       assign hw_rev_o = '{silicon_creator_id: SiliconCreatorId,
306                                           product_id:         ProductId,
307                                           revision_id:        RevisionId,
308                                           reserved:           '0};
309                     
310                       // OTP Vendor control bits
311                       logic ext_clock_switched;
312                       logic use_ext_clock_d, use_ext_clock_q;
313                       logic volatile_raw_unlock_d, volatile_raw_unlock_q;
314                       logic [CsrOtpTestCtrlWidth-1:0] otp_vendor_test_ctrl_d, otp_vendor_test_ctrl_q;
315                       logic [CsrOtpTestStatusWidth-1:0] otp_vendor_test_status;
316                     
317                       always_comb begin : p_csr_assign_outputs
318        1/1              hw2reg = '0;
           Tests:       T1 T2 T3 
319        1/1              hw2reg.status.initialized            = lc_done_d;
           Tests:       T1 T2 T3 
320        1/1              hw2reg.status.ready                  = lc_idle_d;
           Tests:       T1 T2 T3 
321        1/1              hw2reg.status.ext_clock_switched     = ext_clock_switched;
           Tests:       T1 T2 T3 
322        1/1              hw2reg.status.transition_successful  = trans_success_q;
           Tests:       T1 T2 T3 
323        1/1              hw2reg.status.transition_count_error = trans_cnt_oflw_error_q;
           Tests:       T1 T2 T3 
324        1/1              hw2reg.status.transition_error       = trans_invalid_error_q;
           Tests:       T1 T2 T3 
325        1/1              hw2reg.status.token_error            = token_invalid_error_q;
           Tests:       T1 T2 T3 
326        1/1              hw2reg.status.flash_rma_error        = flash_rma_error_q;
           Tests:       T1 T2 T3 
327        1/1              hw2reg.status.otp_error              = fatal_prog_error_q;
           Tests:       T1 T2 T3 
328        1/1              hw2reg.status.state_error            = fatal_state_error_q;
           Tests:       T1 T2 T3 
329        1/1              hw2reg.status.otp_partition_error    = otp_part_error_q;
           Tests:       T1 T2 T3 
330        1/1              hw2reg.status.bus_integ_error        = fatal_bus_integ_error_q;
           Tests:       T1 T2 T3 
331        1/1              hw2reg.lc_state                      = dec_lc_state;
           Tests:       T1 T2 T3 
332        1/1              hw2reg.lc_transition_cnt             = dec_lc_cnt;
           Tests:       T1 T2 T3 
333        1/1              hw2reg.lc_id_state                   = {DecLcIdStateNumRep{dec_lc_id_state}};
           Tests:       T1 T2 T3 
334        1/1              hw2reg.device_id                     = otp_device_id_i;
           Tests:       T1 T2 T3 
335        1/1              hw2reg.manuf_state                   = otp_manuf_state_i;
           Tests:       T1 T2 T3 
336        1/1              hw2reg.hw_revision0.silicon_creator_id = hw_rev_o.silicon_creator_id;
           Tests:       T1 T2 T3 
337        1/1              hw2reg.hw_revision0.product_id         = hw_rev_o.product_id;
           Tests:       T1 T2 T3 
338        1/1              hw2reg.hw_revision1.revision_id        = hw_rev_o.revision_id;
           Tests:       T1 T2 T3 
339        1/1              hw2reg.hw_revision1.reserved           = '0;
           Tests:       T1 T2 T3 
340                     
341                         // The assignments above are identical for the TAP.
342        1/1              tap_hw2reg = hw2reg;
           Tests:       T1 T2 T3 
343                     
344                         // Assignments gated by mutex. Again, the TAP has priority.
345        1/1              tap_hw2reg.claim_transition_if = tap_claim_transition_if_q;
           Tests:       T1 T2 T3 
346        1/1              hw2reg.claim_transition_if = sw_claim_transition_if_q;
           Tests:       T1 T2 T3 
347        1/1              if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
348        1/1                tap_hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
           Tests:       T4 T6 T7 
349        1/1                tap_hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
           Tests:       T4 T6 T7 
350        1/1                tap_hw2reg.transition_token  = transition_token_q;
           Tests:       T4 T6 T7 
351        1/1                tap_hw2reg.transition_target = transition_target_q;
           Tests:       T4 T6 T7 
352                           // SEC_CM: TRANSITION.CONFIG.REGWEN
353        1/1                tap_hw2reg.transition_regwen = lc_idle_d;
           Tests:       T4 T6 T7 
354        1/1                tap_hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
           Tests:       T4 T6 T7 
355        1/1                tap_hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
           Tests:       T4 T6 T7 
356        1/1              end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
357        1/1                hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
           Tests:       T1 T2 T12 
358        1/1                hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
           Tests:       T1 T2 T12 
359        1/1                hw2reg.transition_token  = transition_token_q;
           Tests:       T1 T2 T12 
360        1/1                hw2reg.transition_target = transition_target_q;
           Tests:       T1 T2 T12 
361                           // SEC_CM: TRANSITION.CONFIG.REGWEN
362        1/1                hw2reg.transition_regwen = lc_idle_d;
           Tests:       T1 T2 T12 
363        1/1                hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
           Tests:       T1 T2 T12 
364        1/1                hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
           Tests:       T1 T2 T12 
365                         end
                        MISSING_ELSE
366                       end
367                     
368                       always_comb begin : p_csr_assign_inputs
369        1/1              sw_claim_transition_if_d  = sw_claim_transition_if_q;
           Tests:       T1 T2 T3 
370        1/1              tap_claim_transition_if_d = tap_claim_transition_if_q;
           Tests:       T1 T2 T3 
371        1/1              transition_token_d        = transition_token_q;
           Tests:       T1 T2 T3 
372        1/1              transition_target_d       = transition_target_q;
           Tests:       T1 T2 T3 
373        1/1              transition_cmd            = 1'b0;
           Tests:       T1 T2 T3 
374        1/1              otp_vendor_test_ctrl_d    = otp_vendor_test_ctrl_q;
           Tests:       T1 T2 T3 
375        1/1              use_ext_clock_d           = use_ext_clock_q;
           Tests:       T1 T2 T3 
376        1/1              volatile_raw_unlock_d     = volatile_raw_unlock_q;
           Tests:       T1 T2 T3 
377                     
378                         // Note that the mutex claims from the TAP and SW side could arrive within the same cycle.
379                         // In that case we give priority to the TAP mutex claim in order to avoid a race condition.
380                         // TAP mutex claim.
381        1/1              if (mubi8_test_false_loose(sw_claim_transition_if_q) &&
           Tests:       T1 T2 T3 
382                             tap_reg2hw.claim_transition_if.qe) begin
383        1/1                tap_claim_transition_if_d = mubi8_t'(tap_reg2hw.claim_transition_if.q);
           Tests:       T1 T2 T3 
384                         // SW mutex claim.
385        1/1              end else if (mubi8_test_false_loose(tap_claim_transition_if_q) &&
           Tests:       T1 T2 T3 
386                             reg2hw.claim_transition_if.qe) begin
387        1/1                sw_claim_transition_if_d = mubi8_t'(reg2hw.claim_transition_if.q);
           Tests:       T1 T2 T3 
388                         end
                        MISSING_ELSE
389                     
390                     
391                         // The idle signal serves as the REGWEN in this case.
392        1/1              if (lc_idle_d) begin
           Tests:       T1 T2 T3 
393                           // The TAP has priority.
394        1/1                if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
395        1/1                  transition_cmd = tap_reg2hw.transition_cmd.q &
           Tests:       T4 T6 T7 
396                                              tap_reg2hw.transition_cmd.qe;
397                     
398        1/1                  if (tap_reg2hw.transition_ctrl.ext_clock_en.qe) begin
           Tests:       T4 T6 T7 
399        1/1                    use_ext_clock_d |= tap_reg2hw.transition_ctrl.ext_clock_en.q;
           Tests:       T6 T7 T8 
400                             end
                        MISSING_ELSE
401                     
402                             // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
403                             // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
404                             // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
405                             // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
406                             // ---------------------------------------------------------------
407        1/1                  if (tap_reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
           Tests:       T4 T6 T7 
408        1/1                    volatile_raw_unlock_d = tap_reg2hw.transition_ctrl.volatile_raw_unlock.q;
           Tests:       T6 T7 T8 
409                             end
                        MISSING_ELSE
410                             // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
411                     
412        1/1                  for (int k = 0; k < LcTokenWidth/32; k++) begin
           Tests:       T4 T6 T7 
413        1/1                    if (tap_reg2hw.transition_token[k].qe) begin
           Tests:       T4 T6 T7 
414        1/1                      transition_token_d[k*32 +: 32] = tap_reg2hw.transition_token[k].q;
           Tests:       T4 T6 T7 
415                               end
                        MISSING_ELSE
416                             end
417                     
418        1/1                  if (tap_reg2hw.transition_target.qe) begin
           Tests:       T4 T6 T7 
419        1/1                    for (int k = 0; k < DecLcStateNumRep; k++) begin
           Tests:       T4 T6 T7 
420        1/1                      transition_target_d[k] = dec_lc_state_e'(
           Tests:       T4 T6 T7 
421                                     tap_reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
422                               end
423                             end
                        MISSING_ELSE
424                     
425        1/1                  if (tap_reg2hw.otp_vendor_test_ctrl.qe) begin
           Tests:       T4 T6 T7 
426        1/1                    otp_vendor_test_ctrl_d = tap_reg2hw.otp_vendor_test_ctrl.q;
           Tests:       T4 T6 T7 
427                             end
                        MISSING_ELSE
428        1/1                end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
429        1/1                  transition_cmd = reg2hw.transition_cmd.q &
           Tests:       T1 T2 T12 
430                                              reg2hw.transition_cmd.qe;
431                     
432        1/1                  if (reg2hw.transition_ctrl.ext_clock_en.qe) begin
           Tests:       T1 T2 T12 
433        1/1                    use_ext_clock_d |= reg2hw.transition_ctrl.ext_clock_en.q;
           Tests:       T1 T2 T12 
434                             end
                        MISSING_ELSE
435                     
436                             // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
437                             // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
438                             // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
439                             // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
440                             // ---------------------------------------------------------------
441        1/1                  if (reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
           Tests:       T1 T2 T12 
442        1/1                    volatile_raw_unlock_d = reg2hw.transition_ctrl.volatile_raw_unlock.q;
           Tests:       T1 T2 T12 
443                             end
                        MISSING_ELSE
444                             // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
445                     
446        1/1                  for (int k = 0; k < LcTokenWidth/32; k++) begin
           Tests:       T1 T2 T12 
447        1/1                    if (reg2hw.transition_token[k].qe) begin
           Tests:       T1 T2 T12 
448        1/1                      transition_token_d[k*32 +: 32] = reg2hw.transition_token[k].q;
           Tests:       T1 T2 T12 
449                               end
                        MISSING_ELSE
450                             end
451                     
452        1/1                  if (reg2hw.transition_target.qe) begin
           Tests:       T1 T2 T12 
453        1/1                    for (int k = 0; k < DecLcStateNumRep; k++) begin
           Tests:       T1 T2 T12 
454        1/1                      transition_target_d[k] = dec_lc_state_e'(
           Tests:       T1 T2 T12 
455                                     reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
456                               end
457                             end
                        MISSING_ELSE
458                     
459        1/1                  if (reg2hw.otp_vendor_test_ctrl.qe) begin
           Tests:       T1 T2 T12 
460        1/1                    otp_vendor_test_ctrl_d = reg2hw.otp_vendor_test_ctrl.q;
           Tests:       T2 T5 T7 
461                             end
                        MISSING_ELSE
462                           end
                        MISSING_ELSE
463                         end
                        MISSING_ELSE
464                       end
465                     
466                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_csrs
467        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
468        1/1                trans_success_q           <= 1'b0;
           Tests:       T1 T2 T3 
469        1/1                trans_cnt_oflw_error_q    <= 1'b0;
           Tests:       T1 T2 T3 
470        1/1                trans_invalid_error_q     <= 1'b0;
           Tests:       T1 T2 T3 
471        1/1                token_invalid_error_q     <= 1'b0;
           Tests:       T1 T2 T3 
472        1/1                flash_rma_error_q         <= 1'b0;
           Tests:       T1 T2 T3 
473        1/1                fatal_prog_error_q        <= 1'b0;
           Tests:       T1 T2 T3 
474        1/1                fatal_state_error_q       <= 1'b0;
           Tests:       T1 T2 T3 
475        1/1                sw_claim_transition_if_q  <= MuBi8False;
           Tests:       T1 T2 T3 
476        1/1                tap_claim_transition_if_q <= MuBi8False;
           Tests:       T1 T2 T3 
477        1/1                transition_token_q        <= '0;
           Tests:       T1 T2 T3 
478        1/1                transition_target_q       <= {DecLcStateNumRep{DecLcStRaw}};
           Tests:       T1 T2 T3 
479        1/1                otp_part_error_q          <= 1'b0;
           Tests:       T1 T2 T3 
480        1/1                fatal_bus_integ_error_q   <= 1'b0;
           Tests:       T1 T2 T3 
481        1/1                otp_vendor_test_ctrl_q    <= '0;
           Tests:       T1 T2 T3 
482        1/1                use_ext_clock_q           <= 1'b0;
           Tests:       T1 T2 T3 
483                         end else begin
484                           // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
485                           // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
486                           // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
487                           // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
488                           // ---------------------------------------------------------------
489                           // In case of a volatile RAW unlock, this bit has to be cleared when the volatile
490                           // unlock is followed by a real transition.
491                           // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
492        1/1                if (SecVolatileRawUnlockEn && transition_cmd && !volatile_raw_unlock_q) begin
           Tests:       T1 T2 T3 
493        1/1                  trans_success_q <= 1'b0;
           Tests:       T1 T2 T4 
494                           end else begin
495        1/1                  trans_success_q <= trans_success_d | trans_success_q;
           Tests:       T1 T2 T3 
496                           end
497                           // All other status and error bits are terminal and require a reset cycle.
498        1/1                trans_cnt_oflw_error_q    <= trans_cnt_oflw_error_d  | trans_cnt_oflw_error_q;
           Tests:       T1 T2 T3 
499        1/1                trans_invalid_error_q     <= trans_invalid_error_d   | trans_invalid_error_q;
           Tests:       T1 T2 T3 
500        1/1                token_invalid_error_q     <= token_invalid_error_d   | token_invalid_error_q;
           Tests:       T1 T2 T3 
501        1/1                flash_rma_error_q         <= flash_rma_error_d       | flash_rma_error_q;
           Tests:       T1 T2 T3 
502        1/1                fatal_prog_error_q        <= otp_prog_error_d        | fatal_prog_error_q;
           Tests:       T1 T2 T3 
503        1/1                fatal_state_error_q       <= state_invalid_error_d   | fatal_state_error_q;
           Tests:       T1 T2 T3 
504        1/1                otp_part_error_q          <= otp_lc_data_i.error     | otp_part_error_q;
           Tests:       T1 T2 T3 
505        1/1                fatal_bus_integ_error_q   <= fatal_bus_integ_error_csr_d |
           Tests:       T1 T2 T3 
506                                                        fatal_bus_integ_error_tap_d |
507                                                        fatal_bus_integ_error_q;
508                           // Other regs, gated by mutex further below.
509        1/1                sw_claim_transition_if_q  <= sw_claim_transition_if_d;
           Tests:       T1 T2 T3 
510        1/1                tap_claim_transition_if_q <= tap_claim_transition_if_d;
           Tests:       T1 T2 T3 
511        1/1                transition_token_q        <= transition_token_d;
           Tests:       T1 T2 T3 
512        1/1                transition_target_q       <= transition_target_d;
           Tests:       T1 T2 T3 
513        1/1                otp_vendor_test_ctrl_q    <= otp_vendor_test_ctrl_d;
           Tests:       T1 T2 T3 
514        1/1                use_ext_clock_q           <= use_ext_clock_d;
           Tests:       T1 T2 T3 
515                         end
516                       end
517                     
518                       // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
519                       // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
520                       // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
521                       // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
522                       // ---------------------------------------------------------------
523                       // If not enabled, this register will become a constant.
524                       if (SecVolatileRawUnlockEn) begin : gen_volatile_raw_unlock_reg
525                         always_ff @(posedge clk_i or negedge rst_ni) begin : p_volatile_raw_unlock_reg
526        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
527        1/1                  volatile_raw_unlock_q     <= 1'b0;
           Tests:       T1 T2 T3 
528                           end else begin
529        1/1                  volatile_raw_unlock_q     <= volatile_raw_unlock_d;
           Tests:       T1 T2 T3 
530                           end
531                         end
532                       end else begin : gen_volatile_raw_unlock_const
533                         logic unused_volatile_raw_unlock;
534                         assign unused_volatile_raw_unlock = ^volatile_raw_unlock_d;
535                         assign volatile_raw_unlock_q = 1'b0;
536                       end
537                       // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
538                     
539        1/1            assign lc_flash_rma_seed_o = transition_token_q[RmaSeedWidth-1:0];
           Tests:       T1 T2 T3 
540                     
541                       // Gate the vendor specific test ctrl/status bits to zero in production states.
542                       // Buffer the enable signal to prevent optimization of the multibit signal.
543                       lc_tx_t lc_raw_test_rma;
544                       lc_tx_t [1:0] lc_raw_test_rma_buf;
545                       prim_lc_sync #(
546                         .NumCopies(2),
547                         .AsyncOn(0)
548                       ) u_prim_lc_sync (
549                         .clk_i,
550                         .rst_ni,
551                         .lc_en_i(lc_raw_test_rma),
552                         .lc_en_o(lc_raw_test_rma_buf)
553                       );
554                     
555        1/1            assign lc_otp_vendor_test_o.ctrl = (lc_tx_test_true_strict(lc_raw_test_rma_buf[0])) ?
           Tests:       T1 T2 T3 
556                                                          otp_vendor_test_ctrl_q                           : '0;
557        1/1            assign otp_vendor_test_status    = (lc_tx_test_true_strict(lc_raw_test_rma_buf[1])) ?
           Tests:       T1 T2 T3 
558                                                          lc_otp_vendor_test_i.status                      : '0;
559                     
560                       //////////////////
561                       // Alert Sender //
562                       //////////////////
563                     
564                       logic [NumAlerts-1:0] alerts;
565                       logic [NumAlerts-1:0] alert_test;
566                       logic [NumAlerts-1:0] tap_alert_test;
567                     
568        1/1            assign alerts = {
           Tests:       T1 T2 T3 
569                         fatal_bus_integ_error_q,
570                         fatal_state_error_q,
571                         fatal_prog_error_q
572                       };
573                     
574        1/1            assign alert_test = {
           Tests:       T1 T2 T3 
575                         reg2hw.alert_test.fatal_bus_integ_error.q &
576                         reg2hw.alert_test.fatal_bus_integ_error.qe,
577                         reg2hw.alert_test.fatal_state_error.q &
578                         reg2hw.alert_test.fatal_state_error.qe,
579                         reg2hw.alert_test.fatal_prog_error.q &
580                         reg2hw.alert_test.fatal_prog_error.qe
581                       };
582                     
583        1/1             assign tap_alert_test = {
           Tests:       T1 T2 T3 
584                         tap_reg2hw.alert_test.fatal_bus_integ_error.q &
585                         tap_reg2hw.alert_test.fatal_bus_integ_error.qe,
586                         tap_reg2hw.alert_test.fatal_state_error.q &
587                         tap_reg2hw.alert_test.fatal_state_error.qe,
588                         tap_reg2hw.alert_test.fatal_prog_error.q &
589                         tap_reg2hw.alert_test.fatal_prog_error.qe
590                       };
591                     
592                       for (genvar k = 0; k < NumAlerts; k++) begin : gen_alert_tx
593                         prim_alert_sender #(
594                           .AsyncOn(AlertAsyncOn[k]),
595                           .IsFatal(1)
596                         ) u_prim_alert_sender (
597                           .clk_i,
598                           .rst_ni,
599                           .alert_test_i  ( alert_test[k] |
600                                            tap_alert_test[k] ),
601                           .alert_req_i   ( alerts[k]         ),
602                           .alert_ack_o   (                   ),
603                           .alert_state_o (                   ),
604                           .alert_rx_i    ( alert_rx_i[k]     ),
605                           .alert_tx_o    ( alert_tx_o[k]     )
606                         );
607                       end
608                     
609                       //////////////////////////
610                       // Escalation Receivers //
611                       //////////////////////////
612                     
613                       // SEC_CM: MAIN.FSM.GLOBAL_ESC
614                       // We still have two escalation receivers here for historical reasons.
615                       // The two actions "wipe secrets" and "scrap lifecycle state" have been
616                       // combined in order to simplify both DV and the design, as otherwise
617                       // this separation of very intertwined actions would have caused too many
618                       // unnecessary corner cases. The escalation receivers are now redundant and
619                       // trigger both actions at once.
620                     
621                       // This escalation action moves the life cycle
622                       // state into a temporary "SCRAP" state named "ESCALATE",
623                       // and asserts the lc_escalate_en life cycle control signal.
624                       logic esc_scrap_state0;
625                       prim_esc_receiver #(
626                         .N_ESC_SEV   (alert_handler_reg_pkg::N_ESC_SEV),
627                         .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW)
628                       ) u_prim_esc_receiver0 (
629                         .clk_i,
630                         .rst_ni,
631                         .esc_req_o (esc_scrap_state0),
632                         .esc_rx_o  (esc_scrap_state0_rx_o),
633                         .esc_tx_i  (esc_scrap_state0_tx_i)
634                       );
635                     
636                       // This escalation action moves the life cycle
637                       // state into a temporary "SCRAP" state named "ESCALATE".
638                       logic esc_scrap_state1;
639                       prim_esc_receiver #(
640                         .N_ESC_SEV   (alert_handler_reg_pkg::N_ESC_SEV),
641                         .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW)
642                       ) u_prim_esc_receiver1 (
643                         .clk_i,
644                         .rst_ni,
645                         .esc_req_o (esc_scrap_state1),
646                         .esc_rx_o  (esc_scrap_state1_rx_o),
647                         .esc_tx_i  (esc_scrap_state1_tx_i)
648                       );
649                     
650                       ////////////////////////////
651                       // Synchronization of IOs //
652                       ////////////////////////////
653                     
654                       // Signals going to and coming from power manager.
655                       logic lc_init;
656                       prim_flop_2sync #(
657                         .Width(1)
658                       ) u_prim_flop_2sync_init (
659                         .clk_i,
660                         .rst_ni,
661                         .d_i(pwr_lc_i.lc_init),
662                         .q_o(lc_init)
663                       );
664                     
665                       logic lc_done_q;
666                       logic lc_idle_q;
667                     
668                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_sync_regs
669        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
670        1/1                lc_done_q <= 1'b0;
           Tests:       T1 T2 T3 
671        1/1                lc_idle_q <= 1'b0;
           Tests:       T1 T2 T3 
672                         end else begin
673        1/1                lc_done_q <= lc_done_d;
           Tests:       T1 T2 T3 
674        1/1                lc_idle_q <= lc_idle_d;
           Tests:       T1 T2 T3 
675                         end
676                       end
677                     
678        1/1            assign pwr_lc_o.lc_done = lc_done_q;
           Tests:       T1 T2 T3 
679        1/1            assign pwr_lc_o.lc_idle = lc_idle_q;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : lc_ctrl

	Total	Covered	Percent
Conditions	72	59	81.94
Logical	72	59	81.94
Non-Logical	0	0
Event	0	0

 LINE       213
 EXPRESSION (dmi_req_ready & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T7

 LINE       241
 EXPRESSION (dmi_req_valid & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T4,T6,T7

 LINE       241
 EXPRESSION (dmi_req.op == DTM_WRITE)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       395
 EXPRESSION (tap_reg2hw.transition_cmd.q & tap_reg2hw.transition_cmd.qe)
             -------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T11,T14

 LINE       429
 EXPRESSION (reg2hw.transition_cmd.q & reg2hw.transition_cmd.qe)
             -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       492
 EXPRESSION (SecVolatileRawUnlockEn && transition_cmd && ((!volatile_raw_unlock_q)))
             -----------1----------    -------2------    -------------3------------

-1-	-2-	-3-	Status	Tests
-	0	1	Covered	T1,T2,T3
-	1	0	Covered	T1,T12,T30
-	1	1	Covered	T1,T2,T4

 LINE       495
 EXPRESSION (trans_success_d | trans_success_q)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T12

 LINE       498
 EXPRESSION (trans_cnt_oflw_error_d | trans_cnt_oflw_error_q)
             -----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T43,T44
1	0	Covered	T21,T43,T44

 LINE       499
 EXPRESSION (trans_invalid_error_d | trans_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T7,T39
1	0	Covered	T12,T6,T7

 LINE       500
 EXPRESSION (token_invalid_error_d | token_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T39,T40
1	0	Covered	T33,T39,T40

 LINE       501
 EXPRESSION (flash_rma_error_d | flash_rma_error_q)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T47,T21
1	0	Covered	T33,T47,T21

 LINE       502
 EXPRESSION (otp_prog_error_d | fatal_prog_error_q)
             --------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T14
1	0	Covered	T4,T5,T14

 LINE       503
 EXPRESSION (state_invalid_error_d | fatal_state_error_q)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T16,T36
1	0	Covered	T11,T16,T36

 LINE       504
 EXPRESSION (otp_lc_data_i.error | otp_part_error_q)
             ---------1---------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T51,T52
1	0	Covered	T21,T43,T44

 LINE       505
 EXPRESSION (fatal_bus_integ_error_csr_d | fatal_bus_integ_error_tap_d | fatal_bus_integ_error_q)
             -------------1-------------   -------------2-------------   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T91,T87,T73
1	0	0	Covered	T91,T87,T73

 LINE       574
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T93,T94
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T93,T94

 LINE       574
 SUB-EXPRESSION (reg2hw.alert_test.fatal_state_error.q & reg2hw.alert_test.fatal_state_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T93,T94
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T93,T94

 LINE       574
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prog_error.q & reg2hw.alert_test.fatal_prog_error.qe)
                 ------------------1-----------------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T93,T94
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T93,T94

 LINE       583
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_bus_integ_error.q & tap_reg2hw.alert_test.fatal_bus_integ_error.qe)
                 ----------------------1----------------------   -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Not Covered

 LINE       583
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_state_error.q & tap_reg2hw.alert_test.fatal_state_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Not Covered

 LINE       583
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_prog_error.q & tap_reg2hw.alert_test.fatal_prog_error.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Not Covered

 LINE       596
 EXPRESSION (alert_test[0] | tap_alert_test[0])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T13,T93,T94

 LINE       596
 EXPRESSION (alert_test[1] | tap_alert_test[1])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T13,T93,T94

 LINE       596
 EXPRESSION (alert_test[2] | tap_alert_test[2])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T13,T93,T94

---

Toggle Coverage for Module : lc_ctrl

	Total	Covered	Percent
Totals	105	99	94.29
Total Bits	7426	7289	98.16
Total Bits 0->1	3713	3645	98.17
Total Bits 1->0	3713	3644	98.14

Ports	105	99	94.29
Port Bits	7426	7289	98.16
Port Bits 0->1	3713	3645	98.17
Port Bits 1->0	3713	3644	98.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
clk_kmac_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_kmac_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T12,T13	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T22	Yes	T1,T3,T22	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T6	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T12	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T12	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
jtag_i.tdi	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	INPUT
jtag_i.trst_n	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
jtag_i.tms	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	INPUT
jtag_i.tck	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	INPUT
jtag_o.tdo_oe	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT
jtag_o.tdo	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT
scan_rst_ni	Yes	Yes	T6,T7,T8	Yes	T7,T9,T10	INPUT
scanmode_i[3:0]	No	No		No		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T13,T4,T5	Yes	T13,T4,T5	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T13,T11,T16	Yes	T13,T11,T16	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T13,T93,T94	Yes	T13,T93,T94	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T13,T4,T5	Yes	T13,T4,T5	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T13,T11,T16	Yes	T13,T11,T16	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T13,T93,T94	Yes	T13,T93,T94	OUTPUT
esc_scrap_state0_tx_i.resp_n	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
esc_scrap_state0_tx_i.resp_p	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
esc_scrap_state0_rx_o.esc_n	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
esc_scrap_state0_rx_o.esc_p	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
esc_scrap_state1_tx_i.resp_n	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
esc_scrap_state1_tx_i.resp_p	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
esc_scrap_state1_rx_o.esc_n	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
esc_scrap_state1_rx_o.esc_p	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
pwr_lc_i.lc_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_lc_o.lc_idle	Yes	Yes	T1,T2,T12	Yes	T1,T2,T3	OUTPUT
pwr_lc_o.lc_done	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
strap_en_override_o	No	No		Yes	T1,T12,T30	OUTPUT
lc_otp_vendor_test_o.ctrl[31:0]	Yes	Yes	T5,T7,T11	Yes	T6,T5,T7	OUTPUT
lc_otp_vendor_test_i.status[31:0]	Yes	Yes	T15,T16,T42	Yes	T3,T12,T22	INPUT
lc_otp_program_o.count[383:0]	Yes	Yes	T16,T36,T33	Yes	T16,T36,T33	OUTPUT
lc_otp_program_o.state[319:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	OUTPUT
lc_otp_program_o.req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
lc_otp_program_i.ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
lc_otp_program_i.err	Yes	Yes	T96,T97,T98	Yes	T50,T96,T56	INPUT
kmac_data_i.error	Yes	Yes	T21,T43,T44	Yes	T21,T43,T44	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T2,T16,T17	Yes	T2,T16,T17	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T2,T16,T17	Yes	T2,T16,T17	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	INPUT
kmac_data_i.ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T2,T11,T16	Yes	T2,T11,T16	OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	OUTPUT
otp_lc_data_i.rma_token[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
otp_lc_data_i.rma_token_valid[3:0]	Yes	Yes	T47,T53,T99	Yes	T47,T53,T99	INPUT
otp_lc_data_i.test_exit_token[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
otp_lc_data_i.test_unlock_token[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
otp_lc_data_i.test_tokens_valid[3:0]	Yes	Yes	T33,T47,T53	Yes	T33,T47,T53	INPUT
otp_lc_data_i.secrets_valid[3:0]	Yes	Yes	T33,T47,T53	Yes	T33,T47,T53	INPUT
otp_lc_data_i.count[383:0]	Yes	Yes	T16,T36,T33	Yes	T16,T36,T33	INPUT
otp_lc_data_i.state[319:0]	Yes	Yes	T2,T4,T15	Yes	T2,T4,T11	INPUT
otp_lc_data_i.error	Yes	Yes	T21,T43,T44	Yes	T21,T43,T44	INPUT
otp_lc_data_i.valid	Yes	Yes	T11,T16,T60	Yes	T11,T16,T36	INPUT
lc_dft_en_o[3:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T3	OUTPUT
lc_nvm_debug_en_o[3:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T3	OUTPUT
lc_hw_debug_en_o[3:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T3	OUTPUT
lc_cpu_en_o[3:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T3	OUTPUT
lc_creator_seed_sw_rw_en_o[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
lc_owner_seed_sw_rw_en_o[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
lc_iso_part_sw_rd_en_o[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
lc_iso_part_sw_wr_en_o[3:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T3	OUTPUT
lc_seed_hw_rd_en_o[3:0]	Yes	Yes	T11,T18,T19	Yes	T11,T18,T19	OUTPUT
lc_keymgr_en_o[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
lc_escalate_en_o[3:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
lc_check_byp_en_o[3:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T4	OUTPUT
lc_clk_byp_req_o[3:0]	Yes	Yes	T2,T17,T19	Yes	T2,T7,T17	OUTPUT
lc_clk_byp_ack_i[3:0]	Yes	Yes	T2,T17,T19	Yes	T2,T17,T30	INPUT
lc_flash_rma_seed_o[31:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	OUTPUT
lc_flash_rma_req_o[3:0]	Yes	Yes	T2,T16,T18	Yes	T2,T16,T18	OUTPUT
lc_keymgr_div_o[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
otp_device_id_i[255:0]	Yes	Yes	T2,T4,T11	Yes	T1,T2,T4	INPUT
otp_manuf_state_i[255:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
hw_rev_o.reserved[23:0]	No	No		No		OUTPUT
hw_rev_o.revision_id[7:0]	No	No		No		OUTPUT
hw_rev_o.product_id[15:0]	No	No		No		OUTPUT
hw_rev_o.silicon_creator_id[15:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : lc_ctrl

	Line No.	Total	Covered	Percent
Branches		31	31	100.00
IF	347	3	3	100.00
IF	381	3	3	100.00
IF	392	18	18	100.00
IF	467	3	3	100.00
IF	669	2	2	100.00
IF	526	2	2	100.00

347            if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
               -1-                                                
348              tap_hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
                 ==>
349              tap_hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
350              tap_hw2reg.transition_token  = transition_token_q;
351              tap_hw2reg.transition_target = transition_target_q;
352              // SEC_CM: TRANSITION.CONFIG.REGWEN
353              tap_hw2reg.transition_regwen = lc_idle_d;
354              tap_hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
355              tap_hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
356            end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
                        -2-                                               
357              hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
                 ==>
358              hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
359              hw2reg.transition_token  = transition_token_q;
360              hw2reg.transition_target = transition_target_q;
361              // SEC_CM: TRANSITION.CONFIG.REGWEN
362              hw2reg.transition_regwen = lc_idle_d;
363              hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
364              hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
365            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T7
0	1	Covered	T1,T2,T12
0	0	Covered	T1,T2,T3

381            if (mubi8_test_false_loose(sw_claim_transition_if_q) &&
               -1-                                               
382                tap_reg2hw.claim_transition_if.qe) begin
383              tap_claim_transition_if_d = mubi8_t'(tap_reg2hw.claim_transition_if.q);
                 ==>
384            // SW mutex claim.
385            end else if (mubi8_test_false_loose(tap_claim_transition_if_q) &&
                        -2-                                                
386                reg2hw.claim_transition_if.qe) begin
387              sw_claim_transition_if_d = mubi8_t'(reg2hw.claim_transition_if.q);
                 ==>
388            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

392            if (lc_idle_d) begin
               -1-  
393              // The TAP has priority.
394              if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
                 -2-                                                
395                transition_cmd = tap_reg2hw.transition_cmd.q &
396                                 tap_reg2hw.transition_cmd.qe;
397        
398                if (tap_reg2hw.transition_ctrl.ext_clock_en.qe) begin
                   -3-  
399                  use_ext_clock_d |= tap_reg2hw.transition_ctrl.ext_clock_en.q;
                     ==>
400                end
                   MISSING_ELSE
                   ==>
401        
402                // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
403                // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
404                // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
405                // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
406                // ---------------------------------------------------------------
407                if (tap_reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
                   -4-  
408                  volatile_raw_unlock_d = tap_reg2hw.transition_ctrl.volatile_raw_unlock.q;
                     ==>
409                end
                   MISSING_ELSE
                   ==>
410                // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
411        
412                for (int k = 0; k < LcTokenWidth/32; k++) begin
413                  if (tap_reg2hw.transition_token[k].qe) begin
414                    transition_token_d[k*32 +: 32] = tap_reg2hw.transition_token[k].q;
415                  end
416                end
417        
418                if (tap_reg2hw.transition_target.qe) begin
                   -5-  
419                  for (int k = 0; k < DecLcStateNumRep; k++) begin
                     ==>
420                    transition_target_d[k] = dec_lc_state_e'(
421                        tap_reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
422                  end
423                end
                   MISSING_ELSE
                   ==>
424        
425                if (tap_reg2hw.otp_vendor_test_ctrl.qe) begin
                   -6-  
426                  otp_vendor_test_ctrl_d = tap_reg2hw.otp_vendor_test_ctrl.q;
                     ==>
427                end
                   MISSING_ELSE
                   ==>
428              end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
                          -7-                                               
429                transition_cmd = reg2hw.transition_cmd.q &
430                                 reg2hw.transition_cmd.qe;
431        
432                if (reg2hw.transition_ctrl.ext_clock_en.qe) begin
                   -8-  
433                  use_ext_clock_d |= reg2hw.transition_ctrl.ext_clock_en.q;
                     ==>
434                end
                   MISSING_ELSE
                   ==>
435        
436                // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
437                // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
438                // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
439                // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
440                // ---------------------------------------------------------------
441                if (reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
                   -9-  
442                  volatile_raw_unlock_d = reg2hw.transition_ctrl.volatile_raw_unlock.q;
                     ==>
443                end
                   MISSING_ELSE
                   ==>
444                // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
445        
446                for (int k = 0; k < LcTokenWidth/32; k++) begin
447                  if (reg2hw.transition_token[k].qe) begin
448                    transition_token_d[k*32 +: 32] = reg2hw.transition_token[k].q;
449                  end
450                end
451        
452                if (reg2hw.transition_target.qe) begin
                   -10-  
453                  for (int k = 0; k < DecLcStateNumRep; k++) begin
                     ==>
454                    transition_target_d[k] = dec_lc_state_e'(
455                        reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
456                  end
457                end
                   MISSING_ELSE
                   ==>
458        
459                if (reg2hw.otp_vendor_test_ctrl.qe) begin
                   -11-  
460                  otp_vendor_test_ctrl_d = reg2hw.otp_vendor_test_ctrl.q;
                     ==>
461                end
                   MISSING_ELSE
                   ==>
462              end
                 MISSING_ELSE
                 ==>
463            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
1	1	1	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
1	1	0	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
1	1	-	1	-	-	-	-	-	-	-	Covered	T6,T7,T8
1	1	-	0	-	-	-	-	-	-	-	Covered	T4,T6,T7
1	1	-	-	1	-	-	-	-	-	-	Covered	T4,T6,T7
1	1	-	-	0	-	-	-	-	-	-	Covered	T4,T6,T7
1	1	-	-	-	1	-	-	-	-	-	Covered	T4,T6,T7
1	1	-	-	-	0	-	-	-	-	-	Covered	T4,T6,T7
1	0	-	-	-	-	1	1	-	-	-	Covered	T1,T2,T12
1	0	-	-	-	-	1	0	-	-	-	Covered	T1,T2,T12
1	0	-	-	-	-	1	-	1	-	-	Covered	T1,T2,T12
1	0	-	-	-	-	1	-	0	-	-	Covered	T1,T2,T12
1	0	-	-	-	-	1	-	-	1	-	Covered	T1,T2,T12
1	0	-	-	-	-	1	-	-	0	-	Covered	T1,T2,T12
1	0	-	-	-	-	1	-	-	-	1	Covered	T2,T5,T7
1	0	-	-	-	-	1	-	-	-	0	Covered	T1,T2,T12
1	0	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

467            if (!rst_ni) begin
               -1-  
468              trans_success_q           <= 1'b0;
                 ==>
469              trans_cnt_oflw_error_q    <= 1'b0;
470              trans_invalid_error_q     <= 1'b0;
471              token_invalid_error_q     <= 1'b0;
472              flash_rma_error_q         <= 1'b0;
473              fatal_prog_error_q        <= 1'b0;
474              fatal_state_error_q       <= 1'b0;
475              sw_claim_transition_if_q  <= MuBi8False;
476              tap_claim_transition_if_q <= MuBi8False;
477              transition_token_q        <= '0;
478              transition_target_q       <= {DecLcStateNumRep{DecLcStRaw}};
479              otp_part_error_q          <= 1'b0;
480              fatal_bus_integ_error_q   <= 1'b0;
481              otp_vendor_test_ctrl_q    <= '0;
482              use_ext_clock_q           <= 1'b0;
483            end else begin
484              // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
485              // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
486              // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
487              // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
488              // ---------------------------------------------------------------
489              // In case of a volatile RAW unlock, this bit has to be cleared when the volatile
490              // unlock is followed by a real transition.
491              // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
492              if (SecVolatileRawUnlockEn && transition_cmd && !volatile_raw_unlock_q) begin
                 -2-  
493                trans_success_q <= 1'b0;
                   ==>
494              end else begin
495                trans_success_q <= trans_success_d | trans_success_q;
                   ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

669            if (!rst_ni) begin
               -1-  
670              lc_done_q <= 1'b0;
                 ==>
671              lc_idle_q <= 1'b0;
672            end else begin
673              lc_done_q <= lc_done_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

526              if (!rst_ni) begin
                 -1-  
527                volatile_raw_unlock_q     <= 1'b0;
                   ==>
528              end else begin
529                volatile_raw_unlock_q     <= volatile_raw_unlock_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : lc_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	28	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	28	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	58101981	54873882	0	0
DecLcCountWidthCheck_A	812	812	0	0
DecLcIdStateWidthCheck_A	812	812	0	0
DecLcStateWidthCheck_A	812	812	0	0
FpvSecCmCtrlKmacIfFsmCheck_A	56483286	0	0	0
FpvSecCmCtrlLcCntCheck_A	53137619	0	0	0
FpvSecCmCtrlLcFsmCheck_A	56479171	0	0	0
FpvSecCmCtrlLcStateCheck_A	54746572	1	0	0
FpvSecCmRegWeOnehotCheck_A	58101981	70	0	0
FpvSecCmTapRegWeOnehotCheck_A	58101981	0	0	0
LcCheckBypassEnKnown_A	58101981	54873882	0	0
LcClkBypReqKnown_A	58101981	54873882	0	0
LcCpuEnKnown_A	58101981	54873882	0	0
LcCreatorSwRwEn_A	58101981	54873882	0	0
LcDftEnKnown_A	58101981	54873882	0	0
LcEscalateEnKnown_A	58101981	54873882	0	0
LcFlashRmaReqKnown_A	58101981	54873882	0	0
LcFlashRmaSeedKnown_A	58101981	54873882	0	0
LcHwDebugEnKnown_A	58101981	54873882	0	0
LcIsoSwRwEn_A	58101981	54873882	0	0
LcIsoSwWrEn_A	58101981	54873882	0	0
LcKeymgrDiv_A	58101981	54873882	0	0
LcKeymgrEnKnown_A	58101981	54873882	0	0
LcNvmDebugEnKnown_A	58101981	54873882	0	0
LcOtpProgramKnown_A	58101981	54873882	0	0
LcOtpTokenKnown_A	58101981	54873882	0	0
LcOwnerSwRwEn_A	58101981	54873882	0	0
LcSeedHwRdEn_A	58101981	54873882	0	0
NumTokenWordsCheck_A	812	812	0	0
OtpTestCtrlWidth_A	812	812	0	0
PwrLcKnown_A	58101981	54873882	0	0
TlOKnown	58101981	54873882	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

DecLcCountWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

DecLcIdStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

DecLcStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FpvSecCmCtrlKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56483286	0	0	0

FpvSecCmCtrlLcCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53137619	0	0	0

FpvSecCmCtrlLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56479171	0	0	0

FpvSecCmCtrlLcStateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54746572	1	0	0
T100	177640	1	0	0
T101	1388	0	0	0
T102	48335	0	0	0
T103	24162	0	0	0
T104	6615	0	0	0
T105	2831	0	0	0
T106	24727	0	0	0
T107	51535	0	0	0
T108	8795	0	0	0
T109	25258	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	70	0	0
T10	4948	0	0	0
T48	24433	0	0	0
T67	0	20	0	0
T73	0	10	0	0
T87	0	20	0	0
T91	12013	10	0	0
T92	56103	0	0	0
T110	0	10	0	0
T111	796	0	0	0
T112	7438	0	0	0
T113	4082	0	0	0
T114	121874	0	0	0
T115	20338	0	0	0
T116	91422	0	0	0

FpvSecCmTapRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	0	0	0

LcCheckBypassEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcClkBypReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcCpuEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcCreatorSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcDftEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcEscalateEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcFlashRmaReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcFlashRmaSeedKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcHwDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcIsoSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcIsoSwWrEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcKeymgrDiv_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcKeymgrEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcNvmDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcOtpProgramKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcOtpTokenKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcOwnerSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcSeedHwRdEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

NumTokenWordsCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpTestCtrlWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

PwrLcKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

TlOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
ALWAYS	318	41	41	100.00
ALWAYS	369	41	41	100.00
ALWAYS	467	33	33	100.00
ALWAYS	526	3	3	100.00
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	583	1	1	100.00
ALWAYS	669	5	5	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	679	1	1	100.00

212                       logic req_ready;
213        1/1            assign req_ready = dmi_req_ready & dmi_resp_ready;
           Tests:       T1 T2 T3 
214                       dmi_jtag #(
215                         .IdcodeValue(IdcodeValue),
216                         .NumDmiWordAbits(7)
217                       ) u_dmi_jtag (
218                         .clk_i,
219                         .rst_ni,
220                         .testmode_i       ( scanmode          ),
221                         .test_rst_ni      ( scan_rst_ni       ),
222                         .dmi_rst_no       (                   ), // unused
223                         .dmi_req_o        ( dmi_req           ),
224                         .dmi_req_valid_o  ( dmi_req_valid     ),
225                         // unless there is room for response, stall
226                         .dmi_req_ready_i  ( req_ready         ),
227                         .dmi_resp_i       ( dmi_resp          ),
228                         .dmi_resp_ready_o ( dmi_resp_ready    ),
229                         .dmi_resp_valid_i ( dmi_resp_valid    ),
230                         .tck_i            ( tck_muxed         ),
231                         .tms_i            ( jtag_i.tms        ),
232                         .trst_ni          ( trst_n_muxed      ),
233                         .td_i             ( jtag_i.tdi        ),
234                         .td_o             ( jtag_o.tdo        ),
235                         .tdo_oe_o         ( jtag_o.tdo_oe     )
236                       );
237                     
238                       // DMI to TL-UL transducing
239                       tlul_adapter_host #(
240                         .EnableDataIntgGen(1)
241                       ) u_tap_tlul_host (
242                         .clk_i,
243                         .rst_ni,
244                         // do not make a request unless there is room for the response
245                         .req_i        ( dmi_req_valid & dmi_resp_ready         ),
246                         .gnt_o        ( dmi_req_ready                          ),
247                         .addr_i       ( top_pkg::TL_AW'({dmi_req.addr, 2'b00}) ),
248                         .we_i         ( dmi_req.op == dm::DTM_WRITE            ),
249                         .wdata_i      ( dmi_req.data                           ),
250                         .wdata_intg_i ('0                                      ),
251                         .be_i         ( {top_pkg::TL_DBW{1'b1}}                ),
252                         .user_rsvd_i  ('0                                      ),
253                         .instr_type_i ( prim_mubi_pkg::MuBi4False              ),
254                         .valid_o      ( dmi_resp_valid                         ),
255                         .rdata_o      ( dmi_resp.data                          ),
256                         .rdata_intg_o (                                        ),
257                         .err_o        (                                        ),
258                         .intg_err_o   (                                        ),
259                         .tl_o         ( tap_tl_h2d                             ),
260                         .tl_i         ( tap_tl_d2h                             )
261                       );
262                     
263                       // TL-UL to DMI transducing
264                       assign dmi_resp.resp = '0; // unused inside dmi_jtag
265                     
266                       // These signals are unused
267                       logic unused_tap_tl_d2h;
268        1/1            assign unused_tap_tl_d2h = ^{
           Tests:       T1 T2 T3 
269                         dmi_req.addr[31:30],
270                         tap_tl_d2h.d_opcode,
271                         tap_tl_d2h.d_param,
272                         tap_tl_d2h.d_size,
273                         tap_tl_d2h.d_source,
274                         tap_tl_d2h.d_sink,
275                         tap_tl_d2h.d_user,
276                         tap_tl_d2h.d_error
277                       };
278                     
279                       ///////////////////////////////////////
280                       // Transition Interface and HW Mutex //
281                       ///////////////////////////////////////
282                     
283                       // All registers are HWext
284                       logic          trans_success_d, trans_success_q;
285                       logic          trans_cnt_oflw_error_d, trans_cnt_oflw_error_q;
286                       logic          trans_invalid_error_d, trans_invalid_error_q;
287                       logic          token_invalid_error_d, token_invalid_error_q;
288                       logic          flash_rma_error_d, flash_rma_error_q;
289                       logic          otp_prog_error_d, fatal_prog_error_q;
290                       logic          state_invalid_error_d, fatal_state_error_q;
291                       logic          otp_part_error_q;
292                       mubi8_t        sw_claim_transition_if_d, sw_claim_transition_if_q;
293                       mubi8_t        tap_claim_transition_if_d, tap_claim_transition_if_q;
294                       logic          transition_cmd;
295                       lc_token_t     transition_token_d, transition_token_q;
296                       ext_dec_lc_state_t transition_target_d, transition_target_q;
297                       // No need to register these.
298                       ext_dec_lc_state_t dec_lc_state;
299                       dec_lc_cnt_t       dec_lc_cnt;
300                       dec_lc_id_state_e  dec_lc_id_state;
301                     
302                       logic lc_idle_d, lc_done_d;
303                     
304                       // Assign hardware revision output
305                       assign hw_rev_o = '{silicon_creator_id: SiliconCreatorId,
306                                           product_id:         ProductId,
307                                           revision_id:        RevisionId,
308                                           reserved:           '0};
309                     
310                       // OTP Vendor control bits
311                       logic ext_clock_switched;
312                       logic use_ext_clock_d, use_ext_clock_q;
313                       logic volatile_raw_unlock_d, volatile_raw_unlock_q;
314                       logic [CsrOtpTestCtrlWidth-1:0] otp_vendor_test_ctrl_d, otp_vendor_test_ctrl_q;
315                       logic [CsrOtpTestStatusWidth-1:0] otp_vendor_test_status;
316                     
317                       always_comb begin : p_csr_assign_outputs
318        1/1              hw2reg = '0;
           Tests:       T1 T2 T3 
319        1/1              hw2reg.status.initialized            = lc_done_d;
           Tests:       T1 T2 T3 
320        1/1              hw2reg.status.ready                  = lc_idle_d;
           Tests:       T1 T2 T3 
321        1/1              hw2reg.status.ext_clock_switched     = ext_clock_switched;
           Tests:       T1 T2 T3 
322        1/1              hw2reg.status.transition_successful  = trans_success_q;
           Tests:       T1 T2 T3 
323        1/1              hw2reg.status.transition_count_error = trans_cnt_oflw_error_q;
           Tests:       T1 T2 T3 
324        1/1              hw2reg.status.transition_error       = trans_invalid_error_q;
           Tests:       T1 T2 T3 
325        1/1              hw2reg.status.token_error            = token_invalid_error_q;
           Tests:       T1 T2 T3 
326        1/1              hw2reg.status.flash_rma_error        = flash_rma_error_q;
           Tests:       T1 T2 T3 
327        1/1              hw2reg.status.otp_error              = fatal_prog_error_q;
           Tests:       T1 T2 T3 
328        1/1              hw2reg.status.state_error            = fatal_state_error_q;
           Tests:       T1 T2 T3 
329        1/1              hw2reg.status.otp_partition_error    = otp_part_error_q;
           Tests:       T1 T2 T3 
330        1/1              hw2reg.status.bus_integ_error        = fatal_bus_integ_error_q;
           Tests:       T1 T2 T3 
331        1/1              hw2reg.lc_state                      = dec_lc_state;
           Tests:       T1 T2 T3 
332        1/1              hw2reg.lc_transition_cnt             = dec_lc_cnt;
           Tests:       T1 T2 T3 
333        1/1              hw2reg.lc_id_state                   = {DecLcIdStateNumRep{dec_lc_id_state}};
           Tests:       T1 T2 T3 
334        1/1              hw2reg.device_id                     = otp_device_id_i;
           Tests:       T1 T2 T3 
335        1/1              hw2reg.manuf_state                   = otp_manuf_state_i;
           Tests:       T1 T2 T3 
336        1/1              hw2reg.hw_revision0.silicon_creator_id = hw_rev_o.silicon_creator_id;
           Tests:       T1 T2 T3 
337        1/1              hw2reg.hw_revision0.product_id         = hw_rev_o.product_id;
           Tests:       T1 T2 T3 
338        1/1              hw2reg.hw_revision1.revision_id        = hw_rev_o.revision_id;
           Tests:       T1 T2 T3 
339        1/1              hw2reg.hw_revision1.reserved           = '0;
           Tests:       T1 T2 T3 
340                     
341                         // The assignments above are identical for the TAP.
342        1/1              tap_hw2reg = hw2reg;
           Tests:       T1 T2 T3 
343                     
344                         // Assignments gated by mutex. Again, the TAP has priority.
345        1/1              tap_hw2reg.claim_transition_if = tap_claim_transition_if_q;
           Tests:       T1 T2 T3 
346        1/1              hw2reg.claim_transition_if = sw_claim_transition_if_q;
           Tests:       T1 T2 T3 
347        1/1              if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
348        1/1                tap_hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
           Tests:       T4 T6 T7 
349        1/1                tap_hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
           Tests:       T4 T6 T7 
350        1/1                tap_hw2reg.transition_token  = transition_token_q;
           Tests:       T4 T6 T7 
351        1/1                tap_hw2reg.transition_target = transition_target_q;
           Tests:       T4 T6 T7 
352                           // SEC_CM: TRANSITION.CONFIG.REGWEN
353        1/1                tap_hw2reg.transition_regwen = lc_idle_d;
           Tests:       T4 T6 T7 
354        1/1                tap_hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
           Tests:       T4 T6 T7 
355        1/1                tap_hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
           Tests:       T4 T6 T7 
356        1/1              end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
357        1/1                hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
           Tests:       T1 T2 T12 
358        1/1                hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
           Tests:       T1 T2 T12 
359        1/1                hw2reg.transition_token  = transition_token_q;
           Tests:       T1 T2 T12 
360        1/1                hw2reg.transition_target = transition_target_q;
           Tests:       T1 T2 T12 
361                           // SEC_CM: TRANSITION.CONFIG.REGWEN
362        1/1                hw2reg.transition_regwen = lc_idle_d;
           Tests:       T1 T2 T12 
363        1/1                hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
           Tests:       T1 T2 T12 
364        1/1                hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
           Tests:       T1 T2 T12 
365                         end
                        MISSING_ELSE
366                       end
367                     
368                       always_comb begin : p_csr_assign_inputs
369        1/1              sw_claim_transition_if_d  = sw_claim_transition_if_q;
           Tests:       T1 T2 T3 
370        1/1              tap_claim_transition_if_d = tap_claim_transition_if_q;
           Tests:       T1 T2 T3 
371        1/1              transition_token_d        = transition_token_q;
           Tests:       T1 T2 T3 
372        1/1              transition_target_d       = transition_target_q;
           Tests:       T1 T2 T3 
373        1/1              transition_cmd            = 1'b0;
           Tests:       T1 T2 T3 
374        1/1              otp_vendor_test_ctrl_d    = otp_vendor_test_ctrl_q;
           Tests:       T1 T2 T3 
375        1/1              use_ext_clock_d           = use_ext_clock_q;
           Tests:       T1 T2 T3 
376        1/1              volatile_raw_unlock_d     = volatile_raw_unlock_q;
           Tests:       T1 T2 T3 
377                     
378                         // Note that the mutex claims from the TAP and SW side could arrive within the same cycle.
379                         // In that case we give priority to the TAP mutex claim in order to avoid a race condition.
380                         // TAP mutex claim.
381        1/1              if (mubi8_test_false_loose(sw_claim_transition_if_q) &&
           Tests:       T1 T2 T3 
382                             tap_reg2hw.claim_transition_if.qe) begin
383        1/1                tap_claim_transition_if_d = mubi8_t'(tap_reg2hw.claim_transition_if.q);
           Tests:       T1 T2 T3 
384                         // SW mutex claim.
385        1/1              end else if (mubi8_test_false_loose(tap_claim_transition_if_q) &&
           Tests:       T1 T2 T3 
386                             reg2hw.claim_transition_if.qe) begin
387        1/1                sw_claim_transition_if_d = mubi8_t'(reg2hw.claim_transition_if.q);
           Tests:       T1 T2 T3 
388                         end
                        MISSING_ELSE
389                     
390                     
391                         // The idle signal serves as the REGWEN in this case.
392        1/1              if (lc_idle_d) begin
           Tests:       T1 T2 T3 
393                           // The TAP has priority.
394        1/1                if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
395        1/1                  transition_cmd = tap_reg2hw.transition_cmd.q &
           Tests:       T4 T6 T7 
396                                              tap_reg2hw.transition_cmd.qe;
397                     
398        1/1                  if (tap_reg2hw.transition_ctrl.ext_clock_en.qe) begin
           Tests:       T4 T6 T7 
399        1/1                    use_ext_clock_d |= tap_reg2hw.transition_ctrl.ext_clock_en.q;
           Tests:       T6 T7 T8 
400                             end
                        MISSING_ELSE
401                     
402                             // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
403                             // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
404                             // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
405                             // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
406                             // ---------------------------------------------------------------
407        1/1                  if (tap_reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
           Tests:       T4 T6 T7 
408        1/1                    volatile_raw_unlock_d = tap_reg2hw.transition_ctrl.volatile_raw_unlock.q;
           Tests:       T6 T7 T8 
409                             end
                        MISSING_ELSE
410                             // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
411                     
412        1/1                  for (int k = 0; k < LcTokenWidth/32; k++) begin
           Tests:       T4 T6 T7 
413        1/1                    if (tap_reg2hw.transition_token[k].qe) begin
           Tests:       T4 T6 T7 
414        1/1                      transition_token_d[k*32 +: 32] = tap_reg2hw.transition_token[k].q;
           Tests:       T4 T6 T7 
415                               end
                        MISSING_ELSE
416                             end
417                     
418        1/1                  if (tap_reg2hw.transition_target.qe) begin
           Tests:       T4 T6 T7 
419        1/1                    for (int k = 0; k < DecLcStateNumRep; k++) begin
           Tests:       T4 T6 T7 
420        1/1                      transition_target_d[k] = dec_lc_state_e'(
           Tests:       T4 T6 T7 
421                                     tap_reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
422                               end
423                             end
                        MISSING_ELSE
424                     
425        1/1                  if (tap_reg2hw.otp_vendor_test_ctrl.qe) begin
           Tests:       T4 T6 T7 
426        1/1                    otp_vendor_test_ctrl_d = tap_reg2hw.otp_vendor_test_ctrl.q;
           Tests:       T4 T6 T7 
427                             end
                        MISSING_ELSE
428        1/1                end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
429        1/1                  transition_cmd = reg2hw.transition_cmd.q &
           Tests:       T1 T2 T12 
430                                              reg2hw.transition_cmd.qe;
431                     
432        1/1                  if (reg2hw.transition_ctrl.ext_clock_en.qe) begin
           Tests:       T1 T2 T12 
433        1/1                    use_ext_clock_d |= reg2hw.transition_ctrl.ext_clock_en.q;
           Tests:       T1 T2 T12 
434                             end
                        MISSING_ELSE
435                     
436                             // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
437                             // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
438                             // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
439                             // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
440                             // ---------------------------------------------------------------
441        1/1                  if (reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
           Tests:       T1 T2 T12 
442        1/1                    volatile_raw_unlock_d = reg2hw.transition_ctrl.volatile_raw_unlock.q;
           Tests:       T1 T2 T12 
443                             end
                        MISSING_ELSE
444                             // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
445                     
446        1/1                  for (int k = 0; k < LcTokenWidth/32; k++) begin
           Tests:       T1 T2 T12 
447        1/1                    if (reg2hw.transition_token[k].qe) begin
           Tests:       T1 T2 T12 
448        1/1                      transition_token_d[k*32 +: 32] = reg2hw.transition_token[k].q;
           Tests:       T1 T2 T12 
449                               end
                        MISSING_ELSE
450                             end
451                     
452        1/1                  if (reg2hw.transition_target.qe) begin
           Tests:       T1 T2 T12 
453        1/1                    for (int k = 0; k < DecLcStateNumRep; k++) begin
           Tests:       T1 T2 T12 
454        1/1                      transition_target_d[k] = dec_lc_state_e'(
           Tests:       T1 T2 T12 
455                                     reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
456                               end
457                             end
                        MISSING_ELSE
458                     
459        1/1                  if (reg2hw.otp_vendor_test_ctrl.qe) begin
           Tests:       T1 T2 T12 
460        1/1                    otp_vendor_test_ctrl_d = reg2hw.otp_vendor_test_ctrl.q;
           Tests:       T2 T5 T7 
461                             end
                        MISSING_ELSE
462                           end
                        MISSING_ELSE
463                         end
                        MISSING_ELSE
464                       end
465                     
466                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_csrs
467        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
468        1/1                trans_success_q           <= 1'b0;
           Tests:       T1 T2 T3 
469        1/1                trans_cnt_oflw_error_q    <= 1'b0;
           Tests:       T1 T2 T3 
470        1/1                trans_invalid_error_q     <= 1'b0;
           Tests:       T1 T2 T3 
471        1/1                token_invalid_error_q     <= 1'b0;
           Tests:       T1 T2 T3 
472        1/1                flash_rma_error_q         <= 1'b0;
           Tests:       T1 T2 T3 
473        1/1                fatal_prog_error_q        <= 1'b0;
           Tests:       T1 T2 T3 
474        1/1                fatal_state_error_q       <= 1'b0;
           Tests:       T1 T2 T3 
475        1/1                sw_claim_transition_if_q  <= MuBi8False;
           Tests:       T1 T2 T3 
476        1/1                tap_claim_transition_if_q <= MuBi8False;
           Tests:       T1 T2 T3 
477        1/1                transition_token_q        <= '0;
           Tests:       T1 T2 T3 
478        1/1                transition_target_q       <= {DecLcStateNumRep{DecLcStRaw}};
           Tests:       T1 T2 T3 
479        1/1                otp_part_error_q          <= 1'b0;
           Tests:       T1 T2 T3 
480        1/1                fatal_bus_integ_error_q   <= 1'b0;
           Tests:       T1 T2 T3 
481        1/1                otp_vendor_test_ctrl_q    <= '0;
           Tests:       T1 T2 T3 
482        1/1                use_ext_clock_q           <= 1'b0;
           Tests:       T1 T2 T3 
483                         end else begin
484                           // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
485                           // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
486                           // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
487                           // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
488                           // ---------------------------------------------------------------
489                           // In case of a volatile RAW unlock, this bit has to be cleared when the volatile
490                           // unlock is followed by a real transition.
491                           // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
492        1/1                if (SecVolatileRawUnlockEn && transition_cmd && !volatile_raw_unlock_q) begin
           Tests:       T1 T2 T3 
493        1/1                  trans_success_q <= 1'b0;
           Tests:       T1 T2 T4 
494                           end else begin
495        1/1                  trans_success_q <= trans_success_d | trans_success_q;
           Tests:       T1 T2 T3 
496                           end
497                           // All other status and error bits are terminal and require a reset cycle.
498        1/1                trans_cnt_oflw_error_q    <= trans_cnt_oflw_error_d  | trans_cnt_oflw_error_q;
           Tests:       T1 T2 T3 
499        1/1                trans_invalid_error_q     <= trans_invalid_error_d   | trans_invalid_error_q;
           Tests:       T1 T2 T3 
500        1/1                token_invalid_error_q     <= token_invalid_error_d   | token_invalid_error_q;
           Tests:       T1 T2 T3 
501        1/1                flash_rma_error_q         <= flash_rma_error_d       | flash_rma_error_q;
           Tests:       T1 T2 T3 
502        1/1                fatal_prog_error_q        <= otp_prog_error_d        | fatal_prog_error_q;
           Tests:       T1 T2 T3 
503        1/1                fatal_state_error_q       <= state_invalid_error_d   | fatal_state_error_q;
           Tests:       T1 T2 T3 
504        1/1                otp_part_error_q          <= otp_lc_data_i.error     | otp_part_error_q;
           Tests:       T1 T2 T3 
505        1/1                fatal_bus_integ_error_q   <= fatal_bus_integ_error_csr_d |
           Tests:       T1 T2 T3 
506                                                        fatal_bus_integ_error_tap_d |
507                                                        fatal_bus_integ_error_q;
508                           // Other regs, gated by mutex further below.
509        1/1                sw_claim_transition_if_q  <= sw_claim_transition_if_d;
           Tests:       T1 T2 T3 
510        1/1                tap_claim_transition_if_q <= tap_claim_transition_if_d;
           Tests:       T1 T2 T3 
511        1/1                transition_token_q        <= transition_token_d;
           Tests:       T1 T2 T3 
512        1/1                transition_target_q       <= transition_target_d;
           Tests:       T1 T2 T3 
513        1/1                otp_vendor_test_ctrl_q    <= otp_vendor_test_ctrl_d;
           Tests:       T1 T2 T3 
514        1/1                use_ext_clock_q           <= use_ext_clock_d;
           Tests:       T1 T2 T3 
515                         end
516                       end
517                     
518                       // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
519                       // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
520                       // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
521                       // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
522                       // ---------------------------------------------------------------
523                       // If not enabled, this register will become a constant.
524                       if (SecVolatileRawUnlockEn) begin : gen_volatile_raw_unlock_reg
525                         always_ff @(posedge clk_i or negedge rst_ni) begin : p_volatile_raw_unlock_reg
526        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
527        1/1                  volatile_raw_unlock_q     <= 1'b0;
           Tests:       T1 T2 T3 
528                           end else begin
529        1/1                  volatile_raw_unlock_q     <= volatile_raw_unlock_d;
           Tests:       T1 T2 T3 
530                           end
531                         end
532                       end else begin : gen_volatile_raw_unlock_const
533                         logic unused_volatile_raw_unlock;
534                         assign unused_volatile_raw_unlock = ^volatile_raw_unlock_d;
535                         assign volatile_raw_unlock_q = 1'b0;
536                       end
537                       // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
538                     
539        1/1            assign lc_flash_rma_seed_o = transition_token_q[RmaSeedWidth-1:0];
           Tests:       T1 T2 T3 
540                     
541                       // Gate the vendor specific test ctrl/status bits to zero in production states.
542                       // Buffer the enable signal to prevent optimization of the multibit signal.
543                       lc_tx_t lc_raw_test_rma;
544                       lc_tx_t [1:0] lc_raw_test_rma_buf;
545                       prim_lc_sync #(
546                         .NumCopies(2),
547                         .AsyncOn(0)
548                       ) u_prim_lc_sync (
549                         .clk_i,
550                         .rst_ni,
551                         .lc_en_i(lc_raw_test_rma),
552                         .lc_en_o(lc_raw_test_rma_buf)
553                       );
554                     
555        1/1            assign lc_otp_vendor_test_o.ctrl = (lc_tx_test_true_strict(lc_raw_test_rma_buf[0])) ?
           Tests:       T1 T2 T3 
556                                                          otp_vendor_test_ctrl_q                           : '0;
557        1/1            assign otp_vendor_test_status    = (lc_tx_test_true_strict(lc_raw_test_rma_buf[1])) ?
           Tests:       T1 T2 T3 
558                                                          lc_otp_vendor_test_i.status                      : '0;
559                     
560                       //////////////////
561                       // Alert Sender //
562                       //////////////////
563                     
564                       logic [NumAlerts-1:0] alerts;
565                       logic [NumAlerts-1:0] alert_test;
566                       logic [NumAlerts-1:0] tap_alert_test;
567                     
568        1/1            assign alerts = {
           Tests:       T1 T2 T3 
569                         fatal_bus_integ_error_q,
570                         fatal_state_error_q,
571                         fatal_prog_error_q
572                       };
573                     
574        1/1            assign alert_test = {
           Tests:       T1 T2 T3 
575                         reg2hw.alert_test.fatal_bus_integ_error.q &
576                         reg2hw.alert_test.fatal_bus_integ_error.qe,
577                         reg2hw.alert_test.fatal_state_error.q &
578                         reg2hw.alert_test.fatal_state_error.qe,
579                         reg2hw.alert_test.fatal_prog_error.q &
580                         reg2hw.alert_test.fatal_prog_error.qe
581                       };
582                     
583        1/1             assign tap_alert_test = {
           Tests:       T1 T2 T3 
584                         tap_reg2hw.alert_test.fatal_bus_integ_error.q &
585                         tap_reg2hw.alert_test.fatal_bus_integ_error.qe,
586                         tap_reg2hw.alert_test.fatal_state_error.q &
587                         tap_reg2hw.alert_test.fatal_state_error.qe,
588                         tap_reg2hw.alert_test.fatal_prog_error.q &
589                         tap_reg2hw.alert_test.fatal_prog_error.qe
590                       };
591                     
592                       for (genvar k = 0; k < NumAlerts; k++) begin : gen_alert_tx
593                         prim_alert_sender #(
594                           .AsyncOn(AlertAsyncOn[k]),
595                           .IsFatal(1)
596                         ) u_prim_alert_sender (
597                           .clk_i,
598                           .rst_ni,
599                           .alert_test_i  ( alert_test[k] |
600                                            tap_alert_test[k] ),
601                           .alert_req_i   ( alerts[k]         ),
602                           .alert_ack_o   (                   ),
603                           .alert_state_o (                   ),
604                           .alert_rx_i    ( alert_rx_i[k]     ),
605                           .alert_tx_o    ( alert_tx_o[k]     )
606                         );
607                       end
608                     
609                       //////////////////////////
610                       // Escalation Receivers //
611                       //////////////////////////
612                     
613                       // SEC_CM: MAIN.FSM.GLOBAL_ESC
614                       // We still have two escalation receivers here for historical reasons.
615                       // The two actions "wipe secrets" and "scrap lifecycle state" have been
616                       // combined in order to simplify both DV and the design, as otherwise
617                       // this separation of very intertwined actions would have caused too many
618                       // unnecessary corner cases. The escalation receivers are now redundant and
619                       // trigger both actions at once.
620                     
621                       // This escalation action moves the life cycle
622                       // state into a temporary "SCRAP" state named "ESCALATE",
623                       // and asserts the lc_escalate_en life cycle control signal.
624                       logic esc_scrap_state0;
625                       prim_esc_receiver #(
626                         .N_ESC_SEV   (alert_handler_reg_pkg::N_ESC_SEV),
627                         .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW)
628                       ) u_prim_esc_receiver0 (
629                         .clk_i,
630                         .rst_ni,
631                         .esc_req_o (esc_scrap_state0),
632                         .esc_rx_o  (esc_scrap_state0_rx_o),
633                         .esc_tx_i  (esc_scrap_state0_tx_i)
634                       );
635                     
636                       // This escalation action moves the life cycle
637                       // state into a temporary "SCRAP" state named "ESCALATE".
638                       logic esc_scrap_state1;
639                       prim_esc_receiver #(
640                         .N_ESC_SEV   (alert_handler_reg_pkg::N_ESC_SEV),
641                         .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW)
642                       ) u_prim_esc_receiver1 (
643                         .clk_i,
644                         .rst_ni,
645                         .esc_req_o (esc_scrap_state1),
646                         .esc_rx_o  (esc_scrap_state1_rx_o),
647                         .esc_tx_i  (esc_scrap_state1_tx_i)
648                       );
649                     
650                       ////////////////////////////
651                       // Synchronization of IOs //
652                       ////////////////////////////
653                     
654                       // Signals going to and coming from power manager.
655                       logic lc_init;
656                       prim_flop_2sync #(
657                         .Width(1)
658                       ) u_prim_flop_2sync_init (
659                         .clk_i,
660                         .rst_ni,
661                         .d_i(pwr_lc_i.lc_init),
662                         .q_o(lc_init)
663                       );
664                     
665                       logic lc_done_q;
666                       logic lc_idle_q;
667                     
668                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_sync_regs
669        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
670        1/1                lc_done_q <= 1'b0;
           Tests:       T1 T2 T3 
671        1/1                lc_idle_q <= 1'b0;
           Tests:       T1 T2 T3 
672                         end else begin
673        1/1                lc_done_q <= lc_done_d;
           Tests:       T1 T2 T3 
674        1/1                lc_idle_q <= lc_idle_d;
           Tests:       T1 T2 T3 
675                         end
676                       end
677                     
678        1/1            assign pwr_lc_o.lc_done = lc_done_q;
           Tests:       T1 T2 T3 
679        1/1            assign pwr_lc_o.lc_idle = lc_idle_q;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	71	59	83.10
Logical	71	59	83.10
Non-Logical	0	0
Event	0	0

 LINE       213
 EXPRESSION (dmi_req_ready & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T7

 LINE       241
 EXPRESSION (dmi_req_valid & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T4,T6,T7

 LINE       241
 EXPRESSION (dmi_req.op == DTM_WRITE)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       395
 EXPRESSION (tap_reg2hw.transition_cmd.q & tap_reg2hw.transition_cmd.qe)
             -------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T11,T14

 LINE       429
 EXPRESSION (reg2hw.transition_cmd.q & reg2hw.transition_cmd.qe)
             -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       492
 EXPRESSION (SecVolatileRawUnlockEn && transition_cmd && ((!volatile_raw_unlock_q)))
             -----------1----------    -------2------    -------------3------------

-1-	-2-	-3-	Status	Tests
-	0	1	Covered	T1,T2,T3
-	1	0	Covered	T1,T12,T30
-	1	1	Covered	T1,T2,T4

 LINE       495
 EXPRESSION (trans_success_d | trans_success_q)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T12

 LINE       498
 EXPRESSION (trans_cnt_oflw_error_d | trans_cnt_oflw_error_q)
             -----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T43,T44
1	0	Covered	T21,T43,T44

 LINE       499
 EXPRESSION (trans_invalid_error_d | trans_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T7,T39
1	0	Covered	T12,T6,T7

 LINE       500
 EXPRESSION (token_invalid_error_d | token_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T39,T40
1	0	Covered	T33,T39,T40

 LINE       501
 EXPRESSION (flash_rma_error_d | flash_rma_error_q)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T47,T21
1	0	Covered	T33,T47,T21

 LINE       502
 EXPRESSION (otp_prog_error_d | fatal_prog_error_q)
             --------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T14
1	0	Covered	T4,T5,T14

 LINE       503
 EXPRESSION (state_invalid_error_d | fatal_state_error_q)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T16,T36
1	0	Covered	T11,T16,T36

 LINE       504
 EXPRESSION (otp_lc_data_i.error | otp_part_error_q)
             ---------1---------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T51,T52
1	0	Covered	T21,T43,T44

 LINE       505
 EXPRESSION (fatal_bus_integ_error_csr_d | fatal_bus_integ_error_tap_d | fatal_bus_integ_error_q)
             -------------1-------------   -------------2-------------   -----------3-----------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T1,T2,T3
0	0	1	Excluded		VC_COV_UNR
0	1	0	Covered	T91,T87,T73
1	0	0	Covered	T91,T87,T73

 LINE       574
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T93,T94
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T93,T94

 LINE       574
 SUB-EXPRESSION (reg2hw.alert_test.fatal_state_error.q & reg2hw.alert_test.fatal_state_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T93,T94
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T93,T94

 LINE       574
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prog_error.q & reg2hw.alert_test.fatal_prog_error.qe)
                 ------------------1-----------------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T93,T94
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T93,T94

 LINE       583
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_bus_integ_error.q & tap_reg2hw.alert_test.fatal_bus_integ_error.qe)
                 ----------------------1----------------------   -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Not Covered

 LINE       583
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_state_error.q & tap_reg2hw.alert_test.fatal_state_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Not Covered

 LINE       583
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_prog_error.q & tap_reg2hw.alert_test.fatal_prog_error.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Not Covered

 LINE       596
 EXPRESSION (alert_test[0] | tap_alert_test[0])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T13,T93,T94

 LINE       596
 EXPRESSION (alert_test[1] | tap_alert_test[1])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T13,T93,T94

 LINE       596
 EXPRESSION (alert_test[2] | tap_alert_test[2])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T13,T93,T94

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	101	100	99.01
Total Bits	7297	7289	99.89
Total Bits 0->1	3649	3645	99.89
Total Bits 1->0	3648	3644	99.89

Ports	101	100	99.01
Port Bits	7297	7289	99.89
Port Bits 0->1	3649	3645	99.89
Port Bits 1->0	3648	3644	99.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
clk_kmac_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_kmac_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T12,T13	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T22	Yes	T1,T3,T22	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T6	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T12	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T12	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
jtag_i.tdi	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	INPUT
jtag_i.trst_n	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
jtag_i.tms	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	INPUT
jtag_i.tck	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	INPUT
jtag_o.tdo_oe	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT
jtag_o.tdo	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT
scan_rst_ni	Yes	Yes	T6,T7,T8	Yes	T7,T9,T10	INPUT
scanmode_i[3:0]	No	No		No		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T13,T4,T5	Yes	T13,T4,T5	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T13,T11,T16	Yes	T13,T11,T16	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T13,T93,T94	Yes	T13,T93,T94	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T13,T4,T5	Yes	T13,T4,T5	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T13,T11,T16	Yes	T13,T11,T16	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T13,T93,T94	Yes	T13,T93,T94	OUTPUT
esc_scrap_state0_tx_i.resp_n	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
esc_scrap_state0_tx_i.resp_p	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
esc_scrap_state0_rx_o.esc_n	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
esc_scrap_state0_rx_o.esc_p	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
esc_scrap_state1_tx_i.resp_n	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
esc_scrap_state1_tx_i.resp_p	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
esc_scrap_state1_rx_o.esc_n	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
esc_scrap_state1_rx_o.esc_p	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
pwr_lc_i.lc_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_lc_o.lc_idle	Yes	Yes	T1,T2,T12	Yes	T1,T2,T3	OUTPUT
pwr_lc_o.lc_done	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
strap_en_override_o	Yes	Excluded		Yes	T1,T12,T30	OUTPUT	1->0:VC_COV_UNR
lc_otp_vendor_test_o.ctrl[31:0]	Yes	Yes	T5,T7,T11	Yes	T6,T5,T7	OUTPUT
lc_otp_vendor_test_i.status[31:0]	Yes	Yes	T15,T16,T42	Yes	T3,T12,T22	INPUT
lc_otp_program_o.count[383:0]	Yes	Yes	T16,T36,T33	Yes	T16,T36,T33	OUTPUT
lc_otp_program_o.state[319:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	OUTPUT
lc_otp_program_o.req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
lc_otp_program_i.ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
lc_otp_program_i.err	Yes	Yes	T96,T97,T98	Yes	T50,T96,T56	INPUT
kmac_data_i.error	Yes	Yes	T21,T43,T44	Yes	T21,T43,T44	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T2,T16,T17	Yes	T2,T16,T17	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T2,T16,T17	Yes	T2,T16,T17	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	INPUT
kmac_data_i.ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T2,T11,T16	Yes	T2,T11,T16	OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	OUTPUT
otp_lc_data_i.rma_token[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
otp_lc_data_i.rma_token_valid[3:0]	Yes	Yes	T47,T53,T99	Yes	T47,T53,T99	INPUT
otp_lc_data_i.test_exit_token[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
otp_lc_data_i.test_unlock_token[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
otp_lc_data_i.test_tokens_valid[3:0]	Yes	Yes	T33,T47,T53	Yes	T33,T47,T53	INPUT
otp_lc_data_i.secrets_valid[3:0]	Yes	Yes	T33,T47,T53	Yes	T33,T47,T53	INPUT
otp_lc_data_i.count[383:0]	Yes	Yes	T16,T36,T33	Yes	T16,T36,T33	INPUT
otp_lc_data_i.state[319:0]	Yes	Yes	T2,T4,T15	Yes	T2,T4,T11	INPUT
otp_lc_data_i.error	Yes	Yes	T21,T43,T44	Yes	T21,T43,T44	INPUT
otp_lc_data_i.valid	Yes	Yes	T11,T16,T60	Yes	T11,T16,T36	INPUT
lc_dft_en_o[3:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T3	OUTPUT
lc_nvm_debug_en_o[3:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T3	OUTPUT
lc_hw_debug_en_o[3:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T3	OUTPUT
lc_cpu_en_o[3:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T3	OUTPUT
lc_creator_seed_sw_rw_en_o[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
lc_owner_seed_sw_rw_en_o[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
lc_iso_part_sw_rd_en_o[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
lc_iso_part_sw_wr_en_o[3:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T3	OUTPUT
lc_seed_hw_rd_en_o[3:0]	Yes	Yes	T11,T18,T19	Yes	T11,T18,T19	OUTPUT
lc_keymgr_en_o[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
lc_escalate_en_o[3:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
lc_check_byp_en_o[3:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T4	OUTPUT
lc_clk_byp_req_o[3:0]	Yes	Yes	T2,T17,T19	Yes	T2,T7,T17	OUTPUT
lc_clk_byp_ack_i[3:0]	Yes	Yes	T2,T17,T19	Yes	T2,T17,T30	INPUT
lc_flash_rma_seed_o[31:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	OUTPUT
lc_flash_rma_req_o[3:0]	Yes	Yes	T2,T16,T18	Yes	T2,T16,T18	OUTPUT
lc_keymgr_div_o[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
otp_device_id_i[255:0]	Yes	Yes	T2,T4,T11	Yes	T1,T2,T4	INPUT
otp_manuf_state_i[255:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
hw_rev_o.reserved[23:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
hw_rev_o.revision_id[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
hw_rev_o.product_id[15:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
hw_rev_o.silicon_creator_id[15:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		31	31	100.00
IF	347	3	3	100.00
IF	381	3	3	100.00
IF	392	18	18	100.00
IF	467	3	3	100.00
IF	669	2	2	100.00
IF	526	2	2	100.00

347            if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
               -1-                                                
348              tap_hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
                 ==>
349              tap_hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
350              tap_hw2reg.transition_token  = transition_token_q;
351              tap_hw2reg.transition_target = transition_target_q;
352              // SEC_CM: TRANSITION.CONFIG.REGWEN
353              tap_hw2reg.transition_regwen = lc_idle_d;
354              tap_hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
355              tap_hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
356            end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
                        -2-                                               
357              hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
                 ==>
358              hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
359              hw2reg.transition_token  = transition_token_q;
360              hw2reg.transition_target = transition_target_q;
361              // SEC_CM: TRANSITION.CONFIG.REGWEN
362              hw2reg.transition_regwen = lc_idle_d;
363              hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
364              hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
365            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T7
0	1	Covered	T1,T2,T12
0	0	Covered	T1,T2,T3

381            if (mubi8_test_false_loose(sw_claim_transition_if_q) &&
               -1-                                               
382                tap_reg2hw.claim_transition_if.qe) begin
383              tap_claim_transition_if_d = mubi8_t'(tap_reg2hw.claim_transition_if.q);
                 ==>
384            // SW mutex claim.
385            end else if (mubi8_test_false_loose(tap_claim_transition_if_q) &&
                        -2-                                                
386                reg2hw.claim_transition_if.qe) begin
387              sw_claim_transition_if_d = mubi8_t'(reg2hw.claim_transition_if.q);
                 ==>
388            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

392            if (lc_idle_d) begin
               -1-  
393              // The TAP has priority.
394              if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
                 -2-                                                
395                transition_cmd = tap_reg2hw.transition_cmd.q &
396                                 tap_reg2hw.transition_cmd.qe;
397        
398                if (tap_reg2hw.transition_ctrl.ext_clock_en.qe) begin
                   -3-  
399                  use_ext_clock_d |= tap_reg2hw.transition_ctrl.ext_clock_en.q;
                     ==>
400                end
                   MISSING_ELSE
                   ==>
401        
402                // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
403                // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
404                // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
405                // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
406                // ---------------------------------------------------------------
407                if (tap_reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
                   -4-  
408                  volatile_raw_unlock_d = tap_reg2hw.transition_ctrl.volatile_raw_unlock.q;
                     ==>
409                end
                   MISSING_ELSE
                   ==>
410                // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
411        
412                for (int k = 0; k < LcTokenWidth/32; k++) begin
413                  if (tap_reg2hw.transition_token[k].qe) begin
414                    transition_token_d[k*32 +: 32] = tap_reg2hw.transition_token[k].q;
415                  end
416                end
417        
418                if (tap_reg2hw.transition_target.qe) begin
                   -5-  
419                  for (int k = 0; k < DecLcStateNumRep; k++) begin
                     ==>
420                    transition_target_d[k] = dec_lc_state_e'(
421                        tap_reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
422                  end
423                end
                   MISSING_ELSE
                   ==>
424        
425                if (tap_reg2hw.otp_vendor_test_ctrl.qe) begin
                   -6-  
426                  otp_vendor_test_ctrl_d = tap_reg2hw.otp_vendor_test_ctrl.q;
                     ==>
427                end
                   MISSING_ELSE
                   ==>
428              end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
                          -7-                                               
429                transition_cmd = reg2hw.transition_cmd.q &
430                                 reg2hw.transition_cmd.qe;
431        
432                if (reg2hw.transition_ctrl.ext_clock_en.qe) begin
                   -8-  
433                  use_ext_clock_d |= reg2hw.transition_ctrl.ext_clock_en.q;
                     ==>
434                end
                   MISSING_ELSE
                   ==>
435        
436                // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
437                // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
438                // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
439                // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
440                // ---------------------------------------------------------------
441                if (reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
                   -9-  
442                  volatile_raw_unlock_d = reg2hw.transition_ctrl.volatile_raw_unlock.q;
                     ==>
443                end
                   MISSING_ELSE
                   ==>
444                // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
445        
446                for (int k = 0; k < LcTokenWidth/32; k++) begin
447                  if (reg2hw.transition_token[k].qe) begin
448                    transition_token_d[k*32 +: 32] = reg2hw.transition_token[k].q;
449                  end
450                end
451        
452                if (reg2hw.transition_target.qe) begin
                   -10-  
453                  for (int k = 0; k < DecLcStateNumRep; k++) begin
                     ==>
454                    transition_target_d[k] = dec_lc_state_e'(
455                        reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
456                  end
457                end
                   MISSING_ELSE
                   ==>
458        
459                if (reg2hw.otp_vendor_test_ctrl.qe) begin
                   -11-  
460                  otp_vendor_test_ctrl_d = reg2hw.otp_vendor_test_ctrl.q;
                     ==>
461                end
                   MISSING_ELSE
                   ==>
462              end
                 MISSING_ELSE
                 ==>
463            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
1	1	1	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
1	1	0	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
1	1	-	1	-	-	-	-	-	-	-	Covered	T6,T7,T8
1	1	-	0	-	-	-	-	-	-	-	Covered	T4,T6,T7
1	1	-	-	1	-	-	-	-	-	-	Covered	T4,T6,T7
1	1	-	-	0	-	-	-	-	-	-	Covered	T4,T6,T7
1	1	-	-	-	1	-	-	-	-	-	Covered	T4,T6,T7
1	1	-	-	-	0	-	-	-	-	-	Covered	T4,T6,T7
1	0	-	-	-	-	1	1	-	-	-	Covered	T1,T2,T12
1	0	-	-	-	-	1	0	-	-	-	Covered	T1,T2,T12
1	0	-	-	-	-	1	-	1	-	-	Covered	T1,T2,T12
1	0	-	-	-	-	1	-	0	-	-	Covered	T1,T2,T12
1	0	-	-	-	-	1	-	-	1	-	Covered	T1,T2,T12
1	0	-	-	-	-	1	-	-	0	-	Covered	T1,T2,T12
1	0	-	-	-	-	1	-	-	-	1	Covered	T2,T5,T7
1	0	-	-	-	-	1	-	-	-	0	Covered	T1,T2,T12
1	0	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

467            if (!rst_ni) begin
               -1-  
468              trans_success_q           <= 1'b0;
                 ==>
469              trans_cnt_oflw_error_q    <= 1'b0;
470              trans_invalid_error_q     <= 1'b0;
471              token_invalid_error_q     <= 1'b0;
472              flash_rma_error_q         <= 1'b0;
473              fatal_prog_error_q        <= 1'b0;
474              fatal_state_error_q       <= 1'b0;
475              sw_claim_transition_if_q  <= MuBi8False;
476              tap_claim_transition_if_q <= MuBi8False;
477              transition_token_q        <= '0;
478              transition_target_q       <= {DecLcStateNumRep{DecLcStRaw}};
479              otp_part_error_q          <= 1'b0;
480              fatal_bus_integ_error_q   <= 1'b0;
481              otp_vendor_test_ctrl_q    <= '0;
482              use_ext_clock_q           <= 1'b0;
483            end else begin
484              // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
485              // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
486              // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
487              // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
488              // ---------------------------------------------------------------
489              // In case of a volatile RAW unlock, this bit has to be cleared when the volatile
490              // unlock is followed by a real transition.
491              // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
492              if (SecVolatileRawUnlockEn && transition_cmd && !volatile_raw_unlock_q) begin
                 -2-  
493                trans_success_q <= 1'b0;
                   ==>
494              end else begin
495                trans_success_q <= trans_success_d | trans_success_q;
                   ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

669            if (!rst_ni) begin
               -1-  
670              lc_done_q <= 1'b0;
                 ==>
671              lc_idle_q <= 1'b0;
672            end else begin
673              lc_done_q <= lc_done_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

526              if (!rst_ni) begin
                 -1-  
527                volatile_raw_unlock_q     <= 1'b0;
                   ==>
528              end else begin
529                volatile_raw_unlock_q     <= volatile_raw_unlock_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	28	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	28	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	58101981	54873882	0	0
DecLcCountWidthCheck_A	812	812	0	0
DecLcIdStateWidthCheck_A	812	812	0	0
DecLcStateWidthCheck_A	812	812	0	0
FpvSecCmCtrlKmacIfFsmCheck_A	56483286	0	0	0
FpvSecCmCtrlLcCntCheck_A	53137619	0	0	0
FpvSecCmCtrlLcFsmCheck_A	56479171	0	0	0
FpvSecCmCtrlLcStateCheck_A	54746572	1	0	0
FpvSecCmRegWeOnehotCheck_A	58101981	70	0	0
FpvSecCmTapRegWeOnehotCheck_A	58101981	0	0	0
LcCheckBypassEnKnown_A	58101981	54873882	0	0
LcClkBypReqKnown_A	58101981	54873882	0	0
LcCpuEnKnown_A	58101981	54873882	0	0
LcCreatorSwRwEn_A	58101981	54873882	0	0
LcDftEnKnown_A	58101981	54873882	0	0
LcEscalateEnKnown_A	58101981	54873882	0	0
LcFlashRmaReqKnown_A	58101981	54873882	0	0
LcFlashRmaSeedKnown_A	58101981	54873882	0	0
LcHwDebugEnKnown_A	58101981	54873882	0	0
LcIsoSwRwEn_A	58101981	54873882	0	0
LcIsoSwWrEn_A	58101981	54873882	0	0
LcKeymgrDiv_A	58101981	54873882	0	0
LcKeymgrEnKnown_A	58101981	54873882	0	0
LcNvmDebugEnKnown_A	58101981	54873882	0	0
LcOtpProgramKnown_A	58101981	54873882	0	0
LcOtpTokenKnown_A	58101981	54873882	0	0
LcOwnerSwRwEn_A	58101981	54873882	0	0
LcSeedHwRdEn_A	58101981	54873882	0	0
NumTokenWordsCheck_A	812	812	0	0
OtpTestCtrlWidth_A	812	812	0	0
PwrLcKnown_A	58101981	54873882	0	0
TlOKnown	58101981	54873882	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

DecLcCountWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

DecLcIdStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

DecLcStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FpvSecCmCtrlKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56483286	0	0	0

FpvSecCmCtrlLcCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53137619	0	0	0

FpvSecCmCtrlLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56479171	0	0	0

FpvSecCmCtrlLcStateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54746572	1	0	0
T100	177640	1	0	0
T101	1388	0	0	0
T102	48335	0	0	0
T103	24162	0	0	0
T104	6615	0	0	0
T105	2831	0	0	0
T106	24727	0	0	0
T107	51535	0	0	0
T108	8795	0	0	0
T109	25258	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	70	0	0
T10	4948	0	0	0
T48	24433	0	0	0
T67	0	20	0	0
T73	0	10	0	0
T87	0	20	0	0
T91	12013	10	0	0
T92	56103	0	0	0
T110	0	10	0	0
T111	796	0	0	0
T112	7438	0	0	0
T113	4082	0	0	0
T114	121874	0	0	0
T115	20338	0	0	0
T116	91422	0	0	0

FpvSecCmTapRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	0	0	0

LcCheckBypassEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcClkBypReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcCpuEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcCreatorSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcDftEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcEscalateEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcFlashRmaReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcFlashRmaSeedKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcHwDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcIsoSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcIsoSwWrEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcKeymgrDiv_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcKeymgrEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcNvmDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcOtpProgramKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcOtpTokenKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcOwnerSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcSeedHwRdEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

NumTokenWordsCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpTestCtrlWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

PwrLcKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

TlOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0