83db9403d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 17.000s | 111.435us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 56.000s | 242.190us | 94 | 100 | 94.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 7.000s | 27.841us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 6.000s | 17.181us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 9.000s | 142.931us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 5.000s | 14.665us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 9.000s | 26.963us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 6.000s | 17.181us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 5.000s | 14.665us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 21.000s | 2.294ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 11.000s | 2.090ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 160 | 166 | 96.39 | |||
| V2 | reset_recovery | otbn_reset | 27.000s | 97.192us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 46.000s | 722.121us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 2.583m | 693.724us | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 14.017m | 3.897ms | 8 | 10 | 80.00 |
| V2 | lc_escalation | otbn_escalate | 20.000s | 41.511us | 49 | 60 | 81.67 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 10.000s | 54.130us | 3 | 5 | 60.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 1.067m | 253.752us | 9 | 10 | 90.00 |
| V2 | alert_test | otbn_alert_test | 7.000s | 21.921us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 6.000s | 19.934us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 10.000s | 470.235us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 10.000s | 470.235us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 7.000s | 27.841us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 17.181us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 14.665us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 7.000s | 26.610us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 7.000s | 27.841us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 17.181us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 14.665us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 7.000s | 26.610us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 230 | 246 | 93.50 | |||
| V2S | mem_integrity | otbn_imem_err | 46.000s | 194.348us | 10 | 10 | 100.00 |
| otbn_dmem_err | 20.000s | 82.339us | 14 | 15 | 93.33 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 9.000s | 25.265us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 10.000s | 35.806us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 9.000s | 16.016us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 9.000s | 20.678us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 7.000s | 82.548us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 8.000s | 20.808us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 4.933m | 1.426ms | 5 | 5 | 100.00 |
| otbn_tl_intg_err | 29.000s | 195.045us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 48.000s | 505.311us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 4.933m | 1.426ms | 5 | 5 | 100.00 |
| V2S | prim_count_check | otbn_sec_cm | 4.933m | 1.426ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 17.000s | 111.435us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 20.000s | 82.339us | 14 | 15 | 93.33 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 46.000s | 194.348us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 29.000s | 195.045us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 20.000s | 41.511us | 49 | 60 | 81.67 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 46.000s | 194.348us | 10 | 10 | 100.00 |
| otbn_dmem_err | 20.000s | 82.339us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 10.000s | 54.130us | 3 | 5 | 60.00 | ||
| otbn_illegal_mem_acc | 7.000s | 82.548us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.933m | 1.426ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 4.933m | 1.426ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 56.000s | 242.190us | 94 | 100 | 94.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 46.000s | 194.348us | 10 | 10 | 100.00 |
| otbn_dmem_err | 20.000s | 82.339us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 10.000s | 54.130us | 3 | 5 | 60.00 | ||
| otbn_illegal_mem_acc | 7.000s | 82.548us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.933m | 1.426ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 4.933m | 1.426ms | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 20.000s | 41.511us | 49 | 60 | 81.67 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 46.000s | 194.348us | 10 | 10 | 100.00 |
| otbn_dmem_err | 20.000s | 82.339us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 10.000s | 54.130us | 3 | 5 | 60.00 | ||
| otbn_illegal_mem_acc | 7.000s | 82.548us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.933m | 1.426ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 4.933m | 1.426ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 56.000s | 242.190us | 94 | 100 | 94.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 10.000s | 23.525us | 11 | 12 | 91.67 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 8.000s | 54.036us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 43.000s | 178.171us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 43.000s | 178.171us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 11.000s | 47.870us | 7 | 10 | 70.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 4.933m | 1.426ms | 5 | 5 | 100.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 4.933m | 1.426ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 9.000s | 15.559us | 9 | 10 | 90.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 4.933m | 1.426ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 4.933m | 1.426ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 2.300m | 10.005ms | 3 | 5 | 60.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 2.300m | 10.005ms | 3 | 5 | 60.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 12.000s | 59.733us | 6 | 7 | 85.71 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 56.000s | 242.190us | 94 | 100 | 94.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 56.000s | 242.190us | 94 | 100 | 94.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 56.000s | 242.190us | 94 | 100 | 94.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 2.583m | 693.724us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 56.000s | 242.190us | 94 | 100 | 94.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 56.000s | 242.190us | 94 | 100 | 94.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 53.000s | 232.997us | 4 | 5 | 80.00 |
| V2S | sec_cm_key_sideload | otbn_single | 56.000s | 242.190us | 94 | 100 | 94.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 4.933m | 1.426ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 143 | 153 | 93.46 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 23.117m | 78.133ms | 7 | 10 | 70.00 |
| V3 | TOTAL | 7 | 10 | 70.00 | |||
| TOTAL | 540 | 575 | 93.91 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 7 | 63.64 |
| V2S | 19 | 19 | 12 | 63.16 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.73 | 99.50 | 94.07 | 99.62 | 91.10 | 93.05 | 97.44 | 91.28 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,270): Assertion MatchingStatus_A has failed has 5 failures:
2.otbn_escalate.3715293885
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 8106929 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 8106929 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 8106929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.otbn_escalate.1704620172
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/30.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 29810112 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 29810112 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 29810112 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 29810112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
5.otbn_rf_base_intg_err.1448797093
Line 243, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_rf_base_intg_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 104563063 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 104563063 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 104563063 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 104563063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.otbn_rf_base_intg_err.3901351882
Line 243, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_rf_base_intg_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 117340193 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 117340193 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 117340193 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 117340193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 5 failures:
19.otbn_escalate.3055574773
Line 261, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/19.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4154502 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 4154502 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 4154502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.otbn_escalate.3211806122
Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/31.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1691408 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1691408 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1691408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 4 failures:
1.otbn_single.4180497796
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_single/latest/run.log
UVM_FATAL @ 12400895 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 12400895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.otbn_single.3930564666
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/29.otbn_single/latest/run.log
UVM_FATAL @ 10899857 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 10899857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 2 failures:
Test otbn_stress_all_with_rand_reset has 1 failures.
1.otbn_stress_all_with_rand_reset.3686365045
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 4994058 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 4994058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_single has 1 failures.
97.otbn_single.405699829
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/97.otbn_single/latest/run.log
UVM_FATAL @ 63141389 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 63141389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 2 failures:
2.otbn_stress_all.3840369189
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all/latest/run.log
UVM_FATAL @ 33903697 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 33903697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.otbn_stress_all.2838554619
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all/latest/run.log
UVM_FATAL @ 37359169 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 37359169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:
Test otbn_zero_state_err_urnd has 1 failures.
3.otbn_zero_state_err_urnd.3092403600
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_zero_state_err_urnd/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 8411835 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 8411835 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 8411835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 1 failures.
27.otbn_escalate.3960328949
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/27.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 31218664 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 31218664 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 31218664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
0.otbn_rf_base_intg_err.3848523811
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 11974682 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 11974682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_stack_addr_integ_chk_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
0.otbn_stack_addr_integ_chk.2716706444
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 5021286 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 5021286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_zero_state_err_urnd_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
2.otbn_zero_state_err_urnd.2916563398
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_zero_state_err_urnd/latest/run.log
UVM_FATAL @ 11240220 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_zero_state_err_urnd_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 11240220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_rf_bignum_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
3.otbn_rf_bignum_intg_err.4159393415
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_rf_bignum_intg_err/latest/run.log
UVM_FATAL @ 19741262 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_rf_bignum_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 19741262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
3.otbn_stress_all_with_rand_reset.2594601519
Line 338, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1105284660 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 1105284660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_sec_wipe_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
3.otbn_sec_wipe_err.3487198993
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_wipe_err/latest/run.log
UVM_FATAL @ 14693311 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_sec_wipe_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 14693311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
3.otbn_stack_addr_integ_chk.3615776554
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 10004817738 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
UVM_INFO @ 10004817738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
4.otbn_dmem_err.708905923
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_dmem_err/latest/run.log
UVM_FATAL @ 13243797 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 13243797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_sw_no_acc_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
4.otbn_sw_no_acc.1171393371
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sw_no_acc/latest/run.log
UVM_FATAL @ 11902399 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_sw_no_acc_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 11902399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1258): Assertion InitSecWipeNonZeroWideRegs_A has failed has 1 failures:
8.otbn_ctrl_redun.3492899763
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 6860787 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 6860787 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 6860787 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 6860787 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[28].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 6860787 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[27].InitSecWipeNonZeroWideRegs_A has failed
UVM_ERROR (cip_base_vseq.sv:717) [otbn_common_vseq] Check failed has_outstanding_access() == * (* [*] vs * [*]) No CSR outstanding items after reset! has 1 failures:
9.otbn_stress_all_with_rand_reset.1502350144
Line 358, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2372864722 ps: (cip_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed has_outstanding_access() == 0 (1 [0x1] vs 0 [0x0]) No CSR outstanding items after reset!
UVM_INFO @ 2372864722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_sw_errs_fatal_chk_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
9.otbn_sw_errs_fatal_chk.2909211194
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_sw_errs_fatal_chk/latest/run.log
UVM_FATAL @ 18863697 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_sw_errs_fatal_chk_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 18863697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:495) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 1 failures:
45.otbn_escalate.2692220395
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/45.otbn_escalate/latest/run.log
UVM_FATAL @ 6960298 ps: (otbn_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 400 cycles ago and we still don't think it should have done.
UVM_INFO @ 6960298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_escalate_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
56.otbn_escalate.571735435
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/56.otbn_escalate/latest/run.log
UVM_FATAL @ 21045067 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_escalate_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 21045067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
91.otbn_single.3417791805
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/91.otbn_single/latest/run.log
UVM_FATAL @ 9303771 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 9303771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---