26b0ee226| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 10.000s | 26.632us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 1.650m | 442.488us | 95 | 100 | 95.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 5.000s | 16.814us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 7.000s | 26.595us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 9.000s | 461.008us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 6.000s | 15.395us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 12.000s | 42.047us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 7.000s | 26.595us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 6.000s | 15.395us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 30.000s | 4.066ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 13.000s | 272.189us | 5 | 5 | 100.00 |
| V1 | TOTAL | 161 | 166 | 96.99 | |||
| V2 | reset_recovery | otbn_reset | 35.000s | 138.439us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 55.000s | 144.577us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 1.983m | 503.396us | 8 | 10 | 80.00 |
| V2 | stress_all | otbn_stress_all | 1.783m | 278.260us | 9 | 10 | 90.00 |
| V2 | lc_escalation | otbn_escalate | 20.000s | 271.040us | 45 | 60 | 75.00 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 7.000s | 17.552us | 4 | 5 | 80.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 52.000s | 218.353us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 7.000s | 20.094us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 7.000s | 33.696us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 10.000s | 261.983us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 10.000s | 261.983us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 5.000s | 16.814us | 5 | 5 | 100.00 |
| otbn_csr_rw | 7.000s | 26.595us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 15.395us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 6.000s | 76.656us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 5.000s | 16.814us | 5 | 5 | 100.00 |
| otbn_csr_rw | 7.000s | 26.595us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 15.395us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 6.000s | 76.656us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 227 | 246 | 92.28 | |||
| V2S | mem_integrity | otbn_imem_err | 10.000s | 26.344us | 10 | 10 | 100.00 |
| otbn_dmem_err | 20.000s | 64.188us | 14 | 15 | 93.33 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 16.000s | 37.023us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 12.000s | 33.789us | 4 | 5 | 80.00 | ||
| otbn_mac_bignum_acc_err | 28.000s | 94.399us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 8.000s | 26.240us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 7.000s | 9.959us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 12.000s | 114.814us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 4.867m | 1.361ms | 3 | 5 | 60.00 |
| otbn_tl_intg_err | 49.000s | 362.193us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 38.000s | 215.970us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 4.867m | 1.361ms | 3 | 5 | 60.00 |
| V2S | prim_count_check | otbn_sec_cm | 4.867m | 1.361ms | 3 | 5 | 60.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 10.000s | 26.632us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 20.000s | 64.188us | 14 | 15 | 93.33 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 10.000s | 26.344us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 49.000s | 362.193us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 20.000s | 271.040us | 45 | 60 | 75.00 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 10.000s | 26.344us | 10 | 10 | 100.00 |
| otbn_dmem_err | 20.000s | 64.188us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 7.000s | 17.552us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 7.000s | 9.959us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.867m | 1.361ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 4.867m | 1.361ms | 3 | 5 | 60.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 1.650m | 442.488us | 95 | 100 | 95.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 10.000s | 26.344us | 10 | 10 | 100.00 |
| otbn_dmem_err | 20.000s | 64.188us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 7.000s | 17.552us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 7.000s | 9.959us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.867m | 1.361ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 4.867m | 1.361ms | 3 | 5 | 60.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 20.000s | 271.040us | 45 | 60 | 75.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 10.000s | 26.344us | 10 | 10 | 100.00 |
| otbn_dmem_err | 20.000s | 64.188us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 7.000s | 17.552us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 7.000s | 9.959us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.867m | 1.361ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 4.867m | 1.361ms | 3 | 5 | 60.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 1.650m | 442.488us | 95 | 100 | 95.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 7.000s | 73.198us | 11 | 12 | 91.67 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 8.000s | 37.033us | 4 | 5 | 80.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 1.783m | 505.429us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 1.783m | 505.429us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 11.000s | 29.825us | 8 | 10 | 80.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 4.867m | 1.361ms | 3 | 5 | 60.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 4.867m | 1.361ms | 3 | 5 | 60.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 9.000s | 24.455us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 4.867m | 1.361ms | 3 | 5 | 60.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 4.867m | 1.361ms | 3 | 5 | 60.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 45.000s | 10.003ms | 3 | 5 | 60.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 45.000s | 10.003ms | 3 | 5 | 60.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 18.000s | 134.022us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 1.650m | 442.488us | 95 | 100 | 95.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 1.650m | 442.488us | 95 | 100 | 95.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 1.650m | 442.488us | 95 | 100 | 95.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 1.983m | 503.396us | 8 | 10 | 80.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 1.650m | 442.488us | 95 | 100 | 95.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 1.650m | 442.488us | 95 | 100 | 95.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 21.000s | 166.231us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 1.650m | 442.488us | 95 | 100 | 95.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 4.867m | 1.361ms | 3 | 5 | 60.00 |
| V2S | TOTAL | 143 | 153 | 93.46 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 10.750m | 143.971ms | 4 | 10 | 40.00 |
| V3 | TOTAL | 4 | 10 | 40.00 | |||
| TOTAL | 535 | 575 | 93.04 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 7 | 63.64 |
| V2S | 19 | 19 | 12 | 63.16 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.75 | 99.53 | 94.46 | 99.63 | 91.05 | 92.92 | 97.44 | 91.40 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,270): Assertion MatchingStatus_A has failed has 8 failures:
Test otbn_rf_base_intg_err has 1 failures.
4.otbn_rf_base_intg_err.2043264316
Line 243, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_rf_base_intg_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 97483636 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 97483636 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 97483636 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 97483636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 6 failures.
6.otbn_escalate.2459823396
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 228615227 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 228615227 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 228615227 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 228615227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.otbn_escalate.32937585
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 1580783 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 1580783 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 1580783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test otbn_stress_all_with_rand_reset has 1 failures.
8.otbn_stress_all_with_rand_reset.1417578537
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 20592241 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 20592241 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 20592241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 4 failures:
0.otbn_single.3251302358
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_single/latest/run.log
UVM_FATAL @ 24615960 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 24615960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.otbn_single.1020776041
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_single/latest/run.log
UVM_FATAL @ 9019400 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 9019400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:
Test otbn_ctrl_redun has 1 failures.
0.otbn_ctrl_redun.539338300
Line 247, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 132293442 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 132293442 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 132293442 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 132293442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 3 failures.
4.otbn_escalate.582018137
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12627017 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 12627017 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 12627017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.otbn_escalate.85966109
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/22.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 74249608 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 74249608 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 74249608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 3 failures:
Test otbn_stress_all_with_rand_reset has 1 failures.
5.otbn_stress_all_with_rand_reset.2783476862
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 23447902 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 23447902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_stress_all has 1 failures.
7.otbn_stress_all.115120968
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all/latest/run.log
UVM_FATAL @ 44335376 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 44335376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_single has 1 failures.
87.otbn_single.2157919553
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/87.otbn_single/latest/run.log
UVM_FATAL @ 10355916 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 10355916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
2.otbn_escalate.2923660074
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log
UVM_FATAL @ 10368354 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 10368354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.otbn_escalate.2231804634
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/29.otbn_escalate/latest/run.log
UVM_FATAL @ 12585170 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 12585170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
0.otbn_stack_addr_integ_chk.2321411540
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 10025081718 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
UVM_INFO @ 10025081718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,87): Assertion IdleIfStart_A has failed has 1 failures:
1.otbn_stress_all_with_rand_reset.1418219288
Line 367, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,87): (time 742999597 PS) Assertion tb.dut.idle_checker.IdleIfStart_A has failed
UVM_ERROR @ 742999597 ps: (otbn_idle_checker.sv:87) [ASSERT FAILED] IdleIfStart_A
UVM_INFO @ 742999597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_pc_ctrl_flow_redun_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
1.otbn_pc_ctrl_flow_redun.1782806779
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_pc_ctrl_flow_redun/latest/run.log
UVM_FATAL @ 19767602 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_pc_ctrl_flow_redun_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 19767602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
1.otbn_stack_addr_integ_chk.671885306
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 10002932827 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
UVM_INFO @ 10002932827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_multi_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
2.otbn_multi.1535973855
Line 276, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_multi/latest/run.log
UVM_FATAL @ 96108694 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_multi_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 96108694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_controller_ispr_rdata_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
3.otbn_controller_ispr_rdata_err.2081620291
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_controller_ispr_rdata_err/latest/run.log
UVM_FATAL @ 22031174 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_controller_ispr_rdata_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 22031174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
3.otbn_stress_all_with_rand_reset.634871404
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 146214274 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 146214274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1258): Assertion InitSecWipeNonZeroWideRegs_A has failed has 1 failures:
3.otbn_zero_state_err_urnd.2401213402
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_zero_state_err_urnd/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 54718951 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[11].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 54718951 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[10].InitSecWipeNonZeroWideRegs_A has failed
UVM_ERROR @ 54718951 ps: (otbn.sv:1258) [ASSERT FAILED] InitSecWipeNonZeroWideRegs_A
UVM_INFO @ 54718951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1296): Assertion SecWipeNonZeroMod_A has failed has 1 failures:
3.otbn_sec_cm.4181907324
Line 218, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1296): (time 864697 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1303): (time 864697 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 864697 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 864697 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 864697 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed
UVM_FATAL (otbn_scoreboard.sv:495) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 1 failures:
4.otbn_sec_cm.2869191753
Line 221, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log
UVM_FATAL @ 6802904 ps: (otbn_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 400 cycles ago and we still don't think it should have done.
UVM_INFO @ 6802904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_multi_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
7.otbn_multi.3985086555
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_multi/latest/run.log
UVM_FATAL @ 74015405 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_multi_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 74015405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_escalate_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
7.otbn_escalate.889649945
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log
UVM_FATAL @ 46497622 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_escalate_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 46497622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_imem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
7.otbn_stress_all_with_rand_reset.616137564
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 255182413 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 255182413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_escalate_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
8.otbn_escalate.1443484906
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log
UVM_FATAL @ 20724767 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_escalate_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 20724767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
9.otbn_dmem_err.2372391503
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_dmem_err/latest/run.log
UVM_FATAL @ 49712143 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 49712143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
9.otbn_rf_base_intg_err.1425295724
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 11025365 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 11025365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_imem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
9.otbn_stress_all_with_rand_reset.2577972579
Line 295, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 591523938 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 591523938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
35.otbn_escalate.1899569199
Line 260, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/35.otbn_escalate/latest/run.log
UVM_FATAL @ 1096660 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
UVM_INFO @ 1096660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
55.otbn_escalate.173761569
Line 261, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/55.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1048365 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1048365 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1048365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---