c06cc3921| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 8.000s | 76.458us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 42.000s | 173.062us | 96 | 100 | 96.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 7.000s | 15.411us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 7.000s | 23.457us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 9.000s | 118.097us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 6.000s | 16.076us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 9.000s | 37.243us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 7.000s | 23.457us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 6.000s | 16.076us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 34.000s | 1.140ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 14.000s | 82.431us | 5 | 5 | 100.00 |
| V1 | TOTAL | 162 | 166 | 97.59 | |||
| V2 | reset_recovery | otbn_reset | 1.883m | 533.320us | 9 | 10 | 90.00 |
| V2 | multi_error | otbn_multi_err | 1.117m | 181.298us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 2.683m | 814.262us | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 1.233m | 327.297us | 5 | 10 | 50.00 |
| V2 | lc_escalation | otbn_escalate | 19.000s | 43.296us | 42 | 60 | 70.00 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 8.000s | 22.322us | 4 | 5 | 80.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 17.000s | 54.509us | 8 | 10 | 80.00 |
| V2 | alert_test | otbn_alert_test | 8.000s | 28.712us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 7.000s | 20.548us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 10.000s | 531.418us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 10.000s | 531.418us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 7.000s | 15.411us | 5 | 5 | 100.00 |
| otbn_csr_rw | 7.000s | 23.457us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 16.076us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 12.000s | 61.776us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 7.000s | 15.411us | 5 | 5 | 100.00 |
| otbn_csr_rw | 7.000s | 23.457us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 16.076us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 12.000s | 61.776us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 219 | 246 | 89.02 | |||
| V2S | mem_integrity | otbn_imem_err | 12.000s | 25.277us | 8 | 10 | 80.00 |
| otbn_dmem_err | 13.000s | 26.443us | 14 | 15 | 93.33 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 15.000s | 143.965us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 10.000s | 65.002us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 54.000s | 1.016ms | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 8.000s | 23.897us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 8.000s | 51.344us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 12.000s | 115.986us | 1 | 2 | 50.00 |
| V2S | tl_intg_err | otbn_sec_cm | 4.083m | 5.322ms | 5 | 5 | 100.00 |
| otbn_tl_intg_err | 47.000s | 338.517us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 39.000s | 232.847us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 4.083m | 5.322ms | 5 | 5 | 100.00 |
| V2S | prim_count_check | otbn_sec_cm | 4.083m | 5.322ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 8.000s | 76.458us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 13.000s | 26.443us | 14 | 15 | 93.33 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 12.000s | 25.277us | 8 | 10 | 80.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 47.000s | 338.517us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 19.000s | 43.296us | 42 | 60 | 70.00 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 12.000s | 25.277us | 8 | 10 | 80.00 |
| otbn_dmem_err | 13.000s | 26.443us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 8.000s | 22.322us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 8.000s | 51.344us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.083m | 5.322ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 4.083m | 5.322ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 42.000s | 173.062us | 96 | 100 | 96.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 12.000s | 25.277us | 8 | 10 | 80.00 |
| otbn_dmem_err | 13.000s | 26.443us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 8.000s | 22.322us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 8.000s | 51.344us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.083m | 5.322ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 4.083m | 5.322ms | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 19.000s | 43.296us | 42 | 60 | 70.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 12.000s | 25.277us | 8 | 10 | 80.00 |
| otbn_dmem_err | 13.000s | 26.443us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 8.000s | 22.322us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 8.000s | 51.344us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.083m | 5.322ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 4.083m | 5.322ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 42.000s | 173.062us | 96 | 100 | 96.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 11.000s | 371.263us | 11 | 12 | 91.67 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 10.000s | 24.774us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 1.400m | 947.860us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 1.400m | 947.860us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 12.000s | 37.727us | 6 | 10 | 60.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 4.083m | 5.322ms | 5 | 5 | 100.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 4.083m | 5.322ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 11.000s | 29.711us | 8 | 10 | 80.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 4.083m | 5.322ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 4.083m | 5.322ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 1.583m | 10.001ms | 2 | 5 | 40.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 1.583m | 10.001ms | 2 | 5 | 40.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 18.000s | 118.309us | 6 | 7 | 85.71 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 42.000s | 173.062us | 96 | 100 | 96.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 42.000s | 173.062us | 96 | 100 | 96.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 42.000s | 173.062us | 96 | 100 | 96.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 2.683m | 814.262us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 42.000s | 173.062us | 96 | 100 | 96.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 42.000s | 173.062us | 96 | 100 | 96.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 16.000s | 329.032us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 42.000s | 173.062us | 96 | 100 | 96.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 4.083m | 5.322ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 138 | 153 | 90.20 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 32.083m | 90.477ms | 6 | 10 | 60.00 |
| V3 | TOTAL | 6 | 10 | 60.00 | |||
| TOTAL | 525 | 575 | 91.30 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 6 | 54.55 |
| V2S | 19 | 19 | 11 | 57.89 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.75 | 99.50 | 94.11 | 99.62 | 91.10 | 93.26 | 97.44 | 91.28 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,270): Assertion MatchingStatus_A has failed has 11 failures:
1.otbn_rf_base_intg_err.2900164094
Line 243, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_rf_base_intg_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 397750958 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 397750958 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 397750958 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 397750958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.otbn_rf_base_intg_err.4092711470
Line 243, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_rf_base_intg_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 101675347 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 101675347 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 101675347 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 101675347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
13.otbn_escalate.539513222
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 7391830 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 7391830 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 7391830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.otbn_escalate.3491568230
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/24.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 2411097 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 2411097 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 2411097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 5 failures:
Test otbn_stress_all has 2 failures.
2.otbn_stress_all.1106520330
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all/latest/run.log
UVM_FATAL @ 76679013 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 76679013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.otbn_stress_all.2068093886
Line 278, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all/latest/run.log
UVM_FATAL @ 65542404 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 65542404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_stress_all_with_rand_reset has 2 failures.
5.otbn_stress_all_with_rand_reset.842324397
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 32269660 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 32269660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.otbn_stress_all_with_rand_reset.2113480086
Line 298, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 615663110 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 615663110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_single has 1 failures.
16.otbn_single.58939265
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_single/latest/run.log
UVM_FATAL @ 33076650 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 33076650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:
Test otbn_stack_addr_integ_chk has 1 failures.
3.otbn_stack_addr_integ_chk.2705312517
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 62135051 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 62135051 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 62135051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 4 failures.
18.otbn_escalate.3830498812
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/18.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 157739944 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 157739944 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 157739944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.otbn_escalate.3349172017
Line 243, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 44967375 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 44967375 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 44967375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_imem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 4 failures:
Test otbn_stress_all_with_rand_reset has 1 failures.
4.otbn_stress_all_with_rand_reset.3372548490
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 199616173 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 199616173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_stress_all has 2 failures.
5.otbn_stress_all.1256813934
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all/latest/run.log
UVM_FATAL @ 186399121 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 186399121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.otbn_stress_all.241281496
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all/latest/run.log
UVM_FATAL @ 358241034 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 358241034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_imem_err has 1 failures.
9.otbn_imem_err.4228344466
Line 243, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_imem_err/latest/run.log
UVM_FATAL @ 5252046 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 5252046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:
0.otbn_escalate.892730002
Line 261, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3119700 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 3119700 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 3119700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.otbn_escalate.4131804752
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/33.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1882152 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1882152 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1882152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_imem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 2 failures:
Test otbn_imem_err has 1 failures.
1.otbn_imem_err.2639736149
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_imem_err/latest/run.log
UVM_FATAL @ 10151847 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 10151847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_stress_all has 1 failures.
9.otbn_stress_all.209543361
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all/latest/run.log
UVM_FATAL @ 16329277 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 16329277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:495) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 2 failures:
Test otbn_mem_gnt_acc_err has 1 failures.
1.otbn_mem_gnt_acc_err.1918486584
Line 244, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_mem_gnt_acc_err/latest/run.log
UVM_FATAL @ 14295093 ps: (otbn_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 400 cycles ago and we still don't think it should have done.
UVM_INFO @ 14295093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 1 failures.
55.otbn_escalate.2267796256
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/55.otbn_escalate/latest/run.log
UVM_FATAL @ 7445502 ps: (otbn_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 400 cycles ago and we still don't think it should have done.
UVM_INFO @ 7445502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1258): Assertion InitSecWipeNonZeroWideRegs_A has failed has 2 failures:
Test otbn_zero_state_err_urnd has 1 failures.
2.otbn_zero_state_err_urnd.4215042543
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_zero_state_err_urnd/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 9714405 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[28].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 9714405 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[27].InitSecWipeNonZeroWideRegs_A has failed
UVM_ERROR @ 9714405 ps: (otbn.sv:1258) [ASSERT FAILED] InitSecWipeNonZeroWideRegs_A
UVM_INFO @ 9714405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_ctrl_redun has 1 failures.
4.otbn_ctrl_redun.3108650626
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 18497840 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 18497840 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 18497840 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 18497840 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[28].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 18497840 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[27].InitSecWipeNonZeroWideRegs_A has failed
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
21.otbn_escalate.798059308
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log
UVM_FATAL @ 262392782 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 262392782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.otbn_escalate.981233111
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/36.otbn_escalate/latest/run.log
UVM_FATAL @ 4976847 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 4976847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 2 failures:
53.otbn_single.1449763926
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/53.otbn_single/latest/run.log
UVM_FATAL @ 9593928 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 9593928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
86.otbn_single.4042904980
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/86.otbn_single/latest/run.log
UVM_FATAL @ 12656526 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 12656526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_reset_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
0.otbn_reset.1733976677
Line 251, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_reset/latest/run.log
UVM_FATAL @ 182987791 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_reset_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 182987791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_rf_bignum_intg_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
0.otbn_rf_bignum_intg_err.3638783188
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_rf_bignum_intg_err/latest/run.log
UVM_FATAL @ 7924259 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_rf_bignum_intg_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 7924259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
0.otbn_stack_addr_integ_chk.552485249
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 10001262539 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
UVM_INFO @ 10001262539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_sw_errs_fatal_chk_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
1.otbn_sw_errs_fatal_chk.2027714179
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sw_errs_fatal_chk/latest/run.log
UVM_FATAL @ 26789146 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_sw_errs_fatal_chk_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 26789146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_sec_wipe_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
1.otbn_sec_wipe_err.2883098504
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log
UVM_FATAL @ 9766201 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_sec_wipe_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 9766201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_stack_addr_integ_chk_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
2.otbn_stack_addr_integ_chk.993149988
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 205439189 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 205439189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
3.otbn_dmem_err.3736315440
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_dmem_err/latest/run.log
UVM_FATAL @ 20201267 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 20201267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
3.otbn_stress_all_with_rand_reset.1043381972
Line 297, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 681845720 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 681845720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_rf_bignum_intg_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
5.otbn_rf_bignum_intg_err.3532376914
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_rf_bignum_intg_err/latest/run.log
UVM_FATAL @ 9246656 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_rf_bignum_intg_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 9246656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:495) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 1 failures:
5.otbn_sw_errs_fatal_chk.2275073934
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_sw_errs_fatal_chk/latest/run.log
UVM_FATAL @ 54508866 ps: (otbn_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 400 cycles ago and we still don't think it should have done.
UVM_INFO @ 54508866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
41.otbn_escalate.188956912
Line 261, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/41.otbn_escalate/latest/run.log
UVM_FATAL @ 5921171 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
UVM_INFO @ 5921171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
79.otbn_single.3225582854
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/79.otbn_single/latest/run.log
UVM_FATAL @ 34582569 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 34582569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---