OTBN Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: c06cc3921

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2869101736

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 8.000s 44.081us 1 1 100.00
V1 single_binary otbn_single 1.900m 528.732us 92 100 92.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 17.931us 5 5 100.00
V1 csr_rw otbn_csr_rw 6.000s 43.073us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 9.000s 97.655us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 43.099us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 10.000s 34.886us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 6.000s 43.073us 20 20 100.00
otbn_csr_aliasing 4.000s 43.099us 5 5 100.00
V1 mem_walk otbn_mem_walk 30.000s 765.082us 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 15.000s 1.290ms 5 5 100.00
V1 TOTAL 158 166 95.18
V2 reset_recovery otbn_reset 55.000s 259.245us 9 10 90.00
V2 multi_error otbn_multi_err 1.567m 329.954us 1 1 100.00
V2 back_to_back otbn_multi 10.400m 12.341ms 9 10 90.00
V2 stress_all otbn_stress_all 1.050m 230.325us 7 10 70.00
V2 lc_escalation otbn_escalate 35.000s 134.990us 44 60 73.33
V2 zero_state_err_urnd otbn_zero_state_err_urnd 9.000s 151.063us 5 5 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 14.000s 161.615us 10 10 100.00
V2 alert_test otbn_alert_test 9.000s 31.265us 50 50 100.00
V2 intr_test otbn_intr_test 9.000s 35.295us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 11.000s 117.781us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 11.000s 117.781us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 17.931us 5 5 100.00
otbn_csr_rw 6.000s 43.073us 20 20 100.00
otbn_csr_aliasing 4.000s 43.099us 5 5 100.00
otbn_same_csr_outstanding 7.000s 35.281us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 17.931us 5 5 100.00
otbn_csr_rw 6.000s 43.073us 20 20 100.00
otbn_csr_aliasing 4.000s 43.099us 5 5 100.00
otbn_same_csr_outstanding 7.000s 35.281us 20 20 100.00
V2 TOTAL 225 246 91.46
V2S mem_integrity otbn_imem_err 11.000s 33.317us 10 10 100.00
otbn_dmem_err 17.000s 189.694us 15 15 100.00
V2S internal_integrity otbn_alu_bignum_mod_err 10.000s 55.605us 4 5 80.00
otbn_controller_ispr_rdata_err 9.000s 29.248us 5 5 100.00
otbn_mac_bignum_acc_err 9.000s 146.771us 5 5 100.00
otbn_urnd_err 7.000s 47.875us 2 2 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 8.000s 21.503us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 7.000s 21.766us 2 2 100.00
V2S tl_intg_err otbn_sec_cm 4.167m 6.876ms 3 5 60.00
otbn_tl_intg_err 28.000s 199.430us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 39.000s 233.400us 20 20 100.00
V2S prim_fsm_check otbn_sec_cm 4.167m 6.876ms 3 5 60.00
V2S prim_count_check otbn_sec_cm 4.167m 6.876ms 3 5 60.00
V2S sec_cm_mem_scramble otbn_smoke 8.000s 44.081us 1 1 100.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 17.000s 189.694us 15 15 100.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 11.000s 33.317us 10 10 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 28.000s 199.430us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 35.000s 134.990us 44 60 73.33
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 11.000s 33.317us 10 10 100.00
otbn_dmem_err 17.000s 189.694us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 151.063us 5 5 100.00
otbn_illegal_mem_acc 8.000s 21.503us 5 5 100.00
otbn_sec_cm 4.167m 6.876ms 3 5 60.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.167m 6.876ms 3 5 60.00
V2S sec_cm_scramble_key_sideload otbn_single 1.900m 528.732us 92 100 92.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 11.000s 33.317us 10 10 100.00
otbn_dmem_err 17.000s 189.694us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 151.063us 5 5 100.00
otbn_illegal_mem_acc 8.000s 21.503us 5 5 100.00
otbn_sec_cm 4.167m 6.876ms 3 5 60.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.167m 6.876ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 35.000s 134.990us 44 60 73.33
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 11.000s 33.317us 10 10 100.00
otbn_dmem_err 17.000s 189.694us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 151.063us 5 5 100.00
otbn_illegal_mem_acc 8.000s 21.503us 5 5 100.00
otbn_sec_cm 4.167m 6.876ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.167m 6.876ms 3 5 60.00
V2S sec_cm_data_reg_sw_sca otbn_single 1.900m 528.732us 92 100 92.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 9.000s 21.762us 10 12 83.33
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 9.000s 113.587us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 43.000s 1.659ms 5 5 100.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 43.000s 1.659ms 5 5 100.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 9.000s 86.085us 8 10 80.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.167m 6.876ms 3 5 60.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.167m 6.876ms 3 5 60.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 11.000s 34.754us 9 10 90.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.167m 6.876ms 3 5 60.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.167m 6.876ms 3 5 60.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 13.000s 44.312us 4 5 80.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 13.000s 44.312us 4 5 80.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 13.000s 30.297us 6 7 85.71
V2S sec_cm_data_mem_sec_wipe otbn_single 1.900m 528.732us 92 100 92.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 1.900m 528.732us 92 100 92.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 1.900m 528.732us 92 100 92.00
V2S sec_cm_write_mem_integrity otbn_multi 10.400m 12.341ms 9 10 90.00
V2S sec_cm_ctrl_flow_count otbn_single 1.900m 528.732us 92 100 92.00
V2S sec_cm_ctrl_flow_sca otbn_single 1.900m 528.732us 92 100 92.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 17.000s 141.600us 5 5 100.00
V2S sec_cm_key_sideload otbn_single 1.900m 528.732us 92 100 92.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.167m 6.876ms 3 5 60.00
V2S TOTAL 143 153 93.46
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 22.400m 18.657ms 7 10 70.00
V3 TOTAL 7 10 70.00
TOTAL 533 575 92.70

Testplan Progress

Items Total Written Passing Progress
V1 9 9 8 88.89
V2 11 11 7 63.64
V2S 19 19 12 63.16
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.71 99.49 94.03 99.61 91.07 92.87 97.44 91.28 99.16

Failure Buckets

Past Results