OTP_CTRL Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.160s	240.500us	1	1	100.00
V1	smoke	otp_ctrl_smoke	10.480s	3.880ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.110s	141.847us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.980s	600.067us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.780s	3.041ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	3.810s	235.823us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.290s	323.254us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.980s	600.067us	20	20	100.00
		otp_ctrl_csr_aliasing	3.810s	235.823us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.370s	78.366us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.360s	131.218us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.830s	1.257ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.690s	3.058ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	29.790s	13.269ms	10	10	100.00
		otp_ctrl_check_fail	31.500s	13.800ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	11.640s	3.964ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	46.120s	5.172ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	37.480s	2.246ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	27.670s	9.531ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	15.860s	5.433ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	22.740s	8.118ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	43.720s	8.868ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	26.010s	2.728ms	49	50	98.00
V2	stress_all	otp_ctrl_stress_all	4.297m	86.831ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.940s	527.377us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.110s	264.479us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.930s	2.377ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.930s	2.377ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.110s	141.847us	5	5	100.00
		otp_ctrl_csr_rw	1.980s	600.067us	20	20	100.00
		otp_ctrl_csr_aliasing	3.810s	235.823us	5	5	100.00
		otp_ctrl_same_csr_outstanding	2.860s	113.948us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.110s	141.847us	5	5	100.00
		otp_ctrl_csr_rw	1.980s	600.067us	20	20	100.00
		otp_ctrl_csr_aliasing	3.810s	235.823us	5	5	100.00
		otp_ctrl_same_csr_outstanding	2.860s	113.948us	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
		otp_ctrl_tl_intg_err	40.530s	18.249ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	40.530s	18.249ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	10.480s	3.880ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	10.480s	3.880ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	15.860s	5.433ms	200	200	100.00
		otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	15.860s	5.433ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	15.860s	5.433ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	15.860s	5.433ms	200	200	100.00
		otp_ctrl_macro_errs	43.720s	8.868ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	15.860s	5.433ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	15.860s	5.433ms	200	200	100.00
		otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	15.860s	5.433ms	200	200	100.00
		otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	15.860s	5.433ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	15.860s	5.433ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	15.860s	5.433ms	200	200	100.00
		otp_ctrl_macro_errs	43.720s	8.868ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	15.860s	5.433ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	15.860s	5.433ms	200	200	100.00
		otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.690s	3.058ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	31.500s	13.800ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	46.120s	5.172ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	46.120s	5.172ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	46.120s	5.172ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	46.120s	5.172ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	46.120s	5.172ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	10.480s	3.880ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	46.120s	5.172ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	10.480s	3.880ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.514m	139.590ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	11.640s	3.964ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	10.480s	3.880ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	10.480s	3.880ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	43.720s	8.868ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.040s	5.909ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.857h	771.498ms	92	100	92.00
V3		TOTAL			93	101	92.08
		TOTAL			1334	1343	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.16	92.59	91.11	92.20	91.27	93.24	96.53	95.19

Failure Buckets

Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 29.otp_ctrl_stress_all_with_rand_reset.2271796038
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:14d87dc6-64cd-4d83-bed3-2247cb1208e0
```
  - 32.otp_ctrl_stress_all_with_rand_reset.2471122347
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:30da6f2d-b85f-4df9-89d7-7db1d003476b
```
  - ... and 4 more failures.
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 7.otp_ctrl_stress_all_with_rand_reset.746197965
    Line 337, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 695066787492 ps: (otp_ctrl_if.sv:262) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 695066787492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 25.otp_ctrl_stress_all_with_rand_reset.5695861
    Line 259, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 439368905 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 439368905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1347) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@58544) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_test_access has 1 failures.

46.otp_ctrl_test_access.3286617768
Line 246, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest/run.log

  UVM_ERROR @ 1378997871 ps: (otp_ctrl_scoreboard.sv:1347) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@58544) { a_addr: 'hc319c1a8  a_data: 'h8f175be4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h64  a_opcode: 'h1  a_user: 'h27e29  d_param: 'h0  d_source: 'h64  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 1378997871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---