OTP_CTRL Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.820s	243.662us	1	1	100.00
V1	smoke	otp_ctrl_smoke	38.830s	4.466ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.130s	1.465ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.870s	616.893us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.190s	839.823us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	4.500s	1.720ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.720s	423.909us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.870s	616.893us	20	20	100.00
		otp_ctrl_csr_aliasing	4.500s	1.720ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.780s	513.627us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.890s	523.737us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.190s	1.477ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.550s	2.886ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	26.370s	1.346ms	10	10	100.00
		otp_ctrl_check_fail	37.600s	8.098ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	10.330s	4.491ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	59.810s	7.286ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	37.320s	14.455ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	34.360s	11.371ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	12.970s	6.441ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	17.710s	6.063ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	39.470s	14.472ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.241m	16.419ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	3.513m	27.314ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.990s	547.977us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	5.990s	738.893us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.450s	253.016us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.450s	253.016us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.130s	1.465ms	5	5	100.00
		otp_ctrl_csr_rw	1.870s	616.893us	20	20	100.00
		otp_ctrl_csr_aliasing	4.500s	1.720ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.880s	1.824ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.130s	1.465ms	5	5	100.00
		otp_ctrl_csr_rw	1.870s	616.893us	20	20	100.00
		otp_ctrl_csr_aliasing	4.500s	1.720ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.880s	1.824ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
		otp_ctrl_tl_intg_err	39.150s	19.008ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	39.150s	19.008ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	38.830s	4.466ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	38.830s	4.466ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.970s	6.441ms	200	200	100.00
		otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.970s	6.441ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.970s	6.441ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.970s	6.441ms	200	200	100.00
		otp_ctrl_macro_errs	39.470s	14.472ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.970s	6.441ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.970s	6.441ms	200	200	100.00
		otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.970s	6.441ms	200	200	100.00
		otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.970s	6.441ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.970s	6.441ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.970s	6.441ms	200	200	100.00
		otp_ctrl_macro_errs	39.470s	14.472ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.970s	6.441ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.970s	6.441ms	200	200	100.00
		otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.550s	2.886ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	37.600s	8.098ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	59.810s	7.286ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	59.810s	7.286ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	59.810s	7.286ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	59.810s	7.286ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	59.810s	7.286ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	38.830s	4.466ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	59.810s	7.286ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	38.830s	4.466ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.840m	143.642ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	10.330s	4.491ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	38.830s	4.466ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	38.830s	4.466ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	39.470s	14.472ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	11.740s	3.036ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.836h	541.212ms	90	100	90.00
V3		TOTAL			91	101	90.10
		TOTAL			1333	1343	99.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.16	92.63	91.11	92.13	91.27	93.29	96.53	95.19

Failure Buckets

Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.2532099596
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:da82a573-b369-44d5-a564-3ce0ff772ea9
```
  - 9.otp_ctrl_stress_all_with_rand_reset.902286334
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:6dec05bc-f1ba-4273-aca2-ec29f5721232
```
  - ... and 5 more failures.
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 4.otp_ctrl_stress_all_with_rand_reset.4239456369
    Line 434, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 251438701814 ps: (otp_ctrl_if.sv:262) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 251438701814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1347) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@39792402) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

77.otp_ctrl_stress_all_with_rand_reset.89385703
Line 1257, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/77.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 280112793036 ps: (otp_ctrl_scoreboard.sv:1347) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@39792402) { a_addr: 'h52c3ff04  a_data: 'hc79dc3e6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'he3  a_opcode: 'h1  a_user: 'h27c4d  d_param: 'h0  d_source: 'he3  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 280112793036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1347) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@207224) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

98.otp_ctrl_stress_all_with_rand_reset.182506762
Line 252, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4839803832 ps: (otp_ctrl_scoreboard.sv:1347) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@207224) { a_addr: 'h9ffc0688  a_data: 'h5a469d9e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4e  a_opcode: 'h1  a_user: 'h244d9  d_param: 'h0  d_source: 'h4e  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 4839803832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---