OTP_CTRL Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up otp_ctrl_wake_up 1.740s 67.915us 1 1 100.00
V1 smoke otp_ctrl_smoke 12.290s 5.384ms 50 50 100.00
V1 csr_hw_reset otp_ctrl_csr_hw_reset 2.490s 186.908us 5 5 100.00
V1 csr_rw otp_ctrl_csr_rw 2.360s 631.744us 20 20 100.00
V1 csr_bit_bash otp_ctrl_csr_bit_bash 9.070s 433.398us 5 5 100.00
V1 csr_aliasing otp_ctrl_csr_aliasing 4.900s 2.032ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset otp_ctrl_csr_mem_rw_with_rand_reset 3.240s 430.580us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr otp_ctrl_csr_rw 2.360s 631.744us 20 20 100.00
otp_ctrl_csr_aliasing 4.900s 2.032ms 5 5 100.00
V1 mem_walk otp_ctrl_mem_walk 1.860s 539.270us 5 5 100.00
V1 mem_partial_access otp_ctrl_mem_partial_access 1.820s 520.105us 5 5 100.00
V1 TOTAL 115 116 99.14
V2 dai_access_partition_walk otp_ctrl_partition_walk 19.650s 1.255ms 1 1 100.00
V2 init_fail otp_ctrl_init_fail 8.700s 3.396ms 300 300 100.00
V2 partition_check otp_ctrl_background_chks 22.620s 7.781ms 10 10 100.00
otp_ctrl_check_fail 52.640s 6.717ms 50 50 100.00
V2 regwen_during_otp_init otp_ctrl_regwen 9.780s 3.559ms 50 50 100.00
V2 partition_lock otp_ctrl_dai_lock 35.720s 9.780ms 50 50 100.00
V2 interface_key_check otp_ctrl_parallel_key_req 33.190s 10.599ms 50 50 100.00
V2 lc_interactions otp_ctrl_parallel_lc_req 27.740s 9.732ms 50 50 100.00
otp_ctrl_parallel_lc_esc 12.710s 4.468ms 200 200 100.00
V2 otp_dai_errors otp_ctrl_dai_errs 23.800s 8.152ms 50 50 100.00
V2 otp_macro_errors otp_ctrl_macro_errs 59.140s 6.512ms 50 50 100.00
V2 test_access otp_ctrl_test_access 27.110s 6.935ms 49 50 98.00
V2 stress_all otp_ctrl_stress_all 3.490m 28.437ms 48 50 96.00
V2 intr_test otp_ctrl_intr_test 1.800s 525.699us 50 50 100.00
V2 alert_test otp_ctrl_alert_test 2.560s 785.853us 50 50 100.00
V2 tl_d_oob_addr_access otp_ctrl_tl_errors 6.470s 305.801us 20 20 100.00
V2 tl_d_illegal_access otp_ctrl_tl_errors 6.470s 305.801us 20 20 100.00
V2 tl_d_outstanding_access otp_ctrl_csr_hw_reset 2.490s 186.908us 5 5 100.00
otp_ctrl_csr_rw 2.360s 631.744us 20 20 100.00
otp_ctrl_csr_aliasing 4.900s 2.032ms 5 5 100.00
otp_ctrl_same_csr_outstanding 3.540s 479.440us 20 20 100.00
V2 tl_d_partial_access otp_ctrl_csr_hw_reset 2.490s 186.908us 5 5 100.00
otp_ctrl_csr_rw 2.360s 631.744us 20 20 100.00
otp_ctrl_csr_aliasing 4.900s 2.032ms 5 5 100.00
otp_ctrl_same_csr_outstanding 3.540s 479.440us 20 20 100.00
V2 TOTAL 1098 1101 99.73
V2S sec_cm_additional_check otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S tl_intg_err otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
otp_ctrl_tl_intg_err 28.830s 18.896ms 20 20 100.00
V2S prim_count_check otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S prim_fsm_check otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_bus_integrity otp_ctrl_tl_intg_err 28.830s 18.896ms 20 20 100.00
V2S sec_cm_secret_mem_scramble otp_ctrl_smoke 12.290s 5.384ms 50 50 100.00
V2S sec_cm_part_mem_digest otp_ctrl_smoke 12.290s 5.384ms 50 50 100.00
V2S sec_cm_dai_fsm_sparse otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_kdi_fsm_sparse otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_lci_fsm_sparse otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_part_fsm_sparse otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_scrmbl_fsm_sparse otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_timer_fsm_sparse otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_dai_ctr_redun otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_kdi_seed_ctr_redun otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_kdi_entropy_ctr_redun otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_lci_ctr_redun otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_part_ctr_redun otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_scrmbl_ctr_redun otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_timer_integ_ctr_redun otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_timer_cnsty_ctr_redun otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_timer_lfsr_redun otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_dai_fsm_local_esc otp_ctrl_parallel_lc_esc 12.710s 4.468ms 200 200 100.00
otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_lci_fsm_local_esc otp_ctrl_parallel_lc_esc 12.710s 4.468ms 200 200 100.00
V2S sec_cm_kdi_fsm_local_esc otp_ctrl_parallel_lc_esc 12.710s 4.468ms 200 200 100.00
V2S sec_cm_part_fsm_local_esc otp_ctrl_parallel_lc_esc 12.710s 4.468ms 200 200 100.00
otp_ctrl_macro_errs 59.140s 6.512ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_local_esc otp_ctrl_parallel_lc_esc 12.710s 4.468ms 200 200 100.00
V2S sec_cm_timer_fsm_local_esc otp_ctrl_parallel_lc_esc 12.710s 4.468ms 200 200 100.00
otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_dai_fsm_global_esc otp_ctrl_parallel_lc_esc 12.710s 4.468ms 200 200 100.00
otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_lci_fsm_global_esc otp_ctrl_parallel_lc_esc 12.710s 4.468ms 200 200 100.00
V2S sec_cm_kdi_fsm_global_esc otp_ctrl_parallel_lc_esc 12.710s 4.468ms 200 200 100.00
V2S sec_cm_part_fsm_global_esc otp_ctrl_parallel_lc_esc 12.710s 4.468ms 200 200 100.00
otp_ctrl_macro_errs 59.140s 6.512ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_global_esc otp_ctrl_parallel_lc_esc 12.710s 4.468ms 200 200 100.00
V2S sec_cm_timer_fsm_global_esc otp_ctrl_parallel_lc_esc 12.710s 4.468ms 200 200 100.00
otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_part_data_reg_integrity otp_ctrl_init_fail 8.700s 3.396ms 300 300 100.00
V2S sec_cm_part_data_reg_bkgn_chk otp_ctrl_check_fail 52.640s 6.717ms 50 50 100.00
V2S sec_cm_part_mem_regren otp_ctrl_dai_lock 35.720s 9.780ms 50 50 100.00
V2S sec_cm_part_mem_sw_unreadable otp_ctrl_dai_lock 35.720s 9.780ms 50 50 100.00
V2S sec_cm_part_mem_sw_unwritable otp_ctrl_dai_lock 35.720s 9.780ms 50 50 100.00
V2S sec_cm_lc_part_mem_sw_noaccess otp_ctrl_dai_lock 35.720s 9.780ms 50 50 100.00
V2S sec_cm_access_ctrl_mubi otp_ctrl_dai_lock 35.720s 9.780ms 50 50 100.00
V2S sec_cm_token_valid_ctrl_mubi otp_ctrl_smoke 12.290s 5.384ms 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi otp_ctrl_dai_lock 35.720s 9.780ms 50 50 100.00
V2S sec_cm_test_bus_lc_gated otp_ctrl_smoke 12.290s 5.384ms 50 50 100.00
V2S sec_cm_test_tl_lc_gate_fsm_sparse otp_ctrl_sec_cm 5.139m 138.792ms 5 5 100.00
V2S sec_cm_direct_access_config_regwen otp_ctrl_regwen 9.780s 3.559ms 50 50 100.00
V2S sec_cm_check_trigger_config_regwen otp_ctrl_smoke 12.290s 5.384ms 50 50 100.00
V2S sec_cm_check_config_regwen otp_ctrl_smoke 12.290s 5.384ms 50 50 100.00
V2S sec_cm_macro_mem_integrity otp_ctrl_macro_errs 59.140s 6.512ms 50 50 100.00
V2S TOTAL 25 25 100.00
V3 otp_ctrl_low_freq_read otp_ctrl_low_freq_read 11.970s 3.038ms 1 1 100.00
V3 stress_all_with_rand_reset otp_ctrl_stress_all_with_rand_reset 2.997h 1.378s 92 100 92.00
V3 TOTAL 93 101 92.08
TOTAL 1331 1343 99.11

Testplan Progress

Items Total Written Passing Progress
V1 9 9 8 88.89
V2 17 17 15 88.24
V2S 2 2 2 100.00
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.25 92.57 91.14 92.16 91.83 93.24 96.53 95.27

Failure Buckets

Past Results