877a77116
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | wake_up | otp_ctrl_wake_up | 1.740s | 67.915us | 1 | 1 | 100.00 |
V1 | smoke | otp_ctrl_smoke | 12.290s | 5.384ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | otp_ctrl_csr_hw_reset | 2.490s | 186.908us | 5 | 5 | 100.00 |
V1 | csr_rw | otp_ctrl_csr_rw | 2.360s | 631.744us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | otp_ctrl_csr_bit_bash | 9.070s | 433.398us | 5 | 5 | 100.00 |
V1 | csr_aliasing | otp_ctrl_csr_aliasing | 4.900s | 2.032ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | otp_ctrl_csr_mem_rw_with_rand_reset | 3.240s | 430.580us | 19 | 20 | 95.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | otp_ctrl_csr_rw | 2.360s | 631.744us | 20 | 20 | 100.00 |
otp_ctrl_csr_aliasing | 4.900s | 2.032ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | otp_ctrl_mem_walk | 1.860s | 539.270us | 5 | 5 | 100.00 |
V1 | mem_partial_access | otp_ctrl_mem_partial_access | 1.820s | 520.105us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 116 | 99.14 | |||
V2 | dai_access_partition_walk | otp_ctrl_partition_walk | 19.650s | 1.255ms | 1 | 1 | 100.00 |
V2 | init_fail | otp_ctrl_init_fail | 8.700s | 3.396ms | 300 | 300 | 100.00 |
V2 | partition_check | otp_ctrl_background_chks | 22.620s | 7.781ms | 10 | 10 | 100.00 |
otp_ctrl_check_fail | 52.640s | 6.717ms | 50 | 50 | 100.00 | ||
V2 | regwen_during_otp_init | otp_ctrl_regwen | 9.780s | 3.559ms | 50 | 50 | 100.00 |
V2 | partition_lock | otp_ctrl_dai_lock | 35.720s | 9.780ms | 50 | 50 | 100.00 |
V2 | interface_key_check | otp_ctrl_parallel_key_req | 33.190s | 10.599ms | 50 | 50 | 100.00 |
V2 | lc_interactions | otp_ctrl_parallel_lc_req | 27.740s | 9.732ms | 50 | 50 | 100.00 |
otp_ctrl_parallel_lc_esc | 12.710s | 4.468ms | 200 | 200 | 100.00 | ||
V2 | otp_dai_errors | otp_ctrl_dai_errs | 23.800s | 8.152ms | 50 | 50 | 100.00 |
V2 | otp_macro_errors | otp_ctrl_macro_errs | 59.140s | 6.512ms | 50 | 50 | 100.00 |
V2 | test_access | otp_ctrl_test_access | 27.110s | 6.935ms | 49 | 50 | 98.00 |
V2 | stress_all | otp_ctrl_stress_all | 3.490m | 28.437ms | 48 | 50 | 96.00 |
V2 | intr_test | otp_ctrl_intr_test | 1.800s | 525.699us | 50 | 50 | 100.00 |
V2 | alert_test | otp_ctrl_alert_test | 2.560s | 785.853us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | otp_ctrl_tl_errors | 6.470s | 305.801us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | otp_ctrl_tl_errors | 6.470s | 305.801us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | otp_ctrl_csr_hw_reset | 2.490s | 186.908us | 5 | 5 | 100.00 |
otp_ctrl_csr_rw | 2.360s | 631.744us | 20 | 20 | 100.00 | ||
otp_ctrl_csr_aliasing | 4.900s | 2.032ms | 5 | 5 | 100.00 | ||
otp_ctrl_same_csr_outstanding | 3.540s | 479.440us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | otp_ctrl_csr_hw_reset | 2.490s | 186.908us | 5 | 5 | 100.00 |
otp_ctrl_csr_rw | 2.360s | 631.744us | 20 | 20 | 100.00 | ||
otp_ctrl_csr_aliasing | 4.900s | 2.032ms | 5 | 5 | 100.00 | ||
otp_ctrl_same_csr_outstanding | 3.540s | 479.440us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1098 | 1101 | 99.73 | |||
V2S | sec_cm_additional_check | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
otp_ctrl_tl_intg_err | 28.830s | 18.896ms | 20 | 20 | 100.00 | ||
V2S | prim_count_check | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | otp_ctrl_tl_intg_err | 28.830s | 18.896ms | 20 | 20 | 100.00 |
V2S | sec_cm_secret_mem_scramble | otp_ctrl_smoke | 12.290s | 5.384ms | 50 | 50 | 100.00 |
V2S | sec_cm_part_mem_digest | otp_ctrl_smoke | 12.290s | 5.384ms | 50 | 50 | 100.00 |
V2S | sec_cm_dai_fsm_sparse | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_kdi_fsm_sparse | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_lci_fsm_sparse | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_part_fsm_sparse | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_scrmbl_fsm_sparse | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_timer_fsm_sparse | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_dai_ctr_redun | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_kdi_seed_ctr_redun | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_kdi_entropy_ctr_redun | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_lci_ctr_redun | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_part_ctr_redun | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_scrmbl_ctr_redun | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_timer_integ_ctr_redun | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_timer_cnsty_ctr_redun | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_timer_lfsr_redun | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_dai_fsm_local_esc | otp_ctrl_parallel_lc_esc | 12.710s | 4.468ms | 200 | 200 | 100.00 |
otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 | ||
V2S | sec_cm_lci_fsm_local_esc | otp_ctrl_parallel_lc_esc | 12.710s | 4.468ms | 200 | 200 | 100.00 |
V2S | sec_cm_kdi_fsm_local_esc | otp_ctrl_parallel_lc_esc | 12.710s | 4.468ms | 200 | 200 | 100.00 |
V2S | sec_cm_part_fsm_local_esc | otp_ctrl_parallel_lc_esc | 12.710s | 4.468ms | 200 | 200 | 100.00 |
otp_ctrl_macro_errs | 59.140s | 6.512ms | 50 | 50 | 100.00 | ||
V2S | sec_cm_scrmbl_fsm_local_esc | otp_ctrl_parallel_lc_esc | 12.710s | 4.468ms | 200 | 200 | 100.00 |
V2S | sec_cm_timer_fsm_local_esc | otp_ctrl_parallel_lc_esc | 12.710s | 4.468ms | 200 | 200 | 100.00 |
otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 | ||
V2S | sec_cm_dai_fsm_global_esc | otp_ctrl_parallel_lc_esc | 12.710s | 4.468ms | 200 | 200 | 100.00 |
otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 | ||
V2S | sec_cm_lci_fsm_global_esc | otp_ctrl_parallel_lc_esc | 12.710s | 4.468ms | 200 | 200 | 100.00 |
V2S | sec_cm_kdi_fsm_global_esc | otp_ctrl_parallel_lc_esc | 12.710s | 4.468ms | 200 | 200 | 100.00 |
V2S | sec_cm_part_fsm_global_esc | otp_ctrl_parallel_lc_esc | 12.710s | 4.468ms | 200 | 200 | 100.00 |
otp_ctrl_macro_errs | 59.140s | 6.512ms | 50 | 50 | 100.00 | ||
V2S | sec_cm_scrmbl_fsm_global_esc | otp_ctrl_parallel_lc_esc | 12.710s | 4.468ms | 200 | 200 | 100.00 |
V2S | sec_cm_timer_fsm_global_esc | otp_ctrl_parallel_lc_esc | 12.710s | 4.468ms | 200 | 200 | 100.00 |
otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 | ||
V2S | sec_cm_part_data_reg_integrity | otp_ctrl_init_fail | 8.700s | 3.396ms | 300 | 300 | 100.00 |
V2S | sec_cm_part_data_reg_bkgn_chk | otp_ctrl_check_fail | 52.640s | 6.717ms | 50 | 50 | 100.00 |
V2S | sec_cm_part_mem_regren | otp_ctrl_dai_lock | 35.720s | 9.780ms | 50 | 50 | 100.00 |
V2S | sec_cm_part_mem_sw_unreadable | otp_ctrl_dai_lock | 35.720s | 9.780ms | 50 | 50 | 100.00 |
V2S | sec_cm_part_mem_sw_unwritable | otp_ctrl_dai_lock | 35.720s | 9.780ms | 50 | 50 | 100.00 |
V2S | sec_cm_lc_part_mem_sw_noaccess | otp_ctrl_dai_lock | 35.720s | 9.780ms | 50 | 50 | 100.00 |
V2S | sec_cm_access_ctrl_mubi | otp_ctrl_dai_lock | 35.720s | 9.780ms | 50 | 50 | 100.00 |
V2S | sec_cm_token_valid_ctrl_mubi | otp_ctrl_smoke | 12.290s | 5.384ms | 50 | 50 | 100.00 |
V2S | sec_cm_lc_ctrl_intersig_mubi | otp_ctrl_dai_lock | 35.720s | 9.780ms | 50 | 50 | 100.00 |
V2S | sec_cm_test_bus_lc_gated | otp_ctrl_smoke | 12.290s | 5.384ms | 50 | 50 | 100.00 |
V2S | sec_cm_test_tl_lc_gate_fsm_sparse | otp_ctrl_sec_cm | 5.139m | 138.792ms | 5 | 5 | 100.00 |
V2S | sec_cm_direct_access_config_regwen | otp_ctrl_regwen | 9.780s | 3.559ms | 50 | 50 | 100.00 |
V2S | sec_cm_check_trigger_config_regwen | otp_ctrl_smoke | 12.290s | 5.384ms | 50 | 50 | 100.00 |
V2S | sec_cm_check_config_regwen | otp_ctrl_smoke | 12.290s | 5.384ms | 50 | 50 | 100.00 |
V2S | sec_cm_macro_mem_integrity | otp_ctrl_macro_errs | 59.140s | 6.512ms | 50 | 50 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | otp_ctrl_low_freq_read | otp_ctrl_low_freq_read | 11.970s | 3.038ms | 1 | 1 | 100.00 |
V3 | stress_all_with_rand_reset | otp_ctrl_stress_all_with_rand_reset | 2.997h | 1.378s | 92 | 100 | 92.00 |
V3 | TOTAL | 93 | 101 | 92.08 | |||
TOTAL | 1331 | 1343 | 99.11 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 9 | 9 | 8 | 88.89 |
V2 | 17 | 17 | 15 | 88.24 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 2 | 2 | 1 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
93.25 | 92.57 | 91.14 | 92.16 | 91.83 | 93.24 | 96.53 | 95.27 |
Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 4 failures:
43.otp_ctrl_stress_all_with_rand_reset.826030887
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:49e95fed-4c72-4382-8b8f-78871a5796b3
44.otp_ctrl_stress_all_with_rand_reset.3611055017
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:80e3efeb-b681-46d7-84cb-9db27526672b
... and 2 more failures.
UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*])
has 3 failures:
2.otp_ctrl_stress_all_with_rand_reset.161674374
Line 553, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21110383256 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 21110383256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.otp_ctrl_stress_all_with_rand_reset.3090967914
Line 369, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1781912173694 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1781912173694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '(cio_test_en_o == *)'
has 1 failures:
15.otp_ctrl_csr_mem_rw_with_rand_reset.3082286358
Line 251, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
Offending '(cio_test_en_o == 0)'
UVM_ERROR @ 51925396 ps: (otp_ctrl_if.sv:262) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 51925396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1347) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@70360) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
has 1 failures:
31.otp_ctrl_test_access.1777384871
Line 248, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest/run.log
UVM_ERROR @ 856937968 ps: (otp_ctrl_scoreboard.sv:1347) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@70360) { a_addr: 'haeb9f938 a_data: 'h384eb1b0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hdd a_opcode: 'h0 a_user: 'h278b2 d_param: 'h0 d_source: 'hdd d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, access gated by lc_dft_en_i
UVM_INFO @ 856937968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1347) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1299691) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
has 1 failures:
37.otp_ctrl_stress_all.3072057260
Line 340, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest/run.log
UVM_ERROR @ 17177346026 ps: (otp_ctrl_scoreboard.sv:1347) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1299691) { a_addr: 'hb0dfd220 a_data: 'h11f24840 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h49 a_opcode: 'h0 a_user: 'h25202 d_param: 'h0 d_source: 'h49 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, access gated by lc_dft_en_i
UVM_INFO @ 17177346026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1347) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@924737) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
has 1 failures:
39.otp_ctrl_stress_all.1715575335
Line 285, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest/run.log
UVM_ERROR @ 2576070547 ps: (otp_ctrl_scoreboard.sv:1347) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@924737) { a_addr: 'hadd26a3c a_data: 'h26469e2b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h81 a_opcode: 'h0 a_user: 'h2622b d_param: 'h0 d_source: 'h81 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, access gated by lc_dft_en_i
UVM_INFO @ 2576070547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1347) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@15544139) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
has 1 failures:
48.otp_ctrl_stress_all_with_rand_reset.75912827
Line 823, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 104250333292 ps: (otp_ctrl_scoreboard.sv:1347) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@15544139) { a_addr: 'hbc1bdcb0 a_data: 'h6fa66795 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hb3 a_opcode: 'h1 a_user: 'h246ba d_param: 'h0 d_source: 'hb3 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, access gated by lc_dft_en_i
UVM_INFO @ 104250333292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---