Group : tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
91.67 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv


Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 1 11 91.67


Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
flash_addr_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
flash_addr_req_during_lc_esc 2 1 1 50.00 100 1 1 0
flash_addr_req_during_otbn_req 2 0 2 100.00 100 1 1 2
flash_addr_req_during_otp_idle 2 0 2 100.00 100 1 1 2
flash_addr_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
flash_addr_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable flash_addr_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10805 1 T18 171 T20 9 T21 6
auto[1] 665 1 T18 23 T20 1 T22 1


Summary for Variable flash_addr_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for flash_addr_req_during_lc_esc

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
lc_esc_on 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 11470 1 T18 194 T20 10 T21 6


Summary for Variable flash_addr_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10880 1 T18 186 T20 10 T21 5
auto[1] 590 1 T18 8 T21 1 T36 1


Summary for Variable flash_addr_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1735 1 T18 97 T35 5 T38 5
auto[1] 9735 1 T18 97 T20 10 T21 6


Summary for Variable flash_addr_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11020 1 T18 194 T20 10 T21 5
auto[1] 450 1 T21 1 T36 1 T42 8


Summary for Variable flash_addr_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11360 1 T18 182 T20 10 T21 6
auto[1] 110 1 T18 12 T42 1 T44 1

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