Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.14	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	6	8	57.14

Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
lc_esc_during_flash_addr_req	2	1	1	50.00	100	1	1	2
lc_esc_during_flash_data_req	2	1	1	50.00	100	1	1	2
lc_esc_during_lc_otp_prog_req	2	1	1	50.00	100	1	1	2
lc_esc_during_otbn_req	2	1	1	50.00	100	1	1	2
lc_esc_during_otp_idle	2	1	1	50.00	100	1	1	2
lc_esc_during_sram_0_req	2	0	2	100.00	100	1	1	2
lc_esc_during_sram_1_req	2	1	1	50.00	100	1	1	2

Summary for Variable lc_esc_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for lc_esc_during_flash_addr_req

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

400

1

T49

2

T64

2

T65

2

---

Summary for Variable lc_esc_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for lc_esc_during_flash_data_req

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

400

1

T49

2

T64

2

T65

2

---

Summary for Variable lc_esc_during_lc_otp_prog_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for lc_esc_during_lc_otp_prog_req

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

400

1

T49

2

T64

2

T65

2

---

Summary for Variable lc_esc_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for lc_esc_during_otbn_req

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

400

1

T49

2

T64

2

T65

2

---

Summary for Variable lc_esc_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for lc_esc_during_otp_idle

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

400

1

T49

2

T64

2

T65

2

---

Summary for Variable lc_esc_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

200

1

T49

1

T64

1

T65

1

auto[1]

200

1

T49

1

T64

1

T65

1

---

Summary for Variable lc_esc_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for lc_esc_during_sram_1_req

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

400

1

T49

2

T64

2

T65

2