Group : tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
91.67 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv


Summary for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 1 11 91.67


Variables for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
otbn_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
otbn_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
otbn_req_during_lc_esc 2 1 1 50.00 100 1 1 0
otbn_req_during_otp_idle 2 0 2 100.00 100 1 1 2
otbn_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
otbn_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable otbn_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10210 1 T18 52 T20 10 T21 5
auto[1] 680 1 T18 26 T21 1 T36 1


Summary for Variable otbn_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10185 1 T18 47 T20 10 T21 5
auto[1] 705 1 T18 31 T21 1 T36 1


Summary for Variable otbn_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for otbn_req_during_lc_esc

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
lc_esc_on 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 10890 1 T18 78 T20 10 T21 6


Summary for Variable otbn_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1845 1 T18 39 T21 2 T35 9
auto[1] 9045 1 T18 39 T20 10 T21 4


Summary for Variable otbn_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10135 1 T18 77 T20 10 T21 4
auto[1] 755 1 T18 1 T21 2 T36 2


Summary for Variable otbn_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10880 1 T18 76 T20 10 T21 6
auto[1] 10 1 T18 2 T27 2 T28 2

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