Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
93.75 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 1 15 93.75


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
creator_sw_lock 2 0 2 100.00 100 1 1 2
hw_cfg_lock 2 0 2 100.00 100 1 1 2
lc_esc 2 1 1 50.00 100 1 1 2
owner_sw_lock 2 0 2 100.00 100 1 1 2
secret0_lock 2 0 2 100.00 100 1 1 2
secret1_lock 2 0 2 100.00 100 1 1 2
secret2_lock 2 0 2 100.00 100 1 1 2
vendor_sw_lock 2 0 2 100.00 100 1 1 2


Summary for Variable creator_sw_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for creator_sw_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9423 1 T29 2 T1 2 T11 2
auto[1] 6630 1 T20 9 T21 8 T22 9



Summary for Variable hw_cfg_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_cfg_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10073 1 T29 2 T1 2 T11 2
auto[1] 5980 1 T20 9 T21 8 T22 9



Summary for Variable lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for lc_esc

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 16053 1 T29 2 T1 2 T11 2



Summary for Variable owner_sw_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for owner_sw_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9573 1 T29 2 T1 2 T11 2
auto[1] 6480 1 T20 9 T21 8 T22 9



Summary for Variable secret0_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for secret0_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8603 1 T29 2 T1 2 T11 2
auto[1] 7450 1 T20 9 T21 8 T22 9



Summary for Variable secret1_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for secret1_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8123 1 T29 2 T1 2 T11 2
auto[1] 7930 1 T20 9 T21 8 T22 9



Summary for Variable secret2_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for secret2_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12103 1 T29 2 T1 2 T11 2
auto[1] 3950 1 T20 7 T21 5 T22 7



Summary for Variable vendor_sw_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for vendor_sw_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 15353 1 T29 2 T1 2 T11 2
auto[1] 700 1 T42 14 T44 14 T50 14

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