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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
85.25 91.02 88.86 82.89 67.89 91.20 94.19 80.68


Total test records in report: 1343
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T1251 /workspace/coverage/default/5.otp_ctrl_dai_errs.87638459216696150563345304926482481326704855653077190351990484447006187409679 Nov 22 01:50:10 PM PST 23 Nov 22 01:50:29 PM PST 23 390019183 ps
T1252 /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.46836440994632168606773354121943691528591729745507214055197369216751793232026 Nov 22 01:51:21 PM PST 23 Nov 22 01:51:27 PM PST 23 176929183 ps
T1253 /workspace/coverage/default/36.otp_ctrl_stress_all.52726462728527591027830061315122210334720703670936385920557001895395982522243 Nov 22 01:51:02 PM PST 23 Nov 22 01:53:24 PM PST 23 13240088340 ps
T1254 /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.103533327470115726603613692802852968569955358548097728032616648698548072056392 Nov 22 01:51:34 PM PST 23 Nov 22 01:51:43 PM PST 23 176929183 ps
T1255 /workspace/coverage/default/16.otp_ctrl_stress_all.81507626258113904370802275518992655453354539539239808107749373027837169354587 Nov 22 01:51:45 PM PST 23 Nov 22 01:54:00 PM PST 23 13240088340 ps
T1256 /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.98988677154418207006916950431913862458810420737684059555132193340586807738536 Nov 22 01:52:00 PM PST 23 Nov 22 01:52:06 PM PST 23 176929183 ps
T1257 /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.109698669390852772057359110153071802464202261339003944398570280340784198050852 Nov 22 01:51:59 PM PST 23 Nov 22 01:52:05 PM PST 23 176929183 ps
T1258 /workspace/coverage/default/35.otp_ctrl_smoke.87151914156551921522930061434260054450151093935047442659405896067370720493790 Nov 22 01:51:40 PM PST 23 Nov 22 01:51:48 PM PST 23 138839183 ps
T1259 /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.56286658230034452309979749965871905473652726697930377753242052414602797859811 Nov 22 01:50:44 PM PST 23 Nov 22 01:50:57 PM PST 23 486419183 ps
T1260 /workspace/coverage/default/46.otp_ctrl_dai_lock.56499424707499909664657928778956839340290773079057261473092293886284217694641 Nov 22 01:51:54 PM PST 23 Nov 22 01:52:07 PM PST 23 614979183 ps
T1261 /workspace/coverage/default/250.otp_ctrl_init_fail.3363240378567138188861693726455215111030888325923459293704709158222556722942 Nov 22 01:52:15 PM PST 23 Nov 22 01:52:21 PM PST 23 156689183 ps
T1262 /workspace/coverage/default/0.otp_ctrl_test_access.67219259183462050396357186875835159234534060745980877276456832785351346195510 Nov 22 01:50:02 PM PST 23 Nov 22 01:50:14 PM PST 23 549639183 ps
T1263 /workspace/coverage/default/35.otp_ctrl_stress_all.69525933667605539606915279758388594344811569873753741863028671254049412045054 Nov 22 01:51:36 PM PST 23 Nov 22 01:53:55 PM PST 23 13240088340 ps
T1264 /workspace/coverage/default/5.otp_ctrl_dai_lock.42838399364808019228770205897911117505498203771431967855054430193660613509614 Nov 22 01:50:21 PM PST 23 Nov 22 01:50:33 PM PST 23 614979183 ps
T1265 /workspace/coverage/default/41.otp_ctrl_init_fail.94642328645963530754806347078496407670262782534418802302694916963394323944019 Nov 22 01:51:01 PM PST 23 Nov 22 01:51:07 PM PST 23 156689183 ps
T1266 /workspace/coverage/default/13.otp_ctrl_regwen.99328489258777593216434883004074418402179118864654953330715339765803353856141 Nov 22 01:51:26 PM PST 23 Nov 22 01:51:33 PM PST 23 137469183 ps
T1267 /workspace/coverage/default/12.otp_ctrl_regwen.89097315677990768085506584092895143844900471594820908342181974103655385195557 Nov 22 01:51:04 PM PST 23 Nov 22 01:51:09 PM PST 23 137469183 ps
T1268 /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.93749023413170699253865420100605881151541094692537009601102397345482913691774 Nov 22 01:52:11 PM PST 23 Nov 22 01:52:18 PM PST 23 176929183 ps
T1269 /workspace/coverage/default/43.otp_ctrl_parallel_key_req.79396808979093157204691177977181026981519279240524583305515608595510747389893 Nov 22 01:51:01 PM PST 23 Nov 22 01:51:09 PM PST 23 346349183 ps
T1270 /workspace/coverage/default/220.otp_ctrl_init_fail.63728269503541330857957000743041283074817117738844755990349816582808663639516 Nov 22 01:52:08 PM PST 23 Nov 22 01:52:16 PM PST 23 156689183 ps
T1271 /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.32166220636671912034892518367594562700785544672202941424319039075444771187340 Nov 22 01:51:43 PM PST 23 Nov 22 01:51:52 PM PST 23 176929183 ps
T1272 /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.13904434945846419271999277662840780945114357128082570778329951717289897978969 Nov 22 01:51:32 PM PST 23 Nov 22 01:51:40 PM PST 23 176929183 ps
T1273 /workspace/coverage/default/178.otp_ctrl_init_fail.111038001584364778667546003122718287512774040611776498950293562294995657477380 Nov 22 01:52:07 PM PST 23 Nov 22 01:52:14 PM PST 23 156689183 ps
T1274 /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.10039997622270623880405894348380073632154133943980561960567910559900805852145 Nov 22 01:51:33 PM PST 23 Nov 22 01:51:41 PM PST 23 176929183 ps
T1275 /workspace/coverage/default/44.otp_ctrl_stress_all.80533581950871820272881682903153039312780375328093117719912850037493188318842 Nov 22 01:51:17 PM PST 23 Nov 22 01:53:24 PM PST 23 13240088340 ps
T1276 /workspace/coverage/default/267.otp_ctrl_init_fail.26290017376841484491795574732416120135827533115369367128163205434457435095237 Nov 22 01:52:25 PM PST 23 Nov 22 01:52:31 PM PST 23 156689183 ps
T1277 /workspace/coverage/default/38.otp_ctrl_init_fail.78643910011468849217772033417841637168328034353039623459499944117444808567989 Nov 22 01:51:06 PM PST 23 Nov 22 01:51:12 PM PST 23 156689183 ps
T1278 /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.34021484053105828552280112612841145852461394763190115269550369691694131741348 Nov 22 01:51:56 PM PST 23 Nov 22 02:24:00 PM PST 23 150268849183 ps
T1279 /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.83652561000297339454023212325534429782453124281309885168777627976583200893556 Nov 22 01:51:16 PM PST 23 Nov 22 02:24:03 PM PST 23 150268849183 ps
T1280 /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.106734869168611419139256024928144417597447383962954616673011438496367719248876 Nov 22 01:50:05 PM PST 23 Nov 22 02:22:54 PM PST 23 150268849183 ps
T1281 /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.107388464816301086784283907693688690804375112007099004992127358073046842293713 Nov 22 01:51:04 PM PST 23 Nov 22 01:51:10 PM PST 23 176929183 ps
T1282 /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.49291492339983829162709950914602071002012829004063684932610371400493102482032 Nov 22 01:50:48 PM PST 23 Nov 22 02:23:14 PM PST 23 150268849183 ps
T1283 /workspace/coverage/default/21.otp_ctrl_stress_all.91059141542727502016834834893694720008634471620942956893885528322608895434183 Nov 22 01:50:49 PM PST 23 Nov 22 01:52:57 PM PST 23 13240088340 ps
T1284 /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.9229439142950836172260643938422539642383896431796505058739504246127367038568 Nov 22 01:51:38 PM PST 23 Nov 22 01:51:47 PM PST 23 176929183 ps
T1285 /workspace/coverage/default/22.otp_ctrl_test_access.91327531699871076997609140779754638630167781243509325211312291492862924072152 Nov 22 01:50:50 PM PST 23 Nov 22 01:51:00 PM PST 23 549639183 ps
T1286 /workspace/coverage/default/3.otp_ctrl_dai_errs.14325108362639917134472458631916126596799388803500924868552838132933026281025 Nov 22 01:50:08 PM PST 23 Nov 22 01:50:25 PM PST 23 390019183 ps
T1287 /workspace/coverage/default/49.otp_ctrl_stress_all.51562302880067431264134642870044633473483912144665453641931887060957355871072 Nov 22 01:51:37 PM PST 23 Nov 22 01:53:56 PM PST 23 13240088340 ps
T1288 /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.56792630660990926514157865029674479644437375235779289087506604058859112272710 Nov 22 01:51:36 PM PST 23 Nov 22 01:51:44 PM PST 23 176929183 ps
T1289 /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.83200358541947443919680894721110766144632318217037754954672244606444443108637 Nov 22 01:51:01 PM PST 23 Nov 22 01:51:13 PM PST 23 486419183 ps
T1290 /workspace/coverage/default/22.otp_ctrl_macro_errs.21050488760525194219620988224894249030130226100578076554966040452684232557861 Nov 22 01:51:07 PM PST 23 Nov 22 01:51:28 PM PST 23 1137629183 ps
T1291 /workspace/coverage/default/42.otp_ctrl_smoke.113634430609008571851016618288450009020185959582317289464556592048002603423520 Nov 22 01:51:43 PM PST 23 Nov 22 01:51:50 PM PST 23 138839183 ps
T1292 /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.91093079801395318803652315189854729110028691152858110714288360952722065147897 Nov 22 01:51:09 PM PST 23 Nov 22 01:51:15 PM PST 23 176929183 ps
T1293 /workspace/coverage/default/20.otp_ctrl_check_fail.60068127858735748949420142578049786918255690211011923091273471986905076321357 Nov 22 01:50:42 PM PST 23 Nov 22 01:50:45 PM PST 23 111269183 ps
T1294 /workspace/coverage/default/23.otp_ctrl_parallel_key_req.113877902959881699498139191200968212995647567413836886807972839784443817197832 Nov 22 01:51:45 PM PST 23 Nov 22 01:51:56 PM PST 23 346349183 ps
T1295 /workspace/coverage/default/32.otp_ctrl_check_fail.109650527190819994860716315429622946737271622420068463292443175113068995894269 Nov 22 01:51:07 PM PST 23 Nov 22 01:51:12 PM PST 23 111269183 ps
T1296 /workspace/coverage/default/203.otp_ctrl_init_fail.50839178880346290765793704963332496371831560752828386095886437930723447151638 Nov 22 01:52:16 PM PST 23 Nov 22 01:52:24 PM PST 23 156689183 ps
T1297 /workspace/coverage/default/49.otp_ctrl_alert_test.21540931591536217630172951629482920590073507187839562082287212035717868712078 Nov 22 01:51:15 PM PST 23 Nov 22 01:51:19 PM PST 23 71069183 ps
T1298 /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.24275486246088109411244423926112766249262334927082519700226088318025898583286 Nov 22 01:51:48 PM PST 23 Nov 22 01:51:55 PM PST 23 176929183 ps
T1299 /workspace/coverage/default/44.otp_ctrl_dai_errs.33059761540842946135167654508890096903082678716239162113962254312757400486136 Nov 22 01:51:41 PM PST 23 Nov 22 01:51:56 PM PST 23 390019183 ps
T1300 /workspace/coverage/default/132.otp_ctrl_init_fail.87166077332508216806429108442343577349278790561929632277962314559540395050286 Nov 22 01:52:25 PM PST 23 Nov 22 01:52:31 PM PST 23 156689183 ps
T1301 /workspace/coverage/default/70.otp_ctrl_init_fail.99882214369450485412721734329265495469691699309669393138633585889105780126845 Nov 22 01:51:09 PM PST 23 Nov 22 01:51:15 PM PST 23 156689183 ps
T1302 /workspace/coverage/default/121.otp_ctrl_init_fail.20380972192462566877542067035339545883318976410132947617781998869191569844545 Nov 22 01:52:03 PM PST 23 Nov 22 01:52:08 PM PST 23 156689183 ps
T1303 /workspace/coverage/default/10.otp_ctrl_smoke.31683845276575490968588636406036282960661290186071783299244045863181014572756 Nov 22 01:50:21 PM PST 23 Nov 22 01:50:26 PM PST 23 138839183 ps
T1304 /workspace/coverage/default/18.otp_ctrl_alert_test.99429407957837038458549845945416820279993197588637874986925699072718386995967 Nov 22 01:50:43 PM PST 23 Nov 22 01:50:46 PM PST 23 71069183 ps
T1305 /workspace/coverage/default/24.otp_ctrl_macro_errs.109787444459523583979125952010421349241924866116973203452201950556582345074327 Nov 22 01:51:20 PM PST 23 Nov 22 01:51:42 PM PST 23 1137629183 ps
T1306 /workspace/coverage/default/235.otp_ctrl_init_fail.15350086911852851712853520764910646131451095011055244197317868973693340126885 Nov 22 01:52:04 PM PST 23 Nov 22 01:52:09 PM PST 23 156689183 ps
T1307 /workspace/coverage/default/24.otp_ctrl_smoke.111499452916065878121080848447624648631197035325978472882086803691143158853626 Nov 22 01:51:33 PM PST 23 Nov 22 01:51:40 PM PST 23 138839183 ps
T1308 /workspace/coverage/default/39.otp_ctrl_dai_errs.102736883664388716834065661941903616658184095627145174767458327294239214733058 Nov 22 01:51:55 PM PST 23 Nov 22 01:52:07 PM PST 23 390019183 ps
T1309 /workspace/coverage/default/15.otp_ctrl_test_access.14302519880724250894860685011318243573605326871464280698831619455010687878935 Nov 22 01:51:16 PM PST 23 Nov 22 01:51:26 PM PST 23 549639183 ps
T1310 /workspace/coverage/default/17.otp_ctrl_stress_all.69477153327480655294675769761602156569218424300035132184289825914211374501964 Nov 22 01:51:37 PM PST 23 Nov 22 01:53:51 PM PST 23 13240088340 ps
T1311 /workspace/coverage/default/36.otp_ctrl_regwen.72274063312583090837278344054273312259827666941851193786093269151945315189201 Nov 22 01:51:28 PM PST 23 Nov 22 01:51:34 PM PST 23 137469183 ps
T1312 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.24766247720759301385285797779721602008654860406111588646492850112782685826837 Nov 22 01:20:50 PM PST 23 Nov 22 01:20:55 PM PST 23 38239183 ps
T1313 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.62443228717125569531747865178034753054219505796482026927116746246597456358424 Nov 22 01:20:04 PM PST 23 Nov 22 01:20:07 PM PST 23 61029183 ps
T1314 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.20527332107911447309683922098183694151192808940975009555631690651966830903432 Nov 22 01:19:53 PM PST 23 Nov 22 01:19:58 PM PST 23 35669183 ps
T1315 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.21669368548986136101086255032090948457097821836062260937587715905005596456654 Nov 22 01:20:27 PM PST 23 Nov 22 01:20:34 PM PST 23 38239183 ps
T1316 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.63495043441670571673463000603313105984802318711985896901252692991482174699242 Nov 22 01:20:31 PM PST 23 Nov 22 01:20:38 PM PST 23 38239183 ps
T1317 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.72256309955256697688765384885897059877184188129637298970026487195227085171586 Nov 22 01:20:50 PM PST 23 Nov 22 01:20:55 PM PST 23 38239183 ps
T1318 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.71092038721675634375518763180090849992327804329309415835944248800145266290419 Nov 22 01:21:57 PM PST 23 Nov 22 01:22:13 PM PST 23 647529183 ps
T1319 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.39459745561988694208080065309302064653810755880899718754330473332071093810599 Nov 22 01:21:24 PM PST 23 Nov 22 01:21:36 PM PST 23 61029183 ps
T1320 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.71681770853587266286033256059698952594662936417470293888222949485479458864251 Nov 22 01:19:49 PM PST 23 Nov 22 01:19:58 PM PST 23 225479183 ps
T1321 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.60043046684232958016122018809637744842516435697806123341769331533528729347514 Nov 22 01:20:03 PM PST 23 Nov 22 01:20:05 PM PST 23 38239183 ps
T1322 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.90345076499512321260047439625559717855389689183983997945493021398739908344173 Nov 22 01:20:13 PM PST 23 Nov 22 01:20:17 PM PST 23 71439183 ps
T1323 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.11749659022454789483569755639881753570002145860821923708704988215264060253027 Nov 22 01:20:34 PM PST 23 Nov 22 01:20:41 PM PST 23 38239183 ps
T1324 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.23646276407007695919626373456090594550028189046613610560374149864455987000834 Nov 22 01:19:39 PM PST 23 Nov 22 01:19:48 PM PST 23 71439183 ps
T1325 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.17987490752812537529953334334523183063637255684781440122974013808250664602992 Nov 22 01:20:20 PM PST 23 Nov 22 01:20:24 PM PST 23 65579183 ps
T1326 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.65180991862124637576261362396249942197497683248798081583140576962056067083347 Nov 22 01:20:48 PM PST 23 Nov 22 01:20:54 PM PST 23 61029183 ps
T1327 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.72731487220821057679883646618355495745833122355696451842851530006814883314274 Nov 22 01:19:47 PM PST 23 Nov 22 01:19:54 PM PST 23 61029183 ps
T1328 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2517762900033621331190811191079276073718038905835275348864364120747580139581 Nov 22 01:20:20 PM PST 23 Nov 22 01:20:23 PM PST 23 35669183 ps
T1329 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.43944176953258080849099835407530622791959435419377081317254351156638448520760 Nov 22 01:20:25 PM PST 23 Nov 22 01:20:31 PM PST 23 71439183 ps
T1330 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.22301650864062849151050319841121439139608346451583552294897126948105191276498 Nov 22 01:20:47 PM PST 23 Nov 22 01:20:52 PM PST 23 38049183 ps
T1331 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.74465927829223613760999534541507110593518504896344798473380839792359568136356 Nov 22 01:20:20 PM PST 23 Nov 22 01:20:24 PM PST 23 38239183 ps
T1332 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.46340425363419128000028888814630730551244126442977603555816229164430978588888 Nov 22 01:20:18 PM PST 23 Nov 22 01:20:24 PM PST 23 225479183 ps
T1333 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.89681133033138607246831187570488664021165507917797626456439290022648930070172 Nov 22 01:20:45 PM PST 23 Nov 22 01:20:50 PM PST 23 65579183 ps
T1334 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.112057173557666968117114725199619374875742004563738791872342761796372654348943 Nov 22 01:20:56 PM PST 23 Nov 22 01:21:02 PM PST 23 61029183 ps
T1335 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.46694645152820154773397870572070317302458187733094595384515385998012317275893 Nov 22 01:20:49 PM PST 23 Nov 22 01:20:55 PM PST 23 65579183 ps
T1336 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.24247084857224040699155300923075731740689293221899702047464456290705543828532 Nov 22 01:20:55 PM PST 23 Nov 22 01:21:01 PM PST 23 38239183 ps
T1337 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.98332818781444922560512298375195800166454484991897378457148892001198860421467 Nov 22 01:20:14 PM PST 23 Nov 22 01:20:17 PM PST 23 38049183 ps
T1338 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.90737894344538342540092206376559237108930947669962102114873086077206851336983 Nov 22 01:20:34 PM PST 23 Nov 22 01:20:41 PM PST 23 38239183 ps
T1339 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.3669306012077998658714226550926898409692430452822872356671443490784635596008 Nov 22 01:19:48 PM PST 23 Nov 22 01:20:02 PM PST 23 647529183 ps
T1340 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.24587501772730924006257392599141032356286326115033038561399227102509418938396 Nov 22 01:19:49 PM PST 23 Nov 22 01:19:55 PM PST 23 61029183 ps
T1341 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.41862547121954396757978839993138676155533188429025409697136173365062844138109 Nov 22 01:21:30 PM PST 23 Nov 22 01:21:39 PM PST 23 65579183 ps
T1342 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.41025449496094432706541397048670753626045605896771972841863329606605206401115 Nov 22 01:19:52 PM PST 23 Nov 22 01:19:59 PM PST 23 71489183 ps
T1343 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.69446589195465109864652221667918887802000278873853305166092938829488410820949 Nov 22 01:20:21 PM PST 23 Nov 22 01:20:25 PM PST 23 38239183 ps

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.76828559003342806938986647877055763735128220086518125212052035704426752845678
Short name T21
Test name
Test status
Simulation time 346349183 ps
CPU time 7.36 seconds
Started Nov 22 01:50:06 PM PST 23
Finished Nov 22 01:50:20 PM PST 23
Peak memory 238656 kb
Host smart-e4a786db-9080-44e0-b073-c3b2162e1f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76828559003342806938986647877055763735128220086518125212052035704426752845678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.otp_ctrl_parallel_key_req.76828559003342806938986647877055763735128220086518125212052035704426752845678
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.75295919969856747639343068108918851666485557918423549020699004153242252566581
Short name T29
Test name
Test status
Simulation time 38239183 ps
CPU time 1.43 seconds
Started Nov 22 01:20:24 PM PST 23
Finished Nov 22 01:20:29 PM PST 23
Peak memory 229752 kb
Host smart-92b94657-428f-4bf1-b603-ed9f64eb7acc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75295919969856747639343068108918851666485557918423549020699004153242252566581 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.75295919969856747639343068108918851666485557918423549020699004153242252566581
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.67166413553336209885230598202083272646527416066147799674749188442806630878048
Short name T2
Test name
Test status
Simulation time 647529183 ps
CPU time 9.06 seconds
Started Nov 22 01:20:55 PM PST 23
Finished Nov 22 01:21:09 PM PST 23
Peak memory 230412 kb
Host smart-cf038f65-2bf2-446f-9353-d42d46fb6a42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67166413553336209885230598202083272646527416066147799674749188442806630878048 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.67166413553336209885230598202083272646527416066147799674749188442806630878048
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.33529504033269980964322125007094827481711956419376605396640236370774537290124
Short name T42
Test name
Test status
Simulation time 13240088340 ps
CPU time 132.3 seconds
Started Nov 22 01:51:23 PM PST 23
Finished Nov 22 01:53:38 PM PST 23
Peak memory 241816 kb
Host smart-101adb4a-0056-4644-8f84-da648fc0fc78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33529504033269980964322125007094827481711956419376605396640236370774537290124 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.33529504033269980964322125007094827481711956419376605396640236370774537290124
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.107631902142864799553068266416163868927872014072975468533632882678876678636994
Short name T23
Test name
Test status
Simulation time 150268849183 ps
CPU time 1984.06 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 02:24:33 PM PST 23
Peak memory 517428 kb
Host smart-a94305fa-113b-4017-83a0-3bd8fa3909f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076319021428647995530
68266416163868927872014072975468533632882678876678636994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_re
set.107631902142864799553068266416163868927872014072975468533632882678876678636994
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.24206292282136990010069142438087738100185033137151778510752861211507045738903
Short name T18
Test name
Test status
Simulation time 8539099183 ps
CPU time 150.75 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 01:52:39 PM PST 23
Peak memory 268504 kb
Host smart-0b4fc4a7-1faf-411f-a8bb-a483db522207
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24206292282136990010069142438087738100185033137151778510752861211507045738903 -assert nopostpro
c +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.24206292282136990010069142438087738100185033137151778510752861211507045738903
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.109558326340037929667703755469592821449596522717981532792570991605303485374588
Short name T7
Test name
Test status
Simulation time 71439183 ps
CPU time 2.89 seconds
Started Nov 22 01:21:29 PM PST 23
Finished Nov 22 01:21:40 PM PST 23
Peak memory 238400 kb
Host smart-dd81762a-b163-4dbd-b7f3-bd49a746f8b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109558326340037929667703755469592821449596522717981532792570991605303485374588 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.109558326340037929667703755469592821449596522717981532792570991605303485374588
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.48073409229723267939193606962280783482709257995582555106451410200911903099067
Short name T49
Test name
Test status
Simulation time 176929183 ps
CPU time 4.29 seconds
Started Nov 22 01:52:01 PM PST 23
Finished Nov 22 01:52:07 PM PST 23
Peak memory 238660 kb
Host smart-486c7757-13fd-40ad-ab91-6eeeb3f14426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48073409229723267939193606962280783482709257995582555106451410200911903099067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.48073409229723267939193606962280783482709257995582555106451410200911903099067
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.107631710993150915766769605198228071986000329029905596657231307085693503409705
Short name T54
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.32 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:43 PM PST 23
Peak memory 238928 kb
Host smart-9a9176ca-68f5-461f-bd08-7fd46c9ec664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107631710993150915766769605198228071986000329029905596657231307085693503409705 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.otp_ctrl_macro_errs.107631710993150915766769605198228071986000329029905596657231307085693503409705
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.29341802276722303253946862051127083940495527050221294831515674733384438387084
Short name T109
Test name
Test status
Simulation time 61029183 ps
CPU time 2.03 seconds
Started Nov 22 01:20:43 PM PST 23
Finished Nov 22 01:20:47 PM PST 23
Peak memory 230096 kb
Host smart-09a4e9f9-b31b-45cd-bd87-73bc6d7418aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29341802276722303253946862051127083940495527050221294831515674733384438387084
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.29341802276722303253946862051127083940495527050221294
831515674733384438387084
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.109616743481341491001492986809396388707854311048766075692866693351449319703821
Short name T20
Test name
Test status
Simulation time 549639183 ps
CPU time 8.8 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:33 PM PST 23
Peak memory 246944 kb
Host smart-6e1ea2b8-9c06-4a0a-b655-c4159ed0ceb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109616743481341491001492986809396388707854311048766075692866693351449319703821 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.otp_ctrl_test_access.109616743481341491001492986809396388707854311048766075692866693351449319703821
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.30699061911305739282673698513363183059526343687856755324308152431659115124396
Short name T6
Test name
Test status
Simulation time 65579183 ps
CPU time 1.99 seconds
Started Nov 22 01:19:53 PM PST 23
Finished Nov 22 01:20:00 PM PST 23
Peak memory 238452 kb
Host smart-ca6ef744-de47-481f-8211-eb61ce5cf06f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069906191130573928267369851336318305952634
3687856755324308152431659115124396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.3069906191130
5739282673698513363183059526343687856755324308152431659115124396
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.32045856580582957002759960355658228277770735801932982960663182604278323104721
Short name T48
Test name
Test status
Simulation time 137469183 ps
CPU time 3.64 seconds
Started Nov 22 01:50:50 PM PST 23
Finished Nov 22 01:50:55 PM PST 23
Peak memory 238728 kb
Host smart-5306b0f6-136a-4b1e-8536-e57fbfc1d288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=32045856580582957002759960355658228277770735801932982960663182604278323104721 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_regwen.32045856580582957002759960355658228277770735801932982960663182604278323104721
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.105569288019711817670230501238136112415309778342381333332219876127920438524717
Short name T1225
Test name
Test status
Simulation time 190889183 ps
CPU time 4.76 seconds
Started Nov 22 01:50:06 PM PST 23
Finished Nov 22 01:50:18 PM PST 23
Peak memory 238752 kb
Host smart-8a86350f-df1b-4fca-b7b5-35bc7795620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105569288019711817670230501238136112415309778342381333332219876127920438524717 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.otp_ctrl_background_chks.105569288019711817670230501238136112415309778342381333332219876127920438524717
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.75831512026190089315773181014144661242851485154800436261256533036440200518410
Short name T58
Test name
Test status
Simulation time 156689183 ps
CPU time 3.86 seconds
Started Nov 22 01:52:02 PM PST 23
Finished Nov 22 01:52:07 PM PST 23
Peak memory 238616 kb
Host smart-157597af-4174-4427-afe6-bc62c1df6b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75831512026190089315773181014144661242851485154800436261256533036440200518410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 105.otp_ctrl_init_fail.75831512026190089315773181014144661242851485154800436261256533036440200518410
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.19741120174631317703417793390706342774654102042126152138161734136088166421834
Short name T46
Test name
Test status
Simulation time 614979183 ps
CPU time 10.81 seconds
Started Nov 22 01:50:01 PM PST 23
Finished Nov 22 01:50:14 PM PST 23
Peak memory 238824 kb
Host smart-1f0edd53-e87e-4855-86cb-6c16613e172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19741120174631317703417793390706342774654102042126152138161734136088166421834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.otp_ctrl_dai_lock.19741120174631317703417793390706342774654102042126152138161734136088166421834
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.23646276407007695919626373456090594550028189046613610560374149864455987000834
Short name T1324
Test name
Test status
Simulation time 71439183 ps
CPU time 2.95 seconds
Started Nov 22 01:19:39 PM PST 23
Finished Nov 22 01:19:48 PM PST 23
Peak memory 238384 kb
Host smart-276bd407-d034-4b72-bd12-f63564baeb65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23646276407007695919626373456090594550028189046613610560374149864455987000834 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.23646276407007695919626373456090594550028189046613610560374149864455987000834
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.70469272938443890588664890050848998684613133573018156842670467311464320261987
Short name T307
Test name
Test status
Simulation time 486419183 ps
CPU time 11.74 seconds
Started Nov 22 01:49:54 PM PST 23
Finished Nov 22 01:50:06 PM PST 23
Peak memory 238732 kb
Host smart-ff582f86-9f77-4bd0-9805-2975666c0ae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70469272938443890588664890050848998684613133573018156842670467311464320261987 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.70469272938443890588664890050848998684613133573018156842670467311464320261987
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.74750525041544444266432201948345907262434488893087018832535956520463028084082
Short name T106
Test name
Test status
Simulation time 225479183 ps
CPU time 4.96 seconds
Started Nov 22 01:19:53 PM PST 23
Finished Nov 22 01:20:02 PM PST 23
Peak memory 230064 kb
Host smart-aea92360-67ea-4d55-bd24-c844ce13a248
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74750525041544444266432201948345907262434488893087018832535956520463028084082 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.74750525041544444266432201948345907262434488893087018832535956520463028084082
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.4627401977419509925796532276167979841189918994319608004434913741676993929619
Short name T383
Test name
Test status
Simulation time 71069183 ps
CPU time 1.87 seconds
Started Nov 22 01:50:55 PM PST 23
Finished Nov 22 01:50:58 PM PST 23
Peak memory 238440 kb
Host smart-75525fdb-c025-4fd8-b2d4-58107dd41806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4627401977419509925796532276167979841189918994319608004434913741676993929619 -assert nopostpro
c +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.4627401977419509925796532276167979841189918994319608004434913741676993929619
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.29284165790987801988565786518413573500407496671942263921902548272635411285384
Short name T99
Test name
Test status
Simulation time 111269183 ps
CPU time 2.68 seconds
Started Nov 22 01:50:54 PM PST 23
Finished Nov 22 01:50:58 PM PST 23
Peak memory 246800 kb
Host smart-9de4d428-accc-4085-8084-4f14156842de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29284165790987801988565786518413573500407496671942263921902548272635411285384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.otp_ctrl_check_fail.29284165790987801988565786518413573500407496671942263921902548272635411285384
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.95704798338471763555099867721359466173827410143786788874152988000629718783730
Short name T387
Test name
Test status
Simulation time 390019183 ps
CPU time 10.28 seconds
Started Nov 22 01:50:34 PM PST 23
Finished Nov 22 01:50:45 PM PST 23
Peak memory 238664 kb
Host smart-460a6b04-c58b-4902-9511-5b215b0d3617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95704798338471763555099867721359466173827410143786788874152988000629718783730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.otp_ctrl_dai_errs.95704798338471763555099867721359466173827410143786788874152988000629718783730
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.41025449496094432706541397048670753626045605896771972841863329606605206401115
Short name T1342
Test name
Test status
Simulation time 71489183 ps
CPU time 2.62 seconds
Started Nov 22 01:19:52 PM PST 23
Finished Nov 22 01:19:59 PM PST 23
Peak memory 230064 kb
Host smart-f51ffd6c-13f7-4187-b212-7438ae8a3cfe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41025449496094432706541397048670753626045605896771972841863329606605206401115 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.41025449496094432706541397048670753626045605896771972841863329606605206401115
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.106472018078618701675836757399999400771404575183996349815949555521812976897332
Short name T83
Test name
Test status
Simulation time 64059183 ps
CPU time 1.74 seconds
Started Nov 22 01:19:36 PM PST 23
Finished Nov 22 01:19:44 PM PST 23
Peak memory 230072 kb
Host smart-ba38bcfb-4d05-4e66-a6d1-4326a781f6e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106472018078618701675836757399999400771404575183996349815949555521812976897332 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.106472018078618701675836757399999400771404575183996349815949555521812976897332
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.20321238096498745494296843213127303404116069160682061368753039643894705502734
Short name T216
Test name
Test status
Simulation time 38049183 ps
CPU time 1.4 seconds
Started Nov 22 01:20:04 PM PST 23
Finished Nov 22 01:20:08 PM PST 23
Peak memory 230088 kb
Host smart-f2eed6be-c678-44c6-a5ce-41a3328e137b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20321238096498745494296843213127303404116069160682061368753039643894705502734 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.20321238096498745494296843213127303404116069160682061368753039643894705502734
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.112000442288744306382911164671342453128678278923019276113421928234244227440462
Short name T134
Test name
Test status
Simulation time 38239183 ps
CPU time 1.27 seconds
Started Nov 22 01:19:52 PM PST 23
Finished Nov 22 01:19:58 PM PST 23
Peak memory 229840 kb
Host smart-6305be0e-5a6a-446d-8d03-932c3e428687
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112000442288744306382911164671342453128678278923019276113421928234244227440462 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.112000442288744306382911164671342453128678278923019276113421928234244227440462
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.20527332107911447309683922098183694151192808940975009555631690651966830903432
Short name T1314
Test name
Test status
Simulation time 35669183 ps
CPU time 1.28 seconds
Started Nov 22 01:19:53 PM PST 23
Finished Nov 22 01:19:58 PM PST 23
Peak memory 229832 kb
Host smart-407e50a8-f399-40f5-9d86-b49e71254f0e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20527332107911447309683922098183694151192808940975009555631690651966830903432 -a
ssert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.2052733210791144730968392209818369415119280894097500955563
1690651966830903432
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.24966605547954314138636869298626975735537756458525233333379278626065948851455
Short name T138
Test name
Test status
Simulation time 35669183 ps
CPU time 1.28 seconds
Started Nov 22 01:19:47 PM PST 23
Finished Nov 22 01:19:53 PM PST 23
Peak memory 229856 kb
Host smart-ec04ac68-ee71-4c07-b422-f9a747670542
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24966605547954314138636869298626975735537756458525233333379278626065948851455 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.24966605547954314138636869298626975735537756458525233333379278626065948851455
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.24587501772730924006257392599141032356286326115033038561399227102509418938396
Short name T1340
Test name
Test status
Simulation time 61029183 ps
CPU time 2.1 seconds
Started Nov 22 01:19:49 PM PST 23
Finished Nov 22 01:19:55 PM PST 23
Peak memory 230140 kb
Host smart-972164fd-d7d2-43bb-8655-84f8cb359a58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24587501772730924006257392599141032356286326115033038561399227102509418938396
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.245875017727309240062573925991410323562863261150330385
61399227102509418938396
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.109343938543337624688582826130957897065225022581570498330385467845964010051182
Short name T167
Test name
Test status
Simulation time 647529183 ps
CPU time 9.45 seconds
Started Nov 22 01:19:38 PM PST 23
Finished Nov 22 01:19:53 PM PST 23
Peak memory 230316 kb
Host smart-8faf58a7-884c-42e6-a712-9eea8563d774
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109343938543337624688582826130957897065225022581570498330385467845964010051182 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.109343938543337624688582826130957897065225022581570498330385467845964010051182
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.80492558489099180726507481740082017252779209226211262197197847653852350978942
Short name T16
Test name
Test status
Simulation time 71489183 ps
CPU time 2.74 seconds
Started Nov 22 01:20:23 PM PST 23
Finished Nov 22 01:20:29 PM PST 23
Peak memory 230064 kb
Host smart-ffd84dbe-8c02-4144-b59e-7eca64e34c88
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80492558489099180726507481740082017252779209226211262197197847653852350978942 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.80492558489099180726507481740082017252779209226211262197197847653852350978942
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.71681770853587266286033256059698952594662936417470293888222949485479458864251
Short name T1320
Test name
Test status
Simulation time 225479183 ps
CPU time 4.91 seconds
Started Nov 22 01:19:49 PM PST 23
Finished Nov 22 01:19:58 PM PST 23
Peak memory 229928 kb
Host smart-d1abfd46-4411-4060-a0ef-d1e9c6e15f5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71681770853587266286033256059698952594662936417470293888222949485479458864251 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.71681770853587266286033256059698952594662936417470293888222949485479458864251
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.30827352289679645176117067420459133468489823085505131739781273273637202182650
Short name T171
Test name
Test status
Simulation time 64059183 ps
CPU time 1.72 seconds
Started Nov 22 01:20:34 PM PST 23
Finished Nov 22 01:20:41 PM PST 23
Peak memory 229700 kb
Host smart-d838bf68-a649-47dc-8dc7-ac3f62873d0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30827352289679645176117067420459133468489823085505131739781273273637202182650 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.30827352289679645176117067420459133468489823085505131739781273273637202182650
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.110500119806689719248639476959683030495973504071292045877700004404259293871598
Short name T177
Test name
Test status
Simulation time 65579183 ps
CPU time 1.92 seconds
Started Nov 22 01:19:54 PM PST 23
Finished Nov 22 01:20:01 PM PST 23
Peak memory 238356 kb
Host smart-a78cfa32-95e4-4e04-939f-e53c58cfea22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105001198066897192486394769596830304959735
04071292045877700004404259293871598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.110500119806
689719248639476959683030495973504071292045877700004404259293871598
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.21014129121902964730843655572728594141155620228545887136905932105457108608026
Short name T180
Test name
Test status
Simulation time 38049183 ps
CPU time 1.42 seconds
Started Nov 22 01:19:52 PM PST 23
Finished Nov 22 01:19:58 PM PST 23
Peak memory 230060 kb
Host smart-86acb5c3-c116-413c-9626-d9035603aa5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21014129121902964730843655572728594141155620228545887136905932105457108608026 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.21014129121902964730843655572728594141155620228545887136905932105457108608026
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.64848341545607361152835344342571547887388287950596808624017147514818466058107
Short name T199
Test name
Test status
Simulation time 38239183 ps
CPU time 1.35 seconds
Started Nov 22 01:19:49 PM PST 23
Finished Nov 22 01:19:55 PM PST 23
Peak memory 229756 kb
Host smart-a6a0a693-1205-41fd-84e6-e152adc30b91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64848341545607361152835344342571547887388287950596808624017147514818466058107 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.64848341545607361152835344342571547887388287950596808624017147514818466058107
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.43207816805591345209382549960360908457710464399125296244053838540462009075737
Short name T191
Test name
Test status
Simulation time 35669183 ps
CPU time 1.29 seconds
Started Nov 22 01:19:48 PM PST 23
Finished Nov 22 01:19:54 PM PST 23
Peak memory 229848 kb
Host smart-ddc613dc-717f-4116-b8ef-71baf4e9a3f7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43207816805591345209382549960360908457710464399125296244053838540462009075737 -a
ssert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.4320781680559134520938254996036090845771046439912529624405
3838540462009075737
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.60442867974512011910566347360791199402442456947555160898071307576408351494180
Short name T142
Test name
Test status
Simulation time 35669183 ps
CPU time 1.3 seconds
Started Nov 22 01:19:50 PM PST 23
Finished Nov 22 01:19:55 PM PST 23
Peak memory 229860 kb
Host smart-45c15d58-9d43-4715-b8f6-59138704a590
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60442867974512011910566347360791199402442456947555160898071307576408351494180 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.60442867974512011910566347360791199402442456947555160898071307576408351494180
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.19005628484642663068319923492795100291190823545215884709051989209228947044158
Short name T124
Test name
Test status
Simulation time 61029183 ps
CPU time 1.99 seconds
Started Nov 22 01:19:54 PM PST 23
Finished Nov 22 01:20:01 PM PST 23
Peak memory 230120 kb
Host smart-d2462248-58a6-4845-a1c8-89e1660f8556
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19005628484642663068319923492795100291190823545215884709051989209228947044158
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.190056284846426630683199234927951002911908235452158847
09051989209228947044158
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.53484363595992223864460564000079550566400201785819493751307249083521109025377
Short name T145
Test name
Test status
Simulation time 71439183 ps
CPU time 2.91 seconds
Started Nov 22 01:20:04 PM PST 23
Finished Nov 22 01:20:08 PM PST 23
Peak memory 238280 kb
Host smart-453df045-7a10-405e-84d3-f5e34467ed04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53484363595992223864460564000079550566400201785819493751307249083521109025377 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.53484363595992223864460564000079550566400201785819493751307249083521109025377
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.81029800436580813706531120820405402178707840260428936479660239018034631049066
Short name T217
Test name
Test status
Simulation time 647529183 ps
CPU time 9.53 seconds
Started Nov 22 01:19:52 PM PST 23
Finished Nov 22 01:20:06 PM PST 23
Peak memory 230360 kb
Host smart-27ec32b6-4521-4ce5-ba34-ca1accee76f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81029800436580813706531120820405402178707840260428936479660239018034631049066 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.81029800436580813706531120820405402178707840260428936479660239018034631049066
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.96403277078725567919954814059113029139647464457499517275238104628062633716464
Short name T196
Test name
Test status
Simulation time 65579183 ps
CPU time 1.91 seconds
Started Nov 22 01:20:25 PM PST 23
Finished Nov 22 01:20:31 PM PST 23
Peak memory 238400 kb
Host smart-ce483dfb-13e6-4762-a626-cede33418d60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9640327707872556791995481405911302913964746
4457499517275238104628062633716464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.964032770787
25567919954814059113029139647464457499517275238104628062633716464
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.22301650864062849151050319841121439139608346451583552294897126948105191276498
Short name T1330
Test name
Test status
Simulation time 38049183 ps
CPU time 1.46 seconds
Started Nov 22 01:20:47 PM PST 23
Finished Nov 22 01:20:52 PM PST 23
Peak memory 230020 kb
Host smart-a99b8f5c-0212-4a13-a74b-06130cb85ebd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22301650864062849151050319841121439139608346451583552294897126948105191276498 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.22301650864062849151050319841121439139608346451583552294897126948105191276498
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.21669368548986136101086255032090948457097821836062260937587715905005596456654
Short name T1315
Test name
Test status
Simulation time 38239183 ps
CPU time 1.31 seconds
Started Nov 22 01:20:27 PM PST 23
Finished Nov 22 01:20:34 PM PST 23
Peak memory 229696 kb
Host smart-de860acf-c119-4573-83e2-87156ef10d37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21669368548986136101086255032090948457097821836062260937587715905005596456654 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.21669368548986136101086255032090948457097821836062260937587715905005596456654
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.56421599068843370795472397044239157697748119607328992050575665774161056718690
Short name T206
Test name
Test status
Simulation time 61029183 ps
CPU time 2.04 seconds
Started Nov 22 01:20:50 PM PST 23
Finished Nov 22 01:20:56 PM PST 23
Peak memory 230188 kb
Host smart-e53610a6-b736-4f3b-b232-b3ce5a9936e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56421599068843370795472397044239157697748119607328992050575665774161056718690
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.56421599068843370795472397044239157697748119607328992
050575665774161056718690
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.54910450453189836788969639251490373225361032264459629136499230598268325550757
Short name T141
Test name
Test status
Simulation time 71439183 ps
CPU time 3.23 seconds
Started Nov 22 01:20:25 PM PST 23
Finished Nov 22 01:20:32 PM PST 23
Peak memory 238300 kb
Host smart-cf2c7961-fb73-4f9c-addf-ac56292e263f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54910450453189836788969639251490373225361032264459629136499230598268325550757 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.54910450453189836788969639251490373225361032264459629136499230598268325550757
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.107233712799981542377936000484159121742527777254146584705291851440303427202569
Short name T204
Test name
Test status
Simulation time 647529183 ps
CPU time 9.07 seconds
Started Nov 22 01:20:55 PM PST 23
Finished Nov 22 01:21:09 PM PST 23
Peak memory 230420 kb
Host smart-454962f2-8d4b-41f3-bf57-482c5d4d4565
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107233712799981542377936000484159121742527777254146584705291851440303427202569 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.107233712799981542377936000484159121742527777254146584705291851440303427202569
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.80376297938043357189859749957312863623257313341652905570769739429752993651494
Short name T162
Test name
Test status
Simulation time 65579183 ps
CPU time 1.89 seconds
Started Nov 22 01:21:27 PM PST 23
Finished Nov 22 01:21:39 PM PST 23
Peak memory 238384 kb
Host smart-2d7e6059-b419-496a-a1b1-498bdb6c7fb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8037629793804335718985974995731286362325731
3341652905570769739429752993651494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.803762979380
43357189859749957312863623257313341652905570769739429752993651494
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.66299311403228508083901032027021109642667555008273653143647378238935589428120
Short name T116
Test name
Test status
Simulation time 38049183 ps
CPU time 1.42 seconds
Started Nov 22 01:20:49 PM PST 23
Finished Nov 22 01:20:54 PM PST 23
Peak memory 230048 kb
Host smart-7971e57f-8ef1-4e15-9385-263a3137fe17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66299311403228508083901032027021109642667555008273653143647378238935589428120 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.66299311403228508083901032027021109642667555008273653143647378238935589428120
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.24766247720759301385285797779721602008654860406111588646492850112782685826837
Short name T1312
Test name
Test status
Simulation time 38239183 ps
CPU time 1.3 seconds
Started Nov 22 01:20:50 PM PST 23
Finished Nov 22 01:20:55 PM PST 23
Peak memory 229796 kb
Host smart-bc8e8cb4-328e-42bd-832f-5746888c29e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24766247720759301385285797779721602008654860406111588646492850112782685826837 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.24766247720759301385285797779721602008654860406111588646492850112782685826837
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.65180991862124637576261362396249942197497683248798081583140576962056067083347
Short name T1326
Test name
Test status
Simulation time 61029183 ps
CPU time 1.95 seconds
Started Nov 22 01:20:48 PM PST 23
Finished Nov 22 01:20:54 PM PST 23
Peak memory 230100 kb
Host smart-04a83776-debc-4762-8bfd-57a713d423b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65180991862124637576261362396249942197497683248798081583140576962056067083347
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.65180991862124637576261362396249942197497683248798081
583140576962056067083347
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.82674012482967903506256422846168565459563148900809145684244078810719954500299
Short name T103
Test name
Test status
Simulation time 71439183 ps
CPU time 3.07 seconds
Started Nov 22 01:20:44 PM PST 23
Finished Nov 22 01:20:49 PM PST 23
Peak memory 238380 kb
Host smart-a39d4004-c6d4-4604-a447-31f1511e8760
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82674012482967903506256422846168565459563148900809145684244078810719954500299 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.82674012482967903506256422846168565459563148900809145684244078810719954500299
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.66797227303360402496511629274850678278642914951990409299021605313693810443319
Short name T198
Test name
Test status
Simulation time 647529183 ps
CPU time 9.69 seconds
Started Nov 22 01:20:51 PM PST 23
Finished Nov 22 01:21:04 PM PST 23
Peak memory 230312 kb
Host smart-7a3ebed7-64b5-4030-8056-44dcf67053a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66797227303360402496511629274850678278642914951990409299021605313693810443319 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.66797227303360402496511629274850678278642914951990409299021605313693810443319
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.41862547121954396757978839993138676155533188429025409697136173365062844138109
Short name T1341
Test name
Test status
Simulation time 65579183 ps
CPU time 1.88 seconds
Started Nov 22 01:21:30 PM PST 23
Finished Nov 22 01:21:39 PM PST 23
Peak memory 238364 kb
Host smart-74ad9d71-2373-4df0-b6a4-afd3d4cf2787
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186254712195439675797883999313867615553318
8429025409697136173365062844138109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.418625471219
54396757978839993138676155533188429025409697136173365062844138109
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.30762386528430687413067973512520093105697292228859281249804879361977478130978
Short name T112
Test name
Test status
Simulation time 38049183 ps
CPU time 1.43 seconds
Started Nov 22 01:20:50 PM PST 23
Finished Nov 22 01:20:55 PM PST 23
Peak memory 230048 kb
Host smart-dbaf1901-8feb-4eec-b7ab-6085674f0002
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30762386528430687413067973512520093105697292228859281249804879361977478130978 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.30762386528430687413067973512520093105697292228859281249804879361977478130978
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.24247084857224040699155300923075731740689293221899702047464456290705543828532
Short name T1336
Test name
Test status
Simulation time 38239183 ps
CPU time 1.29 seconds
Started Nov 22 01:20:55 PM PST 23
Finished Nov 22 01:21:01 PM PST 23
Peak memory 229764 kb
Host smart-0afd10a8-9372-4f7f-bc3e-ce608119aaea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24247084857224040699155300923075731740689293221899702047464456290705543828532 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.24247084857224040699155300923075731740689293221899702047464456290705543828532
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.87402439996829291601890300013827406282839666120373555154713013513612374555750
Short name T118
Test name
Test status
Simulation time 61029183 ps
CPU time 2.04 seconds
Started Nov 22 01:21:10 PM PST 23
Finished Nov 22 01:21:14 PM PST 23
Peak memory 230268 kb
Host smart-e4b1ee07-21f7-4a46-a729-132b6186d680
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87402439996829291601890300013827406282839666120373555154713013513612374555750
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.87402439996829291601890300013827406282839666120373555
154713013513612374555750
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.89388953628371725645034950097563492432976247928046608685894404036690545060992
Short name T101
Test name
Test status
Simulation time 71439183 ps
CPU time 2.78 seconds
Started Nov 22 01:20:50 PM PST 23
Finished Nov 22 01:20:57 PM PST 23
Peak memory 238340 kb
Host smart-ab84f537-4ba3-40e1-9010-cba0a72c1724
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89388953628371725645034950097563492432976247928046608685894404036690545060992 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.89388953628371725645034950097563492432976247928046608685894404036690545060992
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.5987517021677710187032894317043083897879356337947142768349814318369127425106
Short name T213
Test name
Test status
Simulation time 647529183 ps
CPU time 9.32 seconds
Started Nov 22 01:21:30 PM PST 23
Finished Nov 22 01:21:46 PM PST 23
Peak memory 230288 kb
Host smart-45858fbf-2bb4-4c32-b35a-4775572f430b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5987517021677710187032894317043083897879356337947142768349814318369127425106 -assert no
postproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.5987517021677710187032894317043083897879356337947142768349814318369127425106
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.106773939535909398710737391647624458411508337025744922437356430942509537212389
Short name T111
Test name
Test status
Simulation time 65579183 ps
CPU time 1.96 seconds
Started Nov 22 01:21:10 PM PST 23
Finished Nov 22 01:21:14 PM PST 23
Peak memory 238340 kb
Host smart-646945b6-fa1c-4246-8f19-882d78522e29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067739395359093987107373916476244584115083
37025744922437356430942509537212389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.10677393953
5909398710737391647624458411508337025744922437356430942509537212389
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.80598328126816303751261659648909024324556552744374565589101546341510435198771
Short name T100
Test name
Test status
Simulation time 38049183 ps
CPU time 1.47 seconds
Started Nov 22 01:21:23 PM PST 23
Finished Nov 22 01:21:33 PM PST 23
Peak memory 230096 kb
Host smart-a2303bb8-381e-4dda-afda-db8e427c4608
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80598328126816303751261659648909024324556552744374565589101546341510435198771 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.80598328126816303751261659648909024324556552744374565589101546341510435198771
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.109591589119988100044337270463577845584236666119491780797232209253302131977793
Short name T163
Test name
Test status
Simulation time 38239183 ps
CPU time 1.42 seconds
Started Nov 22 01:21:09 PM PST 23
Finished Nov 22 01:21:11 PM PST 23
Peak memory 229772 kb
Host smart-c583558f-d13b-4c8b-ba14-4f3a789281fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109591589119988100044337270463577845584236666119491780797232209253302131977793 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.109591589119988100044337270463577845584236666119491780797232209253302131977793
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.39459745561988694208080065309302064653810755880899718754330473332071093810599
Short name T1319
Test name
Test status
Simulation time 61029183 ps
CPU time 2.07 seconds
Started Nov 22 01:21:24 PM PST 23
Finished Nov 22 01:21:36 PM PST 23
Peak memory 230136 kb
Host smart-9d0708e0-c61b-4e99-81bf-6d97573fcb4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39459745561988694208080065309302064653810755880899718754330473332071093810599
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.39459745561988694208080065309302064653810755880899718
754330473332071093810599
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.71092038721675634375518763180090849992327804329309415835944248800145266290419
Short name T1318
Test name
Test status
Simulation time 647529183 ps
CPU time 10.04 seconds
Started Nov 22 01:21:57 PM PST 23
Finished Nov 22 01:22:13 PM PST 23
Peak memory 230368 kb
Host smart-b868dfdc-0cd9-405a-b88a-df94a89d7eef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71092038721675634375518763180090849992327804329309415835944248800145266290419 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.71092038721675634375518763180090849992327804329309415835944248800145266290419
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.74348694676171881185385890633572222876813786524314989715236384616817018236905
Short name T160
Test name
Test status
Simulation time 65579183 ps
CPU time 1.96 seconds
Started Nov 22 01:20:17 PM PST 23
Finished Nov 22 01:20:21 PM PST 23
Peak memory 238408 kb
Host smart-5d6a946b-38fd-499c-b04e-0c349d6937e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7434869467617188118538589063357222287681378
6524314989715236384616817018236905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.743486946761
71881185385890633572222876813786524314989715236384616817018236905
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.37237131518166468920243783339105556262892411350686085895151195807381386127518
Short name T214
Test name
Test status
Simulation time 38049183 ps
CPU time 1.39 seconds
Started Nov 22 01:21:31 PM PST 23
Finished Nov 22 01:21:39 PM PST 23
Peak memory 230000 kb
Host smart-9cf23e5d-8bd6-4021-b317-0671aeac984f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37237131518166468920243783339105556262892411350686085895151195807381386127518 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.37237131518166468920243783339105556262892411350686085895151195807381386127518
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.81709107225343866609645947172425671080337315816311685656916509643287953341256
Short name T15
Test name
Test status
Simulation time 38239183 ps
CPU time 1.35 seconds
Started Nov 22 01:21:24 PM PST 23
Finished Nov 22 01:21:35 PM PST 23
Peak memory 229724 kb
Host smart-bda868a2-2268-4d11-b6f2-ef06595c7a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81709107225343866609645947172425671080337315816311685656916509643287953341256 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.81709107225343866609645947172425671080337315816311685656916509643287953341256
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.66182540318789228256695835877041804106384891895190937646143155283460351469621
Short name T125
Test name
Test status
Simulation time 61029183 ps
CPU time 2.05 seconds
Started Nov 22 01:20:26 PM PST 23
Finished Nov 22 01:20:32 PM PST 23
Peak memory 230172 kb
Host smart-00a59bd7-58d6-4270-a446-1e97488531b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66182540318789228256695835877041804106384891895190937646143155283460351469621
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.66182540318789228256695835877041804106384891895190937
646143155283460351469621
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2074812837410962262543307636103543598747174129558380163431209942114559458318
Short name T3
Test name
Test status
Simulation time 71439183 ps
CPU time 2.91 seconds
Started Nov 22 01:21:07 PM PST 23
Finished Nov 22 01:21:11 PM PST 23
Peak memory 238372 kb
Host smart-4924e4d4-6618-464a-9dc8-eeea73d21c8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074812837410962262543307636103543598747174129558380163431209942114559458318 -assert nopostproc +UV
M_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.2074812837410962262543307636103543598747174129558380163431209942114559458318
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.74551240183432278751799832126862398960458088299991643838801681970630083116620
Short name T115
Test name
Test status
Simulation time 647529183 ps
CPU time 9.03 seconds
Started Nov 22 01:21:31 PM PST 23
Finished Nov 22 01:21:46 PM PST 23
Peak memory 230280 kb
Host smart-2f0fb1d9-9391-4432-9d3d-e21f9244d453
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74551240183432278751799832126862398960458088299991643838801681970630083116620 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.74551240183432278751799832126862398960458088299991643838801681970630083116620
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.15773968273207881328720507432189725961452503505194107710762726199346072456056
Short name T10
Test name
Test status
Simulation time 65579183 ps
CPU time 1.97 seconds
Started Nov 22 01:20:23 PM PST 23
Finished Nov 22 01:20:28 PM PST 23
Peak memory 238308 kb
Host smart-8c4f8a77-ef1c-4273-913c-acd9cda15c54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577396827320788132872050743218972596145250
3505194107710762726199346072456056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.157739682732
07881328720507432189725961452503505194107710762726199346072456056
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.39957117470938378857796785753024348888703878040635644548888002135454408341375
Short name T200
Test name
Test status
Simulation time 38049183 ps
CPU time 1.46 seconds
Started Nov 22 01:20:01 PM PST 23
Finished Nov 22 01:20:04 PM PST 23
Peak memory 230060 kb
Host smart-5b63f6ba-ef24-43b2-8899-751534569a98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39957117470938378857796785753024348888703878040635644548888002135454408341375 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.39957117470938378857796785753024348888703878040635644548888002135454408341375
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.60043046684232958016122018809637744842516435697806123341769331533528729347514
Short name T1321
Test name
Test status
Simulation time 38239183 ps
CPU time 1.35 seconds
Started Nov 22 01:20:03 PM PST 23
Finished Nov 22 01:20:05 PM PST 23
Peak memory 229812 kb
Host smart-a347157b-31b5-43bb-ba58-cf6737ba3030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60043046684232958016122018809637744842516435697806123341769331533528729347514 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.60043046684232958016122018809637744842516435697806123341769331533528729347514
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.61961845704919603022539420007550933852055016223269323133888057026539887187404
Short name T123
Test name
Test status
Simulation time 61029183 ps
CPU time 1.9 seconds
Started Nov 22 01:21:17 PM PST 23
Finished Nov 22 01:21:21 PM PST 23
Peak memory 229700 kb
Host smart-55095c4d-5ea4-46c7-b994-641417d96481
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61961845704919603022539420007550933852055016223269323133888057026539887187404
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.61961845704919603022539420007550933852055016223269323
133888057026539887187404
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2186212739884585370176903389961126623786568627076276899233879366507519174328
Short name T1
Test name
Test status
Simulation time 71439183 ps
CPU time 2.98 seconds
Started Nov 22 01:20:03 PM PST 23
Finished Nov 22 01:20:07 PM PST 23
Peak memory 238428 kb
Host smart-f56001e7-0999-4961-95ff-0dd3c7d8c47d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186212739884585370176903389961126623786568627076276899233879366507519174328 -assert nopostproc +UV
M_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.2186212739884585370176903389961126623786568627076276899233879366507519174328
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.14295771773975152577311910541924720321804460743565371475308152407471278000082
Short name T152
Test name
Test status
Simulation time 647529183 ps
CPU time 9.45 seconds
Started Nov 22 01:20:09 PM PST 23
Finished Nov 22 01:20:19 PM PST 23
Peak memory 230352 kb
Host smart-876db590-41bb-41f2-9df9-bdb5dcce9576
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14295771773975152577311910541924720321804460743565371475308152407471278000082 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.14295771773975152577311910541924720321804460743565371475308152407471278000082
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.4797651590831903895089908632458346462206313323244226199688104712480919150129
Short name T5
Test name
Test status
Simulation time 65579183 ps
CPU time 1.82 seconds
Started Nov 22 01:21:18 PM PST 23
Finished Nov 22 01:21:22 PM PST 23
Peak memory 237968 kb
Host smart-7ff82a47-d62f-4a9f-91da-3571b152e8e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4797651590831903895089908632458346462206313
323244226199688104712480919150129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.4797651590831
903895089908632458346462206313323244226199688104712480919150129
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.22394553801474756898400079673991218390311748603039366842436996468862125865150
Short name T168
Test name
Test status
Simulation time 38049183 ps
CPU time 1.45 seconds
Started Nov 22 01:20:43 PM PST 23
Finished Nov 22 01:20:46 PM PST 23
Peak memory 230036 kb
Host smart-d10972af-2111-440d-8914-be9eac84f0e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22394553801474756898400079673991218390311748603039366842436996468862125865150 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.22394553801474756898400079673991218390311748603039366842436996468862125865150
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.14819916665471299776151100050432393704084793347168789872137845010728444497866
Short name T156
Test name
Test status
Simulation time 38239183 ps
CPU time 1.33 seconds
Started Nov 22 01:20:20 PM PST 23
Finished Nov 22 01:20:24 PM PST 23
Peak memory 229676 kb
Host smart-92a1266e-a05b-4074-b8a5-e0fa6b13b841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14819916665471299776151100050432393704084793347168789872137845010728444497866 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.14819916665471299776151100050432393704084793347168789872137845010728444497866
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.102069455099644735709131500915205945314215257113059220132496125481246064266337
Short name T122
Test name
Test status
Simulation time 61029183 ps
CPU time 1.96 seconds
Started Nov 22 01:21:17 PM PST 23
Finished Nov 22 01:21:21 PM PST 23
Peak memory 228460 kb
Host smart-a6595c47-5d41-4542-805c-3960a0ea5981
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102069455099644735709131500915205945314215257113059220132496125481246064266337
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.1020694550996447357091315009152059453142152571130592
20132496125481246064266337
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.13481846382852019003960959601527311907970150051722044736459359265003952935364
Short name T157
Test name
Test status
Simulation time 71439183 ps
CPU time 2.98 seconds
Started Nov 22 01:20:03 PM PST 23
Finished Nov 22 01:20:07 PM PST 23
Peak memory 238428 kb
Host smart-75c58819-dade-40d6-8dc6-df61c44e0cea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13481846382852019003960959601527311907970150051722044736459359265003952935364 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.13481846382852019003960959601527311907970150051722044736459359265003952935364
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.43178465801242845221994608940715852549804425253160770936380036520915422416624
Short name T108
Test name
Test status
Simulation time 647529183 ps
CPU time 9.25 seconds
Started Nov 22 01:20:05 PM PST 23
Finished Nov 22 01:20:16 PM PST 23
Peak memory 230360 kb
Host smart-1dfcb9d1-8fd5-4b16-92e2-f9fb17662937
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43178465801242845221994608940715852549804425253160770936380036520915422416624 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.43178465801242845221994608940715852549804425253160770936380036520915422416624
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.89681133033138607246831187570488664021165507917797626456439290022648930070172
Short name T1333
Test name
Test status
Simulation time 65579183 ps
CPU time 1.9 seconds
Started Nov 22 01:20:45 PM PST 23
Finished Nov 22 01:20:50 PM PST 23
Peak memory 238352 kb
Host smart-90989cab-0808-4837-ac28-95482a473482
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8968113303313860724683118757048866402116550
7917797626456439290022648930070172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.896811330331
38607246831187570488664021165507917797626456439290022648930070172
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.73394108392679590598540925632611819699864085085820883160475063852676231448589
Short name T150
Test name
Test status
Simulation time 38049183 ps
CPU time 1.44 seconds
Started Nov 22 01:20:24 PM PST 23
Finished Nov 22 01:20:29 PM PST 23
Peak memory 230100 kb
Host smart-61683374-1d64-492c-b311-edeafdc379d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73394108392679590598540925632611819699864085085820883160475063852676231448589 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.73394108392679590598540925632611819699864085085820883160475063852676231448589
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.49201928892451305870731737847502340575138357737101166354088894267516141620123
Short name T208
Test name
Test status
Simulation time 38239183 ps
CPU time 1.33 seconds
Started Nov 22 01:20:24 PM PST 23
Finished Nov 22 01:20:29 PM PST 23
Peak memory 229784 kb
Host smart-4b395ec9-d2c3-46d7-aac1-e8846de91fd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49201928892451305870731737847502340575138357737101166354088894267516141620123 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.49201928892451305870731737847502340575138357737101166354088894267516141620123
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.45807010418437831523482882215008909766881691179640147570964647150493788809180
Short name T119
Test name
Test status
Simulation time 61029183 ps
CPU time 2.07 seconds
Started Nov 22 01:20:44 PM PST 23
Finished Nov 22 01:20:49 PM PST 23
Peak memory 230152 kb
Host smart-80fa0975-1bc4-48bb-bda0-9aeca8ca8380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45807010418437831523482882215008909766881691179640147570964647150493788809180
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.45807010418437831523482882215008909766881691179640147
570964647150493788809180
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.55309165638701803414891231551217713933377336516591290913623990535669610941621
Short name T86
Test name
Test status
Simulation time 71439183 ps
CPU time 3.02 seconds
Started Nov 22 01:20:19 PM PST 23
Finished Nov 22 01:20:24 PM PST 23
Peak memory 238384 kb
Host smart-453a9c06-8131-4d82-9351-14559a21654a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55309165638701803414891231551217713933377336516591290913623990535669610941621 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.55309165638701803414891231551217713933377336516591290913623990535669610941621
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.104951108604215727783040203940126308448210021679843315738449463774045262290858
Short name T133
Test name
Test status
Simulation time 647529183 ps
CPU time 9.32 seconds
Started Nov 22 01:20:12 PM PST 23
Finished Nov 22 01:20:22 PM PST 23
Peak memory 230348 kb
Host smart-b00ae142-43bf-4249-af1b-db2bf15871da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104951108604215727783040203940126308448210021679843315738449463774045262290858 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.104951108604215727783040203940126308448210021679843315738449463774045262290858
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.52218623391652970464531530716308276040655036462803080529919936345160674900091
Short name T193
Test name
Test status
Simulation time 65579183 ps
CPU time 2.03 seconds
Started Nov 22 01:20:27 PM PST 23
Finished Nov 22 01:20:35 PM PST 23
Peak memory 238424 kb
Host smart-3f67baf3-3810-46cc-8fb7-c2273d87c0f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5221862339165297046453153071630827604065503
6462803080529919936345160674900091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.522186233916
52970464531530716308276040655036462803080529919936345160674900091
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.17724930070892257184364001191755106735316460690511367013591271745384064272681
Short name T174
Test name
Test status
Simulation time 38049183 ps
CPU time 1.49 seconds
Started Nov 22 01:20:27 PM PST 23
Finished Nov 22 01:20:35 PM PST 23
Peak memory 230092 kb
Host smart-88a0fcc3-6bba-44aa-bd72-736807a89113
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17724930070892257184364001191755106735316460690511367013591271745384064272681 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.17724930070892257184364001191755106735316460690511367013591271745384064272681
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.60173005543883156464573307961578399963448211052952359693280809321434669235587
Short name T149
Test name
Test status
Simulation time 38239183 ps
CPU time 1.33 seconds
Started Nov 22 01:20:50 PM PST 23
Finished Nov 22 01:20:56 PM PST 23
Peak memory 229720 kb
Host smart-312e3f7b-9991-4e1e-8cd8-9e9e68508941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60173005543883156464573307961578399963448211052952359693280809321434669235587 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.60173005543883156464573307961578399963448211052952359693280809321434669235587
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2111223137154789790414620924063396286680698627330054921314331382179290574596
Short name T102
Test name
Test status
Simulation time 71439183 ps
CPU time 3.15 seconds
Started Nov 22 01:20:24 PM PST 23
Finished Nov 22 01:20:31 PM PST 23
Peak memory 238444 kb
Host smart-68cd375f-4127-4f73-a4af-23c4fa1a3302
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111223137154789790414620924063396286680698627330054921314331382179290574596 -assert nopostproc +UV
M_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.2111223137154789790414620924063396286680698627330054921314331382179290574596
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.22508335194854254743564668578850687803606253361834513404299994236163239706737
Short name T175
Test name
Test status
Simulation time 647529183 ps
CPU time 9.37 seconds
Started Nov 22 01:20:45 PM PST 23
Finished Nov 22 01:20:57 PM PST 23
Peak memory 230452 kb
Host smart-1c061c29-b565-4607-a59b-5141e51469fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22508335194854254743564668578850687803606253361834513404299994236163239706737 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.22508335194854254743564668578850687803606253361834513404299994236163239706737
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.46694645152820154773397870572070317302458187733094595384515385998012317275893
Short name T1335
Test name
Test status
Simulation time 65579183 ps
CPU time 1.86 seconds
Started Nov 22 01:20:49 PM PST 23
Finished Nov 22 01:20:55 PM PST 23
Peak memory 238440 kb
Host smart-4cfadce7-9215-4b57-b620-4372de81e42b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4669464515282015477339787057207031730245818
7733094595384515385998012317275893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.466946451528
20154773397870572070317302458187733094595384515385998012317275893
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.51719547069710143585123851433718426803174893274287179986111683620703503522470
Short name T161
Test name
Test status
Simulation time 38049183 ps
CPU time 1.45 seconds
Started Nov 22 01:22:55 PM PST 23
Finished Nov 22 01:23:08 PM PST 23
Peak memory 229924 kb
Host smart-7ab9fc02-833a-4512-ba2b-e4b2afddb681
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51719547069710143585123851433718426803174893274287179986111683620703503522470 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.51719547069710143585123851433718426803174893274287179986111683620703503522470
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.114125083788179226364028107475002462514658309521049044587542667890325191491708
Short name T14
Test name
Test status
Simulation time 38239183 ps
CPU time 1.28 seconds
Started Nov 22 01:20:49 PM PST 23
Finished Nov 22 01:20:54 PM PST 23
Peak memory 229648 kb
Host smart-d638e740-eb7e-45d5-8122-54b7c8fa5dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114125083788179226364028107475002462514658309521049044587542667890325191491708 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.114125083788179226364028107475002462514658309521049044587542667890325191491708
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.112057173557666968117114725199619374875742004563738791872342761796372654348943
Short name T1334
Test name
Test status
Simulation time 61029183 ps
CPU time 2.02 seconds
Started Nov 22 01:20:56 PM PST 23
Finished Nov 22 01:21:02 PM PST 23
Peak memory 230228 kb
Host smart-dbb21c8e-3a8d-4b89-886f-89f4f612c2b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112057173557666968117114725199619374875742004563738791872342761796372654348943
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.1120571735576669681171147251996193748757420045637387
91872342761796372654348943
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.72113101226309615505698354067161198465771579951427135989209380672556438289534
Short name T194
Test name
Test status
Simulation time 71439183 ps
CPU time 2.83 seconds
Started Nov 22 01:20:26 PM PST 23
Finished Nov 22 01:20:34 PM PST 23
Peak memory 238288 kb
Host smart-54d3c61e-87f5-486a-b2e5-76f486f0a37e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72113101226309615505698354067161198465771579951427135989209380672556438289534 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.72113101226309615505698354067161198465771579951427135989209380672556438289534
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.115586260447483004520651555291304213405051119546421270667823015155444687736951
Short name T183
Test name
Test status
Simulation time 71489183 ps
CPU time 2.61 seconds
Started Nov 22 01:19:38 PM PST 23
Finished Nov 22 01:19:47 PM PST 23
Peak memory 229972 kb
Host smart-0c5db7f8-6b9d-40eb-a201-212bec0a2f6e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115586260447483004520651555291304213405051119546421270667823015155444687736951 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.115586260447483004520651555291304213405051119546421270667823015155444687736951
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3860885933597211243364623710332652134016526586961022149103277894850995773713
Short name T12
Test name
Test status
Simulation time 225479183 ps
CPU time 4.87 seconds
Started Nov 22 01:19:51 PM PST 23
Finished Nov 22 01:20:00 PM PST 23
Peak memory 229996 kb
Host smart-ab5f8d44-ce6d-41f4-952c-c989649a6766
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860885933597211243364623710332652134016526586961022149103277894850995773713 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.3860885933597211243364623710332652134016526586961022149103277894850995773713
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.43799723034348953599290803530075234793559528016096957528935576034834444005561
Short name T84
Test name
Test status
Simulation time 64059183 ps
CPU time 1.67 seconds
Started Nov 22 01:20:34 PM PST 23
Finished Nov 22 01:20:41 PM PST 23
Peak memory 229692 kb
Host smart-3879e3c7-33d0-4402-957e-691c5064b070
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43799723034348953599290803530075234793559528016096957528935576034834444005561 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.43799723034348953599290803530075234793559528016096957528935576034834444005561
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.113926636185785656824633437575727103414259184915459095256160057334524937533390
Short name T202
Test name
Test status
Simulation time 65579183 ps
CPU time 1.92 seconds
Started Nov 22 01:19:51 PM PST 23
Finished Nov 22 01:19:57 PM PST 23
Peak memory 238384 kb
Host smart-35145176-9a3e-46fb-be4f-7194b842fef5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139266361857856568246334375757271034142591
84915459095256160057334524937533390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.113926636185
785656824633437575727103414259184915459095256160057334524937533390
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.72090363685077773638099587375734893612879379157024905781818071275322232705668
Short name T140
Test name
Test status
Simulation time 38049183 ps
CPU time 1.52 seconds
Started Nov 22 01:19:41 PM PST 23
Finished Nov 22 01:19:48 PM PST 23
Peak memory 230072 kb
Host smart-03c0643d-32d1-4711-84eb-be6f6a0cfb9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72090363685077773638099587375734893612879379157024905781818071275322232705668 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.72090363685077773638099587375734893612879379157024905781818071275322232705668
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.48902312157936459147754062906260892197957364839069550949343354318441991933580
Short name T203
Test name
Test status
Simulation time 38239183 ps
CPU time 1.32 seconds
Started Nov 22 01:20:05 PM PST 23
Finished Nov 22 01:20:09 PM PST 23
Peak memory 229792 kb
Host smart-907b9b4c-0345-44a1-990a-9ef9381322b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48902312157936459147754062906260892197957364839069550949343354318441991933580 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.48902312157936459147754062906260892197957364839069550949343354318441991933580
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.109961497438584649663462092730087778198611478394893908066955914565825802989944
Short name T155
Test name
Test status
Simulation time 35669183 ps
CPU time 1.28 seconds
Started Nov 22 01:19:49 PM PST 23
Finished Nov 22 01:19:55 PM PST 23
Peak memory 229932 kb
Host smart-120251a3-07c8-4aa1-953c-b55bae003c4f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109961497438584649663462092730087778198611478394893908066955914565825802989944 -
assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.109961497438584649663462092730087778198611478394893908066
955914565825802989944
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.76699869463819489619582265951036742641272402022655497918394785081577538178553
Short name T151
Test name
Test status
Simulation time 35669183 ps
CPU time 1.27 seconds
Started Nov 22 01:19:42 PM PST 23
Finished Nov 22 01:19:49 PM PST 23
Peak memory 229796 kb
Host smart-6999a4d7-b11e-4567-a9e8-fd83a24ff19f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76699869463819489619582265951036742641272402022655497918394785081577538178553 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.76699869463819489619582265951036742641272402022655497918394785081577538178553
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.72731487220821057679883646618355495745833122355696451842851530006814883314274
Short name T1327
Test name
Test status
Simulation time 61029183 ps
CPU time 1.99 seconds
Started Nov 22 01:19:47 PM PST 23
Finished Nov 22 01:19:54 PM PST 23
Peak memory 229988 kb
Host smart-a460078a-bbde-4b6d-8e77-abe1dceea394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72731487220821057679883646618355495745833122355696451842851530006814883314274
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.727314872208210576798836466183554957458331223556964518
42851530006814883314274
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3301869335107879195392999622517933894785908351319655190116237913765903755108
Short name T88
Test name
Test status
Simulation time 71439183 ps
CPU time 2.91 seconds
Started Nov 22 01:19:53 PM PST 23
Finished Nov 22 01:20:01 PM PST 23
Peak memory 238324 kb
Host smart-6965e639-fc78-415d-964a-24dc1d095e07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301869335107879195392999622517933894785908351319655190116237913765903755108 -assert nopostproc +UV
M_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3301869335107879195392999622517933894785908351319655190116237913765903755108
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.101281677388644724819154687235881875366057388406098296350142125453972501610630
Short name T139
Test name
Test status
Simulation time 647529183 ps
CPU time 9.63 seconds
Started Nov 22 01:19:42 PM PST 23
Finished Nov 22 01:19:58 PM PST 23
Peak memory 230384 kb
Host smart-843170c7-831c-45e4-b406-7a24227a24b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101281677388644724819154687235881875366057388406098296350142125453972501610630 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.101281677388644724819154687235881875366057388406098296350142125453972501610630
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.72256309955256697688765384885897059877184188129637298970026487195227085171586
Short name T1317
Test name
Test status
Simulation time 38239183 ps
CPU time 1.34 seconds
Started Nov 22 01:20:50 PM PST 23
Finished Nov 22 01:20:55 PM PST 23
Peak memory 229692 kb
Host smart-441cf362-d145-4a28-94c6-e0a5f833df3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72256309955256697688765384885897059877184188129637298970026487195227085171586 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.72256309955256697688765384885897059877184188129637298970026487195227085171586
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.67999372698379200479332383887040877002542349038322232917329629803176421054855
Short name T192
Test name
Test status
Simulation time 38239183 ps
CPU time 1.34 seconds
Started Nov 22 01:20:57 PM PST 23
Finished Nov 22 01:21:04 PM PST 23
Peak memory 229800 kb
Host smart-13b01a18-5c92-4409-bb2c-0c5ec933b009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67999372698379200479332383887040877002542349038322232917329629803176421054855 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.67999372698379200479332383887040877002542349038322232917329629803176421054855
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.11749659022454789483569755639881753570002145860821923708704988215264060253027
Short name T1323
Test name
Test status
Simulation time 38239183 ps
CPU time 1.33 seconds
Started Nov 22 01:20:34 PM PST 23
Finished Nov 22 01:20:41 PM PST 23
Peak memory 229716 kb
Host smart-519cea71-219d-4ee5-949d-c3ae4279152f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11749659022454789483569755639881753570002145860821923708704988215264060253027 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.11749659022454789483569755639881753570002145860821923708704988215264060253027
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.57372470930281257220234098639405342551631503839511115672844282192413081061812
Short name T135
Test name
Test status
Simulation time 38239183 ps
CPU time 1.36 seconds
Started Nov 22 01:20:22 PM PST 23
Finished Nov 22 01:20:27 PM PST 23
Peak memory 229768 kb
Host smart-ca27efa7-8168-4eed-ac77-395ef58c098b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57372470930281257220234098639405342551631503839511115672844282192413081061812 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.57372470930281257220234098639405342551631503839511115672844282192413081061812
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.71976204887658686554089920294591149544758315851003938543956388262628720789568
Short name T207
Test name
Test status
Simulation time 38239183 ps
CPU time 1.36 seconds
Started Nov 22 01:20:23 PM PST 23
Finished Nov 22 01:20:28 PM PST 23
Peak memory 229732 kb
Host smart-e3e8a479-c55c-49f2-98ec-8698eb1f455c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71976204887658686554089920294591149544758315851003938543956388262628720789568 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.71976204887658686554089920294591149544758315851003938543956388262628720789568
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.113198206700033918650500969790366682482952252513825219383634738497324677227936
Short name T114
Test name
Test status
Simulation time 38239183 ps
CPU time 1.3 seconds
Started Nov 22 01:20:49 PM PST 23
Finished Nov 22 01:20:54 PM PST 23
Peak memory 229808 kb
Host smart-34865bcf-dcf0-4412-bf96-a0197ed9b655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113198206700033918650500969790366682482952252513825219383634738497324677227936 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.113198206700033918650500969790366682482952252513825219383634738497324677227936
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.676311569422074921475780485613788151414024281900240476333084622333232516091
Short name T181
Test name
Test status
Simulation time 38239183 ps
CPU time 1.32 seconds
Started Nov 22 01:20:10 PM PST 23
Finished Nov 22 01:20:12 PM PST 23
Peak memory 229744 kb
Host smart-30cf3d60-d084-4fd1-a7cc-7afa1791e84b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676311569422074921475780485613788151414024281900240476333084622333232516091 -assert nopostproc +UVM
_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.676311569422074921475780485613788151414024281900240476333084622333232516091
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.43156188443581959627660342765977062300969410857698017192914219059519926021366
Short name T147
Test name
Test status
Simulation time 38239183 ps
CPU time 1.34 seconds
Started Nov 22 01:20:21 PM PST 23
Finished Nov 22 01:20:26 PM PST 23
Peak memory 229792 kb
Host smart-aaa2a0fb-1a59-4271-882f-38294847e8cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43156188443581959627660342765977062300969410857698017192914219059519926021366 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.43156188443581959627660342765977062300969410857698017192914219059519926021366
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.74465927829223613760999534541507110593518504896344798473380839792359568136356
Short name T1331
Test name
Test status
Simulation time 38239183 ps
CPU time 1.33 seconds
Started Nov 22 01:20:20 PM PST 23
Finished Nov 22 01:20:24 PM PST 23
Peak memory 229780 kb
Host smart-008b144a-8868-460a-8107-1299cfe85d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74465927829223613760999534541507110593518504896344798473380839792359568136356 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.74465927829223613760999534541507110593518504896344798473380839792359568136356
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.93875256662975127669850840746134665871422289448130713068843195664959599689864
Short name T178
Test name
Test status
Simulation time 38239183 ps
CPU time 1.38 seconds
Started Nov 22 01:20:50 PM PST 23
Finished Nov 22 01:20:55 PM PST 23
Peak memory 229780 kb
Host smart-88810659-9df7-42fd-9a5e-b45bc669fef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93875256662975127669850840746134665871422289448130713068843195664959599689864 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.93875256662975127669850840746134665871422289448130713068843195664959599689864
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.55688189815216306288548756929731239182126937353941142118949212261935643851063
Short name T81
Test name
Test status
Simulation time 71489183 ps
CPU time 2.58 seconds
Started Nov 22 01:20:06 PM PST 23
Finished Nov 22 01:20:10 PM PST 23
Peak memory 230032 kb
Host smart-11d177ff-2cc2-4cab-b5ce-bde8df62d9db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55688189815216306288548756929731239182126937353941142118949212261935643851063 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.55688189815216306288548756929731239182126937353941142118949212261935643851063
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.75293676537855462607363575471308890189177601236649166262804828992114536456234
Short name T127
Test name
Test status
Simulation time 225479183 ps
CPU time 4.99 seconds
Started Nov 22 01:20:03 PM PST 23
Finished Nov 22 01:20:09 PM PST 23
Peak memory 230036 kb
Host smart-d8505e9c-6daf-49fd-b558-2a1ef2179d48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75293676537855462607363575471308890189177601236649166262804828992114536456234 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.75293676537855462607363575471308890189177601236649166262804828992114536456234
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.96412400679311556628116239099079734367102886475789622184797557476114505460002
Short name T165
Test name
Test status
Simulation time 64059183 ps
CPU time 1.93 seconds
Started Nov 22 01:20:15 PM PST 23
Finished Nov 22 01:20:18 PM PST 23
Peak memory 230064 kb
Host smart-aae8e013-1d42-4281-a5a6-ef31f22c63f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96412400679311556628116239099079734367102886475789622184797557476114505460002 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.96412400679311556628116239099079734367102886475789622184797557476114505460002
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.55370307328400154914717389621392110472295164722283156672085125051837790871735
Short name T173
Test name
Test status
Simulation time 65579183 ps
CPU time 1.9 seconds
Started Nov 22 01:19:58 PM PST 23
Finished Nov 22 01:20:03 PM PST 23
Peak memory 238352 kb
Host smart-66176026-817d-46b2-b397-a53ec6364cae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5537030732840015491471738962139211047229516
4722283156672085125051837790871735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.5537030732840
0154914717389621392110472295164722283156672085125051837790871735
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.98332818781444922560512298375195800166454484991897378457148892001198860421467
Short name T1337
Test name
Test status
Simulation time 38049183 ps
CPU time 1.46 seconds
Started Nov 22 01:20:14 PM PST 23
Finished Nov 22 01:20:17 PM PST 23
Peak memory 230104 kb
Host smart-c115205e-b628-403a-a088-51acdc00cfa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98332818781444922560512298375195800166454484991897378457148892001198860421467 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.98332818781444922560512298375195800166454484991897378457148892001198860421467
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.65255765765178040930316023200318754068446301095403482252073640491257522795787
Short name T137
Test name
Test status
Simulation time 38239183 ps
CPU time 1.33 seconds
Started Nov 22 01:20:03 PM PST 23
Finished Nov 22 01:20:06 PM PST 23
Peak memory 229796 kb
Host smart-2a504430-8660-4521-9fd3-aa0ab5a09810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65255765765178040930316023200318754068446301095403482252073640491257522795787 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.65255765765178040930316023200318754068446301095403482252073640491257522795787
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2517762900033621331190811191079276073718038905835275348864364120747580139581
Short name T1328
Test name
Test status
Simulation time 35669183 ps
CPU time 1.33 seconds
Started Nov 22 01:20:20 PM PST 23
Finished Nov 22 01:20:23 PM PST 23
Peak memory 229872 kb
Host smart-48233091-94e5-4ed5-ba07-6aaba4a16846
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517762900033621331190811191079276073718038905835275348864364120747580139581 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.25177629000336213311908111910792760737180389058352753488643
64120747580139581
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.15612598917559419836852107857193542599234020793720708372170912954227571625194
Short name T215
Test name
Test status
Simulation time 35669183 ps
CPU time 1.29 seconds
Started Nov 22 01:20:16 PM PST 23
Finished Nov 22 01:20:18 PM PST 23
Peak memory 229908 kb
Host smart-bacf5954-7b72-4006-a53e-2fa9b80d2a4f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15612598917559419836852107857193542599234020793720708372170912954227571625194 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.15612598917559419836852107857193542599234020793720708372170912954227571625194
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.62443228717125569531747865178034753054219505796482026927116746246597456358424
Short name T1313
Test name
Test status
Simulation time 61029183 ps
CPU time 1.99 seconds
Started Nov 22 01:20:04 PM PST 23
Finished Nov 22 01:20:07 PM PST 23
Peak memory 230200 kb
Host smart-74658128-99bd-4a60-99a4-5a891c2f56b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62443228717125569531747865178034753054219505796482026927116746246597456358424
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.624432287171255695317478651780347530542195057964820269
27116746246597456358424
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.36920181420177692664769108128634283434541388011950083696972799747257734808349
Short name T144
Test name
Test status
Simulation time 71439183 ps
CPU time 3.04 seconds
Started Nov 22 01:19:59 PM PST 23
Finished Nov 22 01:20:05 PM PST 23
Peak memory 238336 kb
Host smart-0f7feb02-be3f-4628-929a-796cf5f55dae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36920181420177692664769108128634283434541388011950083696972799747257734808349 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.36920181420177692664769108128634283434541388011950083696972799747257734808349
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.3669306012077998658714226550926898409692430452822872356671443490784635596008
Short name T1339
Test name
Test status
Simulation time 647529183 ps
CPU time 9.33 seconds
Started Nov 22 01:19:48 PM PST 23
Finished Nov 22 01:20:02 PM PST 23
Peak memory 230188 kb
Host smart-12b5fee7-0ddb-44e0-bd42-d2d036b7aca4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669306012077998658714226550926898409692430452822872356671443490784635596008 -assert no
postproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.3669306012077998658714226550926898409692430452822872356671443490784635596008
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.42589369146246848513798903322842771245590193054036668835073857549133636177203
Short name T126
Test name
Test status
Simulation time 38239183 ps
CPU time 1.33 seconds
Started Nov 22 01:20:45 PM PST 23
Finished Nov 22 01:20:49 PM PST 23
Peak memory 229792 kb
Host smart-12b6da47-dfa1-4e56-b672-64a1eac56269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42589369146246848513798903322842771245590193054036668835073857549133636177203 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.42589369146246848513798903322842771245590193054036668835073857549133636177203
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.112026002812315663236272681495748395852512657563936509326885882128361532970909
Short name T179
Test name
Test status
Simulation time 38239183 ps
CPU time 1.31 seconds
Started Nov 22 01:20:07 PM PST 23
Finished Nov 22 01:20:10 PM PST 23
Peak memory 229864 kb
Host smart-0ab18f2f-74d5-4836-94a7-1dba3000b8a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112026002812315663236272681495748395852512657563936509326885882128361532970909 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.112026002812315663236272681495748395852512657563936509326885882128361532970909
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.87586924748604521216094779003666559959289334357727652378267304308535917159092
Short name T11
Test name
Test status
Simulation time 38239183 ps
CPU time 1.29 seconds
Started Nov 22 01:20:20 PM PST 23
Finished Nov 22 01:20:23 PM PST 23
Peak memory 229796 kb
Host smart-9ba56259-2d0a-4e3e-9041-d96e021cd842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87586924748604521216094779003666559959289334357727652378267304308535917159092 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.87586924748604521216094779003666559959289334357727652378267304308535917159092
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.73033085480211462012777683905871213031961073765228156912071345046572546703779
Short name T146
Test name
Test status
Simulation time 38239183 ps
CPU time 1.35 seconds
Started Nov 22 01:20:27 PM PST 23
Finished Nov 22 01:20:35 PM PST 23
Peak memory 229696 kb
Host smart-bf47432d-3c64-4765-afb0-3136a7169bbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73033085480211462012777683905871213031961073765228156912071345046572546703779 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.73033085480211462012777683905871213031961073765228156912071345046572546703779
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.14945195968038763328206475814707935153866880738627859122546909478402691502596
Short name T195
Test name
Test status
Simulation time 38239183 ps
CPU time 1.38 seconds
Started Nov 22 01:20:21 PM PST 23
Finished Nov 22 01:20:25 PM PST 23
Peak memory 229788 kb
Host smart-f0463dd3-62e3-46c8-b6e0-a273c84828a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14945195968038763328206475814707935153866880738627859122546909478402691502596 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.14945195968038763328206475814707935153866880738627859122546909478402691502596
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.75481116570393615054513576005767260231223955991985590561782466113571462268536
Short name T130
Test name
Test status
Simulation time 38239183 ps
CPU time 1.38 seconds
Started Nov 22 01:20:33 PM PST 23
Finished Nov 22 01:20:40 PM PST 23
Peak memory 229764 kb
Host smart-cc8647f3-49e8-4243-b1df-1d8fb0588751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75481116570393615054513576005767260231223955991985590561782466113571462268536 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.75481116570393615054513576005767260231223955991985590561782466113571462268536
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.109765366046965077879394043669655938830701902194833277492145291744898189233451
Short name T132
Test name
Test status
Simulation time 38239183 ps
CPU time 1.33 seconds
Started Nov 22 01:20:20 PM PST 23
Finished Nov 22 01:20:23 PM PST 23
Peak memory 229788 kb
Host smart-1d334a45-5eaf-493b-bd57-922d24b9c5f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109765366046965077879394043669655938830701902194833277492145291744898189233451 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.109765366046965077879394043669655938830701902194833277492145291744898189233451
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.55437214420612522856866085804488134584084661402283017851232558900359962324698
Short name T189
Test name
Test status
Simulation time 38239183 ps
CPU time 1.3 seconds
Started Nov 22 01:20:42 PM PST 23
Finished Nov 22 01:20:46 PM PST 23
Peak memory 229776 kb
Host smart-7f02415e-1099-452e-ae65-cfb904f7df9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55437214420612522856866085804488134584084661402283017851232558900359962324698 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.55437214420612522856866085804488134584084661402283017851232558900359962324698
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.11086060615001368423733641679371743134657630737134904092103585990970120415674
Short name T185
Test name
Test status
Simulation time 38239183 ps
CPU time 1.28 seconds
Started Nov 22 01:20:45 PM PST 23
Finished Nov 22 01:20:49 PM PST 23
Peak memory 229656 kb
Host smart-7ac7968e-9f54-458d-b04d-ba6f38e35b1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11086060615001368423733641679371743134657630737134904092103585990970120415674 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.11086060615001368423733641679371743134657630737134904092103585990970120415674
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.83418954887451562424495213815114168358687471593763949060271574738554141972905
Short name T107
Test name
Test status
Simulation time 71489183 ps
CPU time 2.59 seconds
Started Nov 22 01:20:16 PM PST 23
Finished Nov 22 01:20:20 PM PST 23
Peak memory 229936 kb
Host smart-8c4283ab-5e22-4114-b1c7-5a9663c36b0c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83418954887451562424495213815114168358687471593763949060271574738554141972905 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.83418954887451562424495213815114168358687471593763949060271574738554141972905
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.46340425363419128000028888814630730551244126442977603555816229164430978588888
Short name T1332
Test name
Test status
Simulation time 225479183 ps
CPU time 5.02 seconds
Started Nov 22 01:20:18 PM PST 23
Finished Nov 22 01:20:24 PM PST 23
Peak memory 230032 kb
Host smart-5f04d1bf-b436-48b6-97fe-38d311ca8f8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46340425363419128000028888814630730551244126442977603555816229164430978588888 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.46340425363419128000028888814630730551244126442977603555816229164430978588888
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.112200525303960006200978671150944303294439703837404031701956228422064472382812
Short name T82
Test name
Test status
Simulation time 64059183 ps
CPU time 1.8 seconds
Started Nov 22 01:20:09 PM PST 23
Finished Nov 22 01:20:12 PM PST 23
Peak memory 230120 kb
Host smart-7664d2c8-3d41-4d22-8193-a621c51873de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112200525303960006200978671150944303294439703837404031701956228422064472382812 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.112200525303960006200978671150944303294439703837404031701956228422064472382812
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.17987490752812537529953334334523183063637255684781440122974013808250664602992
Short name T1325
Test name
Test status
Simulation time 65579183 ps
CPU time 1.92 seconds
Started Nov 22 01:20:20 PM PST 23
Finished Nov 22 01:20:24 PM PST 23
Peak memory 238404 kb
Host smart-eded87ed-d6ac-4df0-b20d-43225530dcac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798749075281253752995333433452318306363725
5684781440122974013808250664602992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.1798749075281
2537529953334334523183063637255684781440122974013808250664602992
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.58153768145850163679754993306443217298116138781070347630531756363822115322355
Short name T166
Test name
Test status
Simulation time 38049183 ps
CPU time 1.43 seconds
Started Nov 22 01:20:08 PM PST 23
Finished Nov 22 01:20:11 PM PST 23
Peak memory 229996 kb
Host smart-5d550765-970b-4453-875f-ffd0035fb514
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58153768145850163679754993306443217298116138781070347630531756363822115322355 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.58153768145850163679754993306443217298116138781070347630531756363822115322355
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.24540650164672867214958567821695214933982365108395062629314107438283779585834
Short name T190
Test name
Test status
Simulation time 38239183 ps
CPU time 1.29 seconds
Started Nov 22 01:21:18 PM PST 23
Finished Nov 22 01:21:21 PM PST 23
Peak memory 229324 kb
Host smart-2fec67c3-b7f0-49ed-96dc-ec4be55dcbfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24540650164672867214958567821695214933982365108395062629314107438283779585834 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.24540650164672867214958567821695214933982365108395062629314107438283779585834
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.70747613631385762889477387449094990503234062381770440938542765170115168156402
Short name T186
Test name
Test status
Simulation time 35669183 ps
CPU time 1.45 seconds
Started Nov 22 01:20:50 PM PST 23
Finished Nov 22 01:20:55 PM PST 23
Peak memory 229848 kb
Host smart-0bac1ac7-19d2-4059-81be-784932592499
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70747613631385762889477387449094990503234062381770440938542765170115168156402 -a
ssert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.7074761363138576288947738744909499050323406238177044093854
2765170115168156402
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.57073336226464736072322076817332704396048285199663879088506624821548204715411
Short name T154
Test name
Test status
Simulation time 35669183 ps
CPU time 1.34 seconds
Started Nov 22 01:20:03 PM PST 23
Finished Nov 22 01:20:06 PM PST 23
Peak memory 229852 kb
Host smart-5ead5ccf-47da-4da3-a141-dbc88d9ba067
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57073336226464736072322076817332704396048285199663879088506624821548204715411 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.57073336226464736072322076817332704396048285199663879088506624821548204715411
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.52552749945887374565655598551325540819781874190001404205608891293162042450558
Short name T117
Test name
Test status
Simulation time 61029183 ps
CPU time 2.12 seconds
Started Nov 22 01:20:16 PM PST 23
Finished Nov 22 01:20:20 PM PST 23
Peak memory 230024 kb
Host smart-abfc69ac-fba4-4bd6-a30f-d20ec191025f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52552749945887374565655598551325540819781874190001404205608891293162042450558
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.525527499458873745656555985513255408197818741900014042
05608891293162042450558
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.78291528931573151002759707442210423993184384584828405279815995321199654140478
Short name T104
Test name
Test status
Simulation time 71439183 ps
CPU time 2.99 seconds
Started Nov 22 01:20:05 PM PST 23
Finished Nov 22 01:20:10 PM PST 23
Peak memory 238404 kb
Host smart-04795a2d-fb48-447e-8de7-21acc82faaad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78291528931573151002759707442210423993184384584828405279815995321199654140478 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.78291528931573151002759707442210423993184384584828405279815995321199654140478
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.34919311004528725151304472242424735643203662427350573357474569540439149616398
Short name T8
Test name
Test status
Simulation time 647529183 ps
CPU time 9.5 seconds
Started Nov 22 01:20:20 PM PST 23
Finished Nov 22 01:20:32 PM PST 23
Peak memory 230384 kb
Host smart-6155a33e-4f02-45fc-8317-881959ea114b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34919311004528725151304472242424735643203662427350573357474569540439149616398 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.34919311004528725151304472242424735643203662427350573357474569540439149616398
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.62916026539250811965611292456545225649585267882976130376319056815946993512770
Short name T17
Test name
Test status
Simulation time 38239183 ps
CPU time 1.35 seconds
Started Nov 22 01:20:56 PM PST 23
Finished Nov 22 01:21:02 PM PST 23
Peak memory 229828 kb
Host smart-87b4991e-43aa-41d2-8a04-4f16de43d5d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62916026539250811965611292456545225649585267882976130376319056815946993512770 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.62916026539250811965611292456545225649585267882976130376319056815946993512770
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.12420607050775210916517087625028977068179950246913482887225390703885676018429
Short name T211
Test name
Test status
Simulation time 38239183 ps
CPU time 1.31 seconds
Started Nov 22 01:20:46 PM PST 23
Finished Nov 22 01:20:51 PM PST 23
Peak memory 229656 kb
Host smart-d8e11013-9975-4a96-9cb0-11bf2bcfc95a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12420607050775210916517087625028977068179950246913482887225390703885676018429 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.12420607050775210916517087625028977068179950246913482887225390703885676018429
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.114553156850663877911370874898902037548766701040743847020594709314338960660884
Short name T169
Test name
Test status
Simulation time 38239183 ps
CPU time 1.31 seconds
Started Nov 22 01:20:19 PM PST 23
Finished Nov 22 01:20:22 PM PST 23
Peak memory 229792 kb
Host smart-b65cb669-e66c-4d0c-b054-7e6edffa5191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114553156850663877911370874898902037548766701040743847020594709314338960660884 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.114553156850663877911370874898902037548766701040743847020594709314338960660884
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.9536720609508355550779677284818174593111411612896748789986413800329421909242
Short name T176
Test name
Test status
Simulation time 38239183 ps
CPU time 1.28 seconds
Started Nov 22 01:20:22 PM PST 23
Finished Nov 22 01:20:27 PM PST 23
Peak memory 229736 kb
Host smart-70763f63-df96-4f88-9e04-2e5b53796bca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9536720609508355550779677284818174593111411612896748789986413800329421909242 -assert nopostproc +UV
M_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.9536720609508355550779677284818174593111411612896748789986413800329421909242
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.90737894344538342540092206376559237108930947669962102114873086077206851336983
Short name T1338
Test name
Test status
Simulation time 38239183 ps
CPU time 1.38 seconds
Started Nov 22 01:20:34 PM PST 23
Finished Nov 22 01:20:41 PM PST 23
Peak memory 229764 kb
Host smart-12aa1603-27bd-4840-85d2-03b1a7c8a0a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90737894344538342540092206376559237108930947669962102114873086077206851336983 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.90737894344538342540092206376559237108930947669962102114873086077206851336983
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.85701296202742691599696374256403887522886050525629620464342599954532874791533
Short name T13
Test name
Test status
Simulation time 38239183 ps
CPU time 1.32 seconds
Started Nov 22 01:20:24 PM PST 23
Finished Nov 22 01:20:29 PM PST 23
Peak memory 229804 kb
Host smart-33d66967-1347-428e-9e70-4f9d2eb8a4cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85701296202742691599696374256403887522886050525629620464342599954532874791533 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.85701296202742691599696374256403887522886050525629620464342599954532874791533
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.32410281896923060888686156259560157904644369892136372242908781070318997831391
Short name T205
Test name
Test status
Simulation time 38239183 ps
CPU time 1.34 seconds
Started Nov 22 01:20:51 PM PST 23
Finished Nov 22 01:20:56 PM PST 23
Peak memory 229664 kb
Host smart-0f79e61a-6623-4a96-a609-4b840149b505
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32410281896923060888686156259560157904644369892136372242908781070318997831391 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.32410281896923060888686156259560157904644369892136372242908781070318997831391
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.69446589195465109864652221667918887802000278873853305166092938829488410820949
Short name T1343
Test name
Test status
Simulation time 38239183 ps
CPU time 1.33 seconds
Started Nov 22 01:20:21 PM PST 23
Finished Nov 22 01:20:25 PM PST 23
Peak memory 229756 kb
Host smart-88c82ce6-f189-4e50-84b5-55775cf3feeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69446589195465109864652221667918887802000278873853305166092938829488410820949 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.69446589195465109864652221667918887802000278873853305166092938829488410820949
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.55366660784061517032422559724106057872668575555880091171808989153756950101793
Short name T159
Test name
Test status
Simulation time 38239183 ps
CPU time 1.29 seconds
Started Nov 22 01:20:20 PM PST 23
Finished Nov 22 01:20:24 PM PST 23
Peak memory 229764 kb
Host smart-1e5c24e4-3830-43fd-9a25-c3df98bd8516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55366660784061517032422559724106057872668575555880091171808989153756950101793 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.55366660784061517032422559724106057872668575555880091171808989153756950101793
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.45488974296196440035826785661584134510231674907874096359833897850664334231921
Short name T148
Test name
Test status
Simulation time 38239183 ps
CPU time 1.4 seconds
Started Nov 22 01:20:24 PM PST 23
Finished Nov 22 01:20:29 PM PST 23
Peak memory 229696 kb
Host smart-aa4258dc-2e24-4fc2-aca3-50028baceaed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45488974296196440035826785661584134510231674907874096359833897850664334231921 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.45488974296196440035826785661584134510231674907874096359833897850664334231921
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.110290127281651883722141551152041566581308586843948935826005606971585362026289
Short name T143
Test name
Test status
Simulation time 65579183 ps
CPU time 1.85 seconds
Started Nov 22 01:20:07 PM PST 23
Finished Nov 22 01:20:10 PM PST 23
Peak memory 238240 kb
Host smart-8410d777-4bd7-480f-9d7f-4287e2d171bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102901272816518837221415511520415665813085
86843948935826005606971585362026289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.110290127281
651883722141551152041566581308586843948935826005606971585362026289
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.32364583720625619045603082665485791187924478748058240561600720192722590791543
Short name T110
Test name
Test status
Simulation time 38049183 ps
CPU time 1.38 seconds
Started Nov 22 01:20:03 PM PST 23
Finished Nov 22 01:20:05 PM PST 23
Peak memory 229876 kb
Host smart-63b01b20-0f3a-4f7d-bdb1-049c669a305d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32364583720625619045603082665485791187924478748058240561600720192722590791543 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.32364583720625619045603082665485791187924478748058240561600720192722590791543
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.63671967261396945824461184912770677215909946508966094312965917399473779013648
Short name T172
Test name
Test status
Simulation time 38239183 ps
CPU time 1.33 seconds
Started Nov 22 01:20:23 PM PST 23
Finished Nov 22 01:20:27 PM PST 23
Peak memory 229784 kb
Host smart-b238cc60-fd94-4d41-af43-91652f6194c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63671967261396945824461184912770677215909946508966094312965917399473779013648 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.63671967261396945824461184912770677215909946508966094312965917399473779013648
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.51432454206774229303038165338274792015088861888430986716556740655951156237319
Short name T121
Test name
Test status
Simulation time 61029183 ps
CPU time 2.07 seconds
Started Nov 22 01:20:03 PM PST 23
Finished Nov 22 01:20:06 PM PST 23
Peak memory 230232 kb
Host smart-87f30222-428e-4afc-a3da-0913a141a3b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51432454206774229303038165338274792015088861888430986716556740655951156237319
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.514324542067742293030381653382747920150888618884309867
16556740655951156237319
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.43944176953258080849099835407530622791959435419377081317254351156638448520760
Short name T1329
Test name
Test status
Simulation time 71439183 ps
CPU time 2.76 seconds
Started Nov 22 01:20:25 PM PST 23
Finished Nov 22 01:20:31 PM PST 23
Peak memory 238352 kb
Host smart-788e47fc-386e-496a-a82f-53347a5e8d07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43944176953258080849099835407530622791959435419377081317254351156638448520760 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.43944176953258080849099835407530622791959435419377081317254351156638448520760
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.22583921374868439682297882132017888185940393617399597022719557689387196549126
Short name T9
Test name
Test status
Simulation time 647529183 ps
CPU time 9.45 seconds
Started Nov 22 01:20:13 PM PST 23
Finished Nov 22 01:20:24 PM PST 23
Peak memory 230348 kb
Host smart-4d5210e7-878c-4755-ade1-64b9db43d204
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22583921374868439682297882132017888185940393617399597022719557689387196549126 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.22583921374868439682297882132017888185940393617399597022719557689387196549126
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.44730404118200829670677715862546116758477757570088854613406677662035488260109
Short name T184
Test name
Test status
Simulation time 65579183 ps
CPU time 1.89 seconds
Started Nov 22 01:20:04 PM PST 23
Finished Nov 22 01:20:08 PM PST 23
Peak memory 238428 kb
Host smart-00828c31-823e-484b-a268-69d7e7cc9e22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4473040411820082967067771586254611675847775
7570088854613406677662035488260109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.4473040411820
0829670677715862546116758477757570088854613406677662035488260109
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.17714834864652337450840263596458326835306922795431289443980785868132511473104
Short name T188
Test name
Test status
Simulation time 38049183 ps
CPU time 1.46 seconds
Started Nov 22 01:20:20 PM PST 23
Finished Nov 22 01:20:23 PM PST 23
Peak memory 230072 kb
Host smart-c63ebfc8-2a74-4312-90c1-d905b58a15b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17714834864652337450840263596458326835306922795431289443980785868132511473104 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.17714834864652337450840263596458326835306922795431289443980785868132511473104
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.58872378862331515034460574959325904529879505894305266035553826031369056741215
Short name T187
Test name
Test status
Simulation time 38239183 ps
CPU time 1.37 seconds
Started Nov 22 01:20:15 PM PST 23
Finished Nov 22 01:20:17 PM PST 23
Peak memory 229780 kb
Host smart-ed7dabea-12ff-4469-92c2-b76d79fa738d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58872378862331515034460574959325904529879505894305266035553826031369056741215 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.58872378862331515034460574959325904529879505894305266035553826031369056741215
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.89272794445197100014965833299090263958748463178688298478034245339627492282622
Short name T120
Test name
Test status
Simulation time 61029183 ps
CPU time 1.95 seconds
Started Nov 22 01:20:03 PM PST 23
Finished Nov 22 01:20:06 PM PST 23
Peak memory 229988 kb
Host smart-ce803261-6d4c-4bfd-8c69-e26b2198e1d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89272794445197100014965833299090263958748463178688298478034245339627492282622
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.892727944451971000149658332990902639587484631786882984
78034245339627492282622
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.101123071654209352977762814908170651108671301049189920859295844872267807070510
Short name T170
Test name
Test status
Simulation time 71439183 ps
CPU time 2.78 seconds
Started Nov 22 01:21:21 PM PST 23
Finished Nov 22 01:21:28 PM PST 23
Peak memory 238124 kb
Host smart-b9520b0a-ba5a-45ad-b9d9-0991b67c7afc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101123071654209352977762814908170651108671301049189920859295844872267807070510 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.101123071654209352977762814908170651108671301049189920859295844872267807070510
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.31854247491652785599612176318078349514538668584162397344454465345380400712405
Short name T113
Test name
Test status
Simulation time 647529183 ps
CPU time 9.44 seconds
Started Nov 22 01:20:20 PM PST 23
Finished Nov 22 01:20:31 PM PST 23
Peak memory 230352 kb
Host smart-d4522de1-80ad-4402-9f9f-767981bd6ec1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31854247491652785599612176318078349514538668584162397344454465345380400712405 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.31854247491652785599612176318078349514538668584162397344454465345380400712405
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.2250976601563543140371553582115814580627960701396097132150242626113295093485
Short name T87
Test name
Test status
Simulation time 65579183 ps
CPU time 1.92 seconds
Started Nov 22 01:21:16 PM PST 23
Finished Nov 22 01:21:21 PM PST 23
Peak memory 236716 kb
Host smart-cdb94bd2-71a0-42e8-884d-98822a41697e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250976601563543140371553582115814580627960
701396097132150242626113295093485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.22509766015635
43140371553582115814580627960701396097132150242626113295093485
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.8943405100852652011605691485219666418447984050641225239618121898860955457726
Short name T209
Test name
Test status
Simulation time 38049183 ps
CPU time 1.53 seconds
Started Nov 22 01:21:36 PM PST 23
Finished Nov 22 01:21:46 PM PST 23
Peak memory 229984 kb
Host smart-84672a72-7fe1-4618-af0c-bc49811564db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8943405100852652011605691485219666418447984050641225239618121898860955457726 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.8943405100852652011605691485219666418447984050641225239618121898860955457726
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.3818442899370862567389361136959478901726586944495715253279088286153817447897
Short name T136
Test name
Test status
Simulation time 38239183 ps
CPU time 1.41 seconds
Started Nov 22 01:20:11 PM PST 23
Finished Nov 22 01:20:13 PM PST 23
Peak memory 229776 kb
Host smart-3101ef2b-72a8-40df-9252-2da7d6ce4bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818442899370862567389361136959478901726586944495715253279088286153817447897 -assert nopostproc +UV
M_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3818442899370862567389361136959478901726586944495715253279088286153817447897
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.103183084705187880475473276266262527093118007342702465883117633161212803698633
Short name T212
Test name
Test status
Simulation time 61029183 ps
CPU time 1.9 seconds
Started Nov 22 01:21:32 PM PST 23
Finished Nov 22 01:21:40 PM PST 23
Peak memory 230084 kb
Host smart-5265dca2-c3ea-4865-9157-eac56e989cb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103183084705187880475473276266262527093118007342702465883117633161212803698633
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.10318308470518788047547327626626252709311800734270246
5883117633161212803698633
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.90345076499512321260047439625559717855389689183983997945493021398739908344173
Short name T1322
Test name
Test status
Simulation time 71439183 ps
CPU time 2.81 seconds
Started Nov 22 01:20:13 PM PST 23
Finished Nov 22 01:20:17 PM PST 23
Peak memory 238368 kb
Host smart-c006d431-8e96-41fc-a6f3-69d2e338035e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90345076499512321260047439625559717855389689183983997945493021398739908344173 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.90345076499512321260047439625559717855389689183983997945493021398739908344173
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.108341059313299967036293367751598941738864773383107573831652873664799589830739
Short name T164
Test name
Test status
Simulation time 647529183 ps
CPU time 8.85 seconds
Started Nov 22 01:21:20 PM PST 23
Finished Nov 22 01:21:33 PM PST 23
Peak memory 230112 kb
Host smart-476f953f-d62c-4b84-ad60-a92c132dc5c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108341059313299967036293367751598941738864773383107573831652873664799589830739 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.108341059313299967036293367751598941738864773383107573831652873664799589830739
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2523138883870511396662455203669007361562155152079776281571916949398764375926
Short name T197
Test name
Test status
Simulation time 65579183 ps
CPU time 1.96 seconds
Started Nov 22 01:20:26 PM PST 23
Finished Nov 22 01:20:32 PM PST 23
Peak memory 238352 kb
Host smart-cafb4f9f-53a5-4d16-9c57-a1c248d19ab5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523138883870511396662455203669007361562155
152079776281571916949398764375926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.25231388838705
11396662455203669007361562155152079776281571916949398764375926
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.34803482859161952209991158740788456675392702662615709388439951817984296226865
Short name T201
Test name
Test status
Simulation time 38049183 ps
CPU time 1.43 seconds
Started Nov 22 01:20:23 PM PST 23
Finished Nov 22 01:20:28 PM PST 23
Peak memory 230088 kb
Host smart-4847d577-c493-4450-a5fb-820be51fea4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34803482859161952209991158740788456675392702662615709388439951817984296226865 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.34803482859161952209991158740788456675392702662615709388439951817984296226865
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.3555337258606438162638502924357826461788162514243866642887143620999472035301
Short name T131
Test name
Test status
Simulation time 38239183 ps
CPU time 1.3 seconds
Started Nov 22 01:20:21 PM PST 23
Finished Nov 22 01:20:25 PM PST 23
Peak memory 229780 kb
Host smart-61e63b48-dc39-404e-b116-8b26f807ab69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555337258606438162638502924357826461788162514243866642887143620999472035301 -assert nopostproc +UV
M_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.3555337258606438162638502924357826461788162514243866642887143620999472035301
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.64614726892785732394616072380664226441499355753733794869150161612419155555902
Short name T182
Test name
Test status
Simulation time 61029183 ps
CPU time 2 seconds
Started Nov 22 01:20:27 PM PST 23
Finished Nov 22 01:20:35 PM PST 23
Peak memory 230092 kb
Host smart-43506453-0f3f-4df4-a68d-00a4dff085e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64614726892785732394616072380664226441499355753733794869150161612419155555902
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.646147268927857323946160723806642264414993557537337948
69150161612419155555902
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.59427881826166309184731243255731508778446304048159729647380522994664266455532
Short name T153
Test name
Test status
Simulation time 71439183 ps
CPU time 2.78 seconds
Started Nov 22 01:21:17 PM PST 23
Finished Nov 22 01:21:22 PM PST 23
Peak memory 236728 kb
Host smart-1cf69720-bfc6-471b-963f-8262e12d51dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59427881826166309184731243255731508778446304048159729647380522994664266455532 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.59427881826166309184731243255731508778446304048159729647380522994664266455532
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.21291861987008384260179310187383462537613577181826944167118991527650218183835
Short name T4
Test name
Test status
Simulation time 647529183 ps
CPU time 9.61 seconds
Started Nov 22 01:20:21 PM PST 23
Finished Nov 22 01:20:35 PM PST 23
Peak memory 230388 kb
Host smart-6b900b39-c90e-4f3a-8bc4-abef060d7fd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21291861987008384260179310187383462537613577181826944167118991527650218183835 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.21291861987008384260179310187383462537613577181826944167118991527650218183835
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.108038236776969580199206991043627156237741353802965578581884353384465697658236
Short name T158
Test name
Test status
Simulation time 65579183 ps
CPU time 1.86 seconds
Started Nov 22 01:20:25 PM PST 23
Finished Nov 22 01:20:31 PM PST 23
Peak memory 238400 kb
Host smart-16e256de-6ae9-4cb5-9638-91cd5a9dbacc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080382367769695801992069910436271562377413
53802965578581884353384465697658236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.108038236776
969580199206991043627156237741353802965578581884353384465697658236
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.68017710840208018128283920480645065789961539959354957463803835814099327698645
Short name T105
Test name
Test status
Simulation time 38049183 ps
CPU time 1.46 seconds
Started Nov 22 01:20:45 PM PST 23
Finished Nov 22 01:20:49 PM PST 23
Peak memory 230080 kb
Host smart-465ef9ac-03ab-4716-9e00-387897e8ded5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68017710840208018128283920480645065789961539959354957463803835814099327698645 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.68017710840208018128283920480645065789961539959354957463803835814099327698645
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.63495043441670571673463000603313105984802318711985896901252692991482174699242
Short name T1316
Test name
Test status
Simulation time 38239183 ps
CPU time 1.36 seconds
Started Nov 22 01:20:31 PM PST 23
Finished Nov 22 01:20:38 PM PST 23
Peak memory 229768 kb
Host smart-59b0c97f-3786-4641-90c3-a0253ec610b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63495043441670571673463000603313105984802318711985896901252692991482174699242 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.63495043441670571673463000603313105984802318711985896901252692991482174699242
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.110206826725648430566414081300729041549579406894945213904534784389153133153882
Short name T210
Test name
Test status
Simulation time 61029183 ps
CPU time 2.08 seconds
Started Nov 22 01:20:42 PM PST 23
Finished Nov 22 01:20:46 PM PST 23
Peak memory 230132 kb
Host smart-751952c4-f3ea-4e88-9e42-0e85794f1bd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110206826725648430566414081300729041549579406894945213904534784389153133153882
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.11020682672564843056641408130072904154957940689494521
3904534784389153133153882
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.8593746704629781748097190483661290118510183686828027775876130245488056990757
Short name T85
Test name
Test status
Simulation time 71439183 ps
CPU time 3.1 seconds
Started Nov 22 01:20:45 PM PST 23
Finished Nov 22 01:20:52 PM PST 23
Peak memory 238352 kb
Host smart-f97c52da-d01b-4661-981d-ee1fa935e34b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8593746704629781748097190483661290118510183686828027775876130245488056990757 -assert nopostproc +UV
M_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.8593746704629781748097190483661290118510183686828027775876130245488056990757
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.96662749285977876811838339551724151570864799544951005863703662960382150207797
Short name T218
Test name
Test status
Simulation time 647529183 ps
CPU time 9.42 seconds
Started Nov 22 01:20:21 PM PST 23
Finished Nov 22 01:20:33 PM PST 23
Peak memory 230276 kb
Host smart-2dae0256-a216-44ed-b470-103c4e8eea27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96662749285977876811838339551724151570864799544951005863703662960382150207797 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.96662749285977876811838339551724151570864799544951005863703662960382150207797
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.19770743562124180334224312979800322870760851240563623576226126707455768827310
Short name T900
Test name
Test status
Simulation time 71069183 ps
CPU time 1.8 seconds
Started Nov 22 01:49:58 PM PST 23
Finished Nov 22 01:50:02 PM PST 23
Peak memory 238464 kb
Host smart-7fe53731-6cce-4be2-84d7-86acdc5fc795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19770743562124180334224312979800322870760851240563623576226126707455768827310 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.19770743562124180334224312979800322870760851240563623576226126707455768827310
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.71803471335534911534447583346495414762952728354289230416830556305536700339863
Short name T612
Test name
Test status
Simulation time 111269183 ps
CPU time 2.67 seconds
Started Nov 22 01:49:54 PM PST 23
Finished Nov 22 01:49:58 PM PST 23
Peak memory 246764 kb
Host smart-4a81d1d2-5288-416c-a6c3-83b8af77cfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71803471335534911534447583346495414762952728354289230416830556305536700339863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.otp_ctrl_check_fail.71803471335534911534447583346495414762952728354289230416830556305536700339863
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.17469252352493222696475260275667777511195982525572148762941634862713345090345
Short name T812
Test name
Test status
Simulation time 390019183 ps
CPU time 10.9 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:24 PM PST 23
Peak memory 238580 kb
Host smart-a56fd9c3-ca78-4d75-9a76-8640dfeacfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17469252352493222696475260275667777511195982525572148762941634862713345090345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.otp_ctrl_dai_errs.17469252352493222696475260275667777511195982525572148762941634862713345090345
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.7465137764709371596998412234397753679577963183595703918339803561910540047313
Short name T826
Test name
Test status
Simulation time 156689183 ps
CPU time 3.94 seconds
Started Nov 22 01:49:37 PM PST 23
Finished Nov 22 01:49:45 PM PST 23
Peak memory 238620 kb
Host smart-9d542b94-a89b-449a-b523-a57f4c24daba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7465137764709371596998412234397753679577963183595703918339803561910540047313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.otp_ctrl_init_fail.7465137764709371596998412234397753679577963183595703918339803561910540047313
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.107745084857208650696134396984743165312353799687946731675279749259341402980633
Short name T1080
Test name
Test status
Simulation time 5945919348 ps
CPU time 13.38 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:26 PM PST 23
Peak memory 230324 kb
Host smart-bba0915d-72c6-473b-b385-fe90118e1fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107745084857208650696134396984743165312353799687946731675279749259341402980633 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.otp_ctrl_low_freq_read.107745084857208650696134396984743165312353799687946731675279749259341402980633
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.87939481476692578298091549418053782656693162753572153259727667452193196234562
Short name T1199
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.57 seconds
Started Nov 22 01:50:04 PM PST 23
Finished Nov 22 01:50:26 PM PST 23
Peak memory 238860 kb
Host smart-097ca262-bcf8-47c6-82a2-f1de249ad033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87939481476692578298091549418053782656693162753572153259727667452193196234562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.otp_ctrl_macro_errs.87939481476692578298091549418053782656693162753572153259727667452193196234562
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.87929915646376984084562393512588779365890840293370299341437189363088499573758
Short name T440
Test name
Test status
Simulation time 346349183 ps
CPU time 7.6 seconds
Started Nov 22 01:49:45 PM PST 23
Finished Nov 22 01:49:54 PM PST 23
Peak memory 238740 kb
Host smart-ae94f598-a69d-4c8b-a7eb-6ff1e5125c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87929915646376984084562393512588779365890840293370299341437189363088499573758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.otp_ctrl_parallel_key_req.87929915646376984084562393512588779365890840293370299341437189363088499573758
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.60717719050441014523738777225716999926455995198738559684789445504091562516645
Short name T920
Test name
Test status
Simulation time 176929183 ps
CPU time 4.35 seconds
Started Nov 22 01:49:54 PM PST 23
Finished Nov 22 01:49:59 PM PST 23
Peak memory 238584 kb
Host smart-f9491a57-9331-4514-967e-f80af952d941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60717719050441014523738777225716999926455995198738559684789445504091562516645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.60717719050441014523738777225716999926455995198738559684789445504091562516645
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.81624810531097012923511858516618828566395646893278260068685754355025102928592
Short name T338
Test name
Test status
Simulation time 601119183 ps
CPU time 16.47 seconds
Started Nov 22 01:49:43 PM PST 23
Finished Nov 22 01:50:01 PM PST 23
Peak memory 230344 kb
Host smart-88ad9a74-4da0-456d-86ef-2f77a576eb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81624810531097012923511858516618828566395646893278260068685754355025102928592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.otp_ctrl_partition_walk.81624810531097012923511858516618828566395646893278260068685754355025102928592
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.52326787885780174485302263795202351864895011772556826475390877030304396493424
Short name T774
Test name
Test status
Simulation time 137469183 ps
CPU time 3.62 seconds
Started Nov 22 01:50:03 PM PST 23
Finished Nov 22 01:50:10 PM PST 23
Peak memory 238708 kb
Host smart-08e21797-bc15-4fed-bb5b-512cf7d290f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52326787885780174485302263795202351864895011772556826475390877030304396493424 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_regwen.52326787885780174485302263795202351864895011772556826475390877030304396493424
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.51421053550837345331338921042749559299694184105905624172769676894307599146926
Short name T28
Test name
Test status
Simulation time 8539099183 ps
CPU time 146.1 seconds
Started Nov 22 01:50:06 PM PST 23
Finished Nov 22 01:52:35 PM PST 23
Peak memory 268428 kb
Host smart-aa31845c-a447-4d17-85e1-ef3d3c35f05f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51421053550837345331338921042749559299694184105905624172769676894307599146926 -assert nopostpro
c +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.51421053550837345331338921042749559299694184105905624172769676894307599146926
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.70803014555586995009750424349816827306289088303121900491440491631874691734746
Short name T625
Test name
Test status
Simulation time 138839183 ps
CPU time 3 seconds
Started Nov 22 01:50:06 PM PST 23
Finished Nov 22 01:50:16 PM PST 23
Peak memory 238748 kb
Host smart-95abebf9-c3fb-4267-8fe2-b23ac0fb7104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70803014555586995009750424349816827306289088303121900491440491631874691734746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.otp_ctrl_smoke.70803014555586995009750424349816827306289088303121900491440491631874691734746
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.102941450057117573812333097858859617755229768086153884676168311836136283218429
Short name T50
Test name
Test status
Simulation time 13240088340 ps
CPU time 134.35 seconds
Started Nov 22 01:50:03 PM PST 23
Finished Nov 22 01:52:20 PM PST 23
Peak memory 241900 kb
Host smart-c9650829-09dd-41b2-b5c0-5a6534c7e754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102941450057117573812333097858859617755229768086153884676168311836136283218429 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.102941450057117573812333097858859617755229768086153884676168311836136283218429
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.82148188423898480650519945045011291187018367602075111270264557055394473547202
Short name T363
Test name
Test status
Simulation time 150268849183 ps
CPU time 1946.22 seconds
Started Nov 22 01:50:06 PM PST 23
Finished Nov 22 02:22:36 PM PST 23
Peak memory 517592 kb
Host smart-8dd28a4e-c94d-4911-b3d3-96272311e17e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8214818842389848065051
9945045011291187018367602075111270264557055394473547202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_rese
t.82148188423898480650519945045011291187018367602075111270264557055394473547202
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.67219259183462050396357186875835159234534060745980877276456832785351346195510
Short name T1262
Test name
Test status
Simulation time 549639183 ps
CPU time 8.84 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:14 PM PST 23
Peak memory 246980 kb
Host smart-07c77e3a-63c3-4a0b-919c-43871df94d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67219259183462050396357186875835159234534060745980877276456832785351346195510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.otp_ctrl_test_access.67219259183462050396357186875835159234534060745980877276456832785351346195510
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.42037263007977886624528835207021529819691710167426785656359848397293803057117
Short name T259
Test name
Test status
Simulation time 62509183 ps
CPU time 1.82 seconds
Started Nov 22 01:50:29 PM PST 23
Finished Nov 22 01:50:32 PM PST 23
Peak memory 230092 kb
Host smart-6a8d6328-891b-494f-a126-c22b728cb67e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=42037263007977886624528835207021529819691710167426785656359848397293803057117 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.otp_ctrl_wake_up.42037263007977886624528835207021529819691710167426785656359848397293803057117
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.78067527191431109231565684474306577760180320304276653108530839138573912587635
Short name T836
Test name
Test status
Simulation time 71069183 ps
CPU time 1.82 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:15 PM PST 23
Peak memory 238364 kb
Host smart-34200a27-5ff8-488b-8698-88d4a5b19590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78067527191431109231565684474306577760180320304276653108530839138573912587635 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.78067527191431109231565684474306577760180320304276653108530839138573912587635
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.76528333342691275014351089428313736034065409282397084809625760123279985211984
Short name T1109
Test name
Test status
Simulation time 190889183 ps
CPU time 4.77 seconds
Started Nov 22 01:50:11 PM PST 23
Finished Nov 22 01:50:22 PM PST 23
Peak memory 238748 kb
Host smart-ae6e6b79-400f-4624-a60b-04ac163484c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76528333342691275014351089428313736034065409282397084809625760123279985211984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.otp_ctrl_background_chks.76528333342691275014351089428313736034065409282397084809625760123279985211984
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.46260885266146598860259462129497685824037456632290462448307670292197706483069
Short name T849
Test name
Test status
Simulation time 111269183 ps
CPU time 2.72 seconds
Started Nov 22 01:49:51 PM PST 23
Finished Nov 22 01:49:55 PM PST 23
Peak memory 246696 kb
Host smart-f6686b8f-2222-480a-8d4b-b3eb99d087be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46260885266146598860259462129497685824037456632290462448307670292197706483069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.otp_ctrl_check_fail.46260885266146598860259462129497685824037456632290462448307670292197706483069
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.91618767460023198902127632403329586772761994960089083730325629406358669542286
Short name T1147
Test name
Test status
Simulation time 390019183 ps
CPU time 10.48 seconds
Started Nov 22 01:50:01 PM PST 23
Finished Nov 22 01:50:14 PM PST 23
Peak memory 238564 kb
Host smart-2ea3b1ca-0992-4fab-891e-bb5a0f923669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91618767460023198902127632403329586772761994960089083730325629406358669542286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.otp_ctrl_dai_errs.91618767460023198902127632403329586772761994960089083730325629406358669542286
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.67363853595483942054393973335322956298251430753764698214020110331358146928706
Short name T40
Test name
Test status
Simulation time 614979183 ps
CPU time 10.12 seconds
Started Nov 22 01:49:59 PM PST 23
Finished Nov 22 01:50:11 PM PST 23
Peak memory 238720 kb
Host smart-10d27e13-d58b-4fe9-a6af-8ac92d7d7220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67363853595483942054393973335322956298251430753764698214020110331358146928706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.otp_ctrl_dai_lock.67363853595483942054393973335322956298251430753764698214020110331358146928706
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.65959770873550707524376427910220957691206975927218325305082782645076380830961
Short name T869
Test name
Test status
Simulation time 156689183 ps
CPU time 3.96 seconds
Started Nov 22 01:50:01 PM PST 23
Finished Nov 22 01:50:08 PM PST 23
Peak memory 238580 kb
Host smart-9ed1fee4-465f-42e7-a618-b728d971d192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65959770873550707524376427910220957691206975927218325305082782645076380830961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.otp_ctrl_init_fail.65959770873550707524376427910220957691206975927218325305082782645076380830961
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.31882871923139750633569129836226089287702718572036861521552985757362266348967
Short name T717
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.49 seconds
Started Nov 22 01:49:56 PM PST 23
Finished Nov 22 01:50:17 PM PST 23
Peak memory 238992 kb
Host smart-afb37ae1-6647-4ef3-b476-dbb93ad098dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31882871923139750633569129836226089287702718572036861521552985757362266348967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.otp_ctrl_macro_errs.31882871923139750633569129836226089287702718572036861521552985757362266348967
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.108343725765716761797399814946117630511368961409288981608057616892923194335026
Short name T1037
Test name
Test status
Simulation time 346349183 ps
CPU time 7.41 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 01:50:16 PM PST 23
Peak memory 238704 kb
Host smart-799b0d06-9bce-47e2-9ebf-a6d5ca25f750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108343725765716761797399814946117630511368961409288981608057616892923194335026 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.108343725765716761797399814946117630511368961409288981608057616892923194335026
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.107002843984039398240691221280351082335963284726635523008492324458782353032694
Short name T662
Test name
Test status
Simulation time 176929183 ps
CPU time 4.33 seconds
Started Nov 22 01:50:11 PM PST 23
Finished Nov 22 01:50:22 PM PST 23
Peak memory 238672 kb
Host smart-931f5cdd-5d79-41e0-98b8-47e957b8a4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107002843984039398240691221280351082335963284726635523008492324458782353032694 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.107002843984039398240691221280351082335963284726635523008492324458782353032694
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.65523756054344985109530810539589953598804078058197649233102498339142518260530
Short name T1005
Test name
Test status
Simulation time 486419183 ps
CPU time 11.97 seconds
Started Nov 22 01:49:59 PM PST 23
Finished Nov 22 01:50:13 PM PST 23
Peak memory 238720 kb
Host smart-ad4b6760-665c-43af-a037-c1b573ac9c24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=65523756054344985109530810539589953598804078058197649233102498339142518260530 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.65523756054344985109530810539589953598804078058197649233102498339142518260530
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.50075143319322639499022990349421645084100288795781159711219332536674507033393
Short name T473
Test name
Test status
Simulation time 137469183 ps
CPU time 3.74 seconds
Started Nov 22 01:50:00 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 238712 kb
Host smart-835347c9-0f1b-4275-b837-4d3da865d9d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50075143319322639499022990349421645084100288795781159711219332536674507033393 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_regwen.50075143319322639499022990349421645084100288795781159711219332536674507033393
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.49842572648089497287957480407897494767665067237195200100068206113300983902903
Short name T96
Test name
Test status
Simulation time 8539099183 ps
CPU time 146.68 seconds
Started Nov 22 01:50:06 PM PST 23
Finished Nov 22 01:52:36 PM PST 23
Peak memory 268452 kb
Host smart-deab9af9-e82d-4566-b949-4f758079fdd5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49842572648089497287957480407897494767665067237195200100068206113300983902903 -assert nopostpro
c +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.49842572648089497287957480407897494767665067237195200100068206113300983902903
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.83307070124827711973809586181539276496128559880092884342170931195263127244071
Short name T1207
Test name
Test status
Simulation time 138839183 ps
CPU time 3.05 seconds
Started Nov 22 01:50:06 PM PST 23
Finished Nov 22 01:50:16 PM PST 23
Peak memory 238832 kb
Host smart-f5a19041-0e54-4a59-adc1-dd72e40441b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83307070124827711973809586181539276496128559880092884342170931195263127244071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.otp_ctrl_smoke.83307070124827711973809586181539276496128559880092884342170931195263127244071
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.66253785736541913672385061894301794075036772747810418467506841882845987347174
Short name T1092
Test name
Test status
Simulation time 13240088340 ps
CPU time 131.36 seconds
Started Nov 22 01:49:58 PM PST 23
Finished Nov 22 01:52:12 PM PST 23
Peak memory 241688 kb
Host smart-65169fb5-568a-4cca-9b43-dad23b705527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66253785736541913672385061894301794075036772747810418467506841882845987347174 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.66253785736541913672385061894301794075036772747810418467506841882845987347174
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.18218298910585449924213777716617771241860292695530509111695870105974680410245
Short name T830
Test name
Test status
Simulation time 150268849183 ps
CPU time 2003.8 seconds
Started Nov 22 01:50:01 PM PST 23
Finished Nov 22 02:23:28 PM PST 23
Peak memory 517596 kb
Host smart-94244477-e904-4d75-ab20-da62070a8cd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821829891058544992421
3777716617771241860292695530509111695870105974680410245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_rese
t.18218298910585449924213777716617771241860292695530509111695870105974680410245
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.7918425370254783756661017995969584301722768842315916494681287248221305510432
Short name T577
Test name
Test status
Simulation time 549639183 ps
CPU time 8.77 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:13 PM PST 23
Peak memory 246988 kb
Host smart-e6677cbe-2ef8-4fd7-ae0d-6ac9001a0299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7918425370254783756661017995969584301722768842315916494681287248221305510432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.otp_ctrl_test_access.7918425370254783756661017995969584301722768842315916494681287248221305510432
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.64834166503883185455142989615907841056960219897455366059318737738685066627370
Short name T1015
Test name
Test status
Simulation time 71069183 ps
CPU time 1.87 seconds
Started Nov 22 01:50:08 PM PST 23
Finished Nov 22 01:50:16 PM PST 23
Peak memory 238448 kb
Host smart-3cb2b1d0-b182-40eb-a4a5-350f542e19e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64834166503883185455142989615907841056960219897455366059318737738685066627370 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.64834166503883185455142989615907841056960219897455366059318737738685066627370
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.96737487773182500422622419256909219275861009922514508978726175825585281419241
Short name T1190
Test name
Test status
Simulation time 111269183 ps
CPU time 2.82 seconds
Started Nov 22 01:50:29 PM PST 23
Finished Nov 22 01:50:33 PM PST 23
Peak memory 246036 kb
Host smart-9be30b4b-e817-4ac8-95af-1b18b1aefa85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96737487773182500422622419256909219275861009922514508978726175825585281419241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.otp_ctrl_check_fail.96737487773182500422622419256909219275861009922514508978726175825585281419241
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.111736131491491333360995100841576060720649851622522897188509325362745028278448
Short name T1194
Test name
Test status
Simulation time 390019183 ps
CPU time 10.93 seconds
Started Nov 22 01:50:11 PM PST 23
Finished Nov 22 01:50:29 PM PST 23
Peak memory 238544 kb
Host smart-87dfaa15-7eee-4f73-a9d6-ea4a3fc987ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111736131491491333360995100841576060720649851622522897188509325362745028278448 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.otp_ctrl_dai_errs.111736131491491333360995100841576060720649851622522897188509325362745028278448
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.87820281209839599363771093129530918363665299438950228563627512149653293741833
Short name T1181
Test name
Test status
Simulation time 614979183 ps
CPU time 10.77 seconds
Started Nov 22 01:50:14 PM PST 23
Finished Nov 22 01:50:29 PM PST 23
Peak memory 238756 kb
Host smart-532fa1c6-4977-4ff9-b68c-ce49ac340f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87820281209839599363771093129530918363665299438950228563627512149653293741833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.otp_ctrl_dai_lock.87820281209839599363771093129530918363665299438950228563627512149653293741833
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.30574989666133696693535227696359803094496643614367699159718164752138252062291
Short name T1220
Test name
Test status
Simulation time 156689183 ps
CPU time 4.57 seconds
Started Nov 22 01:50:08 PM PST 23
Finished Nov 22 01:50:18 PM PST 23
Peak memory 238628 kb
Host smart-56636662-afc8-4804-ac11-211fbb8a38bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30574989666133696693535227696359803094496643614367699159718164752138252062291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.otp_ctrl_init_fail.30574989666133696693535227696359803094496643614367699159718164752138252062291
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.82937033940961909407068035775707178438074978473145047843223505946679867899120
Short name T1106
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.52 seconds
Started Nov 22 01:50:13 PM PST 23
Finished Nov 22 01:50:37 PM PST 23
Peak memory 239012 kb
Host smart-4236e083-a1f2-4c66-84d1-71b6ae4a4690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82937033940961909407068035775707178438074978473145047843223505946679867899120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.otp_ctrl_macro_errs.82937033940961909407068035775707178438074978473145047843223505946679867899120
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.8357393279610163776513432737992122907745166345835530771726526637232671096489
Short name T466
Test name
Test status
Simulation time 346349183 ps
CPU time 7.6 seconds
Started Nov 22 01:50:04 PM PST 23
Finished Nov 22 01:50:22 PM PST 23
Peak memory 238780 kb
Host smart-79680a41-d277-4465-bad3-bd8302b8242b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8357393279610163776513432737992122907745166345835530771726526637232671096489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 10.otp_ctrl_parallel_key_req.8357393279610163776513432737992122907745166345835530771726526637232671096489
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.22393329795785857494521859071807930648714884206283031811347288160086103208671
Short name T515
Test name
Test status
Simulation time 176929183 ps
CPU time 4.21 seconds
Started Nov 22 01:50:20 PM PST 23
Finished Nov 22 01:50:27 PM PST 23
Peak memory 238568 kb
Host smart-a277666d-ed54-4447-be5d-0038220c588a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22393329795785857494521859071807930648714884206283031811347288160086103208671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.22393329795785857494521859071807930648714884206283031811347288160086103208671
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.103998084679380984949225447103921194277060055255550249545859659319726352313424
Short name T282
Test name
Test status
Simulation time 486419183 ps
CPU time 11.92 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:17 PM PST 23
Peak memory 238708 kb
Host smart-117c27bc-09a7-409a-8724-4c6aef95190a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103998084679380984949225447103921194277060055255550249545859659319726352313424 -assert nopostproc +UVM_TE
STNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.103998084679380984949225447103921194277060055255550249545859659319726352313424
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.56189945799145620100940544681329407482495264342938856501719218333447696952
Short name T801
Test name
Test status
Simulation time 137469183 ps
CPU time 3.59 seconds
Started Nov 22 01:50:23 PM PST 23
Finished Nov 22 01:50:27 PM PST 23
Peak memory 238684 kb
Host smart-225c7d4f-db83-40ea-b092-a8d472ce8223
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56189945799145620100940544681329407482495264342938856501719218333447696952 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.otp_ctrl_regwen.56189945799145620100940544681329407482495264342938856501719218333447696952
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.31683845276575490968588636406036282960661290186071783299244045863181014572756
Short name T1303
Test name
Test status
Simulation time 138839183 ps
CPU time 3.12 seconds
Started Nov 22 01:50:21 PM PST 23
Finished Nov 22 01:50:26 PM PST 23
Peak memory 238780 kb
Host smart-fac905e9-b8d2-4111-933b-c867f35103d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31683845276575490968588636406036282960661290186071783299244045863181014572756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.otp_ctrl_smoke.31683845276575490968588636406036282960661290186071783299244045863181014572756
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.51622803635849282631815753024707945129628132917932820367724475812272991701852
Short name T953
Test name
Test status
Simulation time 13240088340 ps
CPU time 129.75 seconds
Started Nov 22 01:50:14 PM PST 23
Finished Nov 22 01:52:28 PM PST 23
Peak memory 241792 kb
Host smart-4b44db12-7c45-456e-9e15-e7cb5e4ef4f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51622803635849282631815753024707945129628132917932820367724475812272991701852 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.51622803635849282631815753024707945129628132917932820367724475812272991701852
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.86479716648460780565929317600100456962878759957317826524742761544192609788027
Short name T740
Test name
Test status
Simulation time 150268849183 ps
CPU time 1993.93 seconds
Started Nov 22 01:50:16 PM PST 23
Finished Nov 22 02:23:36 PM PST 23
Peak memory 517600 kb
Host smart-92d3c019-7bd3-40c3-b52f-2bb6ad35bb65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8647971664846078056592
9317600100456962878759957317826524742761544192609788027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_res
et.86479716648460780565929317600100456962878759957317826524742761544192609788027
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.97417669053806270236395267085824628786091486480173751525640388449757293456938
Short name T1056
Test name
Test status
Simulation time 549639183 ps
CPU time 8.71 seconds
Started Nov 22 01:50:12 PM PST 23
Finished Nov 22 01:50:26 PM PST 23
Peak memory 247036 kb
Host smart-972c30b1-1550-49c5-b285-3d212c4d4c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97417669053806270236395267085824628786091486480173751525640388449757293456938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.otp_ctrl_test_access.97417669053806270236395267085824628786091486480173751525640388449757293456938
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.83776314432766386612220692190297287171686623887168379363677321362345408946685
Short name T1133
Test name
Test status
Simulation time 156689183 ps
CPU time 3.91 seconds
Started Nov 22 01:51:58 PM PST 23
Finished Nov 22 01:52:03 PM PST 23
Peak memory 238584 kb
Host smart-cbea01d3-a14e-4f04-be18-8e03eb4a0751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83776314432766386612220692190297287171686623887168379363677321362345408946685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 100.otp_ctrl_init_fail.83776314432766386612220692190297287171686623887168379363677321362345408946685
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.55888030290919170248256262919674525312320215657980106866447236784132166471533
Short name T1040
Test name
Test status
Simulation time 176929183 ps
CPU time 4.23 seconds
Started Nov 22 01:51:37 PM PST 23
Finished Nov 22 01:51:46 PM PST 23
Peak memory 238604 kb
Host smart-d733f0c2-2edd-479f-876e-5fddb8fc5acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55888030290919170248256262919674525312320215657980106866447236784132166471533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.55888030290919170248256262919674525312320215657980106866447236784132166471533
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.71040618501721475478709983583794744794789119832276875810866444479766123575942
Short name T579
Test name
Test status
Simulation time 156689183 ps
CPU time 4.01 seconds
Started Nov 22 01:51:59 PM PST 23
Finished Nov 22 01:52:05 PM PST 23
Peak memory 238584 kb
Host smart-a41f8e31-4b49-475f-bc63-210ca793e0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71040618501721475478709983583794744794789119832276875810866444479766123575942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 101.otp_ctrl_init_fail.71040618501721475478709983583794744794789119832276875810866444479766123575942
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.103533327470115726603613692802852968569955358548097728032616648698548072056392
Short name T1254
Test name
Test status
Simulation time 176929183 ps
CPU time 4.43 seconds
Started Nov 22 01:51:34 PM PST 23
Finished Nov 22 01:51:43 PM PST 23
Peak memory 238720 kb
Host smart-4478f63c-0d33-4403-b63d-5383bd9c3728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103533327470115726603613692802852968569955358548097728032616648698548072056392 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.103533327470115726603613692802852968569955358548097728032616648698548072056392
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.106068017956463427096483723395525411530304403556628277251194419199777114682704
Short name T292
Test name
Test status
Simulation time 156689183 ps
CPU time 3.93 seconds
Started Nov 22 01:51:58 PM PST 23
Finished Nov 22 01:52:04 PM PST 23
Peak memory 238592 kb
Host smart-0c70cd54-38d8-487d-a73e-1843048ddc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106068017956463427096483723395525411530304403556628277251194419199777114682704 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 102.otp_ctrl_init_fail.106068017956463427096483723395525411530304403556628277251194419199777114682704
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.115292671414609471957094975122882505111553105693975090746053254912134635565674
Short name T523
Test name
Test status
Simulation time 176929183 ps
CPU time 4.24 seconds
Started Nov 22 01:51:58 PM PST 23
Finished Nov 22 01:52:03 PM PST 23
Peak memory 238644 kb
Host smart-c738bb87-bb0d-4f7e-b49f-76fe20c85f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115292671414609471957094975122882505111553105693975090746053254912134635565674 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.115292671414609471957094975122882505111553105693975090746053254912134635565674
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.73547458377122780533955914836208388650887786259133729480389849140181208548281
Short name T228
Test name
Test status
Simulation time 156689183 ps
CPU time 3.9 seconds
Started Nov 22 01:51:53 PM PST 23
Finished Nov 22 01:51:59 PM PST 23
Peak memory 238436 kb
Host smart-2774cc83-9af6-490a-9028-be510c9b256b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73547458377122780533955914836208388650887786259133729480389849140181208548281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 103.otp_ctrl_init_fail.73547458377122780533955914836208388650887786259133729480389849140181208548281
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.80186928576072155220013115196592723311297170637453948157568192268779855967181
Short name T1022
Test name
Test status
Simulation time 176929183 ps
CPU time 4.35 seconds
Started Nov 22 01:52:01 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238668 kb
Host smart-13f4a4ee-bf07-4e22-991a-fd6588340206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80186928576072155220013115196592723311297170637453948157568192268779855967181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.80186928576072155220013115196592723311297170637453948157568192268779855967181
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.27999031196200723583933116849885457051622277182053434060457373932634031129282
Short name T817
Test name
Test status
Simulation time 156689183 ps
CPU time 3.92 seconds
Started Nov 22 01:51:55 PM PST 23
Finished Nov 22 01:52:00 PM PST 23
Peak memory 238652 kb
Host smart-2287164b-b0ef-46aa-bd94-4516c7e3f7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27999031196200723583933116849885457051622277182053434060457373932634031129282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 104.otp_ctrl_init_fail.27999031196200723583933116849885457051622277182053434060457373932634031129282
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.19452483942007271343965267364633191628965164445528071419838682258400487599027
Short name T940
Test name
Test status
Simulation time 176929183 ps
CPU time 4.47 seconds
Started Nov 22 01:52:03 PM PST 23
Finished Nov 22 01:52:09 PM PST 23
Peak memory 238696 kb
Host smart-8b228286-ccbd-4dc5-ae5e-2fcb1f4b3985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19452483942007271343965267364633191628965164445528071419838682258400487599027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.19452483942007271343965267364633191628965164445528071419838682258400487599027
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.56026117415531510307306152277202105137901216962324208456043994262421948532245
Short name T412
Test name
Test status
Simulation time 176929183 ps
CPU time 4.35 seconds
Started Nov 22 01:51:49 PM PST 23
Finished Nov 22 01:51:56 PM PST 23
Peak memory 238624 kb
Host smart-99310f68-1242-4d02-8a4c-19108a91c68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56026117415531510307306152277202105137901216962324208456043994262421948532245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.56026117415531510307306152277202105137901216962324208456043994262421948532245
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.25239706228273428506917041073077736869464097104791305226314915873391603961128
Short name T1222
Test name
Test status
Simulation time 156689183 ps
CPU time 3.92 seconds
Started Nov 22 01:51:58 PM PST 23
Finished Nov 22 01:52:02 PM PST 23
Peak memory 238560 kb
Host smart-308a5638-a5fb-4d24-8c24-a532a63d11f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25239706228273428506917041073077736869464097104791305226314915873391603961128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 106.otp_ctrl_init_fail.25239706228273428506917041073077736869464097104791305226314915873391603961128
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.100389068021923856907802602570913151549345578079174434501533713852413055883628
Short name T980
Test name
Test status
Simulation time 176929183 ps
CPU time 4.31 seconds
Started Nov 22 01:52:09 PM PST 23
Finished Nov 22 01:52:17 PM PST 23
Peak memory 238632 kb
Host smart-0201dcd8-18c1-456d-9055-b18922fc8b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100389068021923856907802602570913151549345578079174434501533713852413055883628 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.100389068021923856907802602570913151549345578079174434501533713852413055883628
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.95984246037855413121630368646536762490173474650193611226706002392441186764863
Short name T327
Test name
Test status
Simulation time 156689183 ps
CPU time 3.92 seconds
Started Nov 22 01:51:56 PM PST 23
Finished Nov 22 01:52:01 PM PST 23
Peak memory 238580 kb
Host smart-31e217c1-5f45-4d7e-94cc-6c403ab0ee8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95984246037855413121630368646536762490173474650193611226706002392441186764863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 107.otp_ctrl_init_fail.95984246037855413121630368646536762490173474650193611226706002392441186764863
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.111570483078638316928370741802249407102740716635804665348602528499800146513676
Short name T362
Test name
Test status
Simulation time 176929183 ps
CPU time 4.2 seconds
Started Nov 22 01:51:58 PM PST 23
Finished Nov 22 01:52:04 PM PST 23
Peak memory 238692 kb
Host smart-b747b12f-1217-4549-99c9-6c4092f0965d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111570483078638316928370741802249407102740716635804665348602528499800146513676 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.111570483078638316928370741802249407102740716635804665348602528499800146513676
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.104001447998853532623944887706223274640160912323841828544857524822507950184985
Short name T925
Test name
Test status
Simulation time 156689183 ps
CPU time 4.01 seconds
Started Nov 22 01:51:59 PM PST 23
Finished Nov 22 01:52:05 PM PST 23
Peak memory 238660 kb
Host smart-59bb24d4-73cc-4a4c-b763-43a191bab6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104001447998853532623944887706223274640160912323841828544857524822507950184985 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 108.otp_ctrl_init_fail.104001447998853532623944887706223274640160912323841828544857524822507950184985
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.114101159441312443945170404809367905950355778347591312898177153677312692616469
Short name T404
Test name
Test status
Simulation time 176929183 ps
CPU time 4.51 seconds
Started Nov 22 01:52:06 PM PST 23
Finished Nov 22 01:52:14 PM PST 23
Peak memory 238712 kb
Host smart-e2ef8e4b-38a9-4703-8c57-1a60a195350f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114101159441312443945170404809367905950355778347591312898177153677312692616469 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.114101159441312443945170404809367905950355778347591312898177153677312692616469
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.48623286889278690925574925738754418770804454027040440440175062940092538166570
Short name T643
Test name
Test status
Simulation time 156689183 ps
CPU time 4.11 seconds
Started Nov 22 01:52:08 PM PST 23
Finished Nov 22 01:52:15 PM PST 23
Peak memory 238620 kb
Host smart-648ee675-970b-46a0-b1e7-19eb77602e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48623286889278690925574925738754418770804454027040440440175062940092538166570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 109.otp_ctrl_init_fail.48623286889278690925574925738754418770804454027040440440175062940092538166570
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.98861340597656003889988118837806348483405232997734690863688135037430301045097
Short name T341
Test name
Test status
Simulation time 176929183 ps
CPU time 4.66 seconds
Started Nov 22 01:52:00 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238668 kb
Host smart-ffae23c3-fa19-4292-b7f9-0e64f16fae83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98861340597656003889988118837806348483405232997734690863688135037430301045097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.98861340597656003889988118837806348483405232997734690863688135037430301045097
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.53372596745496839535496392454093646040336823415304455103289755159513828514249
Short name T1018
Test name
Test status
Simulation time 71069183 ps
CPU time 1.96 seconds
Started Nov 22 01:50:30 PM PST 23
Finished Nov 22 01:50:32 PM PST 23
Peak memory 238356 kb
Host smart-6a2847b2-7972-48ca-a0eb-8af24ee8bf8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53372596745496839535496392454093646040336823415304455103289755159513828514249 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.53372596745496839535496392454093646040336823415304455103289755159513828514249
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.70999783207828196262941287581096359890271761084467769882474668858319950323553
Short name T543
Test name
Test status
Simulation time 111269183 ps
CPU time 2.67 seconds
Started Nov 22 01:50:26 PM PST 23
Finished Nov 22 01:50:30 PM PST 23
Peak memory 246900 kb
Host smart-bd9694a6-10cc-4c06-82f5-624497cb68c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70999783207828196262941287581096359890271761084467769882474668858319950323553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.otp_ctrl_check_fail.70999783207828196262941287581096359890271761084467769882474668858319950323553
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.70324100507218587106926511423457353061115347330391848903429371842148605195767
Short name T1075
Test name
Test status
Simulation time 390019183 ps
CPU time 11.06 seconds
Started Nov 22 01:50:12 PM PST 23
Finished Nov 22 01:50:29 PM PST 23
Peak memory 238592 kb
Host smart-b1ce050c-a4c8-4083-9aff-7042af9a44e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70324100507218587106926511423457353061115347330391848903429371842148605195767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.otp_ctrl_dai_errs.70324100507218587106926511423457353061115347330391848903429371842148605195767
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.115121605756690148886863867065827136505036994818263025613132043402688688559957
Short name T492
Test name
Test status
Simulation time 614979183 ps
CPU time 11.07 seconds
Started Nov 22 01:50:28 PM PST 23
Finished Nov 22 01:50:41 PM PST 23
Peak memory 238744 kb
Host smart-f38a37c4-36c5-4fd7-b149-e1e8cad931d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115121605756690148886863867065827136505036994818263025613132043402688688559957 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.otp_ctrl_dai_lock.115121605756690148886863867065827136505036994818263025613132043402688688559957
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.83897376397925432356949284467467614898220332188171396607270709221554594773350
Short name T408
Test name
Test status
Simulation time 156689183 ps
CPU time 4.02 seconds
Started Nov 22 01:50:15 PM PST 23
Finished Nov 22 01:50:24 PM PST 23
Peak memory 238656 kb
Host smart-e0fed8ad-d4a9-4e6b-b63e-07291fd6008f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83897376397925432356949284467467614898220332188171396607270709221554594773350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.otp_ctrl_init_fail.83897376397925432356949284467467614898220332188171396607270709221554594773350
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.51322549393426355345685177503630611448858689356906533439493378774539888378380
Short name T564
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.61 seconds
Started Nov 22 01:50:22 PM PST 23
Finished Nov 22 01:50:43 PM PST 23
Peak memory 238912 kb
Host smart-d3926b7e-7c6f-4688-b2ef-954b1c2dc926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51322549393426355345685177503630611448858689356906533439493378774539888378380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.otp_ctrl_macro_errs.51322549393426355345685177503630611448858689356906533439493378774539888378380
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.2524380043332597510869642341033154467309212534088420528688083541134831555951
Short name T376
Test name
Test status
Simulation time 346349183 ps
CPU time 7.39 seconds
Started Nov 22 01:50:24 PM PST 23
Finished Nov 22 01:50:33 PM PST 23
Peak memory 238600 kb
Host smart-0f8925e8-40eb-4b04-ab51-851ad34ddeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524380043332597510869642341033154467309212534088420528688083541134831555951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 11.otp_ctrl_parallel_key_req.2524380043332597510869642341033154467309212534088420528688083541134831555951
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.2182542824256488018926481449506334846213334564996629403529946476216602850469
Short name T573
Test name
Test status
Simulation time 176929183 ps
CPU time 4.39 seconds
Started Nov 22 01:50:16 PM PST 23
Finished Nov 22 01:50:26 PM PST 23
Peak memory 238644 kb
Host smart-dd6e7299-e07f-400f-a9b6-97b9a6fc0fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182542824256488018926481449506334846213334564996629403529946476216602850469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.2182542824256488018926481449506334846213334564996629403529946476216602850469
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.68648224258028306343251831921706739688247601144504140128512428265165106814159
Short name T732
Test name
Test status
Simulation time 486419183 ps
CPU time 12.25 seconds
Started Nov 22 01:50:26 PM PST 23
Finished Nov 22 01:50:39 PM PST 23
Peak memory 238632 kb
Host smart-ed3f73ff-0b7d-473f-8a80-46af844e0de4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=68648224258028306343251831921706739688247601144504140128512428265165106814159 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.68648224258028306343251831921706739688247601144504140128512428265165106814159
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.25472379086570116744359217423984001047269214029237407101437226848707506679395
Short name T835
Test name
Test status
Simulation time 137469183 ps
CPU time 4.12 seconds
Started Nov 22 01:50:27 PM PST 23
Finished Nov 22 01:50:32 PM PST 23
Peak memory 238804 kb
Host smart-5bc8e760-d8b9-44b9-8af6-d9b8408f9426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25472379086570116744359217423984001047269214029237407101437226848707506679395 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_regwen.25472379086570116744359217423984001047269214029237407101437226848707506679395
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.42693994067782284070865247070530940598349839535453022059661741846858528291402
Short name T1044
Test name
Test status
Simulation time 138839183 ps
CPU time 3.06 seconds
Started Nov 22 01:50:23 PM PST 23
Finished Nov 22 01:50:27 PM PST 23
Peak memory 238816 kb
Host smart-5165ecc5-3aa3-4fe5-8e8c-03913a66b3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42693994067782284070865247070530940598349839535453022059661741846858528291402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.otp_ctrl_smoke.42693994067782284070865247070530940598349839535453022059661741846858528291402
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.38079081146742423034648881959601996567714710405787001884949498708705442900235
Short name T786
Test name
Test status
Simulation time 13240088340 ps
CPU time 130.19 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 01:52:25 PM PST 23
Peak memory 241772 kb
Host smart-c18b21c8-dacf-49e1-812d-2823ae10d678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38079081146742423034648881959601996567714710405787001884949498708705442900235 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.38079081146742423034648881959601996567714710405787001884949498708705442900235
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.22375790884612931729916781155266133776158478622667257901042395563559228887365
Short name T1135
Test name
Test status
Simulation time 150268849183 ps
CPU time 1962.07 seconds
Started Nov 22 01:50:06 PM PST 23
Finished Nov 22 02:22:51 PM PST 23
Peak memory 517552 kb
Host smart-8c25265d-c69b-4618-851d-5d669b558d05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237579088461293172991
6781155266133776158478622667257901042395563559228887365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_res
et.22375790884612931729916781155266133776158478622667257901042395563559228887365
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.77259010972708477708005503341725306611767207102261970159455895801667240816776
Short name T839
Test name
Test status
Simulation time 549639183 ps
CPU time 9 seconds
Started Nov 22 01:50:29 PM PST 23
Finished Nov 22 01:50:39 PM PST 23
Peak memory 246948 kb
Host smart-89a58ba8-322e-4e9e-90b4-bac76efe63fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77259010972708477708005503341725306611767207102261970159455895801667240816776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.otp_ctrl_test_access.77259010972708477708005503341725306611767207102261970159455895801667240816776
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.89621090191581381577978212537837739454068491788297860461466442300364450600068
Short name T592
Test name
Test status
Simulation time 156689183 ps
CPU time 3.98 seconds
Started Nov 22 01:51:58 PM PST 23
Finished Nov 22 01:52:03 PM PST 23
Peak memory 238612 kb
Host smart-99a159a1-89c8-4e80-9256-8c17d57c7a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89621090191581381577978212537837739454068491788297860461466442300364450600068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 110.otp_ctrl_init_fail.89621090191581381577978212537837739454068491788297860461466442300364450600068
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.80363414169388946481871329066098998424982470464457152245105700803719300294487
Short name T593
Test name
Test status
Simulation time 176929183 ps
CPU time 4.32 seconds
Started Nov 22 01:52:00 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238680 kb
Host smart-d24bca77-5a52-427d-b596-794b005c347a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80363414169388946481871329066098998424982470464457152245105700803719300294487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.80363414169388946481871329066098998424982470464457152245105700803719300294487
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.90831164886777084426092068741192000165974368967452032458675172121299316017138
Short name T1183
Test name
Test status
Simulation time 156689183 ps
CPU time 4.04 seconds
Started Nov 22 01:52:07 PM PST 23
Finished Nov 22 01:52:14 PM PST 23
Peak memory 238012 kb
Host smart-c95abc54-6b0c-4fae-ab92-b033cc8d5ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90831164886777084426092068741192000165974368967452032458675172121299316017138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 111.otp_ctrl_init_fail.90831164886777084426092068741192000165974368967452032458675172121299316017138
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.3326654061201298259285896465673397926789413737625515748555731595717318105980
Short name T512
Test name
Test status
Simulation time 176929183 ps
CPU time 4.27 seconds
Started Nov 22 01:51:58 PM PST 23
Finished Nov 22 01:52:04 PM PST 23
Peak memory 238576 kb
Host smart-0dfefeec-d5f8-44c4-8e10-f474f8b2df1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326654061201298259285896465673397926789413737625515748555731595717318105980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.3326654061201298259285896465673397926789413737625515748555731595717318105980
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.3007943642425625767518549359566327470387938502664166549930678701572335181009
Short name T354
Test name
Test status
Simulation time 156689183 ps
CPU time 3.97 seconds
Started Nov 22 01:51:56 PM PST 23
Finished Nov 22 01:52:01 PM PST 23
Peak memory 238692 kb
Host smart-c05e6cea-ae5b-47df-a0f2-7ab7738a9554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007943642425625767518549359566327470387938502664166549930678701572335181009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 112.otp_ctrl_init_fail.3007943642425625767518549359566327470387938502664166549930678701572335181009
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.108295082789770907498771352239843217204598027950796120036310934055247871843697
Short name T934
Test name
Test status
Simulation time 176929183 ps
CPU time 4.48 seconds
Started Nov 22 01:51:52 PM PST 23
Finished Nov 22 01:51:59 PM PST 23
Peak memory 238680 kb
Host smart-cd4ce6f6-de9f-4d0c-80bb-064ba64cee11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108295082789770907498771352239843217204598027950796120036310934055247871843697 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.108295082789770907498771352239843217204598027950796120036310934055247871843697
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.88346396483369058992987766704822574231682211338963016089252708808858468161369
Short name T1180
Test name
Test status
Simulation time 156689183 ps
CPU time 3.99 seconds
Started Nov 22 01:51:59 PM PST 23
Finished Nov 22 01:52:05 PM PST 23
Peak memory 238608 kb
Host smart-dd706f00-2f96-4f66-84e8-80368c29670c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88346396483369058992987766704822574231682211338963016089252708808858468161369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 113.otp_ctrl_init_fail.88346396483369058992987766704822574231682211338963016089252708808858468161369
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.105468493915845370922491782010086477101723946455527613206846005578708550427928
Short name T791
Test name
Test status
Simulation time 176929183 ps
CPU time 4.26 seconds
Started Nov 22 01:52:00 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238660 kb
Host smart-726c877b-80f1-446b-b0ca-cc87ea19dbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105468493915845370922491782010086477101723946455527613206846005578708550427928 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.105468493915845370922491782010086477101723946455527613206846005578708550427928
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.78292398491367387194312372302264037424178544766845226596895519411715923950022
Short name T968
Test name
Test status
Simulation time 156689183 ps
CPU time 4.26 seconds
Started Nov 22 01:52:03 PM PST 23
Finished Nov 22 01:52:09 PM PST 23
Peak memory 238652 kb
Host smart-40542cd3-ee29-4493-b780-bab7a4d2d8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78292398491367387194312372302264037424178544766845226596895519411715923950022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 114.otp_ctrl_init_fail.78292398491367387194312372302264037424178544766845226596895519411715923950022
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.84015767826289459389291322352258370673372287714442317878315673762596721365473
Short name T227
Test name
Test status
Simulation time 176929183 ps
CPU time 4.36 seconds
Started Nov 22 01:52:05 PM PST 23
Finished Nov 22 01:52:13 PM PST 23
Peak memory 238676 kb
Host smart-85444eea-8e39-49b7-a626-77b408c7432f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84015767826289459389291322352258370673372287714442317878315673762596721365473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.84015767826289459389291322352258370673372287714442317878315673762596721365473
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.35662122979103551205299002390155781161928625769651299966490752388589209250431
Short name T47
Test name
Test status
Simulation time 156689183 ps
CPU time 4.14 seconds
Started Nov 22 01:51:59 PM PST 23
Finished Nov 22 01:52:04 PM PST 23
Peak memory 238652 kb
Host smart-0df41fbe-d5b2-4287-8810-49a3a8160d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35662122979103551205299002390155781161928625769651299966490752388589209250431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 115.otp_ctrl_init_fail.35662122979103551205299002390155781161928625769651299966490752388589209250431
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.59122575848539330028332460991211578283297203785981211867477021583545137428963
Short name T607
Test name
Test status
Simulation time 176929183 ps
CPU time 4.21 seconds
Started Nov 22 01:52:04 PM PST 23
Finished Nov 22 01:52:12 PM PST 23
Peak memory 238680 kb
Host smart-8f86a101-7f9a-4fea-b6c2-69bf53b7f760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59122575848539330028332460991211578283297203785981211867477021583545137428963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.59122575848539330028332460991211578283297203785981211867477021583545137428963
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.18582088844132995852814714465803898139682057292666482414133110276938941122884
Short name T603
Test name
Test status
Simulation time 156689183 ps
CPU time 3.97 seconds
Started Nov 22 01:52:01 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238588 kb
Host smart-33cdeb12-b7f8-437d-8b90-45d634ab67ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18582088844132995852814714465803898139682057292666482414133110276938941122884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 116.otp_ctrl_init_fail.18582088844132995852814714465803898139682057292666482414133110276938941122884
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.91255814759882864396325943881911016617539121627529313822749201124631750816021
Short name T1131
Test name
Test status
Simulation time 176929183 ps
CPU time 4.4 seconds
Started Nov 22 01:51:59 PM PST 23
Finished Nov 22 01:52:05 PM PST 23
Peak memory 238676 kb
Host smart-198496df-05a0-4e24-bd6d-810dff76187b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91255814759882864396325943881911016617539121627529313822749201124631750816021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.91255814759882864396325943881911016617539121627529313822749201124631750816021
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.50032268705812840629939420870588062037393421095425723783372771072827813772065
Short name T711
Test name
Test status
Simulation time 156689183 ps
CPU time 4.17 seconds
Started Nov 22 01:52:00 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238564 kb
Host smart-2a74e644-2234-4ba2-b73b-4a960dbe7d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50032268705812840629939420870588062037393421095425723783372771072827813772065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 117.otp_ctrl_init_fail.50032268705812840629939420870588062037393421095425723783372771072827813772065
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.9723101877194394013774861003759239655650332884428442667624993984327334217938
Short name T679
Test name
Test status
Simulation time 176929183 ps
CPU time 4.41 seconds
Started Nov 22 01:52:14 PM PST 23
Finished Nov 22 01:52:20 PM PST 23
Peak memory 238564 kb
Host smart-e36a3c46-140e-431a-bc4e-2ac5ebf3ed25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9723101877194394013774861003759239655650332884428442667624993984327334217938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.9723101877194394013774861003759239655650332884428442667624993984327334217938
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.2221935981512078978996921746780353912396147518649389747671970234993373752630
Short name T26
Test name
Test status
Simulation time 156689183 ps
CPU time 4.18 seconds
Started Nov 22 01:52:26 PM PST 23
Finished Nov 22 01:52:37 PM PST 23
Peak memory 238580 kb
Host smart-c1fa5f9f-5311-4e66-96c2-07d867834f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221935981512078978996921746780353912396147518649389747671970234993373752630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 118.otp_ctrl_init_fail.2221935981512078978996921746780353912396147518649389747671970234993373752630
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.109698669390852772057359110153071802464202261339003944398570280340784198050852
Short name T1257
Test name
Test status
Simulation time 176929183 ps
CPU time 4.24 seconds
Started Nov 22 01:51:59 PM PST 23
Finished Nov 22 01:52:05 PM PST 23
Peak memory 238708 kb
Host smart-a5f56b36-c2c0-44c2-b14a-87ba94b28c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109698669390852772057359110153071802464202261339003944398570280340784198050852 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.109698669390852772057359110153071802464202261339003944398570280340784198050852
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.39068434560449422868995328973606465889895690854153568044378959186742224289603
Short name T916
Test name
Test status
Simulation time 156689183 ps
CPU time 3.98 seconds
Started Nov 22 01:52:14 PM PST 23
Finished Nov 22 01:52:21 PM PST 23
Peak memory 238656 kb
Host smart-8b506bae-8825-41dc-9a88-c25723edb88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39068434560449422868995328973606465889895690854153568044378959186742224289603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 119.otp_ctrl_init_fail.39068434560449422868995328973606465889895690854153568044378959186742224289603
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.3377643307318804204107369084317838357992794386361834204501916727985813271680
Short name T1048
Test name
Test status
Simulation time 176929183 ps
CPU time 4.37 seconds
Started Nov 22 01:52:01 PM PST 23
Finished Nov 22 01:52:07 PM PST 23
Peak memory 238700 kb
Host smart-17e9fc61-14a3-4ab3-ac96-6bc640c1a7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377643307318804204107369084317838357992794386361834204501916727985813271680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.3377643307318804204107369084317838357992794386361834204501916727985813271680
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.71437675176423233866392975326951990362057756001453834590062093787322540663570
Short name T1167
Test name
Test status
Simulation time 71069183 ps
CPU time 1.85 seconds
Started Nov 22 01:51:01 PM PST 23
Finished Nov 22 01:51:04 PM PST 23
Peak memory 238464 kb
Host smart-c7d35ef6-ae97-4796-bd0b-ecddc21df775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71437675176423233866392975326951990362057756001453834590062093787322540663570 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.71437675176423233866392975326951990362057756001453834590062093787322540663570
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.28731043712817731170234371427530158013427010640392847297502825412915235690353
Short name T1161
Test name
Test status
Simulation time 390019183 ps
CPU time 11.09 seconds
Started Nov 22 01:50:15 PM PST 23
Finished Nov 22 01:50:32 PM PST 23
Peak memory 238616 kb
Host smart-b014f1ce-6939-44d0-aef4-2ae25edf73ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28731043712817731170234371427530158013427010640392847297502825412915235690353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.otp_ctrl_dai_errs.28731043712817731170234371427530158013427010640392847297502825412915235690353
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.13274933123586176220653193487299460609310564847290400421826053089964005063436
Short name T1177
Test name
Test status
Simulation time 614979183 ps
CPU time 10.89 seconds
Started Nov 22 01:50:33 PM PST 23
Finished Nov 22 01:50:45 PM PST 23
Peak memory 238748 kb
Host smart-4f3a114a-0078-46f5-b04f-5bebffed31d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13274933123586176220653193487299460609310564847290400421826053089964005063436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.otp_ctrl_dai_lock.13274933123586176220653193487299460609310564847290400421826053089964005063436
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.90130042791256821150496221241192105675623454825785525797375976096953558768547
Short name T597
Test name
Test status
Simulation time 156689183 ps
CPU time 4.03 seconds
Started Nov 22 01:50:22 PM PST 23
Finished Nov 22 01:50:27 PM PST 23
Peak memory 238620 kb
Host smart-526bd32b-a55b-415c-92d4-3012a05ccd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90130042791256821150496221241192105675623454825785525797375976096953558768547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.otp_ctrl_init_fail.90130042791256821150496221241192105675623454825785525797375976096953558768547
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.110446559356123343386983549297789967015526560941749034390875535221321994235094
Short name T825
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.72 seconds
Started Nov 22 01:50:28 PM PST 23
Finished Nov 22 01:50:48 PM PST 23
Peak memory 239024 kb
Host smart-049dee9c-2246-4121-b4ae-4d19f27dfcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110446559356123343386983549297789967015526560941749034390875535221321994235094 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.otp_ctrl_macro_errs.110446559356123343386983549297789967015526560941749034390875535221321994235094
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.94081717913310680031791564793392044725015576857788788592593395119736180624933
Short name T1140
Test name
Test status
Simulation time 346349183 ps
CPU time 7.66 seconds
Started Nov 22 01:50:47 PM PST 23
Finished Nov 22 01:50:55 PM PST 23
Peak memory 238740 kb
Host smart-bc5986a4-798f-4e4f-b37f-5550cd19a9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94081717913310680031791564793392044725015576857788788592593395119736180624933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.otp_ctrl_parallel_key_req.94081717913310680031791564793392044725015576857788788592593395119736180624933
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.50826653962753682603199287671177612184288887288370790151727220864448940775827
Short name T1210
Test name
Test status
Simulation time 176929183 ps
CPU time 4.25 seconds
Started Nov 22 01:50:20 PM PST 23
Finished Nov 22 01:50:27 PM PST 23
Peak memory 238520 kb
Host smart-72a8baad-1c08-4db2-95ad-7d5bc94fddf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50826653962753682603199287671177612184288887288370790151727220864448940775827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.50826653962753682603199287671177612184288887288370790151727220864448940775827
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.56286658230034452309979749965871905473652726697930377753242052414602797859811
Short name T1259
Test name
Test status
Simulation time 486419183 ps
CPU time 12.1 seconds
Started Nov 22 01:50:44 PM PST 23
Finished Nov 22 01:50:57 PM PST 23
Peak memory 238724 kb
Host smart-66cbad13-e0c2-4c50-8f1d-a3c57d1cf854
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56286658230034452309979749965871905473652726697930377753242052414602797859811 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.56286658230034452309979749965871905473652726697930377753242052414602797859811
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.89097315677990768085506584092895143844900471594820908342181974103655385195557
Short name T1267
Test name
Test status
Simulation time 137469183 ps
CPU time 3.56 seconds
Started Nov 22 01:51:04 PM PST 23
Finished Nov 22 01:51:09 PM PST 23
Peak memory 238704 kb
Host smart-172f1028-49f6-48ec-9999-942a9d3abb93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89097315677990768085506584092895143844900471594820908342181974103655385195557 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_regwen.89097315677990768085506584092895143844900471594820908342181974103655385195557
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.101686427956163183142732220865146126130929307090485529095452327220724114190855
Short name T364
Test name
Test status
Simulation time 138839183 ps
CPU time 3.04 seconds
Started Nov 22 01:50:11 PM PST 23
Finished Nov 22 01:50:21 PM PST 23
Peak memory 238648 kb
Host smart-e2dad16c-dbc7-4c45-8f96-f530124ee242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101686427956163183142732220865146126130929307090485529095452327220724114190855 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.otp_ctrl_smoke.101686427956163183142732220865146126130929307090485529095452327220724114190855
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.114832136513045889541429675942867405609776704285133436840390950657571732234659
Short name T1206
Test name
Test status
Simulation time 13240088340 ps
CPU time 136.41 seconds
Started Nov 22 01:50:15 PM PST 23
Finished Nov 22 01:52:37 PM PST 23
Peak memory 241832 kb
Host smart-fbf0a395-77f0-4fb0-8280-db5383f89c32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114832136513045889541429675942867405609776704285133436840390950657571732234659 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.114832136513045889541429675942867405609776704285133436840390950657571732234659
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.63358955388067273163502857460998290767037080682903911395350011271435048398170
Short name T247
Test name
Test status
Simulation time 150268849183 ps
CPU time 1937.69 seconds
Started Nov 22 01:50:54 PM PST 23
Finished Nov 22 02:23:13 PM PST 23
Peak memory 517580 kb
Host smart-3ea52c52-356f-4ea2-82f8-06c6fb512ae1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6335895538806727316350
2857460998290767037080682903911395350011271435048398170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_res
et.63358955388067273163502857460998290767037080682903911395350011271435048398170
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.97819874640628133803308764994533210957022282768440277576347888332933163638440
Short name T41
Test name
Test status
Simulation time 549639183 ps
CPU time 9.02 seconds
Started Nov 22 01:50:53 PM PST 23
Finished Nov 22 01:51:03 PM PST 23
Peak memory 246992 kb
Host smart-812c1f8c-721e-4016-931a-144d1eec74a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97819874640628133803308764994533210957022282768440277576347888332933163638440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.otp_ctrl_test_access.97819874640628133803308764994533210957022282768440277576347888332933163638440
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.10121257878349356656515367167859588677225982937998718855692615383008477958645
Short name T371
Test name
Test status
Simulation time 156689183 ps
CPU time 4.08 seconds
Started Nov 22 01:52:11 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238648 kb
Host smart-b67518ae-eff6-49a7-acd2-bb4d951a626e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10121257878349356656515367167859588677225982937998718855692615383008477958645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 120.otp_ctrl_init_fail.10121257878349356656515367167859588677225982937998718855692615383008477958645
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.27063131999306058925772041488445925590350988714962275124224878818461239870028
Short name T233
Test name
Test status
Simulation time 176929183 ps
CPU time 4.49 seconds
Started Nov 22 01:51:57 PM PST 23
Finished Nov 22 01:52:02 PM PST 23
Peak memory 238676 kb
Host smart-f50b7bb5-0a16-4755-a90a-dddb02ce1603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27063131999306058925772041488445925590350988714962275124224878818461239870028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.27063131999306058925772041488445925590350988714962275124224878818461239870028
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.20380972192462566877542067035339545883318976410132947617781998869191569844545
Short name T1302
Test name
Test status
Simulation time 156689183 ps
CPU time 3.99 seconds
Started Nov 22 01:52:03 PM PST 23
Finished Nov 22 01:52:08 PM PST 23
Peak memory 238528 kb
Host smart-c436c206-d494-46a2-9f03-70f9a8ce4ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20380972192462566877542067035339545883318976410132947617781998869191569844545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 121.otp_ctrl_init_fail.20380972192462566877542067035339545883318976410132947617781998869191569844545
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.35743559854590166284905430227820917715233860871898937757998596493336636285919
Short name T736
Test name
Test status
Simulation time 176929183 ps
CPU time 4.4 seconds
Started Nov 22 01:52:10 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238672 kb
Host smart-051869d2-d1f0-401c-874b-e4f3417743cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35743559854590166284905430227820917715233860871898937757998596493336636285919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.35743559854590166284905430227820917715233860871898937757998596493336636285919
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.3022914181033260665062658223773931791751404876287207557587523792145388594631
Short name T494
Test name
Test status
Simulation time 156689183 ps
CPU time 4.08 seconds
Started Nov 22 01:51:59 PM PST 23
Finished Nov 22 01:52:08 PM PST 23
Peak memory 238600 kb
Host smart-688a931d-2328-44fd-965e-8c3e795f3744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022914181033260665062658223773931791751404876287207557587523792145388594631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 122.otp_ctrl_init_fail.3022914181033260665062658223773931791751404876287207557587523792145388594631
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.3892622498877657570826128597340606629128543729956254301315111820151480680158
Short name T818
Test name
Test status
Simulation time 176929183 ps
CPU time 4.25 seconds
Started Nov 22 01:52:02 PM PST 23
Finished Nov 22 01:52:07 PM PST 23
Peak memory 238660 kb
Host smart-3a55e240-e1d3-4918-9b3c-69ce78a1b174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892622498877657570826128597340606629128543729956254301315111820151480680158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.3892622498877657570826128597340606629128543729956254301315111820151480680158
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.104688906404349780984595817658328679452777320796951890082282640410371573050075
Short name T1150
Test name
Test status
Simulation time 156689183 ps
CPU time 4.11 seconds
Started Nov 22 01:52:09 PM PST 23
Finished Nov 22 01:52:17 PM PST 23
Peak memory 238468 kb
Host smart-51ee7427-2b45-49cb-834e-21129b0873eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104688906404349780984595817658328679452777320796951890082282640410371573050075 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 123.otp_ctrl_init_fail.104688906404349780984595817658328679452777320796951890082282640410371573050075
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.27262794692964187182074442317616667181911194268333195134607049598268762745622
Short name T220
Test name
Test status
Simulation time 176929183 ps
CPU time 4.15 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 01:52:22 PM PST 23
Peak memory 238700 kb
Host smart-3798a680-1d27-4367-8c62-da85fbe3b7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27262794692964187182074442317616667181911194268333195134607049598268762745622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.27262794692964187182074442317616667181911194268333195134607049598268762745622
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.27587157242395824852455912918554134406862167575882212112610578175692451863694
Short name T838
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:52:07 PM PST 23
Finished Nov 22 01:52:15 PM PST 23
Peak memory 238632 kb
Host smart-90135b55-8e7e-403d-a56e-65bfadc1b7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27587157242395824852455912918554134406862167575882212112610578175692451863694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 124.otp_ctrl_init_fail.27587157242395824852455912918554134406862167575882212112610578175692451863694
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.63763921111832671456648520695002348924844340543933960421910892260058309008284
Short name T1214
Test name
Test status
Simulation time 176929183 ps
CPU time 4.33 seconds
Started Nov 22 01:52:04 PM PST 23
Finished Nov 22 01:52:12 PM PST 23
Peak memory 238652 kb
Host smart-bb04a03f-127b-4a16-8406-898231248690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63763921111832671456648520695002348924844340543933960421910892260058309008284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.63763921111832671456648520695002348924844340543933960421910892260058309008284
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.42952844287752827808331888958658172437878978533983696247281183459699642117756
Short name T1102
Test name
Test status
Simulation time 156689183 ps
CPU time 3.89 seconds
Started Nov 22 01:52:08 PM PST 23
Finished Nov 22 01:52:15 PM PST 23
Peak memory 238648 kb
Host smart-eb44a03f-3582-448e-8f2c-665a0e9931f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42952844287752827808331888958658172437878978533983696247281183459699642117756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 125.otp_ctrl_init_fail.42952844287752827808331888958658172437878978533983696247281183459699642117756
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.67974759018773670591670329255618380961359881998269386963025618904935636859103
Short name T947
Test name
Test status
Simulation time 176929183 ps
CPU time 4.46 seconds
Started Nov 22 01:52:04 PM PST 23
Finished Nov 22 01:52:12 PM PST 23
Peak memory 238652 kb
Host smart-ae35e3a6-113f-4f82-b3a6-6cf994218a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67974759018773670591670329255618380961359881998269386963025618904935636859103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.67974759018773670591670329255618380961359881998269386963025618904935636859103
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.98864096207195613715318069060339073708136315010199165894561458732131103236862
Short name T1195
Test name
Test status
Simulation time 156689183 ps
CPU time 4.08 seconds
Started Nov 22 01:52:16 PM PST 23
Finished Nov 22 01:52:24 PM PST 23
Peak memory 238648 kb
Host smart-114f8f67-0e65-40c6-a82a-8c73fb10618f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98864096207195613715318069060339073708136315010199165894561458732131103236862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 126.otp_ctrl_init_fail.98864096207195613715318069060339073708136315010199165894561458732131103236862
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.85953213567040156127613499421980262935080041233303262022834341873275131766978
Short name T784
Test name
Test status
Simulation time 176929183 ps
CPU time 4.43 seconds
Started Nov 22 01:52:05 PM PST 23
Finished Nov 22 01:52:13 PM PST 23
Peak memory 238644 kb
Host smart-d4766e8c-3f57-4e4a-84cf-e9d3e9844cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85953213567040156127613499421980262935080041233303262022834341873275131766978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.85953213567040156127613499421980262935080041233303262022834341873275131766978
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.93931553317039551386099029914252084169761791572807696747266029675925924112786
Short name T284
Test name
Test status
Simulation time 156689183 ps
CPU time 4.09 seconds
Started Nov 22 01:52:09 PM PST 23
Finished Nov 22 01:52:17 PM PST 23
Peak memory 238608 kb
Host smart-18829df4-c477-40a8-bbdc-02f09875766c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93931553317039551386099029914252084169761791572807696747266029675925924112786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 127.otp_ctrl_init_fail.93931553317039551386099029914252084169761791572807696747266029675925924112786
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.32488249177760117357287197227922507101994441313992394195578922037556713817672
Short name T706
Test name
Test status
Simulation time 176929183 ps
CPU time 4.39 seconds
Started Nov 22 01:52:33 PM PST 23
Finished Nov 22 01:52:40 PM PST 23
Peak memory 238660 kb
Host smart-7a8eae4b-44ae-45fd-a5cd-2afbde6783ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32488249177760117357287197227922507101994441313992394195578922037556713817672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.32488249177760117357287197227922507101994441313992394195578922037556713817672
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.32436834268357698623406950752426584115029684725364036839513405302456668010067
Short name T57
Test name
Test status
Simulation time 156689183 ps
CPU time 3.97 seconds
Started Nov 22 01:52:02 PM PST 23
Finished Nov 22 01:52:08 PM PST 23
Peak memory 238644 kb
Host smart-7713d960-b35e-4085-831a-caedaca8a466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32436834268357698623406950752426584115029684725364036839513405302456668010067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 128.otp_ctrl_init_fail.32436834268357698623406950752426584115029684725364036839513405302456668010067
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.107044583244289721308897266976569981873284336736181393519417398586507781544359
Short name T731
Test name
Test status
Simulation time 176929183 ps
CPU time 4.23 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 01:52:23 PM PST 23
Peak memory 238676 kb
Host smart-02a2fa1e-98c9-4a2b-a40a-3004d3583836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107044583244289721308897266976569981873284336736181393519417398586507781544359 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.107044583244289721308897266976569981873284336736181393519417398586507781544359
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.112746590388564120280856151394720649960505826489699414560648342214116860809976
Short name T578
Test name
Test status
Simulation time 156689183 ps
CPU time 3.86 seconds
Started Nov 22 01:52:12 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238640 kb
Host smart-fb2a5f8c-5c3d-416a-ae86-fa617bbf500e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112746590388564120280856151394720649960505826489699414560648342214116860809976 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 129.otp_ctrl_init_fail.112746590388564120280856151394720649960505826489699414560648342214116860809976
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.61995008041601068989654605584984133739417623773467620888568066996751358091500
Short name T1146
Test name
Test status
Simulation time 176929183 ps
CPU time 4.57 seconds
Started Nov 22 01:52:08 PM PST 23
Finished Nov 22 01:52:16 PM PST 23
Peak memory 238668 kb
Host smart-d9f39953-34a9-47e1-8379-5e4b4f81b54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61995008041601068989654605584984133739417623773467620888568066996751358091500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.61995008041601068989654605584984133739417623773467620888568066996751358091500
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.98476129070466192951730462978359735872024669843957811953285512658301876239622
Short name T713
Test name
Test status
Simulation time 71069183 ps
CPU time 1.86 seconds
Started Nov 22 01:51:12 PM PST 23
Finished Nov 22 01:51:15 PM PST 23
Peak memory 238436 kb
Host smart-6fa5cd17-c2b1-415d-aec9-0cc8bed9a017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98476129070466192951730462978359735872024669843957811953285512658301876239622 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.98476129070466192951730462978359735872024669843957811953285512658301876239622
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.107632006808967297897625685676178222846159148120017541822539259583692214653094
Short name T1241
Test name
Test status
Simulation time 111269183 ps
CPU time 2.72 seconds
Started Nov 22 01:51:25 PM PST 23
Finished Nov 22 01:51:31 PM PST 23
Peak memory 246716 kb
Host smart-ca919c64-8a9f-49ba-b42c-ae9b397a7c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107632006808967297897625685676178222846159148120017541822539259583692214653094 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.otp_ctrl_check_fail.107632006808967297897625685676178222846159148120017541822539259583692214653094
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.12099465162650488063050730982456260042921895388547494977500504233208717254035
Short name T470
Test name
Test status
Simulation time 390019183 ps
CPU time 10.64 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:35 PM PST 23
Peak memory 238668 kb
Host smart-9bf131d1-0e16-494c-a7a9-36337bbc7c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12099465162650488063050730982456260042921895388547494977500504233208717254035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.otp_ctrl_dai_errs.12099465162650488063050730982456260042921895388547494977500504233208717254035
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.62270806184478863840015109280138028529109519475911142853793417814473864906247
Short name T506
Test name
Test status
Simulation time 614979183 ps
CPU time 10.31 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 01:51:15 PM PST 23
Peak memory 238680 kb
Host smart-fccb4972-6ddd-4f1a-9ecf-9a3c1772ec65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62270806184478863840015109280138028529109519475911142853793417814473864906247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.otp_ctrl_dai_lock.62270806184478863840015109280138028529109519475911142853793417814473864906247
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.21038945190252529534904877450043055473853987419217483450205112991848719951225
Short name T268
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:51:19 PM PST 23
Finished Nov 22 01:51:26 PM PST 23
Peak memory 238556 kb
Host smart-dd8a951a-adea-41f8-958e-becb50627c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21038945190252529534904877450043055473853987419217483450205112991848719951225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.otp_ctrl_init_fail.21038945190252529534904877450043055473853987419217483450205112991848719951225
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.32047591901802506891599173379539459358875649917094225781767498289780489922250
Short name T1114
Test name
Test status
Simulation time 1137629183 ps
CPU time 18.56 seconds
Started Nov 22 01:51:02 PM PST 23
Finished Nov 22 01:51:22 PM PST 23
Peak memory 239020 kb
Host smart-85653762-59e9-4b9d-86b8-22f5c77696b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32047591901802506891599173379539459358875649917094225781767498289780489922250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.otp_ctrl_macro_errs.32047591901802506891599173379539459358875649917094225781767498289780489922250
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.8394410283988082847398139350460585942585065031487666980314880997201888466681
Short name T1057
Test name
Test status
Simulation time 346349183 ps
CPU time 7.59 seconds
Started Nov 22 01:51:04 PM PST 23
Finished Nov 22 01:51:13 PM PST 23
Peak memory 238744 kb
Host smart-2e9bcaf5-5db2-4275-bf67-48755a16d747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8394410283988082847398139350460585942585065031487666980314880997201888466681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.otp_ctrl_parallel_key_req.8394410283988082847398139350460585942585065031487666980314880997201888466681
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.87394834355386422906541993662200780069619780815038799545577656671676379163475
Short name T488
Test name
Test status
Simulation time 176929183 ps
CPU time 4.32 seconds
Started Nov 22 01:51:05 PM PST 23
Finished Nov 22 01:51:11 PM PST 23
Peak memory 238684 kb
Host smart-32d93132-b17e-41fc-a34f-e4d03810196e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87394834355386422906541993662200780069619780815038799545577656671676379163475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.87394834355386422906541993662200780069619780815038799545577656671676379163475
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.83200358541947443919680894721110766144632318217037754954672244606444443108637
Short name T1289
Test name
Test status
Simulation time 486419183 ps
CPU time 11.57 seconds
Started Nov 22 01:51:01 PM PST 23
Finished Nov 22 01:51:13 PM PST 23
Peak memory 238592 kb
Host smart-8ad67157-532c-417a-ae88-92dae7c632b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83200358541947443919680894721110766144632318217037754954672244606444443108637 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.83200358541947443919680894721110766144632318217037754954672244606444443108637
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.99328489258777593216434883004074418402179118864654953330715339765803353856141
Short name T1266
Test name
Test status
Simulation time 137469183 ps
CPU time 3.64 seconds
Started Nov 22 01:51:26 PM PST 23
Finished Nov 22 01:51:33 PM PST 23
Peak memory 238656 kb
Host smart-80413386-5ac5-4539-b6ff-3855e7bcc301
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99328489258777593216434883004074418402179118864654953330715339765803353856141 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_regwen.99328489258777593216434883004074418402179118864654953330715339765803353856141
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.103164068049988769917468839764759331062992494577662354203307388491047851213619
Short name T541
Test name
Test status
Simulation time 138839183 ps
CPU time 3.12 seconds
Started Nov 22 01:51:29 PM PST 23
Finished Nov 22 01:51:34 PM PST 23
Peak memory 238812 kb
Host smart-fc70a742-77b1-49be-ad88-c28bd6f888be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103164068049988769917468839764759331062992494577662354203307388491047851213619 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.otp_ctrl_smoke.103164068049988769917468839764759331062992494577662354203307388491047851213619
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.111644155286990784403545435861224666216802361273655770378626530855740344509998
Short name T69
Test name
Test status
Simulation time 13240088340 ps
CPU time 135.52 seconds
Started Nov 22 01:50:56 PM PST 23
Finished Nov 22 01:53:13 PM PST 23
Peak memory 241832 kb
Host smart-980816a9-f913-49e9-87d1-164da19deaba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111644155286990784403545435861224666216802361273655770378626530855740344509998 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.111644155286990784403545435861224666216802361273655770378626530855740344509998
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.73438132279360384917992387296988875069413782869367950961844558517961400431218
Short name T895
Test name
Test status
Simulation time 150268849183 ps
CPU time 1977.85 seconds
Started Nov 22 01:51:14 PM PST 23
Finished Nov 22 02:24:15 PM PST 23
Peak memory 517572 kb
Host smart-20d69487-7289-41a9-b8ea-48915b793571
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7343813227936038491799
2387296988875069413782869367950961844558517961400431218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_res
et.73438132279360384917992387296988875069413782869367950961844558517961400431218
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.54784326495168807838993999749531151924299960290978775860146207954678840415559
Short name T691
Test name
Test status
Simulation time 549639183 ps
CPU time 9.36 seconds
Started Nov 22 01:51:35 PM PST 23
Finished Nov 22 01:51:48 PM PST 23
Peak memory 247016 kb
Host smart-00e5751b-8b57-428a-a5ab-4648edeb6fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54784326495168807838993999749531151924299960290978775860146207954678840415559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.otp_ctrl_test_access.54784326495168807838993999749531151924299960290978775860146207954678840415559
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.58269787852127233420050393064428487212760621115479809943624789553151458793624
Short name T913
Test name
Test status
Simulation time 156689183 ps
CPU time 4.31 seconds
Started Nov 22 01:52:06 PM PST 23
Finished Nov 22 01:52:13 PM PST 23
Peak memory 238636 kb
Host smart-e8bde13e-a61f-4f47-92a0-8b2c82f0a78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58269787852127233420050393064428487212760621115479809943624789553151458793624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 130.otp_ctrl_init_fail.58269787852127233420050393064428487212760621115479809943624789553151458793624
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.40205639246375243862119499972574644770376098577071515914780867369574133179517
Short name T67
Test name
Test status
Simulation time 176929183 ps
CPU time 4.32 seconds
Started Nov 22 01:52:12 PM PST 23
Finished Nov 22 01:52:19 PM PST 23
Peak memory 238680 kb
Host smart-2bb899d8-f348-4bdb-b570-b5ff8394845d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40205639246375243862119499972574644770376098577071515914780867369574133179517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.40205639246375243862119499972574644770376098577071515914780867369574133179517
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.26978554679511753093514431089064805789086239308513760891651347243579819850759
Short name T1071
Test name
Test status
Simulation time 156689183 ps
CPU time 4.07 seconds
Started Nov 22 01:51:55 PM PST 23
Finished Nov 22 01:52:01 PM PST 23
Peak memory 238736 kb
Host smart-6f1ec4d5-bfac-4c50-bde2-921c71eae25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26978554679511753093514431089064805789086239308513760891651347243579819850759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 131.otp_ctrl_init_fail.26978554679511753093514431089064805789086239308513760891651347243579819850759
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.18373706247691693124288574326414442285260204130536197910586355174366244614762
Short name T390
Test name
Test status
Simulation time 176929183 ps
CPU time 4.38 seconds
Started Nov 22 01:51:56 PM PST 23
Finished Nov 22 01:52:01 PM PST 23
Peak memory 238700 kb
Host smart-9a8564e4-f9c6-42b0-8d70-190f18b6d820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18373706247691693124288574326414442285260204130536197910586355174366244614762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.18373706247691693124288574326414442285260204130536197910586355174366244614762
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.87166077332508216806429108442343577349278790561929632277962314559540395050286
Short name T1300
Test name
Test status
Simulation time 156689183 ps
CPU time 4.1 seconds
Started Nov 22 01:52:25 PM PST 23
Finished Nov 22 01:52:31 PM PST 23
Peak memory 238608 kb
Host smart-5e5327a0-e3ee-49ef-9424-1f0c6ddaab48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87166077332508216806429108442343577349278790561929632277962314559540395050286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 132.otp_ctrl_init_fail.87166077332508216806429108442343577349278790561929632277962314559540395050286
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.10504180035325050548051022770511746627829756434224083991196034281063279387558
Short name T320
Test name
Test status
Simulation time 176929183 ps
CPU time 4.42 seconds
Started Nov 22 01:52:08 PM PST 23
Finished Nov 22 01:52:16 PM PST 23
Peak memory 238564 kb
Host smart-f00a7b8e-ddd3-4db4-8d45-dc5b83ea1be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10504180035325050548051022770511746627829756434224083991196034281063279387558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.10504180035325050548051022770511746627829756434224083991196034281063279387558
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.22865540071276677781536042391478889402852940981367125495948447719329308247172
Short name T787
Test name
Test status
Simulation time 156689183 ps
CPU time 3.9 seconds
Started Nov 22 01:52:04 PM PST 23
Finished Nov 22 01:52:11 PM PST 23
Peak memory 238656 kb
Host smart-e7d829b2-e1fc-462e-ba76-23f6788f98ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22865540071276677781536042391478889402852940981367125495948447719329308247172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 133.otp_ctrl_init_fail.22865540071276677781536042391478889402852940981367125495948447719329308247172
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.15399254152226745209867108653315040287365196707217433431202708505505978803727
Short name T64
Test name
Test status
Simulation time 176929183 ps
CPU time 4.46 seconds
Started Nov 22 01:52:10 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238548 kb
Host smart-5271fbc7-7af7-46fa-879e-9605bb84bde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15399254152226745209867108653315040287365196707217433431202708505505978803727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.15399254152226745209867108653315040287365196707217433431202708505505978803727
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.13261272180910899491184735142732762098183805491122517064403605817571332853872
Short name T416
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:52:18 PM PST 23
Finished Nov 22 01:52:26 PM PST 23
Peak memory 238584 kb
Host smart-44f5c73d-1449-4e24-adb9-a6cd7b974520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13261272180910899491184735142732762098183805491122517064403605817571332853872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 134.otp_ctrl_init_fail.13261272180910899491184735142732762098183805491122517064403605817571332853872
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.56572315316675260944797531795835719028172962139533482317039705111718850566364
Short name T276
Test name
Test status
Simulation time 156689183 ps
CPU time 4.09 seconds
Started Nov 22 01:51:56 PM PST 23
Finished Nov 22 01:52:02 PM PST 23
Peak memory 238628 kb
Host smart-cdf5e610-4cdf-4624-a141-b9c0389e40fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56572315316675260944797531795835719028172962139533482317039705111718850566364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 135.otp_ctrl_init_fail.56572315316675260944797531795835719028172962139533482317039705111718850566364
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.110426332463382170173210474877530898750291686866128719891160995017295147108660
Short name T1076
Test name
Test status
Simulation time 176929183 ps
CPU time 4.3 seconds
Started Nov 22 01:51:59 PM PST 23
Finished Nov 22 01:52:05 PM PST 23
Peak memory 238588 kb
Host smart-809509af-2a9a-4edd-ade4-716574fc938e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110426332463382170173210474877530898750291686866128719891160995017295147108660 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.110426332463382170173210474877530898750291686866128719891160995017295147108660
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.106747774566566716364419342734119867947172586996754147557853354588544557097357
Short name T264
Test name
Test status
Simulation time 156689183 ps
CPU time 4.26 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 01:52:21 PM PST 23
Peak memory 238644 kb
Host smart-df881db6-7c51-45a0-94a5-6c95b2bbb351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106747774566566716364419342734119867947172586996754147557853354588544557097357 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 136.otp_ctrl_init_fail.106747774566566716364419342734119867947172586996754147557853354588544557097357
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.53137676578414211134904523876019508425005971464769447129795754277142240540397
Short name T234
Test name
Test status
Simulation time 176929183 ps
CPU time 4.35 seconds
Started Nov 22 01:52:01 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238660 kb
Host smart-aa8652a7-fb38-4008-8d81-c67192c984fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53137676578414211134904523876019508425005971464769447129795754277142240540397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.53137676578414211134904523876019508425005971464769447129795754277142240540397
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.88852629584437801830072748898729967245896294274680621492208216387227282649636
Short name T804
Test name
Test status
Simulation time 156689183 ps
CPU time 4.15 seconds
Started Nov 22 01:52:13 PM PST 23
Finished Nov 22 01:52:19 PM PST 23
Peak memory 238648 kb
Host smart-6f1518eb-4538-45f7-bd22-cba98ea33a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88852629584437801830072748898729967245896294274680621492208216387227282649636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 137.otp_ctrl_init_fail.88852629584437801830072748898729967245896294274680621492208216387227282649636
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.80431671048115404618979487183964465732130022399222341410215459086390546421514
Short name T943
Test name
Test status
Simulation time 176929183 ps
CPU time 4.35 seconds
Started Nov 22 01:52:11 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238680 kb
Host smart-e282252f-221b-41f0-9cf1-bb5314e2d0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80431671048115404618979487183964465732130022399222341410215459086390546421514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.80431671048115404618979487183964465732130022399222341410215459086390546421514
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.32970616845704621883682679390786077535247729410201441379419376252411038499291
Short name T769
Test name
Test status
Simulation time 156689183 ps
CPU time 4.04 seconds
Started Nov 22 01:52:16 PM PST 23
Finished Nov 22 01:52:23 PM PST 23
Peak memory 238636 kb
Host smart-9ad45249-ccda-4b1a-9ca6-bc00a4ffdb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32970616845704621883682679390786077535247729410201441379419376252411038499291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 138.otp_ctrl_init_fail.32970616845704621883682679390786077535247729410201441379419376252411038499291
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.93749023413170699253865420100605881151541094692537009601102397345482913691774
Short name T1268
Test name
Test status
Simulation time 176929183 ps
CPU time 4.23 seconds
Started Nov 22 01:52:11 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238680 kb
Host smart-60513696-8566-40e4-be97-90ddd65c57e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93749023413170699253865420100605881151541094692537009601102397345482913691774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.93749023413170699253865420100605881151541094692537009601102397345482913691774
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.1582572075169242547344769358781385908780869098469156515527096814905834474539
Short name T435
Test name
Test status
Simulation time 156689183 ps
CPU time 3.91 seconds
Started Nov 22 01:52:03 PM PST 23
Finished Nov 22 01:52:08 PM PST 23
Peak memory 238504 kb
Host smart-3e8635f8-87f8-433a-bfdf-04cdbeba60af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582572075169242547344769358781385908780869098469156515527096814905834474539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 139.otp_ctrl_init_fail.1582572075169242547344769358781385908780869098469156515527096814905834474539
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.101987279664961700886759108942633835560789001898789165198123561295934515452728
Short name T806
Test name
Test status
Simulation time 176929183 ps
CPU time 4.5 seconds
Started Nov 22 01:52:00 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238704 kb
Host smart-389ea255-617d-4a7c-8e28-d3f733bb4f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101987279664961700886759108942633835560789001898789165198123561295934515452728 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.101987279664961700886759108942633835560789001898789165198123561295934515452728
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.86436907331330954988840969821373348977699660531367194092745466863335454311509
Short name T476
Test name
Test status
Simulation time 71069183 ps
CPU time 1.87 seconds
Started Nov 22 01:50:19 PM PST 23
Finished Nov 22 01:50:24 PM PST 23
Peak memory 238452 kb
Host smart-d2a4ae2e-03d8-4d26-bea0-d4c0a048303a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86436907331330954988840969821373348977699660531367194092745466863335454311509 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.86436907331330954988840969821373348977699660531367194092745466863335454311509
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.12727903659481183048587224111247916769283409369036467977224478709827012847467
Short name T961
Test name
Test status
Simulation time 111269183 ps
CPU time 2.65 seconds
Started Nov 22 01:50:16 PM PST 23
Finished Nov 22 01:50:24 PM PST 23
Peak memory 246788 kb
Host smart-7d2b9c4b-c3c0-4290-b502-478b265f5977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12727903659481183048587224111247916769283409369036467977224478709827012847467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.otp_ctrl_check_fail.12727903659481183048587224111247916769283409369036467977224478709827012847467
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.101028055215920538148476251815380149568476946032450011549355190476103854726595
Short name T313
Test name
Test status
Simulation time 614979183 ps
CPU time 10.29 seconds
Started Nov 22 01:50:25 PM PST 23
Finished Nov 22 01:50:37 PM PST 23
Peak memory 238540 kb
Host smart-93776fb6-ef11-4ea2-9391-6015420b1bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101028055215920538148476251815380149568476946032450011549355190476103854726595 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.otp_ctrl_dai_lock.101028055215920538148476251815380149568476946032450011549355190476103854726595
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.79240068271596086047375204485779672394655425163950498404651597695323560010490
Short name T1111
Test name
Test status
Simulation time 156689183 ps
CPU time 4.02 seconds
Started Nov 22 01:51:17 PM PST 23
Finished Nov 22 01:51:23 PM PST 23
Peak memory 238528 kb
Host smart-14fc78f9-52a9-4c4d-882e-3df3be219328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79240068271596086047375204485779672394655425163950498404651597695323560010490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.otp_ctrl_init_fail.79240068271596086047375204485779672394655425163950498404651597695323560010490
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.47083664882431078705485043147627593507925027004472147384781044429669517494696
Short name T287
Test name
Test status
Simulation time 1137629183 ps
CPU time 20.07 seconds
Started Nov 22 01:50:25 PM PST 23
Finished Nov 22 01:50:46 PM PST 23
Peak memory 238992 kb
Host smart-8c5c7080-30cb-4d3e-aacc-d5d4b34ee6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47083664882431078705485043147627593507925027004472147384781044429669517494696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.otp_ctrl_macro_errs.47083664882431078705485043147627593507925027004472147384781044429669517494696
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.22886642057758973595022957951359358065276877414372394077292968002724244088572
Short name T384
Test name
Test status
Simulation time 346349183 ps
CPU time 7.77 seconds
Started Nov 22 01:50:20 PM PST 23
Finished Nov 22 01:50:30 PM PST 23
Peak memory 238780 kb
Host smart-ac52c66b-4e07-4b4d-8f8a-f6b6ded83269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22886642057758973595022957951359358065276877414372394077292968002724244088572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.otp_ctrl_parallel_key_req.22886642057758973595022957951359358065276877414372394077292968002724244088572
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.33495358806887265220856833280941520961900872168468519967418071718748144929386
Short name T348
Test name
Test status
Simulation time 176929183 ps
CPU time 4.33 seconds
Started Nov 22 01:51:28 PM PST 23
Finished Nov 22 01:51:35 PM PST 23
Peak memory 238716 kb
Host smart-eaf77ea3-25c1-4a4f-ad2b-3990cd1434c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33495358806887265220856833280941520961900872168468519967418071718748144929386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.33495358806887265220856833280941520961900872168468519967418071718748144929386
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.11575896136399103202982317938466746938579028631281127394552245402421485506959
Short name T1077
Test name
Test status
Simulation time 486419183 ps
CPU time 11.83 seconds
Started Nov 22 01:51:20 PM PST 23
Finished Nov 22 01:51:35 PM PST 23
Peak memory 238628 kb
Host smart-ca544396-262b-4c46-832a-4e3d219410b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11575896136399103202982317938466746938579028631281127394552245402421485506959 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.11575896136399103202982317938466746938579028631281127394552245402421485506959
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.68835695568294691320191553899773107649905247626172994485958542826140496441650
Short name T468
Test name
Test status
Simulation time 137469183 ps
CPU time 3.74 seconds
Started Nov 22 01:50:54 PM PST 23
Finished Nov 22 01:50:58 PM PST 23
Peak memory 238692 kb
Host smart-c44e1a3a-590c-47a4-9816-5a7fc62601a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=68835695568294691320191553899773107649905247626172994485958542826140496441650 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_regwen.68835695568294691320191553899773107649905247626172994485958542826140496441650
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.11634319461286412426444022343214516696721470684976064521393918471400375636347
Short name T1165
Test name
Test status
Simulation time 138839183 ps
CPU time 3.04 seconds
Started Nov 22 01:51:35 PM PST 23
Finished Nov 22 01:51:42 PM PST 23
Peak memory 238716 kb
Host smart-fc67e2c2-b4f5-46f0-be15-ebeaa6ec0417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11634319461286412426444022343214516696721470684976064521393918471400375636347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.otp_ctrl_smoke.11634319461286412426444022343214516696721470684976064521393918471400375636347
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.84900866080141959271184614316685407943351038124035779652401330949367781208730
Short name T834
Test name
Test status
Simulation time 13240088340 ps
CPU time 132.76 seconds
Started Nov 22 01:50:26 PM PST 23
Finished Nov 22 01:52:40 PM PST 23
Peak memory 241832 kb
Host smart-6367a0df-61e5-4d53-a584-deebd205e6c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84900866080141959271184614316685407943351038124035779652401330949367781208730 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.84900866080141959271184614316685407943351038124035779652401330949367781208730
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.115141928123441999484700900845248912550550395914085876369824994164594426807102
Short name T722
Test name
Test status
Simulation time 150268849183 ps
CPU time 1962.92 seconds
Started Nov 22 01:50:24 PM PST 23
Finished Nov 22 02:23:09 PM PST 23
Peak memory 517580 kb
Host smart-bd1635b4-888a-4825-a5e6-d3907c556cc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151419281234419994847
00900845248912550550395914085876369824994164594426807102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_re
set.115141928123441999484700900845248912550550395914085876369824994164594426807102
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.82878267581811682702857002840593509097963591411626644880780089092427589018338
Short name T37
Test name
Test status
Simulation time 549639183 ps
CPU time 9.52 seconds
Started Nov 22 01:50:24 PM PST 23
Finished Nov 22 01:50:35 PM PST 23
Peak memory 247020 kb
Host smart-c0952dfb-e886-4cf5-ab8e-7cc727c74035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82878267581811682702857002840593509097963591411626644880780089092427589018338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.otp_ctrl_test_access.82878267581811682702857002840593509097963591411626644880780089092427589018338
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.92387241767101307390476323594431995602702584064129536640718176177758454264681
Short name T1205
Test name
Test status
Simulation time 156689183 ps
CPU time 4.1 seconds
Started Nov 22 01:52:00 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238564 kb
Host smart-e2214b46-9372-43fd-a5e6-e45f09fe43e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92387241767101307390476323594431995602702584064129536640718176177758454264681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 140.otp_ctrl_init_fail.92387241767101307390476323594431995602702584064129536640718176177758454264681
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.101228427801770976013628618847584809039913211960637647927152200330836509123886
Short name T388
Test name
Test status
Simulation time 176929183 ps
CPU time 4.05 seconds
Started Nov 22 01:52:40 PM PST 23
Finished Nov 22 01:52:50 PM PST 23
Peak memory 236872 kb
Host smart-cf24b6d7-0d97-4eeb-a508-d8d88246d434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101228427801770976013628618847584809039913211960637647927152200330836509123886 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.101228427801770976013628618847584809039913211960637647927152200330836509123886
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.108208952158664039378382358556829371520803010093504235771716999233660735096705
Short name T886
Test name
Test status
Simulation time 156689183 ps
CPU time 4.08 seconds
Started Nov 22 01:52:18 PM PST 23
Finished Nov 22 01:52:26 PM PST 23
Peak memory 238684 kb
Host smart-c3b559c8-1960-42fc-93e5-eed48b177c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108208952158664039378382358556829371520803010093504235771716999233660735096705 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 141.otp_ctrl_init_fail.108208952158664039378382358556829371520803010093504235771716999233660735096705
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.31507320169573241324860756157220546378383953730904931534637745183533103619191
Short name T1172
Test name
Test status
Simulation time 176929183 ps
CPU time 4.54 seconds
Started Nov 22 01:52:13 PM PST 23
Finished Nov 22 01:52:20 PM PST 23
Peak memory 238720 kb
Host smart-86da2aa1-d310-46b2-87c7-cc577e0d9f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31507320169573241324860756157220546378383953730904931534637745183533103619191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.31507320169573241324860756157220546378383953730904931534637745183533103619191
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.6171406378568076139383205510170278247745959694028632579297323758100128010368
Short name T928
Test name
Test status
Simulation time 156689183 ps
CPU time 3.92 seconds
Started Nov 22 01:52:29 PM PST 23
Finished Nov 22 01:52:38 PM PST 23
Peak memory 238660 kb
Host smart-13bcdfee-30f3-4f00-afa1-0b2c001952af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6171406378568076139383205510170278247745959694028632579297323758100128010368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 142.otp_ctrl_init_fail.6171406378568076139383205510170278247745959694028632579297323758100128010368
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.91903137753267109857940076410602557528648321967648381986621061011610959615582
Short name T235
Test name
Test status
Simulation time 176929183 ps
CPU time 4.08 seconds
Started Nov 22 01:52:33 PM PST 23
Finished Nov 22 01:52:40 PM PST 23
Peak memory 238444 kb
Host smart-b23139ca-1bf7-4822-b0cd-678ea9f5c1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91903137753267109857940076410602557528648321967648381986621061011610959615582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.91903137753267109857940076410602557528648321967648381986621061011610959615582
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.71109214807918914951373426264173292932706341617731368558753075416527995808631
Short name T931
Test name
Test status
Simulation time 156689183 ps
CPU time 3.89 seconds
Started Nov 22 01:52:34 PM PST 23
Finished Nov 22 01:52:41 PM PST 23
Peak memory 238476 kb
Host smart-c8e62eaa-3945-4662-b7c7-38fde57a8bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71109214807918914951373426264173292932706341617731368558753075416527995808631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 143.otp_ctrl_init_fail.71109214807918914951373426264173292932706341617731368558753075416527995808631
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.17172465411868351975580341220569656526233618463981768234456175470627914355815
Short name T325
Test name
Test status
Simulation time 176929183 ps
CPU time 4.27 seconds
Started Nov 22 01:52:36 PM PST 23
Finished Nov 22 01:52:48 PM PST 23
Peak memory 238532 kb
Host smart-76ca8820-65f2-4ab0-a07f-86c6ec4da98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17172465411868351975580341220569656526233618463981768234456175470627914355815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.17172465411868351975580341220569656526233618463981768234456175470627914355815
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.90147972804581673450166333762888564996670802017412940879602850564630621761458
Short name T1127
Test name
Test status
Simulation time 156689183 ps
CPU time 3.73 seconds
Started Nov 22 01:52:04 PM PST 23
Finished Nov 22 01:52:11 PM PST 23
Peak memory 238384 kb
Host smart-e8801f56-21ff-4cb8-a581-843ad5fb0f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90147972804581673450166333762888564996670802017412940879602850564630621761458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 144.otp_ctrl_init_fail.90147972804581673450166333762888564996670802017412940879602850564630621761458
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.5627828071939976765122716309342773902117643970405110958565043955359014633451
Short name T978
Test name
Test status
Simulation time 176929183 ps
CPU time 4.38 seconds
Started Nov 22 01:52:33 PM PST 23
Finished Nov 22 01:52:40 PM PST 23
Peak memory 238616 kb
Host smart-757d6daf-6208-4d27-90f4-d265bc59a06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5627828071939976765122716309342773902117643970405110958565043955359014633451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.5627828071939976765122716309342773902117643970405110958565043955359014633451
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.17826716970715903344656178361957864400598802813437882147315994045936930220227
Short name T245
Test name
Test status
Simulation time 156689183 ps
CPU time 4.06 seconds
Started Nov 22 01:52:13 PM PST 23
Finished Nov 22 01:52:26 PM PST 23
Peak memory 238652 kb
Host smart-ae35ded6-b107-4f76-8e1f-7b12a79491b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17826716970715903344656178361957864400598802813437882147315994045936930220227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 145.otp_ctrl_init_fail.17826716970715903344656178361957864400598802813437882147315994045936930220227
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.39981294669496983679692561929424637288115663899213462220353456274913768177743
Short name T906
Test name
Test status
Simulation time 176929183 ps
CPU time 4.47 seconds
Started Nov 22 01:52:00 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238704 kb
Host smart-1794e7b1-c474-4d11-8ae2-c6cda6ef5a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39981294669496983679692561929424637288115663899213462220353456274913768177743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.39981294669496983679692561929424637288115663899213462220353456274913768177743
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.64050765614454934558589771598189157258066702501092895084694860949894666855029
Short name T461
Test name
Test status
Simulation time 156689183 ps
CPU time 3.68 seconds
Started Nov 22 01:52:32 PM PST 23
Finished Nov 22 01:52:39 PM PST 23
Peak memory 238384 kb
Host smart-914055e3-cbd3-41b4-b7db-dfee0e554f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64050765614454934558589771598189157258066702501092895084694860949894666855029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 146.otp_ctrl_init_fail.64050765614454934558589771598189157258066702501092895084694860949894666855029
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.2168959814923379535485547704308077952159624865784980999358372256147952251886
Short name T256
Test name
Test status
Simulation time 176929183 ps
CPU time 4.48 seconds
Started Nov 22 01:52:05 PM PST 23
Finished Nov 22 01:52:12 PM PST 23
Peak memory 238704 kb
Host smart-34b2fbab-e003-46b7-8e64-05472f21c085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168959814923379535485547704308077952159624865784980999358372256147952251886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.2168959814923379535485547704308077952159624865784980999358372256147952251886
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.4461490888455510244250084783583040591651507399167221534770979918562496915557
Short name T898
Test name
Test status
Simulation time 156689183 ps
CPU time 3.81 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 01:52:22 PM PST 23
Peak memory 238472 kb
Host smart-a84b26c7-86a1-4738-bf6c-3c51ca34309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4461490888455510244250084783583040591651507399167221534770979918562496915557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 147.otp_ctrl_init_fail.4461490888455510244250084783583040591651507399167221534770979918562496915557
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.8546273468076922341129046586299725543255413312851997471834200167256391571061
Short name T875
Test name
Test status
Simulation time 176929183 ps
CPU time 4.2 seconds
Started Nov 22 01:52:25 PM PST 23
Finished Nov 22 01:52:31 PM PST 23
Peak memory 238600 kb
Host smart-07f68134-7102-4316-a867-17e01be3563f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8546273468076922341129046586299725543255413312851997471834200167256391571061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.8546273468076922341129046586299725543255413312851997471834200167256391571061
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.113677252312878623458445894803898008095033194014551473910738432036357606700981
Short name T1067
Test name
Test status
Simulation time 156689183 ps
CPU time 3.91 seconds
Started Nov 22 01:52:17 PM PST 23
Finished Nov 22 01:52:25 PM PST 23
Peak memory 238476 kb
Host smart-de07323b-96f9-46b3-9dff-0e474a70d0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113677252312878623458445894803898008095033194014551473910738432036357606700981 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 148.otp_ctrl_init_fail.113677252312878623458445894803898008095033194014551473910738432036357606700981
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.5993571281134937634694182847191894247227864282374051016778196024798634000307
Short name T698
Test name
Test status
Simulation time 176929183 ps
CPU time 4.5 seconds
Started Nov 22 01:52:08 PM PST 23
Finished Nov 22 01:52:17 PM PST 23
Peak memory 238688 kb
Host smart-7fd4b55a-cfdf-4b70-a3ba-9db138fab1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5993571281134937634694182847191894247227864282374051016778196024798634000307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.5993571281134937634694182847191894247227864282374051016778196024798634000307
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.24413441993738137426988473494463088645176063828074785749960946323386319898289
Short name T559
Test name
Test status
Simulation time 156689183 ps
CPU time 3.97 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 01:52:22 PM PST 23
Peak memory 238644 kb
Host smart-36b09371-162f-43b2-924d-8c9d08c1aff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24413441993738137426988473494463088645176063828074785749960946323386319898289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 149.otp_ctrl_init_fail.24413441993738137426988473494463088645176063828074785749960946323386319898289
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.86552226946409451659728064830692655807056273516006942151426579717972920308289
Short name T477
Test name
Test status
Simulation time 176929183 ps
CPU time 4.35 seconds
Started Nov 22 01:52:05 PM PST 23
Finished Nov 22 01:52:12 PM PST 23
Peak memory 238652 kb
Host smart-25c5a738-2552-4a3e-bd0b-4569da833b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86552226946409451659728064830692655807056273516006942151426579717972920308289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.86552226946409451659728064830692655807056273516006942151426579717972920308289
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.100849381889553259227508228682798129007240769809539379113799753621811323721888
Short name T1026
Test name
Test status
Simulation time 71069183 ps
CPU time 1.88 seconds
Started Nov 22 01:51:20 PM PST 23
Finished Nov 22 01:51:24 PM PST 23
Peak memory 238456 kb
Host smart-84903b2f-629b-435d-98b7-c99f88d3cb64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100849381889553259227508228682798129007240769809539379113799753621811323721888 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.100849381889553259227508228682798129007240769809539379113799753621811323721888
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.71298935416549741375846123783201210310381108331275668822666324476758331646445
Short name T757
Test name
Test status
Simulation time 111269183 ps
CPU time 2.72 seconds
Started Nov 22 01:50:43 PM PST 23
Finished Nov 22 01:50:46 PM PST 23
Peak memory 246656 kb
Host smart-b52f2e3a-26cd-44ff-9ee6-95eb7584dc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71298935416549741375846123783201210310381108331275668822666324476758331646445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.otp_ctrl_check_fail.71298935416549741375846123783201210310381108331275668822666324476758331646445
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.115429736152916513300692769547263398145456276871064683704654045702156490197753
Short name T773
Test name
Test status
Simulation time 390019183 ps
CPU time 11.2 seconds
Started Nov 22 01:50:43 PM PST 23
Finished Nov 22 01:50:55 PM PST 23
Peak memory 238644 kb
Host smart-4a39bff1-31fe-4154-9978-5798b0195d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115429736152916513300692769547263398145456276871064683704654045702156490197753 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.otp_ctrl_dai_errs.115429736152916513300692769547263398145456276871064683704654045702156490197753
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.3737706544861283187807903772194837903969349431441348365699990018924144199173
Short name T1081
Test name
Test status
Simulation time 614979183 ps
CPU time 10.28 seconds
Started Nov 22 01:50:49 PM PST 23
Finished Nov 22 01:51:00 PM PST 23
Peak memory 238836 kb
Host smart-ec5994d0-01eb-4b85-b78c-a7f2421035ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737706544861283187807903772194837903969349431441348365699990018924144199173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.otp_ctrl_dai_lock.3737706544861283187807903772194837903969349431441348365699990018924144199173
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.21960018156106489337407348955204883432369368296920788940821711448521622616402
Short name T1042
Test name
Test status
Simulation time 156689183 ps
CPU time 4.17 seconds
Started Nov 22 01:50:23 PM PST 23
Finished Nov 22 01:50:28 PM PST 23
Peak memory 238580 kb
Host smart-326e7940-3a93-4a24-80de-955e8542509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21960018156106489337407348955204883432369368296920788940821711448521622616402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.otp_ctrl_init_fail.21960018156106489337407348955204883432369368296920788940821711448521622616402
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.57239450625622107117177177651805536759026170691834037715762332427375063007714
Short name T332
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.1 seconds
Started Nov 22 01:50:58 PM PST 23
Finished Nov 22 01:51:18 PM PST 23
Peak memory 239024 kb
Host smart-eef8629b-41b2-498d-85ce-3e2c0a9af47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57239450625622107117177177651805536759026170691834037715762332427375063007714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.otp_ctrl_macro_errs.57239450625622107117177177651805536759026170691834037715762332427375063007714
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.69012589477217574170620553439588151029760891465137607780343689116033562318596
Short name T305
Test name
Test status
Simulation time 346349183 ps
CPU time 7.59 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 01:51:12 PM PST 23
Peak memory 238748 kb
Host smart-480ca44a-f2d5-4577-bd10-c8c355986819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69012589477217574170620553439588151029760891465137607780343689116033562318596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.otp_ctrl_parallel_key_req.69012589477217574170620553439588151029760891465137607780343689116033562318596
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.96432295268825036156012749676855524601621694728906036076901251400063037835530
Short name T248
Test name
Test status
Simulation time 176929183 ps
CPU time 4.39 seconds
Started Nov 22 01:50:30 PM PST 23
Finished Nov 22 01:50:35 PM PST 23
Peak memory 238704 kb
Host smart-a1a85eb2-1a1a-4dd4-b2ba-10f5be03ffb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96432295268825036156012749676855524601621694728906036076901251400063037835530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.96432295268825036156012749676855524601621694728906036076901251400063037835530
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.72894921988696986749000061933170455591906710884936145400136767083739768942644
Short name T38
Test name
Test status
Simulation time 486419183 ps
CPU time 12.43 seconds
Started Nov 22 01:50:31 PM PST 23
Finished Nov 22 01:50:44 PM PST 23
Peak memory 238720 kb
Host smart-211ffae4-1455-4520-ad16-83593db4433c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72894921988696986749000061933170455591906710884936145400136767083739768942644 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.72894921988696986749000061933170455591906710884936145400136767083739768942644
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.11361881771968105162718891808259607564059849963537734619934280666713850088662
Short name T889
Test name
Test status
Simulation time 137469183 ps
CPU time 3.74 seconds
Started Nov 22 01:51:16 PM PST 23
Finished Nov 22 01:51:21 PM PST 23
Peak memory 238700 kb
Host smart-56bbce34-360e-49bd-91fa-c7343561c460
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11361881771968105162718891808259607564059849963537734619934280666713850088662 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_regwen.11361881771968105162718891808259607564059849963537734619934280666713850088662
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.19903767496525157264600480415986663384000973338628839163924317158007552852024
Short name T957
Test name
Test status
Simulation time 138839183 ps
CPU time 2.96 seconds
Started Nov 22 01:50:51 PM PST 23
Finished Nov 22 01:50:55 PM PST 23
Peak memory 238796 kb
Host smart-d9fbf201-a073-4573-ba64-2ee6d29b3cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19903767496525157264600480415986663384000973338628839163924317158007552852024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.otp_ctrl_smoke.19903767496525157264600480415986663384000973338628839163924317158007552852024
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.39540568351172314485538183187759948185749366567943396607924319473903399354649
Short name T432
Test name
Test status
Simulation time 13240088340 ps
CPU time 127.57 seconds
Started Nov 22 01:51:05 PM PST 23
Finished Nov 22 01:53:15 PM PST 23
Peak memory 241748 kb
Host smart-7ec8899c-7304-4575-958b-7343fe8b75e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39540568351172314485538183187759948185749366567943396607924319473903399354649 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.39540568351172314485538183187759948185749366567943396607924319473903399354649
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.13401661063332871598495126702974054252174743730454977408203348743925500512940
Short name T664
Test name
Test status
Simulation time 150268849183 ps
CPU time 1952.65 seconds
Started Nov 22 01:51:17 PM PST 23
Finished Nov 22 02:23:52 PM PST 23
Peak memory 517592 kb
Host smart-38955250-cb16-497e-b6d3-303114ec9155
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340166106333287159849
5126702974054252174743730454977408203348743925500512940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_res
et.13401661063332871598495126702974054252174743730454977408203348743925500512940
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.14302519880724250894860685011318243573605326871464280698831619455010687878935
Short name T1309
Test name
Test status
Simulation time 549639183 ps
CPU time 8.64 seconds
Started Nov 22 01:51:16 PM PST 23
Finished Nov 22 01:51:26 PM PST 23
Peak memory 247020 kb
Host smart-d17cb343-c140-477f-89a8-b5390f2de994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14302519880724250894860685011318243573605326871464280698831619455010687878935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.otp_ctrl_test_access.14302519880724250894860685011318243573605326871464280698831619455010687878935
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.44357184312884604918928682870692920953881969272564100453630012202352355702697
Short name T491
Test name
Test status
Simulation time 156689183 ps
CPU time 3.93 seconds
Started Nov 22 01:52:29 PM PST 23
Finished Nov 22 01:52:38 PM PST 23
Peak memory 238648 kb
Host smart-67bc99d3-b7d2-4393-838c-10d7378d8902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44357184312884604918928682870692920953881969272564100453630012202352355702697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 150.otp_ctrl_init_fail.44357184312884604918928682870692920953881969272564100453630012202352355702697
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.6425368853553181050330263986264422144443794007269703204860770119296086537285
Short name T1099
Test name
Test status
Simulation time 176929183 ps
CPU time 4.44 seconds
Started Nov 22 01:52:18 PM PST 23
Finished Nov 22 01:52:26 PM PST 23
Peak memory 238680 kb
Host smart-61eefde4-0eec-47cd-a6be-a388bd90fde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6425368853553181050330263986264422144443794007269703204860770119296086537285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.6425368853553181050330263986264422144443794007269703204860770119296086537285
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.47948801703367794440851554500197191023588944338532707436246286596367424595998
Short name T255
Test name
Test status
Simulation time 156689183 ps
CPU time 3.94 seconds
Started Nov 22 01:52:08 PM PST 23
Finished Nov 22 01:52:15 PM PST 23
Peak memory 238592 kb
Host smart-33002316-2683-4929-8728-27042fabf4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47948801703367794440851554500197191023588944338532707436246286596367424595998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 151.otp_ctrl_init_fail.47948801703367794440851554500197191023588944338532707436246286596367424595998
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.51648705593983854039274846151839872625506030678329430653628406649054208548462
Short name T1058
Test name
Test status
Simulation time 176929183 ps
CPU time 4.02 seconds
Started Nov 22 01:52:41 PM PST 23
Finished Nov 22 01:52:50 PM PST 23
Peak memory 237456 kb
Host smart-7d6c1cd8-291f-49b6-9792-ed44401df316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51648705593983854039274846151839872625506030678329430653628406649054208548462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.51648705593983854039274846151839872625506030678329430653628406649054208548462
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.97491595369976272697633856698791209628183567148633797222090770383478075832355
Short name T464
Test name
Test status
Simulation time 156689183 ps
CPU time 4.24 seconds
Started Nov 22 01:52:10 PM PST 23
Finished Nov 22 01:52:17 PM PST 23
Peak memory 238608 kb
Host smart-f1405021-895d-4378-b8c9-a77041740bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97491595369976272697633856698791209628183567148633797222090770383478075832355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 152.otp_ctrl_init_fail.97491595369976272697633856698791209628183567148633797222090770383478075832355
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.112937971436099471617305524253062552534356160741925464003882797330142001795203
Short name T241
Test name
Test status
Simulation time 176929183 ps
CPU time 4.32 seconds
Started Nov 22 01:52:12 PM PST 23
Finished Nov 22 01:52:19 PM PST 23
Peak memory 238624 kb
Host smart-19556c2c-4add-4fd2-9b2b-2d73cab3a8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112937971436099471617305524253062552534356160741925464003882797330142001795203 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.112937971436099471617305524253062552534356160741925464003882797330142001795203
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.77418176476658439231113304404315849417640242129907422073138871354821836178409
Short name T781
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:52:07 PM PST 23
Finished Nov 22 01:52:15 PM PST 23
Peak memory 238736 kb
Host smart-e388ab6b-8b02-4065-8e7e-b77e969372ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77418176476658439231113304404315849417640242129907422073138871354821836178409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 153.otp_ctrl_init_fail.77418176476658439231113304404315849417640242129907422073138871354821836178409
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.77985585801039618970834950080321011921226531184952558733127959919349778207747
Short name T474
Test name
Test status
Simulation time 176929183 ps
CPU time 4.18 seconds
Started Nov 22 01:52:12 PM PST 23
Finished Nov 22 01:52:19 PM PST 23
Peak memory 238644 kb
Host smart-9c8794ba-f679-4a3b-b822-1a9e79dc3f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77985585801039618970834950080321011921226531184952558733127959919349778207747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.77985585801039618970834950080321011921226531184952558733127959919349778207747
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.83724253341635347282299147107705866208209651394955525358888321119388511008342
Short name T611
Test name
Test status
Simulation time 156689183 ps
CPU time 4.11 seconds
Started Nov 22 01:52:29 PM PST 23
Finished Nov 22 01:52:38 PM PST 23
Peak memory 238652 kb
Host smart-c2e1e634-a3a3-442f-9305-314e730a2100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83724253341635347282299147107705866208209651394955525358888321119388511008342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 154.otp_ctrl_init_fail.83724253341635347282299147107705866208209651394955525358888321119388511008342
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.20566525071848671301547255728447647110606884313718182159815037650038114504433
Short name T970
Test name
Test status
Simulation time 176929183 ps
CPU time 4.53 seconds
Started Nov 22 01:52:08 PM PST 23
Finished Nov 22 01:52:16 PM PST 23
Peak memory 238688 kb
Host smart-1c724b79-f5b5-4ed3-b819-1ea581e47d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20566525071848671301547255728447647110606884313718182159815037650038114504433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.20566525071848671301547255728447647110606884313718182159815037650038114504433
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.75347477137090893874604899599665388560958166694366951499842246177118163952668
Short name T922
Test name
Test status
Simulation time 156689183 ps
CPU time 4.08 seconds
Started Nov 22 01:52:05 PM PST 23
Finished Nov 22 01:52:13 PM PST 23
Peak memory 238612 kb
Host smart-60906adc-e4ff-4b0c-a134-90bfd9813558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75347477137090893874604899599665388560958166694366951499842246177118163952668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 155.otp_ctrl_init_fail.75347477137090893874604899599665388560958166694366951499842246177118163952668
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.32320325495889395445877894696687787725635540544432244531365873501898224713882
Short name T1021
Test name
Test status
Simulation time 176929183 ps
CPU time 4.37 seconds
Started Nov 22 01:52:22 PM PST 23
Finished Nov 22 01:52:28 PM PST 23
Peak memory 238708 kb
Host smart-4475c37e-46d7-41d2-9713-0a59149c3399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32320325495889395445877894696687787725635540544432244531365873501898224713882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.32320325495889395445877894696687787725635540544432244531365873501898224713882
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.62376304602345346931470748223743757458423536205539923801307316544745909141738
Short name T230
Test name
Test status
Simulation time 156689183 ps
CPU time 4.13 seconds
Started Nov 22 01:52:10 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238636 kb
Host smart-3e37ae1d-e355-47f4-bf7d-57b5cd66496b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62376304602345346931470748223743757458423536205539923801307316544745909141738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 156.otp_ctrl_init_fail.62376304602345346931470748223743757458423536205539923801307316544745909141738
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.113998079506905618708173687813924310875030485288462546779739092936114967385536
Short name T946
Test name
Test status
Simulation time 176929183 ps
CPU time 4.23 seconds
Started Nov 22 01:52:01 PM PST 23
Finished Nov 22 01:52:07 PM PST 23
Peak memory 238712 kb
Host smart-8a7875b6-abe3-4bed-8c26-ee8635a71699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113998079506905618708173687813924310875030485288462546779739092936114967385536 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.113998079506905618708173687813924310875030485288462546779739092936114967385536
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.80100149679162943984490797589599806304676916484164945636447740108202372252919
Short name T796
Test name
Test status
Simulation time 156689183 ps
CPU time 4.12 seconds
Started Nov 22 01:52:03 PM PST 23
Finished Nov 22 01:52:09 PM PST 23
Peak memory 238468 kb
Host smart-f3ccac36-5656-4dc5-b8e4-432cf4e96b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80100149679162943984490797589599806304676916484164945636447740108202372252919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 157.otp_ctrl_init_fail.80100149679162943984490797589599806304676916484164945636447740108202372252919
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.39393492490600994113193586342820798642868200408352588431436532248814295794501
Short name T1227
Test name
Test status
Simulation time 176929183 ps
CPU time 4.25 seconds
Started Nov 22 01:52:09 PM PST 23
Finished Nov 22 01:52:17 PM PST 23
Peak memory 238688 kb
Host smart-81c5cd3f-a4a2-4b71-b47e-a85c55b4339e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39393492490600994113193586342820798642868200408352588431436532248814295794501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.39393492490600994113193586342820798642868200408352588431436532248814295794501
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.102887009170696037842926574723296721516958066135442272211850946477200514055742
Short name T783
Test name
Test status
Simulation time 156689183 ps
CPU time 3.99 seconds
Started Nov 22 01:52:14 PM PST 23
Finished Nov 22 01:52:20 PM PST 23
Peak memory 238608 kb
Host smart-290a7e9a-7181-42ff-baaf-afd66cfe3931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102887009170696037842926574723296721516958066135442272211850946477200514055742 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 158.otp_ctrl_init_fail.102887009170696037842926574723296721516958066135442272211850946477200514055742
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.68299260218689979592624310979594264462428477643913498631570000216124275383492
Short name T582
Test name
Test status
Simulation time 176929183 ps
CPU time 4.35 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 01:52:23 PM PST 23
Peak memory 238676 kb
Host smart-75922e4a-d82a-44f2-915d-77b4f0507ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68299260218689979592624310979594264462428477643913498631570000216124275383492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.68299260218689979592624310979594264462428477643913498631570000216124275383492
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.112609988465569020216463365435189065260510220771917605720232066949272709944436
Short name T1065
Test name
Test status
Simulation time 156689183 ps
CPU time 3.81 seconds
Started Nov 22 01:52:10 PM PST 23
Finished Nov 22 01:52:17 PM PST 23
Peak memory 238652 kb
Host smart-7b518508-2a3c-4913-90e1-c721bd6cfdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112609988465569020216463365435189065260510220771917605720232066949272709944436 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 159.otp_ctrl_init_fail.112609988465569020216463365435189065260510220771917605720232066949272709944436
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.89215007024566666126952432661467453064393050964441570338775839021116208520642
Short name T1216
Test name
Test status
Simulation time 176929183 ps
CPU time 4.5 seconds
Started Nov 22 01:52:02 PM PST 23
Finished Nov 22 01:52:08 PM PST 23
Peak memory 238700 kb
Host smart-095986b6-31d3-4d2d-896b-c7a0fb88cd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89215007024566666126952432661467453064393050964441570338775839021116208520642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.89215007024566666126952432661467453064393050964441570338775839021116208520642
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.15970173909305477649768631391201937211762431016055291001371519262560963877858
Short name T1186
Test name
Test status
Simulation time 71069183 ps
CPU time 1.91 seconds
Started Nov 22 01:51:12 PM PST 23
Finished Nov 22 01:51:16 PM PST 23
Peak memory 238408 kb
Host smart-7322518b-9ecb-421b-9941-66f6cbe6bff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15970173909305477649768631391201937211762431016055291001371519262560963877858 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.15970173909305477649768631391201937211762431016055291001371519262560963877858
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.93844868659098023351315027206130917209214702963544678680905633878828692012991
Short name T726
Test name
Test status
Simulation time 111269183 ps
CPU time 2.67 seconds
Started Nov 22 01:51:15 PM PST 23
Finished Nov 22 01:51:19 PM PST 23
Peak memory 246824 kb
Host smart-beb4e17f-9327-429b-a509-43f94e11d518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93844868659098023351315027206130917209214702963544678680905633878828692012991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.otp_ctrl_check_fail.93844868659098023351315027206130917209214702963544678680905633878828692012991
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.548845894594687867317536012762355902235571461461392709041894338736690459026
Short name T485
Test name
Test status
Simulation time 390019183 ps
CPU time 11.04 seconds
Started Nov 22 01:51:32 PM PST 23
Finished Nov 22 01:51:45 PM PST 23
Peak memory 238632 kb
Host smart-c3be567d-a7c1-48f9-93c9-41d43932d058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548845894594687867317536012762355902235571461461392709041894338736690459026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_ba
se_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.otp_ctrl_dai_errs.548845894594687867317536012762355902235571461461392709041894338736690459026
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.9108137838941236326023719360902616107668144214714335056783523502594654634402
Short name T353
Test name
Test status
Simulation time 614979183 ps
CPU time 10.52 seconds
Started Nov 22 01:51:29 PM PST 23
Finished Nov 22 01:51:42 PM PST 23
Peak memory 238840 kb
Host smart-b1d10bbe-6caa-416a-a454-a6efed6e3795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9108137838941236326023719360902616107668144214714335056783523502594654634402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.otp_ctrl_dai_lock.9108137838941236326023719360902616107668144214714335056783523502594654634402
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.18844851016783449323019744981578173114330654664360769642100312480277929844752
Short name T61
Test name
Test status
Simulation time 156689183 ps
CPU time 3.91 seconds
Started Nov 22 01:51:19 PM PST 23
Finished Nov 22 01:51:25 PM PST 23
Peak memory 238652 kb
Host smart-e74c05c8-5b4a-40ee-99c0-0ec48a900673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18844851016783449323019744981578173114330654664360769642100312480277929844752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.otp_ctrl_init_fail.18844851016783449323019744981578173114330654664360769642100312480277929844752
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.89769692386392964869529884732653632984524713355063407445583928472037571498581
Short name T1139
Test name
Test status
Simulation time 1137629183 ps
CPU time 18.87 seconds
Started Nov 22 01:51:09 PM PST 23
Finished Nov 22 01:51:29 PM PST 23
Peak memory 238816 kb
Host smart-28875afd-145e-4bce-b690-aacf708c0adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89769692386392964869529884732653632984524713355063407445583928472037571498581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.otp_ctrl_macro_errs.89769692386392964869529884732653632984524713355063407445583928472037571498581
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.109898663359875384135759046737135811395238570878140591899111360729288630552543
Short name T359
Test name
Test status
Simulation time 346349183 ps
CPU time 7.42 seconds
Started Nov 22 01:51:12 PM PST 23
Finished Nov 22 01:51:22 PM PST 23
Peak memory 238724 kb
Host smart-91343b65-ff65-4ce0-9749-38a9e3bde47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109898663359875384135759046737135811395238570878140591899111360729288630552543 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.109898663359875384135759046737135811395238570878140591899111360729288630552543
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.55415489400958865221423874838185610361107830326901837479264409231754152929938
Short name T1179
Test name
Test status
Simulation time 176929183 ps
CPU time 4.24 seconds
Started Nov 22 01:51:33 PM PST 23
Finished Nov 22 01:51:41 PM PST 23
Peak memory 238492 kb
Host smart-a70d939e-e5dc-4f90-b060-0a364d8e5e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55415489400958865221423874838185610361107830326901837479264409231754152929938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.55415489400958865221423874838185610361107830326901837479264409231754152929938
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.101494934756876964185166497621408450355118656409058773112243321596286451979514
Short name T939
Test name
Test status
Simulation time 486419183 ps
CPU time 11.88 seconds
Started Nov 22 01:51:24 PM PST 23
Finished Nov 22 01:51:39 PM PST 23
Peak memory 238708 kb
Host smart-6e0895ae-d2d0-4465-8c17-abee7facd53c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=101494934756876964185166497621408450355118656409058773112243321596286451979514 -assert nopostproc +UVM_TE
STNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.101494934756876964185166497621408450355118656409058773112243321596286451979514
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.83213890240503871858801530387589670628918298189808946119274596083939787573725
Short name T1134
Test name
Test status
Simulation time 137469183 ps
CPU time 3.54 seconds
Started Nov 22 01:51:24 PM PST 23
Finished Nov 22 01:51:31 PM PST 23
Peak memory 238716 kb
Host smart-d63c0374-bfa7-41e9-8fd7-a2da3a92c3bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83213890240503871858801530387589670628918298189808946119274596083939787573725 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_regwen.83213890240503871858801530387589670628918298189808946119274596083939787573725
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.14234622869619231765109022094075212254130578936211468493470125590967209103493
Short name T524
Test name
Test status
Simulation time 138839183 ps
CPU time 3.06 seconds
Started Nov 22 01:51:06 PM PST 23
Finished Nov 22 01:51:11 PM PST 23
Peak memory 238724 kb
Host smart-8d97cd3f-5d04-4e43-9652-e5bd59dfb747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14234622869619231765109022094075212254130578936211468493470125590967209103493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.otp_ctrl_smoke.14234622869619231765109022094075212254130578936211468493470125590967209103493
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.81507626258113904370802275518992655453354539539239808107749373027837169354587
Short name T1255
Test name
Test status
Simulation time 13240088340 ps
CPU time 131.13 seconds
Started Nov 22 01:51:45 PM PST 23
Finished Nov 22 01:54:00 PM PST 23
Peak memory 241764 kb
Host smart-d9221a82-5f10-4c15-ac7d-4510f790ac2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81507626258113904370802275518992655453354539539239808107749373027837169354587 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.81507626258113904370802275518992655453354539539239808107749373027837169354587
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.109070362592408723183612525123073866833767400334077037928987888048470145927819
Short name T471
Test name
Test status
Simulation time 150268849183 ps
CPU time 1979.49 seconds
Started Nov 22 01:51:45 PM PST 23
Finished Nov 22 02:24:49 PM PST 23
Peak memory 517528 kb
Host smart-3bdea658-75d1-4c65-b0b0-019bcae7ae78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090703625924087231836
12525123073866833767400334077037928987888048470145927819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_re
set.109070362592408723183612525123073866833767400334077037928987888048470145927819
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.68559280580972277845880771892457165819665302046406389333408244482758411874900
Short name T761
Test name
Test status
Simulation time 549639183 ps
CPU time 8.9 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:34 PM PST 23
Peak memory 247028 kb
Host smart-61504fcd-ced7-429e-b4ce-956c62cc02f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68559280580972277845880771892457165819665302046406389333408244482758411874900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.otp_ctrl_test_access.68559280580972277845880771892457165819665302046406389333408244482758411874900
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.114936127984940373737382882786609130420382867924867328116118938629496454777234
Short name T1156
Test name
Test status
Simulation time 156689183 ps
CPU time 3.9 seconds
Started Nov 22 01:52:13 PM PST 23
Finished Nov 22 01:52:19 PM PST 23
Peak memory 238572 kb
Host smart-64cf9374-4bfc-482e-a234-6859fda1b629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114936127984940373737382882786609130420382867924867328116118938629496454777234 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 160.otp_ctrl_init_fail.114936127984940373737382882786609130420382867924867328116118938629496454777234
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.9293987935654052312207671730387288115845918511227953340706246639577838596963
Short name T990
Test name
Test status
Simulation time 176929183 ps
CPU time 4.4 seconds
Started Nov 22 01:52:00 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238684 kb
Host smart-d82f5f70-0b7a-4c69-aedc-43027b8c0b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9293987935654052312207671730387288115845918511227953340706246639577838596963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.9293987935654052312207671730387288115845918511227953340706246639577838596963
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.41638937401890054338054703327146220056753415813618462060855569222014011590002
Short name T448
Test name
Test status
Simulation time 156689183 ps
CPU time 3.98 seconds
Started Nov 22 01:52:27 PM PST 23
Finished Nov 22 01:52:38 PM PST 23
Peak memory 238612 kb
Host smart-a3ad876f-b9bd-49ed-8891-c1a0e7544972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41638937401890054338054703327146220056753415813618462060855569222014011590002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 161.otp_ctrl_init_fail.41638937401890054338054703327146220056753415813618462060855569222014011590002
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.70943190415078101327880759302471087245018598103161761340395834274723281414483
Short name T844
Test name
Test status
Simulation time 176929183 ps
CPU time 4.21 seconds
Started Nov 22 01:52:11 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238540 kb
Host smart-d24c8a45-a314-4d9d-b1ab-248c189d51ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70943190415078101327880759302471087245018598103161761340395834274723281414483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.70943190415078101327880759302471087245018598103161761340395834274723281414483
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.76547727743914440305323750164651769179134891493589365859968491204231785895532
Short name T296
Test name
Test status
Simulation time 156689183 ps
CPU time 3.85 seconds
Started Nov 22 01:52:11 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238588 kb
Host smart-2bfbe964-f939-4176-8f7d-c06354bea836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76547727743914440305323750164651769179134891493589365859968491204231785895532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 162.otp_ctrl_init_fail.76547727743914440305323750164651769179134891493589365859968491204231785895532
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.2265914938569356514619647171877949747055918592744455722980754113999399410256
Short name T1090
Test name
Test status
Simulation time 176929183 ps
CPU time 4.31 seconds
Started Nov 22 01:52:06 PM PST 23
Finished Nov 22 01:52:13 PM PST 23
Peak memory 238548 kb
Host smart-a0e12d35-b80a-4314-bb54-0612c51d1ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265914938569356514619647171877949747055918592744455722980754113999399410256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.2265914938569356514619647171877949747055918592744455722980754113999399410256
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.12788236163912833797034445627050665119592281286678645221879413010533027576706
Short name T242
Test name
Test status
Simulation time 156689183 ps
CPU time 4.08 seconds
Started Nov 22 01:52:05 PM PST 23
Finished Nov 22 01:52:12 PM PST 23
Peak memory 238468 kb
Host smart-8497d28b-cf9b-421a-8b28-42ec98262fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12788236163912833797034445627050665119592281286678645221879413010533027576706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 163.otp_ctrl_init_fail.12788236163912833797034445627050665119592281286678645221879413010533027576706
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.80941866007150674794317975885550233887313591968115072594147384848958023987388
Short name T880
Test name
Test status
Simulation time 176929183 ps
CPU time 4.3 seconds
Started Nov 22 01:52:03 PM PST 23
Finished Nov 22 01:52:08 PM PST 23
Peak memory 238708 kb
Host smart-908e4404-649e-41e8-99fc-ef44fc8b2f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80941866007150674794317975885550233887313591968115072594147384848958023987388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.80941866007150674794317975885550233887313591968115072594147384848958023987388
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.28991204761183130348713977108508732206378104608682112351892486731860225834501
Short name T312
Test name
Test status
Simulation time 156689183 ps
CPU time 3.97 seconds
Started Nov 22 01:52:48 PM PST 23
Finished Nov 22 01:52:56 PM PST 23
Peak memory 238584 kb
Host smart-577df2a8-358b-4249-b28c-aa955d6aef7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28991204761183130348713977108508732206378104608682112351892486731860225834501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 164.otp_ctrl_init_fail.28991204761183130348713977108508732206378104608682112351892486731860225834501
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.63502451367407098539984608067863634613618430820788842827240401901873519150484
Short name T335
Test name
Test status
Simulation time 176929183 ps
CPU time 4.33 seconds
Started Nov 22 01:52:17 PM PST 23
Finished Nov 22 01:52:26 PM PST 23
Peak memory 238680 kb
Host smart-7b175bb9-3306-4111-aaa2-f6bed65854ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63502451367407098539984608067863634613618430820788842827240401901873519150484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.63502451367407098539984608067863634613618430820788842827240401901873519150484
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.20252438531594606033363406434617786832891887825127771746371691278327935254865
Short name T319
Test name
Test status
Simulation time 156689183 ps
CPU time 4.11 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 01:52:21 PM PST 23
Peak memory 238468 kb
Host smart-04e63ed8-3703-423f-8154-062a8caf79b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20252438531594606033363406434617786832891887825127771746371691278327935254865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 165.otp_ctrl_init_fail.20252438531594606033363406434617786832891887825127771746371691278327935254865
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.98988677154418207006916950431913862458810420737684059555132193340586807738536
Short name T1256
Test name
Test status
Simulation time 176929183 ps
CPU time 4.28 seconds
Started Nov 22 01:52:00 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238700 kb
Host smart-955a1c9d-5841-42a9-af29-af428d55bf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98988677154418207006916950431913862458810420737684059555132193340586807738536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.98988677154418207006916950431913862458810420737684059555132193340586807738536
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.33695017500411875830524498269238415546247482392801673091476896998638049679594
Short name T1043
Test name
Test status
Simulation time 156689183 ps
CPU time 4.18 seconds
Started Nov 22 01:52:09 PM PST 23
Finished Nov 22 01:52:17 PM PST 23
Peak memory 238636 kb
Host smart-129f393c-fe24-49d8-a66e-7b535b19c70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33695017500411875830524498269238415546247482392801673091476896998638049679594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 166.otp_ctrl_init_fail.33695017500411875830524498269238415546247482392801673091476896998638049679594
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.58150383337360393262822977945603683452985635530457521759645405499003323848448
Short name T1110
Test name
Test status
Simulation time 176929183 ps
CPU time 4.22 seconds
Started Nov 22 01:52:14 PM PST 23
Finished Nov 22 01:52:21 PM PST 23
Peak memory 238700 kb
Host smart-36b38d96-4a4f-4bda-8600-b654b7d77c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58150383337360393262822977945603683452985635530457521759645405499003323848448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.58150383337360393262822977945603683452985635530457521759645405499003323848448
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.102205583690275991763248235441183350401842800032275484195487760603693569817491
Short name T907
Test name
Test status
Simulation time 156689183 ps
CPU time 3.95 seconds
Started Nov 22 01:52:20 PM PST 23
Finished Nov 22 01:52:27 PM PST 23
Peak memory 238552 kb
Host smart-72260670-4db0-4112-90e0-58390ffa1683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102205583690275991763248235441183350401842800032275484195487760603693569817491 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 167.otp_ctrl_init_fail.102205583690275991763248235441183350401842800032275484195487760603693569817491
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.41399592421026515298546613930024673676266005496779083804229625494227710814403
Short name T721
Test name
Test status
Simulation time 176929183 ps
CPU time 4.47 seconds
Started Nov 22 01:52:02 PM PST 23
Finished Nov 22 01:52:08 PM PST 23
Peak memory 238700 kb
Host smart-2747f9bc-c8ff-45df-b273-8de3a32aac28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41399592421026515298546613930024673676266005496779083804229625494227710814403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.41399592421026515298546613930024673676266005496779083804229625494227710814403
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.63912148892565474948246013468613591542532335637207621831750892908317531537053
Short name T530
Test name
Test status
Simulation time 156689183 ps
CPU time 3.95 seconds
Started Nov 22 01:52:06 PM PST 23
Finished Nov 22 01:52:13 PM PST 23
Peak memory 238608 kb
Host smart-3d5c9ad9-f00d-4448-a6d1-16325456521e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63912148892565474948246013468613591542532335637207621831750892908317531537053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 168.otp_ctrl_init_fail.63912148892565474948246013468613591542532335637207621831750892908317531537053
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.28536596249309683873589316044516363576120306762667892544165008566703045890063
Short name T1137
Test name
Test status
Simulation time 176929183 ps
CPU time 4.26 seconds
Started Nov 22 01:52:08 PM PST 23
Finished Nov 22 01:52:16 PM PST 23
Peak memory 238408 kb
Host smart-fd804720-ab12-481b-a3bc-2046798ee88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28536596249309683873589316044516363576120306762667892544165008566703045890063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.28536596249309683873589316044516363576120306762667892544165008566703045890063
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.76512574916140686527217598440818424544171031267008152847347513216260170760927
Short name T269
Test name
Test status
Simulation time 156689183 ps
CPU time 3.84 seconds
Started Nov 22 01:52:45 PM PST 23
Finished Nov 22 01:52:53 PM PST 23
Peak memory 238044 kb
Host smart-65457ac8-a353-409b-8fc1-d5e9301c4329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76512574916140686527217598440818424544171031267008152847347513216260170760927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 169.otp_ctrl_init_fail.76512574916140686527217598440818424544171031267008152847347513216260170760927
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.960272852590688276037950896540256611626237215547307217378692643857239701828
Short name T641
Test name
Test status
Simulation time 176929183 ps
CPU time 4.32 seconds
Started Nov 22 01:52:02 PM PST 23
Finished Nov 22 01:52:07 PM PST 23
Peak memory 238688 kb
Host smart-d53d0d3e-2c3c-42d3-8101-a210c875de7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960272852590688276037950896540256611626237215547307217378692643857239701828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_ba
se_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.960272852590688276037950896540256611626237215547307217378692643857239701828
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.13994565176389192957640082066411540253397598490278479379277045673850212265566
Short name T460
Test name
Test status
Simulation time 71069183 ps
CPU time 1.85 seconds
Started Nov 22 01:51:33 PM PST 23
Finished Nov 22 01:51:38 PM PST 23
Peak memory 238468 kb
Host smart-46d607f1-137f-4ad7-bbeb-3a488aa6c3b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13994565176389192957640082066411540253397598490278479379277045673850212265566 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.13994565176389192957640082066411540253397598490278479379277045673850212265566
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.25272697820678395008515027846370505488493933764122331392982572059692690407249
Short name T763
Test name
Test status
Simulation time 111269183 ps
CPU time 2.78 seconds
Started Nov 22 01:51:32 PM PST 23
Finished Nov 22 01:51:37 PM PST 23
Peak memory 246780 kb
Host smart-b6c0273b-3730-429c-9fad-e810eee158b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25272697820678395008515027846370505488493933764122331392982572059692690407249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.otp_ctrl_check_fail.25272697820678395008515027846370505488493933764122331392982572059692690407249
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.8884357291767555812085012435355096266177722595100810643680933543798759665372
Short name T243
Test name
Test status
Simulation time 390019183 ps
CPU time 10.49 seconds
Started Nov 22 01:51:27 PM PST 23
Finished Nov 22 01:51:40 PM PST 23
Peak memory 238552 kb
Host smart-1a02897a-4e46-4d6e-980a-8b2a9c908dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8884357291767555812085012435355096266177722595100810643680933543798759665372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.otp_ctrl_dai_errs.8884357291767555812085012435355096266177722595100810643680933543798759665372
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.18304078720444528944251527324874635754602719550364898804473217371568182321581
Short name T927
Test name
Test status
Simulation time 614979183 ps
CPU time 10.43 seconds
Started Nov 22 01:51:29 PM PST 23
Finished Nov 22 01:51:42 PM PST 23
Peak memory 238716 kb
Host smart-16aee1de-c90e-4ef8-93d8-53cb40ba5230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18304078720444528944251527324874635754602719550364898804473217371568182321581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.otp_ctrl_dai_lock.18304078720444528944251527324874635754602719550364898804473217371568182321581
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.106442459373479601917746725591711492722331506120363001773264399938451611451870
Short name T770
Test name
Test status
Simulation time 156689183 ps
CPU time 3.99 seconds
Started Nov 22 01:51:24 PM PST 23
Finished Nov 22 01:51:31 PM PST 23
Peak memory 238592 kb
Host smart-9ab111f6-dc98-4eb9-ba91-fb1bf6f36e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106442459373479601917746725591711492722331506120363001773264399938451611451870 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.otp_ctrl_init_fail.106442459373479601917746725591711492722331506120363001773264399938451611451870
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.86065570295574642757841384138409993216181065536021675841028920935106210541875
Short name T420
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.48 seconds
Started Nov 22 01:51:52 PM PST 23
Finished Nov 22 01:52:13 PM PST 23
Peak memory 239048 kb
Host smart-62566c55-782f-4fb5-af4b-660b067ba28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86065570295574642757841384138409993216181065536021675841028920935106210541875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.otp_ctrl_macro_errs.86065570295574642757841384138409993216181065536021675841028920935106210541875
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.84942755901949744881408588524927227068207717439010147412689691890814674896905
Short name T1234
Test name
Test status
Simulation time 346349183 ps
CPU time 7.26 seconds
Started Nov 22 01:51:35 PM PST 23
Finished Nov 22 01:51:46 PM PST 23
Peak memory 238732 kb
Host smart-ae590da3-810b-4d3e-8e76-b1f3139a7cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84942755901949744881408588524927227068207717439010147412689691890814674896905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.otp_ctrl_parallel_key_req.84942755901949744881408588524927227068207717439010147412689691890814674896905
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.89191791383552844219960354480950975330249934474800798867069331760936346895461
Short name T596
Test name
Test status
Simulation time 176929183 ps
CPU time 4.58 seconds
Started Nov 22 01:51:45 PM PST 23
Finished Nov 22 01:51:53 PM PST 23
Peak memory 238608 kb
Host smart-3de0c505-99e7-4bb8-b668-8d924271e7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89191791383552844219960354480950975330249934474800798867069331760936346895461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.89191791383552844219960354480950975330249934474800798867069331760936346895461
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.107948941052710997814101430899614063370864924241180619690042182633406320849386
Short name T974
Test name
Test status
Simulation time 486419183 ps
CPU time 12.85 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:37 PM PST 23
Peak memory 238592 kb
Host smart-d71793a3-8a0d-49ef-abbd-63a9cebe06bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107948941052710997814101430899614063370864924241180619690042182633406320849386 -assert nopostproc +UVM_TE
STNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.107948941052710997814101430899614063370864924241180619690042182633406320849386
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.84008629214318229869071123068109467632728136386312526744645399670625948464335
Short name T355
Test name
Test status
Simulation time 137469183 ps
CPU time 3.79 seconds
Started Nov 22 01:51:23 PM PST 23
Finished Nov 22 01:51:29 PM PST 23
Peak memory 238660 kb
Host smart-cccf6ead-081e-4aad-85a8-595399924ffa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84008629214318229869071123068109467632728136386312526744645399670625948464335 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_regwen.84008629214318229869071123068109467632728136386312526744645399670625948464335
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.109535449416007343877285597150921888734494158468285628958451174264651978074808
Short name T1242
Test name
Test status
Simulation time 138839183 ps
CPU time 3.13 seconds
Started Nov 22 01:51:34 PM PST 23
Finished Nov 22 01:51:41 PM PST 23
Peak memory 238812 kb
Host smart-7e7a16c7-24a7-4282-8b07-0587d0f0153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109535449416007343877285597150921888734494158468285628958451174264651978074808 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.otp_ctrl_smoke.109535449416007343877285597150921888734494158468285628958451174264651978074808
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.69477153327480655294675769761602156569218424300035132184289825914211374501964
Short name T1310
Test name
Test status
Simulation time 13240088340 ps
CPU time 129.17 seconds
Started Nov 22 01:51:37 PM PST 23
Finished Nov 22 01:53:51 PM PST 23
Peak memory 241804 kb
Host smart-0774a88a-536f-4bdd-a55e-afd3bc3b1560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69477153327480655294675769761602156569218424300035132184289825914211374501964 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.69477153327480655294675769761602156569218424300035132184289825914211374501964
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.33162418900298235407887159176813098345606269694590673451143628207226649021246
Short name T574
Test name
Test status
Simulation time 150268849183 ps
CPU time 1949.7 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 02:23:53 PM PST 23
Peak memory 517592 kb
Host smart-816585da-3b42-4ada-9ebb-ac712842116b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316241890029823540788
7159176813098345606269694590673451143628207226649021246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_res
et.33162418900298235407887159176813098345606269694590673451143628207226649021246
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.58862920430882143649407355116357873372021873885546536428104100195218334779996
Short name T1209
Test name
Test status
Simulation time 549639183 ps
CPU time 8.62 seconds
Started Nov 22 01:51:39 PM PST 23
Finished Nov 22 01:51:53 PM PST 23
Peak memory 246852 kb
Host smart-313af41e-abe9-4561-9798-1dd3948660b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58862920430882143649407355116357873372021873885546536428104100195218334779996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.otp_ctrl_test_access.58862920430882143649407355116357873372021873885546536428104100195218334779996
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.103279892043767424752994396016975735553008327354894618232329682887397459528686
Short name T258
Test name
Test status
Simulation time 156689183 ps
CPU time 4.04 seconds
Started Nov 22 01:52:04 PM PST 23
Finished Nov 22 01:52:11 PM PST 23
Peak memory 238624 kb
Host smart-85024f2a-7258-406f-9b9e-6d659f58edec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103279892043767424752994396016975735553008327354894618232329682887397459528686 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 170.otp_ctrl_init_fail.103279892043767424752994396016975735553008327354894618232329682887397459528686
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.76750400704799114011236178313143338780307314785522224483383084519136404016516
Short name T635
Test name
Test status
Simulation time 176929183 ps
CPU time 4.22 seconds
Started Nov 22 01:52:12 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238676 kb
Host smart-be669754-7501-4aaf-b174-304f883606ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76750400704799114011236178313143338780307314785522224483383084519136404016516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.76750400704799114011236178313143338780307314785522224483383084519136404016516
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.2295488537783893926378696800169796908746524550476689799177919551377637056020
Short name T479
Test name
Test status
Simulation time 156689183 ps
CPU time 4.19 seconds
Started Nov 22 01:52:04 PM PST 23
Finished Nov 22 01:52:12 PM PST 23
Peak memory 238620 kb
Host smart-48caa203-51a2-4b08-9ca4-4cbec72c26c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295488537783893926378696800169796908746524550476689799177919551377637056020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 171.otp_ctrl_init_fail.2295488537783893926378696800169796908746524550476689799177919551377637056020
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.83420150059464078654553875182938531055048833444538626799120048378740194315815
Short name T520
Test name
Test status
Simulation time 176929183 ps
CPU time 4.28 seconds
Started Nov 22 01:52:17 PM PST 23
Finished Nov 22 01:52:25 PM PST 23
Peak memory 238604 kb
Host smart-b7fd128b-ad70-4919-ae09-99dfd4cadb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83420150059464078654553875182938531055048833444538626799120048378740194315815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.83420150059464078654553875182938531055048833444538626799120048378740194315815
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.85671911108703006600809464804089194476265992700175369589399697322908394465319
Short name T720
Test name
Test status
Simulation time 156689183 ps
CPU time 3.94 seconds
Started Nov 22 01:52:06 PM PST 23
Finished Nov 22 01:52:13 PM PST 23
Peak memory 238616 kb
Host smart-97ba56f2-8228-42ef-be60-236f48d60fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85671911108703006600809464804089194476265992700175369589399697322908394465319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 172.otp_ctrl_init_fail.85671911108703006600809464804089194476265992700175369589399697322908394465319
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.13427495008746837771007724597704030653620177562739252950401394122547234185826
Short name T921
Test name
Test status
Simulation time 176929183 ps
CPU time 4.48 seconds
Started Nov 22 01:52:24 PM PST 23
Finished Nov 22 01:52:31 PM PST 23
Peak memory 238640 kb
Host smart-b0e51bba-5c51-4ea7-8392-0ab0c3da5ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13427495008746837771007724597704030653620177562739252950401394122547234185826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.13427495008746837771007724597704030653620177562739252950401394122547234185826
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.60556402957892477616593685335945583592833752939314628476231693570102304271446
Short name T74
Test name
Test status
Simulation time 156689183 ps
CPU time 4.18 seconds
Started Nov 22 01:52:00 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238652 kb
Host smart-41af5bdf-d4df-4266-9fe2-868901280f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60556402957892477616593685335945583592833752939314628476231693570102304271446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 173.otp_ctrl_init_fail.60556402957892477616593685335945583592833752939314628476231693570102304271446
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.17714390087290040775708151782616849055428361222148107781649995506447519279082
Short name T1246
Test name
Test status
Simulation time 176929183 ps
CPU time 4.42 seconds
Started Nov 22 01:52:03 PM PST 23
Finished Nov 22 01:52:10 PM PST 23
Peak memory 238688 kb
Host smart-59bf585b-028a-47f0-bc01-9b5518355143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17714390087290040775708151782616849055428361222148107781649995506447519279082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.17714390087290040775708151782616849055428361222148107781649995506447519279082
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.39008923529764774106914352519652358758805541044002475599922260911779448707710
Short name T314
Test name
Test status
Simulation time 156689183 ps
CPU time 4.13 seconds
Started Nov 22 01:52:07 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238620 kb
Host smart-fba4d7e9-107e-40c5-923e-aa1cdb78bd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39008923529764774106914352519652358758805541044002475599922260911779448707710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 174.otp_ctrl_init_fail.39008923529764774106914352519652358758805541044002475599922260911779448707710
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.58972896570821728708446706029296720513861851220518737388764040912727715085844
Short name T1249
Test name
Test status
Simulation time 176929183 ps
CPU time 4.3 seconds
Started Nov 22 01:52:22 PM PST 23
Finished Nov 22 01:52:28 PM PST 23
Peak memory 238680 kb
Host smart-2b08968e-7055-421c-808d-873a6899a223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58972896570821728708446706029296720513861851220518737388764040912727715085844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.58972896570821728708446706029296720513861851220518737388764040912727715085844
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.38096451260878358731103088363988235058537125691880665449837720822139369950964
Short name T672
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:52:02 PM PST 23
Finished Nov 22 01:52:07 PM PST 23
Peak memory 238564 kb
Host smart-47485702-4ddf-4c20-8d79-fdd1b8ca03a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38096451260878358731103088363988235058537125691880665449837720822139369950964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 175.otp_ctrl_init_fail.38096451260878358731103088363988235058537125691880665449837720822139369950964
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.22867171000570360480026525975953756625143824150889314711414058522469577270840
Short name T1240
Test name
Test status
Simulation time 176929183 ps
CPU time 4.24 seconds
Started Nov 22 01:52:04 PM PST 23
Finished Nov 22 01:52:11 PM PST 23
Peak memory 238688 kb
Host smart-9527cb00-2f20-45a1-8d15-82ef343ec2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22867171000570360480026525975953756625143824150889314711414058522469577270840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.22867171000570360480026525975953756625143824150889314711414058522469577270840
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.33654092123435638730377910596124192507628301926658876196544458738362428016694
Short name T823
Test name
Test status
Simulation time 156689183 ps
CPU time 3.99 seconds
Started Nov 22 01:52:28 PM PST 23
Finished Nov 22 01:52:38 PM PST 23
Peak memory 238632 kb
Host smart-04da34f0-f08c-4f86-a33d-cc50b184bae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33654092123435638730377910596124192507628301926658876196544458738362428016694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 176.otp_ctrl_init_fail.33654092123435638730377910596124192507628301926658876196544458738362428016694
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.52374521682701702209226347326851604482815028315381111741709449830436332652403
Short name T831
Test name
Test status
Simulation time 176929183 ps
CPU time 4.44 seconds
Started Nov 22 01:52:00 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238688 kb
Host smart-3d095077-96d8-4174-bd2b-32081e04cd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52374521682701702209226347326851604482815028315381111741709449830436332652403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.52374521682701702209226347326851604482815028315381111741709449830436332652403
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.101930096045658601681765144134938958359963511744475312227486505381872517671487
Short name T666
Test name
Test status
Simulation time 156689183 ps
CPU time 3.9 seconds
Started Nov 22 01:52:06 PM PST 23
Finished Nov 22 01:52:13 PM PST 23
Peak memory 238604 kb
Host smart-c285d7d3-4a70-41b6-95de-98f6b1fd2f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101930096045658601681765144134938958359963511744475312227486505381872517671487 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 177.otp_ctrl_init_fail.101930096045658601681765144134938958359963511744475312227486505381872517671487
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.98316424043828663949273615516103037021214937192702784470176083038385339376315
Short name T78
Test name
Test status
Simulation time 176929183 ps
CPU time 4.3 seconds
Started Nov 22 01:52:23 PM PST 23
Finished Nov 22 01:52:38 PM PST 23
Peak memory 238624 kb
Host smart-798ff3ca-cda1-44a9-b578-ed9dc1eeb854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98316424043828663949273615516103037021214937192702784470176083038385339376315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.98316424043828663949273615516103037021214937192702784470176083038385339376315
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.111038001584364778667546003122718287512774040611776498950293562294995657477380
Short name T1273
Test name
Test status
Simulation time 156689183 ps
CPU time 4.09 seconds
Started Nov 22 01:52:07 PM PST 23
Finished Nov 22 01:52:14 PM PST 23
Peak memory 238052 kb
Host smart-80751fdc-134b-4b49-b7c7-c2d24abde11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111038001584364778667546003122718287512774040611776498950293562294995657477380 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 178.otp_ctrl_init_fail.111038001584364778667546003122718287512774040611776498950293562294995657477380
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.47811308183606974607571127879127167750801271206641227876169492504834319107326
Short name T368
Test name
Test status
Simulation time 176929183 ps
CPU time 4.26 seconds
Started Nov 22 01:52:08 PM PST 23
Finished Nov 22 01:52:16 PM PST 23
Peak memory 238680 kb
Host smart-53d2fa38-ae79-4bb0-bf78-6919cde00cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47811308183606974607571127879127167750801271206641227876169492504834319107326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.47811308183606974607571127879127167750801271206641227876169492504834319107326
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.106204198211857152219703433360262223945274504128716742226779566138044347324077
Short name T810
Test name
Test status
Simulation time 156689183 ps
CPU time 4.09 seconds
Started Nov 22 01:51:58 PM PST 23
Finished Nov 22 01:52:03 PM PST 23
Peak memory 238644 kb
Host smart-f7c34509-469a-46c0-9bd1-ab5808855428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106204198211857152219703433360262223945274504128716742226779566138044347324077 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 179.otp_ctrl_init_fail.106204198211857152219703433360262223945274504128716742226779566138044347324077
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.54782049795667780464184440471054777129168533174002062547197243180719086812382
Short name T749
Test name
Test status
Simulation time 176929183 ps
CPU time 4.3 seconds
Started Nov 22 01:52:03 PM PST 23
Finished Nov 22 01:52:10 PM PST 23
Peak memory 238696 kb
Host smart-93bdf307-5337-48eb-8f7b-4840910c7ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54782049795667780464184440471054777129168533174002062547197243180719086812382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.54782049795667780464184440471054777129168533174002062547197243180719086812382
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.99429407957837038458549845945416820279993197588637874986925699072718386995967
Short name T1304
Test name
Test status
Simulation time 71069183 ps
CPU time 1.86 seconds
Started Nov 22 01:50:43 PM PST 23
Finished Nov 22 01:50:46 PM PST 23
Peak memory 238292 kb
Host smart-af4f8548-cace-4721-a354-c4a4583a1b38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99429407957837038458549845945416820279993197588637874986925699072718386995967 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.99429407957837038458549845945416820279993197588637874986925699072718386995967
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.68410290586771746545658267417733712298745319545831141856148105013647972289629
Short name T752
Test name
Test status
Simulation time 111269183 ps
CPU time 2.89 seconds
Started Nov 22 01:50:25 PM PST 23
Finished Nov 22 01:50:29 PM PST 23
Peak memory 246844 kb
Host smart-337064f7-ef72-4a2f-9a3c-7d908f442d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68410290586771746545658267417733712298745319545831141856148105013647972289629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.otp_ctrl_check_fail.68410290586771746545658267417733712298745319545831141856148105013647972289629
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.112147531146499517240674880265605370733347375497134465804602164471772524851342
Short name T537
Test name
Test status
Simulation time 390019183 ps
CPU time 11.27 seconds
Started Nov 22 01:50:28 PM PST 23
Finished Nov 22 01:50:40 PM PST 23
Peak memory 238472 kb
Host smart-c3274584-fcae-4515-9686-6a40dc85856b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112147531146499517240674880265605370733347375497134465804602164471772524851342 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.otp_ctrl_dai_errs.112147531146499517240674880265605370733347375497134465804602164471772524851342
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.52998429628638541699273801327159791289287022452869237485090456301759747326131
Short name T568
Test name
Test status
Simulation time 614979183 ps
CPU time 10.49 seconds
Started Nov 22 01:50:47 PM PST 23
Finished Nov 22 01:50:58 PM PST 23
Peak memory 238836 kb
Host smart-9ecb3282-2cca-4360-956e-9696dbf1e7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52998429628638541699273801327159791289287022452869237485090456301759747326131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.otp_ctrl_dai_lock.52998429628638541699273801327159791289287022452869237485090456301759747326131
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.50904638032064253388591755912798755906258388687319375049573960327737129693139
Short name T352
Test name
Test status
Simulation time 156689183 ps
CPU time 3.88 seconds
Started Nov 22 01:51:38 PM PST 23
Finished Nov 22 01:51:47 PM PST 23
Peak memory 238540 kb
Host smart-a4120120-2abb-423c-b377-90923514b5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50904638032064253388591755912798755906258388687319375049573960327737129693139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.otp_ctrl_init_fail.50904638032064253388591755912798755906258388687319375049573960327737129693139
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.56648893164671979505302539373035762246226988415147277413878644892221970847657
Short name T700
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.72 seconds
Started Nov 22 01:50:51 PM PST 23
Finished Nov 22 01:51:12 PM PST 23
Peak memory 238968 kb
Host smart-03ae16a7-b18e-4be0-ba73-94c84faac099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56648893164671979505302539373035762246226988415147277413878644892221970847657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.otp_ctrl_macro_errs.56648893164671979505302539373035762246226988415147277413878644892221970847657
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.8967784029800682683998727343290961138546664409013210136403813015460548966069
Short name T653
Test name
Test status
Simulation time 346349183 ps
CPU time 7.3 seconds
Started Nov 22 01:50:51 PM PST 23
Finished Nov 22 01:50:59 PM PST 23
Peak memory 238620 kb
Host smart-4987ed28-5037-4278-aab7-8756fe322e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8967784029800682683998727343290961138546664409013210136403813015460548966069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 18.otp_ctrl_parallel_key_req.8967784029800682683998727343290961138546664409013210136403813015460548966069
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.6033534626963592262563351671132831099231262181753391734247495870214296820191
Short name T417
Test name
Test status
Simulation time 176929183 ps
CPU time 4.15 seconds
Started Nov 22 01:51:56 PM PST 23
Finished Nov 22 01:52:01 PM PST 23
Peak memory 238460 kb
Host smart-dd23b308-80e6-43d6-ad1b-74ddecf11560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6033534626963592262563351671132831099231262181753391734247495870214296820191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.6033534626963592262563351671132831099231262181753391734247495870214296820191
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.48005839641339491897595652116371023231766989620965043400494877896011096062434
Short name T1030
Test name
Test status
Simulation time 486419183 ps
CPU time 11.93 seconds
Started Nov 22 01:51:39 PM PST 23
Finished Nov 22 01:51:56 PM PST 23
Peak memory 238668 kb
Host smart-0b8d87e6-3de3-4cb9-afd5-f1e3847755e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48005839641339491897595652116371023231766989620965043400494877896011096062434 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.48005839641339491897595652116371023231766989620965043400494877896011096062434
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.89844006647484645057255761029241061838384419379475511393948784969430249489310
Short name T890
Test name
Test status
Simulation time 137469183 ps
CPU time 3.53 seconds
Started Nov 22 01:50:21 PM PST 23
Finished Nov 22 01:50:26 PM PST 23
Peak memory 238708 kb
Host smart-a7ab5e37-3f3a-4e9e-a985-91ef858ff74a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89844006647484645057255761029241061838384419379475511393948784969430249489310 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_regwen.89844006647484645057255761029241061838384419379475511393948784969430249489310
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.25383688771284252949514447962077193287322571184881074711552685847269272008399
Short name T1235
Test name
Test status
Simulation time 138839183 ps
CPU time 3.1 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:27 PM PST 23
Peak memory 238920 kb
Host smart-2d6c49be-ac01-4fb7-a836-23af644b08a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25383688771284252949514447962077193287322571184881074711552685847269272008399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.otp_ctrl_smoke.25383688771284252949514447962077193287322571184881074711552685847269272008399
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.13679160770067911220047543802103651252259372127280159446472707175319564837139
Short name T684
Test name
Test status
Simulation time 13240088340 ps
CPU time 133.43 seconds
Started Nov 22 01:50:31 PM PST 23
Finished Nov 22 01:52:45 PM PST 23
Peak memory 241792 kb
Host smart-88cf8531-7dca-44f5-9405-ca17069e3dc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13679160770067911220047543802103651252259372127280159446472707175319564837139 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.13679160770067911220047543802103651252259372127280159446472707175319564837139
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.80677572462345361810297823965711685742488423129086483152048537697142084037241
Short name T1020
Test name
Test status
Simulation time 150268849183 ps
CPU time 1951.73 seconds
Started Nov 22 01:50:13 PM PST 23
Finished Nov 22 02:22:50 PM PST 23
Peak memory 517592 kb
Host smart-17f1065d-982d-4fd2-a4cb-69ff88bd3e54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8067757246234536181029
7823965711685742488423129086483152048537697142084037241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_res
et.80677572462345361810297823965711685742488423129086483152048537697142084037241
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.81543145730311120149903821941417652283228284241049827955906432827904146829772
Short name T714
Test name
Test status
Simulation time 549639183 ps
CPU time 9.28 seconds
Started Nov 22 01:50:28 PM PST 23
Finished Nov 22 01:50:39 PM PST 23
Peak memory 246988 kb
Host smart-466aa67a-2592-4cb2-89b5-7c273899683b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81543145730311120149903821941417652283228284241049827955906432827904146829772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.otp_ctrl_test_access.81543145730311120149903821941417652283228284241049827955906432827904146829772
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.28934092524104439956615616533895040493515384055765865072895710546412455877146
Short name T1098
Test name
Test status
Simulation time 156689183 ps
CPU time 4.05 seconds
Started Nov 22 01:52:34 PM PST 23
Finished Nov 22 01:52:43 PM PST 23
Peak memory 238608 kb
Host smart-a0381bf5-90ea-482f-b26d-542f920aa6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28934092524104439956615616533895040493515384055765865072895710546412455877146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 180.otp_ctrl_init_fail.28934092524104439956615616533895040493515384055765865072895710546412455877146
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.16492765288133510851253791405231180194143703182229700562452666076463185463872
Short name T683
Test name
Test status
Simulation time 176929183 ps
CPU time 4.32 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 01:52:21 PM PST 23
Peak memory 238688 kb
Host smart-15341e70-bf97-4317-82b4-a6528bdeff3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16492765288133510851253791405231180194143703182229700562452666076463185463872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.16492765288133510851253791405231180194143703182229700562452666076463185463872
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.90121085209723198887736075251951289265111053153262055658749021437872497733047
Short name T864
Test name
Test status
Simulation time 156689183 ps
CPU time 3.92 seconds
Started Nov 22 01:52:12 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238556 kb
Host smart-eb0aab9e-e544-452d-94c8-7f904229bea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90121085209723198887736075251951289265111053153262055658749021437872497733047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 181.otp_ctrl_init_fail.90121085209723198887736075251951289265111053153262055658749021437872497733047
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.46791756132099262353008929248138863747340685481242216175966705212834711969046
Short name T1087
Test name
Test status
Simulation time 176929183 ps
CPU time 4.4 seconds
Started Nov 22 01:52:02 PM PST 23
Finished Nov 22 01:52:08 PM PST 23
Peak memory 238784 kb
Host smart-225fb79b-e45d-4825-8acb-db828959c8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46791756132099262353008929248138863747340685481242216175966705212834711969046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.46791756132099262353008929248138863747340685481242216175966705212834711969046
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.75395970553528124202134020150577188335692369599496291380277898245064571064125
Short name T1203
Test name
Test status
Simulation time 156689183 ps
CPU time 3.75 seconds
Started Nov 22 01:52:13 PM PST 23
Finished Nov 22 01:52:19 PM PST 23
Peak memory 238632 kb
Host smart-a11ad936-5ed3-471e-94df-ad2012f50ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75395970553528124202134020150577188335692369599496291380277898245064571064125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 182.otp_ctrl_init_fail.75395970553528124202134020150577188335692369599496291380277898245064571064125
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.6044261618283358518302042551334736826404552637639455879945540043306654055646
Short name T1107
Test name
Test status
Simulation time 176929183 ps
CPU time 4.22 seconds
Started Nov 22 01:52:03 PM PST 23
Finished Nov 22 01:52:08 PM PST 23
Peak memory 238700 kb
Host smart-d4e803a7-478f-4765-9a83-3784068d8248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6044261618283358518302042551334736826404552637639455879945540043306654055646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.6044261618283358518302042551334736826404552637639455879945540043306654055646
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.94307899709093975023191270612252951140481267128421347748103731952054276857908
Short name T933
Test name
Test status
Simulation time 156689183 ps
CPU time 3.84 seconds
Started Nov 22 01:52:12 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238652 kb
Host smart-ed0543bf-a08a-4261-9792-8621e10a1727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94307899709093975023191270612252951140481267128421347748103731952054276857908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 183.otp_ctrl_init_fail.94307899709093975023191270612252951140481267128421347748103731952054276857908
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.72584241315220833087649951431362575071461441136538230656141583196070432194737
Short name T617
Test name
Test status
Simulation time 176929183 ps
CPU time 4.32 seconds
Started Nov 22 01:52:13 PM PST 23
Finished Nov 22 01:52:20 PM PST 23
Peak memory 238588 kb
Host smart-8fc4eb14-bf08-41e4-8b26-5712ed200605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72584241315220833087649951431362575071461441136538230656141583196070432194737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.72584241315220833087649951431362575071461441136538230656141583196070432194737
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.46747931718262063766898295051241588457433089241550962256062210729660640346779
Short name T1151
Test name
Test status
Simulation time 156689183 ps
CPU time 4.07 seconds
Started Nov 22 01:52:03 PM PST 23
Finished Nov 22 01:52:09 PM PST 23
Peak memory 238608 kb
Host smart-22376011-8738-4f25-b29b-32244641b8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46747931718262063766898295051241588457433089241550962256062210729660640346779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 184.otp_ctrl_init_fail.46747931718262063766898295051241588457433089241550962256062210729660640346779
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.38606788086065183221528995194657875558166867176061298554979796273730518300300
Short name T932
Test name
Test status
Simulation time 176929183 ps
CPU time 4.38 seconds
Started Nov 22 01:52:16 PM PST 23
Finished Nov 22 01:52:25 PM PST 23
Peak memory 238676 kb
Host smart-4ee55182-d291-4a84-a04a-791fb0a274b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38606788086065183221528995194657875558166867176061298554979796273730518300300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.38606788086065183221528995194657875558166867176061298554979796273730518300300
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.80635718202130428709562320955980122684613530790056164033967182234762517688656
Short name T534
Test name
Test status
Simulation time 156689183 ps
CPU time 3.95 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 01:52:23 PM PST 23
Peak memory 238660 kb
Host smart-dc682779-455a-44f2-98f1-a7f819630092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80635718202130428709562320955980122684613530790056164033967182234762517688656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 185.otp_ctrl_init_fail.80635718202130428709562320955980122684613530790056164033967182234762517688656
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.14491149665994501266420137157039867178711693005969980422607291308777560980428
Short name T533
Test name
Test status
Simulation time 176929183 ps
CPU time 4.41 seconds
Started Nov 22 01:52:10 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238588 kb
Host smart-1832e14a-f9bf-4315-b845-aa01df939be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14491149665994501266420137157039867178711693005969980422607291308777560980428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.14491149665994501266420137157039867178711693005969980422607291308777560980428
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.22360170787403734719346767557265688766949954430773418722073691980374428590529
Short name T505
Test name
Test status
Simulation time 156689183 ps
CPU time 3.81 seconds
Started Nov 22 01:52:11 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238652 kb
Host smart-2ccc7258-61c1-4914-a7f5-e18253224444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22360170787403734719346767557265688766949954430773418722073691980374428590529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 186.otp_ctrl_init_fail.22360170787403734719346767557265688766949954430773418722073691980374428590529
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.46957144931687070626482285563452630068948914333059871544709670762750249880467
Short name T1184
Test name
Test status
Simulation time 176929183 ps
CPU time 4.27 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 01:52:23 PM PST 23
Peak memory 238696 kb
Host smart-1914bd9a-95fa-40a1-acf8-288543144d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46957144931687070626482285563452630068948914333059871544709670762750249880467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.46957144931687070626482285563452630068948914333059871544709670762750249880467
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.54098675084756126347105700108892809891687708429474736128097610771720070210808
Short name T59
Test name
Test status
Simulation time 156689183 ps
CPU time 4.01 seconds
Started Nov 22 01:52:23 PM PST 23
Finished Nov 22 01:52:30 PM PST 23
Peak memory 238588 kb
Host smart-974f0af0-dd3d-40a7-a4fd-9f6ab8e680af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54098675084756126347105700108892809891687708429474736128097610771720070210808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 187.otp_ctrl_init_fail.54098675084756126347105700108892809891687708429474736128097610771720070210808
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.61065900718463464907033058752882287245752873127068238682892638778760389242062
Short name T1171
Test name
Test status
Simulation time 176929183 ps
CPU time 4.26 seconds
Started Nov 22 01:52:32 PM PST 23
Finished Nov 22 01:52:39 PM PST 23
Peak memory 238588 kb
Host smart-f5f79913-9cb1-498c-8162-d27933fbfe40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61065900718463464907033058752882287245752873127068238682892638778760389242062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.61065900718463464907033058752882287245752873127068238682892638778760389242062
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.45738465515419924698219667799605292690072723412594053966087690579756619535771
Short name T281
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:52:07 PM PST 23
Finished Nov 22 01:52:14 PM PST 23
Peak memory 238532 kb
Host smart-975e3527-fcb0-48d0-8d13-b4c9b60b9297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45738465515419924698219667799605292690072723412594053966087690579756619535771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 188.otp_ctrl_init_fail.45738465515419924698219667799605292690072723412594053966087690579756619535771
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.79520697431313686492586147707006079840948409435315008733712378597526998230209
Short name T509
Test name
Test status
Simulation time 176929183 ps
CPU time 4.34 seconds
Started Nov 22 01:52:09 PM PST 23
Finished Nov 22 01:52:17 PM PST 23
Peak memory 238616 kb
Host smart-58479920-0cd9-42ee-a3e1-f033d9964325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79520697431313686492586147707006079840948409435315008733712378597526998230209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.79520697431313686492586147707006079840948409435315008733712378597526998230209
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.39963803892107187222391581775328813687665763635154149137659117044672935083886
Short name T75
Test name
Test status
Simulation time 156689183 ps
CPU time 4.11 seconds
Started Nov 22 01:52:14 PM PST 23
Finished Nov 22 01:52:21 PM PST 23
Peak memory 238648 kb
Host smart-71ccad6f-5951-4e2e-85d7-3120e756d6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39963803892107187222391581775328813687665763635154149137659117044672935083886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 189.otp_ctrl_init_fail.39963803892107187222391581775328813687665763635154149137659117044672935083886
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.69829138796893607742012644183405000929417637871614827626609958003218510835221
Short name T994
Test name
Test status
Simulation time 176929183 ps
CPU time 4.37 seconds
Started Nov 22 01:52:10 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238616 kb
Host smart-5111b664-05bb-4952-8437-b72a45d46664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69829138796893607742012644183405000929417637871614827626609958003218510835221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.69829138796893607742012644183405000929417637871614827626609958003218510835221
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.41497557118931532793467786714826941690575946849987246952356291535072135570562
Short name T606
Test name
Test status
Simulation time 71069183 ps
CPU time 1.87 seconds
Started Nov 22 01:50:53 PM PST 23
Finished Nov 22 01:50:55 PM PST 23
Peak memory 238436 kb
Host smart-cf5dbc6d-4752-4553-af82-a9a4bf9ee0fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41497557118931532793467786714826941690575946849987246952356291535072135570562 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.41497557118931532793467786714826941690575946849987246952356291535072135570562
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.9264801586818885255868734790482227021341356388551839944056311180512264786608
Short name T655
Test name
Test status
Simulation time 111269183 ps
CPU time 2.72 seconds
Started Nov 22 01:50:48 PM PST 23
Finished Nov 22 01:50:52 PM PST 23
Peak memory 246812 kb
Host smart-a01da04c-2a58-445b-8d4b-1fbac5c970b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9264801586818885255868734790482227021341356388551839944056311180512264786608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.otp_ctrl_check_fail.9264801586818885255868734790482227021341356388551839944056311180512264786608
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.16661622116312659874269567990998975267907288062153200653760542701753317972105
Short name T795
Test name
Test status
Simulation time 390019183 ps
CPU time 10.83 seconds
Started Nov 22 01:50:59 PM PST 23
Finished Nov 22 01:51:11 PM PST 23
Peak memory 238548 kb
Host smart-5e821230-e32e-4fec-8757-780535a570e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16661622116312659874269567990998975267907288062153200653760542701753317972105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.otp_ctrl_dai_errs.16661622116312659874269567990998975267907288062153200653760542701753317972105
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.59747459866844626608087978434484712192629131403329637767884211860797758217774
Short name T772
Test name
Test status
Simulation time 614979183 ps
CPU time 11.18 seconds
Started Nov 22 01:50:25 PM PST 23
Finished Nov 22 01:50:37 PM PST 23
Peak memory 238812 kb
Host smart-3ca38881-ee69-4082-b8f2-bbf841a05ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59747459866844626608087978434484712192629131403329637767884211860797758217774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.otp_ctrl_dai_lock.59747459866844626608087978434484712192629131403329637767884211860797758217774
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.29689657884576692431818718559030969123444638503140968528676847566402671890333
Short name T735
Test name
Test status
Simulation time 156689183 ps
CPU time 3.93 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 01:51:09 PM PST 23
Peak memory 238604 kb
Host smart-aeebd466-0dbb-4175-9e56-aa615a4bd9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29689657884576692431818718559030969123444638503140968528676847566402671890333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.otp_ctrl_init_fail.29689657884576692431818718559030969123444638503140968528676847566402671890333
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.69738419085547288601900517065978095463901251852468136444197780308847809434704
Short name T1218
Test name
Test status
Simulation time 1137629183 ps
CPU time 18.29 seconds
Started Nov 22 01:50:59 PM PST 23
Finished Nov 22 01:51:19 PM PST 23
Peak memory 238908 kb
Host smart-013f2ab2-a91e-4365-b538-f0d88145b33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69738419085547288601900517065978095463901251852468136444197780308847809434704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.otp_ctrl_macro_errs.69738419085547288601900517065978095463901251852468136444197780308847809434704
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.40627191801595425972740165025036060740498833417653600689804192174197543477005
Short name T1129
Test name
Test status
Simulation time 346349183 ps
CPU time 7.76 seconds
Started Nov 22 01:50:31 PM PST 23
Finished Nov 22 01:50:40 PM PST 23
Peak memory 238780 kb
Host smart-23983909-8dd5-46f8-9a8b-f757aba94c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40627191801595425972740165025036060740498833417653600689804192174197543477005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.otp_ctrl_parallel_key_req.40627191801595425972740165025036060740498833417653600689804192174197543477005
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.109624413273375644338328230953428330785685607611664563541347695680351325774940
Short name T430
Test name
Test status
Simulation time 176929183 ps
CPU time 4.31 seconds
Started Nov 22 01:51:07 PM PST 23
Finished Nov 22 01:51:13 PM PST 23
Peak memory 238668 kb
Host smart-e45c883a-1c5f-41f6-9ee4-e9eff2797bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109624413273375644338328230953428330785685607611664563541347695680351325774940 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.109624413273375644338328230953428330785685607611664563541347695680351325774940
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.66244076865517979358545984554754194242028980483618317934287799730254244052483
Short name T501
Test name
Test status
Simulation time 486419183 ps
CPU time 12.23 seconds
Started Nov 22 01:50:29 PM PST 23
Finished Nov 22 01:50:42 PM PST 23
Peak memory 238712 kb
Host smart-d7a21345-b561-419b-8954-28d2d228f4c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66244076865517979358545984554754194242028980483618317934287799730254244052483 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.66244076865517979358545984554754194242028980483618317934287799730254244052483
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.35090370946809728095834597157103688748542926197823287467406707705605180758960
Short name T334
Test name
Test status
Simulation time 138839183 ps
CPU time 3.15 seconds
Started Nov 22 01:50:23 PM PST 23
Finished Nov 22 01:50:26 PM PST 23
Peak memory 238808 kb
Host smart-03e09ba8-6962-42b7-b752-4bca14d4b5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35090370946809728095834597157103688748542926197823287467406707705605180758960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.otp_ctrl_smoke.35090370946809728095834597157103688748542926197823287467406707705605180758960
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.59971621506769543729832486609116855757365469982175225875782838758258106264517
Short name T51
Test name
Test status
Simulation time 13240088340 ps
CPU time 130.25 seconds
Started Nov 22 01:50:44 PM PST 23
Finished Nov 22 01:52:55 PM PST 23
Peak memory 241832 kb
Host smart-bc1b1fea-2fcb-4e1b-9cb8-0132d7b5849e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59971621506769543729832486609116855757365469982175225875782838758258106264517 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.59971621506769543729832486609116855757365469982175225875782838758258106264517
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.39949184622599934189156109789738886742076929902657074378070368710001018566573
Short name T901
Test name
Test status
Simulation time 150268849183 ps
CPU time 1863.32 seconds
Started Nov 22 01:50:53 PM PST 23
Finished Nov 22 02:21:58 PM PST 23
Peak memory 517576 kb
Host smart-9f0f1c5c-9c7c-4fa5-8397-62c39ef6139e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994918462259993418915
6109789738886742076929902657074378070368710001018566573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_res
et.39949184622599934189156109789738886742076929902657074378070368710001018566573
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.38441507290579019313549218973875688894319623531057353219405512059363559382269
Short name T636
Test name
Test status
Simulation time 549639183 ps
CPU time 8.98 seconds
Started Nov 22 01:50:51 PM PST 23
Finished Nov 22 01:51:01 PM PST 23
Peak memory 246960 kb
Host smart-7ec4c95a-23cb-4658-b8f1-285ab2da4780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38441507290579019313549218973875688894319623531057353219405512059363559382269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.otp_ctrl_test_access.38441507290579019313549218973875688894319623531057353219405512059363559382269
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.86848994882409383550212245863690227682109955017404027506947629821511145602753
Short name T283
Test name
Test status
Simulation time 156689183 ps
CPU time 3.9 seconds
Started Nov 22 01:52:09 PM PST 23
Finished Nov 22 01:52:16 PM PST 23
Peak memory 238652 kb
Host smart-f8db0785-accb-4412-9692-131601e0606c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86848994882409383550212245863690227682109955017404027506947629821511145602753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 190.otp_ctrl_init_fail.86848994882409383550212245863690227682109955017404027506947629821511145602753
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.115609205024740983402278176840330919356875204961531616596679409799046374696179
Short name T438
Test name
Test status
Simulation time 176929183 ps
CPU time 4.13 seconds
Started Nov 22 01:52:13 PM PST 23
Finished Nov 22 01:52:20 PM PST 23
Peak memory 238680 kb
Host smart-acd7a661-4942-4883-ac23-f7750548be26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115609205024740983402278176840330919356875204961531616596679409799046374696179 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.115609205024740983402278176840330919356875204961531616596679409799046374696179
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.38223923854043643071809242305546883378051182017217153930203994490923192613916
Short name T351
Test name
Test status
Simulation time 156689183 ps
CPU time 4.04 seconds
Started Nov 22 01:51:58 PM PST 23
Finished Nov 22 01:52:03 PM PST 23
Peak memory 238660 kb
Host smart-8e794a5c-e47d-4fc8-8e1f-e71430a0df92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38223923854043643071809242305546883378051182017217153930203994490923192613916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 191.otp_ctrl_init_fail.38223923854043643071809242305546883378051182017217153930203994490923192613916
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.62027660576586205521034071881880581428448678679626364832967875128390525650613
Short name T396
Test name
Test status
Simulation time 176929183 ps
CPU time 4.38 seconds
Started Nov 22 01:52:13 PM PST 23
Finished Nov 22 01:52:20 PM PST 23
Peak memory 238680 kb
Host smart-9ca645d7-062c-4cb1-a6b2-43e11c4e01ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62027660576586205521034071881880581428448678679626364832967875128390525650613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.62027660576586205521034071881880581428448678679626364832967875128390525650613
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.99372519602008697131151499656357857094002294372736294784988063886607096651003
Short name T389
Test name
Test status
Simulation time 156689183 ps
CPU time 3.98 seconds
Started Nov 22 01:52:04 PM PST 23
Finished Nov 22 01:52:10 PM PST 23
Peak memory 238656 kb
Host smart-9174219a-2d38-4f3c-8c4c-8b1bb6cbee56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99372519602008697131151499656357857094002294372736294784988063886607096651003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 192.otp_ctrl_init_fail.99372519602008697131151499656357857094002294372736294784988063886607096651003
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.85370139164341506462509210820044592101068579632354559549711572325751264394516
Short name T571
Test name
Test status
Simulation time 176929183 ps
CPU time 4.29 seconds
Started Nov 22 01:52:09 PM PST 23
Finished Nov 22 01:52:17 PM PST 23
Peak memory 238680 kb
Host smart-1116411a-66f6-46c3-b5d2-86083371b7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85370139164341506462509210820044592101068579632354559549711572325751264394516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.85370139164341506462509210820044592101068579632354559549711572325751264394516
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.52486257001630069255818619462153933860968306442674850928047444130099915234572
Short name T423
Test name
Test status
Simulation time 156689183 ps
CPU time 4.24 seconds
Started Nov 22 01:52:30 PM PST 23
Finished Nov 22 01:52:38 PM PST 23
Peak memory 238652 kb
Host smart-b6a6d4ed-c07f-4373-b00e-69d348f205f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52486257001630069255818619462153933860968306442674850928047444130099915234572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 193.otp_ctrl_init_fail.52486257001630069255818619462153933860968306442674850928047444130099915234572
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.75432570455562992198915991212538065977718173536220387324873926731382346204901
Short name T226
Test name
Test status
Simulation time 176929183 ps
CPU time 4.36 seconds
Started Nov 22 01:52:07 PM PST 23
Finished Nov 22 01:52:15 PM PST 23
Peak memory 238624 kb
Host smart-06dd071f-9969-4796-942b-7bb2bcc277d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75432570455562992198915991212538065977718173536220387324873926731382346204901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.75432570455562992198915991212538065977718173536220387324873926731382346204901
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.69079213686562424689981477120379431942089507681072249645208099967948198532070
Short name T627
Test name
Test status
Simulation time 156689183 ps
CPU time 4.44 seconds
Started Nov 22 01:52:04 PM PST 23
Finished Nov 22 01:52:12 PM PST 23
Peak memory 238604 kb
Host smart-10ce70c2-08e0-4d96-b1c5-015ad134e246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69079213686562424689981477120379431942089507681072249645208099967948198532070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 194.otp_ctrl_init_fail.69079213686562424689981477120379431942089507681072249645208099967948198532070
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.59963000814038665943374201404748135801436822667379972924862895441392483656786
Short name T616
Test name
Test status
Simulation time 176929183 ps
CPU time 4.39 seconds
Started Nov 22 01:51:58 PM PST 23
Finished Nov 22 01:52:04 PM PST 23
Peak memory 238708 kb
Host smart-eef793a8-5d56-4f62-9716-1fc7d412fe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59963000814038665943374201404748135801436822667379972924862895441392483656786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.59963000814038665943374201404748135801436822667379972924862895441392483656786
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.53988605973496685943808274491496746126130695878130301471145740030829204891918
Short name T1170
Test name
Test status
Simulation time 156689183 ps
CPU time 3.88 seconds
Started Nov 22 01:52:02 PM PST 23
Finished Nov 22 01:52:13 PM PST 23
Peak memory 238484 kb
Host smart-e93d3774-e72a-463b-ada5-bc0933ed2f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53988605973496685943808274491496746126130695878130301471145740030829204891918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 195.otp_ctrl_init_fail.53988605973496685943808274491496746126130695878130301471145740030829204891918
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.47811541106215606629654752857416628855741500310226152565164207022357119786269
Short name T486
Test name
Test status
Simulation time 176929183 ps
CPU time 4.54 seconds
Started Nov 22 01:52:14 PM PST 23
Finished Nov 22 01:52:20 PM PST 23
Peak memory 238680 kb
Host smart-41a09389-c98f-4ca8-958c-ecf6690db090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47811541106215606629654752857416628855741500310226152565164207022357119786269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.47811541106215606629654752857416628855741500310226152565164207022357119786269
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.71844509628639430482065734285282859966490642406533567042187001622244000223461
Short name T910
Test name
Test status
Simulation time 156689183 ps
CPU time 3.99 seconds
Started Nov 22 01:52:09 PM PST 23
Finished Nov 22 01:52:16 PM PST 23
Peak memory 238588 kb
Host smart-92df15b0-bce0-41c9-be28-281d01812d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71844509628639430482065734285282859966490642406533567042187001622244000223461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 196.otp_ctrl_init_fail.71844509628639430482065734285282859966490642406533567042187001622244000223461
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.31730403762528201503347796287870515097994642649693864500130274572028197635507
Short name T66
Test name
Test status
Simulation time 176929183 ps
CPU time 4.25 seconds
Started Nov 22 01:52:02 PM PST 23
Finished Nov 22 01:52:07 PM PST 23
Peak memory 238696 kb
Host smart-47c87145-4235-44ff-9635-d24d75d5dd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31730403762528201503347796287870515097994642649693864500130274572028197635507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.31730403762528201503347796287870515097994642649693864500130274572028197635507
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.33898011798051373661116561258799442874167388727932680163385572808374230327259
Short name T535
Test name
Test status
Simulation time 156689183 ps
CPU time 4.03 seconds
Started Nov 22 01:52:01 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238612 kb
Host smart-95afc5cb-9cde-4e0a-b471-5fffd15a691e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33898011798051373661116561258799442874167388727932680163385572808374230327259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 197.otp_ctrl_init_fail.33898011798051373661116561258799442874167388727932680163385572808374230327259
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.87685640017915538395599054753230737704393492041208825303950824416738092783687
Short name T985
Test name
Test status
Simulation time 176929183 ps
CPU time 4.23 seconds
Started Nov 22 01:51:59 PM PST 23
Finished Nov 22 01:52:05 PM PST 23
Peak memory 238700 kb
Host smart-79915e3e-982c-4a87-85b3-82a134de9dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87685640017915538395599054753230737704393492041208825303950824416738092783687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.87685640017915538395599054753230737704393492041208825303950824416738092783687
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.109878018901167292164810040137927859501605421887056626893453486422091080757179
Short name T1060
Test name
Test status
Simulation time 156689183 ps
CPU time 4.03 seconds
Started Nov 22 01:52:13 PM PST 23
Finished Nov 22 01:52:20 PM PST 23
Peak memory 238684 kb
Host smart-17ebe7be-80a7-4c29-a112-208cede549ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109878018901167292164810040137927859501605421887056626893453486422091080757179 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 198.otp_ctrl_init_fail.109878018901167292164810040137927859501605421887056626893453486422091080757179
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.17964503600259117036389012032467007337378359978221478669352181348417031765108
Short name T715
Test name
Test status
Simulation time 176929183 ps
CPU time 4.16 seconds
Started Nov 22 01:52:00 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238540 kb
Host smart-2c9853ac-f25d-4faf-a21f-3700e1e39590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17964503600259117036389012032467007337378359978221478669352181348417031765108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.17964503600259117036389012032467007337378359978221478669352181348417031765108
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.86236028276387160572367138075209932895986429143425770693319173146839930523921
Short name T1121
Test name
Test status
Simulation time 156689183 ps
CPU time 4.06 seconds
Started Nov 22 01:52:11 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238648 kb
Host smart-42cde8ce-973f-4e21-ae06-a66d8aeb683a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86236028276387160572367138075209932895986429143425770693319173146839930523921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 199.otp_ctrl_init_fail.86236028276387160572367138075209932895986429143425770693319173146839930523921
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.64675515665003078859365411528341801610936412578300965886495869444609081834720
Short name T995
Test name
Test status
Simulation time 176929183 ps
CPU time 4.26 seconds
Started Nov 22 01:52:20 PM PST 23
Finished Nov 22 01:52:27 PM PST 23
Peak memory 238660 kb
Host smart-d4a4de0e-9cc2-45c6-95a7-cb0bfa8bc6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64675515665003078859365411528341801610936412578300965886495869444609081834720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.64675515665003078859365411528341801610936412578300965886495869444609081834720
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.24505270076392432473959163459199080541878840247449813186761028300836730374950
Short name T733
Test name
Test status
Simulation time 71069183 ps
CPU time 1.82 seconds
Started Nov 22 01:49:58 PM PST 23
Finished Nov 22 01:50:02 PM PST 23
Peak memory 238460 kb
Host smart-398f45d7-8ee2-4dbb-9ffa-b1d1c6fb5954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24505270076392432473959163459199080541878840247449813186761028300836730374950 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.24505270076392432473959163459199080541878840247449813186761028300836730374950
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.33278359508223003084588044146664338330804911295335005798297690286432096708846
Short name T1012
Test name
Test status
Simulation time 190889183 ps
CPU time 4.78 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:10 PM PST 23
Peak memory 238744 kb
Host smart-e682dfbc-5b3d-4c98-85bc-936d0d2df38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33278359508223003084588044146664338330804911295335005798297690286432096708846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.otp_ctrl_background_chks.33278359508223003084588044146664338330804911295335005798297690286432096708846
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.24727407821450937872064364072053440456351878835042277237104771254384384971900
Short name T766
Test name
Test status
Simulation time 111269183 ps
CPU time 2.62 seconds
Started Nov 22 01:49:59 PM PST 23
Finished Nov 22 01:50:03 PM PST 23
Peak memory 246748 kb
Host smart-c3022904-d173-4f9e-8447-790b7bde9dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24727407821450937872064364072053440456351878835042277237104771254384384971900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.otp_ctrl_check_fail.24727407821450937872064364072053440456351878835042277237104771254384384971900
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.114593837551887447462570088020606887774024220429574977592865704081385225376572
Short name T1034
Test name
Test status
Simulation time 390019183 ps
CPU time 11.44 seconds
Started Nov 22 01:50:10 PM PST 23
Finished Nov 22 01:50:29 PM PST 23
Peak memory 238748 kb
Host smart-b5d4b933-355f-4e32-a139-962d22ee5442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114593837551887447462570088020606887774024220429574977592865704081385225376572 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.otp_ctrl_dai_errs.114593837551887447462570088020606887774024220429574977592865704081385225376572
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.102915677481653640304520959284934445812462827514882927652676202691533736227455
Short name T1168
Test name
Test status
Simulation time 614979183 ps
CPU time 10.78 seconds
Started Nov 22 01:50:00 PM PST 23
Finished Nov 22 01:50:13 PM PST 23
Peak memory 238820 kb
Host smart-96e50e9e-de64-4c9d-a459-d48d270981e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102915677481653640304520959284934445812462827514882927652676202691533736227455 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.otp_ctrl_dai_lock.102915677481653640304520959284934445812462827514882927652676202691533736227455
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.86017699556086957183476996680010638890096714028215988968467219765858633552799
Short name T992
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:50:06 PM PST 23
Finished Nov 22 01:50:13 PM PST 23
Peak memory 238732 kb
Host smart-9a01994e-1755-4ca2-96e9-c97b14b4fc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86017699556086957183476996680010638890096714028215988968467219765858633552799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.otp_ctrl_init_fail.86017699556086957183476996680010638890096714028215988968467219765858633552799
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.98820437835770039139883163523466345261157084597826967234793714428750903457889
Short name T779
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.1 seconds
Started Nov 22 01:50:03 PM PST 23
Finished Nov 22 01:50:25 PM PST 23
Peak memory 238992 kb
Host smart-4c3960e7-5348-4e07-8a7a-d5da0e119dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98820437835770039139883163523466345261157084597826967234793714428750903457889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.otp_ctrl_macro_errs.98820437835770039139883163523466345261157084597826967234793714428750903457889
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.51475630891389469628927594762470957697834442874682731226790185230721628267746
Short name T821
Test name
Test status
Simulation time 346349183 ps
CPU time 7.39 seconds
Started Nov 22 01:50:09 PM PST 23
Finished Nov 22 01:50:24 PM PST 23
Peak memory 238780 kb
Host smart-de124b49-689b-4c6f-90a2-0b09a0b59973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51475630891389469628927594762470957697834442874682731226790185230721628267746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.otp_ctrl_parallel_key_req.51475630891389469628927594762470957697834442874682731226790185230721628267746
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.110389548497591939809725074971276988618495764820189775757914527721725599357151
Short name T583
Test name
Test status
Simulation time 176929183 ps
CPU time 4.33 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:17 PM PST 23
Peak memory 238672 kb
Host smart-cd7289dc-369f-448a-aaf5-5ae09d5172eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110389548497591939809725074971276988618495764820189775757914527721725599357151 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.110389548497591939809725074971276988618495764820189775757914527721725599357151
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.46892990671571057486644112464022645396512162958598619572354640628549816368379
Short name T967
Test name
Test status
Simulation time 486419183 ps
CPU time 12.43 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:17 PM PST 23
Peak memory 238704 kb
Host smart-f7df8be3-a0d7-4753-87a7-ecc554e125d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=46892990671571057486644112464022645396512162958598619572354640628549816368379 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.46892990671571057486644112464022645396512162958598619572354640628549816368379
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.105546461674570699337594982034069508026028253652315283737370728155462345802619
Short name T986
Test name
Test status
Simulation time 137469183 ps
CPU time 3.8 seconds
Started Nov 22 01:50:04 PM PST 23
Finished Nov 22 01:50:10 PM PST 23
Peak memory 238680 kb
Host smart-0277d614-d6ed-41b8-8147-29bb70f08da3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105546461674570699337594982034069508026028253652315283737370728155462345802619 -assert nopostproc +UVM_TE
STNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_regwen.105546461674570699337594982034069508026028253652315283737370728155462345802619
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.51501862400424499946633739997631367262764184435185561852083102063916373715661
Short name T27
Test name
Test status
Simulation time 8539099183 ps
CPU time 146.17 seconds
Started Nov 22 01:50:01 PM PST 23
Finished Nov 22 01:52:30 PM PST 23
Peak memory 268344 kb
Host smart-9c0efc0c-2cca-4ecb-a6d6-2f447e34127e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51501862400424499946633739997631367262764184435185561852083102063916373715661 -assert nopostpro
c +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.51501862400424499946633739997631367262764184435185561852083102063916373715661
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.55301358153941631116692554171789008130768404635885673459221223448656543356175
Short name T257
Test name
Test status
Simulation time 138839183 ps
CPU time 3.07 seconds
Started Nov 22 01:50:11 PM PST 23
Finished Nov 22 01:50:21 PM PST 23
Peak memory 238808 kb
Host smart-17d72240-ef0b-4f74-b4d2-cd283b6802d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55301358153941631116692554171789008130768404635885673459221223448656543356175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.otp_ctrl_smoke.55301358153941631116692554171789008130768404635885673459221223448656543356175
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.111260044959104347754206134625321386310584730645195521184428883888185665186477
Short name T1228
Test name
Test status
Simulation time 13240088340 ps
CPU time 135.11 seconds
Started Nov 22 01:50:00 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 241840 kb
Host smart-f17dd046-ee4b-4328-9a5c-ba3fe65c9284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111260044959104347754206134625321386310584730645195521184428883888185665186477 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.111260044959104347754206134625321386310584730645195521184428883888185665186477
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.109055375341776216080714759367939983691512400074805891924612133720107960203033
Short name T697
Test name
Test status
Simulation time 150268849183 ps
CPU time 1974.61 seconds
Started Nov 22 01:50:01 PM PST 23
Finished Nov 22 02:22:58 PM PST 23
Peak memory 517576 kb
Host smart-fb63bbb2-85ae-4877-9817-0ee2344007f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090553753417762160807
14759367939983691512400074805891924612133720107960203033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_res
et.109055375341776216080714759367939983691512400074805891924612133720107960203033
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.90756910423813798381031516737726207301626116893313674532205203633935745312001
Short name T297
Test name
Test status
Simulation time 549639183 ps
CPU time 9.42 seconds
Started Nov 22 01:49:55 PM PST 23
Finished Nov 22 01:50:05 PM PST 23
Peak memory 246960 kb
Host smart-f4f97416-3157-4394-9d4b-359489f0f4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90756910423813798381031516737726207301626116893313674532205203633935745312001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.otp_ctrl_test_access.90756910423813798381031516737726207301626116893313674532205203633935745312001
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.28910174561552152782494373996211065952205736249980123957568988105297361959956
Short name T868
Test name
Test status
Simulation time 71069183 ps
CPU time 1.87 seconds
Started Nov 22 01:50:44 PM PST 23
Finished Nov 22 01:50:47 PM PST 23
Peak memory 238408 kb
Host smart-7a59bb84-de8d-4585-81d6-58a5c03ce4d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28910174561552152782494373996211065952205736249980123957568988105297361959956 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.28910174561552152782494373996211065952205736249980123957568988105297361959956
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.60068127858735748949420142578049786918255690211011923091273471986905076321357
Short name T1293
Test name
Test status
Simulation time 111269183 ps
CPU time 2.8 seconds
Started Nov 22 01:50:42 PM PST 23
Finished Nov 22 01:50:45 PM PST 23
Peak memory 246720 kb
Host smart-cb6460d9-36b3-41b7-af60-398d7ef6ac28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60068127858735748949420142578049786918255690211011923091273471986905076321357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.otp_ctrl_check_fail.60068127858735748949420142578049786918255690211011923091273471986905076321357
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.79396452754283369399550815191428930911702839051595284501506422641279565715730
Short name T803
Test name
Test status
Simulation time 390019183 ps
CPU time 10.77 seconds
Started Nov 22 01:50:50 PM PST 23
Finished Nov 22 01:51:01 PM PST 23
Peak memory 238616 kb
Host smart-beb5d33f-34ec-45b4-abd2-cce56c49819b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79396452754283369399550815191428930911702839051595284501506422641279565715730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.otp_ctrl_dai_errs.79396452754283369399550815191428930911702839051595284501506422641279565715730
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.78785811985973056747402030019872444063030677474802567620843297777244418614131
Short name T265
Test name
Test status
Simulation time 614979183 ps
CPU time 10.62 seconds
Started Nov 22 01:50:51 PM PST 23
Finished Nov 22 01:51:03 PM PST 23
Peak memory 238844 kb
Host smart-6f3322f3-b87b-4f82-a98c-47ccf5930a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78785811985973056747402030019872444063030677474802567620843297777244418614131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.otp_ctrl_dai_lock.78785811985973056747402030019872444063030677474802567620843297777244418614131
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.111961631621611808113248384901260248590422969080797814778899713230563931342315
Short name T1213
Test name
Test status
Simulation time 156689183 ps
CPU time 4.02 seconds
Started Nov 22 01:50:56 PM PST 23
Finished Nov 22 01:51:01 PM PST 23
Peak memory 238656 kb
Host smart-e74e6c38-1927-4fe4-b2f6-d30d2ae304da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111961631621611808113248384901260248590422969080797814778899713230563931342315 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.otp_ctrl_init_fail.111961631621611808113248384901260248590422969080797814778899713230563931342315
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.62530412314529901906640183828079403013769175361218890085633875553224834509695
Short name T55
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.55 seconds
Started Nov 22 01:50:43 PM PST 23
Finished Nov 22 01:51:03 PM PST 23
Peak memory 238948 kb
Host smart-b803855e-7965-45f2-86cc-a95e363a4b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62530412314529901906640183828079403013769175361218890085633875553224834509695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.otp_ctrl_macro_errs.62530412314529901906640183828079403013769175361218890085633875553224834509695
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.3848716481639988356828189169696000071244767059832495488003352510338327960270
Short name T1016
Test name
Test status
Simulation time 346349183 ps
CPU time 7.45 seconds
Started Nov 22 01:50:51 PM PST 23
Finished Nov 22 01:50:59 PM PST 23
Peak memory 238788 kb
Host smart-4ab0ec9e-ecff-4011-8430-6bb64bdb260d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848716481639988356828189169696000071244767059832495488003352510338327960270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 20.otp_ctrl_parallel_key_req.3848716481639988356828189169696000071244767059832495488003352510338327960270
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.37068945643339676821103812069650026964998022563457837883947126391762110339780
Short name T219
Test name
Test status
Simulation time 176929183 ps
CPU time 4.23 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 01:51:08 PM PST 23
Peak memory 238616 kb
Host smart-4fa0b07a-56e6-4837-81d7-dcd68410fbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37068945643339676821103812069650026964998022563457837883947126391762110339780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.37068945643339676821103812069650026964998022563457837883947126391762110339780
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.60575819100958034185544983330145580205233167754288426366756866594268909469649
Short name T424
Test name
Test status
Simulation time 486419183 ps
CPU time 11.93 seconds
Started Nov 22 01:50:57 PM PST 23
Finished Nov 22 01:51:10 PM PST 23
Peak memory 238688 kb
Host smart-fca76be4-c824-4d1b-b1c1-c401fa6889aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60575819100958034185544983330145580205233167754288426366756866594268909469649 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.60575819100958034185544983330145580205233167754288426366756866594268909469649
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.113299604992323691068273212713195827898998657527200530389692119274366575325716
Short name T403
Test name
Test status
Simulation time 137469183 ps
CPU time 3.47 seconds
Started Nov 22 01:50:51 PM PST 23
Finished Nov 22 01:50:55 PM PST 23
Peak memory 238544 kb
Host smart-f55b56aa-2748-4d93-b072-587d902e40ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113299604992323691068273212713195827898998657527200530389692119274366575325716 -assert nopostproc +UVM_TE
STNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.otp_ctrl_regwen.113299604992323691068273212713195827898998657527200530389692119274366575325716
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.26744524891397370224262599556605460448845419089016923287539282105992327628661
Short name T671
Test name
Test status
Simulation time 138839183 ps
CPU time 3.05 seconds
Started Nov 22 01:50:54 PM PST 23
Finished Nov 22 01:50:57 PM PST 23
Peak memory 238720 kb
Host smart-756ab553-5d6c-4af9-a648-fc7884f82ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26744524891397370224262599556605460448845419089016923287539282105992327628661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.otp_ctrl_smoke.26744524891397370224262599556605460448845419089016923287539282105992327628661
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.84591440163332861521012399950020999645916637043037996483279391693678687538492
Short name T1104
Test name
Test status
Simulation time 13240088340 ps
CPU time 136.84 seconds
Started Nov 22 01:50:44 PM PST 23
Finished Nov 22 01:53:02 PM PST 23
Peak memory 241832 kb
Host smart-2761bf3a-39ba-4cc6-8e6b-f7840a2f4faf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84591440163332861521012399950020999645916637043037996483279391693678687538492 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.84591440163332861521012399950020999645916637043037996483279391693678687538492
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.10835871252453650258479131791291167339716813770759253002156051626697772999199
Short name T421
Test name
Test status
Simulation time 150268849183 ps
CPU time 1929.64 seconds
Started Nov 22 01:51:08 PM PST 23
Finished Nov 22 02:23:20 PM PST 23
Peak memory 517544 kb
Host smart-52d0555e-d72f-43cc-8dd4-69927c384d13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083587125245365025847
9131791291167339716813770759253002156051626697772999199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_res
et.10835871252453650258479131791291167339716813770759253002156051626697772999199
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.24598384814111590250568490114058428070339581709616701799077396283592098526007
Short name T560
Test name
Test status
Simulation time 549639183 ps
CPU time 9.24 seconds
Started Nov 22 01:50:30 PM PST 23
Finished Nov 22 01:50:40 PM PST 23
Peak memory 246996 kb
Host smart-c7e61036-f248-4f6a-8fd7-f4718d84c807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24598384814111590250568490114058428070339581709616701799077396283592098526007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.otp_ctrl_test_access.24598384814111590250568490114058428070339581709616701799077396283592098526007
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.82918594722923677025984659391482628000509647905378148361363288031809082246550
Short name T799
Test name
Test status
Simulation time 156689183 ps
CPU time 3.98 seconds
Started Nov 22 01:52:17 PM PST 23
Finished Nov 22 01:52:25 PM PST 23
Peak memory 238652 kb
Host smart-f5893f64-9eb8-44a6-8b05-153aa57fdca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82918594722923677025984659391482628000509647905378148361363288031809082246550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 200.otp_ctrl_init_fail.82918594722923677025984659391482628000509647905378148361363288031809082246550
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.59279604363255172298523528678941910780722790462996660271157346898170576056321
Short name T415
Test name
Test status
Simulation time 156689183 ps
CPU time 4.16 seconds
Started Nov 22 01:52:00 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238652 kb
Host smart-54bed51b-0791-4207-9eae-57431a9f47c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59279604363255172298523528678941910780722790462996660271157346898170576056321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 201.otp_ctrl_init_fail.59279604363255172298523528678941910780722790462996660271157346898170576056321
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.106973025092931081213090090519805608585727130603043315954374918576070895018219
Short name T339
Test name
Test status
Simulation time 156689183 ps
CPU time 4.08 seconds
Started Nov 22 01:52:02 PM PST 23
Finished Nov 22 01:52:08 PM PST 23
Peak memory 238612 kb
Host smart-35be688f-78d8-480b-ad47-767bcf7d1618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106973025092931081213090090519805608585727130603043315954374918576070895018219 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 202.otp_ctrl_init_fail.106973025092931081213090090519805608585727130603043315954374918576070895018219
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.50839178880346290765793704963332496371831560752828386095886437930723447151638
Short name T1296
Test name
Test status
Simulation time 156689183 ps
CPU time 4.05 seconds
Started Nov 22 01:52:16 PM PST 23
Finished Nov 22 01:52:24 PM PST 23
Peak memory 238532 kb
Host smart-99f5e9a3-a75b-417f-a7a8-945c69f5314e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50839178880346290765793704963332496371831560752828386095886437930723447151638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 203.otp_ctrl_init_fail.50839178880346290765793704963332496371831560752828386095886437930723447151638
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.87596496533256268337636793992446935946704464442520106652719942252331324106657
Short name T237
Test name
Test status
Simulation time 156689183 ps
CPU time 3.95 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 01:52:21 PM PST 23
Peak memory 238648 kb
Host smart-9c452abf-a066-4147-a8a9-6ae2ceb5c699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87596496533256268337636793992446935946704464442520106652719942252331324106657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 204.otp_ctrl_init_fail.87596496533256268337636793992446935946704464442520106652719942252331324106657
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.20140322460493878675186294522348566988003883650863154972261860854796676561503
Short name T1176
Test name
Test status
Simulation time 156689183 ps
CPU time 3.96 seconds
Started Nov 22 01:52:24 PM PST 23
Finished Nov 22 01:52:30 PM PST 23
Peak memory 238492 kb
Host smart-c2051c54-39c3-4441-98fe-2bd21f2ab9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20140322460493878675186294522348566988003883650863154972261860854796676561503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 205.otp_ctrl_init_fail.20140322460493878675186294522348566988003883650863154972261860854796676561503
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.98689202706485978836440472017941171474059989685606351598904005891124898315245
Short name T452
Test name
Test status
Simulation time 156689183 ps
CPU time 3.98 seconds
Started Nov 22 01:52:05 PM PST 23
Finished Nov 22 01:52:12 PM PST 23
Peak memory 238604 kb
Host smart-1e292a9d-a8b8-48de-a871-52c921b994ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98689202706485978836440472017941171474059989685606351598904005891124898315245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 206.otp_ctrl_init_fail.98689202706485978836440472017941171474059989685606351598904005891124898315245
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.59410613684702295297364088799330045053457016676894114324183116909938860588144
Short name T406
Test name
Test status
Simulation time 156689183 ps
CPU time 3.96 seconds
Started Nov 22 01:52:06 PM PST 23
Finished Nov 22 01:52:13 PM PST 23
Peak memory 238616 kb
Host smart-7c735886-bebb-4a6d-bf32-436209a371f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59410613684702295297364088799330045053457016676894114324183116909938860588144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 207.otp_ctrl_init_fail.59410613684702295297364088799330045053457016676894114324183116909938860588144
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.1086988404241798405170057052826628552243039695075742061913876089197959991725
Short name T457
Test name
Test status
Simulation time 156689183 ps
CPU time 3.95 seconds
Started Nov 22 01:52:17 PM PST 23
Finished Nov 22 01:52:25 PM PST 23
Peak memory 238644 kb
Host smart-6e0194d3-442c-470a-a315-42c6f71656bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086988404241798405170057052826628552243039695075742061913876089197959991725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 208.otp_ctrl_init_fail.1086988404241798405170057052826628552243039695075742061913876089197959991725
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.74687555713430727575077374962481778390799748266126863876947445617073771432213
Short name T469
Test name
Test status
Simulation time 156689183 ps
CPU time 3.93 seconds
Started Nov 22 01:52:11 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238484 kb
Host smart-80a65a92-e457-441a-998c-9635f2b2731e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74687555713430727575077374962481778390799748266126863876947445617073771432213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 209.otp_ctrl_init_fail.74687555713430727575077374962481778390799748266126863876947445617073771432213
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.96403199865791413155203573321723081983673340584404015603529106298268033478332
Short name T370
Test name
Test status
Simulation time 111269183 ps
CPU time 2.65 seconds
Started Nov 22 01:50:57 PM PST 23
Finished Nov 22 01:51:01 PM PST 23
Peak memory 246812 kb
Host smart-22f89e38-949c-4aae-b319-e797b79413b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96403199865791413155203573321723081983673340584404015603529106298268033478332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.otp_ctrl_check_fail.96403199865791413155203573321723081983673340584404015603529106298268033478332
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.42890027563359539707673065705553924055450500579466055781784579030606470750367
Short name T1088
Test name
Test status
Simulation time 390019183 ps
CPU time 11.23 seconds
Started Nov 22 01:50:59 PM PST 23
Finished Nov 22 01:51:11 PM PST 23
Peak memory 238640 kb
Host smart-5ec77b4a-1809-46bc-aa74-9cc5312755f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42890027563359539707673065705553924055450500579466055781784579030606470750367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.otp_ctrl_dai_errs.42890027563359539707673065705553924055450500579466055781784579030606470750367
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.17285235106222162310136575059499912777761741555785001642738432554277336907576
Short name T45
Test name
Test status
Simulation time 614979183 ps
CPU time 10.56 seconds
Started Nov 22 01:50:23 PM PST 23
Finished Nov 22 01:50:34 PM PST 23
Peak memory 238812 kb
Host smart-b5cdf694-9989-4fc6-a44a-c42ccf3a1ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17285235106222162310136575059499912777761741555785001642738432554277336907576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.otp_ctrl_dai_lock.17285235106222162310136575059499912777761741555785001642738432554277336907576
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.95028212244170334744690264628577072377304254026330956360594877320272827796867
Short name T321
Test name
Test status
Simulation time 156689183 ps
CPU time 3.82 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 01:51:08 PM PST 23
Peak memory 238560 kb
Host smart-b9388d2c-f585-4fb7-93ec-749890c78cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95028212244170334744690264628577072377304254026330956360594877320272827796867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.otp_ctrl_init_fail.95028212244170334744690264628577072377304254026330956360594877320272827796867
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.17483014082783773904907786177219310044838799603765295764673978627360586655302
Short name T1035
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.07 seconds
Started Nov 22 01:50:49 PM PST 23
Finished Nov 22 01:51:09 PM PST 23
Peak memory 238980 kb
Host smart-31a40294-14dd-48da-b843-8e54fe0631a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17483014082783773904907786177219310044838799603765295764673978627360586655302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.otp_ctrl_macro_errs.17483014082783773904907786177219310044838799603765295764673978627360586655302
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.95235341647613036789421746288583598058855246305108350519792776316679608625436
Short name T385
Test name
Test status
Simulation time 346349183 ps
CPU time 7.62 seconds
Started Nov 22 01:50:52 PM PST 23
Finished Nov 22 01:51:01 PM PST 23
Peak memory 238792 kb
Host smart-32401231-ccd6-42fd-b5a1-b7f04b927f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95235341647613036789421746288583598058855246305108350519792776316679608625436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.otp_ctrl_parallel_key_req.95235341647613036789421746288583598058855246305108350519792776316679608625436
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.91093079801395318803652315189854729110028691152858110714288360952722065147897
Short name T1292
Test name
Test status
Simulation time 176929183 ps
CPU time 4.58 seconds
Started Nov 22 01:51:09 PM PST 23
Finished Nov 22 01:51:15 PM PST 23
Peak memory 238620 kb
Host smart-985375d9-7ff9-44c2-8e72-52f2f2b6a2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91093079801395318803652315189854729110028691152858110714288360952722065147897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.91093079801395318803652315189854729110028691152858110714288360952722065147897
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.49397051057608096527335888803416262723898566478036221379342802563808589227341
Short name T1008
Test name
Test status
Simulation time 486419183 ps
CPU time 12.52 seconds
Started Nov 22 01:50:42 PM PST 23
Finished Nov 22 01:50:55 PM PST 23
Peak memory 238608 kb
Host smart-97c46c82-4b0d-432e-9240-240ba842bb36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49397051057608096527335888803416262723898566478036221379342802563808589227341 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.49397051057608096527335888803416262723898566478036221379342802563808589227341
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.49240534801065008393627663059963293892050629956828999935496736333231786404512
Short name T881
Test name
Test status
Simulation time 137469183 ps
CPU time 3.67 seconds
Started Nov 22 01:50:35 PM PST 23
Finished Nov 22 01:50:40 PM PST 23
Peak memory 238676 kb
Host smart-e5854714-74c9-4712-a679-956535c8ee39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49240534801065008393627663059963293892050629956828999935496736333231786404512 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.otp_ctrl_regwen.49240534801065008393627663059963293892050629956828999935496736333231786404512
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.58865042525687007280642669681167124710249753404949211552446482236337961586644
Short name T997
Test name
Test status
Simulation time 138839183 ps
CPU time 3.02 seconds
Started Nov 22 01:51:07 PM PST 23
Finished Nov 22 01:51:12 PM PST 23
Peak memory 238768 kb
Host smart-072c11c0-737d-4eb5-a9b9-acffacc2b1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58865042525687007280642669681167124710249753404949211552446482236337961586644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.otp_ctrl_smoke.58865042525687007280642669681167124710249753404949211552446482236337961586644
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.91059141542727502016834834893694720008634471620942956893885528322608895434183
Short name T1283
Test name
Test status
Simulation time 13240088340 ps
CPU time 127.56 seconds
Started Nov 22 01:50:49 PM PST 23
Finished Nov 22 01:52:57 PM PST 23
Peak memory 241828 kb
Host smart-36656b91-ca0a-4a8b-b801-34e412f4793a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91059141542727502016834834893694720008634471620942956893885528322608895434183 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.91059141542727502016834834893694720008634471620942956893885528322608895434183
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.73779091770506810038302639606211523714428970852721118630605731742476336181359
Short name T680
Test name
Test status
Simulation time 150268849183 ps
CPU time 1923.78 seconds
Started Nov 22 01:50:54 PM PST 23
Finished Nov 22 02:23:03 PM PST 23
Peak memory 517392 kb
Host smart-69169000-5fdb-4c9b-8f20-0051b0133295
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7377909177050681003830
2639606211523714428970852721118630605731742476336181359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_res
et.73779091770506810038302639606211523714428970852721118630605731742476336181359
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.13448129439795405483594597614567613070808103084589689747902677521957313597474
Short name T274
Test name
Test status
Simulation time 549639183 ps
CPU time 8.63 seconds
Started Nov 22 01:51:05 PM PST 23
Finished Nov 22 01:51:16 PM PST 23
Peak memory 247028 kb
Host smart-894669df-8ab7-491e-9663-8fe561289ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13448129439795405483594597614567613070808103084589689747902677521957313597474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.otp_ctrl_test_access.13448129439795405483594597614567613070808103084589689747902677521957313597474
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.72903029606080122516389625569795769073708079947220137018189860113579795726121
Short name T525
Test name
Test status
Simulation time 156689183 ps
CPU time 3.81 seconds
Started Nov 22 01:52:40 PM PST 23
Finished Nov 22 01:52:50 PM PST 23
Peak memory 236728 kb
Host smart-4750c128-6321-43e9-8ed8-34a74ef5ee12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72903029606080122516389625569795769073708079947220137018189860113579795726121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 210.otp_ctrl_init_fail.72903029606080122516389625569795769073708079947220137018189860113579795726121
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.52402729731532542657670080402188725227827385927364280283778842548601093840704
Short name T304
Test name
Test status
Simulation time 156689183 ps
CPU time 3.98 seconds
Started Nov 22 01:52:10 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238492 kb
Host smart-045696ed-cff3-4c6c-bc56-1bb2a39ff31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52402729731532542657670080402188725227827385927364280283778842548601093840704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 211.otp_ctrl_init_fail.52402729731532542657670080402188725227827385927364280283778842548601093840704
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.80650383975128969889997767564974969499028755070838426374547803621277344731625
Short name T455
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:52:32 PM PST 23
Finished Nov 22 01:52:39 PM PST 23
Peak memory 238688 kb
Host smart-128a90bc-5bba-4a13-aa5e-d0961d315db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80650383975128969889997767564974969499028755070838426374547803621277344731625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 212.otp_ctrl_init_fail.80650383975128969889997767564974969499028755070838426374547803621277344731625
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.67057926778220083684787906278782400118480244563948783845101099805749590840114
Short name T969
Test name
Test status
Simulation time 156689183 ps
CPU time 4.13 seconds
Started Nov 22 01:52:18 PM PST 23
Finished Nov 22 01:52:26 PM PST 23
Peak memory 238652 kb
Host smart-89d00739-93a7-42d6-9186-62da963b6d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67057926778220083684787906278782400118480244563948783845101099805749590840114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 213.otp_ctrl_init_fail.67057926778220083684787906278782400118480244563948783845101099805749590840114
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.51403310956618976349782693914573892395709006807623600076407329699014611348541
Short name T532
Test name
Test status
Simulation time 156689183 ps
CPU time 3.94 seconds
Started Nov 22 01:52:32 PM PST 23
Finished Nov 22 01:52:39 PM PST 23
Peak memory 238476 kb
Host smart-3d114b8e-8820-4340-a114-09d09c0d6b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51403310956618976349782693914573892395709006807623600076407329699014611348541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 214.otp_ctrl_init_fail.51403310956618976349782693914573892395709006807623600076407329699014611348541
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.112025925218370408295211532052916427133644241988258326459707983736073297360687
Short name T397
Test name
Test status
Simulation time 156689183 ps
CPU time 3.89 seconds
Started Nov 22 01:52:08 PM PST 23
Finished Nov 22 01:52:16 PM PST 23
Peak memory 238480 kb
Host smart-70d4e8e3-331d-4a73-a93d-38c9e1513a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112025925218370408295211532052916427133644241988258326459707983736073297360687 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 215.otp_ctrl_init_fail.112025925218370408295211532052916427133644241988258326459707983736073297360687
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.62277870055262434524523436400470519366114142464264686564043503499357281428766
Short name T551
Test name
Test status
Simulation time 156689183 ps
CPU time 4.1 seconds
Started Nov 22 01:52:04 PM PST 23
Finished Nov 22 01:52:10 PM PST 23
Peak memory 238652 kb
Host smart-eede5546-2536-4be4-b2a0-049fa2ba5c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62277870055262434524523436400470519366114142464264686564043503499357281428766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 216.otp_ctrl_init_fail.62277870055262434524523436400470519366114142464264686564043503499357281428766
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.51210840528590724067414159456582034591951308064979621932771603645968020803999
Short name T590
Test name
Test status
Simulation time 156689183 ps
CPU time 3.94 seconds
Started Nov 22 01:52:31 PM PST 23
Finished Nov 22 01:52:38 PM PST 23
Peak memory 238484 kb
Host smart-78089ff8-2b05-496f-b634-fead9bd21b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51210840528590724067414159456582034591951308064979621932771603645968020803999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 217.otp_ctrl_init_fail.51210840528590724067414159456582034591951308064979621932771603645968020803999
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.76637665705618365213197975004143298035339458591000068795864934564359217850002
Short name T999
Test name
Test status
Simulation time 156689183 ps
CPU time 4.11 seconds
Started Nov 22 01:52:11 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238624 kb
Host smart-d056cc79-3ffb-49d6-9219-0ca982be6605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76637665705618365213197975004143298035339458591000068795864934564359217850002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 218.otp_ctrl_init_fail.76637665705618365213197975004143298035339458591000068795864934564359217850002
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.88930254257113604648997863715747677108993476421852922794732868886881477678648
Short name T951
Test name
Test status
Simulation time 156689183 ps
CPU time 3.84 seconds
Started Nov 22 01:52:14 PM PST 23
Finished Nov 22 01:52:20 PM PST 23
Peak memory 238476 kb
Host smart-83ebf207-b22b-47bb-9e54-2832223b196d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88930254257113604648997863715747677108993476421852922794732868886881477678648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 219.otp_ctrl_init_fail.88930254257113604648997863715747677108993476421852922794732868886881477678648
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.32471327063707590347179422712441538256609177507266555788123657355745773370082
Short name T846
Test name
Test status
Simulation time 71069183 ps
CPU time 1.79 seconds
Started Nov 22 01:51:19 PM PST 23
Finished Nov 22 01:51:24 PM PST 23
Peak memory 238372 kb
Host smart-226886c0-d962-47fd-bdad-3609c9f7313a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32471327063707590347179422712441538256609177507266555788123657355745773370082 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.32471327063707590347179422712441538256609177507266555788123657355745773370082
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.66666541179395669182657718944146358178508780378187925814586744118305981524492
Short name T977
Test name
Test status
Simulation time 111269183 ps
CPU time 2.7 seconds
Started Nov 22 01:50:47 PM PST 23
Finished Nov 22 01:50:50 PM PST 23
Peak memory 246792 kb
Host smart-7a3cc428-8bbd-4b39-ac44-23521cc5fee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66666541179395669182657718944146358178508780378187925814586744118305981524492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.otp_ctrl_check_fail.66666541179395669182657718944146358178508780378187925814586744118305981524492
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.71676168230644220501486951825661589549635748264339562905734404977265782120194
Short name T656
Test name
Test status
Simulation time 390019183 ps
CPU time 10.87 seconds
Started Nov 22 01:51:00 PM PST 23
Finished Nov 22 01:51:12 PM PST 23
Peak memory 238668 kb
Host smart-19aa1e33-5aef-47eb-885c-a60218066a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71676168230644220501486951825661589549635748264339562905734404977265782120194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.otp_ctrl_dai_errs.71676168230644220501486951825661589549635748264339562905734404977265782120194
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.84518696361058509535375506415996567574264540551200260149057393750345016004835
Short name T349
Test name
Test status
Simulation time 614979183 ps
CPU time 10.28 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 01:51:15 PM PST 23
Peak memory 238804 kb
Host smart-15739926-c135-4e4d-a1b9-073e4048125f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84518696361058509535375506415996567574264540551200260149057393750345016004835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.otp_ctrl_dai_lock.84518696361058509535375506415996567574264540551200260149057393750345016004835
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.113232047975120773746167053993740521607962487166624064638314073381044385753779
Short name T767
Test name
Test status
Simulation time 156689183 ps
CPU time 3.86 seconds
Started Nov 22 01:51:02 PM PST 23
Finished Nov 22 01:51:08 PM PST 23
Peak memory 238588 kb
Host smart-8182f4f9-3125-4ddd-9df8-273002456c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113232047975120773746167053993740521607962487166624064638314073381044385753779 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.otp_ctrl_init_fail.113232047975120773746167053993740521607962487166624064638314073381044385753779
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.21050488760525194219620988224894249030130226100578076554966040452684232557861
Short name T1290
Test name
Test status
Simulation time 1137629183 ps
CPU time 18.95 seconds
Started Nov 22 01:51:07 PM PST 23
Finished Nov 22 01:51:28 PM PST 23
Peak memory 238944 kb
Host smart-a4bda1ed-f6a2-4dd1-a5da-9b8df78d5122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21050488760525194219620988224894249030130226100578076554966040452684232557861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.otp_ctrl_macro_errs.21050488760525194219620988224894249030130226100578076554966040452684232557861
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.6950373591171816725528732905256298797683735871476971822835919726769688236545
Short name T285
Test name
Test status
Simulation time 346349183 ps
CPU time 7.62 seconds
Started Nov 22 01:50:24 PM PST 23
Finished Nov 22 01:50:33 PM PST 23
Peak memory 238792 kb
Host smart-34632c2f-271c-46c3-bf3b-63e13806e0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6950373591171816725528732905256298797683735871476971822835919726769688236545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 22.otp_ctrl_parallel_key_req.6950373591171816725528732905256298797683735871476971822835919726769688236545
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.39225391164568294206883898592886224473287508039532832882454437201092095474370
Short name T526
Test name
Test status
Simulation time 176929183 ps
CPU time 4.6 seconds
Started Nov 22 01:50:43 PM PST 23
Finished Nov 22 01:50:48 PM PST 23
Peak memory 238684 kb
Host smart-2372fbb5-a102-4363-88d3-02dfdba979f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39225391164568294206883898592886224473287508039532832882454437201092095474370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.39225391164568294206883898592886224473287508039532832882454437201092095474370
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.54166815758239843287169109147457737627348965703552755088414541106494195612718
Short name T300
Test name
Test status
Simulation time 486419183 ps
CPU time 11.85 seconds
Started Nov 22 01:50:51 PM PST 23
Finished Nov 22 01:51:04 PM PST 23
Peak memory 238708 kb
Host smart-e25d4fa8-ec4d-4f4d-acb4-2c3b06dd6acf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54166815758239843287169109147457737627348965703552755088414541106494195612718 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.54166815758239843287169109147457737627348965703552755088414541106494195612718
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.79824716847178823895276299123464769130443882342026609741403303920437449278160
Short name T1019
Test name
Test status
Simulation time 137469183 ps
CPU time 3.65 seconds
Started Nov 22 01:50:42 PM PST 23
Finished Nov 22 01:50:46 PM PST 23
Peak memory 238640 kb
Host smart-56e1fbe3-769b-4e30-a3cf-c3bb096c7956
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=79824716847178823895276299123464769130443882342026609741403303920437449278160 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.otp_ctrl_regwen.79824716847178823895276299123464769130443882342026609741403303920437449278160
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.47314531755919738382155169457001871457201886312157611527994146306692266694482
Short name T53
Test name
Test status
Simulation time 138839183 ps
CPU time 3.12 seconds
Started Nov 22 01:50:44 PM PST 23
Finished Nov 22 01:50:48 PM PST 23
Peak memory 238808 kb
Host smart-b7c03d45-5fdc-4f2b-b862-f3f6c55ba5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47314531755919738382155169457001871457201886312157611527994146306692266694482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.otp_ctrl_smoke.47314531755919738382155169457001871457201886312157611527994146306692266694482
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.42831718567111606980261113373164745240054821887972175130358430469245066323542
Short name T1219
Test name
Test status
Simulation time 13240088340 ps
CPU time 131.2 seconds
Started Nov 22 01:51:27 PM PST 23
Finished Nov 22 01:53:40 PM PST 23
Peak memory 241800 kb
Host smart-bd1be8b9-1581-494c-98e9-48946e8c35ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42831718567111606980261113373164745240054821887972175130358430469245066323542 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.42831718567111606980261113373164745240054821887972175130358430469245066323542
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.45020594805871904049049882773599558995826691205898185586872734695621569856030
Short name T630
Test name
Test status
Simulation time 150268849183 ps
CPU time 1926.84 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 02:23:12 PM PST 23
Peak memory 517516 kb
Host smart-ceaa21a8-a4d6-4cb2-8fe0-34082cde434e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4502059480587190404904
9882773599558995826691205898185586872734695621569856030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_res
et.45020594805871904049049882773599558995826691205898185586872734695621569856030
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.91327531699871076997609140779754638630167781243509325211312291492862924072152
Short name T1285
Test name
Test status
Simulation time 549639183 ps
CPU time 8.75 seconds
Started Nov 22 01:50:50 PM PST 23
Finished Nov 22 01:51:00 PM PST 23
Peak memory 246980 kb
Host smart-fcc4496e-4635-4f43-8924-1cb66678ccd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91327531699871076997609140779754638630167781243509325211312291492862924072152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.otp_ctrl_test_access.91327531699871076997609140779754638630167781243509325211312291492862924072152
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.63728269503541330857957000743041283074817117738844755990349816582808663639516
Short name T1270
Test name
Test status
Simulation time 156689183 ps
CPU time 4.1 seconds
Started Nov 22 01:52:08 PM PST 23
Finished Nov 22 01:52:16 PM PST 23
Peak memory 238492 kb
Host smart-a6a28433-eb39-4064-bc83-977c8d409ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63728269503541330857957000743041283074817117738844755990349816582808663639516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 220.otp_ctrl_init_fail.63728269503541330857957000743041283074817117738844755990349816582808663639516
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.30229360008000754229939844567464408291951806137178777778574307006746322178064
Short name T497
Test name
Test status
Simulation time 156689183 ps
CPU time 3.87 seconds
Started Nov 22 01:52:09 PM PST 23
Finished Nov 22 01:52:16 PM PST 23
Peak memory 238492 kb
Host smart-a5d4042d-2418-46ab-9018-e9a168ccfe76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30229360008000754229939844567464408291951806137178777778574307006746322178064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 221.otp_ctrl_init_fail.30229360008000754229939844567464408291951806137178777778574307006746322178064
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.88797303044622255873584978385942204741977557359418040076699989396384330475547
Short name T62
Test name
Test status
Simulation time 156689183 ps
CPU time 3.96 seconds
Started Nov 22 01:52:14 PM PST 23
Finished Nov 22 01:52:20 PM PST 23
Peak memory 238492 kb
Host smart-a435a7fd-6c77-433d-90ed-e8d0728881eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88797303044622255873584978385942204741977557359418040076699989396384330475547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 222.otp_ctrl_init_fail.88797303044622255873584978385942204741977557359418040076699989396384330475547
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.69933050695107188950289209400391607877028404876123217822552561311755537373995
Short name T614
Test name
Test status
Simulation time 156689183 ps
CPU time 3.82 seconds
Started Nov 22 01:52:09 PM PST 23
Finished Nov 22 01:52:17 PM PST 23
Peak memory 238560 kb
Host smart-fa44ac17-bfc7-4bf6-8bda-5e630841a4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69933050695107188950289209400391607877028404876123217822552561311755537373995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 223.otp_ctrl_init_fail.69933050695107188950289209400391607877028404876123217822552561311755537373995
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.114114328275494917853941574537800843016856229093058722669288525583972732970300
Short name T542
Test name
Test status
Simulation time 156689183 ps
CPU time 4.02 seconds
Started Nov 22 01:52:46 PM PST 23
Finished Nov 22 01:52:54 PM PST 23
Peak memory 238224 kb
Host smart-345033c0-69a3-4867-b54d-b4e7fc573de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114114328275494917853941574537800843016856229093058722669288525583972732970300 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 224.otp_ctrl_init_fail.114114328275494917853941574537800843016856229093058722669288525583972732970300
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.82809880291429001290600864220803430368435406231817379935804376072707667643179
Short name T634
Test name
Test status
Simulation time 156689183 ps
CPU time 3.98 seconds
Started Nov 22 01:52:25 PM PST 23
Finished Nov 22 01:52:34 PM PST 23
Peak memory 238652 kb
Host smart-a93b0085-ac63-413c-be1e-2b7d8ad98f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82809880291429001290600864220803430368435406231817379935804376072707667643179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 225.otp_ctrl_init_fail.82809880291429001290600864220803430368435406231817379935804376072707667643179
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.108464073852893882743026644871805863289807003437277307682350679381911174793812
Short name T1009
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:52:47 PM PST 23
Finished Nov 22 01:52:55 PM PST 23
Peak memory 238212 kb
Host smart-11919954-6705-4cfe-b463-db2f6d3adc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108464073852893882743026644871805863289807003437277307682350679381911174793812 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 226.otp_ctrl_init_fail.108464073852893882743026644871805863289807003437277307682350679381911174793812
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.35688301505394750511399171339624214740242857604883947522352779165674535940378
Short name T850
Test name
Test status
Simulation time 156689183 ps
CPU time 3.84 seconds
Started Nov 22 01:52:16 PM PST 23
Finished Nov 22 01:52:24 PM PST 23
Peak memory 238476 kb
Host smart-9ed84051-e85f-437a-bdce-86ef16db9c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35688301505394750511399171339624214740242857604883947522352779165674535940378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 227.otp_ctrl_init_fail.35688301505394750511399171339624214740242857604883947522352779165674535940378
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.95763223793269444916686736063058380709945711948441107046477372142815827547127
Short name T360
Test name
Test status
Simulation time 156689183 ps
CPU time 3.85 seconds
Started Nov 22 01:52:44 PM PST 23
Finished Nov 22 01:52:53 PM PST 23
Peak memory 238012 kb
Host smart-abcfe298-c8e9-498b-a603-09e79df85371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95763223793269444916686736063058380709945711948441107046477372142815827547127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 228.otp_ctrl_init_fail.95763223793269444916686736063058380709945711948441107046477372142815827547127
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.104615852589142149882541961553033297810505263572630592037328429933238047746035
Short name T996
Test name
Test status
Simulation time 156689183 ps
CPU time 3.8 seconds
Started Nov 22 01:52:13 PM PST 23
Finished Nov 22 01:52:19 PM PST 23
Peak memory 238476 kb
Host smart-5044badc-b10f-46b8-b9c0-df665e5fa85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104615852589142149882541961553033297810505263572630592037328429933238047746035 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 229.otp_ctrl_init_fail.104615852589142149882541961553033297810505263572630592037328429933238047746035
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.105935469800590727878304489731994542163914520385260151367589746402022009492555
Short name T966
Test name
Test status
Simulation time 71069183 ps
CPU time 1.81 seconds
Started Nov 22 01:51:31 PM PST 23
Finished Nov 22 01:51:36 PM PST 23
Peak memory 238404 kb
Host smart-9de00ba4-96c7-4ec0-a108-9b9370fdd400
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105935469800590727878304489731994542163914520385260151367589746402022009492555 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.105935469800590727878304489731994542163914520385260151367589746402022009492555
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.44074506782404142368376935188032861386491965855093043751904879096136320895962
Short name T1017
Test name
Test status
Simulation time 111269183 ps
CPU time 2.72 seconds
Started Nov 22 01:51:33 PM PST 23
Finished Nov 22 01:51:39 PM PST 23
Peak memory 246784 kb
Host smart-c5b4d351-2d33-433f-a223-1df61a84f550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44074506782404142368376935188032861386491965855093043751904879096136320895962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.otp_ctrl_check_fail.44074506782404142368376935188032861386491965855093043751904879096136320895962
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.97673289743350148359555639018362313654376307308465091467092562738668339081748
Short name T1148
Test name
Test status
Simulation time 390019183 ps
CPU time 11.19 seconds
Started Nov 22 01:51:06 PM PST 23
Finished Nov 22 01:51:20 PM PST 23
Peak memory 238636 kb
Host smart-e1b10bb6-c3be-4197-b65f-38b420a1102b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97673289743350148359555639018362313654376307308465091467092562738668339081748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.otp_ctrl_dai_errs.97673289743350148359555639018362313654376307308465091467092562738668339081748
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.29599377332950660061857928089498809421341034590535901698831653569379462770899
Short name T1063
Test name
Test status
Simulation time 614979183 ps
CPU time 10.51 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:35 PM PST 23
Peak memory 238704 kb
Host smart-75e4dd75-0a45-4415-8025-134b0a2d038a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29599377332950660061857928089498809421341034590535901698831653569379462770899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.otp_ctrl_dai_lock.29599377332950660061857928089498809421341034590535901698831653569379462770899
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.75555732871529781912558756447025249512923737614135494523578524649885095381953
Short name T1118
Test name
Test status
Simulation time 156689183 ps
CPU time 3.86 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 01:51:09 PM PST 23
Peak memory 238488 kb
Host smart-85af8ff5-ca05-45a4-9d19-a099bd1c7d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75555732871529781912558756447025249512923737614135494523578524649885095381953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.otp_ctrl_init_fail.75555732871529781912558756447025249512923737614135494523578524649885095381953
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.61994436593495912069233049510511226031759778154914009879173710731901162727148
Short name T884
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.63 seconds
Started Nov 22 01:51:18 PM PST 23
Finished Nov 22 01:51:40 PM PST 23
Peak memory 238896 kb
Host smart-7c9744be-5644-472e-90ed-b34897c94c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61994436593495912069233049510511226031759778154914009879173710731901162727148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.otp_ctrl_macro_errs.61994436593495912069233049510511226031759778154914009879173710731901162727148
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.113877902959881699498139191200968212995647567413836886807972839784443817197832
Short name T1294
Test name
Test status
Simulation time 346349183 ps
CPU time 7.51 seconds
Started Nov 22 01:51:45 PM PST 23
Finished Nov 22 01:51:56 PM PST 23
Peak memory 238784 kb
Host smart-7b7d1e39-f5a9-45db-8cf9-b0f61c037670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113877902959881699498139191200968212995647567413836886807972839784443817197832 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.113877902959881699498139191200968212995647567413836886807972839784443817197832
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.73406979248780829378999301543755261317139372425475425200531723212716340073550
Short name T225
Test name
Test status
Simulation time 176929183 ps
CPU time 4.37 seconds
Started Nov 22 01:51:07 PM PST 23
Finished Nov 22 01:51:14 PM PST 23
Peak memory 238704 kb
Host smart-9f9ffc12-878b-4b35-893c-06ba853df3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73406979248780829378999301543755261317139372425475425200531723212716340073550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.73406979248780829378999301543755261317139372425475425200531723212716340073550
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.4777524622091655863626653964172777501807179951332210991844890832444637325690
Short name T1200
Test name
Test status
Simulation time 486419183 ps
CPU time 11.74 seconds
Started Nov 22 01:51:23 PM PST 23
Finished Nov 22 01:51:38 PM PST 23
Peak memory 238456 kb
Host smart-daca90ac-e0e2-451c-bd62-cf7b2b78f71c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4777524622091655863626653964172777501807179951332210991844890832444637325690 -assert nopostproc +UVM_TEST
NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.4777524622091655863626653964172777501807179951332210991844890832444637325690
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.71144066635464392417992315779377541709471295560899100798103195416929103517563
Short name T318
Test name
Test status
Simulation time 137469183 ps
CPU time 3.67 seconds
Started Nov 22 01:51:28 PM PST 23
Finished Nov 22 01:51:34 PM PST 23
Peak memory 238716 kb
Host smart-4860cc5a-0d9f-4c1a-91dd-7bed16f21a27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71144066635464392417992315779377541709471295560899100798103195416929103517563 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.otp_ctrl_regwen.71144066635464392417992315779377541709471295560899100798103195416929103517563
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.14072080014008075445762802748012885577713564292292744045140776462625866290614
Short name T924
Test name
Test status
Simulation time 138839183 ps
CPU time 2.96 seconds
Started Nov 22 01:50:54 PM PST 23
Finished Nov 22 01:50:58 PM PST 23
Peak memory 238836 kb
Host smart-4c3e0275-ef31-455c-8dba-db8d10cd09f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14072080014008075445762802748012885577713564292292744045140776462625866290614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.otp_ctrl_smoke.14072080014008075445762802748012885577713564292292744045140776462625866290614
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.21887487460808817797148813834533761699027564771335668610192399844839965346817
Short name T399
Test name
Test status
Simulation time 13240088340 ps
CPU time 131.57 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:53:36 PM PST 23
Peak memory 241824 kb
Host smart-5770345f-3985-40ff-ad0c-c347d7534d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21887487460808817797148813834533761699027564771335668610192399844839965346817 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.21887487460808817797148813834533761699027564771335668610192399844839965346817
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.109526730873866403337965223536907766195080278433330957819530474889765587831762
Short name T519
Test name
Test status
Simulation time 150268849183 ps
CPU time 1962.38 seconds
Started Nov 22 01:51:23 PM PST 23
Finished Nov 22 02:24:12 PM PST 23
Peak memory 517576 kb
Host smart-81f07519-8990-4350-a810-98f2c0bb1ecc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095267308738664033379
65223536907766195080278433330957819530474889765587831762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_re
set.109526730873866403337965223536907766195080278433330957819530474889765587831762
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.76825459097325228832050304514377834479681095130251116811773616989199342170646
Short name T1011
Test name
Test status
Simulation time 549639183 ps
CPU time 9.14 seconds
Started Nov 22 01:51:40 PM PST 23
Finished Nov 22 01:51:54 PM PST 23
Peak memory 246972 kb
Host smart-7f1fae86-efc4-4970-ad53-82e5c4c706a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76825459097325228832050304514377834479681095130251116811773616989199342170646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.otp_ctrl_test_access.76825459097325228832050304514377834479681095130251116811773616989199342170646
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.105133042067286828579507947991397131458947493426496430807242606526022224874526
Short name T1149
Test name
Test status
Simulation time 156689183 ps
CPU time 3.8 seconds
Started Nov 22 01:52:45 PM PST 23
Finished Nov 22 01:52:53 PM PST 23
Peak memory 238024 kb
Host smart-8a19756c-5185-4075-bc83-28bec04fc621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105133042067286828579507947991397131458947493426496430807242606526022224874526 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 230.otp_ctrl_init_fail.105133042067286828579507947991397131458947493426496430807242606526022224874526
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.62077779631099503277338103028225035474271792477973813965003743330315271913858
Short name T705
Test name
Test status
Simulation time 156689183 ps
CPU time 3.75 seconds
Started Nov 22 01:52:44 PM PST 23
Finished Nov 22 01:52:52 PM PST 23
Peak memory 238012 kb
Host smart-97749a01-52a6-4eff-a3b2-1c44c2414194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62077779631099503277338103028225035474271792477973813965003743330315271913858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 231.otp_ctrl_init_fail.62077779631099503277338103028225035474271792477973813965003743330315271913858
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.18383849533055676611748290399283177946208567314280592940921902887417043545091
Short name T608
Test name
Test status
Simulation time 156689183 ps
CPU time 3.99 seconds
Started Nov 22 01:52:12 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238588 kb
Host smart-4c50f570-59ea-48bc-98db-6319b12d359e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18383849533055676611748290399283177946208567314280592940921902887417043545091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 232.otp_ctrl_init_fail.18383849533055676611748290399283177946208567314280592940921902887417043545091
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.47880405462624313910590267848762438884173307894358954928580666727481755882016
Short name T382
Test name
Test status
Simulation time 156689183 ps
CPU time 4.03 seconds
Started Nov 22 01:52:24 PM PST 23
Finished Nov 22 01:52:31 PM PST 23
Peak memory 238484 kb
Host smart-3263b011-7dd6-43b4-98eb-fffd42adce29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47880405462624313910590267848762438884173307894358954928580666727481755882016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 233.otp_ctrl_init_fail.47880405462624313910590267848762438884173307894358954928580666727481755882016
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.49585721792752048687484571811908026981791481522281030526739125819369475625670
Short name T1154
Test name
Test status
Simulation time 156689183 ps
CPU time 3.85 seconds
Started Nov 22 01:52:58 PM PST 23
Finished Nov 22 01:53:02 PM PST 23
Peak memory 238372 kb
Host smart-53fd1e87-7e38-4a17-adfd-1f2fd2e58a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49585721792752048687484571811908026981791481522281030526739125819369475625670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 234.otp_ctrl_init_fail.49585721792752048687484571811908026981791481522281030526739125819369475625670
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.15350086911852851712853520764910646131451095011055244197317868973693340126885
Short name T1306
Test name
Test status
Simulation time 156689183 ps
CPU time 3.92 seconds
Started Nov 22 01:52:04 PM PST 23
Finished Nov 22 01:52:09 PM PST 23
Peak memory 238664 kb
Host smart-daa3cfc8-10c9-4774-a0f1-96974d38f683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15350086911852851712853520764910646131451095011055244197317868973693340126885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 235.otp_ctrl_init_fail.15350086911852851712853520764910646131451095011055244197317868973693340126885
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.64933258871212927934912540148069444676174249995676059063147539560803904055322
Short name T782
Test name
Test status
Simulation time 156689183 ps
CPU time 3.76 seconds
Started Nov 22 01:52:34 PM PST 23
Finished Nov 22 01:52:43 PM PST 23
Peak memory 238384 kb
Host smart-4aad5f1f-a459-4a2b-acfa-94a755cf1a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64933258871212927934912540148069444676174249995676059063147539560803904055322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 236.otp_ctrl_init_fail.64933258871212927934912540148069444676174249995676059063147539560803904055322
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.45059278914839943767617278950891134572848442539234808838870943018062247169304
Short name T1169
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:52:47 PM PST 23
Finished Nov 22 01:52:55 PM PST 23
Peak memory 238208 kb
Host smart-4decdf8a-05f5-4a77-8198-5eb97b14f5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45059278914839943767617278950891134572848442539234808838870943018062247169304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 237.otp_ctrl_init_fail.45059278914839943767617278950891134572848442539234808838870943018062247169304
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.4236569962834739366751586965085566854249011952185532255530508053359602483657
Short name T824
Test name
Test status
Simulation time 156689183 ps
CPU time 3.79 seconds
Started Nov 22 01:52:13 PM PST 23
Finished Nov 22 01:52:19 PM PST 23
Peak memory 238456 kb
Host smart-e3e28501-f32e-4640-9348-7dbd57fd7e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236569962834739366751586965085566854249011952185532255530508053359602483657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 238.otp_ctrl_init_fail.4236569962834739366751586965085566854249011952185532255530508053359602483657
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.25736963535668079740967712848955084080125376676246224394760630406250922404447
Short name T822
Test name
Test status
Simulation time 156689183 ps
CPU time 4.06 seconds
Started Nov 22 01:52:27 PM PST 23
Finished Nov 22 01:52:47 PM PST 23
Peak memory 238484 kb
Host smart-d4831326-4e9a-4a3e-a793-023e550763a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25736963535668079740967712848955084080125376676246224394760630406250922404447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 239.otp_ctrl_init_fail.25736963535668079740967712848955084080125376676246224394760630406250922404447
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.13421564181340713062463866684359306395252010024990722359358101135921967623480
Short name T1028
Test name
Test status
Simulation time 71069183 ps
CPU time 1.86 seconds
Started Nov 22 01:50:59 PM PST 23
Finished Nov 22 01:51:02 PM PST 23
Peak memory 238392 kb
Host smart-b7df3276-4a11-440d-a071-cf373ff60576
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13421564181340713062463866684359306395252010024990722359358101135921967623480 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.13421564181340713062463866684359306395252010024990722359358101135921967623480
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.95317078960083639969998304427512101505509347952783050880385469005863312702737
Short name T650
Test name
Test status
Simulation time 111269183 ps
CPU time 2.78 seconds
Started Nov 22 01:51:25 PM PST 23
Finished Nov 22 01:51:31 PM PST 23
Peak memory 246788 kb
Host smart-5e8cc189-6589-4387-96bd-73e72c3c01ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95317078960083639969998304427512101505509347952783050880385469005863312702737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.otp_ctrl_check_fail.95317078960083639969998304427512101505509347952783050880385469005863312702737
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.106400967177018244221813119787665044285062710879185329658844661795437968857750
Short name T467
Test name
Test status
Simulation time 390019183 ps
CPU time 11 seconds
Started Nov 22 01:51:37 PM PST 23
Finished Nov 22 01:51:53 PM PST 23
Peak memory 238628 kb
Host smart-53ffda48-9234-4312-b7c6-a271083ac27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106400967177018244221813119787665044285062710879185329658844661795437968857750 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.otp_ctrl_dai_errs.106400967177018244221813119787665044285062710879185329658844661795437968857750
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.37673619968811138468625102589460963445872526215038656892557078888759149015803
Short name T785
Test name
Test status
Simulation time 614979183 ps
CPU time 10.52 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:35 PM PST 23
Peak memory 238812 kb
Host smart-651d0196-e5a2-4b54-b1da-5270d9c35809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37673619968811138468625102589460963445872526215038656892557078888759149015803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.otp_ctrl_dai_lock.37673619968811138468625102589460963445872526215038656892557078888759149015803
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.26492594970024486702221371950436980695866143583638323928210198461233615646528
Short name T1006
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:51:41 PM PST 23
Finished Nov 22 01:51:50 PM PST 23
Peak memory 238608 kb
Host smart-49168ee3-f5d1-45bc-a997-8cb810a32dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26492594970024486702221371950436980695866143583638323928210198461233615646528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.otp_ctrl_init_fail.26492594970024486702221371950436980695866143583638323928210198461233615646528
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.109787444459523583979125952010421349241924866116973203452201950556582345074327
Short name T1305
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.64 seconds
Started Nov 22 01:51:20 PM PST 23
Finished Nov 22 01:51:42 PM PST 23
Peak memory 239036 kb
Host smart-dcf00090-6152-4708-8f25-9d164a465c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109787444459523583979125952010421349241924866116973203452201950556582345074327 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.otp_ctrl_macro_errs.109787444459523583979125952010421349241924866116973203452201950556582345074327
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.55088667444178311850939382046127697175600483641139389470392372951323385104212
Short name T1208
Test name
Test status
Simulation time 346349183 ps
CPU time 7.19 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 01:51:11 PM PST 23
Peak memory 238752 kb
Host smart-0bb480d3-a449-4aa7-86f5-e705c5ad6ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55088667444178311850939382046127697175600483641139389470392372951323385104212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.otp_ctrl_parallel_key_req.55088667444178311850939382046127697175600483641139389470392372951323385104212
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.92551602577897360783432036129805338481766301857479717328690199846907981790000
Short name T954
Test name
Test status
Simulation time 176929183 ps
CPU time 4.5 seconds
Started Nov 22 01:51:50 PM PST 23
Finished Nov 22 01:51:56 PM PST 23
Peak memory 238648 kb
Host smart-0ea28715-c7dd-4ecc-875c-86031e81eb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92551602577897360783432036129805338481766301857479717328690199846907981790000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.92551602577897360783432036129805338481766301857479717328690199846907981790000
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.21654722631690752265187281946549539219541710889072129059268340328407247012256
Short name T529
Test name
Test status
Simulation time 486419183 ps
CPU time 11.84 seconds
Started Nov 22 01:51:51 PM PST 23
Finished Nov 22 01:52:04 PM PST 23
Peak memory 238680 kb
Host smart-53cb1fe1-9242-4112-b08b-fdffdc6b4bc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21654722631690752265187281946549539219541710889072129059268340328407247012256 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.21654722631690752265187281946549539219541710889072129059268340328407247012256
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.38697372242437044452856470787710144908166265500226106816701217710999519869596
Short name T266
Test name
Test status
Simulation time 137469183 ps
CPU time 3.68 seconds
Started Nov 22 01:50:55 PM PST 23
Finished Nov 22 01:51:00 PM PST 23
Peak memory 238696 kb
Host smart-3b93b347-5083-40ab-9dfc-d992f6d9ed82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38697372242437044452856470787710144908166265500226106816701217710999519869596 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.otp_ctrl_regwen.38697372242437044452856470787710144908166265500226106816701217710999519869596
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.111499452916065878121080848447624648631197035325978472882086803691143158853626
Short name T1307
Test name
Test status
Simulation time 138839183 ps
CPU time 3.24 seconds
Started Nov 22 01:51:33 PM PST 23
Finished Nov 22 01:51:40 PM PST 23
Peak memory 238784 kb
Host smart-07e6e182-590f-4148-8225-d2ecc8f99a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111499452916065878121080848447624648631197035325978472882086803691143158853626 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.otp_ctrl_smoke.111499452916065878121080848447624648631197035325978472882086803691143158853626
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.92304989694830455436788177439282316260028534202051608882680772206271533806976
Short name T1191
Test name
Test status
Simulation time 13240088340 ps
CPU time 133.3 seconds
Started Nov 22 01:51:13 PM PST 23
Finished Nov 22 01:53:29 PM PST 23
Peak memory 241776 kb
Host smart-4d712de7-b07c-4cee-98ce-dce583b8cb1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92304989694830455436788177439282316260028534202051608882680772206271533806976 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.92304989694830455436788177439282316260028534202051608882680772206271533806976
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.111816982687909351117942147414861782281357374547093328121611916471882164218212
Short name T555
Test name
Test status
Simulation time 150268849183 ps
CPU time 1940.45 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 02:23:26 PM PST 23
Peak memory 517568 kb
Host smart-8a96acff-125b-49a4-9491-b0fccadb6056
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118169826879093511179
42147414861782281357374547093328121611916471882164218212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_re
set.111816982687909351117942147414861782281357374547093328121611916471882164218212
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.92170929173145258138925168401072986937436172310696462534818145956856034309070
Short name T678
Test name
Test status
Simulation time 549639183 ps
CPU time 8.63 seconds
Started Nov 22 01:50:53 PM PST 23
Finished Nov 22 01:51:02 PM PST 23
Peak memory 247020 kb
Host smart-50bcf1ff-2960-4d53-93ff-57a9ae0588aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92170929173145258138925168401072986937436172310696462534818145956856034309070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.otp_ctrl_test_access.92170929173145258138925168401072986937436172310696462534818145956856034309070
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.89959455071455676757064154594606105495142499898192010530207946644191365412802
Short name T962
Test name
Test status
Simulation time 156689183 ps
CPU time 3.71 seconds
Started Nov 22 01:52:12 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238476 kb
Host smart-b2000962-be16-4332-9e3d-19c9802d7d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89959455071455676757064154594606105495142499898192010530207946644191365412802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 240.otp_ctrl_init_fail.89959455071455676757064154594606105495142499898192010530207946644191365412802
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.73782323324278606015992464133036224880208662800380599674957979464695147640482
Short name T918
Test name
Test status
Simulation time 156689183 ps
CPU time 4.11 seconds
Started Nov 22 01:52:14 PM PST 23
Finished Nov 22 01:52:21 PM PST 23
Peak memory 238648 kb
Host smart-e7a8feef-b071-4af5-8e2a-8976e73b6572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73782323324278606015992464133036224880208662800380599674957979464695147640482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 241.otp_ctrl_init_fail.73782323324278606015992464133036224880208662800380599674957979464695147640482
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.50713299471912646233106122523589296164675340882317614063980952677080730752260
Short name T750
Test name
Test status
Simulation time 156689183 ps
CPU time 4.11 seconds
Started Nov 22 01:52:12 PM PST 23
Finished Nov 22 01:52:19 PM PST 23
Peak memory 238632 kb
Host smart-15514858-5710-44e1-8a8f-fc9a4c5efcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50713299471912646233106122523589296164675340882317614063980952677080730752260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 242.otp_ctrl_init_fail.50713299471912646233106122523589296164675340882317614063980952677080730752260
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.72239112612855987105379435941048679743446560066200200393501867752323180630429
Short name T729
Test name
Test status
Simulation time 156689183 ps
CPU time 3.98 seconds
Started Nov 22 01:52:06 PM PST 23
Finished Nov 22 01:52:13 PM PST 23
Peak memory 238616 kb
Host smart-9d0cd643-3064-4607-a6ca-472273f1f829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72239112612855987105379435941048679743446560066200200393501867752323180630429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 243.otp_ctrl_init_fail.72239112612855987105379435941048679743446560066200200393501867752323180630429
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.740984004902187235784567743241054886767792194019163478770733435773458529689
Short name T832
Test name
Test status
Simulation time 156689183 ps
CPU time 3.74 seconds
Started Nov 22 01:52:33 PM PST 23
Finished Nov 22 01:52:39 PM PST 23
Peak memory 238388 kb
Host smart-d086673c-48c7-4e34-9c10-c624e9973d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740984004902187235784567743241054886767792194019163478770733435773458529689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_ba
se_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 244.otp_ctrl_init_fail.740984004902187235784567743241054886767792194019163478770733435773458529689
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.3191125425466750746002369494896692663014621672348409284826366018778634108982
Short name T366
Test name
Test status
Simulation time 156689183 ps
CPU time 4.01 seconds
Started Nov 22 01:52:08 PM PST 23
Finished Nov 22 01:52:16 PM PST 23
Peak memory 238604 kb
Host smart-a0b85a8a-6b85-4c55-9d87-5baa353f52df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191125425466750746002369494896692663014621672348409284826366018778634108982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 245.otp_ctrl_init_fail.3191125425466750746002369494896692663014621672348409284826366018778634108982
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.29010960853118435622864021548010426586002044624177254348903840722377947014145
Short name T377
Test name
Test status
Simulation time 156689183 ps
CPU time 3.99 seconds
Started Nov 22 01:52:47 PM PST 23
Finished Nov 22 01:52:55 PM PST 23
Peak memory 238384 kb
Host smart-5e8a69a8-2e40-4360-9ec0-463653bc4e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29010960853118435622864021548010426586002044624177254348903840722377947014145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 246.otp_ctrl_init_fail.29010960853118435622864021548010426586002044624177254348903840722377947014145
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.109027739178390104107331397285597222609071770682619589619973621620601879497216
Short name T443
Test name
Test status
Simulation time 156689183 ps
CPU time 4.02 seconds
Started Nov 22 01:52:30 PM PST 23
Finished Nov 22 01:52:38 PM PST 23
Peak memory 238660 kb
Host smart-6dc6257a-bf6d-4d83-b89a-8e401e14a1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109027739178390104107331397285597222609071770682619589619973621620601879497216 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 247.otp_ctrl_init_fail.109027739178390104107331397285597222609071770682619589619973621620601879497216
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.20839976791486263471392581021560311200255714849657552831780739007900149922641
Short name T1062
Test name
Test status
Simulation time 156689183 ps
CPU time 4.09 seconds
Started Nov 22 01:52:13 PM PST 23
Finished Nov 22 01:52:20 PM PST 23
Peak memory 238528 kb
Host smart-8ec9f306-5395-4e37-affa-1a5dcd286938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20839976791486263471392581021560311200255714849657552831780739007900149922641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 248.otp_ctrl_init_fail.20839976791486263471392581021560311200255714849657552831780739007900149922641
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.64995652962712475825533187856608115554261519301986938205395969380884469340854
Short name T589
Test name
Test status
Simulation time 156689183 ps
CPU time 3.93 seconds
Started Nov 22 01:52:46 PM PST 23
Finished Nov 22 01:52:54 PM PST 23
Peak memory 238384 kb
Host smart-e71ac24b-f339-4b66-a51c-5ee11ff99685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64995652962712475825533187856608115554261519301986938205395969380884469340854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 249.otp_ctrl_init_fail.64995652962712475825533187856608115554261519301986938205395969380884469340854
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.26747937268111477781319875232087666570463385424438250959268889218333587636962
Short name T1178
Test name
Test status
Simulation time 71069183 ps
CPU time 1.83 seconds
Started Nov 22 01:51:35 PM PST 23
Finished Nov 22 01:51:41 PM PST 23
Peak memory 238460 kb
Host smart-f605d366-ff0b-45e5-9aba-5e747c65d6b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26747937268111477781319875232087666570463385424438250959268889218333587636962 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.26747937268111477781319875232087666570463385424438250959268889218333587636962
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.73205667327241633039709152268918512859882774654664975740403225080406993713615
Short name T747
Test name
Test status
Simulation time 111269183 ps
CPU time 2.67 seconds
Started Nov 22 01:51:09 PM PST 23
Finished Nov 22 01:51:13 PM PST 23
Peak memory 246724 kb
Host smart-8dc416ba-0ee9-408a-bea3-d715f1f39e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73205667327241633039709152268918512859882774654664975740403225080406993713615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.otp_ctrl_check_fail.73205667327241633039709152268918512859882774654664975740403225080406993713615
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.114109571795173205294189122876835848357309255352174733534573724249517145761146
Short name T1142
Test name
Test status
Simulation time 390019183 ps
CPU time 10.88 seconds
Started Nov 22 01:51:00 PM PST 23
Finished Nov 22 01:51:11 PM PST 23
Peak memory 238520 kb
Host smart-ab47fc2c-ecd8-44ec-8e40-ad102f29eae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114109571795173205294189122876835848357309255352174733534573724249517145761146 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.otp_ctrl_dai_errs.114109571795173205294189122876835848357309255352174733534573724249517145761146
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.51455611199430273032165258516599240308625750114818860485496469972175705365925
Short name T522
Test name
Test status
Simulation time 614979183 ps
CPU time 10.72 seconds
Started Nov 22 01:50:43 PM PST 23
Finished Nov 22 01:50:54 PM PST 23
Peak memory 238772 kb
Host smart-66e55b36-65d5-4499-aa11-44a27e54053d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51455611199430273032165258516599240308625750114818860485496469972175705365925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.otp_ctrl_dai_lock.51455611199430273032165258516599240308625750114818860485496469972175705365925
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.27083329160016454843443183246997578893478062362679048989997786162142145388330
Short name T63
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:50:54 PM PST 23
Finished Nov 22 01:50:58 PM PST 23
Peak memory 238656 kb
Host smart-5ac36366-df6b-4e12-bcd2-03edc959e9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27083329160016454843443183246997578893478062362679048989997786162142145388330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.otp_ctrl_init_fail.27083329160016454843443183246997578893478062362679048989997786162142145388330
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.58822571040090315176878558127541007992446701854165486952400265486832708076026
Short name T1126
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.38 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 01:51:24 PM PST 23
Peak memory 239008 kb
Host smart-0450e06e-efa0-4db7-bc37-3464bf4aec61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58822571040090315176878558127541007992446701854165486952400265486832708076026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.otp_ctrl_macro_errs.58822571040090315176878558127541007992446701854165486952400265486832708076026
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.97562380067222486189346487097461271126953487898596807571007373411018635619933
Short name T308
Test name
Test status
Simulation time 346349183 ps
CPU time 7.18 seconds
Started Nov 22 01:51:19 PM PST 23
Finished Nov 22 01:51:29 PM PST 23
Peak memory 238696 kb
Host smart-aed433db-78e4-449c-8b14-72148bbcef11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97562380067222486189346487097461271126953487898596807571007373411018635619933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.otp_ctrl_parallel_key_req.97562380067222486189346487097461271126953487898596807571007373411018635619933
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.92992021311283726401322296695515983315704348958684258711738436810225674427001
Short name T1036
Test name
Test status
Simulation time 176929183 ps
CPU time 4.29 seconds
Started Nov 22 01:51:01 PM PST 23
Finished Nov 22 01:51:06 PM PST 23
Peak memory 238788 kb
Host smart-51328820-caea-4b96-b6e4-40200e8b3639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92992021311283726401322296695515983315704348958684258711738436810225674427001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.92992021311283726401322296695515983315704348958684258711738436810225674427001
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.81530396152305092861161612174901525363964639553654714708941917041228775198722
Short name T1248
Test name
Test status
Simulation time 486419183 ps
CPU time 11.81 seconds
Started Nov 22 01:51:26 PM PST 23
Finished Nov 22 01:51:41 PM PST 23
Peak memory 238676 kb
Host smart-5f6b634a-8d96-449a-9318-998faebf1eb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81530396152305092861161612174901525363964639553654714708941917041228775198722 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.81530396152305092861161612174901525363964639553654714708941917041228775198722
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.110743850496053114343171471276854747735138500556710515678254240777095092163287
Short name T447
Test name
Test status
Simulation time 137469183 ps
CPU time 3.49 seconds
Started Nov 22 01:51:18 PM PST 23
Finished Nov 22 01:51:24 PM PST 23
Peak memory 238716 kb
Host smart-a5fd9491-e72f-4bca-bc70-e77ca60aba7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=110743850496053114343171471276854747735138500556710515678254240777095092163287 -assert nopostproc +UVM_TE
STNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.otp_ctrl_regwen.110743850496053114343171471276854747735138500556710515678254240777095092163287
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.59776498030445752937113055493022247619476126409153002745541308647000191678075
Short name T917
Test name
Test status
Simulation time 138839183 ps
CPU time 3.07 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 01:51:07 PM PST 23
Peak memory 238792 kb
Host smart-09aca271-b03f-4085-8c37-ac4a47814dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59776498030445752937113055493022247619476126409153002745541308647000191678075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.otp_ctrl_smoke.59776498030445752937113055493022247619476126409153002745541308647000191678075
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.110023864003574902219623271382823716225043437522091613477178258460609861245805
Short name T778
Test name
Test status
Simulation time 13240088340 ps
CPU time 132.22 seconds
Started Nov 22 01:51:18 PM PST 23
Finished Nov 22 01:53:33 PM PST 23
Peak memory 241812 kb
Host smart-cc6bf682-949d-42f0-8013-d6a53978bdc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110023864003574902219623271382823716225043437522091613477178258460609861245805 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.110023864003574902219623271382823716225043437522091613477178258460609861245805
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.25697642780822407154392514080733979431721321922948986037279712418909856711461
Short name T1112
Test name
Test status
Simulation time 150268849183 ps
CPU time 1962.96 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 02:23:48 PM PST 23
Peak memory 517564 kb
Host smart-40feca77-50f6-4d36-b8ba-db67e0f6e2e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569764278082240715439
2514080733979431721321922948986037279712418909856711461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_res
et.25697642780822407154392514080733979431721321922948986037279712418909856711461
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.3414968973667576558702126216404992665391297210112486087355791952689744622910
Short name T395
Test name
Test status
Simulation time 549639183 ps
CPU time 9.21 seconds
Started Nov 22 01:51:15 PM PST 23
Finished Nov 22 01:51:26 PM PST 23
Peak memory 246992 kb
Host smart-bed359d8-c6cc-4b6d-81c2-0ef89cce28e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414968973667576558702126216404992665391297210112486087355791952689744622910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.otp_ctrl_test_access.3414968973667576558702126216404992665391297210112486087355791952689744622910
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.3363240378567138188861693726455215111030888325923459293704709158222556722942
Short name T1261
Test name
Test status
Simulation time 156689183 ps
CPU time 4.22 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 01:52:21 PM PST 23
Peak memory 238528 kb
Host smart-01c24cf8-5c31-4fb9-828c-7dbe84876c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363240378567138188861693726455215111030888325923459293704709158222556722942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 250.otp_ctrl_init_fail.3363240378567138188861693726455215111030888325923459293704709158222556722942
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.109777511065496761069516093259773487892360577720772695700689689846570003221542
Short name T433
Test name
Test status
Simulation time 156689183 ps
CPU time 4.08 seconds
Started Nov 22 01:52:26 PM PST 23
Finished Nov 22 01:52:37 PM PST 23
Peak memory 238648 kb
Host smart-84cfb5f2-e38b-4fcb-bc55-2810439b87bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109777511065496761069516093259773487892360577720772695700689689846570003221542 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 251.otp_ctrl_init_fail.109777511065496761069516093259773487892360577720772695700689689846570003221542
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.21218549191373595173865850873740218495290220487478871129592962478985591009079
Short name T1061
Test name
Test status
Simulation time 156689183 ps
CPU time 4.09 seconds
Started Nov 22 01:52:21 PM PST 23
Finished Nov 22 01:52:27 PM PST 23
Peak memory 238620 kb
Host smart-d5078e4e-b271-4704-9de2-a8a67f92f7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21218549191373595173865850873740218495290220487478871129592962478985591009079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 252.otp_ctrl_init_fail.21218549191373595173865850873740218495290220487478871129592962478985591009079
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.103240266844318011104333514028076449493682032492570861532768644445275792412353
Short name T860
Test name
Test status
Simulation time 156689183 ps
CPU time 4.11 seconds
Started Nov 22 01:52:19 PM PST 23
Finished Nov 22 01:52:27 PM PST 23
Peak memory 238512 kb
Host smart-8c3d116d-637c-4d35-9f0b-da07b8c8b261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103240266844318011104333514028076449493682032492570861532768644445275792412353 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 253.otp_ctrl_init_fail.103240266844318011104333514028076449493682032492570861532768644445275792412353
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.35597589106705921926661512771981138911787319821796982001688516237201335836624
Short name T816
Test name
Test status
Simulation time 156689183 ps
CPU time 4.02 seconds
Started Nov 22 01:52:13 PM PST 23
Finished Nov 22 01:52:19 PM PST 23
Peak memory 238608 kb
Host smart-cfce7550-387f-486d-a27f-6b61a1e89ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35597589106705921926661512771981138911787319821796982001688516237201335836624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 254.otp_ctrl_init_fail.35597589106705921926661512771981138911787319821796982001688516237201335836624
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.61254539394576124825450651335408606395995553839178838016144520042115094346449
Short name T449
Test name
Test status
Simulation time 156689183 ps
CPU time 3.97 seconds
Started Nov 22 01:52:19 PM PST 23
Finished Nov 22 01:52:26 PM PST 23
Peak memory 238600 kb
Host smart-95400eff-3802-4c3a-87f2-844888d027d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61254539394576124825450651335408606395995553839178838016144520042115094346449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 255.otp_ctrl_init_fail.61254539394576124825450651335408606395995553839178838016144520042115094346449
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.90874995732156170464711715363135402949442497132211902355686786696112312736848
Short name T1000
Test name
Test status
Simulation time 156689183 ps
CPU time 3.99 seconds
Started Nov 22 01:52:12 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238528 kb
Host smart-d52dcbbc-9074-4149-9503-e98f5c6b0cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90874995732156170464711715363135402949442497132211902355686786696112312736848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 256.otp_ctrl_init_fail.90874995732156170464711715363135402949442497132211902355686786696112312736848
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.95263062976302576333823873758700898370617613419382688615242462546387269111391
Short name T451
Test name
Test status
Simulation time 156689183 ps
CPU time 3.88 seconds
Started Nov 22 01:52:23 PM PST 23
Finished Nov 22 01:52:29 PM PST 23
Peak memory 238556 kb
Host smart-a7c4d21e-c9a5-400a-812a-bcdd7fbc8ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95263062976302576333823873758700898370617613419382688615242462546387269111391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 257.otp_ctrl_init_fail.95263062976302576333823873758700898370617613419382688615242462546387269111391
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.5376018223948101313665737067575803399562321675258903622892222372417812002818
Short name T741
Test name
Test status
Simulation time 156689183 ps
CPU time 4.07 seconds
Started Nov 22 01:52:22 PM PST 23
Finished Nov 22 01:52:28 PM PST 23
Peak memory 238544 kb
Host smart-81308113-ffe4-45b0-87bd-562b58089003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5376018223948101313665737067575803399562321675258903622892222372417812002818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 258.otp_ctrl_init_fail.5376018223948101313665737067575803399562321675258903622892222372417812002818
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.32236424849178096138211938149902882423423570443771768286932034643846891960881
Short name T502
Test name
Test status
Simulation time 156689183 ps
CPU time 3.92 seconds
Started Nov 22 01:52:12 PM PST 23
Finished Nov 22 01:52:19 PM PST 23
Peak memory 238528 kb
Host smart-971810ec-a135-43fd-8eb0-e86949fcd953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32236424849178096138211938149902882423423570443771768286932034643846891960881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 259.otp_ctrl_init_fail.32236424849178096138211938149902882423423570443771768286932034643846891960881
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.115497442341019938839077985761028357304289052049527365263011222309658870389562
Short name T689
Test name
Test status
Simulation time 71069183 ps
CPU time 1.84 seconds
Started Nov 22 01:50:44 PM PST 23
Finished Nov 22 01:50:46 PM PST 23
Peak memory 238448 kb
Host smart-152dad49-abca-47cb-99d2-bb7fbf094dab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115497442341019938839077985761028357304289052049527365263011222309658870389562 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.115497442341019938839077985761028357304289052049527365263011222309658870389562
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.102773227342993061243888057413621428459609774324656209550351801637404433998311
Short name T780
Test name
Test status
Simulation time 111269183 ps
CPU time 2.65 seconds
Started Nov 22 01:51:16 PM PST 23
Finished Nov 22 01:51:26 PM PST 23
Peak memory 246792 kb
Host smart-1c011ee6-0da3-43f4-aa65-dc28672753b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102773227342993061243888057413621428459609774324656209550351801637404433998311 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.otp_ctrl_check_fail.102773227342993061243888057413621428459609774324656209550351801637404433998311
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.80450273498916964765231790646907473467113236409002884828588666580773486913549
Short name T618
Test name
Test status
Simulation time 390019183 ps
CPU time 9.99 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:33 PM PST 23
Peak memory 238572 kb
Host smart-d1896dd7-6d41-4a43-88a1-556fb241e8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80450273498916964765231790646907473467113236409002884828588666580773486913549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.otp_ctrl_dai_errs.80450273498916964765231790646907473467113236409002884828588666580773486913549
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.36090966560686245910716618129401863560612965087605230774032364666351043997854
Short name T511
Test name
Test status
Simulation time 614979183 ps
CPU time 10.78 seconds
Started Nov 22 01:51:11 PM PST 23
Finished Nov 22 01:51:22 PM PST 23
Peak memory 238812 kb
Host smart-19431d71-27f1-4668-a1de-ca23e541d482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36090966560686245910716618129401863560612965087605230774032364666351043997854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.otp_ctrl_dai_lock.36090966560686245910716618129401863560612965087605230774032364666351043997854
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.109788332788404976019656808901199209850222290120394473527960446013656426975075
Short name T331
Test name
Test status
Simulation time 156689183 ps
CPU time 4.06 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:28 PM PST 23
Peak memory 238620 kb
Host smart-970a724d-88f5-41b3-8a7b-fbfe0f95c6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109788332788404976019656808901199209850222290120394473527960446013656426975075 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.otp_ctrl_init_fail.109788332788404976019656808901199209850222290120394473527960446013656426975075
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.67612978315983933908193957336778254359889363648557700580510601340802491675098
Short name T649
Test name
Test status
Simulation time 1137629183 ps
CPU time 18.22 seconds
Started Nov 22 01:51:33 PM PST 23
Finished Nov 22 01:51:54 PM PST 23
Peak memory 238972 kb
Host smart-d7b3e1ce-3675-4c8f-a74e-6f13d3524a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67612978315983933908193957336778254359889363648557700580510601340802491675098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.otp_ctrl_macro_errs.67612978315983933908193957336778254359889363648557700580510601340802491675098
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.7212509149923601180534687447753882735998035537800286468598370246561573030144
Short name T737
Test name
Test status
Simulation time 346349183 ps
CPU time 7.52 seconds
Started Nov 22 01:51:42 PM PST 23
Finished Nov 22 01:51:54 PM PST 23
Peak memory 238724 kb
Host smart-17e99d1a-bd4a-43c2-9290-f5d3b580dd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7212509149923601180534687447753882735998035537800286468598370246561573030144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 26.otp_ctrl_parallel_key_req.7212509149923601180534687447753882735998035537800286468598370246561573030144
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.61561459535134343885005321050947985823788700097693877763828260248941765459904
Short name T902
Test name
Test status
Simulation time 176929183 ps
CPU time 4.48 seconds
Started Nov 22 01:51:18 PM PST 23
Finished Nov 22 01:51:24 PM PST 23
Peak memory 238616 kb
Host smart-7b40ae37-9f98-475a-8b17-6da0d2b88eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61561459535134343885005321050947985823788700097693877763828260248941765459904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.61561459535134343885005321050947985823788700097693877763828260248941765459904
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.6824955605175487984007019352893442885616147952499618955080129078232397063132
Short name T425
Test name
Test status
Simulation time 486419183 ps
CPU time 11.98 seconds
Started Nov 22 01:51:20 PM PST 23
Finished Nov 22 01:51:34 PM PST 23
Peak memory 238732 kb
Host smart-3401d262-ce42-4f68-b51f-8531da15ceb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6824955605175487984007019352893442885616147952499618955080129078232397063132 -assert nopostproc +UVM_TEST
NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.6824955605175487984007019352893442885616147952499618955080129078232397063132
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.73621231627000904816058260183955167429815001271225559243703663713574192617147
Short name T673
Test name
Test status
Simulation time 137469183 ps
CPU time 3.67 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:51 PM PST 23
Peak memory 238640 kb
Host smart-0ee1a6b4-7e67-47be-8862-43452461b2a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73621231627000904816058260183955167429815001271225559243703663713574192617147 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.otp_ctrl_regwen.73621231627000904816058260183955167429815001271225559243703663713574192617147
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.10705767225069011943394867563564343797217562634505458086294766003230990108495
Short name T942
Test name
Test status
Simulation time 138839183 ps
CPU time 2.99 seconds
Started Nov 22 01:51:06 PM PST 23
Finished Nov 22 01:51:10 PM PST 23
Peak memory 238808 kb
Host smart-e34ed522-63b2-4935-90c3-48ce06aa0de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10705767225069011943394867563564343797217562634505458086294766003230990108495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.otp_ctrl_smoke.10705767225069011943394867563564343797217562634505458086294766003230990108495
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.106502459666364170202867506828292618905477274723482894543706163850779699423638
Short name T482
Test name
Test status
Simulation time 13240088340 ps
CPU time 128.22 seconds
Started Nov 22 01:51:11 PM PST 23
Finished Nov 22 01:53:21 PM PST 23
Peak memory 241732 kb
Host smart-3080a2d4-06b6-43bd-b65f-0c1e69cedd0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106502459666364170202867506828292618905477274723482894543706163850779699423638 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.106502459666364170202867506828292618905477274723482894543706163850779699423638
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.27895452882302070394050575619836910257280677124915229351663846762648682521750
Short name T323
Test name
Test status
Simulation time 150268849183 ps
CPU time 1948.28 seconds
Started Nov 22 01:51:42 PM PST 23
Finished Nov 22 02:24:15 PM PST 23
Peak memory 517496 kb
Host smart-ee7de480-3fb1-45d5-96ef-d9a2eaf62960
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789545288230207039405
0575619836910257280677124915229351663846762648682521750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_res
et.27895452882302070394050575619836910257280677124915229351663846762648682521750
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.95688302578858106749622538151542873387918130155247463834151955584425750824158
Short name T521
Test name
Test status
Simulation time 156689183 ps
CPU time 3.8 seconds
Started Nov 22 01:52:36 PM PST 23
Finished Nov 22 01:52:46 PM PST 23
Peak memory 238384 kb
Host smart-d2d6704e-def7-42bc-aa71-933c7f823a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95688302578858106749622538151542873387918130155247463834151955584425750824158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 260.otp_ctrl_init_fail.95688302578858106749622538151542873387918130155247463834151955584425750824158
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.26012596163752449925245829516327161574837450831516041658756112475633626031533
Short name T239
Test name
Test status
Simulation time 156689183 ps
CPU time 3.91 seconds
Started Nov 22 01:52:18 PM PST 23
Finished Nov 22 01:52:26 PM PST 23
Peak memory 238656 kb
Host smart-ec552e01-b61b-449e-b401-20192468c51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26012596163752449925245829516327161574837450831516041658756112475633626031533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 261.otp_ctrl_init_fail.26012596163752449925245829516327161574837450831516041658756112475633626031533
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.97107676139993205622616956016500616253823219820406634191944351939787873117686
Short name T513
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:52:47 PM PST 23
Finished Nov 22 01:52:55 PM PST 23
Peak memory 238384 kb
Host smart-fe999d3e-cee1-4818-b3b1-f384a745558a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97107676139993205622616956016500616253823219820406634191944351939787873117686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 262.otp_ctrl_init_fail.97107676139993205622616956016500616253823219820406634191944351939787873117686
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.1756345026857199245696196073547920895577149380512031021450966331000572968090
Short name T498
Test name
Test status
Simulation time 156689183 ps
CPU time 4.04 seconds
Started Nov 22 01:52:24 PM PST 23
Finished Nov 22 01:52:31 PM PST 23
Peak memory 238540 kb
Host smart-9ce91b39-b604-45bf-a2bf-3997cf2a8b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756345026857199245696196073547920895577149380512031021450966331000572968090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 263.otp_ctrl_init_fail.1756345026857199245696196073547920895577149380512031021450966331000572968090
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.47418616752498780133346234366864826186521323503314434558862009998957341942598
Short name T930
Test name
Test status
Simulation time 156689183 ps
CPU time 3.85 seconds
Started Nov 22 01:52:13 PM PST 23
Finished Nov 22 01:52:19 PM PST 23
Peak memory 238616 kb
Host smart-ffb62367-09a4-4936-8d2a-a9041b263754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47418616752498780133346234366864826186521323503314434558862009998957341942598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 264.otp_ctrl_init_fail.47418616752498780133346234366864826186521323503314434558862009998957341942598
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.30001802289599419536347525878421289382451858596346331364612420623904013511151
Short name T746
Test name
Test status
Simulation time 156689183 ps
CPU time 3.92 seconds
Started Nov 22 01:52:27 PM PST 23
Finished Nov 22 01:52:37 PM PST 23
Peak memory 238660 kb
Host smart-eb833bd9-c3f7-4e72-a29c-dc4f20263d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30001802289599419536347525878421289382451858596346331364612420623904013511151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 265.otp_ctrl_init_fail.30001802289599419536347525878421289382451858596346331364612420623904013511151
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.29050379874531586810465442081524563592622054497795739385424693477755149764674
Short name T685
Test name
Test status
Simulation time 156689183 ps
CPU time 4.2 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 01:52:22 PM PST 23
Peak memory 238648 kb
Host smart-2f26a861-bcf9-4a99-9c46-2bb31193c952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29050379874531586810465442081524563592622054497795739385424693477755149764674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 266.otp_ctrl_init_fail.29050379874531586810465442081524563592622054497795739385424693477755149764674
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.26290017376841484491795574732416120135827533115369367128163205434457435095237
Short name T1276
Test name
Test status
Simulation time 156689183 ps
CPU time 3.87 seconds
Started Nov 22 01:52:25 PM PST 23
Finished Nov 22 01:52:31 PM PST 23
Peak memory 238556 kb
Host smart-5fb264fe-f18b-4b4d-badf-e58334852f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26290017376841484491795574732416120135827533115369367128163205434457435095237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 267.otp_ctrl_init_fail.26290017376841484491795574732416120135827533115369367128163205434457435095237
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.53711931929002292307799590908121209397585968283621822066821673898156402996366
Short name T642
Test name
Test status
Simulation time 156689183 ps
CPU time 4.1 seconds
Started Nov 22 01:52:28 PM PST 23
Finished Nov 22 01:52:38 PM PST 23
Peak memory 238648 kb
Host smart-a6f3780f-d395-42cb-bfe2-f09e078b28a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53711931929002292307799590908121209397585968283621822066821673898156402996366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 268.otp_ctrl_init_fail.53711931929002292307799590908121209397585968283621822066821673898156402996366
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.33911427848614173616115329440895073794755164865980889627921416717071716027647
Short name T1239
Test name
Test status
Simulation time 156689183 ps
CPU time 3.96 seconds
Started Nov 22 01:52:12 PM PST 23
Finished Nov 22 01:52:19 PM PST 23
Peak memory 238616 kb
Host smart-15dd2e76-a4d1-4736-ac37-ece2d0be3617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33911427848614173616115329440895073794755164865980889627921416717071716027647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 269.otp_ctrl_init_fail.33911427848614173616115329440895073794755164865980889627921416717071716027647
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.21780022226241131622026376231390728388286810448019920100618797889483656500355
Short name T1143
Test name
Test status
Simulation time 71069183 ps
CPU time 1.89 seconds
Started Nov 22 01:51:49 PM PST 23
Finished Nov 22 01:51:53 PM PST 23
Peak memory 238468 kb
Host smart-a8b5318a-9c77-4891-86cc-e0ba264375f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21780022226241131622026376231390728388286810448019920100618797889483656500355 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.21780022226241131622026376231390728388286810448019920100618797889483656500355
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.109216417912733788626788022131912568103320147084566689843864322532288378759995
Short name T622
Test name
Test status
Simulation time 111269183 ps
CPU time 2.66 seconds
Started Nov 22 01:51:49 PM PST 23
Finished Nov 22 01:51:54 PM PST 23
Peak memory 246832 kb
Host smart-d61af3bf-a275-4ceb-bdbe-78e7b1d400f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109216417912733788626788022131912568103320147084566689843864322532288378759995 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.otp_ctrl_check_fail.109216417912733788626788022131912568103320147084566689843864322532288378759995
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.55694693671097413388808244618984460528649401150910544452313388034187397174523
Short name T1103
Test name
Test status
Simulation time 390019183 ps
CPU time 11.18 seconds
Started Nov 22 01:51:35 PM PST 23
Finished Nov 22 01:51:50 PM PST 23
Peak memory 238668 kb
Host smart-bb99ff83-4705-47e6-895b-f615c91c9ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55694693671097413388808244618984460528649401150910544452313388034187397174523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.otp_ctrl_dai_errs.55694693671097413388808244618984460528649401150910544452313388034187397174523
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.26589115783728827682655611826827666575399263359178700614760667311386765749638
Short name T43
Test name
Test status
Simulation time 614979183 ps
CPU time 10.42 seconds
Started Nov 22 01:51:31 PM PST 23
Finished Nov 22 01:51:44 PM PST 23
Peak memory 238840 kb
Host smart-f68b7c7b-3c31-48c6-96c7-a8e0230449eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26589115783728827682655611826827666575399263359178700614760667311386765749638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.otp_ctrl_dai_lock.26589115783728827682655611826827666575399263359178700614760667311386765749638
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.49925139037641796021307308619052559750035366836439356552447425003334215831282
Short name T828
Test name
Test status
Simulation time 156689183 ps
CPU time 4.12 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:28 PM PST 23
Peak memory 238612 kb
Host smart-5ecb446d-e61d-4d9e-84b7-6fbe16a0fc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49925139037641796021307308619052559750035366836439356552447425003334215831282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.otp_ctrl_init_fail.49925139037641796021307308619052559750035366836439356552447425003334215831282
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.50857919572185622727406262114680426427181734331117179804042851058017034112386
Short name T670
Test name
Test status
Simulation time 1137629183 ps
CPU time 18.33 seconds
Started Nov 22 01:51:42 PM PST 23
Finished Nov 22 01:52:05 PM PST 23
Peak memory 238848 kb
Host smart-55546397-3b8b-4c2a-bd25-5b3ad1523365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50857919572185622727406262114680426427181734331117179804042851058017034112386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.otp_ctrl_macro_errs.50857919572185622727406262114680426427181734331117179804042851058017034112386
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.46624663497363559429093440541590273907773850331731928945447437695995619343214
Short name T1108
Test name
Test status
Simulation time 346349183 ps
CPU time 7.5 seconds
Started Nov 22 01:51:32 PM PST 23
Finished Nov 22 01:51:43 PM PST 23
Peak memory 238804 kb
Host smart-5def0b09-7395-4c3f-b4ab-efeadfe36623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46624663497363559429093440541590273907773850331731928945447437695995619343214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.otp_ctrl_parallel_key_req.46624663497363559429093440541590273907773850331731928945447437695995619343214
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.111162319790221686089074809295049594229177559065810028567476430901802980297768
Short name T959
Test name
Test status
Simulation time 176929183 ps
CPU time 4.37 seconds
Started Nov 22 01:51:48 PM PST 23
Finished Nov 22 01:51:55 PM PST 23
Peak memory 238712 kb
Host smart-1f804155-854a-4c72-aaf8-66145767c1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111162319790221686089074809295049594229177559065810028567476430901802980297768 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.111162319790221686089074809295049594229177559065810028567476430901802980297768
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.46227122125471602101725566241678033141250899516349175797123414378305205846214
Short name T129
Test name
Test status
Simulation time 486419183 ps
CPU time 11.79 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:35 PM PST 23
Peak memory 238684 kb
Host smart-79e5a666-5283-424f-80f1-66da283527b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=46227122125471602101725566241678033141250899516349175797123414378305205846214 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.46227122125471602101725566241678033141250899516349175797123414378305205846214
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.18305343296283055359612825808312761893269331013208206997133952074300546791423
Short name T373
Test name
Test status
Simulation time 137469183 ps
CPU time 3.66 seconds
Started Nov 22 01:51:34 PM PST 23
Finished Nov 22 01:51:41 PM PST 23
Peak memory 238548 kb
Host smart-5f9a3bcf-fccd-4951-91dc-74e40debea26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18305343296283055359612825808312761893269331013208206997133952074300546791423 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.otp_ctrl_regwen.18305343296283055359612825808312761893269331013208206997133952074300546791423
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.50050174968571941637516188681730719509460586979679472751251148725117223529899
Short name T734
Test name
Test status
Simulation time 138839183 ps
CPU time 3.05 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:50 PM PST 23
Peak memory 238796 kb
Host smart-a66af603-47ad-4f60-aa97-3a3043ed9284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50050174968571941637516188681730719509460586979679472751251148725117223529899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.otp_ctrl_smoke.50050174968571941637516188681730719509460586979679472751251148725117223529899
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.11534448291420404176102698516536760291727930878159989713202578856515476683726
Short name T1212
Test name
Test status
Simulation time 13240088340 ps
CPU time 134.51 seconds
Started Nov 22 01:51:41 PM PST 23
Finished Nov 22 01:54:00 PM PST 23
Peak memory 241820 kb
Host smart-c97d3782-88a2-4b93-aa03-b54f10f3e2bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11534448291420404176102698516536760291727930878159989713202578856515476683726 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.11534448291420404176102698516536760291727930878159989713202578856515476683726
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.17421072116891958442484200321076241587439174559369374182506093896163434318026
Short name T392
Test name
Test status
Simulation time 150268849183 ps
CPU time 1963.35 seconds
Started Nov 22 01:51:20 PM PST 23
Finished Nov 22 02:24:06 PM PST 23
Peak memory 517500 kb
Host smart-4c974c68-4505-43aa-ac8b-ce0d2c5f6a93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742107211689195844248
4200321076241587439174559369374182506093896163434318026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_res
et.17421072116891958442484200321076241587439174559369374182506093896163434318026
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.109584063936250791997602184404212609436250177347630347578705912834169429256818
Short name T936
Test name
Test status
Simulation time 549639183 ps
CPU time 8.75 seconds
Started Nov 22 01:51:30 PM PST 23
Finished Nov 22 01:51:42 PM PST 23
Peak memory 246860 kb
Host smart-595a0cf7-2cf8-4ad8-abf5-ef617917735f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109584063936250791997602184404212609436250177347630347578705912834169429256818 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.otp_ctrl_test_access.109584063936250791997602184404212609436250177347630347578705912834169429256818
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.41439942965345664961328379551088854856851871309399130339298747177234302041710
Short name T855
Test name
Test status
Simulation time 156689183 ps
CPU time 4.08 seconds
Started Nov 22 01:52:20 PM PST 23
Finished Nov 22 01:52:27 PM PST 23
Peak memory 238600 kb
Host smart-6e8b039c-3b89-4919-93f5-7f8ca6c2bef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41439942965345664961328379551088854856851871309399130339298747177234302041710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 270.otp_ctrl_init_fail.41439942965345664961328379551088854856851871309399130339298747177234302041710
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.112400852944400343345078517697311250888487223089169598499416840698973476506180
Short name T358
Test name
Test status
Simulation time 156689183 ps
CPU time 3.85 seconds
Started Nov 22 01:52:32 PM PST 23
Finished Nov 22 01:52:48 PM PST 23
Peak memory 238656 kb
Host smart-9fbc79d2-1543-4ccb-a7af-6fa1a615f8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112400852944400343345078517697311250888487223089169598499416840698973476506180 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 271.otp_ctrl_init_fail.112400852944400343345078517697311250888487223089169598499416840698973476506180
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.65373714789437641550351680721727010202913672521887115079146263706775006129230
Short name T883
Test name
Test status
Simulation time 156689183 ps
CPU time 3.96 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 01:52:21 PM PST 23
Peak memory 238648 kb
Host smart-65f16f04-9198-42c0-985c-64677a04c3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65373714789437641550351680721727010202913672521887115079146263706775006129230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 272.otp_ctrl_init_fail.65373714789437641550351680721727010202913672521887115079146263706775006129230
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.6863664835649952898055093586184206560894646337250905148851435540257024569965
Short name T413
Test name
Test status
Simulation time 156689183 ps
CPU time 3.96 seconds
Started Nov 22 01:52:36 PM PST 23
Finished Nov 22 01:52:47 PM PST 23
Peak memory 238532 kb
Host smart-5455cdea-19fb-45cd-ae35-12aaf714c268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6863664835649952898055093586184206560894646337250905148851435540257024569965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 273.otp_ctrl_init_fail.6863664835649952898055093586184206560894646337250905148851435540257024569965
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.675115089732272479916083153415073593732087514816855535210275786571410634012
Short name T333
Test name
Test status
Simulation time 156689183 ps
CPU time 4.01 seconds
Started Nov 22 01:52:30 PM PST 23
Finished Nov 22 01:52:38 PM PST 23
Peak memory 238588 kb
Host smart-3cc81280-e881-46ec-ab83-af6421d0e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675115089732272479916083153415073593732087514816855535210275786571410634012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_ba
se_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 274.otp_ctrl_init_fail.675115089732272479916083153415073593732087514816855535210275786571410634012
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.47080505110744718993873898318724138262225019854974061735594110082245275536799
Short name T794
Test name
Test status
Simulation time 156689183 ps
CPU time 4.17 seconds
Started Nov 22 01:52:28 PM PST 23
Finished Nov 22 01:52:38 PM PST 23
Peak memory 238600 kb
Host smart-ef8202aa-7be7-4d9c-93f6-ceb28cf9a81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47080505110744718993873898318724138262225019854974061735594110082245275536799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 275.otp_ctrl_init_fail.47080505110744718993873898318724138262225019854974061735594110082245275536799
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.60097632399216504527249775162005491526285496155343625449994412504409688771525
Short name T863
Test name
Test status
Simulation time 156689183 ps
CPU time 4.31 seconds
Started Nov 22 01:52:22 PM PST 23
Finished Nov 22 01:52:28 PM PST 23
Peak memory 238656 kb
Host smart-1641c688-57ae-45c2-a7b9-516f5d6db0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60097632399216504527249775162005491526285496155343625449994412504409688771525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 276.otp_ctrl_init_fail.60097632399216504527249775162005491526285496155343625449994412504409688771525
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.112055678323130854426171172262655475276818488000569692095569846556020287671766
Short name T326
Test name
Test status
Simulation time 156689183 ps
CPU time 3.89 seconds
Started Nov 22 01:52:32 PM PST 23
Finished Nov 22 01:52:39 PM PST 23
Peak memory 238476 kb
Host smart-3c39399e-4e38-4bcc-b5f0-5f5b7703073b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112055678323130854426171172262655475276818488000569692095569846556020287671766 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 277.otp_ctrl_init_fail.112055678323130854426171172262655475276818488000569692095569846556020287671766
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.37536225491872596566907596853782339544719120853736503890172603709925394351282
Short name T380
Test name
Test status
Simulation time 156689183 ps
CPU time 3.93 seconds
Started Nov 22 01:52:07 PM PST 23
Finished Nov 22 01:52:15 PM PST 23
Peak memory 238644 kb
Host smart-754dcfdd-fb7d-4e2e-907f-de0d85c8e5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37536225491872596566907596853782339544719120853736503890172603709925394351282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 278.otp_ctrl_init_fail.37536225491872596566907596853782339544719120853736503890172603709925394351282
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.14527810726002612180291952002532099713435727586866172066764989853053918261646
Short name T755
Test name
Test status
Simulation time 156689183 ps
CPU time 3.8 seconds
Started Nov 22 01:52:38 PM PST 23
Finished Nov 22 01:52:48 PM PST 23
Peak memory 238384 kb
Host smart-6a0fc7f4-bbf8-4078-845f-bdcea55f874c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14527810726002612180291952002532099713435727586866172066764989853053918261646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 279.otp_ctrl_init_fail.14527810726002612180291952002532099713435727586866172066764989853053918261646
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.15669130524482440355278839357266075699824657233860350091207900953716313919766
Short name T278
Test name
Test status
Simulation time 71069183 ps
CPU time 1.8 seconds
Started Nov 22 01:51:04 PM PST 23
Finished Nov 22 01:51:08 PM PST 23
Peak memory 238416 kb
Host smart-5c672840-9e33-49f0-b596-adf2c1cbcc7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15669130524482440355278839357266075699824657233860350091207900953716313919766 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.15669130524482440355278839357266075699824657233860350091207900953716313919766
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.46427029311411039483183536549805355686244076830732472554046877841089714303266
Short name T554
Test name
Test status
Simulation time 111269183 ps
CPU time 2.72 seconds
Started Nov 22 01:50:57 PM PST 23
Finished Nov 22 01:51:01 PM PST 23
Peak memory 246776 kb
Host smart-74440aa7-7d19-4b89-a501-cb732dd12f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46427029311411039483183536549805355686244076830732472554046877841089714303266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.otp_ctrl_check_fail.46427029311411039483183536549805355686244076830732472554046877841089714303266
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.102391976181057930943945937178704353750351096430026557221805550104897120996558
Short name T981
Test name
Test status
Simulation time 390019183 ps
CPU time 10.85 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 01:51:15 PM PST 23
Peak memory 238504 kb
Host smart-a10835c9-9c65-4bc0-91cc-cdfd0d0deb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102391976181057930943945937178704353750351096430026557221805550104897120996558 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.otp_ctrl_dai_errs.102391976181057930943945937178704353750351096430026557221805550104897120996558
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.15043875500118680374205115739495950635444603563395202400238980059328607260970
Short name T478
Test name
Test status
Simulation time 614979183 ps
CPU time 10.73 seconds
Started Nov 22 01:51:28 PM PST 23
Finished Nov 22 01:51:41 PM PST 23
Peak memory 238692 kb
Host smart-99086ed4-eed2-4ffc-864d-bc7903de7c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15043875500118680374205115739495950635444603563395202400238980059328607260970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.otp_ctrl_dai_lock.15043875500118680374205115739495950635444603563395202400238980059328607260970
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.108922827785638226491823108551793193919652784192230517536585627576193223131732
Short name T739
Test name
Test status
Simulation time 156689183 ps
CPU time 4.04 seconds
Started Nov 22 01:51:32 PM PST 23
Finished Nov 22 01:51:39 PM PST 23
Peak memory 238544 kb
Host smart-41caca1e-c43d-4c3f-a9e4-c9edc230cf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108922827785638226491823108551793193919652784192230517536585627576193223131732 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.otp_ctrl_init_fail.108922827785638226491823108551793193919652784192230517536585627576193223131732
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.35217024186383750595674079157740856394153033393841121639654497244491372577580
Short name T742
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.65 seconds
Started Nov 22 01:50:55 PM PST 23
Finished Nov 22 01:51:15 PM PST 23
Peak memory 238984 kb
Host smart-4cd68336-ddf7-4faa-b872-a054283fbd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35217024186383750595674079157740856394153033393841121639654497244491372577580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.otp_ctrl_macro_errs.35217024186383750595674079157740856394153033393841121639654497244491372577580
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.68557027812280500566613702023721369579470477899113466360112077702364580093028
Short name T454
Test name
Test status
Simulation time 346349183 ps
CPU time 7.42 seconds
Started Nov 22 01:51:02 PM PST 23
Finished Nov 22 01:51:11 PM PST 23
Peak memory 238752 kb
Host smart-b90b15dd-412e-4cde-8a37-3e114a4c2c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68557027812280500566613702023721369579470477899113466360112077702364580093028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.otp_ctrl_parallel_key_req.68557027812280500566613702023721369579470477899113466360112077702364580093028
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.48409025044496430063037874282985968806378095818966186982630155202104026376632
Short name T964
Test name
Test status
Simulation time 176929183 ps
CPU time 4.44 seconds
Started Nov 22 01:51:49 PM PST 23
Finished Nov 22 01:51:55 PM PST 23
Peak memory 238648 kb
Host smart-4458dc2d-4926-4013-a0b0-f1a03097feea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48409025044496430063037874282985968806378095818966186982630155202104026376632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.48409025044496430063037874282985968806378095818966186982630155202104026376632
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.77103817759041608310173237598790758588675002469377158108508194205723280383024
Short name T710
Test name
Test status
Simulation time 486419183 ps
CPU time 11.76 seconds
Started Nov 22 01:51:34 PM PST 23
Finished Nov 22 01:51:50 PM PST 23
Peak memory 238716 kb
Host smart-9eaca483-32b6-4dee-9158-9720285c7174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77103817759041608310173237598790758588675002469377158108508194205723280383024 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.77103817759041608310173237598790758588675002469377158108508194205723280383024
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.62018693554241344347944669390773271554701513328006652492044795375483657689593
Short name T402
Test name
Test status
Simulation time 137469183 ps
CPU time 3.58 seconds
Started Nov 22 01:50:54 PM PST 23
Finished Nov 22 01:50:58 PM PST 23
Peak memory 238720 kb
Host smart-ef232721-17f4-4cfc-a7cc-15bd01030417
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=62018693554241344347944669390773271554701513328006652492044795375483657689593 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.otp_ctrl_regwen.62018693554241344347944669390773271554701513328006652492044795375483657689593
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.70102409811603390711831470338614076122414044245205386674388928553339560026058
Short name T896
Test name
Test status
Simulation time 138839183 ps
CPU time 3.07 seconds
Started Nov 22 01:52:05 PM PST 23
Finished Nov 22 01:52:11 PM PST 23
Peak memory 238780 kb
Host smart-4f653aa3-4f0b-455e-89c0-5ee708263b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70102409811603390711831470338614076122414044245205386674388928553339560026058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.otp_ctrl_smoke.70102409811603390711831470338614076122414044245205386674388928553339560026058
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.93214662694312348197911521086079309474886268186205125017618429566833197293440
Short name T73
Test name
Test status
Simulation time 13240088340 ps
CPU time 127.79 seconds
Started Nov 22 01:50:54 PM PST 23
Finished Nov 22 01:53:03 PM PST 23
Peak memory 241816 kb
Host smart-67bb626a-414a-4c8d-b187-cc0417891d9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93214662694312348197911521086079309474886268186205125017618429566833197293440 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.93214662694312348197911521086079309474886268186205125017618429566833197293440
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.22093154519456148471835813247954949090565999029169499183734337192448483799317
Short name T499
Test name
Test status
Simulation time 150268849183 ps
CPU time 1957.75 seconds
Started Nov 22 01:51:36 PM PST 23
Finished Nov 22 02:24:18 PM PST 23
Peak memory 517600 kb
Host smart-71d55d6d-e9e2-4b20-8fc4-db8e49f781d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209315451945614847183
5813247954949090565999029169499183734337192448483799317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_res
et.22093154519456148471835813247954949090565999029169499183734337192448483799317
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.43753079624173487762448038414114799979928655711247456031974743165270115866333
Short name T973
Test name
Test status
Simulation time 549639183 ps
CPU time 9.09 seconds
Started Nov 22 01:51:05 PM PST 23
Finished Nov 22 01:51:16 PM PST 23
Peak memory 246972 kb
Host smart-f12b9bd5-1579-4538-8894-2e3b9e78df86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43753079624173487762448038414114799979928655711247456031974743165270115866333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.otp_ctrl_test_access.43753079624173487762448038414114799979928655711247456031974743165270115866333
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.82935502003451475299513672220509976111752208342835904800814555079133203758759
Short name T914
Test name
Test status
Simulation time 156689183 ps
CPU time 4.2 seconds
Started Nov 22 01:52:20 PM PST 23
Finished Nov 22 01:52:27 PM PST 23
Peak memory 238652 kb
Host smart-dd4e2e7e-6309-442f-9a6d-18c741852c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82935502003451475299513672220509976111752208342835904800814555079133203758759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 280.otp_ctrl_init_fail.82935502003451475299513672220509976111752208342835904800814555079133203758759
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.28016586342806721432614286675847295176881867891579838367713780656395087505101
Short name T419
Test name
Test status
Simulation time 156689183 ps
CPU time 3.76 seconds
Started Nov 22 01:52:33 PM PST 23
Finished Nov 22 01:52:40 PM PST 23
Peak memory 238384 kb
Host smart-9c271c32-4baf-4cd0-bcc4-e1011d11be2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28016586342806721432614286675847295176881867891579838367713780656395087505101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 281.otp_ctrl_init_fail.28016586342806721432614286675847295176881867891579838367713780656395087505101
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.114713226471256887262466050225540559748617887074723017625198482601455310273582
Short name T979
Test name
Test status
Simulation time 156689183 ps
CPU time 4.17 seconds
Started Nov 22 01:52:17 PM PST 23
Finished Nov 22 01:52:25 PM PST 23
Peak memory 238652 kb
Host smart-07923c5a-f4b7-4557-af28-a552c0f95d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114713226471256887262466050225540559748617887074723017625198482601455310273582 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 282.otp_ctrl_init_fail.114713226471256887262466050225540559748617887074723017625198482601455310273582
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.15090655098565462795361899804302256310438183457233309860053283619826633894646
Short name T704
Test name
Test status
Simulation time 156689183 ps
CPU time 4.02 seconds
Started Nov 22 01:52:10 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 238648 kb
Host smart-a9c4483c-7cb9-41c1-a78d-5e30d40135fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15090655098565462795361899804302256310438183457233309860053283619826633894646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 283.otp_ctrl_init_fail.15090655098565462795361899804302256310438183457233309860053283619826633894646
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.104252602366666909621563233868733594380811241761200990343084195389400269060459
Short name T888
Test name
Test status
Simulation time 156689183 ps
CPU time 4.03 seconds
Started Nov 22 01:52:41 PM PST 23
Finished Nov 22 01:52:50 PM PST 23
Peak memory 238596 kb
Host smart-d6e46628-299a-4311-93c7-b50fda77510b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104252602366666909621563233868733594380811241761200990343084195389400269060459 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 284.otp_ctrl_init_fail.104252602366666909621563233868733594380811241761200990343084195389400269060459
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.433588876410227225345330675719066108407900190039161386230819323662587213627
Short name T1051
Test name
Test status
Simulation time 156689183 ps
CPU time 3.9 seconds
Started Nov 22 01:52:27 PM PST 23
Finished Nov 22 01:52:37 PM PST 23
Peak memory 238652 kb
Host smart-65fc0a81-2f04-4e4c-a0d1-ace1cd35d240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433588876410227225345330675719066108407900190039161386230819323662587213627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_ba
se_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 285.otp_ctrl_init_fail.433588876410227225345330675719066108407900190039161386230819323662587213627
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.30883212953736202209576560737474544490493453767282291675705879046256288842756
Short name T972
Test name
Test status
Simulation time 156689183 ps
CPU time 3.76 seconds
Started Nov 22 01:52:07 PM PST 23
Finished Nov 22 01:52:15 PM PST 23
Peak memory 238568 kb
Host smart-8376efc7-34ef-4e5d-b512-6a6fc106585a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30883212953736202209576560737474544490493453767282291675705879046256288842756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 286.otp_ctrl_init_fail.30883212953736202209576560737474544490493453767282291675705879046256288842756
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.10262547279454030205664632113050722493801620289734832409676800972149305862107
Short name T489
Test name
Test status
Simulation time 156689183 ps
CPU time 4.12 seconds
Started Nov 22 01:52:17 PM PST 23
Finished Nov 22 01:52:25 PM PST 23
Peak memory 238608 kb
Host smart-9a9eecf5-8148-43e4-80da-ca87fea9cd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10262547279454030205664632113050722493801620289734832409676800972149305862107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 287.otp_ctrl_init_fail.10262547279454030205664632113050722493801620289734832409676800972149305862107
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.84966384734105547623590929700725576987783105176277765815304905545927883088276
Short name T983
Test name
Test status
Simulation time 156689183 ps
CPU time 3.99 seconds
Started Nov 22 01:52:41 PM PST 23
Finished Nov 22 01:52:50 PM PST 23
Peak memory 238600 kb
Host smart-1a67e3c9-7620-41c2-9f22-7121c67530c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84966384734105547623590929700725576987783105176277765815304905545927883088276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 288.otp_ctrl_init_fail.84966384734105547623590929700725576987783105176277765815304905545927883088276
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.55654478627129426334652389986299023091869279447437940858911722929144300358593
Short name T249
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:52:30 PM PST 23
Finished Nov 22 01:52:38 PM PST 23
Peak memory 238584 kb
Host smart-8a238ce5-baef-4c9a-a905-3a1e9fcccef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55654478627129426334652389986299023091869279447437940858911722929144300358593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 289.otp_ctrl_init_fail.55654478627129426334652389986299023091869279447437940858911722929144300358593
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.3176513644295802655373342539896798250729271313826182999360802993441506500793
Short name T1078
Test name
Test status
Simulation time 71069183 ps
CPU time 1.83 seconds
Started Nov 22 01:51:28 PM PST 23
Finished Nov 22 01:51:33 PM PST 23
Peak memory 238452 kb
Host smart-35605207-4f61-4879-af5c-e34a30979514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176513644295802655373342539896798250729271313826182999360802993441506500793 -assert nopostpro
c +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.3176513644295802655373342539896798250729271313826182999360802993441506500793
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.4891617368183465153055139227084987870832616548145848792164100988136249092171
Short name T490
Test name
Test status
Simulation time 111269183 ps
CPU time 2.57 seconds
Started Nov 22 01:51:23 PM PST 23
Finished Nov 22 01:51:28 PM PST 23
Peak memory 246704 kb
Host smart-20159195-55d0-4a82-9894-73fac5c8c9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4891617368183465153055139227084987870832616548145848792164100988136249092171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.otp_ctrl_check_fail.4891617368183465153055139227084987870832616548145848792164100988136249092171
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.87176862504816030548601130376170062279005407646376747131522788419194183319607
Short name T77
Test name
Test status
Simulation time 390019183 ps
CPU time 11.35 seconds
Started Nov 22 01:51:41 PM PST 23
Finished Nov 22 01:51:57 PM PST 23
Peak memory 238700 kb
Host smart-8784bcc1-c3ac-41fc-8d16-42eea1f1bbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87176862504816030548601130376170062279005407646376747131522788419194183319607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.otp_ctrl_dai_errs.87176862504816030548601130376170062279005407646376747131522788419194183319607
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.108601240967420002536693224089180668478417965886643462525166764943698685086425
Short name T604
Test name
Test status
Simulation time 614979183 ps
CPU time 10.79 seconds
Started Nov 22 01:51:02 PM PST 23
Finished Nov 22 01:51:15 PM PST 23
Peak memory 238796 kb
Host smart-6a50452c-c74a-41b9-8e94-be37b6f2ee5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108601240967420002536693224089180668478417965886643462525166764943698685086425 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.otp_ctrl_dai_lock.108601240967420002536693224089180668478417965886643462525166764943698685086425
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.18938912633261935563417159333513630991929878781210876896438341225675722067374
Short name T866
Test name
Test status
Simulation time 156689183 ps
CPU time 3.96 seconds
Started Nov 22 01:51:15 PM PST 23
Finished Nov 22 01:51:21 PM PST 23
Peak memory 238600 kb
Host smart-53c4c523-303f-40c4-a33d-2ced7c47558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18938912633261935563417159333513630991929878781210876896438341225675722067374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.otp_ctrl_init_fail.18938912633261935563417159333513630991929878781210876896438341225675722067374
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.107890417352664910738675201270692825546158630855593912296570842166655326215986
Short name T310
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.63 seconds
Started Nov 22 01:51:32 PM PST 23
Finished Nov 22 01:51:55 PM PST 23
Peak memory 239024 kb
Host smart-cc13517e-1268-4224-bf65-47f64ca32a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107890417352664910738675201270692825546158630855593912296570842166655326215986 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.otp_ctrl_macro_errs.107890417352664910738675201270692825546158630855593912296570842166655326215986
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.40925483810497210687412438443965702527282467950036828972177132528459914765017
Short name T562
Test name
Test status
Simulation time 346349183 ps
CPU time 7.59 seconds
Started Nov 22 01:51:34 PM PST 23
Finished Nov 22 01:51:45 PM PST 23
Peak memory 238752 kb
Host smart-db86796d-1e67-4f01-9584-d925bb96ede2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40925483810497210687412438443965702527282467950036828972177132528459914765017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.otp_ctrl_parallel_key_req.40925483810497210687412438443965702527282467950036828972177132528459914765017
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.83807827661437618132052784879703887794160787799834587582787497415651900289434
Short name T1105
Test name
Test status
Simulation time 176929183 ps
CPU time 4.2 seconds
Started Nov 22 01:51:06 PM PST 23
Finished Nov 22 01:51:12 PM PST 23
Peak memory 238592 kb
Host smart-1129b346-ad25-41be-88e0-78fdba036f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83807827661437618132052784879703887794160787799834587582787497415651900289434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.83807827661437618132052784879703887794160787799834587582787497415651900289434
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.52094645501912166473684981955297642790530280829388706699809422977680386517314
Short name T765
Test name
Test status
Simulation time 486419183 ps
CPU time 12.05 seconds
Started Nov 22 01:51:23 PM PST 23
Finished Nov 22 01:51:37 PM PST 23
Peak memory 238724 kb
Host smart-44aba822-2af8-4cc8-906c-8a667605e683
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52094645501912166473684981955297642790530280829388706699809422977680386517314 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.52094645501912166473684981955297642790530280829388706699809422977680386517314
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.43457014013649783453330903491032472708260701599718200834038676584967829370270
Short name T378
Test name
Test status
Simulation time 137469183 ps
CPU time 3.67 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:27 PM PST 23
Peak memory 238688 kb
Host smart-16a84f5e-77ff-4095-bbbf-5429bb639590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=43457014013649783453330903491032472708260701599718200834038676584967829370270 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.otp_ctrl_regwen.43457014013649783453330903491032472708260701599718200834038676584967829370270
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.27253745295898013466013046950681071637319407586389832253260202339342204943985
Short name T809
Test name
Test status
Simulation time 138839183 ps
CPU time 3.04 seconds
Started Nov 22 01:51:29 PM PST 23
Finished Nov 22 01:51:35 PM PST 23
Peak memory 238816 kb
Host smart-6a121eda-4874-430f-9458-285ca90fed55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27253745295898013466013046950681071637319407586389832253260202339342204943985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.otp_ctrl_smoke.27253745295898013466013046950681071637319407586389832253260202339342204943985
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.4726023897518810756713002490664724686864497897716235514227517972208708926355
Short name T852
Test name
Test status
Simulation time 13240088340 ps
CPU time 135.81 seconds
Started Nov 22 01:51:23 PM PST 23
Finished Nov 22 01:53:41 PM PST 23
Peak memory 241824 kb
Host smart-9b91c292-f61c-4ea1-a1c2-51e50dd68f58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4726023897518810756713002490664724686864497897716235514227517972208708926355 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.4726023897518810756713002490664724686864497897716235514227517972208708926355
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.73356912016981138806283177564160821131651517660634584821877279035370632876701
Short name T754
Test name
Test status
Simulation time 150268849183 ps
CPU time 1933.22 seconds
Started Nov 22 01:51:33 PM PST 23
Finished Nov 22 02:23:50 PM PST 23
Peak memory 517596 kb
Host smart-47469d55-ed9c-4fa5-853f-f2cd1a27f361
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7335691201698113880628
3177564160821131651517660634584821877279035370632876701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_res
et.73356912016981138806283177564160821131651517660634584821877279035370632876701
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.85163344123661752056449448902404197070920356722818408557013759268551092336986
Short name T652
Test name
Test status
Simulation time 549639183 ps
CPU time 9.42 seconds
Started Nov 22 01:51:27 PM PST 23
Finished Nov 22 01:51:39 PM PST 23
Peak memory 247028 kb
Host smart-bd6e7d57-3b4f-47fa-9046-9f09f3b087ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85163344123661752056449448902404197070920356722818408557013759268551092336986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.otp_ctrl_test_access.85163344123661752056449448902404197070920356722818408557013759268551092336986
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.81812744995046109518590892360919298647340254451959226413002513136549304153646
Short name T837
Test name
Test status
Simulation time 156689183 ps
CPU time 3.84 seconds
Started Nov 22 01:52:41 PM PST 23
Finished Nov 22 01:52:50 PM PST 23
Peak memory 238568 kb
Host smart-d5c12610-6b3f-4c11-8b89-c2e22a7b748c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81812744995046109518590892360919298647340254451959226413002513136549304153646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 290.otp_ctrl_init_fail.81812744995046109518590892360919298647340254451959226413002513136549304153646
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.88849868057409666984828542930428632581897119095650449181128852013924324030312
Short name T254
Test name
Test status
Simulation time 156689183 ps
CPU time 4.02 seconds
Started Nov 22 01:52:28 PM PST 23
Finished Nov 22 01:52:38 PM PST 23
Peak memory 238584 kb
Host smart-f8564895-45c2-4021-950c-6dc4a3d6b081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88849868057409666984828542930428632581897119095650449181128852013924324030312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 291.otp_ctrl_init_fail.88849868057409666984828542930428632581897119095650449181128852013924324030312
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.21924927561379375071414439805984027268904047448115302854462530223952704418057
Short name T1070
Test name
Test status
Simulation time 156689183 ps
CPU time 3.79 seconds
Started Nov 22 01:52:36 PM PST 23
Finished Nov 22 01:52:46 PM PST 23
Peak memory 238568 kb
Host smart-62232d97-abba-4957-af61-a757949efb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21924927561379375071414439805984027268904047448115302854462530223952704418057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 292.otp_ctrl_init_fail.21924927561379375071414439805984027268904047448115302854462530223952704418057
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.14204895553324627489683049769814998404400495192026770774700932755368485514657
Short name T481
Test name
Test status
Simulation time 156689183 ps
CPU time 3.76 seconds
Started Nov 22 01:52:19 PM PST 23
Finished Nov 22 01:52:26 PM PST 23
Peak memory 238568 kb
Host smart-027e7de4-3e86-4029-85ba-b6f67e7eef9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14204895553324627489683049769814998404400495192026770774700932755368485514657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 293.otp_ctrl_init_fail.14204895553324627489683049769814998404400495192026770774700932755368485514657
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.100550803056686607345132084242254285970817242749086804427762605501947430990725
Short name T1007
Test name
Test status
Simulation time 156689183 ps
CPU time 4.1 seconds
Started Nov 22 01:52:25 PM PST 23
Finished Nov 22 01:52:31 PM PST 23
Peak memory 238596 kb
Host smart-7ed41cdc-6db1-4748-a0ff-693ae1e1a708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100550803056686607345132084242254285970817242749086804427762605501947430990725 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 294.otp_ctrl_init_fail.100550803056686607345132084242254285970817242749086804427762605501947430990725
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.54576127839252491286292938073347570376939338989995422080354394141089514487806
Short name T1064
Test name
Test status
Simulation time 156689183 ps
CPU time 3.94 seconds
Started Nov 22 01:52:05 PM PST 23
Finished Nov 22 01:52:12 PM PST 23
Peak memory 238616 kb
Host smart-29d31d29-844f-4214-970a-47af41b0e6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54576127839252491286292938073347570376939338989995422080354394141089514487806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 295.otp_ctrl_init_fail.54576127839252491286292938073347570376939338989995422080354394141089514487806
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.29376686267080872766494890529687048873412148646964318408303386237301670658382
Short name T919
Test name
Test status
Simulation time 156689183 ps
CPU time 4.07 seconds
Started Nov 22 01:52:17 PM PST 23
Finished Nov 22 01:52:25 PM PST 23
Peak memory 238664 kb
Host smart-05db6eda-915d-4099-94da-9e9956b96182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29376686267080872766494890529687048873412148646964318408303386237301670658382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 296.otp_ctrl_init_fail.29376686267080872766494890529687048873412148646964318408303386237301670658382
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.87505268123799135763177291371412858445511408956851044771652344000445915448800
Short name T544
Test name
Test status
Simulation time 156689183 ps
CPU time 3.93 seconds
Started Nov 22 01:52:19 PM PST 23
Finished Nov 22 01:52:26 PM PST 23
Peak memory 238652 kb
Host smart-1044538c-0a13-4708-9051-005575de46d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87505268123799135763177291371412858445511408956851044771652344000445915448800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 297.otp_ctrl_init_fail.87505268123799135763177291371412858445511408956851044771652344000445915448800
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.73534809761559570608874200509654777538528627194504540959422141877352941330899
Short name T1166
Test name
Test status
Simulation time 156689183 ps
CPU time 4.03 seconds
Started Nov 22 01:52:29 PM PST 23
Finished Nov 22 01:52:38 PM PST 23
Peak memory 238636 kb
Host smart-31f40d17-c38f-49d5-8f73-3977c4fb066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73534809761559570608874200509654777538528627194504540959422141877352941330899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 298.otp_ctrl_init_fail.73534809761559570608874200509654777538528627194504540959422141877352941330899
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.87172344765146630429801511001803120696670370827949881425499440723819403662464
Short name T1233
Test name
Test status
Simulation time 156689183 ps
CPU time 4.11 seconds
Started Nov 22 01:52:34 PM PST 23
Finished Nov 22 01:52:41 PM PST 23
Peak memory 238616 kb
Host smart-c18d33b5-b1cf-440a-8161-a16feedac465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87172344765146630429801511001803120696670370827949881425499440723819403662464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 299.otp_ctrl_init_fail.87172344765146630429801511001803120696670370827949881425499440723819403662464
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.62221078463033985280620856628714311921833369263276779246929692771456437132396
Short name T638
Test name
Test status
Simulation time 71069183 ps
CPU time 1.88 seconds
Started Nov 22 01:50:03 PM PST 23
Finished Nov 22 01:50:08 PM PST 23
Peak memory 238328 kb
Host smart-989d5030-02ec-4e48-9729-5a2f2db0302b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62221078463033985280620856628714311921833369263276779246929692771456437132396 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.62221078463033985280620856628714311921833369263276779246929692771456437132396
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.73543412133586334293516798292680068070234475446779949253917875890384527986529
Short name T450
Test name
Test status
Simulation time 190889183 ps
CPU time 4.68 seconds
Started Nov 22 01:49:57 PM PST 23
Finished Nov 22 01:50:04 PM PST 23
Peak memory 238776 kb
Host smart-7fca1cd7-4f8d-4026-907a-26db0ad76a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73543412133586334293516798292680068070234475446779949253917875890384527986529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.otp_ctrl_background_chks.73543412133586334293516798292680068070234475446779949253917875890384527986529
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.45208743518948878232368566743735434945432697454352115547008724760662535059365
Short name T982
Test name
Test status
Simulation time 111269183 ps
CPU time 2.64 seconds
Started Nov 22 01:49:56 PM PST 23
Finished Nov 22 01:50:00 PM PST 23
Peak memory 246680 kb
Host smart-320cc412-1081-4171-8cd9-b5def05048f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45208743518948878232368566743735434945432697454352115547008724760662535059365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.otp_ctrl_check_fail.45208743518948878232368566743735434945432697454352115547008724760662535059365
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.14325108362639917134472458631916126596799388803500924868552838132933026281025
Short name T1286
Test name
Test status
Simulation time 390019183 ps
CPU time 11.16 seconds
Started Nov 22 01:50:08 PM PST 23
Finished Nov 22 01:50:25 PM PST 23
Peak memory 238560 kb
Host smart-96c99db7-43c8-4e1c-8a35-59224b001bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14325108362639917134472458631916126596799388803500924868552838132933026281025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.otp_ctrl_dai_errs.14325108362639917134472458631916126596799388803500924868552838132933026281025
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.15595224041600235784658985304700771249011679914871655394151752276811346293646
Short name T1224
Test name
Test status
Simulation time 614979183 ps
CPU time 10.22 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:23 PM PST 23
Peak memory 238840 kb
Host smart-bcbc6c2c-377b-41f3-987f-63d0e0609055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15595224041600235784658985304700771249011679914871655394151752276811346293646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.otp_ctrl_dai_lock.15595224041600235784658985304700771249011679914871655394151752276811346293646
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.40770307840573143537481070746662279953276787254624369361857071670585640424826
Short name T688
Test name
Test status
Simulation time 156689183 ps
CPU time 4.15 seconds
Started Nov 22 01:50:08 PM PST 23
Finished Nov 22 01:50:18 PM PST 23
Peak memory 238528 kb
Host smart-5310f607-896a-453d-b4e2-b9bcd8987620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40770307840573143537481070746662279953276787254624369361857071670585640424826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.otp_ctrl_init_fail.40770307840573143537481070746662279953276787254624369361857071670585640424826
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.60846213540368037339854844111210096593265029347265093795355550004959083837596
Short name T692
Test name
Test status
Simulation time 1137629183 ps
CPU time 20.31 seconds
Started Nov 22 01:50:08 PM PST 23
Finished Nov 22 01:50:35 PM PST 23
Peak memory 239108 kb
Host smart-ea000239-e4f6-4719-90bd-015a1b70325c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60846213540368037339854844111210096593265029347265093795355550004959083837596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.otp_ctrl_macro_errs.60846213540368037339854844111210096593265029347265093795355550004959083837596
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.78721945580511248899322499956111933761444144738218715657868864910722758869498
Short name T690
Test name
Test status
Simulation time 346349183 ps
CPU time 7.41 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:13 PM PST 23
Peak memory 238760 kb
Host smart-699359e1-eff6-4907-a9b6-253f2b9eb257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78721945580511248899322499956111933761444144738218715657868864910722758869498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.otp_ctrl_parallel_key_req.78721945580511248899322499956111933761444144738218715657868864910722758869498
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.83566264913707090044436810649211558518787536730349945361218981671142120912552
Short name T493
Test name
Test status
Simulation time 176929183 ps
CPU time 4.31 seconds
Started Nov 22 01:49:57 PM PST 23
Finished Nov 22 01:50:02 PM PST 23
Peak memory 238576 kb
Host smart-4b620ac4-f72c-479a-9515-21e38e7f31bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83566264913707090044436810649211558518787536730349945361218981671142120912552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.83566264913707090044436810649211558518787536730349945361218981671142120912552
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.12982012709105531081576746750432829683318030309565528953369864197363371083204
Short name T609
Test name
Test status
Simulation time 486419183 ps
CPU time 11.66 seconds
Started Nov 22 01:49:57 PM PST 23
Finished Nov 22 01:50:10 PM PST 23
Peak memory 238564 kb
Host smart-4a340675-50aa-4c12-afe6-05a9fd93ee4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=12982012709105531081576746750432829683318030309565528953369864197363371083204 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.12982012709105531081576746750432829683318030309565528953369864197363371083204
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.89986573537463836673462206263941677658118332735973008041418673735013230725826
Short name T632
Test name
Test status
Simulation time 137469183 ps
CPU time 3.59 seconds
Started Nov 22 01:50:01 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 238704 kb
Host smart-57b362c1-26e4-45ce-b3e3-0e97616767eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89986573537463836673462206263941677658118332735973008041418673735013230725826 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_regwen.89986573537463836673462206263941677658118332735973008041418673735013230725826
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.68892115814736297298265990185948267198594826652123421735524700895806219108089
Short name T95
Test name
Test status
Simulation time 8539099183 ps
CPU time 145.99 seconds
Started Nov 22 01:50:00 PM PST 23
Finished Nov 22 01:52:29 PM PST 23
Peak memory 268480 kb
Host smart-f31bc4f2-a8cc-48c1-a07a-9154a3d51c38
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68892115814736297298265990185948267198594826652123421735524700895806219108089 -assert nopostpro
c +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.68892115814736297298265990185948267198594826652123421735524700895806219108089
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.93980823613885420937267213224827957084375856645074697437714057462200027887174
Short name T545
Test name
Test status
Simulation time 138839183 ps
CPU time 3.11 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:16 PM PST 23
Peak memory 238728 kb
Host smart-d9ac80f4-4ce8-46b5-9377-e1387fa7e354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93980823613885420937267213224827957084375856645074697437714057462200027887174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.otp_ctrl_smoke.93980823613885420937267213224827957084375856645074697437714057462200027887174
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.10466836308243883698389230207983582732156121745590839547341933002347503332772
Short name T595
Test name
Test status
Simulation time 13240088340 ps
CPU time 130.68 seconds
Started Nov 22 01:50:06 PM PST 23
Finished Nov 22 01:52:20 PM PST 23
Peak memory 241656 kb
Host smart-5e06bbe5-aaf1-467f-aab9-4d6c5e209649
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10466836308243883698389230207983582732156121745590839547341933002347503332772 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.10466836308243883698389230207983582732156121745590839547341933002347503332772
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.96552496805589719045274347372125100165435407448540132419848597253703369312915
Short name T1013
Test name
Test status
Simulation time 150268849183 ps
CPU time 1987.89 seconds
Started Nov 22 01:49:58 PM PST 23
Finished Nov 22 02:23:08 PM PST 23
Peak memory 517568 kb
Host smart-802b95bf-88f2-4b2e-b043-0508bd2c58aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9655249680558971904527
4347372125100165435407448540132419848597253703369312915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_rese
t.96552496805589719045274347372125100165435407448540132419848597253703369312915
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.8814720191509259227225720665980528705805230529964878816409778975999440047570
Short name T897
Test name
Test status
Simulation time 549639183 ps
CPU time 9.01 seconds
Started Nov 22 01:50:08 PM PST 23
Finished Nov 22 01:50:23 PM PST 23
Peak memory 247008 kb
Host smart-ab36cb0e-11ab-44f5-ad84-4269f8879c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8814720191509259227225720665980528705805230529964878816409778975999440047570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.otp_ctrl_test_access.8814720191509259227225720665980528705805230529964878816409778975999440047570
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.3630878503249809067678077270966013559822036969133746755787060566827238889817
Short name T546
Test name
Test status
Simulation time 71069183 ps
CPU time 1.85 seconds
Started Nov 22 01:51:52 PM PST 23
Finished Nov 22 01:51:55 PM PST 23
Peak memory 238344 kb
Host smart-7f77d07f-a12a-4d28-b5ca-21f5bafcf0e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630878503249809067678077270966013559822036969133746755787060566827238889817 -assert nopostpro
c +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.3630878503249809067678077270966013559822036969133746755787060566827238889817
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.113750107332798399895349381585213110332135110850769677053896352345837131311895
Short name T660
Test name
Test status
Simulation time 111269183 ps
CPU time 2.67 seconds
Started Nov 22 01:51:34 PM PST 23
Finished Nov 22 01:51:41 PM PST 23
Peak memory 246728 kb
Host smart-e8045641-f907-44e2-aa98-825699f18896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113750107332798399895349381585213110332135110850769677053896352345837131311895 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.otp_ctrl_check_fail.113750107332798399895349381585213110332135110850769677053896352345837131311895
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.25569599843975102708999144019826508334419212038595868885614830634240331298034
Short name T788
Test name
Test status
Simulation time 390019183 ps
CPU time 10.85 seconds
Started Nov 22 01:51:46 PM PST 23
Finished Nov 22 01:52:03 PM PST 23
Peak memory 238628 kb
Host smart-bae41184-edee-4eda-b71f-7f5a1d80553e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25569599843975102708999144019826508334419212038595868885614830634240331298034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.otp_ctrl_dai_errs.25569599843975102708999144019826508334419212038595868885614830634240331298034
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.104275439963376435123644507374963098426970844800342655694289499453497535354009
Short name T240
Test name
Test status
Simulation time 614979183 ps
CPU time 10.76 seconds
Started Nov 22 01:51:50 PM PST 23
Finished Nov 22 01:52:02 PM PST 23
Peak memory 238764 kb
Host smart-c45bbb09-d1ec-4da5-bad2-2a58fc8a5b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104275439963376435123644507374963098426970844800342655694289499453497535354009 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.otp_ctrl_dai_lock.104275439963376435123644507374963098426970844800342655694289499453497535354009
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.30552052916559384046799029084239246375675038292994464837963043853842708718603
Short name T1100
Test name
Test status
Simulation time 156689183 ps
CPU time 4.02 seconds
Started Nov 22 01:51:53 PM PST 23
Finished Nov 22 01:51:59 PM PST 23
Peak memory 238592 kb
Host smart-8b6efe9e-46a5-424d-91e4-1636a1b3674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30552052916559384046799029084239246375675038292994464837963043853842708718603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.otp_ctrl_init_fail.30552052916559384046799029084239246375675038292994464837963043853842708718603
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.65436089039506994668134277706475510888649171403565932312816493682901090788570
Short name T1185
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.02 seconds
Started Nov 22 01:51:12 PM PST 23
Finished Nov 22 01:51:34 PM PST 23
Peak memory 238908 kb
Host smart-fba710ba-734c-4c1c-a82c-5ab9b2b28fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65436089039506994668134277706475510888649171403565932312816493682901090788570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.otp_ctrl_macro_errs.65436089039506994668134277706475510888649171403565932312816493682901090788570
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.26809350535109192245314804654185971516472969909264941570403552850893704292894
Short name T819
Test name
Test status
Simulation time 346349183 ps
CPU time 7.75 seconds
Started Nov 22 01:51:53 PM PST 23
Finished Nov 22 01:52:03 PM PST 23
Peak memory 238804 kb
Host smart-b3fe00f7-e6fe-4e79-ba55-b210a5025fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26809350535109192245314804654185971516472969909264941570403552850893704292894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.otp_ctrl_parallel_key_req.26809350535109192245314804654185971516472969909264941570403552850893704292894
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.42348288253002184365992888630350824089744786720996397762482374849133118292942
Short name T820
Test name
Test status
Simulation time 176929183 ps
CPU time 4.22 seconds
Started Nov 22 01:51:27 PM PST 23
Finished Nov 22 01:51:34 PM PST 23
Peak memory 238608 kb
Host smart-aabc2b2d-2492-457f-87a0-4ffeed86dd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42348288253002184365992888630350824089744786720996397762482374849133118292942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.42348288253002184365992888630350824089744786720996397762482374849133118292942
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.81809446520497147126173902291693631778629505367372772337329955695668030136793
Short name T628
Test name
Test status
Simulation time 486419183 ps
CPU time 11.92 seconds
Started Nov 22 01:51:39 PM PST 23
Finished Nov 22 01:51:56 PM PST 23
Peak memory 238680 kb
Host smart-b70fab11-0393-4259-adc4-a5bd98cdc067
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81809446520497147126173902291693631778629505367372772337329955695668030136793 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.81809446520497147126173902291693631778629505367372772337329955695668030136793
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.68420664252220304161875222090829246247051032413028903282574369857776349118196
Short name T33
Test name
Test status
Simulation time 137469183 ps
CPU time 3.66 seconds
Started Nov 22 01:51:26 PM PST 23
Finished Nov 22 01:51:33 PM PST 23
Peak memory 238644 kb
Host smart-a05eefb8-4150-4809-901b-5b62dd045ea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=68420664252220304161875222090829246247051032413028903282574369857776349118196 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.otp_ctrl_regwen.68420664252220304161875222090829246247051032413028903282574369857776349118196
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.103710653254055497153038188906247927412627253513806579822801043534296297315221
Short name T1157
Test name
Test status
Simulation time 138839183 ps
CPU time 3.02 seconds
Started Nov 22 01:51:24 PM PST 23
Finished Nov 22 01:51:30 PM PST 23
Peak memory 238812 kb
Host smart-b7fcacc0-dd55-4d03-a538-995fb3731a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103710653254055497153038188906247927412627253513806579822801043534296297315221 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.otp_ctrl_smoke.103710653254055497153038188906247927412627253513806579822801043534296297315221
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.16176178462622021344881521599858326634027562985062242435547235676329952053063
Short name T1097
Test name
Test status
Simulation time 13240088340 ps
CPU time 127.33 seconds
Started Nov 22 01:51:34 PM PST 23
Finished Nov 22 01:53:45 PM PST 23
Peak memory 241804 kb
Host smart-4386f138-3874-4ac0-9114-e8a31c69df9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16176178462622021344881521599858326634027562985062242435547235676329952053063 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.16176178462622021344881521599858326634027562985062242435547235676329952053063
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.92564128261805407937119565191509474173771065671025508315610595069677723543685
Short name T829
Test name
Test status
Simulation time 150268849183 ps
CPU time 1999.67 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 02:24:44 PM PST 23
Peak memory 517612 kb
Host smart-267cfc36-a3a2-4b25-98a4-b8529d36e2d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9256412826180540793711
9565191509474173771065671025508315610595069677723543685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_res
et.92564128261805407937119565191509474173771065671025508315610595069677723543685
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.84784173151333516976574206818694655567144432751749928769320983218638637826992
Short name T496
Test name
Test status
Simulation time 549639183 ps
CPU time 9.13 seconds
Started Nov 22 01:51:30 PM PST 23
Finished Nov 22 01:51:42 PM PST 23
Peak memory 247036 kb
Host smart-19c75de3-3e76-4aed-844f-7fe94e769d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84784173151333516976574206818694655567144432751749928769320983218638637826992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.otp_ctrl_test_access.84784173151333516976574206818694655567144432751749928769320983218638637826992
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.108713367316236694632571379203724022016691883171588850799052889364024878460462
Short name T90
Test name
Test status
Simulation time 71069183 ps
CPU time 1.87 seconds
Started Nov 22 01:51:00 PM PST 23
Finished Nov 22 01:51:03 PM PST 23
Peak memory 238456 kb
Host smart-30fb378f-a57e-4df5-b648-8b0a2513b90b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108713367316236694632571379203724022016691883171588850799052889364024878460462 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.108713367316236694632571379203724022016691883171588850799052889364024878460462
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.87396359340542659431831134102295646063137749222511900102449790632260354792063
Short name T330
Test name
Test status
Simulation time 111269183 ps
CPU time 2.73 seconds
Started Nov 22 01:51:49 PM PST 23
Finished Nov 22 01:51:54 PM PST 23
Peak memory 246760 kb
Host smart-b0bf2f91-bba1-49cc-b096-83b126acb3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87396359340542659431831134102295646063137749222511900102449790632260354792063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.otp_ctrl_check_fail.87396359340542659431831134102295646063137749222511900102449790632260354792063
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.87182266378521272111779274219031787370921464831484720655643252393916724960381
Short name T909
Test name
Test status
Simulation time 390019183 ps
CPU time 10.6 seconds
Started Nov 22 01:51:32 PM PST 23
Finished Nov 22 01:51:45 PM PST 23
Peak memory 238636 kb
Host smart-60ff5b39-8218-475e-839f-b1f61ae247bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87182266378521272111779274219031787370921464831484720655643252393916724960381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.otp_ctrl_dai_errs.87182266378521272111779274219031787370921464831484720655643252393916724960381
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.46092001189397186980444289915300395716956047405552495967448545448535541201435
Short name T401
Test name
Test status
Simulation time 614979183 ps
CPU time 10.23 seconds
Started Nov 22 01:51:42 PM PST 23
Finished Nov 22 01:51:56 PM PST 23
Peak memory 238808 kb
Host smart-9fff18d7-310e-4add-9a0d-259cc2d8bf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46092001189397186980444289915300395716956047405552495967448545448535541201435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.otp_ctrl_dai_lock.46092001189397186980444289915300395716956047405552495967448545448535541201435
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.5889235021727774605403052346258412536819120410771942437886826548511934950427
Short name T345
Test name
Test status
Simulation time 156689183 ps
CPU time 4.12 seconds
Started Nov 22 01:51:40 PM PST 23
Finished Nov 22 01:51:49 PM PST 23
Peak memory 238560 kb
Host smart-f64cfc81-6686-49a9-b63a-131883fa720c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5889235021727774605403052346258412536819120410771942437886826548511934950427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.otp_ctrl_init_fail.5889235021727774605403052346258412536819120410771942437886826548511934950427
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.8277319532296404855794132873125101484277292837689474406755901284848712195343
Short name T444
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.16 seconds
Started Nov 22 01:51:39 PM PST 23
Finished Nov 22 01:52:03 PM PST 23
Peak memory 239020 kb
Host smart-fe849ad0-5c1e-43fc-9621-2d7c09346cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8277319532296404855794132873125101484277292837689474406755901284848712195343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.otp_ctrl_macro_errs.8277319532296404855794132873125101484277292837689474406755901284848712195343
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.15462765113125392776468470509510156899750008420696744463247046029706077574064
Short name T361
Test name
Test status
Simulation time 346349183 ps
CPU time 7.66 seconds
Started Nov 22 01:51:53 PM PST 23
Finished Nov 22 01:52:03 PM PST 23
Peak memory 238648 kb
Host smart-cba01ec2-3c06-4464-88b8-4a99a1fc24e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15462765113125392776468470509510156899750008420696744463247046029706077574064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.otp_ctrl_parallel_key_req.15462765113125392776468470509510156899750008420696744463247046029706077574064
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.25029967877556636351212698935954929188329847500043263813639717884419545727160
Short name T289
Test name
Test status
Simulation time 176929183 ps
CPU time 4.27 seconds
Started Nov 22 01:51:26 PM PST 23
Finished Nov 22 01:51:33 PM PST 23
Peak memory 238588 kb
Host smart-aa5ae1cc-cf4d-4393-9127-0b5cec98e81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25029967877556636351212698935954929188329847500043263813639717884419545727160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.25029967877556636351212698935954929188329847500043263813639717884419545727160
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.64487086607109607962099541041838024191264406582456614323850887941239001229051
Short name T365
Test name
Test status
Simulation time 486419183 ps
CPU time 11.95 seconds
Started Nov 22 01:51:46 PM PST 23
Finished Nov 22 01:52:01 PM PST 23
Peak memory 238664 kb
Host smart-2bac92d4-ca51-443a-9ecb-8e5838938590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64487086607109607962099541041838024191264406582456614323850887941239001229051 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.64487086607109607962099541041838024191264406582456614323850887941239001229051
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.21294456078073376898074232004245072662243203510371500055246704078250043111502
Short name T315
Test name
Test status
Simulation time 137469183 ps
CPU time 3.58 seconds
Started Nov 22 01:51:37 PM PST 23
Finished Nov 22 01:51:45 PM PST 23
Peak memory 238696 kb
Host smart-3842a7c3-9589-48c6-a730-d5f55b58ad19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21294456078073376898074232004245072662243203510371500055246704078250043111502 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.otp_ctrl_regwen.21294456078073376898074232004245072662243203510371500055246704078250043111502
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.32920933928470126334115321807913364097525523050025419195325559249364943742627
Short name T798
Test name
Test status
Simulation time 138839183 ps
CPU time 2.99 seconds
Started Nov 22 01:51:51 PM PST 23
Finished Nov 22 01:51:56 PM PST 23
Peak memory 238720 kb
Host smart-5431e7d3-ebd2-4ecd-a894-ebbece5d6e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32920933928470126334115321807913364097525523050025419195325559249364943742627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.otp_ctrl_smoke.32920933928470126334115321807913364097525523050025419195325559249364943742627
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.62460238432133879168256891850121887367644838338191999652340202807842797130938
Short name T576
Test name
Test status
Simulation time 13240088340 ps
CPU time 128.18 seconds
Started Nov 22 01:51:33 PM PST 23
Finished Nov 22 01:53:44 PM PST 23
Peak memory 241828 kb
Host smart-08135861-5786-4f15-afa2-793742c261d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62460238432133879168256891850121887367644838338191999652340202807842797130938 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.62460238432133879168256891850121887367644838338191999652340202807842797130938
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.6102051017889411214824203025512246280337665165031944746958948359893724007620
Short name T575
Test name
Test status
Simulation time 150268849183 ps
CPU time 1925.44 seconds
Started Nov 22 01:51:09 PM PST 23
Finished Nov 22 02:23:16 PM PST 23
Peak memory 517516 kb
Host smart-a7d7e597-a5ed-44c4-adb4-7ff111f42f1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6102051017889411214824
203025512246280337665165031944746958948359893724007620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_rese
t.6102051017889411214824203025512246280337665165031944746958948359893724007620
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.14287124830504833352956203616351024695767596768027820914267899759911055810993
Short name T965
Test name
Test status
Simulation time 549639183 ps
CPU time 8.77 seconds
Started Nov 22 01:51:57 PM PST 23
Finished Nov 22 01:52:07 PM PST 23
Peak memory 246808 kb
Host smart-7cbfe9cd-eee3-4c79-a302-4a83bce3edd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14287124830504833352956203616351024695767596768027820914267899759911055810993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.otp_ctrl_test_access.14287124830504833352956203616351024695767596768027820914267899759911055810993
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.52854776921301293057970032841388744098154376265446083910776435761280799887901
Short name T687
Test name
Test status
Simulation time 71069183 ps
CPU time 1.89 seconds
Started Nov 22 01:50:42 PM PST 23
Finished Nov 22 01:50:45 PM PST 23
Peak memory 238284 kb
Host smart-b49aa524-541f-417a-bc25-b64fc326fe43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52854776921301293057970032841388744098154376265446083910776435761280799887901 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.52854776921301293057970032841388744098154376265446083910776435761280799887901
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.109650527190819994860716315429622946737271622420068463292443175113068995894269
Short name T1295
Test name
Test status
Simulation time 111269183 ps
CPU time 2.68 seconds
Started Nov 22 01:51:07 PM PST 23
Finished Nov 22 01:51:12 PM PST 23
Peak memory 246740 kb
Host smart-f79fc8d8-e0da-4fde-b902-db13ecfeba47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109650527190819994860716315429622946737271622420068463292443175113068995894269 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.otp_ctrl_check_fail.109650527190819994860716315429622946737271622420068463292443175113068995894269
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.25715393312733656167050498989890050727815970273334961944031185187805452269586
Short name T667
Test name
Test status
Simulation time 390019183 ps
CPU time 11.06 seconds
Started Nov 22 01:51:04 PM PST 23
Finished Nov 22 01:51:17 PM PST 23
Peak memory 238624 kb
Host smart-859be536-eb05-48b5-aef6-697cdb23cf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25715393312733656167050498989890050727815970273334961944031185187805452269586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.otp_ctrl_dai_errs.25715393312733656167050498989890050727815970273334961944031185187805452269586
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.20453994465821178488463624839499525550089796663850002948319503016750606845222
Short name T703
Test name
Test status
Simulation time 614979183 ps
CPU time 10.62 seconds
Started Nov 22 01:51:08 PM PST 23
Finished Nov 22 01:51:20 PM PST 23
Peak memory 238788 kb
Host smart-ca3a8c5a-99d0-44c7-a0a4-1fc55daa6267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20453994465821178488463624839499525550089796663850002948319503016750606845222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.otp_ctrl_dai_lock.20453994465821178488463624839499525550089796663850002948319503016750606845222
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.2294998490379174976180386222883201881101980232260941793815221350352727224950
Short name T756
Test name
Test status
Simulation time 156689183 ps
CPU time 4.05 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:28 PM PST 23
Peak memory 238476 kb
Host smart-4a7e74cd-67d5-41d8-86bc-e11a45724fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294998490379174976180386222883201881101980232260941793815221350352727224950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.otp_ctrl_init_fail.2294998490379174976180386222883201881101980232260941793815221350352727224950
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.85882459123899815456479572903845326308880805516614363344639646174881335026335
Short name T301
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.51 seconds
Started Nov 22 01:51:01 PM PST 23
Finished Nov 22 01:51:21 PM PST 23
Peak memory 239028 kb
Host smart-c0e23cfe-a852-4e25-968d-b90e0049f781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85882459123899815456479572903845326308880805516614363344639646174881335026335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.otp_ctrl_macro_errs.85882459123899815456479572903845326308880805516614363344639646174881335026335
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.105091760240375080968953362939958926730546614822828338102923271085039967438013
Short name T894
Test name
Test status
Simulation time 346349183 ps
CPU time 8.08 seconds
Started Nov 22 01:50:38 PM PST 23
Finished Nov 22 01:50:47 PM PST 23
Peak memory 238652 kb
Host smart-1630a08c-d0db-4fd1-88a2-90ad0753a0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105091760240375080968953362939958926730546614822828338102923271085039967438013 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.105091760240375080968953362939958926730546614822828338102923271085039967438013
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.5772832222557839016389608875132926496921863973583273387888837606616873903763
Short name T879
Test name
Test status
Simulation time 176929183 ps
CPU time 4.32 seconds
Started Nov 22 01:51:02 PM PST 23
Finished Nov 22 01:51:08 PM PST 23
Peak memory 238660 kb
Host smart-122d4318-dd47-4e3f-a9cf-32cc7f2cf462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5772832222557839016389608875132926496921863973583273387888837606616873903763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.5772832222557839016389608875132926496921863973583273387888837606616873903763
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.65438156354701163290994849521229264169534388531368153811129073274062821131130
Short name T538
Test name
Test status
Simulation time 486419183 ps
CPU time 11.99 seconds
Started Nov 22 01:51:05 PM PST 23
Finished Nov 22 01:51:19 PM PST 23
Peak memory 238676 kb
Host smart-36763ea8-b351-41b0-95c8-4127ab3d12be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=65438156354701163290994849521229264169534388531368153811129073274062821131130 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.65438156354701163290994849521229264169534388531368153811129073274062821131130
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.37953238619043226300332763849381198076390948280910164457923504835242532222592
Short name T1144
Test name
Test status
Simulation time 137469183 ps
CPU time 3.63 seconds
Started Nov 22 01:50:54 PM PST 23
Finished Nov 22 01:50:58 PM PST 23
Peak memory 238712 kb
Host smart-768c8ead-3d3b-4d50-b776-287ba3545794
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37953238619043226300332763849381198076390948280910164457923504835242532222592 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.otp_ctrl_regwen.37953238619043226300332763849381198076390948280910164457923504835242532222592
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.75891400518417359311840969435890415792070159938416567472092882940875460827990
Short name T876
Test name
Test status
Simulation time 138839183 ps
CPU time 3.08 seconds
Started Nov 22 01:51:37 PM PST 23
Finished Nov 22 01:51:45 PM PST 23
Peak memory 238920 kb
Host smart-7c830f84-1764-422a-8e4b-70c88d69754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75891400518417359311840969435890415792070159938416567472092882940875460827990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.otp_ctrl_smoke.75891400518417359311840969435890415792070159938416567472092882940875460827990
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.38521139838180228542195250353192450997884651063466481836169672889479560358886
Short name T1247
Test name
Test status
Simulation time 13240088340 ps
CPU time 129.69 seconds
Started Nov 22 01:50:44 PM PST 23
Finished Nov 22 01:52:55 PM PST 23
Peak memory 241832 kb
Host smart-665a6c4d-ed5f-4191-a971-d46a2fbd9b99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38521139838180228542195250353192450997884651063466481836169672889479560358886 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.38521139838180228542195250353192450997884651063466481836169672889479560358886
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.106705042161284372359698586924268665305084329890084595888888050592647858903206
Short name T663
Test name
Test status
Simulation time 150268849183 ps
CPU time 1956.58 seconds
Started Nov 22 01:50:48 PM PST 23
Finished Nov 22 02:23:25 PM PST 23
Peak memory 517540 kb
Host smart-8deca9ff-de79-4856-8395-776da8f5c208
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067050421612843723596
98586924268665305084329890084595888888050592647858903206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_re
set.106705042161284372359698586924268665305084329890084595888888050592647858903206
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.88580577134449819298429103589592309413082293190186821798877811158038354625981
Short name T1202
Test name
Test status
Simulation time 549639183 ps
CPU time 8.99 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 01:51:14 PM PST 23
Peak memory 247028 kb
Host smart-619b44a5-4fde-4bcc-8b15-0c00be420fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88580577134449819298429103589592309413082293190186821798877811158038354625981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.otp_ctrl_test_access.88580577134449819298429103589592309413082293190186821798877811158038354625981
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.99734818012947019786620564050765389050243025910347702160643322215869434263993
Short name T695
Test name
Test status
Simulation time 71069183 ps
CPU time 1.88 seconds
Started Nov 22 01:51:30 PM PST 23
Finished Nov 22 01:51:35 PM PST 23
Peak memory 238416 kb
Host smart-3e31fdb5-ec96-4adc-9fc3-c57367b6555b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99734818012947019786620564050765389050243025910347702160643322215869434263993 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.99734818012947019786620564050765389050243025910347702160643322215869434263993
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.66265195010305290510182976114062513379273613694758035423995778415887012580886
Short name T861
Test name
Test status
Simulation time 111269183 ps
CPU time 2.71 seconds
Started Nov 22 01:51:08 PM PST 23
Finished Nov 22 01:51:13 PM PST 23
Peak memory 246732 kb
Host smart-ace90d65-8cb8-43be-9967-d068050ada2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66265195010305290510182976114062513379273613694758035423995778415887012580886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.otp_ctrl_check_fail.66265195010305290510182976114062513379273613694758035423995778415887012580886
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.82005510653738662662138306380260609167577698858712718010443637776802290521908
Short name T434
Test name
Test status
Simulation time 390019183 ps
CPU time 11.32 seconds
Started Nov 22 01:51:41 PM PST 23
Finished Nov 22 01:51:57 PM PST 23
Peak memory 238660 kb
Host smart-cd2bd0ee-9ab4-4ac0-9b25-fde6dc2ca3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82005510653738662662138306380260609167577698858712718010443637776802290521908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.otp_ctrl_dai_errs.82005510653738662662138306380260609167577698858712718010443637776802290521908
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.63781246925970781726181290500023042737010506073023426071402895729165675628661
Short name T528
Test name
Test status
Simulation time 614979183 ps
CPU time 10.39 seconds
Started Nov 22 01:51:02 PM PST 23
Finished Nov 22 01:51:14 PM PST 23
Peak memory 238752 kb
Host smart-5babb6df-90ca-4dea-b526-46734fbe3465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63781246925970781726181290500023042737010506073023426071402895729165675628661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.otp_ctrl_dai_lock.63781246925970781726181290500023042737010506073023426071402895729165675628661
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.51780256632164740025583765954202493711281280240710704836682243563747967765861
Short name T374
Test name
Test status
Simulation time 156689183 ps
CPU time 4.07 seconds
Started Nov 22 01:51:12 PM PST 23
Finished Nov 22 01:51:23 PM PST 23
Peak memory 238616 kb
Host smart-23d17820-2595-4373-9416-a027589f4415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51780256632164740025583765954202493711281280240710704836682243563747967765861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.otp_ctrl_init_fail.51780256632164740025583765954202493711281280240710704836682243563747967765861
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.16655054705786048511148624018336259535297117782483297183776916605156353623711
Short name T437
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.24 seconds
Started Nov 22 01:51:11 PM PST 23
Finished Nov 22 01:51:31 PM PST 23
Peak memory 238940 kb
Host smart-cdcf0b73-df7f-4de1-943f-b9375a052fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16655054705786048511148624018336259535297117782483297183776916605156353623711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.otp_ctrl_macro_errs.16655054705786048511148624018336259535297117782483297183776916605156353623711
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.42666046317564414302141403360129549291993542661511598186882656077121241259233
Short name T815
Test name
Test status
Simulation time 346349183 ps
CPU time 7.3 seconds
Started Nov 22 01:51:26 PM PST 23
Finished Nov 22 01:51:36 PM PST 23
Peak memory 238652 kb
Host smart-43b30b1c-e3ae-400c-956c-39e6f7a49723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42666046317564414302141403360129549291993542661511598186882656077121241259233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.otp_ctrl_parallel_key_req.42666046317564414302141403360129549291993542661511598186882656077121241259233
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.85887656197539153589528292838796333777934612957847151604708158295924619011843
Short name T661
Test name
Test status
Simulation time 176929183 ps
CPU time 4.4 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:28 PM PST 23
Peak memory 238704 kb
Host smart-fb2c8c7c-695f-48c6-9a3f-b6eda60bed66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85887656197539153589528292838796333777934612957847151604708158295924619011843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.85887656197539153589528292838796333777934612957847151604708158295924619011843
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.11669498875327272481798109757008813715828505035631821667715287768553237165177
Short name T536
Test name
Test status
Simulation time 486419183 ps
CPU time 11.67 seconds
Started Nov 22 01:51:13 PM PST 23
Finished Nov 22 01:51:27 PM PST 23
Peak memory 238596 kb
Host smart-8c10a0c5-815f-44f2-a1ee-0e828e40dc44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11669498875327272481798109757008813715828505035631821667715287768553237165177 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.11669498875327272481798109757008813715828505035631821667715287768553237165177
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.60609353866261710639852688871632575486136936950983585419992579359294113874869
Short name T379
Test name
Test status
Simulation time 137469183 ps
CPU time 3.68 seconds
Started Nov 22 01:51:20 PM PST 23
Finished Nov 22 01:51:26 PM PST 23
Peak memory 238660 kb
Host smart-7a07405a-d32b-48bd-b277-190d36399cc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60609353866261710639852688871632575486136936950983585419992579359294113874869 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.otp_ctrl_regwen.60609353866261710639852688871632575486136936950983585419992579359294113874869
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.90713251335770572623422822539541077626515306731244090399140551326390690195980
Short name T854
Test name
Test status
Simulation time 138839183 ps
CPU time 2.93 seconds
Started Nov 22 01:51:05 PM PST 23
Finished Nov 22 01:51:10 PM PST 23
Peak memory 238748 kb
Host smart-a722ba72-caf5-476e-9bb2-0b4e681eba10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90713251335770572623422822539541077626515306731244090399140551326390690195980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.otp_ctrl_smoke.90713251335770572623422822539541077626515306731244090399140551326390690195980
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.73391298093218069534102878340419114979204460411310038966754567503734533745148
Short name T44
Test name
Test status
Simulation time 13240088340 ps
CPU time 130.4 seconds
Started Nov 22 01:51:39 PM PST 23
Finished Nov 22 01:53:54 PM PST 23
Peak memory 241840 kb
Host smart-17425641-c829-4184-a12d-e91ba3ae18e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73391298093218069534102878340419114979204460411310038966754567503734533745148 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.73391298093218069534102878340419114979204460411310038966754567503734533745148
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.77701797342066870501928355707008338633979122285156476770499405856380152551043
Short name T1130
Test name
Test status
Simulation time 150268849183 ps
CPU time 1917.35 seconds
Started Nov 22 01:51:41 PM PST 23
Finished Nov 22 02:23:43 PM PST 23
Peak memory 517540 kb
Host smart-364d9ba9-fa1e-407a-88de-355ec83cdf42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7770179734206687050192
8355707008338633979122285156476770499405856380152551043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_res
et.77701797342066870501928355707008338633979122285156476770499405856380152551043
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.69878041334997209160362496450308870694060050464650357235476556225861432920303
Short name T1141
Test name
Test status
Simulation time 549639183 ps
CPU time 8.94 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:33 PM PST 23
Peak memory 247028 kb
Host smart-16a39b3e-4bdb-4a68-bc3f-9543da6c7cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69878041334997209160362496450308870694060050464650357235476556225861432920303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.otp_ctrl_test_access.69878041334997209160362496450308870694060050464650357235476556225861432920303
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.45439633184278741254198044098694617608687636875029828398123622108739524246106
Short name T426
Test name
Test status
Simulation time 71069183 ps
CPU time 1.86 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:49 PM PST 23
Peak memory 238484 kb
Host smart-79307295-dba8-4afb-8182-afeeb16833a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45439633184278741254198044098694617608687636875029828398123622108739524246106 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.45439633184278741254198044098694617608687636875029828398123622108739524246106
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.114325354960166304708905125663236157996032216956292786805311841429089662339867
Short name T324
Test name
Test status
Simulation time 111269183 ps
CPU time 2.67 seconds
Started Nov 22 01:51:47 PM PST 23
Finished Nov 22 01:51:53 PM PST 23
Peak memory 246728 kb
Host smart-981d2cea-f31f-43c5-a5f7-34f9c2e15545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114325354960166304708905125663236157996032216956292786805311841429089662339867 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.otp_ctrl_check_fail.114325354960166304708905125663236157996032216956292786805311841429089662339867
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.38369419325029224060694295228956773643946035813421463439437794666831686954671
Short name T246
Test name
Test status
Simulation time 390019183 ps
CPU time 10.66 seconds
Started Nov 22 01:51:54 PM PST 23
Finished Nov 22 01:52:07 PM PST 23
Peak memory 238564 kb
Host smart-26f82b59-0758-4d23-adcc-623db4655fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38369419325029224060694295228956773643946035813421463439437794666831686954671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.otp_ctrl_dai_errs.38369419325029224060694295228956773643946035813421463439437794666831686954671
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.97904046089066963737877045926567875257167993401040977228389160820699536745107
Short name T463
Test name
Test status
Simulation time 614979183 ps
CPU time 10.31 seconds
Started Nov 22 01:51:28 PM PST 23
Finished Nov 22 01:51:41 PM PST 23
Peak memory 238720 kb
Host smart-d3268c09-9c84-435c-a1df-ed163822606d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97904046089066963737877045926567875257167993401040977228389160820699536745107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.otp_ctrl_dai_lock.97904046089066963737877045926567875257167993401040977228389160820699536745107
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.65540187473692878636773426926488064412907727448689200138733006516941697327956
Short name T760
Test name
Test status
Simulation time 156689183 ps
CPU time 3.83 seconds
Started Nov 22 01:51:16 PM PST 23
Finished Nov 22 01:51:22 PM PST 23
Peak memory 238524 kb
Host smart-39cc5202-e573-44b2-bc7a-b80e52bb19b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65540187473692878636773426926488064412907727448689200138733006516941697327956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.otp_ctrl_init_fail.65540187473692878636773426926488064412907727448689200138733006516941697327956
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.40657586515190528923278712772707930546778687134242673744116699033329101131039
Short name T508
Test name
Test status
Simulation time 1137629183 ps
CPU time 20.25 seconds
Started Nov 22 01:51:38 PM PST 23
Finished Nov 22 01:52:03 PM PST 23
Peak memory 239000 kb
Host smart-91007163-a48f-46a6-924c-14359b2658b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40657586515190528923278712772707930546778687134242673744116699033329101131039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.otp_ctrl_macro_errs.40657586515190528923278712772707930546778687134242673744116699033329101131039
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.70694797426815573418388857919296999147862618770883921095519596678422199552261
Short name T580
Test name
Test status
Simulation time 346349183 ps
CPU time 7.32 seconds
Started Nov 22 01:51:33 PM PST 23
Finished Nov 22 01:51:44 PM PST 23
Peak memory 238732 kb
Host smart-22b19879-8d83-4fad-8a4c-484967c013f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70694797426815573418388857919296999147862618770883921095519596678422199552261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.otp_ctrl_parallel_key_req.70694797426815573418388857919296999147862618770883921095519596678422199552261
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.8699875696645697659404210785079929747884692458986088461521011378908136019746
Short name T1001
Test name
Test status
Simulation time 176929183 ps
CPU time 4.29 seconds
Started Nov 22 01:51:09 PM PST 23
Finished Nov 22 01:51:15 PM PST 23
Peak memory 238644 kb
Host smart-f760bc03-ddbf-4d61-ab5f-b49358ba7c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8699875696645697659404210785079929747884692458986088461521011378908136019746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.8699875696645697659404210785079929747884692458986088461521011378908136019746
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.11230673168828395660426827004292109239547976291930812819117449455988347284517
Short name T1122
Test name
Test status
Simulation time 486419183 ps
CPU time 11.66 seconds
Started Nov 22 01:51:28 PM PST 23
Finished Nov 22 01:51:42 PM PST 23
Peak memory 238620 kb
Host smart-d1d7e223-aadc-4def-ad64-c6607e0445c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11230673168828395660426827004292109239547976291930812819117449455988347284517 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.11230673168828395660426827004292109239547976291930812819117449455988347284517
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.108737149749117842234282823453103850977461399383637542649723206278217506967710
Short name T1215
Test name
Test status
Simulation time 137469183 ps
CPU time 3.54 seconds
Started Nov 22 01:51:36 PM PST 23
Finished Nov 22 01:51:44 PM PST 23
Peak memory 238552 kb
Host smart-7b0c19bd-9581-4144-b296-6f111263d413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=108737149749117842234282823453103850977461399383637542649723206278217506967710 -assert nopostproc +UVM_TE
STNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.otp_ctrl_regwen.108737149749117842234282823453103850977461399383637542649723206278217506967710
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.78621122190979357964426285630943823213044390860744158625952000914405613690489
Short name T584
Test name
Test status
Simulation time 138839183 ps
CPU time 3.11 seconds
Started Nov 22 01:51:27 PM PST 23
Finished Nov 22 01:51:32 PM PST 23
Peak memory 238780 kb
Host smart-09b3d66a-4913-4c1e-abb3-6e682c53ef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78621122190979357964426285630943823213044390860744158625952000914405613690489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.otp_ctrl_smoke.78621122190979357964426285630943823213044390860744158625952000914405613690489
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.26989325505230707543251912844332017430899748171510567967214259221614468390992
Short name T442
Test name
Test status
Simulation time 13240088340 ps
CPU time 126.59 seconds
Started Nov 22 01:51:53 PM PST 23
Finished Nov 22 01:54:02 PM PST 23
Peak memory 241536 kb
Host smart-2167138b-cbb9-4105-8f86-9c4275d70300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26989325505230707543251912844332017430899748171510567967214259221614468390992 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.26989325505230707543251912844332017430899748171510567967214259221614468390992
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.110528686005760335768120060501095380998431227313022493324801924979378892582956
Short name T1230
Test name
Test status
Simulation time 150268849183 ps
CPU time 1965.65 seconds
Started Nov 22 01:51:34 PM PST 23
Finished Nov 22 02:24:23 PM PST 23
Peak memory 517584 kb
Host smart-1dd5c3dd-69fc-41b6-b447-3708db5ef26c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105286860057603357681
20060501095380998431227313022493324801924979378892582956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_re
set.110528686005760335768120060501095380998431227313022493324801924979378892582956
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.37813585041727908361566646212123275931319762196245278100586707183534116711847
Short name T1159
Test name
Test status
Simulation time 549639183 ps
CPU time 8.92 seconds
Started Nov 22 01:51:35 PM PST 23
Finished Nov 22 01:51:48 PM PST 23
Peak memory 247036 kb
Host smart-23f28d2d-b62e-4ef8-a971-1ef9b80906a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37813585041727908361566646212123275931319762196245278100586707183534116711847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.otp_ctrl_test_access.37813585041727908361566646212123275931319762196245278100586707183534116711847
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.7096360408463904550588372790626552457149707842972368870178871857235748495458
Short name T1039
Test name
Test status
Simulation time 71069183 ps
CPU time 1.78 seconds
Started Nov 22 01:50:54 PM PST 23
Finished Nov 22 01:50:56 PM PST 23
Peak memory 238440 kb
Host smart-b974b1d4-cbd4-491f-90e7-f798208a4601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7096360408463904550588372790626552457149707842972368870178871857235748495458 -assert nopostpro
c +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.7096360408463904550588372790626552457149707842972368870178871857235748495458
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.22350656545323890960388583839708762786375430717729778529204873358469070734680
Short name T316
Test name
Test status
Simulation time 111269183 ps
CPU time 2.67 seconds
Started Nov 22 01:51:05 PM PST 23
Finished Nov 22 01:51:09 PM PST 23
Peak memory 246720 kb
Host smart-2738ebc1-061a-4172-9640-0622048c2488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22350656545323890960388583839708762786375430717729778529204873358469070734680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.otp_ctrl_check_fail.22350656545323890960388583839708762786375430717729778529204873358469070734680
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.52160092598591409898452222481848137209588244429545658974290453381112798509003
Short name T915
Test name
Test status
Simulation time 390019183 ps
CPU time 10.96 seconds
Started Nov 22 01:51:49 PM PST 23
Finished Nov 22 01:52:02 PM PST 23
Peak memory 238520 kb
Host smart-c81b4131-691f-4e8b-9750-c92d2e1d661c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52160092598591409898452222481848137209588244429545658974290453381112798509003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.otp_ctrl_dai_errs.52160092598591409898452222481848137209588244429545658974290453381112798509003
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.56996208192968960330145734619207413359358143895386320008689613372091732969924
Short name T701
Test name
Test status
Simulation time 614979183 ps
CPU time 10.49 seconds
Started Nov 22 01:51:39 PM PST 23
Finished Nov 22 01:51:55 PM PST 23
Peak memory 238808 kb
Host smart-d072f921-99e8-4707-b512-d83d7944283b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56996208192968960330145734619207413359358143895386320008689613372091732969924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.otp_ctrl_dai_lock.56996208192968960330145734619207413359358143895386320008689613372091732969924
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.16923338405612590148903230007625565258056876438721110323341719211321571010842
Short name T472
Test name
Test status
Simulation time 156689183 ps
CPU time 3.97 seconds
Started Nov 22 01:51:53 PM PST 23
Finished Nov 22 01:51:59 PM PST 23
Peak memory 238460 kb
Host smart-755fd724-21ca-48a9-9210-2264ed870d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16923338405612590148903230007625565258056876438721110323341719211321571010842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.otp_ctrl_init_fail.16923338405612590148903230007625565258056876438721110323341719211321571010842
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.43978035917796123547678538052825609210815666088891429183775727635863080421514
Short name T629
Test name
Test status
Simulation time 1137629183 ps
CPU time 18.43 seconds
Started Nov 22 01:51:51 PM PST 23
Finished Nov 22 01:52:11 PM PST 23
Peak memory 238912 kb
Host smart-71792df8-671d-4012-b707-97c1e9bf73b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43978035917796123547678538052825609210815666088891429183775727635863080421514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.otp_ctrl_macro_errs.43978035917796123547678538052825609210815666088891429183775727635863080421514
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.100899793598556540947795300343398210739305008571298455978688501684909505155776
Short name T1023
Test name
Test status
Simulation time 346349183 ps
CPU time 7.44 seconds
Started Nov 22 01:51:42 PM PST 23
Finished Nov 22 01:51:54 PM PST 23
Peak memory 238756 kb
Host smart-11e2047b-d745-4f18-99a6-71df84d480e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100899793598556540947795300343398210739305008571298455978688501684909505155776 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.100899793598556540947795300343398210739305008571298455978688501684909505155776
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.76388914141324090193064064980051804239400489364611591656802643352961656016296
Short name T244
Test name
Test status
Simulation time 176929183 ps
CPU time 4.29 seconds
Started Nov 22 01:51:26 PM PST 23
Finished Nov 22 01:51:33 PM PST 23
Peak memory 238708 kb
Host smart-d384bbcc-5744-4f33-9ea7-c9371910a5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76388914141324090193064064980051804239400489364611591656802643352961656016296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.76388914141324090193064064980051804239400489364611591656802643352961656016296
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.66410822963424560094900240242976654003632444484206099661060878576628185516635
Short name T35
Test name
Test status
Simulation time 486419183 ps
CPU time 11.92 seconds
Started Nov 22 01:51:16 PM PST 23
Finished Nov 22 01:51:30 PM PST 23
Peak memory 238756 kb
Host smart-d61972dc-0385-4cc1-a320-9b022c4c4cc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66410822963424560094900240242976654003632444484206099661060878576628185516635 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.66410822963424560094900240242976654003632444484206099661060878576628185516635
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.1972595968743554945743080080279169414680693267078023467461827671657124099943
Short name T52
Test name
Test status
Simulation time 137469183 ps
CPU time 3.57 seconds
Started Nov 22 01:51:36 PM PST 23
Finished Nov 22 01:51:44 PM PST 23
Peak memory 238700 kb
Host smart-201d28cd-e63d-48a8-8871-92995eb22f10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1972595968743554945743080080279169414680693267078023467461827671657124099943 -assert nopostproc +UVM_TEST
NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.otp_ctrl_regwen.1972595968743554945743080080279169414680693267078023467461827671657124099943
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.87151914156551921522930061434260054450151093935047442659405896067370720493790
Short name T1258
Test name
Test status
Simulation time 138839183 ps
CPU time 2.97 seconds
Started Nov 22 01:51:40 PM PST 23
Finished Nov 22 01:51:48 PM PST 23
Peak memory 238668 kb
Host smart-c198d108-0e38-4fbc-bcb7-faf5a2e4b054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87151914156551921522930061434260054450151093935047442659405896067370720493790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.otp_ctrl_smoke.87151914156551921522930061434260054450151093935047442659405896067370720493790
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.69525933667605539606915279758388594344811569873753741863028671254049412045054
Short name T1263
Test name
Test status
Simulation time 13240088340 ps
CPU time 134.3 seconds
Started Nov 22 01:51:36 PM PST 23
Finished Nov 22 01:53:55 PM PST 23
Peak memory 241820 kb
Host smart-694db2c8-24b2-4610-b702-fecf17b49516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69525933667605539606915279758388594344811569873753741863028671254049412045054 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.69525933667605539606915279758388594344811569873753741863028671254049412045054
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.40428811215163461160835951112918882439434359322419815043343857747906409750170
Short name T594
Test name
Test status
Simulation time 150268849183 ps
CPU time 1968.9 seconds
Started Nov 22 01:51:57 PM PST 23
Finished Nov 22 02:24:47 PM PST 23
Peak memory 517372 kb
Host smart-2804c245-046e-44d7-b709-49bf58de3475
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042881121516346116083
5951112918882439434359322419815043343857747906409750170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_res
et.40428811215163461160835951112918882439434359322419815043343857747906409750170
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.25413265818983340392818297102418883198384936582961809832070250719603750991486
Short name T34
Test name
Test status
Simulation time 549639183 ps
CPU time 9.25 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:57 PM PST 23
Peak memory 247024 kb
Host smart-3a13fb93-f4a7-4b00-b69e-fa28ca2ce518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25413265818983340392818297102418883198384936582961809832070250719603750991486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.otp_ctrl_test_access.25413265818983340392818297102418883198384936582961809832070250719603750991486
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.67377599163593672495694642219657242401794652820793043637613069916810781814625
Short name T682
Test name
Test status
Simulation time 71069183 ps
CPU time 1.84 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:26 PM PST 23
Peak memory 238468 kb
Host smart-b206242b-dd9b-47b5-8e2d-ff390f832b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67377599163593672495694642219657242401794652820793043637613069916810781814625 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.67377599163593672495694642219657242401794652820793043637613069916810781814625
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.105273847905309863237238107793119002386017791205465582793497975551901903127103
Short name T409
Test name
Test status
Simulation time 111269183 ps
CPU time 2.65 seconds
Started Nov 22 01:51:11 PM PST 23
Finished Nov 22 01:51:21 PM PST 23
Peak memory 246704 kb
Host smart-ff2ec7ce-795a-4d82-b7b3-684e0a4d2e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105273847905309863237238107793119002386017791205465582793497975551901903127103 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.otp_ctrl_check_fail.105273847905309863237238107793119002386017791205465582793497975551901903127103
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.5493954800046903418865163360331186467932296771077576586335965195233013385561
Short name T547
Test name
Test status
Simulation time 390019183 ps
CPU time 11.02 seconds
Started Nov 22 01:50:56 PM PST 23
Finished Nov 22 01:51:09 PM PST 23
Peak memory 238664 kb
Host smart-15c3aeb9-0ec9-4208-b1b6-ecc5e894d530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5493954800046903418865163360331186467932296771077576586335965195233013385561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.otp_ctrl_dai_errs.5493954800046903418865163360331186467932296771077576586335965195233013385561
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.40998018300994611426233494076908521301289911621787847873826633599936508741610
Short name T885
Test name
Test status
Simulation time 614979183 ps
CPU time 10.78 seconds
Started Nov 22 01:50:57 PM PST 23
Finished Nov 22 01:51:09 PM PST 23
Peak memory 238920 kb
Host smart-62994e8e-028c-4997-aba0-47d8f8d5b5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40998018300994611426233494076908521301289911621787847873826633599936508741610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.otp_ctrl_dai_lock.40998018300994611426233494076908521301289911621787847873826633599936508741610
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.95152420225809794315176776806652828435835703924223549755692285939570354006808
Short name T1174
Test name
Test status
Simulation time 156689183 ps
CPU time 3.88 seconds
Started Nov 22 01:50:57 PM PST 23
Finished Nov 22 01:51:03 PM PST 23
Peak memory 238604 kb
Host smart-70840a33-8a32-40f1-a13a-281066f761aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95152420225809794315176776806652828435835703924223549755692285939570354006808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.otp_ctrl_init_fail.95152420225809794315176776806652828435835703924223549755692285939570354006808
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.35687408160764876935822831722402740441695380244567916576690837837157511090901
Short name T431
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.05 seconds
Started Nov 22 01:50:55 PM PST 23
Finished Nov 22 01:51:15 PM PST 23
Peak memory 239028 kb
Host smart-7ed32aa5-cd3a-4ce6-96a9-f4a35d9b38f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35687408160764876935822831722402740441695380244567916576690837837157511090901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.otp_ctrl_macro_errs.35687408160764876935822831722402740441695380244567916576690837837157511090901
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.111870575306039429000265652971103050906008327337019963347618065636775547919759
Short name T963
Test name
Test status
Simulation time 346349183 ps
CPU time 7.47 seconds
Started Nov 22 01:51:36 PM PST 23
Finished Nov 22 01:51:48 PM PST 23
Peak memory 238488 kb
Host smart-41ad977a-fdfd-4b2c-bfcb-cf4f2b37ddf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111870575306039429000265652971103050906008327337019963347618065636775547919759 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.111870575306039429000265652971103050906008327337019963347618065636775547919759
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.93219354484611412420788057606861936266274296424467171753903767808533254096115
Short name T775
Test name
Test status
Simulation time 176929183 ps
CPU time 4.42 seconds
Started Nov 22 01:50:42 PM PST 23
Finished Nov 22 01:50:47 PM PST 23
Peak memory 238512 kb
Host smart-65efd91e-77a5-483c-a5b4-81ce31d444f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93219354484611412420788057606861936266274296424467171753903767808533254096115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.93219354484611412420788057606861936266274296424467171753903767808533254096115
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.76105317733946413278817730630490919280760559781277854795717299938814854537787
Short name T337
Test name
Test status
Simulation time 486419183 ps
CPU time 11.92 seconds
Started Nov 22 01:50:59 PM PST 23
Finished Nov 22 01:51:12 PM PST 23
Peak memory 238608 kb
Host smart-96ef1608-115f-40ea-b460-7096a94909f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76105317733946413278817730630490919280760559781277854795717299938814854537787 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.76105317733946413278817730630490919280760559781277854795717299938814854537787
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.72274063312583090837278344054273312259827666941851193786093269151945315189201
Short name T1311
Test name
Test status
Simulation time 137469183 ps
CPU time 3.67 seconds
Started Nov 22 01:51:28 PM PST 23
Finished Nov 22 01:51:34 PM PST 23
Peak memory 238592 kb
Host smart-e3f5b8fc-8ecc-457a-a4d1-9351ec0926b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72274063312583090837278344054273312259827666941851193786093269151945315189201 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.otp_ctrl_regwen.72274063312583090837278344054273312259827666941851193786093269151945315189201
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.100091738278416622552846925751258969523028651338390926814915349413973517216801
Short name T393
Test name
Test status
Simulation time 138839183 ps
CPU time 3.05 seconds
Started Nov 22 01:50:48 PM PST 23
Finished Nov 22 01:50:52 PM PST 23
Peak memory 238764 kb
Host smart-9ba28d3d-b077-49c6-aab7-6a071f606d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100091738278416622552846925751258969523028651338390926814915349413973517216801 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.otp_ctrl_smoke.100091738278416622552846925751258969523028651338390926814915349413973517216801
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.52726462728527591027830061315122210334720703670936385920557001895395982522243
Short name T1253
Test name
Test status
Simulation time 13240088340 ps
CPU time 134.03 seconds
Started Nov 22 01:51:02 PM PST 23
Finished Nov 22 01:53:24 PM PST 23
Peak memory 241832 kb
Host smart-b54ac229-08d6-467c-909e-7d2173dcb6cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52726462728527591027830061315122210334720703670936385920557001895395982522243 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.52726462728527591027830061315122210334720703670936385920557001895395982522243
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.108025598407495331480757568824139721316712298179832323052312717073941549984059
Short name T1089
Test name
Test status
Simulation time 150268849183 ps
CPU time 1958.46 seconds
Started Nov 22 01:50:55 PM PST 23
Finished Nov 22 02:23:34 PM PST 23
Peak memory 517472 kb
Host smart-4e6e9c47-bb2c-4ead-84cd-0cc6bc2902d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080255984074953314807
57568824139721316712298179832323052312717073941549984059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_re
set.108025598407495331480757568824139721316712298179832323052312717073941549984059
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.107907909738899713032419210099075098821801472191890372585860206214790732346607
Short name T1084
Test name
Test status
Simulation time 549639183 ps
CPU time 9.01 seconds
Started Nov 22 01:51:12 PM PST 23
Finished Nov 22 01:51:23 PM PST 23
Peak memory 246856 kb
Host smart-88aeef83-8e1f-4dcb-b0f6-4d97a08d2d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107907909738899713032419210099075098821801472191890372585860206214790732346607 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.otp_ctrl_test_access.107907909738899713032419210099075098821801472191890372585860206214790732346607
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.72351633662560784751256679221076035267165081519731068869597332665682803598200
Short name T633
Test name
Test status
Simulation time 71069183 ps
CPU time 1.8 seconds
Started Nov 22 01:51:01 PM PST 23
Finished Nov 22 01:51:03 PM PST 23
Peak memory 238464 kb
Host smart-22437a80-ff16-4f6b-af59-f02b83ab05d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72351633662560784751256679221076035267165081519731068869597332665682803598200 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.72351633662560784751256679221076035267165081519731068869597332665682803598200
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.28409298292808055319001985565048751014632209185898634794543238766946965543869
Short name T728
Test name
Test status
Simulation time 111269183 ps
CPU time 2.7 seconds
Started Nov 22 01:51:00 PM PST 23
Finished Nov 22 01:51:03 PM PST 23
Peak memory 246812 kb
Host smart-2f167d8f-9edc-4fdd-a661-73f78671517d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28409298292808055319001985565048751014632209185898634794543238766946965543869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.otp_ctrl_check_fail.28409298292808055319001985565048751014632209185898634794543238766946965543869
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.18668595906713032249319941048568947823472614191784286824640075883482208998386
Short name T1002
Test name
Test status
Simulation time 390019183 ps
CPU time 10.94 seconds
Started Nov 22 01:50:57 PM PST 23
Finished Nov 22 01:51:10 PM PST 23
Peak memory 238604 kb
Host smart-91d55571-d7a5-4148-9805-57b645ed03f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18668595906713032249319941048568947823472614191784286824640075883482208998386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.otp_ctrl_dai_errs.18668595906713032249319941048568947823472614191784286824640075883482208998386
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.19201003459944498600490276819324144358265884550697860548115162875877716353620
Short name T507
Test name
Test status
Simulation time 614979183 ps
CPU time 10.87 seconds
Started Nov 22 01:50:55 PM PST 23
Finished Nov 22 01:51:07 PM PST 23
Peak memory 238812 kb
Host smart-18f235e3-c073-4574-ab52-83df9f649b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19201003459944498600490276819324144358265884550697860548115162875877716353620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.otp_ctrl_dai_lock.19201003459944498600490276819324144358265884550697860548115162875877716353620
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.22871693801853572553381962431706996188721258219598714850878916202373809122728
Short name T675
Test name
Test status
Simulation time 156689183 ps
CPU time 4.04 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 01:51:09 PM PST 23
Peak memory 238524 kb
Host smart-f267898c-6075-43db-b774-3a05661abe02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22871693801853572553381962431706996188721258219598714850878916202373809122728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.otp_ctrl_init_fail.22871693801853572553381962431706996188721258219598714850878916202373809122728
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.84932716863582207760425955088216157349287698271399349581379763507288964531202
Short name T514
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.7 seconds
Started Nov 22 01:51:36 PM PST 23
Finished Nov 22 01:52:00 PM PST 23
Peak memory 238732 kb
Host smart-651b4db6-0d4a-4bc2-8ff1-faf47e1d048f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84932716863582207760425955088216157349287698271399349581379763507288964531202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.otp_ctrl_macro_errs.84932716863582207760425955088216157349287698271399349581379763507288964531202
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.10929649000839441976150414400629273378990718142406465504103954201258185756864
Short name T814
Test name
Test status
Simulation time 346349183 ps
CPU time 7.48 seconds
Started Nov 22 01:51:39 PM PST 23
Finished Nov 22 01:51:52 PM PST 23
Peak memory 238652 kb
Host smart-1d404f87-edab-4246-b9bc-b9eeb1de6e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10929649000839441976150414400629273378990718142406465504103954201258185756864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.otp_ctrl_parallel_key_req.10929649000839441976150414400629273378990718142406465504103954201258185756864
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.63528111740892737384326325878769783790807057844676157389134535254854421768615
Short name T1201
Test name
Test status
Simulation time 176929183 ps
CPU time 4.53 seconds
Started Nov 22 01:50:57 PM PST 23
Finished Nov 22 01:51:02 PM PST 23
Peak memory 238620 kb
Host smart-2cd19740-8618-45f3-bcd6-ae8327239cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63528111740892737384326325878769783790807057844676157389134535254854421768615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.63528111740892737384326325878769783790807057844676157389134535254854421768615
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.45742339222468664970713191704817060206999083475288323237603750569907806097871
Short name T696
Test name
Test status
Simulation time 486419183 ps
CPU time 12.2 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:37 PM PST 23
Peak memory 238628 kb
Host smart-a7e00279-cf5c-4c86-85b7-0e03cc6c4161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45742339222468664970713191704817060206999083475288323237603750569907806097871 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.45742339222468664970713191704817060206999083475288323237603750569907806097871
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.40637622009870265163669567260219864649104605832920650361143957329389119913591
Short name T646
Test name
Test status
Simulation time 137469183 ps
CPU time 3.63 seconds
Started Nov 22 01:51:04 PM PST 23
Finished Nov 22 01:51:09 PM PST 23
Peak memory 238708 kb
Host smart-5b9a2f83-9cad-494d-8592-53b2ebc9b289
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=40637622009870265163669567260219864649104605832920650361143957329389119913591 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.otp_ctrl_regwen.40637622009870265163669567260219864649104605832920650361143957329389119913591
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.101651792171611439081002643884185275789896281414592447023023076644137627848411
Short name T874
Test name
Test status
Simulation time 138839183 ps
CPU time 3.11 seconds
Started Nov 22 01:50:44 PM PST 23
Finished Nov 22 01:50:48 PM PST 23
Peak memory 238804 kb
Host smart-56b56aa0-317e-4cee-8dee-864aed68b7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101651792171611439081002643884185275789896281414592447023023076644137627848411 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.otp_ctrl_smoke.101651792171611439081002643884185275789896281414592447023023076644137627848411
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.109669161229437892614796647548410740235455168232659752742117346646938745017424
Short name T1086
Test name
Test status
Simulation time 13240088340 ps
CPU time 129.77 seconds
Started Nov 22 01:50:43 PM PST 23
Finished Nov 22 01:52:53 PM PST 23
Peak memory 241796 kb
Host smart-7ec129df-5e0f-4816-ae25-85744bfbefb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109669161229437892614796647548410740235455168232659752742117346646938745017424 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.109669161229437892614796647548410740235455168232659752742117346646938745017424
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.60681748117932919808725094806002146622034859411907110106413241556835001670835
Short name T565
Test name
Test status
Simulation time 150268849183 ps
CPU time 1908.75 seconds
Started Nov 22 01:51:04 PM PST 23
Finished Nov 22 02:22:55 PM PST 23
Peak memory 517516 kb
Host smart-ab95c15d-8537-4c81-84b3-0012e65dcac2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6068174811793291980872
5094806002146622034859411907110106413241556835001670835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_res
et.60681748117932919808725094806002146622034859411907110106413241556835001670835
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.45268808764219231544770534962011669052263195375191458890348888662495351062417
Short name T958
Test name
Test status
Simulation time 549639183 ps
CPU time 9.14 seconds
Started Nov 22 01:51:05 PM PST 23
Finished Nov 22 01:51:16 PM PST 23
Peak memory 247024 kb
Host smart-32e274ea-8c53-4ca9-9904-7271626f243f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45268808764219231544770534962011669052263195375191458890348888662495351062417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.otp_ctrl_test_access.45268808764219231544770534962011669052263195375191458890348888662495351062417
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.24650380826704982060761769435674843925315710336224238046104144928189492577972
Short name T480
Test name
Test status
Simulation time 71069183 ps
CPU time 1.83 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:49 PM PST 23
Peak memory 238436 kb
Host smart-bd5b0638-5389-4d5e-b01c-ac76e6aa594f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24650380826704982060761769435674843925315710336224238046104144928189492577972 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.24650380826704982060761769435674843925315710336224238046104144928189492577972
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.40664215785656524356351225733034535621670218063318618679888224324773266712825
Short name T805
Test name
Test status
Simulation time 111269183 ps
CPU time 2.77 seconds
Started Nov 22 01:51:38 PM PST 23
Finished Nov 22 01:51:46 PM PST 23
Peak memory 246700 kb
Host smart-1c802ec7-2f1b-40cd-bff2-386cf1953157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40664215785656524356351225733034535621670218063318618679888224324773266712825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.otp_ctrl_check_fail.40664215785656524356351225733034535621670218063318618679888224324773266712825
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.113068921462307621046273220907924866080796958730856270385458990431011323145803
Short name T1188
Test name
Test status
Simulation time 390019183 ps
CPU time 11.07 seconds
Started Nov 22 01:51:11 PM PST 23
Finished Nov 22 01:51:24 PM PST 23
Peak memory 238588 kb
Host smart-b6ca698e-18ee-497f-a5a9-c40058dfd750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113068921462307621046273220907924866080796958730856270385458990431011323145803 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.otp_ctrl_dai_errs.113068921462307621046273220907924866080796958730856270385458990431011323145803
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.33107006190635543704347386346133355299702938458790693098301987201647590228942
Short name T1160
Test name
Test status
Simulation time 614979183 ps
CPU time 10.3 seconds
Started Nov 22 01:51:02 PM PST 23
Finished Nov 22 01:51:14 PM PST 23
Peak memory 238832 kb
Host smart-28dc6be0-7535-437e-ad15-f4a1156cc384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33107006190635543704347386346133355299702938458790693098301987201647590228942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.otp_ctrl_dai_lock.33107006190635543704347386346133355299702938458790693098301987201647590228942
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.78643910011468849217772033417841637168328034353039623459499944117444808567989
Short name T1277
Test name
Test status
Simulation time 156689183 ps
CPU time 3.83 seconds
Started Nov 22 01:51:06 PM PST 23
Finished Nov 22 01:51:12 PM PST 23
Peak memory 238468 kb
Host smart-29892e11-2dbc-40ed-82c6-4c6109509519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78643910011468849217772033417841637168328034353039623459499944117444808567989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.otp_ctrl_init_fail.78643910011468849217772033417841637168328034353039623459499944117444808567989
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.37616177770863059206840441249783132690026519774271701863717435676951034077338
Short name T1163
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.82 seconds
Started Nov 22 01:51:28 PM PST 23
Finished Nov 22 01:51:50 PM PST 23
Peak memory 239040 kb
Host smart-dcee38b5-fe48-4d10-aa25-90530e9d1b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37616177770863059206840441249783132690026519774271701863717435676951034077338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.otp_ctrl_macro_errs.37616177770863059206840441249783132690026519774271701863717435676951034077338
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.57704688030858528865609632582098200949840657168354196971979859143257143591585
Short name T439
Test name
Test status
Simulation time 346349183 ps
CPU time 7.17 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:31 PM PST 23
Peak memory 238660 kb
Host smart-4ad77c97-e0e9-4c04-b9a6-9bd1470dbc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57704688030858528865609632582098200949840657168354196971979859143257143591585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.otp_ctrl_parallel_key_req.57704688030858528865609632582098200949840657168354196971979859143257143591585
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.43496367808415659657022497375103666873577721256915957658565814498872786971210
Short name T712
Test name
Test status
Simulation time 176929183 ps
CPU time 4.43 seconds
Started Nov 22 01:51:07 PM PST 23
Finished Nov 22 01:51:13 PM PST 23
Peak memory 238468 kb
Host smart-4845dfb3-eea3-4f5f-94e9-28fa5f4536e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43496367808415659657022497375103666873577721256915957658565814498872786971210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.43496367808415659657022497375103666873577721256915957658565814498872786971210
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.69199726004710350282119783546107530362886329207863810034844693931742173716037
Short name T311
Test name
Test status
Simulation time 486419183 ps
CPU time 12.1 seconds
Started Nov 22 01:51:17 PM PST 23
Finished Nov 22 01:51:32 PM PST 23
Peak memory 238768 kb
Host smart-e9cc9c42-9933-42b9-acca-0117664a6dbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=69199726004710350282119783546107530362886329207863810034844693931742173716037 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.69199726004710350282119783546107530362886329207863810034844693931742173716037
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.11926327008974274496961222809311381692251350948093279931508909279767428962551
Short name T1250
Test name
Test status
Simulation time 137469183 ps
CPU time 3.61 seconds
Started Nov 22 01:51:24 PM PST 23
Finished Nov 22 01:51:30 PM PST 23
Peak memory 238648 kb
Host smart-c8450dbe-7f74-457a-ac22-4c980853355c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11926327008974274496961222809311381692251350948093279931508909279767428962551 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.otp_ctrl_regwen.11926327008974274496961222809311381692251350948093279931508909279767428962551
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.101422519296151288709182175375028357339793492543670693148613547936538560584856
Short name T291
Test name
Test status
Simulation time 138839183 ps
CPU time 3.05 seconds
Started Nov 22 01:51:18 PM PST 23
Finished Nov 22 01:51:24 PM PST 23
Peak memory 238788 kb
Host smart-c1df27dc-6eea-4a7e-838d-b5eacab1499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101422519296151288709182175375028357339793492543670693148613547936538560584856 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.otp_ctrl_smoke.101422519296151288709182175375028357339793492543670693148613547936538560584856
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.105941137409665514455181869136677811600071781639051002003591785940914145176473
Short name T68
Test name
Test status
Simulation time 13240088340 ps
CPU time 131.37 seconds
Started Nov 22 01:51:17 PM PST 23
Finished Nov 22 01:53:30 PM PST 23
Peak memory 241724 kb
Host smart-862524af-1b5d-4fce-9a67-985ed5c020f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105941137409665514455181869136677811600071781639051002003591785940914145176473 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.105941137409665514455181869136677811600071781639051002003591785940914145176473
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.42516115651063425921837203916056048762330199540714877805726960205766503949939
Short name T645
Test name
Test status
Simulation time 150268849183 ps
CPU time 1957.26 seconds
Started Nov 22 01:51:40 PM PST 23
Finished Nov 22 02:24:22 PM PST 23
Peak memory 517520 kb
Host smart-7ae49920-6b5e-46be-8e3a-0877f256dfd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251611565106342592183
7203916056048762330199540714877805726960205766503949939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_res
et.42516115651063425921837203916056048762330199540714877805726960205766503949939
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.71490564923929994261472501967710087961128521961985141464458324422347093640659
Short name T456
Test name
Test status
Simulation time 549639183 ps
CPU time 9.1 seconds
Started Nov 22 01:51:41 PM PST 23
Finished Nov 22 01:51:55 PM PST 23
Peak memory 246976 kb
Host smart-5f123b1b-bf18-4eaf-860a-baec60d5e90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71490564923929994261472501967710087961128521961985141464458324422347093640659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.otp_ctrl_test_access.71490564923929994261472501967710087961128521961985141464458324422347093640659
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.41942261169219019279627970734508112312868473680638409926683671690066308856430
Short name T991
Test name
Test status
Simulation time 71069183 ps
CPU time 1.84 seconds
Started Nov 22 01:51:53 PM PST 23
Finished Nov 22 01:51:57 PM PST 23
Peak memory 238280 kb
Host smart-c852239e-d55e-4fed-8eb5-7c9eead4935f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41942261169219019279627970734508112312868473680638409926683671690066308856430 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.41942261169219019279627970734508112312868473680638409926683671690066308856430
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.55878800448206615231151612151120274587061649950835960301419971419324322950135
Short name T1152
Test name
Test status
Simulation time 111269183 ps
CPU time 2.65 seconds
Started Nov 22 01:51:17 PM PST 23
Finished Nov 22 01:51:22 PM PST 23
Peak memory 246820 kb
Host smart-f6776652-5457-48db-b91a-465bd2fac78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55878800448206615231151612151120274587061649950835960301419971419324322950135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.otp_ctrl_check_fail.55878800448206615231151612151120274587061649950835960301419971419324322950135
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.102736883664388716834065661941903616658184095627145174767458327294239214733058
Short name T1308
Test name
Test status
Simulation time 390019183 ps
CPU time 10.52 seconds
Started Nov 22 01:51:55 PM PST 23
Finished Nov 22 01:52:07 PM PST 23
Peak memory 238420 kb
Host smart-794f2abe-e7d8-4d0c-9181-4a0d9bab1dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102736883664388716834065661941903616658184095627145174767458327294239214733058 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.otp_ctrl_dai_errs.102736883664388716834065661941903616658184095627145174767458327294239214733058
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.24406478426697494234033049520350615008503557945939331761566949165206425054264
Short name T989
Test name
Test status
Simulation time 614979183 ps
CPU time 10.53 seconds
Started Nov 22 01:51:35 PM PST 23
Finished Nov 22 01:51:49 PM PST 23
Peak memory 238784 kb
Host smart-883e0964-e3e0-45d3-992a-43ea650c9724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24406478426697494234033049520350615008503557945939331761566949165206425054264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.otp_ctrl_dai_lock.24406478426697494234033049520350615008503557945939331761566949165206425054264
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.4311000902040397383007666579684447152450688367496577465823695583156608872822
Short name T745
Test name
Test status
Simulation time 156689183 ps
CPU time 4.07 seconds
Started Nov 22 01:51:39 PM PST 23
Finished Nov 22 01:51:49 PM PST 23
Peak memory 238612 kb
Host smart-2d3c87c0-a906-4784-9b6d-0100217c6db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4311000902040397383007666579684447152450688367496577465823695583156608872822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.otp_ctrl_init_fail.4311000902040397383007666579684447152450688367496577465823695583156608872822
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.22106414888744857858348761104826690246473785896102790220772153369108751968503
Short name T792
Test name
Test status
Simulation time 346349183 ps
CPU time 7.55 seconds
Started Nov 22 01:51:23 PM PST 23
Finished Nov 22 01:51:32 PM PST 23
Peak memory 238644 kb
Host smart-71a5eafd-20ec-4656-9b72-4be3db89d814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22106414888744857858348761104826690246473785896102790220772153369108751968503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.otp_ctrl_parallel_key_req.22106414888744857858348761104826690246473785896102790220772153369108751968503
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.58544779718686636924783921183751093589449897536886627172187257731479081909532
Short name T586
Test name
Test status
Simulation time 176929183 ps
CPU time 4.41 seconds
Started Nov 22 01:51:36 PM PST 23
Finished Nov 22 01:51:45 PM PST 23
Peak memory 238676 kb
Host smart-0a591fee-9516-4899-8893-192340fc6356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58544779718686636924783921183751093589449897536886627172187257731479081909532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.58544779718686636924783921183751093589449897536886627172187257731479081909532
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.57669960062483642934927176029529055447427212143662650646411600286452356168586
Short name T776
Test name
Test status
Simulation time 486419183 ps
CPU time 11.47 seconds
Started Nov 22 01:51:46 PM PST 23
Finished Nov 22 01:52:01 PM PST 23
Peak memory 238628 kb
Host smart-92d21962-dfd7-45d4-abf3-c9e2eb616711
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57669960062483642934927176029529055447427212143662650646411600286452356168586 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.57669960062483642934927176029529055447427212143662650646411600286452356168586
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.42788068073030307680411452236374369865425878684462353777483965100407660747844
Short name T858
Test name
Test status
Simulation time 137469183 ps
CPU time 3.64 seconds
Started Nov 22 01:51:38 PM PST 23
Finished Nov 22 01:51:47 PM PST 23
Peak memory 238664 kb
Host smart-7227c9f8-603d-44fe-9ea7-7fb931a59a32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=42788068073030307680411452236374369865425878684462353777483965100407660747844 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.otp_ctrl_regwen.42788068073030307680411452236374369865425878684462353777483965100407660747844
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.71301050412232392628010464375126096627724481141914103120647600923517765366117
Short name T261
Test name
Test status
Simulation time 138839183 ps
CPU time 3.15 seconds
Started Nov 22 01:51:29 PM PST 23
Finished Nov 22 01:51:35 PM PST 23
Peak memory 238796 kb
Host smart-f03231f8-f15a-4010-ade4-a009b41c859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71301050412232392628010464375126096627724481141914103120647600923517765366117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.otp_ctrl_smoke.71301050412232392628010464375126096627724481141914103120647600923517765366117
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.86627184408660240648336663484980876478254797524205614841850417173838448375127
Short name T1072
Test name
Test status
Simulation time 13240088340 ps
CPU time 133.57 seconds
Started Nov 22 01:51:37 PM PST 23
Finished Nov 22 01:53:55 PM PST 23
Peak memory 241904 kb
Host smart-de4c1d2d-fdc2-4871-aff5-6b2994dad901
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86627184408660240648336663484980876478254797524205614841850417173838448375127 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.86627184408660240648336663484980876478254797524205614841850417173838448375127
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.1102751951228591357264420445556596245489913044517993875992272315654420511437
Short name T267
Test name
Test status
Simulation time 150268849183 ps
CPU time 1951.1 seconds
Started Nov 22 01:51:45 PM PST 23
Finished Nov 22 02:24:20 PM PST 23
Peak memory 517592 kb
Host smart-5dcca0be-b72d-4b4b-b8c3-7c7234a21f6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102751951228591357264
420445556596245489913044517993875992272315654420511437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_rese
t.1102751951228591357264420445556596245489913044517993875992272315654420511437
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.49520970265169883900534282368526676807865891707460836797519822309248992021913
Short name T1231
Test name
Test status
Simulation time 549639183 ps
CPU time 8.88 seconds
Started Nov 22 01:51:40 PM PST 23
Finished Nov 22 01:51:54 PM PST 23
Peak memory 246860 kb
Host smart-ec61b13b-fe3a-40ee-9e2a-b2e50d577a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49520970265169883900534282368526676807865891707460836797519822309248992021913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.otp_ctrl_test_access.49520970265169883900534282368526676807865891707460836797519822309248992021913
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.49077045009402507525825627429908360206509478424025954237038142644123946785367
Short name T429
Test name
Test status
Simulation time 71069183 ps
CPU time 1.87 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:16 PM PST 23
Peak memory 238420 kb
Host smart-14a319ee-cd76-4f6b-a637-b11ef6638b6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49077045009402507525825627429908360206509478424025954237038142644123946785367 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.49077045009402507525825627429908360206509478424025954237038142644123946785367
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.95022686661146844546210203462353017424238836834212086889429088080616154380591
Short name T1069
Test name
Test status
Simulation time 190889183 ps
CPU time 4.79 seconds
Started Nov 22 01:50:00 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 238812 kb
Host smart-28a0322b-90f6-4ffb-93d6-49f3ec3ea686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95022686661146844546210203462353017424238836834212086889429088080616154380591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.otp_ctrl_background_chks.95022686661146844546210203462353017424238836834212086889429088080616154380591
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.3811388167009339019159933165770427296662984470415706023961062622368173247143
Short name T1033
Test name
Test status
Simulation time 111269183 ps
CPU time 2.68 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 246772 kb
Host smart-da38a2da-9992-43c3-8d66-0681caf4af7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811388167009339019159933165770427296662984470415706023961062622368173247143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.otp_ctrl_check_fail.3811388167009339019159933165770427296662984470415706023961062622368173247143
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.76417795710334206964162492010371578176104713661391021772744101367263089328633
Short name T1232
Test name
Test status
Simulation time 390019183 ps
CPU time 10.69 seconds
Started Nov 22 01:50:14 PM PST 23
Finished Nov 22 01:50:29 PM PST 23
Peak memory 238636 kb
Host smart-ce65e7d9-658a-45a9-911f-969d3c4e30d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76417795710334206964162492010371578176104713661391021772744101367263089328633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.otp_ctrl_dai_errs.76417795710334206964162492010371578176104713661391021772744101367263089328633
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.5319033168367304644085528855842115293640370319076475125724264905667833639346
Short name T904
Test name
Test status
Simulation time 614979183 ps
CPU time 10.58 seconds
Started Nov 22 01:50:10 PM PST 23
Finished Nov 22 01:50:28 PM PST 23
Peak memory 238836 kb
Host smart-6f3e0924-9b79-4f77-826f-ee2de0393098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5319033168367304644085528855842115293640370319076475125724264905667833639346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.otp_ctrl_dai_lock.5319033168367304644085528855842115293640370319076475125724264905667833639346
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.77867154872088414213604530531935834701066066501610624785466810867428774063246
Short name T605
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:09 PM PST 23
Peak memory 238624 kb
Host smart-6ee2f0fc-8472-463a-a414-f678c88fc443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77867154872088414213604530531935834701066066501610624785466810867428774063246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.otp_ctrl_init_fail.77867154872088414213604530531935834701066066501610624785466810867428774063246
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.82131772629997424707548107409131597878135564742042839663576357974103862972335
Short name T260
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.13 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:23 PM PST 23
Peak memory 239008 kb
Host smart-4815d62f-1a9d-4b2c-aa1d-5c8ce04d7651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82131772629997424707548107409131597878135564742042839663576357974103862972335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.otp_ctrl_macro_errs.82131772629997424707548107409131597878135564742042839663576357974103862972335
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.33655860297169147238968489605362000994362692643074647126620971446417856653146
Short name T303
Test name
Test status
Simulation time 176929183 ps
CPU time 4.32 seconds
Started Nov 22 01:50:04 PM PST 23
Finished Nov 22 01:50:11 PM PST 23
Peak memory 238588 kb
Host smart-b882130c-59a6-45de-ad21-8dc9ca9e1b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33655860297169147238968489605362000994362692643074647126620971446417856653146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.33655860297169147238968489605362000994362692643074647126620971446417856653146
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.56379870044427273187385832208517250719205112054552440534291116440021380900745
Short name T394
Test name
Test status
Simulation time 486419183 ps
CPU time 12.17 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:17 PM PST 23
Peak memory 238704 kb
Host smart-80ef9525-c7d7-4d04-9b1a-bed834d9c70c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56379870044427273187385832208517250719205112054552440534291116440021380900745 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.56379870044427273187385832208517250719205112054552440534291116440021380900745
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.70391449483737676331869196039310087074475613032889286275115982066742210663448
Short name T1123
Test name
Test status
Simulation time 137469183 ps
CPU time 3.53 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 01:50:12 PM PST 23
Peak memory 238672 kb
Host smart-e72a2ede-f68a-404b-a603-90bb18dac85a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70391449483737676331869196039310087074475613032889286275115982066742210663448 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_regwen.70391449483737676331869196039310087074475613032889286275115982066742210663448
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.22246794033383638121769670715492639977621265226253532479049179314120185490287
Short name T92
Test name
Test status
Simulation time 138839183 ps
CPU time 3.09 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:16 PM PST 23
Peak memory 238920 kb
Host smart-927524af-8330-42cc-8b0d-d2efdaace544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22246794033383638121769670715492639977621265226253532479049179314120185490287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.otp_ctrl_smoke.22246794033383638121769670715492639977621265226253532479049179314120185490287
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.11120534447299725794603915825595788675672964542785904842224344812506787553356
Short name T72
Test name
Test status
Simulation time 13240088340 ps
CPU time 134.88 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 01:52:23 PM PST 23
Peak memory 241728 kb
Host smart-1aa5ae88-6bac-4ea2-9e6f-4858bbd7db2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11120534447299725794603915825595788675672964542785904842224344812506787553356 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.11120534447299725794603915825595788675672964542785904842224344812506787553356
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.68605418987483729697920986025847519347693561416041588502448789712624297755197
Short name T1054
Test name
Test status
Simulation time 150268849183 ps
CPU time 1999.15 seconds
Started Nov 22 01:49:59 PM PST 23
Finished Nov 22 02:23:21 PM PST 23
Peak memory 517556 kb
Host smart-60b5a2b6-b5bd-45ef-8df7-f02acb801ff6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6860541898748372969792
0986025847519347693561416041588502448789712624297755197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_rese
t.68605418987483729697920986025847519347693561416041588502448789712624297755197
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.94435544044839104682030338620284095909327216712643727081179456785065928588749
Short name T347
Test name
Test status
Simulation time 549639183 ps
CPU time 8.96 seconds
Started Nov 22 01:50:06 PM PST 23
Finished Nov 22 01:50:18 PM PST 23
Peak memory 246968 kb
Host smart-be9d501e-a2cd-4927-80b1-dc2384842bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94435544044839104682030338620284095909327216712643727081179456785065928588749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.otp_ctrl_test_access.94435544044839104682030338620284095909327216712643727081179456785065928588749
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.19924145162138274509291123172760905929216424507420550471942367612690059685185
Short name T807
Test name
Test status
Simulation time 71069183 ps
CPU time 1.78 seconds
Started Nov 22 01:51:54 PM PST 23
Finished Nov 22 01:51:58 PM PST 23
Peak memory 238368 kb
Host smart-1f661b18-ec4e-4dfd-b440-877025f1a7c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19924145162138274509291123172760905929216424507420550471942367612690059685185 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.19924145162138274509291123172760905929216424507420550471942367612690059685185
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.93047401665979491608225666519637235387421916473220201754779801571314161312469
Short name T1085
Test name
Test status
Simulation time 111269183 ps
CPU time 2.72 seconds
Started Nov 22 01:51:50 PM PST 23
Finished Nov 22 01:51:54 PM PST 23
Peak memory 246684 kb
Host smart-de0009c2-b4c4-4c06-b1c9-13a0cd721d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93047401665979491608225666519637235387421916473220201754779801571314161312469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.otp_ctrl_check_fail.93047401665979491608225666519637235387421916473220201754779801571314161312469
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.72237049814724506776994845513926022756442896316208644368356823849934205761403
Short name T569
Test name
Test status
Simulation time 390019183 ps
CPU time 11.17 seconds
Started Nov 22 01:51:35 PM PST 23
Finished Nov 22 01:51:50 PM PST 23
Peak memory 238636 kb
Host smart-8e5b9e3d-5a22-43ab-b66a-9e1ff3f7316c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72237049814724506776994845513926022756442896316208644368356823849934205761403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.otp_ctrl_dai_errs.72237049814724506776994845513926022756442896316208644368356823849934205761403
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.4681873479519704887927134419926099760976877259802480136647579474180810438007
Short name T1116
Test name
Test status
Simulation time 614979183 ps
CPU time 10.35 seconds
Started Nov 22 01:51:55 PM PST 23
Finished Nov 22 01:52:07 PM PST 23
Peak memory 238596 kb
Host smart-30651cc2-e3ef-4b53-a9d2-accc6abbb8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4681873479519704887927134419926099760976877259802480136647579474180810438007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.otp_ctrl_dai_lock.4681873479519704887927134419926099760976877259802480136647579474180810438007
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.56269110978267768872783542915686062973789076857946147813898438259219864862295
Short name T856
Test name
Test status
Simulation time 156689183 ps
CPU time 3.97 seconds
Started Nov 22 01:51:46 PM PST 23
Finished Nov 22 01:51:53 PM PST 23
Peak memory 238612 kb
Host smart-6f8fb861-5790-4244-8512-c59c2f830757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56269110978267768872783542915686062973789076857946147813898438259219864862295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.otp_ctrl_init_fail.56269110978267768872783542915686062973789076857946147813898438259219864862295
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.84258639709582651657959275021212427853261700205734444076274427068746878314825
Short name T984
Test name
Test status
Simulation time 1137629183 ps
CPU time 18.77 seconds
Started Nov 22 01:51:44 PM PST 23
Finished Nov 22 01:52:06 PM PST 23
Peak memory 238972 kb
Host smart-c4cb2af7-dc04-4d44-802a-76dd963fc153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84258639709582651657959275021212427853261700205734444076274427068746878314825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.otp_ctrl_macro_errs.84258639709582651657959275021212427853261700205734444076274427068746878314825
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.37148410397562033294567156669584957361359091954108146209750727740866247569889
Short name T1082
Test name
Test status
Simulation time 346349183 ps
CPU time 7.65 seconds
Started Nov 22 01:51:51 PM PST 23
Finished Nov 22 01:52:00 PM PST 23
Peak memory 238648 kb
Host smart-0b5bd8f0-c30f-4f45-b2ef-e249000f43a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37148410397562033294567156669584957361359091954108146209750727740866247569889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.otp_ctrl_parallel_key_req.37148410397562033294567156669584957361359091954108146209750727740866247569889
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.10133000377995055092736409995932961103569042875347559059141686727083009579405
Short name T222
Test name
Test status
Simulation time 176929183 ps
CPU time 4.12 seconds
Started Nov 22 01:51:57 PM PST 23
Finished Nov 22 01:52:02 PM PST 23
Peak memory 238484 kb
Host smart-d3c77a1d-815a-42b9-9300-ab56852f577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10133000377995055092736409995932961103569042875347559059141686727083009579405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.10133000377995055092736409995932961103569042875347559059141686727083009579405
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.91040305582271694385895434420856562154048122336753373481325313877268729069504
Short name T587
Test name
Test status
Simulation time 486419183 ps
CPU time 11.39 seconds
Started Nov 22 01:51:32 PM PST 23
Finished Nov 22 01:51:47 PM PST 23
Peak memory 238716 kb
Host smart-7fb8cf8c-084b-4beb-99c1-4dbd585c33ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91040305582271694385895434420856562154048122336753373481325313877268729069504 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.91040305582271694385895434420856562154048122336753373481325313877268729069504
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.42195739924354283853143842285906719741460644128004416684155230560585731767758
Short name T1029
Test name
Test status
Simulation time 137469183 ps
CPU time 3.72 seconds
Started Nov 22 01:51:57 PM PST 23
Finished Nov 22 01:52:01 PM PST 23
Peak memory 238696 kb
Host smart-3258070e-a653-4a9f-a3fe-52dbf911928a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=42195739924354283853143842285906719741460644128004416684155230560585731767758 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.otp_ctrl_regwen.42195739924354283853143842285906719741460644128004416684155230560585731767758
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.59506424601608717214889869046917063944968658569227403751043517462204023323792
Short name T859
Test name
Test status
Simulation time 138839183 ps
CPU time 2.98 seconds
Started Nov 22 01:51:54 PM PST 23
Finished Nov 22 01:51:59 PM PST 23
Peak memory 238732 kb
Host smart-703dc5f8-f524-430b-8be6-a2dbbb062b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59506424601608717214889869046917063944968658569227403751043517462204023323792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.otp_ctrl_smoke.59506424601608717214889869046917063944968658569227403751043517462204023323792
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.5698009205608573659886855808267737928863849199607072486362382193648054312351
Short name T1003
Test name
Test status
Simulation time 13240088340 ps
CPU time 128.04 seconds
Started Nov 22 01:51:56 PM PST 23
Finished Nov 22 01:54:06 PM PST 23
Peak memory 241620 kb
Host smart-cc1b3e4f-00e6-42ac-a289-1df4873f1998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5698009205608573659886855808267737928863849199607072486362382193648054312351 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.5698009205608573659886855808267737928863849199607072486362382193648054312351
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.30136443311012368752035792022922908379840168985278041418148096932233977645446
Short name T1226
Test name
Test status
Simulation time 150268849183 ps
CPU time 1958.56 seconds
Started Nov 22 01:51:28 PM PST 23
Finished Nov 22 02:24:10 PM PST 23
Peak memory 517592 kb
Host smart-a1339cd3-50a8-4bf1-83ce-4c7c39b840e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013644331101236875203
5792022922908379840168985278041418148096932233977645446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_res
et.30136443311012368752035792022922908379840168985278041418148096932233977645446
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.70510314626304453300537679606937365217652993705679888209316877406191984727503
Short name T22
Test name
Test status
Simulation time 549639183 ps
CPU time 8.55 seconds
Started Nov 22 01:51:34 PM PST 23
Finished Nov 22 01:51:47 PM PST 23
Peak memory 246784 kb
Host smart-d6f88bdb-ee38-4b1d-bc93-de790f4cfffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70510314626304453300537679606937365217652993705679888209316877406191984727503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.otp_ctrl_test_access.70510314626304453300537679606937365217652993705679888209316877406191984727503
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.54694606303605529204622899019658806567686810933967055394037806809456485801644
Short name T1052
Test name
Test status
Simulation time 71069183 ps
CPU time 1.86 seconds
Started Nov 22 01:51:08 PM PST 23
Finished Nov 22 01:51:12 PM PST 23
Peak memory 238464 kb
Host smart-94b87a6a-5605-4e8f-ba3c-8743851d69a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54694606303605529204622899019658806567686810933967055394037806809456485801644 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.54694606303605529204622899019658806567686810933967055394037806809456485801644
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.58624376531893202195574521491919303553756358049527108450798671354328926066077
Short name T892
Test name
Test status
Simulation time 111269183 ps
CPU time 2.65 seconds
Started Nov 22 01:51:02 PM PST 23
Finished Nov 22 01:51:07 PM PST 23
Peak memory 246808 kb
Host smart-0c25c647-aee8-495b-a4ab-f54f9488605f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58624376531893202195574521491919303553756358049527108450798671354328926066077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.otp_ctrl_check_fail.58624376531893202195574521491919303553756358049527108450798671354328926066077
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.41602473873514854182010827387837147742988751634817025007264337937230310591379
Short name T367
Test name
Test status
Simulation time 390019183 ps
CPU time 10.51 seconds
Started Nov 22 01:51:14 PM PST 23
Finished Nov 22 01:51:27 PM PST 23
Peak memory 238548 kb
Host smart-40afd670-0173-43ec-be19-d08a4315cf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41602473873514854182010827387837147742988751634817025007264337937230310591379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.otp_ctrl_dai_errs.41602473873514854182010827387837147742988751634817025007264337937230310591379
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.44929691545579524482039705070909360200680817034327161198537822405701717237102
Short name T1014
Test name
Test status
Simulation time 614979183 ps
CPU time 10.22 seconds
Started Nov 22 01:51:05 PM PST 23
Finished Nov 22 01:51:17 PM PST 23
Peak memory 238788 kb
Host smart-4bafcae6-7f16-4782-a404-ad3d6020f4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44929691545579524482039705070909360200680817034327161198537822405701717237102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.otp_ctrl_dai_lock.44929691545579524482039705070909360200680817034327161198537822405701717237102
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.94642328645963530754806347078496407670262782534418802302694916963394323944019
Short name T1265
Test name
Test status
Simulation time 156689183 ps
CPU time 4.17 seconds
Started Nov 22 01:51:01 PM PST 23
Finished Nov 22 01:51:07 PM PST 23
Peak memory 238648 kb
Host smart-f0cecd13-fe49-4545-96f5-da384c599640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94642328645963530754806347078496407670262782534418802302694916963394323944019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.otp_ctrl_init_fail.94642328645963530754806347078496407670262782534418802302694916963394323944019
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.64166056115464116415134380948691467861018779012971206950952382529701121773770
Short name T273
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.27 seconds
Started Nov 22 01:51:28 PM PST 23
Finished Nov 22 01:51:50 PM PST 23
Peak memory 239024 kb
Host smart-9ffd4181-7c70-4618-ad06-5d8be3ca20fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64166056115464116415134380948691467861018779012971206950952382529701121773770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.otp_ctrl_macro_errs.64166056115464116415134380948691467861018779012971206950952382529701121773770
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.4937806777099470474348819381659111765193577367147938777701661144157328061452
Short name T771
Test name
Test status
Simulation time 346349183 ps
CPU time 7.5 seconds
Started Nov 22 01:51:16 PM PST 23
Finished Nov 22 01:51:25 PM PST 23
Peak memory 238784 kb
Host smart-f43dc306-adeb-4a70-a930-c43ce5b8edee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4937806777099470474348819381659111765193577367147938777701661144157328061452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 41.otp_ctrl_parallel_key_req.4937806777099470474348819381659111765193577367147938777701661144157328061452
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.52058597880471820407628076272616312586520232528383852792614833318567683867622
Short name T553
Test name
Test status
Simulation time 176929183 ps
CPU time 4.35 seconds
Started Nov 22 01:51:01 PM PST 23
Finished Nov 22 01:51:06 PM PST 23
Peak memory 238512 kb
Host smart-936870c7-15b2-4202-866f-b16cbed88f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52058597880471820407628076272616312586520232528383852792614833318567683867622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.52058597880471820407628076272616312586520232528383852792614833318567683867622
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.57307949636096018853356736405615161793456852656208222651498329599798345289981
Short name T350
Test name
Test status
Simulation time 486419183 ps
CPU time 11.98 seconds
Started Nov 22 01:50:59 PM PST 23
Finished Nov 22 01:51:12 PM PST 23
Peak memory 238600 kb
Host smart-e85612ef-dc72-4e0e-92c1-ccccf480e2a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57307949636096018853356736405615161793456852656208222651498329599798345289981 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.57307949636096018853356736405615161793456852656208222651498329599798345289981
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.49761792998101039533207930777918131659715595034817013787368449119217353008454
Short name T458
Test name
Test status
Simulation time 137469183 ps
CPU time 3.67 seconds
Started Nov 22 01:51:20 PM PST 23
Finished Nov 22 01:51:26 PM PST 23
Peak memory 238688 kb
Host smart-fc67d37d-1494-4acf-9679-3b22f4dca797
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49761792998101039533207930777918131659715595034817013787368449119217353008454 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.otp_ctrl_regwen.49761792998101039533207930777918131659715595034817013787368449119217353008454
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.72032938198594152609722022210031040297039059181495399415420797848697182675789
Short name T677
Test name
Test status
Simulation time 138839183 ps
CPU time 3.16 seconds
Started Nov 22 01:51:25 PM PST 23
Finished Nov 22 01:51:31 PM PST 23
Peak memory 238760 kb
Host smart-f23f814e-d3a2-4033-9ff0-b891a07d839c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72032938198594152609722022210031040297039059181495399415420797848697182675789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.otp_ctrl_smoke.72032938198594152609722022210031040297039059181495399415420797848697182675789
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.17979413408486049970026483914718930078828951654646185776336340532288234222883
Short name T71
Test name
Test status
Simulation time 13240088340 ps
CPU time 128.01 seconds
Started Nov 22 01:51:06 PM PST 23
Finished Nov 22 01:53:16 PM PST 23
Peak memory 241800 kb
Host smart-39b4b62b-7842-40dd-809a-0d341d703901
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17979413408486049970026483914718930078828951654646185776336340532288234222883 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.17979413408486049970026483914718930078828951654646185776336340532288234222883
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.38256429051064674233192429209123708845165682419481583064886052588592294020969
Short name T793
Test name
Test status
Simulation time 150268849183 ps
CPU time 1937.53 seconds
Started Nov 22 01:51:18 PM PST 23
Finished Nov 22 02:23:39 PM PST 23
Peak memory 517596 kb
Host smart-203e41d7-c62f-48ac-a37d-2576203fd8f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825642905106467423319
2429209123708845165682419481583064886052588592294020969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_res
et.38256429051064674233192429209123708845165682419481583064886052588592294020969
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.44451916821505258193031182144451333999473748176810362946026695497015916976719
Short name T1066
Test name
Test status
Simulation time 549639183 ps
CPU time 8.86 seconds
Started Nov 22 01:51:10 PM PST 23
Finished Nov 22 01:51:20 PM PST 23
Peak memory 246912 kb
Host smart-cb5f9dc2-f117-44f4-b3b2-aff448ff3a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44451916821505258193031182144451333999473748176810362946026695497015916976719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.otp_ctrl_test_access.44451916821505258193031182144451333999473748176810362946026695497015916976719
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.1956775512417628564090977352119128270351051031592058464719333937163560881312
Short name T252
Test name
Test status
Simulation time 71069183 ps
CPU time 1.85 seconds
Started Nov 22 01:51:19 PM PST 23
Finished Nov 22 01:51:24 PM PST 23
Peak memory 238464 kb
Host smart-559fd46b-5d50-4f33-83d5-81c4a37aac46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956775512417628564090977352119128270351051031592058464719333937163560881312 -assert nopostpro
c +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.1956775512417628564090977352119128270351051031592058464719333937163560881312
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.93700912628347787853145171469074646708500216711242779298113285583025258264924
Short name T98
Test name
Test status
Simulation time 111269183 ps
CPU time 2.62 seconds
Started Nov 22 01:51:25 PM PST 23
Finished Nov 22 01:51:31 PM PST 23
Peak memory 246812 kb
Host smart-f8216f95-b6be-4965-a157-19075be0e67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93700912628347787853145171469074646708500216711242779298113285583025258264924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.otp_ctrl_check_fail.93700912628347787853145171469074646708500216711242779298113285583025258264924
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.80062551960311472072353879494455602559938112189109684611399578091507011329096
Short name T516
Test name
Test status
Simulation time 390019183 ps
CPU time 10.76 seconds
Started Nov 22 01:50:58 PM PST 23
Finished Nov 22 01:51:10 PM PST 23
Peak memory 238476 kb
Host smart-b51f8ffe-fc55-4fc1-9afb-2a7c6ef7a95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80062551960311472072353879494455602559938112189109684611399578091507011329096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.otp_ctrl_dai_errs.80062551960311472072353879494455602559938112189109684611399578091507011329096
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.28676619484147034506397559510912581784049624385166590165522868704512928422372
Short name T602
Test name
Test status
Simulation time 614979183 ps
CPU time 10.88 seconds
Started Nov 22 01:51:10 PM PST 23
Finished Nov 22 01:51:22 PM PST 23
Peak memory 238816 kb
Host smart-1f17afed-a99c-4328-a28a-6253f1d3688b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28676619484147034506397559510912581784049624385166590165522868704512928422372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.otp_ctrl_dai_lock.28676619484147034506397559510912581784049624385166590165522868704512928422372
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.99027642392169371523658480184139671154336380892324544686933742663103987244013
Short name T905
Test name
Test status
Simulation time 156689183 ps
CPU time 3.96 seconds
Started Nov 22 01:51:06 PM PST 23
Finished Nov 22 01:51:12 PM PST 23
Peak memory 238644 kb
Host smart-4a3c1cfd-ed4d-4c0a-92af-c2068ed9cd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99027642392169371523658480184139671154336380892324544686933742663103987244013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.otp_ctrl_init_fail.99027642392169371523658480184139671154336380892324544686933742663103987244013
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.65471493417589436288386075845647138094449007868740975516635957331658035738621
Short name T848
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.8 seconds
Started Nov 22 01:51:25 PM PST 23
Finished Nov 22 01:51:48 PM PST 23
Peak memory 239004 kb
Host smart-2153a0fb-5d1b-4d58-be06-24c43fe76ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65471493417589436288386075845647138094449007868740975516635957331658035738621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.otp_ctrl_macro_errs.65471493417589436288386075845647138094449007868740975516635957331658035738621
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.33618022660852613550040136844325987036164130072117138311746094467064996032885
Short name T386
Test name
Test status
Simulation time 346349183 ps
CPU time 7.51 seconds
Started Nov 22 01:51:19 PM PST 23
Finished Nov 22 01:51:29 PM PST 23
Peak memory 238764 kb
Host smart-e8d1b509-8098-4f57-acbb-4cc49e137bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33618022660852613550040136844325987036164130072117138311746094467064996032885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.otp_ctrl_parallel_key_req.33618022660852613550040136844325987036164130072117138311746094467064996032885
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.71227390644960806409631881674140098605619069380848354655865232028546066741838
Short name T738
Test name
Test status
Simulation time 176929183 ps
CPU time 4.23 seconds
Started Nov 22 01:51:19 PM PST 23
Finished Nov 22 01:51:26 PM PST 23
Peak memory 238544 kb
Host smart-9f610d32-0051-4530-8277-158f5aff5a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71227390644960806409631881674140098605619069380848354655865232028546066741838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.71227390644960806409631881674140098605619069380848354655865232028546066741838
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.99263581394849577034588585263492285731050719637166432488839140198999403894298
Short name T657
Test name
Test status
Simulation time 486419183 ps
CPU time 11.75 seconds
Started Nov 22 01:51:00 PM PST 23
Finished Nov 22 01:51:12 PM PST 23
Peak memory 238688 kb
Host smart-82718fc0-b7e8-46c4-89b3-bb9434de86dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99263581394849577034588585263492285731050719637166432488839140198999403894298 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.99263581394849577034588585263492285731050719637166432488839140198999403894298
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.83238118327858441092523167463850649032325474735659587789214255442042930275286
Short name T873
Test name
Test status
Simulation time 137469183 ps
CPU time 3.66 seconds
Started Nov 22 01:51:07 PM PST 23
Finished Nov 22 01:51:13 PM PST 23
Peak memory 238724 kb
Host smart-24b1f826-27fe-4cf3-bf44-54fe0f24a6fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83238118327858441092523167463850649032325474735659587789214255442042930275286 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.otp_ctrl_regwen.83238118327858441092523167463850649032325474735659587789214255442042930275286
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.113634430609008571851016618288450009020185959582317289464556592048002603423520
Short name T1291
Test name
Test status
Simulation time 138839183 ps
CPU time 3.17 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:50 PM PST 23
Peak memory 238800 kb
Host smart-856f6fc3-94b3-4670-99e2-2f8d75441813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113634430609008571851016618288450009020185959582317289464556592048002603423520 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.otp_ctrl_smoke.113634430609008571851016618288450009020185959582317289464556592048002603423520
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.50648313646924281468154459330905990314900696134966575484545692777054031127876
Short name T566
Test name
Test status
Simulation time 13240088340 ps
CPU time 137.1 seconds
Started Nov 22 01:51:05 PM PST 23
Finished Nov 22 01:53:24 PM PST 23
Peak memory 241816 kb
Host smart-c2916749-a7a6-419c-875b-0906f4c89a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50648313646924281468154459330905990314900696134966575484545692777054031127876 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.50648313646924281468154459330905990314900696134966575484545692777054031127876
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.9889424249225179625924195970112913447966273782450788093538954831140654067895
Short name T853
Test name
Test status
Simulation time 150268849183 ps
CPU time 1919.07 seconds
Started Nov 22 01:51:35 PM PST 23
Finished Nov 22 02:23:38 PM PST 23
Peak memory 517624 kb
Host smart-d4da286c-4875-41c2-8f16-cd3cee7847d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9889424249225179625924
195970112913447966273782450788093538954831140654067895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_rese
t.9889424249225179625924195970112913447966273782450788093538954831140654067895
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.76123038473314791865535639694531316860776836043661571270914909339495931424574
Short name T948
Test name
Test status
Simulation time 549639183 ps
CPU time 9.16 seconds
Started Nov 22 01:51:24 PM PST 23
Finished Nov 22 01:51:36 PM PST 23
Peak memory 246960 kb
Host smart-5f4f5ce2-d9bb-4376-9f3e-854ab0445332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76123038473314791865535639694531316860776836043661571270914909339495931424574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.otp_ctrl_test_access.76123038473314791865535639694531316860776836043661571270914909339495931424574
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.43454993696636252695820020467901178704061071081840958299748146553023539735080
Short name T250
Test name
Test status
Simulation time 71069183 ps
CPU time 1.84 seconds
Started Nov 22 01:51:24 PM PST 23
Finished Nov 22 01:51:29 PM PST 23
Peak memory 238372 kb
Host smart-4458a82a-b3be-47fc-9680-afbfd6fc27a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43454993696636252695820020467901178704061071081840958299748146553023539735080 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.43454993696636252695820020467901178704061071081840958299748146553023539735080
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.28925106075468478727201508519340547646677411812557753191748771788250989233605
Short name T993
Test name
Test status
Simulation time 111269183 ps
CPU time 2.68 seconds
Started Nov 22 01:51:41 PM PST 23
Finished Nov 22 01:51:48 PM PST 23
Peak memory 246692 kb
Host smart-e796a2e8-a824-4ee7-9e62-26c23bb15397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28925106075468478727201508519340547646677411812557753191748771788250989233605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.otp_ctrl_check_fail.28925106075468478727201508519340547646677411812557753191748771788250989233605
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.86556005720924397139552004442259506724598725068132487356555381859601200213031
Short name T80
Test name
Test status
Simulation time 390019183 ps
CPU time 10.95 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:34 PM PST 23
Peak memory 238572 kb
Host smart-831b8b9b-1a0c-4e13-b9ef-d65b0108772b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86556005720924397139552004442259506724598725068132487356555381859601200213031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.otp_ctrl_dai_errs.86556005720924397139552004442259506724598725068132487356555381859601200213031
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.100624634843758722519129124080300160933488947057739900374584319739146771427954
Short name T277
Test name
Test status
Simulation time 614979183 ps
CPU time 10.65 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:35 PM PST 23
Peak memory 238632 kb
Host smart-d6c1b1e6-1297-41ba-980a-00dbd3b47284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100624634843758722519129124080300160933488947057739900374584319739146771427954 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.otp_ctrl_dai_lock.100624634843758722519129124080300160933488947057739900374584319739146771427954
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.61291563976965030668457550293347385076436226212243265859747315276552914515307
Short name T60
Test name
Test status
Simulation time 156689183 ps
CPU time 3.9 seconds
Started Nov 22 01:51:28 PM PST 23
Finished Nov 22 01:51:35 PM PST 23
Peak memory 238588 kb
Host smart-51e98b6a-e466-4428-b1fd-b73d50a464e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61291563976965030668457550293347385076436226212243265859747315276552914515307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.otp_ctrl_init_fail.61291563976965030668457550293347385076436226212243265859747315276552914515307
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.24517135052241044808223294459406003902450636874913362220887967705938630699854
Short name T903
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.5 seconds
Started Nov 22 01:51:01 PM PST 23
Finished Nov 22 01:51:21 PM PST 23
Peak memory 239024 kb
Host smart-be10730d-eb0e-4c89-a861-39f1d6a0363f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24517135052241044808223294459406003902450636874913362220887967705938630699854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.otp_ctrl_macro_errs.24517135052241044808223294459406003902450636874913362220887967705938630699854
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.79396808979093157204691177977181026981519279240524583305515608595510747389893
Short name T1269
Test name
Test status
Simulation time 346349183 ps
CPU time 7.41 seconds
Started Nov 22 01:51:01 PM PST 23
Finished Nov 22 01:51:09 PM PST 23
Peak memory 238760 kb
Host smart-1cc2c6c2-1905-481d-bf4e-c86f2ba13d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79396808979093157204691177977181026981519279240524583305515608595510747389893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.otp_ctrl_parallel_key_req.79396808979093157204691177977181026981519279240524583305515608595510747389893
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.95326750994402070072703630906428254133766830111457883096490318451462249373869
Short name T1204
Test name
Test status
Simulation time 176929183 ps
CPU time 4.29 seconds
Started Nov 22 01:51:02 PM PST 23
Finished Nov 22 01:51:08 PM PST 23
Peak memory 238676 kb
Host smart-2a7c6c08-bef7-4589-93f8-59c19815d308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95326750994402070072703630906428254133766830111457883096490318451462249373869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.95326750994402070072703630906428254133766830111457883096490318451462249373869
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.64837819899709551913284902493356040155713253330626406526809174344849018534040
Short name T1175
Test name
Test status
Simulation time 486419183 ps
CPU time 12.13 seconds
Started Nov 22 01:51:30 PM PST 23
Finished Nov 22 01:51:46 PM PST 23
Peak memory 238768 kb
Host smart-eba018ea-a2ff-4f75-b162-c75e3abe2fc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64837819899709551913284902493356040155713253330626406526809174344849018534040 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.64837819899709551913284902493356040155713253330626406526809174344849018534040
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.114235396277369425843098111915107905479799541213498171186244290810562624172780
Short name T232
Test name
Test status
Simulation time 137469183 ps
CPU time 3.77 seconds
Started Nov 22 01:51:08 PM PST 23
Finished Nov 22 01:51:14 PM PST 23
Peak memory 238700 kb
Host smart-f22c1fb8-83a1-4ec5-ae07-8387f81e4c23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114235396277369425843098111915107905479799541213498171186244290810562624172780 -assert nopostproc +UVM_TE
STNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.otp_ctrl_regwen.114235396277369425843098111915107905479799541213498171186244290810562624172780
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.100899717333383058175679179807656070738279077422217821335342000440411867941328
Short name T1223
Test name
Test status
Simulation time 138839183 ps
CPU time 2.92 seconds
Started Nov 22 01:51:04 PM PST 23
Finished Nov 22 01:51:09 PM PST 23
Peak memory 238868 kb
Host smart-ef4c7ed1-e14d-40dd-b527-05ea875f4825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100899717333383058175679179807656070738279077422217821335342000440411867941328 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.otp_ctrl_smoke.100899717333383058175679179807656070738279077422217821335342000440411867941328
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.10786900458351462717423043532804562829098075367521713892255085055864305673722
Short name T768
Test name
Test status
Simulation time 13240088340 ps
CPU time 130.26 seconds
Started Nov 22 01:51:06 PM PST 23
Finished Nov 22 01:53:18 PM PST 23
Peak memory 241748 kb
Host smart-f9f1db65-08b3-4bf8-a023-2611146f5ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10786900458351462717423043532804562829098075367521713892255085055864305673722 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.10786900458351462717423043532804562829098075367521713892255085055864305673722
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.60324305229915115262038903739140938213578375362915983018317836976215009555324
Short name T1094
Test name
Test status
Simulation time 150268849183 ps
CPU time 1906.66 seconds
Started Nov 22 01:51:06 PM PST 23
Finished Nov 22 02:22:55 PM PST 23
Peak memory 517628 kb
Host smart-d519cead-ab8a-4e67-9486-e9e5a342acd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6032430522991511526203
8903739140938213578375362915983018317836976215009555324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_res
et.60324305229915115262038903739140938213578375362915983018317836976215009555324
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.59946092683397893927832883353184443087065356713473512139433694616979417303959
Short name T654
Test name
Test status
Simulation time 549639183 ps
CPU time 8.89 seconds
Started Nov 22 01:51:36 PM PST 23
Finished Nov 22 01:51:48 PM PST 23
Peak memory 247000 kb
Host smart-0d4b72c6-4721-4395-a936-b6fe825571aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59946092683397893927832883353184443087065356713473512139433694616979417303959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.otp_ctrl_test_access.59946092683397893927832883353184443087065356713473512139433694616979417303959
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.23808071280807693640176505007046788311558793125788242939705524944400588287817
Short name T840
Test name
Test status
Simulation time 71069183 ps
CPU time 1.83 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:49 PM PST 23
Peak memory 238396 kb
Host smart-4a4f2b7c-9768-4eca-94ed-ca6b875b2a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23808071280807693640176505007046788311558793125788242939705524944400588287817 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.23808071280807693640176505007046788311558793125788242939705524944400588287817
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.19344054377925869481598549777416773623407256629738778058555122260449593330237
Short name T1032
Test name
Test status
Simulation time 111269183 ps
CPU time 2.73 seconds
Started Nov 22 01:51:41 PM PST 23
Finished Nov 22 01:51:48 PM PST 23
Peak memory 246784 kb
Host smart-53fb0f8b-34da-4a32-b984-766df02a6811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19344054377925869481598549777416773623407256629738778058555122260449593330237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.otp_ctrl_check_fail.19344054377925869481598549777416773623407256629738778058555122260449593330237
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.33059761540842946135167654508890096903082678716239162113962254312757400486136
Short name T1299
Test name
Test status
Simulation time 390019183 ps
CPU time 10.8 seconds
Started Nov 22 01:51:41 PM PST 23
Finished Nov 22 01:51:56 PM PST 23
Peak memory 238644 kb
Host smart-c61978b2-3b5a-4580-9205-0db9c7059e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33059761540842946135167654508890096903082678716239162113962254312757400486136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.otp_ctrl_dai_errs.33059761540842946135167654508890096903082678716239162113962254312757400486136
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.71036039842852690560029170881020484312376059517632137048163238961752979727599
Short name T503
Test name
Test status
Simulation time 614979183 ps
CPU time 10.23 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 01:51:14 PM PST 23
Peak memory 238808 kb
Host smart-4c25de2c-c932-4e57-ae97-39249e246996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71036039842852690560029170881020484312376059517632137048163238961752979727599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.otp_ctrl_dai_lock.71036039842852690560029170881020484312376059517632137048163238961752979727599
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.75994898118743280108660081216266258944403516112571318622645343106128449296680
Short name T427
Test name
Test status
Simulation time 156689183 ps
CPU time 4.07 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:28 PM PST 23
Peak memory 238432 kb
Host smart-accea5ff-3e3b-462a-94f3-c8a30219c47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75994898118743280108660081216266258944403516112571318622645343106128449296680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.otp_ctrl_init_fail.75994898118743280108660081216266258944403516112571318622645343106128449296680
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.2586259385415412409722617685955561095388271028244911092668004823819138773145
Short name T1155
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.22 seconds
Started Nov 22 01:51:30 PM PST 23
Finished Nov 22 01:51:52 PM PST 23
Peak memory 238904 kb
Host smart-bbe96e0b-70ba-42ce-8876-7c0e6e80a0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586259385415412409722617685955561095388271028244911092668004823819138773145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.otp_ctrl_macro_errs.2586259385415412409722617685955561095388271028244911092668004823819138773145
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.59626142632433565408377959646719687361329759948423196218118954791561937556812
Short name T1236
Test name
Test status
Simulation time 346349183 ps
CPU time 7.66 seconds
Started Nov 22 01:51:40 PM PST 23
Finished Nov 22 01:51:53 PM PST 23
Peak memory 238708 kb
Host smart-4114a070-941a-40e4-b810-619891d62121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59626142632433565408377959646719687361329759948423196218118954791561937556812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.otp_ctrl_parallel_key_req.59626142632433565408377959646719687361329759948423196218118954791561937556812
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.12041172790141881008936180507693367221823828729747752931508933845397239619753
Short name T238
Test name
Test status
Simulation time 176929183 ps
CPU time 4.36 seconds
Started Nov 22 01:51:30 PM PST 23
Finished Nov 22 01:51:37 PM PST 23
Peak memory 238572 kb
Host smart-b401413e-e258-4dd3-81d9-74ae4cc060c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12041172790141881008936180507693367221823828729747752931508933845397239619753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.12041172790141881008936180507693367221823828729747752931508933845397239619753
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.20243458394407041069925322684531796071101668293665132392590852583296742626758
Short name T665
Test name
Test status
Simulation time 486419183 ps
CPU time 12.11 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:36 PM PST 23
Peak memory 238724 kb
Host smart-d66b3298-4b76-4d5b-b37b-b09effb232b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20243458394407041069925322684531796071101668293665132392590852583296742626758 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.20243458394407041069925322684531796071101668293665132392590852583296742626758
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.65631373555648986353929617781462846941910122102919436970598927305448617150016
Short name T718
Test name
Test status
Simulation time 137469183 ps
CPU time 3.52 seconds
Started Nov 22 01:51:31 PM PST 23
Finished Nov 22 01:51:37 PM PST 23
Peak memory 238656 kb
Host smart-f574039e-cbd2-4b7d-b9b2-1617081b3837
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=65631373555648986353929617781462846941910122102919436970598927305448617150016 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.otp_ctrl_regwen.65631373555648986353929617781462846941910122102919436970598927305448617150016
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.32029216514296364742738445014290236885073967116180141677444382836751995182296
Short name T709
Test name
Test status
Simulation time 138839183 ps
CPU time 3.1 seconds
Started Nov 22 01:51:03 PM PST 23
Finished Nov 22 01:51:08 PM PST 23
Peak memory 238804 kb
Host smart-660d676d-28ad-4cde-a329-3183b3def1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32029216514296364742738445014290236885073967116180141677444382836751995182296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.otp_ctrl_smoke.32029216514296364742738445014290236885073967116180141677444382836751995182296
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.80533581950871820272881682903153039312780375328093117719912850037493188318842
Short name T1275
Test name
Test status
Simulation time 13240088340 ps
CPU time 124.88 seconds
Started Nov 22 01:51:17 PM PST 23
Finished Nov 22 01:53:24 PM PST 23
Peak memory 241724 kb
Host smart-1ef1c691-62f1-4c57-bbfd-aa08459d66a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80533581950871820272881682903153039312780375328093117719912850037493188318842 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.80533581950871820272881682903153039312780375328093117719912850037493188318842
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.72585096882887507055570760869573643032879190945163451980922425098634288059458
Short name T1059
Test name
Test status
Simulation time 150268849183 ps
CPU time 1972.58 seconds
Started Nov 22 01:51:42 PM PST 23
Finished Nov 22 02:24:39 PM PST 23
Peak memory 517536 kb
Host smart-83a367ad-d04a-413f-b661-419090632f3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7258509688288750705557
0760869573643032879190945163451980922425098634288059458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_res
et.72585096882887507055570760869573643032879190945163451980922425098634288059458
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.89593301936295917743817919387584784564581756162545357700074510355361266260951
Short name T882
Test name
Test status
Simulation time 549639183 ps
CPU time 9.09 seconds
Started Nov 22 01:51:42 PM PST 23
Finished Nov 22 01:51:56 PM PST 23
Peak memory 246948 kb
Host smart-52243128-1baf-446e-a445-01c42154ac61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89593301936295917743817919387584784564581756162545357700074510355361266260951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.otp_ctrl_test_access.89593301936295917743817919387584784564581756162545357700074510355361266260951
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.9354438643231755760155655943210711500544831874479130906992625637426666407847
Short name T30
Test name
Test status
Simulation time 71069183 ps
CPU time 1.79 seconds
Started Nov 22 01:51:53 PM PST 23
Finished Nov 22 01:51:57 PM PST 23
Peak memory 238180 kb
Host smart-f3562aef-e87d-4731-8d4e-62d1378521ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9354438643231755760155655943210711500544831874479130906992625637426666407847 -assert nopostpro
c +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.9354438643231755760155655943210711500544831874479130906992625637426666407847
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.46290169359939622870596690259717058614736109518921176170323383508822916704438
Short name T648
Test name
Test status
Simulation time 111269183 ps
CPU time 2.7 seconds
Started Nov 22 01:51:04 PM PST 23
Finished Nov 22 01:51:09 PM PST 23
Peak memory 246696 kb
Host smart-61c3c091-0654-4b34-8cbb-5f10919cb96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46290169359939622870596690259717058614736109518921176170323383508822916704438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.otp_ctrl_check_fail.46290169359939622870596690259717058614736109518921176170323383508822916704438
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.78445404152949566326967076637575204273329578940409974122240745725276504510910
Short name T619
Test name
Test status
Simulation time 390019183 ps
CPU time 12 seconds
Started Nov 22 01:51:38 PM PST 23
Finished Nov 22 01:51:54 PM PST 23
Peak memory 238636 kb
Host smart-c1886d57-3efc-4405-bc84-c7e25e1b0605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78445404152949566326967076637575204273329578940409974122240745725276504510910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.otp_ctrl_dai_errs.78445404152949566326967076637575204273329578940409974122240745725276504510910
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.105769701408620604132529814343685076664869240505156334656501670758025314450327
Short name T1229
Test name
Test status
Simulation time 614979183 ps
CPU time 10.63 seconds
Started Nov 22 01:51:23 PM PST 23
Finished Nov 22 01:51:36 PM PST 23
Peak memory 238716 kb
Host smart-5cf819c5-649a-4e42-b967-a1a4e095f3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105769701408620604132529814343685076664869240505156334656501670758025314450327 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.otp_ctrl_dai_lock.105769701408620604132529814343685076664869240505156334656501670758025314450327
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.66068543245712836290502403854190451785120453106144305207141199858640790453734
Short name T517
Test name
Test status
Simulation time 156689183 ps
CPU time 4.03 seconds
Started Nov 22 01:51:45 PM PST 23
Finished Nov 22 01:51:53 PM PST 23
Peak memory 238548 kb
Host smart-9de16c61-9421-4dd0-afd4-7ea202f3cbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66068543245712836290502403854190451785120453106144305207141199858640790453734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.otp_ctrl_init_fail.66068543245712836290502403854190451785120453106144305207141199858640790453734
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.50259293498251592449363049748775577517919161861867986344905205997504766527460
Short name T624
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.95 seconds
Started Nov 22 01:51:26 PM PST 23
Finished Nov 22 01:51:49 PM PST 23
Peak memory 239028 kb
Host smart-c433b557-8ff9-44c3-8cd7-a874038618c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50259293498251592449363049748775577517919161861867986344905205997504766527460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.otp_ctrl_macro_errs.50259293498251592449363049748775577517919161861867986344905205997504766527460
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.54747663794594075582077953600960873789313486937330226093559207347746049060848
Short name T1217
Test name
Test status
Simulation time 346349183 ps
CPU time 7.33 seconds
Started Nov 22 01:51:53 PM PST 23
Finished Nov 22 01:52:03 PM PST 23
Peak memory 238604 kb
Host smart-cbf520fe-1d53-444c-be12-ffd1b95938b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54747663794594075582077953600960873789313486937330226093559207347746049060848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 45.otp_ctrl_parallel_key_req.54747663794594075582077953600960873789313486937330226093559207347746049060848
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.3346979243390556023556178285954224784634342113569876885137893598841408945695
Short name T699
Test name
Test status
Simulation time 176929183 ps
CPU time 4.56 seconds
Started Nov 22 01:51:33 PM PST 23
Finished Nov 22 01:51:41 PM PST 23
Peak memory 238584 kb
Host smart-f9316e65-ba80-407b-a92f-cea96fa507ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346979243390556023556178285954224784634342113569876885137893598841408945695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.3346979243390556023556178285954224784634342113569876885137893598841408945695
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.58608944192554144898634467772501827149150218863354738251460309735366187626890
Short name T1145
Test name
Test status
Simulation time 486419183 ps
CPU time 12.16 seconds
Started Nov 22 01:51:09 PM PST 23
Finished Nov 22 01:51:23 PM PST 23
Peak memory 238724 kb
Host smart-9e4102c5-3a48-473b-a9dd-667b9aa87edc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58608944192554144898634467772501827149150218863354738251460309735366187626890 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.58608944192554144898634467772501827149150218863354738251460309735366187626890
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.106926744163921672038033848136593459627320870457089651899218009509399503663795
Short name T952
Test name
Test status
Simulation time 137469183 ps
CPU time 3.59 seconds
Started Nov 22 01:51:38 PM PST 23
Finished Nov 22 01:51:46 PM PST 23
Peak memory 238680 kb
Host smart-0fdc520b-46bf-4ad0-8f13-c87a4133511c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106926744163921672038033848136593459627320870457089651899218009509399503663795 -assert nopostproc +UVM_TE
STNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.otp_ctrl_regwen.106926744163921672038033848136593459627320870457089651899218009509399503663795
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.5426824262418083775046342630377338858511844903742958074177145280344034396462
Short name T674
Test name
Test status
Simulation time 138839183 ps
CPU time 3.02 seconds
Started Nov 22 01:51:29 PM PST 23
Finished Nov 22 01:51:36 PM PST 23
Peak memory 238780 kb
Host smart-fc70c385-0f96-4e55-8e35-768d63208039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5426824262418083775046342630377338858511844903742958074177145280344034396462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.otp_ctrl_smoke.5426824262418083775046342630377338858511844903742958074177145280344034396462
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.32214490211034472481689549963852565102265108584403997349077472240796448737323
Short name T585
Test name
Test status
Simulation time 13240088340 ps
CPU time 129.37 seconds
Started Nov 22 01:51:51 PM PST 23
Finished Nov 22 01:54:02 PM PST 23
Peak memory 241840 kb
Host smart-1e5da76a-d516-4411-b7b7-2c4361dc14ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32214490211034472481689549963852565102265108584403997349077472240796448737323 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.32214490211034472481689549963852565102265108584403997349077472240796448737323
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.52771515332696544026884867954264084499979882136149193308958388177616619105769
Short name T790
Test name
Test status
Simulation time 150268849183 ps
CPU time 1993.78 seconds
Started Nov 22 01:51:20 PM PST 23
Finished Nov 22 02:24:37 PM PST 23
Peak memory 517584 kb
Host smart-ebc4cb7e-d083-4a9f-a133-3aee27567442
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5277151533269654402688
4867954264084499979882136149193308958388177616619105769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_res
et.52771515332696544026884867954264084499979882136149193308958388177616619105769
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.11575566380120225279832473040140931480616823598461079419103590726422199439144
Short name T39
Test name
Test status
Simulation time 549639183 ps
CPU time 9.35 seconds
Started Nov 22 01:51:24 PM PST 23
Finished Nov 22 01:51:36 PM PST 23
Peak memory 247008 kb
Host smart-d181bc9d-ab31-4763-a809-278239767333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11575566380120225279832473040140931480616823598461079419103590726422199439144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.otp_ctrl_test_access.11575566380120225279832473040140931480616823598461079419103590726422199439144
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.41660462234732218880261518530960644035338931397633100011594344084543363277684
Short name T725
Test name
Test status
Simulation time 71069183 ps
CPU time 1.85 seconds
Started Nov 22 01:51:00 PM PST 23
Finished Nov 22 01:51:02 PM PST 23
Peak memory 238292 kb
Host smart-823a48e8-7f16-4590-89a9-6441b8b4d0ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41660462234732218880261518530960644035338931397633100011594344084543363277684 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.41660462234732218880261518530960644035338931397633100011594344084543363277684
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.86217416798883062337391427769898698547753282962900333486067797580100480950027
Short name T833
Test name
Test status
Simulation time 111269183 ps
CPU time 2.73 seconds
Started Nov 22 01:51:00 PM PST 23
Finished Nov 22 01:51:03 PM PST 23
Peak memory 246656 kb
Host smart-4c2836ee-9312-4f39-9377-03b43c031c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86217416798883062337391427769898698547753282962900333486067797580100480950027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.otp_ctrl_check_fail.86217416798883062337391427769898698547753282962900333486067797580100480950027
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.19073728452377429237777854785438248324845233393089182588068495839877844931672
Short name T847
Test name
Test status
Simulation time 390019183 ps
CPU time 10.74 seconds
Started Nov 22 01:51:07 PM PST 23
Finished Nov 22 01:51:20 PM PST 23
Peak memory 238396 kb
Host smart-05d61366-ca06-4655-8171-272c4a141583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19073728452377429237777854785438248324845233393089182588068495839877844931672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.otp_ctrl_dai_errs.19073728452377429237777854785438248324845233393089182588068495839877844931672
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.56499424707499909664657928778956839340290773079057261473092293886284217694641
Short name T1260
Test name
Test status
Simulation time 614979183 ps
CPU time 10.57 seconds
Started Nov 22 01:51:54 PM PST 23
Finished Nov 22 01:52:07 PM PST 23
Peak memory 238788 kb
Host smart-ff64bcf7-e9fd-408b-aaa8-498706f6df8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56499424707499909664657928778956839340290773079057261473092293886284217694641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.otp_ctrl_dai_lock.56499424707499909664657928778956839340290773079057261473092293886284217694641
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.2861998969743662191450954290941555686537845979216776883862838359592568753390
Short name T764
Test name
Test status
Simulation time 156689183 ps
CPU time 4.03 seconds
Started Nov 22 01:51:24 PM PST 23
Finished Nov 22 01:51:32 PM PST 23
Peak memory 238568 kb
Host smart-81a95825-122f-494d-805b-7de1a97596a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861998969743662191450954290941555686537845979216776883862838359592568753390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.otp_ctrl_init_fail.2861998969743662191450954290941555686537845979216776883862838359592568753390
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.12462907754461270411670909902644086831964654568518432075978608017686821609904
Short name T1187
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.68 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:43 PM PST 23
Peak memory 239032 kb
Host smart-afc5a4ce-a532-4826-9e2a-f047afbffc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12462907754461270411670909902644086831964654568518432075978608017686821609904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.otp_ctrl_macro_errs.12462907754461270411670909902644086831964654568518432075978608017686821609904
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.20177207184979646025415326114691583217204266012776343022410466553135409093548
Short name T591
Test name
Test status
Simulation time 346349183 ps
CPU time 7.33 seconds
Started Nov 22 01:51:25 PM PST 23
Finished Nov 22 01:51:36 PM PST 23
Peak memory 238740 kb
Host smart-1e5a7e86-e0ec-44ae-937a-bb759acce2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20177207184979646025415326114691583217204266012776343022410466553135409093548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.otp_ctrl_parallel_key_req.20177207184979646025415326114691583217204266012776343022410466553135409093548
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.86053130153573599662875734844640092399207458850191386033041852382373774351777
Short name T1238
Test name
Test status
Simulation time 176929183 ps
CPU time 4.24 seconds
Started Nov 22 01:51:51 PM PST 23
Finished Nov 22 01:51:57 PM PST 23
Peak memory 238576 kb
Host smart-539738df-fba4-4e5f-b027-2f82b7b6a30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86053130153573599662875734844640092399207458850191386033041852382373774351777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.86053130153573599662875734844640092399207458850191386033041852382373774351777
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.41398982119001013407266529102819196491283025160725897132209914414692757636140
Short name T600
Test name
Test status
Simulation time 486419183 ps
CPU time 11.7 seconds
Started Nov 22 01:51:32 PM PST 23
Finished Nov 22 01:51:47 PM PST 23
Peak memory 238632 kb
Host smart-4a6e18f3-a294-47e0-9395-4c1e67b7853d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=41398982119001013407266529102819196491283025160725897132209914414692757636140 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.41398982119001013407266529102819196491283025160725897132209914414692757636140
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.71011547922734481648277261730761988671614079210219176304188985578867479007652
Short name T400
Test name
Test status
Simulation time 137469183 ps
CPU time 3.54 seconds
Started Nov 22 01:51:07 PM PST 23
Finished Nov 22 01:51:13 PM PST 23
Peak memory 238552 kb
Host smart-7702a2b2-fc28-4c3d-8d0d-c71003d4fa2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71011547922734481648277261730761988671614079210219176304188985578867479007652 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.otp_ctrl_regwen.71011547922734481648277261730761988671614079210219176304188985578867479007652
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.55202991656616816293632303739597633931114103876750297160843129729692067039291
Short name T299
Test name
Test status
Simulation time 138839183 ps
CPU time 3.18 seconds
Started Nov 22 01:51:25 PM PST 23
Finished Nov 22 01:51:32 PM PST 23
Peak memory 238792 kb
Host smart-d06bc0a9-f384-4ac1-a875-9c8eb1c44bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55202991656616816293632303739597633931114103876750297160843129729692067039291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.otp_ctrl_smoke.55202991656616816293632303739597633931114103876750297160843129729692067039291
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.92559952691660085188836356215223402306536652937150525705335340349643269483116
Short name T550
Test name
Test status
Simulation time 13240088340 ps
CPU time 127.17 seconds
Started Nov 22 01:51:02 PM PST 23
Finished Nov 22 01:53:11 PM PST 23
Peak memory 241828 kb
Host smart-83d020b4-5f66-462c-8d42-f1c71c40f7bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92559952691660085188836356215223402306536652937150525705335340349643269483116 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.92559952691660085188836356215223402306536652937150525705335340349643269483116
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.59618886022340694063460724694945489321629197807119599298466402065377824086078
Short name T346
Test name
Test status
Simulation time 150268849183 ps
CPU time 1941.86 seconds
Started Nov 22 01:51:53 PM PST 23
Finished Nov 22 02:24:18 PM PST 23
Peak memory 517500 kb
Host smart-41c8ab69-86bb-43ce-aedf-34eff2e23b56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5961888602234069406346
0724694945489321629197807119599298466402065377824086078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_res
et.59618886022340694063460724694945489321629197807119599298466402065377824086078
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.83134155328622223466894783569124291721688495140821008068238885527165465060302
Short name T317
Test name
Test status
Simulation time 549639183 ps
CPU time 9.09 seconds
Started Nov 22 01:51:12 PM PST 23
Finished Nov 22 01:51:23 PM PST 23
Peak memory 247028 kb
Host smart-9d39651d-4e7f-4f78-ba9f-23e721648d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83134155328622223466894783569124291721688495140821008068238885527165465060302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.otp_ctrl_test_access.83134155328622223466894783569124291721688495140821008068238885527165465060302
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.61187267528889197873242043238541579963314383030845960813158727070819235294863
Short name T336
Test name
Test status
Simulation time 71069183 ps
CPU time 1.85 seconds
Started Nov 22 01:51:31 PM PST 23
Finished Nov 22 01:51:36 PM PST 23
Peak memory 238352 kb
Host smart-7ffb4dde-de23-4682-b3e7-d14c3b945b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61187267528889197873242043238541579963314383030845960813158727070819235294863 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.61187267528889197873242043238541579963314383030845960813158727070819235294863
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.20485292851632738732688118509847372928201830127899428581749828430477142781758
Short name T1004
Test name
Test status
Simulation time 111269183 ps
CPU time 2.75 seconds
Started Nov 22 01:51:04 PM PST 23
Finished Nov 22 01:51:08 PM PST 23
Peak memory 246788 kb
Host smart-99f751bb-d6e5-4579-bab6-9911943438fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20485292851632738732688118509847372928201830127899428581749828430477142781758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.otp_ctrl_check_fail.20485292851632738732688118509847372928201830127899428581749828430477142781758
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.18368046599558430728929114304956742517628810961161035923410314660041408424287
Short name T719
Test name
Test status
Simulation time 390019183 ps
CPU time 11.03 seconds
Started Nov 22 01:51:19 PM PST 23
Finished Nov 22 01:51:33 PM PST 23
Peak memory 238664 kb
Host smart-5773b579-3395-47e6-953c-b19037857a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18368046599558430728929114304956742517628810961161035923410314660041408424287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.otp_ctrl_dai_errs.18368046599558430728929114304956742517628810961161035923410314660041408424287
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.77207116794808909467403389273359280633656488707990671164995207896021718585928
Short name T800
Test name
Test status
Simulation time 614979183 ps
CPU time 10.48 seconds
Started Nov 22 01:51:20 PM PST 23
Finished Nov 22 01:51:33 PM PST 23
Peak memory 238792 kb
Host smart-c7bf373e-23e2-428a-8cc8-5ba64686db01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77207116794808909467403389273359280633656488707990671164995207896021718585928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.otp_ctrl_dai_lock.77207116794808909467403389273359280633656488707990671164995207896021718585928
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.61574597615363405609542254227652968503056802895613265526931378523926900716461
Short name T309
Test name
Test status
Simulation time 156689183 ps
CPU time 3.99 seconds
Started Nov 22 01:51:07 PM PST 23
Finished Nov 22 01:51:13 PM PST 23
Peak memory 238316 kb
Host smart-523122d7-09bc-4e5b-8150-5f2d55c3f9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61574597615363405609542254227652968503056802895613265526931378523926900716461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.otp_ctrl_init_fail.61574597615363405609542254227652968503056802895613265526931378523926900716461
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.106214643478976740608342544764731130758869274402033765924459271315188294059023
Short name T295
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.66 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:43 PM PST 23
Peak memory 238996 kb
Host smart-7077c3cb-babf-4f9a-a321-cfa60a2f88ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106214643478976740608342544764731130758869274402033765924459271315188294059023 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.otp_ctrl_macro_errs.106214643478976740608342544764731130758869274402033765924459271315188294059023
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.21011853642227753669341625675428787757468895617016604772233006119120159156456
Short name T436
Test name
Test status
Simulation time 346349183 ps
CPU time 7.51 seconds
Started Nov 22 01:51:11 PM PST 23
Finished Nov 22 01:51:20 PM PST 23
Peak memory 238796 kb
Host smart-a795e9de-78a3-4e54-9a86-73449a745f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21011853642227753669341625675428787757468895617016604772233006119120159156456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.otp_ctrl_parallel_key_req.21011853642227753669341625675428787757468895617016604772233006119120159156456
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.26595461112664161632580062990034201298012316271304813967149432457760340988606
Short name T1113
Test name
Test status
Simulation time 176929183 ps
CPU time 4.77 seconds
Started Nov 22 01:51:31 PM PST 23
Finished Nov 22 01:51:39 PM PST 23
Peak memory 238656 kb
Host smart-ee0480f9-690d-49e2-9ffa-d7ce41bd9c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26595461112664161632580062990034201298012316271304813967149432457760340988606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.26595461112664161632580062990034201298012316271304813967149432457760340988606
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.38727840979481017761256251202789189799934091420433706533955516852718641271234
Short name T286
Test name
Test status
Simulation time 486419183 ps
CPU time 11.71 seconds
Started Nov 22 01:51:02 PM PST 23
Finished Nov 22 01:51:26 PM PST 23
Peak memory 238716 kb
Host smart-4517006b-7fa4-4afe-9b79-0e39a77d810a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38727840979481017761256251202789189799934091420433706533955516852718641271234 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.38727840979481017761256251202789189799934091420433706533955516852718641271234
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.100868842446460444692437616920547281640613992457052193933491842148851147241103
Short name T976
Test name
Test status
Simulation time 137469183 ps
CPU time 3.55 seconds
Started Nov 22 01:51:19 PM PST 23
Finished Nov 22 01:51:25 PM PST 23
Peak memory 238720 kb
Host smart-acf24fb0-7f0c-4c1f-84f6-ce12dbc8c62d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100868842446460444692437616920547281640613992457052193933491842148851147241103 -assert nopostproc +UVM_TE
STNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.otp_ctrl_regwen.100868842446460444692437616920547281640613992457052193933491842148851147241103
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.66838336453974045930135329824825973054346433864366256124549140764303850334156
Short name T231
Test name
Test status
Simulation time 138839183 ps
CPU time 3.11 seconds
Started Nov 22 01:51:26 PM PST 23
Finished Nov 22 01:51:32 PM PST 23
Peak memory 238760 kb
Host smart-7b5781f3-7805-469b-ae4d-5050491dbb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66838336453974045930135329824825973054346433864366256124549140764303850334156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.otp_ctrl_smoke.66838336453974045930135329824825973054346433864366256124549140764303850334156
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.9422534380974406024419663611254316961554081729513544719399596812171872563573
Short name T988
Test name
Test status
Simulation time 150268849183 ps
CPU time 1970.09 seconds
Started Nov 22 01:51:42 PM PST 23
Finished Nov 22 02:24:36 PM PST 23
Peak memory 517536 kb
Host smart-91f1a078-dc8f-40dc-8590-da46e1d39ad1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9422534380974406024419
663611254316961554081729513544719399596812171872563573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_rese
t.9422534380974406024419663611254316961554081729513544719399596812171872563573
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.46522495994358169438464875777358163246743702946429842992048664075985114790682
Short name T1041
Test name
Test status
Simulation time 549639183 ps
CPU time 9.28 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:33 PM PST 23
Peak memory 246948 kb
Host smart-35c24ad4-5893-4e97-8938-6316c963678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46522495994358169438464875777358163246743702946429842992048664075985114790682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.otp_ctrl_test_access.46522495994358169438464875777358163246743702946429842992048664075985114790682
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.112910920369118584582585354736826307709517436866990735470885041926367670043872
Short name T1243
Test name
Test status
Simulation time 71069183 ps
CPU time 1.8 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:49 PM PST 23
Peak memory 238420 kb
Host smart-ef3428f8-7762-4e33-9953-a0bb7ff5608a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112910920369118584582585354736826307709517436866990735470885041926367670043872 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.112910920369118584582585354736826307709517436866990735470885041926367670043872
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.29245485890261384493179146216983870311015099278533414615184470885113193290546
Short name T911
Test name
Test status
Simulation time 111269183 ps
CPU time 2.73 seconds
Started Nov 22 01:51:38 PM PST 23
Finished Nov 22 01:51:46 PM PST 23
Peak memory 246836 kb
Host smart-3a32ebb5-40d0-4834-b7ff-bbc70753d216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29245485890261384493179146216983870311015099278533414615184470885113193290546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.otp_ctrl_check_fail.29245485890261384493179146216983870311015099278533414615184470885113193290546
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.61940301407910081968283547498107099610569791522775298005277610621170145068430
Short name T558
Test name
Test status
Simulation time 390019183 ps
CPU time 10.77 seconds
Started Nov 22 01:51:46 PM PST 23
Finished Nov 22 01:52:00 PM PST 23
Peak memory 238564 kb
Host smart-1eb8cb4e-bb7a-4509-8bd1-09a0f8640811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61940301407910081968283547498107099610569791522775298005277610621170145068430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.otp_ctrl_dai_errs.61940301407910081968283547498107099610569791522775298005277610621170145068430
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.85182119956536777400873033509489121177750983128917865491852063803613894886586
Short name T789
Test name
Test status
Simulation time 614979183 ps
CPU time 10.72 seconds
Started Nov 22 01:51:19 PM PST 23
Finished Nov 22 01:51:32 PM PST 23
Peak memory 238800 kb
Host smart-b87738a7-fafc-4496-8846-1dd114cfaf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85182119956536777400873033509489121177750983128917865491852063803613894886586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.otp_ctrl_dai_lock.85182119956536777400873033509489121177750983128917865491852063803613894886586
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.105107192383166977372858960677672156715790377754838878415478851797808474881034
Short name T659
Test name
Test status
Simulation time 156689183 ps
CPU time 4.02 seconds
Started Nov 22 01:51:45 PM PST 23
Finished Nov 22 01:51:52 PM PST 23
Peak memory 238552 kb
Host smart-9233609d-5bc1-489a-9f26-9fe70faa4790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105107192383166977372858960677672156715790377754838878415478851797808474881034 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.otp_ctrl_init_fail.105107192383166977372858960677672156715790377754838878415478851797808474881034
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.38320783706464964819821898052162235608784399657522831414803673041629393758675
Short name T56
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.62 seconds
Started Nov 22 01:51:20 PM PST 23
Finished Nov 22 01:51:42 PM PST 23
Peak memory 238948 kb
Host smart-7d0485b8-af91-4da3-a96a-632ea300f5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38320783706464964819821898052162235608784399657522831414803673041629393758675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.otp_ctrl_macro_errs.38320783706464964819821898052162235608784399657522831414803673041629393758675
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.52953246263636872605687297495921370431630403526016768420197084490999036917652
Short name T681
Test name
Test status
Simulation time 346349183 ps
CPU time 7.55 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:31 PM PST 23
Peak memory 238748 kb
Host smart-ca0faf50-71e6-4aa8-a35b-f6b8accff6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52953246263636872605687297495921370431630403526016768420197084490999036917652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.otp_ctrl_parallel_key_req.52953246263636872605687297495921370431630403526016768420197084490999036917652
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.64021873145783440221742568275946306584013468191515437273920680098894679034193
Short name T647
Test name
Test status
Simulation time 176929183 ps
CPU time 4.49 seconds
Started Nov 22 01:51:25 PM PST 23
Finished Nov 22 01:51:33 PM PST 23
Peak memory 238704 kb
Host smart-8af6e811-8544-412a-84bc-b5c8723ba371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64021873145783440221742568275946306584013468191515437273920680098894679034193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.64021873145783440221742568275946306584013468191515437273920680098894679034193
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.43147801123559316435777716396656135079406819905532303447270487318946116735517
Short name T531
Test name
Test status
Simulation time 486419183 ps
CPU time 11.69 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:34 PM PST 23
Peak memory 238620 kb
Host smart-e25860e3-fd7d-455a-8307-f39f85aada64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=43147801123559316435777716396656135079406819905532303447270487318946116735517 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.43147801123559316435777716396656135079406819905532303447270487318946116735517
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.67193864250851994787019221394305554562666116747985085653021484955518283433271
Short name T223
Test name
Test status
Simulation time 137469183 ps
CPU time 3.55 seconds
Started Nov 22 01:51:20 PM PST 23
Finished Nov 22 01:51:26 PM PST 23
Peak memory 238692 kb
Host smart-39e096a0-3998-486b-86c2-ae00716377ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67193864250851994787019221394305554562666116747985085653021484955518283433271 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.otp_ctrl_regwen.67193864250851994787019221394305554562666116747985085653021484955518283433271
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.7089134050294472462101899536216712010450130530313594325046139793980499381183
Short name T1083
Test name
Test status
Simulation time 138839183 ps
CPU time 3.06 seconds
Started Nov 22 01:51:18 PM PST 23
Finished Nov 22 01:51:24 PM PST 23
Peak memory 238800 kb
Host smart-d57043e3-d589-4f4f-b3c3-2488c0a1b465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7089134050294472462101899536216712010450130530313594325046139793980499381183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.otp_ctrl_smoke.7089134050294472462101899536216712010450130530313594325046139793980499381183
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.43965788143567920936481340011024451863280043594726845734074215521220130254849
Short name T445
Test name
Test status
Simulation time 13240088340 ps
CPU time 130.31 seconds
Started Nov 22 01:51:33 PM PST 23
Finished Nov 22 01:53:47 PM PST 23
Peak memory 241840 kb
Host smart-dd300113-07d8-4c97-8e5a-32c49f66ea40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43965788143567920936481340011024451863280043594726845734074215521220130254849 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.43965788143567920936481340011024451863280043594726845734074215521220130254849
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.108978702581787913327687194771645597038084523951642723429129983858596943408133
Short name T588
Test name
Test status
Simulation time 150268849183 ps
CPU time 1996.6 seconds
Started Nov 22 01:51:30 PM PST 23
Finished Nov 22 02:24:50 PM PST 23
Peak memory 517584 kb
Host smart-011409ba-5e71-48c0-92c5-33be6648d92a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089787025817879133276
87194771645597038084523951642723429129983858596943408133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_re
set.108978702581787913327687194771645597038084523951642723429129983858596943408133
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.105839869808178612568377598818196908312526820177262867630761187866366895117091
Short name T1193
Test name
Test status
Simulation time 549639183 ps
CPU time 9.07 seconds
Started Nov 22 01:51:31 PM PST 23
Finished Nov 22 01:51:43 PM PST 23
Peak memory 247032 kb
Host smart-4b100121-e598-47f1-9cc1-b25f9e59fb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105839869808178612568377598818196908312526820177262867630761187866366895117091 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.otp_ctrl_test_access.105839869808178612568377598818196908312526820177262867630761187866366895117091
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.21540931591536217630172951629482920590073507187839562082287212035717868712078
Short name T1297
Test name
Test status
Simulation time 71069183 ps
CPU time 1.87 seconds
Started Nov 22 01:51:15 PM PST 23
Finished Nov 22 01:51:19 PM PST 23
Peak memory 238456 kb
Host smart-84e5e937-a4ea-4f60-aea9-ecf1915f398e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21540931591536217630172951629482920590073507187839562082287212035717868712078 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.21540931591536217630172951629482920590073507187839562082287212035717868712078
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.44042891191248793201013261710994738666468499585860833958346817952736846128476
Short name T938
Test name
Test status
Simulation time 111269183 ps
CPU time 2.64 seconds
Started Nov 22 01:51:06 PM PST 23
Finished Nov 22 01:51:10 PM PST 23
Peak memory 246648 kb
Host smart-00bc0109-4add-4e4d-9329-523ebf5cdb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44042891191248793201013261710994738666468499585860833958346817952736846128476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.otp_ctrl_check_fail.44042891191248793201013261710994738666468499585860833958346817952736846128476
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.114327409113628138025698800967179532540938330350936260054784412961502906259779
Short name T872
Test name
Test status
Simulation time 390019183 ps
CPU time 10.99 seconds
Started Nov 22 01:51:17 PM PST 23
Finished Nov 22 01:51:30 PM PST 23
Peak memory 238496 kb
Host smart-6e88f203-aa00-49a1-9731-5222fadc4355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114327409113628138025698800967179532540938330350936260054784412961502906259779 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.otp_ctrl_dai_errs.114327409113628138025698800967179532540938330350936260054784412961502906259779
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.17444566588074071720600894670061834399592047440809042710797641512104323118841
Short name T1221
Test name
Test status
Simulation time 614979183 ps
CPU time 10.31 seconds
Started Nov 22 01:51:04 PM PST 23
Finished Nov 22 01:51:16 PM PST 23
Peak memory 238680 kb
Host smart-5b835775-595d-4f44-baf9-e0a1cc307c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17444566588074071720600894670061834399592047440809042710797641512104323118841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.otp_ctrl_dai_lock.17444566588074071720600894670061834399592047440809042710797641512104323118841
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.18095132856973166886607353668821688502956650714709847915926859098843323010834
Short name T1073
Test name
Test status
Simulation time 156689183 ps
CPU time 3.92 seconds
Started Nov 22 01:51:35 PM PST 23
Finished Nov 22 01:51:42 PM PST 23
Peak memory 238460 kb
Host smart-6cd837cf-0529-4a26-9a68-5e32059c12be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18095132856973166886607353668821688502956650714709847915926859098843323010834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.otp_ctrl_init_fail.18095132856973166886607353668821688502956650714709847915926859098843323010834
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.15984636309682803708923166758524417362960524437743817152684794943627956050725
Short name T484
Test name
Test status
Simulation time 1137629183 ps
CPU time 18.88 seconds
Started Nov 22 01:51:37 PM PST 23
Finished Nov 22 01:52:01 PM PST 23
Peak memory 238964 kb
Host smart-24fe35e3-0cbd-4904-ab8e-bf559bb96821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15984636309682803708923166758524417362960524437743817152684794943627956050725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.otp_ctrl_macro_errs.15984636309682803708923166758524417362960524437743817152684794943627956050725
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.99361870156556683302575060322937728062611763055953190585721088792140257440725
Short name T1115
Test name
Test status
Simulation time 346349183 ps
CPU time 7.26 seconds
Started Nov 22 01:51:17 PM PST 23
Finished Nov 22 01:51:26 PM PST 23
Peak memory 238656 kb
Host smart-82ef94a2-f3be-43b7-b205-60932a4ccf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99361870156556683302575060322937728062611763055953190585721088792140257440725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.otp_ctrl_parallel_key_req.99361870156556683302575060322937728062611763055953190585721088792140257440725
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.50429501764016278542282115934650004312388777045184254848726286371933036867133
Short name T599
Test name
Test status
Simulation time 176929183 ps
CPU time 4.05 seconds
Started Nov 22 01:51:13 PM PST 23
Finished Nov 22 01:51:20 PM PST 23
Peak memory 238540 kb
Host smart-10d692ab-ee4f-4040-9c40-1054a221e049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50429501764016278542282115934650004312388777045184254848726286371933036867133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.50429501764016278542282115934650004312388777045184254848726286371933036867133
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.54478521808626562064517851546201859015027212740386365086020613758613126465391
Short name T808
Test name
Test status
Simulation time 486419183 ps
CPU time 12.05 seconds
Started Nov 22 01:51:41 PM PST 23
Finished Nov 22 01:51:58 PM PST 23
Peak memory 238720 kb
Host smart-52f99e6e-34ba-4f6a-b222-6329fff293c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54478521808626562064517851546201859015027212740386365086020613758613126465391 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.54478521808626562064517851546201859015027212740386365086020613758613126465391
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.62659162081702702515507493391318009410463079992228901686737945910137084212125
Short name T272
Test name
Test status
Simulation time 137469183 ps
CPU time 3.59 seconds
Started Nov 22 01:51:20 PM PST 23
Finished Nov 22 01:51:26 PM PST 23
Peak memory 238440 kb
Host smart-aecebd56-c2c1-409b-9455-b2a3052d504f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=62659162081702702515507493391318009410463079992228901686737945910137084212125 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.otp_ctrl_regwen.62659162081702702515507493391318009410463079992228901686737945910137084212125
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.88655097903193366243048373583974514089069856131138432461038372782121698207164
Short name T329
Test name
Test status
Simulation time 138839183 ps
CPU time 3.04 seconds
Started Nov 22 01:51:54 PM PST 23
Finished Nov 22 01:51:59 PM PST 23
Peak memory 238840 kb
Host smart-5156354d-c65d-4469-ae67-db4e71a78df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88655097903193366243048373583974514089069856131138432461038372782121698207164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.otp_ctrl_smoke.88655097903193366243048373583974514089069856131138432461038372782121698207164
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.51562302880067431264134642870044633473483912144665453641931887060957355871072
Short name T1287
Test name
Test status
Simulation time 13240088340 ps
CPU time 133.83 seconds
Started Nov 22 01:51:37 PM PST 23
Finished Nov 22 01:53:56 PM PST 23
Peak memory 241824 kb
Host smart-677bf55c-6323-4c93-91f0-1646907e9492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51562302880067431264134642870044633473483912144665453641931887060957355871072 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.51562302880067431264134642870044633473483912144665453641931887060957355871072
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.95422068206247758619500491333943474973173533691572136431600858025307425497349
Short name T949
Test name
Test status
Simulation time 549639183 ps
CPU time 8.95 seconds
Started Nov 22 01:51:17 PM PST 23
Finished Nov 22 01:51:29 PM PST 23
Peak memory 246988 kb
Host smart-1f798993-04e9-4254-93a8-9eacfd54034b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95422068206247758619500491333943474973173533691572136431600858025307425497349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.otp_ctrl_test_access.95422068206247758619500491333943474973173533691572136431600858025307425497349
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.36907647025814343735157492776426592272750095030579598908847363933033834808042
Short name T621
Test name
Test status
Simulation time 71069183 ps
CPU time 1.79 seconds
Started Nov 22 01:50:51 PM PST 23
Finished Nov 22 01:50:54 PM PST 23
Peak memory 238472 kb
Host smart-10aea7b5-36a2-4593-9a02-a9b55ba82469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36907647025814343735157492776426592272750095030579598908847363933033834808042 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.36907647025814343735157492776426592272750095030579598908847363933033834808042
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.34676078208063963762078383384317238208696279538960282262446282397720709595766
Short name T93
Test name
Test status
Simulation time 190889183 ps
CPU time 5.08 seconds
Started Nov 22 01:50:15 PM PST 23
Finished Nov 22 01:50:26 PM PST 23
Peak memory 238836 kb
Host smart-699418a7-0ede-4726-9f4b-eaa78e7eb28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34676078208063963762078383384317238208696279538960282262446282397720709595766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 5.otp_ctrl_background_chks.34676078208063963762078383384317238208696279538960282262446282397720709595766
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.51435004675848220885672750015284822089920570154547418862466967413406034039559
Short name T730
Test name
Test status
Simulation time 111269183 ps
CPU time 2.6 seconds
Started Nov 22 01:50:11 PM PST 23
Finished Nov 22 01:50:20 PM PST 23
Peak memory 246696 kb
Host smart-7967ca9d-fe53-4ef1-a1af-fb58d1a1e4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51435004675848220885672750015284822089920570154547418862466967413406034039559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.otp_ctrl_check_fail.51435004675848220885672750015284822089920570154547418862466967413406034039559
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.87638459216696150563345304926482481326704855653077190351990484447006187409679
Short name T1251
Test name
Test status
Simulation time 390019183 ps
CPU time 10.98 seconds
Started Nov 22 01:50:10 PM PST 23
Finished Nov 22 01:50:29 PM PST 23
Peak memory 238700 kb
Host smart-b1e0805a-a162-4819-a557-f2c07e2a8f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87638459216696150563345304926482481326704855653077190351990484447006187409679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.otp_ctrl_dai_errs.87638459216696150563345304926482481326704855653077190351990484447006187409679
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.42838399364808019228770205897911117505498203771431967855054430193660613509614
Short name T1264
Test name
Test status
Simulation time 614979183 ps
CPU time 10.68 seconds
Started Nov 22 01:50:21 PM PST 23
Finished Nov 22 01:50:33 PM PST 23
Peak memory 238816 kb
Host smart-264bcfd5-ea6e-4083-b326-81f325bccfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42838399364808019228770205897911117505498203771431967855054430193660613509614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.otp_ctrl_dai_lock.42838399364808019228770205897911117505498203771431967855054430193660613509614
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.9110920023309801954548299703794674784669884764454292400432684045488875461839
Short name T487
Test name
Test status
Simulation time 156689183 ps
CPU time 4.12 seconds
Started Nov 22 01:50:27 PM PST 23
Finished Nov 22 01:50:32 PM PST 23
Peak memory 238584 kb
Host smart-7dce5faf-cac5-459a-bfe1-298df23d3e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9110920023309801954548299703794674784669884764454292400432684045488875461839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.otp_ctrl_init_fail.9110920023309801954548299703794674784669884764454292400432684045488875461839
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.109934097166800096953832751479102519244053246415580925482370050272622387556690
Short name T610
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.57 seconds
Started Nov 22 01:50:28 PM PST 23
Finished Nov 22 01:50:49 PM PST 23
Peak memory 239060 kb
Host smart-22916d99-13bc-42b4-bdbc-95711dce9ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109934097166800096953832751479102519244053246415580925482370050272622387556690 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.otp_ctrl_macro_errs.109934097166800096953832751479102519244053246415580925482370050272622387556690
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.8073139822392266330420144423300969483456358790452006860817614839260061593861
Short name T270
Test name
Test status
Simulation time 346349183 ps
CPU time 7.57 seconds
Started Nov 22 01:50:31 PM PST 23
Finished Nov 22 01:50:39 PM PST 23
Peak memory 238784 kb
Host smart-8d28f360-acce-4a1d-bcc4-a92d15b06cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8073139822392266330420144423300969483456358790452006860817614839260061593861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 5.otp_ctrl_parallel_key_req.8073139822392266330420144423300969483456358790452006860817614839260061593861
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.64427254270959359855465472117617596523712398779294595240959726909484791654746
Short name T944
Test name
Test status
Simulation time 176929183 ps
CPU time 4.42 seconds
Started Nov 22 01:50:25 PM PST 23
Finished Nov 22 01:50:31 PM PST 23
Peak memory 238584 kb
Host smart-a6a5f789-0ebc-45f6-b86d-ad9aa2ce7a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64427254270959359855465472117617596523712398779294595240959726909484791654746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.64427254270959359855465472117617596523712398779294595240959726909484791654746
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.40499703167544345784513169667493223703519202689492028423007415939270464413051
Short name T935
Test name
Test status
Simulation time 486419183 ps
CPU time 11.81 seconds
Started Nov 22 01:50:10 PM PST 23
Finished Nov 22 01:50:30 PM PST 23
Peak memory 238688 kb
Host smart-db96be02-e11b-4de6-9eab-c9747b81ad34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=40499703167544345784513169667493223703519202689492028423007415939270464413051 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.40499703167544345784513169667493223703519202689492028423007415939270464413051
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.100726858458079925364586732974587371910835977973731403542297815400243920322538
Short name T275
Test name
Test status
Simulation time 137469183 ps
CPU time 3.66 seconds
Started Nov 22 01:50:29 PM PST 23
Finished Nov 22 01:50:34 PM PST 23
Peak memory 238624 kb
Host smart-b7aafd6d-d64e-4bdc-a83c-45f21ea04ed4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100726858458079925364586732974587371910835977973731403542297815400243920322538 -assert nopostproc +UVM_TE
STNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_regwen.100726858458079925364586732974587371910835977973731403542297815400243920322538
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.82535931161237082393403417464334253983064199177734728504459488564092973772397
Short name T1047
Test name
Test status
Simulation time 138839183 ps
CPU time 3.03 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:08 PM PST 23
Peak memory 238844 kb
Host smart-3702a063-7331-4a24-9686-c0018ecdd926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82535931161237082393403417464334253983064199177734728504459488564092973772397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.otp_ctrl_smoke.82535931161237082393403417464334253983064199177734728504459488564092973772397
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.72695396488495983412685057014955745540984980279079727043090662146556742033468
Short name T70
Test name
Test status
Simulation time 13240088340 ps
CPU time 133.79 seconds
Started Nov 22 01:50:08 PM PST 23
Finished Nov 22 01:52:28 PM PST 23
Peak memory 241792 kb
Host smart-d094dd53-7210-41d2-a205-2c7f0104036e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72695396488495983412685057014955745540984980279079727043090662146556742033468 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.72695396488495983412685057014955745540984980279079727043090662146556742033468
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.88599999869173976789718550660784609223067215297457545000986119508866010249355
Short name T462
Test name
Test status
Simulation time 150268849183 ps
CPU time 1965.47 seconds
Started Nov 22 01:50:08 PM PST 23
Finished Nov 22 02:23:00 PM PST 23
Peak memory 517624 kb
Host smart-3989a5ca-a17a-4f33-b401-2b0d179ca287
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8859999986917397678971
8550660784609223067215297457545000986119508866010249355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_rese
t.88599999869173976789718550660784609223067215297457545000986119508866010249355
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.69917854458665142142657369915080047653518298340128278345364497285740347844263
Short name T570
Test name
Test status
Simulation time 549639183 ps
CPU time 8.88 seconds
Started Nov 22 01:50:53 PM PST 23
Finished Nov 22 01:51:02 PM PST 23
Peak memory 247020 kb
Host smart-eb65bc6f-96ba-42ee-88b3-64fd3ca24c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69917854458665142142657369915080047653518298340128278345364497285740347844263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.otp_ctrl_test_access.69917854458665142142657369915080047653518298340128278345364497285740347844263
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.53978543570146247162819606098477037258086022331808429283557064138502463648701
Short name T1189
Test name
Test status
Simulation time 156689183 ps
CPU time 4.19 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:51 PM PST 23
Peak memory 238616 kb
Host smart-42849fde-53db-4cf6-bbe5-c0dea904dbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53978543570146247162819606098477037258086022331808429283557064138502463648701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 50.otp_ctrl_init_fail.53978543570146247162819606098477037258086022331808429283557064138502463648701
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.46836440994632168606773354121943691528591729745507214055197369216751793232026
Short name T1252
Test name
Test status
Simulation time 176929183 ps
CPU time 4.29 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:27 PM PST 23
Peak memory 238408 kb
Host smart-1a1e0c01-2351-4452-8e87-2f756bc0747b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46836440994632168606773354121943691528591729745507214055197369216751793232026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.46836440994632168606773354121943691528591729745507214055197369216751793232026
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.106851819937092148245965292359425781064430037671843237450933799663732107885373
Short name T668
Test name
Test status
Simulation time 150268849183 ps
CPU time 1855.63 seconds
Started Nov 22 01:51:16 PM PST 23
Finished Nov 22 02:22:14 PM PST 23
Peak memory 517380 kb
Host smart-7b7ab6a3-68c2-4f3d-8923-ea9238c9e341
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068518199370921482459
65292359425781064430037671843237450933799663732107885373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_re
set.106851819937092148245965292359425781064430037671843237450933799663732107885373
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.98272075103714777285675588150164757988390748065240096156356557866281022500076
Short name T615
Test name
Test status
Simulation time 156689183 ps
CPU time 4.12 seconds
Started Nov 22 01:51:13 PM PST 23
Finished Nov 22 01:51:20 PM PST 23
Peak memory 238620 kb
Host smart-c7e1d782-1562-422d-81b6-efd526c6bfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98272075103714777285675588150164757988390748065240096156356557866281022500076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 51.otp_ctrl_init_fail.98272075103714777285675588150164757988390748065240096156356557866281022500076
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.37474143327569270892224004018914655855154927487566385829078805371840936649807
Short name T500
Test name
Test status
Simulation time 176929183 ps
CPU time 4.45 seconds
Started Nov 22 01:51:46 PM PST 23
Finished Nov 22 01:51:54 PM PST 23
Peak memory 238672 kb
Host smart-dac681de-9f40-4380-b603-3fc66037bc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37474143327569270892224004018914655855154927487566385829078805371840936649807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.37474143327569270892224004018914655855154927487566385829078805371840936649807
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.90860687887372775521261408408797868111719177386342650809954321053146315111766
Short name T640
Test name
Test status
Simulation time 150268849183 ps
CPU time 1984.92 seconds
Started Nov 22 01:51:05 PM PST 23
Finished Nov 22 02:24:12 PM PST 23
Peak memory 517592 kb
Host smart-c23f8d2d-8fb2-4e50-9e34-894b65f53537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9086068788737277552126
1408408797868111719177386342650809954321053146315111766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_res
et.90860687887372775521261408408797868111719177386342650809954321053146315111766
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.74340456353301027761111153811599225560027809427394478145878500871517324190941
Short name T1096
Test name
Test status
Simulation time 156689183 ps
CPU time 4.26 seconds
Started Nov 22 01:51:39 PM PST 23
Finished Nov 22 01:51:48 PM PST 23
Peak memory 238660 kb
Host smart-e981c903-083e-4284-baea-5ad22cf1e40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74340456353301027761111153811599225560027809427394478145878500871517324190941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 52.otp_ctrl_init_fail.74340456353301027761111153811599225560027809427394478145878500871517324190941
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.31213811982871150489649993048892960858642922363826188020598812267279354603651
Short name T280
Test name
Test status
Simulation time 176929183 ps
CPU time 4.17 seconds
Started Nov 22 01:51:24 PM PST 23
Finished Nov 22 01:51:31 PM PST 23
Peak memory 238492 kb
Host smart-46c60ee7-154d-451d-8ef8-9be06ecf0e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31213811982871150489649993048892960858642922363826188020598812267279354603651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.31213811982871150489649993048892960858642922363826188020598812267279354603651
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.61943418507775251879101213980032483879599562608675841761141806139267395550886
Short name T1153
Test name
Test status
Simulation time 150268849183 ps
CPU time 1953.06 seconds
Started Nov 22 01:51:32 PM PST 23
Finished Nov 22 02:24:09 PM PST 23
Peak memory 517428 kb
Host smart-cce4dc28-85f0-473b-bb9d-e2e658b7e581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6194341850777525187910
1213980032483879599562608675841761141806139267395550886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_res
et.61943418507775251879101213980032483879599562608675841761141806139267395550886
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.12989088572508937243850522484574226677373998980468436643141062132808637458114
Short name T702
Test name
Test status
Simulation time 156689183 ps
CPU time 4.08 seconds
Started Nov 22 01:51:07 PM PST 23
Finished Nov 22 01:51:13 PM PST 23
Peak memory 238484 kb
Host smart-71a2349b-bf7d-4a19-a9af-10b59c77d918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12989088572508937243850522484574226677373998980468436643141062132808637458114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 53.otp_ctrl_init_fail.12989088572508937243850522484574226677373998980468436643141062132808637458114
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.104041849142137682496412704208400301609906278848903724850552043580577152245788
Short name T340
Test name
Test status
Simulation time 176929183 ps
CPU time 4.41 seconds
Started Nov 22 01:51:40 PM PST 23
Finished Nov 22 01:51:49 PM PST 23
Peak memory 238628 kb
Host smart-d6e76a7d-e2bc-47bc-8433-dcbedbce8bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104041849142137682496412704208400301609906278848903724850552043580577152245788 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.104041849142137682496412704208400301609906278848903724850552043580577152245788
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.4340672308496590444459584357065997861509972382953710023100068986699719634091
Short name T686
Test name
Test status
Simulation time 150268849183 ps
CPU time 1981.09 seconds
Started Nov 22 01:51:25 PM PST 23
Finished Nov 22 02:24:30 PM PST 23
Peak memory 517544 kb
Host smart-75e426b7-2a83-4a07-807b-e8488a8e98bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4340672308496590444459
584357065997861509972382953710023100068986699719634091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_rese
t.4340672308496590444459584357065997861509972382953710023100068986699719634091
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.32038861071271817542387075326507261510897463521729533678655538558748614436682
Short name T504
Test name
Test status
Simulation time 156689183 ps
CPU time 4.02 seconds
Started Nov 22 01:51:22 PM PST 23
Finished Nov 22 01:51:28 PM PST 23
Peak memory 238468 kb
Host smart-d9ebaa3d-8bf1-478f-85d1-29fdacada803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32038861071271817542387075326507261510897463521729533678655538558748614436682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 54.otp_ctrl_init_fail.32038861071271817542387075326507261510897463521729533678655538558748614436682
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.79818812841329503660854374110254402069765811401118408029612215826479511286748
Short name T1162
Test name
Test status
Simulation time 176929183 ps
CPU time 4.44 seconds
Started Nov 22 01:51:17 PM PST 23
Finished Nov 22 01:51:23 PM PST 23
Peak memory 238680 kb
Host smart-3479be1c-e7a2-4a04-94ed-eca398ffde02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79818812841329503660854374110254402069765811401118408029612215826479511286748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.79818812841329503660854374110254402069765811401118408029612215826479511286748
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.34495083259782748657027034715275250195035878473086049934566798572586696438576
Short name T923
Test name
Test status
Simulation time 150268849183 ps
CPU time 1963.79 seconds
Started Nov 22 01:51:25 PM PST 23
Finished Nov 22 02:24:12 PM PST 23
Peak memory 517604 kb
Host smart-69860aef-ed61-4f63-bfe0-dc465b7d3e11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449508325978274865702
7034715275250195035878473086049934566798572586696438576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_res
et.34495083259782748657027034715275250195035878473086049934566798572586696438576
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.77329101247475209179647703901927875257308566427735816990871440478166852019998
Short name T797
Test name
Test status
Simulation time 156689183 ps
CPU time 4.02 seconds
Started Nov 22 01:51:34 PM PST 23
Finished Nov 22 01:51:41 PM PST 23
Peak memory 238584 kb
Host smart-751a8a33-3292-4419-ab5e-5ea8b5194713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77329101247475209179647703901927875257308566427735816990871440478166852019998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 55.otp_ctrl_init_fail.77329101247475209179647703901927875257308566427735816990871440478166852019998
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.85631464685219870595998732913074419783556402228025503811327708692375843922385
Short name T221
Test name
Test status
Simulation time 176929183 ps
CPU time 4.21 seconds
Started Nov 22 01:51:30 PM PST 23
Finished Nov 22 01:51:37 PM PST 23
Peak memory 238644 kb
Host smart-f73b26de-2bcd-48af-af0a-5d75ef09992b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85631464685219870595998732913074419783556402228025503811327708692375843922385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.85631464685219870595998732913074419783556402228025503811327708692375843922385
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.23132227380373851866596947057499711022892651473579010277692417563344835411202
Short name T518
Test name
Test status
Simulation time 150268849183 ps
CPU time 1969.41 seconds
Started Nov 22 01:51:29 PM PST 23
Finished Nov 22 02:24:21 PM PST 23
Peak memory 517600 kb
Host smart-7293335d-59ad-454e-986c-a116d1d4d5d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313222738037385186659
6947057499711022892651473579010277692417563344835411202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_res
et.23132227380373851866596947057499711022892651473579010277692417563344835411202
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.58322472069611974835108458024728197643538173651277256266978625719825766330547
Short name T343
Test name
Test status
Simulation time 156689183 ps
CPU time 4.21 seconds
Started Nov 22 01:51:08 PM PST 23
Finished Nov 22 01:51:14 PM PST 23
Peak memory 238648 kb
Host smart-e532651b-088f-4065-b8bf-325331e85f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58322472069611974835108458024728197643538173651277256266978625719825766330547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 56.otp_ctrl_init_fail.58322472069611974835108458024728197643538173651277256266978625719825766330547
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.59740476526888240658538056750587799901307376342612705353902457511889477729864
Short name T669
Test name
Test status
Simulation time 176929183 ps
CPU time 4.26 seconds
Started Nov 22 01:51:34 PM PST 23
Finished Nov 22 01:51:42 PM PST 23
Peak memory 238540 kb
Host smart-8f567018-f44e-49bf-8b0c-5322abf464bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59740476526888240658538056750587799901307376342612705353902457511889477729864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.59740476526888240658538056750587799901307376342612705353902457511889477729864
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.51216716174433401592062435889347463578211000856180906773914804202576139192514
Short name T344
Test name
Test status
Simulation time 150268849183 ps
CPU time 1879.03 seconds
Started Nov 22 01:51:28 PM PST 23
Finished Nov 22 02:22:50 PM PST 23
Peak memory 517484 kb
Host smart-d816a0cf-a258-4583-8a24-86b84b5b2a7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5121671617443340159206
2435889347463578211000856180906773914804202576139192514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_res
et.51216716174433401592062435889347463578211000856180906773914804202576139192514
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.50606887287298216468503077131651609254549379267268573671644067069744567837148
Short name T802
Test name
Test status
Simulation time 156689183 ps
CPU time 3.81 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:27 PM PST 23
Peak memory 238616 kb
Host smart-4f959f31-6013-45bf-b37e-2f1050749c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50606887287298216468503077131651609254549379267268573671644067069744567837148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 57.otp_ctrl_init_fail.50606887287298216468503077131651609254549379267268573671644067069744567837148
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.88892171200904220975898281720567892240407587940033183241310645066859412864215
Short name T357
Test name
Test status
Simulation time 176929183 ps
CPU time 4.37 seconds
Started Nov 22 01:51:12 PM PST 23
Finished Nov 22 01:51:19 PM PST 23
Peak memory 238612 kb
Host smart-525e49d2-dec5-49f6-8cba-3192110feed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88892171200904220975898281720567892240407587940033183241310645066859412864215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.88892171200904220975898281720567892240407587940033183241310645066859412864215
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.66727954006297712097443740293649488086598351377408301461406766779035627627812
Short name T753
Test name
Test status
Simulation time 150268849183 ps
CPU time 1997.46 seconds
Started Nov 22 01:51:42 PM PST 23
Finished Nov 22 02:25:04 PM PST 23
Peak memory 517528 kb
Host smart-b7fd52a3-c457-4b53-9444-ae43eef6b271
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6672795400629771209744
3740293649488086598351377408301461406766779035627627812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_res
et.66727954006297712097443740293649488086598351377408301461406766779035627627812
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.9270193887407709768719767648603092397578064141440028712739801260942857627076
Short name T465
Test name
Test status
Simulation time 156689183 ps
CPU time 3.96 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 01:51:27 PM PST 23
Peak memory 238624 kb
Host smart-8cfb1eda-f3e1-4035-af21-36e9e0128f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9270193887407709768719767648603092397578064141440028712739801260942857627076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 58.otp_ctrl_init_fail.9270193887407709768719767648603092397578064141440028712739801260942857627076
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.66953112380104730253910229263481837040647147780033017657791035713961696555617
Short name T495
Test name
Test status
Simulation time 176929183 ps
CPU time 4.32 seconds
Started Nov 22 01:51:20 PM PST 23
Finished Nov 22 01:51:27 PM PST 23
Peak memory 238640 kb
Host smart-4c07fa66-83ab-489f-8d76-b235ca01e24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66953112380104730253910229263481837040647147780033017657791035713961696555617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.66953112380104730253910229263481837040647147780033017657791035713961696555617
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.31770444502308801467542633974881351612441853854304582073271153641893880610221
Short name T1024
Test name
Test status
Simulation time 150268849183 ps
CPU time 1930.46 seconds
Started Nov 22 01:51:19 PM PST 23
Finished Nov 22 02:23:32 PM PST 23
Peak memory 517380 kb
Host smart-d2120b58-5d0e-4be7-8d59-7138ed3aa1ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177044450230880146754
2633974881351612441853854304582073271153641893880610221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_res
et.31770444502308801467542633974881351612441853854304582073271153641893880610221
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.13874958055239405547176787329908421446283511861674715800327471825519714934789
Short name T372
Test name
Test status
Simulation time 156689183 ps
CPU time 4.07 seconds
Started Nov 22 01:51:30 PM PST 23
Finished Nov 22 01:51:37 PM PST 23
Peak memory 238588 kb
Host smart-d9b458e7-9546-4169-a130-d9e6fa961ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13874958055239405547176787329908421446283511861674715800327471825519714934789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 59.otp_ctrl_init_fail.13874958055239405547176787329908421446283511861674715800327471825519714934789
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.9077322692979677247366584203589793496580145465977233450346078871177520383439
Short name T428
Test name
Test status
Simulation time 176929183 ps
CPU time 4.77 seconds
Started Nov 22 01:51:38 PM PST 23
Finished Nov 22 01:51:48 PM PST 23
Peak memory 238536 kb
Host smart-251e5a0e-b42f-4f29-aad1-67ec5742912c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9077322692979677247366584203589793496580145465977233450346078871177520383439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.9077322692979677247366584203589793496580145465977233450346078871177520383439
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.51592196668192632088939029414009441588561527276596544660628984790531963079113
Short name T613
Test name
Test status
Simulation time 150268849183 ps
CPU time 1959.36 seconds
Started Nov 22 01:51:32 PM PST 23
Finished Nov 22 02:24:15 PM PST 23
Peak memory 517560 kb
Host smart-f3aefe00-c52e-4258-84b2-6774ce9be742
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5159219666819263208893
9029414009441588561527276596544660628984790531963079113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_res
et.51592196668192632088939029414009441588561527276596544660628984790531963079113
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.103895108611761355536473725655593151978577691561615750415362372212318596984814
Short name T598
Test name
Test status
Simulation time 71069183 ps
CPU time 1.81 seconds
Started Nov 22 01:51:00 PM PST 23
Finished Nov 22 01:51:02 PM PST 23
Peak memory 238448 kb
Host smart-b95ac6e3-119e-4b88-a38b-19bdd7161432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103895108611761355536473725655593151978577691561615750415362372212318596984814 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.103895108611761355536473725655593151978577691561615750415362372212318596984814
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.53503905166070772372567054223710972783701075884208165281314186034951435776489
Short name T94
Test name
Test status
Simulation time 190889183 ps
CPU time 4.65 seconds
Started Nov 22 01:50:51 PM PST 23
Finished Nov 22 01:50:57 PM PST 23
Peak memory 238672 kb
Host smart-44d461b1-5374-43cd-a0c6-39d2c7bff6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53503905166070772372567054223710972783701075884208165281314186034951435776489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 6.otp_ctrl_background_chks.53503905166070772372567054223710972783701075884208165281314186034951435776489
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.44204192130819052847190940926835242553583844304707221160742481893659671823460
Short name T539
Test name
Test status
Simulation time 111269183 ps
CPU time 2.71 seconds
Started Nov 22 01:50:54 PM PST 23
Finished Nov 22 01:50:58 PM PST 23
Peak memory 246800 kb
Host smart-b7962cb0-fdb9-4226-8829-cf464a2523ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44204192130819052847190940926835242553583844304707221160742481893659671823460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.otp_ctrl_check_fail.44204192130819052847190940926835242553583844304707221160742481893659671823460
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.7828859639310415806108953570186373612804977848217086109591275480569492250286
Short name T19
Test name
Test status
Simulation time 390019183 ps
CPU time 11.23 seconds
Started Nov 22 01:50:42 PM PST 23
Finished Nov 22 01:50:54 PM PST 23
Peak memory 238536 kb
Host smart-012a56d4-300f-4cd4-b1ce-54d8110f4e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7828859639310415806108953570186373612804977848217086109591275480569492250286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.otp_ctrl_dai_errs.7828859639310415806108953570186373612804977848217086109591275480569492250286
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.46385439625596914176548320628281696851883951729614036909006973598236412750719
Short name T572
Test name
Test status
Simulation time 614979183 ps
CPU time 10.79 seconds
Started Nov 22 01:50:59 PM PST 23
Finished Nov 22 01:51:16 PM PST 23
Peak memory 238836 kb
Host smart-78e60c79-6683-4f09-91b2-980daffc63db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46385439625596914176548320628281696851883951729614036909006973598236412750719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.otp_ctrl_dai_lock.46385439625596914176548320628281696851883951729614036909006973598236412750719
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.45787161976537006764172081814035281821565266631325243656665548450118680462558
Short name T723
Test name
Test status
Simulation time 156689183 ps
CPU time 3.96 seconds
Started Nov 22 01:50:26 PM PST 23
Finished Nov 22 01:50:31 PM PST 23
Peak memory 238532 kb
Host smart-dc9da458-2c8e-4cc0-8859-d5fd34e43eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45787161976537006764172081814035281821565266631325243656665548450118680462558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.otp_ctrl_init_fail.45787161976537006764172081814035281821565266631325243656665548450118680462558
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.103578358762694620892905187704940900966010378344754047670967310861876239403776
Short name T407
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.47 seconds
Started Nov 22 01:50:48 PM PST 23
Finished Nov 22 01:51:08 PM PST 23
Peak memory 238988 kb
Host smart-6071e8d0-d50c-4c2c-a664-52f5150c650e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103578358762694620892905187704940900966010378344754047670967310861876239403776 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.otp_ctrl_macro_errs.103578358762694620892905187704940900966010378344754047670967310861876239403776
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.64516905172373102636903587303093569531029668833898147295712479559271680719826
Short name T128
Test name
Test status
Simulation time 346349183 ps
CPU time 7.68 seconds
Started Nov 22 01:50:41 PM PST 23
Finished Nov 22 01:50:50 PM PST 23
Peak memory 238724 kb
Host smart-98abdb28-d825-4a46-a0c9-b11cf449326b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64516905172373102636903587303093569531029668833898147295712479559271680719826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.otp_ctrl_parallel_key_req.64516905172373102636903587303093569531029668833898147295712479559271680719826
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.80899796908777034014434677494677333653077703414486607527491862150115169933841
Short name T777
Test name
Test status
Simulation time 176929183 ps
CPU time 4.32 seconds
Started Nov 22 01:50:49 PM PST 23
Finished Nov 22 01:50:54 PM PST 23
Peak memory 238656 kb
Host smart-637d5bfd-aa83-425c-a9e6-ed44e76c7146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80899796908777034014434677494677333653077703414486607527491862150115169933841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.80899796908777034014434677494677333653077703414486607527491862150115169933841
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.105788214471768482189932735408622328208194608675163095339707746799822218708750
Short name T744
Test name
Test status
Simulation time 486419183 ps
CPU time 11.51 seconds
Started Nov 22 01:51:00 PM PST 23
Finished Nov 22 01:51:12 PM PST 23
Peak memory 238724 kb
Host smart-b3673755-c726-402e-9258-c59e6323e8ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105788214471768482189932735408622328208194608675163095339707746799822218708750 -assert nopostproc +UVM_TE
STNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.105788214471768482189932735408622328208194608675163095339707746799822218708750
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.110602075666700280586498635115141378361015918189646270476291591655176419355764
Short name T601
Test name
Test status
Simulation time 137469183 ps
CPU time 3.68 seconds
Started Nov 22 01:51:08 PM PST 23
Finished Nov 22 01:51:14 PM PST 23
Peak memory 238660 kb
Host smart-c8d9e463-fd10-47b3-bdd7-d3f421183c18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=110602075666700280586498635115141378361015918189646270476291591655176419355764 -assert nopostproc +UVM_TE
STNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_regwen.110602075666700280586498635115141378361015918189646270476291591655176419355764
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.4371772197849744733028099243883613447314154487425747953687855340670740403954
Short name T1196
Test name
Test status
Simulation time 138839183 ps
CPU time 3.14 seconds
Started Nov 22 01:50:32 PM PST 23
Finished Nov 22 01:50:36 PM PST 23
Peak memory 238828 kb
Host smart-ec18663e-60a8-4cf8-9267-6c4356479ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4371772197849744733028099243883613447314154487425747953687855340670740403954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.otp_ctrl_smoke.4371772197849744733028099243883613447314154487425747953687855340670740403954
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.113437408784551122087115896141802572101853225378153659081135583629677673375785
Short name T422
Test name
Test status
Simulation time 13240088340 ps
CPU time 125.46 seconds
Started Nov 22 01:51:07 PM PST 23
Finished Nov 22 01:53:15 PM PST 23
Peak memory 241796 kb
Host smart-501cf87e-fff8-492b-ace1-f8621e1aff5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113437408784551122087115896141802572101853225378153659081135583629677673375785 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.113437408784551122087115896141802572101853225378153659081135583629677673375785
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.8379954987746763948920739891576594356351321051107738262360805984765045032934
Short name T446
Test name
Test status
Simulation time 150268849183 ps
CPU time 1961.21 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 02:22:50 PM PST 23
Peak memory 517672 kb
Host smart-2589f66b-1de1-466b-aabc-0fcc3383dc95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8379954987746763948920
739891576594356351321051107738262360805984765045032934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset
.8379954987746763948920739891576594356351321051107738262360805984765045032934
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.74877406773207403248983179307362005822403110103339502444085275310930350169676
Short name T950
Test name
Test status
Simulation time 549639183 ps
CPU time 9.35 seconds
Started Nov 22 01:50:04 PM PST 23
Finished Nov 22 01:50:17 PM PST 23
Peak memory 247016 kb
Host smart-c715f737-7c2b-4b4a-993f-41c1717cfc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74877406773207403248983179307362005822403110103339502444085275310930350169676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.otp_ctrl_test_access.74877406773207403248983179307362005822403110103339502444085275310930350169676
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.19570069409550136411557776472314511304539900309276897997898202937015937831280
Short name T1132
Test name
Test status
Simulation time 156689183 ps
CPU time 4.04 seconds
Started Nov 22 01:51:40 PM PST 23
Finished Nov 22 01:51:49 PM PST 23
Peak memory 238520 kb
Host smart-67a29093-86e3-4b24-b87d-396d81c40dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19570069409550136411557776472314511304539900309276897997898202937015937831280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 60.otp_ctrl_init_fail.19570069409550136411557776472314511304539900309276897997898202937015937831280
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.60670238171969309654186510695607071304548479981409107348970344492040769512624
Short name T891
Test name
Test status
Simulation time 176929183 ps
CPU time 4.36 seconds
Started Nov 22 01:51:32 PM PST 23
Finished Nov 22 01:51:39 PM PST 23
Peak memory 238684 kb
Host smart-cb74355d-667f-43e2-b689-720a212ed118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60670238171969309654186510695607071304548479981409107348970344492040769512624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.60670238171969309654186510695607071304548479981409107348970344492040769512624
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.53079042496177572863349404361053135590878571632261455623138917090578023054968
Short name T758
Test name
Test status
Simulation time 150268849183 ps
CPU time 1912.44 seconds
Started Nov 22 01:51:16 PM PST 23
Finished Nov 22 02:23:11 PM PST 23
Peak memory 517380 kb
Host smart-0f8358d2-e528-42c7-b7b3-4e0ca2e1c581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5307904249617757286334
9404361053135590878571632261455623138917090578023054968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_res
et.53079042496177572863349404361053135590878571632261455623138917090578023054968
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.104343086018657547373768923787132560392172411505965837616124640541117186033947
Short name T1138
Test name
Test status
Simulation time 156689183 ps
CPU time 3.92 seconds
Started Nov 22 01:51:49 PM PST 23
Finished Nov 22 01:51:55 PM PST 23
Peak memory 238628 kb
Host smart-e6197ccb-4053-416b-bcf0-05b19c84b9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104343086018657547373768923787132560392172411505965837616124640541117186033947 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 61.otp_ctrl_init_fail.104343086018657547373768923787132560392172411505965837616124640541117186033947
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.15948053024549398393485266331824444748227025582545879296529558412331776224503
Short name T375
Test name
Test status
Simulation time 176929183 ps
CPU time 4.24 seconds
Started Nov 22 01:51:37 PM PST 23
Finished Nov 22 01:51:45 PM PST 23
Peak memory 238408 kb
Host smart-906e9b31-1994-4817-8cb7-54f3b3863138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15948053024549398393485266331824444748227025582545879296529558412331776224503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.15948053024549398393485266331824444748227025582545879296529558412331776224503
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.97103803597348235404625126637001424257438553736151251712503307228284677596141
Short name T843
Test name
Test status
Simulation time 150268849183 ps
CPU time 1919.93 seconds
Started Nov 22 01:51:29 PM PST 23
Finished Nov 22 02:23:31 PM PST 23
Peak memory 517604 kb
Host smart-735f97e2-6427-409f-9769-d2bca255ee54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9710380359734823540462
5126637001424257438553736151251712503307228284677596141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_res
et.97103803597348235404625126637001424257438553736151251712503307228284677596141
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.88304791905387243045602310425883974978141877022073963334281430819461154628640
Short name T623
Test name
Test status
Simulation time 156689183 ps
CPU time 4.05 seconds
Started Nov 22 01:51:15 PM PST 23
Finished Nov 22 01:51:21 PM PST 23
Peak memory 238576 kb
Host smart-dfdb3910-6a01-4814-b55f-0d9cf9bd7395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88304791905387243045602310425883974978141877022073963334281430819461154628640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 62.otp_ctrl_init_fail.88304791905387243045602310425883974978141877022073963334281430819461154628640
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.86760347581080270893603933186226777384615503858165999587919933492187100167774
Short name T548
Test name
Test status
Simulation time 176929183 ps
CPU time 4.19 seconds
Started Nov 22 01:51:37 PM PST 23
Finished Nov 22 01:51:46 PM PST 23
Peak memory 238632 kb
Host smart-ba4d424d-8224-4a8b-b1df-23e1c6f9bcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86760347581080270893603933186226777384615503858165999587919933492187100167774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.86760347581080270893603933186226777384615503858165999587919933492187100167774
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.30821949156408839301484668556586198988132237348633526440927278099436533483403
Short name T1120
Test name
Test status
Simulation time 150268849183 ps
CPU time 1926.68 seconds
Started Nov 22 01:51:25 PM PST 23
Finished Nov 22 02:23:35 PM PST 23
Peak memory 517560 kb
Host smart-4cab6c92-e243-4f65-94bf-98ee1a7cdf7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082194915640883930148
4668556586198988132237348633526440927278099436533483403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_res
et.30821949156408839301484668556586198988132237348633526440927278099436533483403
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.53832730260567007894574101375622687905755913504670468716564621089983764311850
Short name T290
Test name
Test status
Simulation time 156689183 ps
CPU time 4.08 seconds
Started Nov 22 01:51:42 PM PST 23
Finished Nov 22 01:51:50 PM PST 23
Peak memory 238576 kb
Host smart-0d9f6f83-d473-495b-bb1d-4199d8a5c39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53832730260567007894574101375622687905755913504670468716564621089983764311850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 63.otp_ctrl_init_fail.53832730260567007894574101375622687905755913504670468716564621089983764311850
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.112735070718724240717559784732588466291020690751616915123218743168242225216522
Short name T483
Test name
Test status
Simulation time 176929183 ps
CPU time 4.57 seconds
Started Nov 22 01:51:33 PM PST 23
Finished Nov 22 01:51:41 PM PST 23
Peak memory 238608 kb
Host smart-a8f2a368-6d42-4f98-a013-89ce06ddcad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112735070718724240717559784732588466291020690751616915123218743168242225216522 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.112735070718724240717559784732588466291020690751616915123218743168242225216522
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.22650277345283779275612800451783920964046293195134149445033302930165963507786
Short name T556
Test name
Test status
Simulation time 150268849183 ps
CPU time 1939.26 seconds
Started Nov 22 01:51:29 PM PST 23
Finished Nov 22 02:23:52 PM PST 23
Peak memory 517592 kb
Host smart-b382c6b0-691e-4c7b-8d3c-453478d76622
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265027734528377927561
2800451783920964046293195134149445033302930165963507786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_res
et.22650277345283779275612800451783920964046293195134149445033302930165963507786
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.51980207308516892878849734998719390093662970235904012462836362536055665400991
Short name T322
Test name
Test status
Simulation time 156689183 ps
CPU time 4.07 seconds
Started Nov 22 01:51:12 PM PST 23
Finished Nov 22 01:51:18 PM PST 23
Peak memory 238620 kb
Host smart-dd500d33-d828-4a67-80d6-a737e88db49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51980207308516892878849734998719390093662970235904012462836362536055665400991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 64.otp_ctrl_init_fail.51980207308516892878849734998719390093662970235904012462836362536055665400991
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.73093427584436976130314773557521657965836003316124125804890921806975207302527
Short name T1074
Test name
Test status
Simulation time 176929183 ps
CPU time 4.27 seconds
Started Nov 22 01:51:44 PM PST 23
Finished Nov 22 01:51:52 PM PST 23
Peak memory 238608 kb
Host smart-b59e8a80-a7fc-4ec1-ac3b-b3f6f1ac7571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73093427584436976130314773557521657965836003316124125804890921806975207302527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.73093427584436976130314773557521657965836003316124125804890921806975207302527
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.33456733934111808616587942818784352690742722899243191485894307212589835951918
Short name T878
Test name
Test status
Simulation time 150268849183 ps
CPU time 1969.94 seconds
Started Nov 22 01:51:37 PM PST 23
Finished Nov 22 02:24:31 PM PST 23
Peak memory 517520 kb
Host smart-c0e20891-ed78-4bd0-a50c-db29a37c97de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345673393411180861658
7942818784352690742722899243191485894307212589835951918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_res
et.33456733934111808616587942818784352690742722899243191485894307212589835951918
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.105813097108840888287870753897328809536716677590490431503671330992182151429566
Short name T651
Test name
Test status
Simulation time 156689183 ps
CPU time 4.03 seconds
Started Nov 22 01:51:37 PM PST 23
Finished Nov 22 01:51:46 PM PST 23
Peak memory 238576 kb
Host smart-4a470c7a-7760-47e6-ac5c-a49ae7ddffc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105813097108840888287870753897328809536716677590490431503671330992182151429566 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 65.otp_ctrl_init_fail.105813097108840888287870753897328809536716677590490431503671330992182151429566
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.111713518105804940817393623622038864682470077129666623688431204461312667966213
Short name T567
Test name
Test status
Simulation time 176929183 ps
CPU time 4.4 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:52 PM PST 23
Peak memory 238712 kb
Host smart-a1001e7f-2720-41ff-8c4e-c8519d9dfcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111713518105804940817393623622038864682470077129666623688431204461312667966213 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.111713518105804940817393623622038864682470077129666623688431204461312667966213
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.1171202486554710566041048735305261507582281014244659559884352324107526465348
Short name T1136
Test name
Test status
Simulation time 150268849183 ps
CPU time 1984.11 seconds
Started Nov 22 01:51:45 PM PST 23
Finished Nov 22 02:24:53 PM PST 23
Peak memory 517504 kb
Host smart-e3e0bd07-e6dd-403b-9d21-987019a6cb67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171202486554710566041
048735305261507582281014244659559884352324107526465348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_rese
t.1171202486554710566041048735305261507582281014244659559884352324107526465348
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.25649699085044706785465121448317843597158709621200917634347132145291914155047
Short name T475
Test name
Test status
Simulation time 156689183 ps
CPU time 3.89 seconds
Started Nov 22 01:51:26 PM PST 23
Finished Nov 22 01:51:33 PM PST 23
Peak memory 238656 kb
Host smart-ceedaee3-fb28-48aa-9f17-1a128957e5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25649699085044706785465121448317843597158709621200917634347132145291914155047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 66.otp_ctrl_init_fail.25649699085044706785465121448317843597158709621200917634347132145291914155047
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.107388464816301086784283907693688690804375112007099004992127358073046842293713
Short name T1281
Test name
Test status
Simulation time 176929183 ps
CPU time 4.23 seconds
Started Nov 22 01:51:04 PM PST 23
Finished Nov 22 01:51:10 PM PST 23
Peak memory 238688 kb
Host smart-eb7e2b0e-664d-457d-aedd-a793fe01be1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107388464816301086784283907693688690804375112007099004992127358073046842293713 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.107388464816301086784283907693688690804375112007099004992127358073046842293713
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.84231384899756296424820120480092568229171012892353208184295094706120532250302
Short name T76
Test name
Test status
Simulation time 150268849183 ps
CPU time 1987.76 seconds
Started Nov 22 01:51:21 PM PST 23
Finished Nov 22 02:24:31 PM PST 23
Peak memory 517504 kb
Host smart-7db384e3-f615-4b48-8e21-71b3875d7446
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8423138489975629642482
0120480092568229171012892353208184295094706120532250302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_res
et.84231384899756296424820120480092568229171012892353208184295094706120532250302
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.113506601352830830554485308411350125503491555521663617343947553935981302730736
Short name T851
Test name
Test status
Simulation time 156689183 ps
CPU time 3.89 seconds
Started Nov 22 01:51:08 PM PST 23
Finished Nov 22 01:51:14 PM PST 23
Peak memory 238476 kb
Host smart-29c25e85-fa0c-4af4-9fcb-059acf84392e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113506601352830830554485308411350125503491555521663617343947553935981302730736 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 67.otp_ctrl_init_fail.113506601352830830554485308411350125503491555521663617343947553935981302730736
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.113604050344521656762264077092125293153683073342472627206103628743192249972537
Short name T1010
Test name
Test status
Simulation time 176929183 ps
CPU time 4.35 seconds
Started Nov 22 01:51:42 PM PST 23
Finished Nov 22 01:51:51 PM PST 23
Peak memory 238712 kb
Host smart-5ed67846-b94f-4591-827c-0cddc9267f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113604050344521656762264077092125293153683073342472627206103628743192249972537 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.113604050344521656762264077092125293153683073342472627206103628743192249972537
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.21867335914905363830750124228103462097443297975346642209274483557980015600990
Short name T857
Test name
Test status
Simulation time 150268849183 ps
CPU time 1975.89 seconds
Started Nov 22 01:51:11 PM PST 23
Finished Nov 22 02:24:08 PM PST 23
Peak memory 517556 kb
Host smart-bbb1d5f6-0c7b-422c-ae31-8609433c930b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186733591490536383075
0124228103462097443297975346642209274483557980015600990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_res
et.21867335914905363830750124228103462097443297975346642209274483557980015600990
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.94575850908689156717370446874756888848792381387957196639592564361506915736337
Short name T279
Test name
Test status
Simulation time 156689183 ps
CPU time 3.9 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:51 PM PST 23
Peak memory 238656 kb
Host smart-0f29ae1d-3d6f-49a9-abed-b293d57b7801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94575850908689156717370446874756888848792381387957196639592564361506915736337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 68.otp_ctrl_init_fail.94575850908689156717370446874756888848792381387957196639592564361506915736337
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.16875395834199335896878345126163142244401697162057350819901112834689840968845
Short name T1049
Test name
Test status
Simulation time 176929183 ps
CPU time 4.16 seconds
Started Nov 22 01:51:32 PM PST 23
Finished Nov 22 01:51:39 PM PST 23
Peak memory 238632 kb
Host smart-0381aa40-27d1-4fe4-928a-b40c165d4748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16875395834199335896878345126163142244401697162057350819901112834689840968845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.16875395834199335896878345126163142244401697162057350819901112834689840968845
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.8348471647239707881678023335939813818449490797784322648179977009673100278221
Short name T1192
Test name
Test status
Simulation time 150268849183 ps
CPU time 1933.79 seconds
Started Nov 22 01:51:31 PM PST 23
Finished Nov 22 02:23:48 PM PST 23
Peak memory 517520 kb
Host smart-5f780873-cb6c-49c5-893e-812acf9b045e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8348471647239707881678
023335939813818449490797784322648179977009673100278221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_rese
t.8348471647239707881678023335939813818449490797784322648179977009673100278221
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.86163159700047188047842374391572107103292745589188456797239634445848025221702
Short name T865
Test name
Test status
Simulation time 156689183 ps
CPU time 3.98 seconds
Started Nov 22 01:51:35 PM PST 23
Finished Nov 22 01:51:43 PM PST 23
Peak memory 238576 kb
Host smart-2d134672-e4bc-4a03-8abb-bcd850092479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86163159700047188047842374391572107103292745589188456797239634445848025221702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 69.otp_ctrl_init_fail.86163159700047188047842374391572107103292745589188456797239634445848025221702
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.9259188168684895776741750887856586788119893697380577818981641568936483823051
Short name T1053
Test name
Test status
Simulation time 176929183 ps
CPU time 4.26 seconds
Started Nov 22 01:51:35 PM PST 23
Finished Nov 22 01:51:43 PM PST 23
Peak memory 238632 kb
Host smart-fb71ba38-1d99-41d8-81bf-52790cf4fd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9259188168684895776741750887856586788119893697380577818981641568936483823051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.9259188168684895776741750887856586788119893697380577818981641568936483823051
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.64355794748530365546255127670002989624480183678180821491416615364337400107507
Short name T827
Test name
Test status
Simulation time 150268849183 ps
CPU time 1954.52 seconds
Started Nov 22 01:51:36 PM PST 23
Finished Nov 22 02:24:15 PM PST 23
Peak memory 517484 kb
Host smart-314e12b9-88e1-46a4-9f3a-894d33dfc12f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6435579474853036554625
5127670002989624480183678180821491416615364337400107507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_res
et.64355794748530365546255127670002989624480183678180821491416615364337400107507
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.32938101035935037996445733023613457771421036162044528709126877667308281616054
Short name T937
Test name
Test status
Simulation time 71069183 ps
CPU time 1.88 seconds
Started Nov 22 01:50:20 PM PST 23
Finished Nov 22 01:50:25 PM PST 23
Peak memory 238356 kb
Host smart-608745bb-12c7-47f4-bcb3-007a216e5ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32938101035935037996445733023613457771421036162044528709126877667308281616054 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.32938101035935037996445733023613457771421036162044528709126877667308281616054
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.69175842604646373203125505885401039859006684603927388043860649196699850013266
Short name T418
Test name
Test status
Simulation time 190889183 ps
CPU time 4.61 seconds
Started Nov 22 01:50:10 PM PST 23
Finished Nov 22 01:50:22 PM PST 23
Peak memory 238820 kb
Host smart-d28ecc48-be41-46cc-a353-d81cb1964dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69175842604646373203125505885401039859006684603927388043860649196699850013266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.otp_ctrl_background_chks.69175842604646373203125505885401039859006684603927388043860649196699850013266
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.65050894148005764062251306217997960382320034554138294379127716085951520544868
Short name T1091
Test name
Test status
Simulation time 111269183 ps
CPU time 2.72 seconds
Started Nov 22 01:50:13 PM PST 23
Finished Nov 22 01:50:21 PM PST 23
Peak memory 246728 kb
Host smart-0fb21fa3-ac5e-4afa-ac1c-1a173c2bb2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65050894148005764062251306217997960382320034554138294379127716085951520544868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.otp_ctrl_check_fail.65050894148005764062251306217997960382320034554138294379127716085951520544868
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.99422022333615250652931029521064867248067162647058693334238714957056282985835
Short name T1055
Test name
Test status
Simulation time 390019183 ps
CPU time 10.7 seconds
Started Nov 22 01:50:01 PM PST 23
Finished Nov 22 01:50:15 PM PST 23
Peak memory 238664 kb
Host smart-7e4dcb1d-4c20-4b4e-b6bb-133b988dc339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99422022333615250652931029521064867248067162647058693334238714957056282985835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.otp_ctrl_dai_errs.99422022333615250652931029521064867248067162647058693334238714957056282985835
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.33437734973198063329263954738783123982947573062567861650171086813579038346455
Short name T676
Test name
Test status
Simulation time 614979183 ps
CPU time 10.56 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 01:50:19 PM PST 23
Peak memory 238832 kb
Host smart-dd9d9c8b-884e-4d28-81ce-5b84bf748638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33437734973198063329263954738783123982947573062567861650171086813579038346455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.otp_ctrl_dai_lock.33437734973198063329263954738783123982947573062567861650171086813579038346455
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.10718863206603168405285131598642061747959321420094920517523995995445144330460
Short name T1173
Test name
Test status
Simulation time 156689183 ps
CPU time 3.97 seconds
Started Nov 22 01:50:10 PM PST 23
Finished Nov 22 01:50:21 PM PST 23
Peak memory 238648 kb
Host smart-4716b78f-a469-4f98-b8a3-64eae72c3a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10718863206603168405285131598642061747959321420094920517523995995445144330460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.otp_ctrl_init_fail.10718863206603168405285131598642061747959321420094920517523995995445144330460
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.4200678212356168768747499669358531522006377816758236022601663220365921331231
Short name T540
Test name
Test status
Simulation time 1137629183 ps
CPU time 19 seconds
Started Nov 22 01:50:00 PM PST 23
Finished Nov 22 01:50:22 PM PST 23
Peak memory 238972 kb
Host smart-c69e752e-ff9b-4035-97b6-4f85df19fadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200678212356168768747499669358531522006377816758236022601663220365921331231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.otp_ctrl_macro_errs.4200678212356168768747499669358531522006377816758236022601663220365921331231
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.40946859794593117368492966646871818776255684122146666759825365633967007957796
Short name T453
Test name
Test status
Simulation time 346349183 ps
CPU time 7.33 seconds
Started Nov 22 01:49:58 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 238736 kb
Host smart-b3f77ab0-1e81-46f4-8ba0-fa0317610482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40946859794593117368492966646871818776255684122146666759825365633967007957796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.otp_ctrl_parallel_key_req.40946859794593117368492966646871818776255684122146666759825365633967007957796
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.90511657427968187810825543067640867245364044413807213677703293185158145658382
Short name T971
Test name
Test status
Simulation time 176929183 ps
CPU time 4.49 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 01:50:13 PM PST 23
Peak memory 238516 kb
Host smart-cc90b24e-cdf7-4055-a664-1d7a0da207e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90511657427968187810825543067640867245364044413807213677703293185158145658382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.90511657427968187810825543067640867245364044413807213677703293185158145658382
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.73462909133986306654089402002304883772348627290426409662143372125479058903724
Short name T941
Test name
Test status
Simulation time 486419183 ps
CPU time 11.72 seconds
Started Nov 22 01:50:01 PM PST 23
Finished Nov 22 01:50:15 PM PST 23
Peak memory 238616 kb
Host smart-1218b456-c435-476e-b156-3cb70134a3ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73462909133986306654089402002304883772348627290426409662143372125479058903724 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.73462909133986306654089402002304883772348627290426409662143372125479058903724
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.20033373765785297779026711307247638224310139941145155036771081432863005680761
Short name T557
Test name
Test status
Simulation time 137469183 ps
CPU time 3.68 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:09 PM PST 23
Peak memory 238444 kb
Host smart-b853eefa-6b30-414e-adba-b236770787c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20033373765785297779026711307247638224310139941145155036771081432863005680761 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_regwen.20033373765785297779026711307247638224310139941145155036771081432863005680761
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.17216192534853331470169192808670519142812979576453551843936295673262721472512
Short name T727
Test name
Test status
Simulation time 138839183 ps
CPU time 3.14 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:09 PM PST 23
Peak memory 238836 kb
Host smart-c3cf9dd1-039e-4305-b42c-0c3e78da142b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17216192534853331470169192808670519142812979576453551843936295673262721472512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.otp_ctrl_smoke.17216192534853331470169192808670519142812979576453551843936295673262721472512
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.89682897010949329888994617721502870441743264148871295316084636922390174497202
Short name T410
Test name
Test status
Simulation time 13240088340 ps
CPU time 127.98 seconds
Started Nov 22 01:50:09 PM PST 23
Finished Nov 22 01:52:24 PM PST 23
Peak memory 241820 kb
Host smart-00271773-05b9-46dd-9e53-c2fda11d2315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89682897010949329888994617721502870441743264148871295316084636922390174497202 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.89682897010949329888994617721502870441743264148871295316084636922390174497202
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.106734869168611419139256024928144417597447383962954616673011438496367719248876
Short name T1280
Test name
Test status
Simulation time 150268849183 ps
CPU time 1965.65 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 02:22:54 PM PST 23
Peak memory 517532 kb
Host smart-bd743498-4c8d-47f7-9093-a8a10b668f2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067348691686114191392
56024928144417597447383962954616673011438496367719248876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_res
et.106734869168611419139256024928144417597447383962954616673011438496367719248876
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.56545775547129418380539994751747593509020469818342367868728659077087031009806
Short name T975
Test name
Test status
Simulation time 549639183 ps
CPU time 9.11 seconds
Started Nov 22 01:50:11 PM PST 23
Finished Nov 22 01:50:27 PM PST 23
Peak memory 247020 kb
Host smart-7fcfcb45-274d-4200-9ce6-e6aa594d09b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56545775547129418380539994751747593509020469818342367868728659077087031009806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.otp_ctrl_test_access.56545775547129418380539994751747593509020469818342367868728659077087031009806
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.99882214369450485412721734329265495469691699309669393138633585889105780126845
Short name T1301
Test name
Test status
Simulation time 156689183 ps
CPU time 4.03 seconds
Started Nov 22 01:51:09 PM PST 23
Finished Nov 22 01:51:15 PM PST 23
Peak memory 238576 kb
Host smart-2f3fac94-ea6b-43d6-84f6-eb3c04405cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99882214369450485412721734329265495469691699309669393138633585889105780126845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 70.otp_ctrl_init_fail.99882214369450485412721734329265495469691699309669393138633585889105780126845
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.32166220636671912034892518367594562700785544672202941424319039075444771187340
Short name T1271
Test name
Test status
Simulation time 176929183 ps
CPU time 4.34 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:52 PM PST 23
Peak memory 238708 kb
Host smart-9eb31068-2c09-4d21-b13d-e7bf2dc5c95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32166220636671912034892518367594562700785544672202941424319039075444771187340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.32166220636671912034892518367594562700785544672202941424319039075444771187340
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.50639304250819281305733542036792123387785497872279676009477081032414897247676
Short name T877
Test name
Test status
Simulation time 150268849183 ps
CPU time 1936.44 seconds
Started Nov 22 01:51:51 PM PST 23
Finished Nov 22 02:24:09 PM PST 23
Peak memory 517520 kb
Host smart-d095dc0c-cbea-4326-b480-4424eb316730
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5063930425081928130573
3542036792123387785497872279676009477081032414897247676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_res
et.50639304250819281305733542036792123387785497872279676009477081032414897247676
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.52719117007884025284979631777394389772278413498187488841662091975857631170245
Short name T369
Test name
Test status
Simulation time 156689183 ps
CPU time 3.92 seconds
Started Nov 22 01:51:29 PM PST 23
Finished Nov 22 01:51:36 PM PST 23
Peak memory 238628 kb
Host smart-f0cbe716-79be-4cb4-b78c-47b64e3ac1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52719117007884025284979631777394389772278413498187488841662091975857631170245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 71.otp_ctrl_init_fail.52719117007884025284979631777394389772278413498187488841662091975857631170245
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.18051770074782438647305614675196868341999692406393143721739287780539607336936
Short name T743
Test name
Test status
Simulation time 176929183 ps
CPU time 4.27 seconds
Started Nov 22 01:51:24 PM PST 23
Finished Nov 22 01:51:32 PM PST 23
Peak memory 238708 kb
Host smart-e01b3b62-c790-4aa0-8826-c09611ebc3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18051770074782438647305614675196868341999692406393143721739287780539607336936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.18051770074782438647305614675196868341999692406393143721739287780539607336936
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.83737433703427017235591250154922375057192125213358625871109420749528605356376
Short name T398
Test name
Test status
Simulation time 150268849183 ps
CPU time 1950.9 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 02:24:19 PM PST 23
Peak memory 517592 kb
Host smart-1b0ffd56-3ce5-4966-80a6-4feb84ee4c44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8373743370342701723559
1250154922375057192125213358625871109420749528605356376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_res
et.83737433703427017235591250154922375057192125213358625871109420749528605356376
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.57155085739749820455361144121390334138049701341112966894452676898953125778164
Short name T391
Test name
Test status
Simulation time 156689183 ps
CPU time 4.06 seconds
Started Nov 22 01:51:33 PM PST 23
Finished Nov 22 01:51:40 PM PST 23
Peak memory 238552 kb
Host smart-6d716f51-5447-4c5f-b065-5ed1538dc06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57155085739749820455361144121390334138049701341112966894452676898953125778164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 72.otp_ctrl_init_fail.57155085739749820455361144121390334138049701341112966894452676898953125778164
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.98814828604048973259969624467065788237417406246796760140605853636858016158503
Short name T405
Test name
Test status
Simulation time 176929183 ps
CPU time 4.25 seconds
Started Nov 22 01:51:26 PM PST 23
Finished Nov 22 01:51:33 PM PST 23
Peak memory 238608 kb
Host smart-110b5288-7ee4-48dd-8e26-eb8441f67c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98814828604048973259969624467065788237417406246796760140605853636858016158503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.98814828604048973259969624467065788237417406246796760140605853636858016158503
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.13545781212687795874882255957314112426691049991911320839287646880268354178413
Short name T908
Test name
Test status
Simulation time 150268849183 ps
CPU time 2001.63 seconds
Started Nov 22 01:51:44 PM PST 23
Finished Nov 22 02:25:10 PM PST 23
Peak memory 517496 kb
Host smart-512781f5-0a01-4cfe-9a27-a31161273d02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354578121268779587488
2255957314112426691049991911320839287646880268354178413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_res
et.13545781212687795874882255957314112426691049991911320839287646880268354178413
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.49823139111388239790224210151653417485435681871124800274883554892147712155095
Short name T263
Test name
Test status
Simulation time 156689183 ps
CPU time 4.05 seconds
Started Nov 22 01:51:50 PM PST 23
Finished Nov 22 01:51:56 PM PST 23
Peak memory 238552 kb
Host smart-eab46c8f-7487-4681-8b26-04eb1ff0b612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49823139111388239790224210151653417485435681871124800274883554892147712155095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 73.otp_ctrl_init_fail.49823139111388239790224210151653417485435681871124800274883554892147712155095
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.89026305521015841243446856981941268027924392146121101220882254606176608190913
Short name T708
Test name
Test status
Simulation time 176929183 ps
CPU time 4.28 seconds
Started Nov 22 01:51:51 PM PST 23
Finished Nov 22 01:51:56 PM PST 23
Peak memory 238632 kb
Host smart-acd347b3-fe5b-48a8-a51d-a13a6e4c2511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89026305521015841243446856981941268027924392146121101220882254606176608190913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.89026305521015841243446856981941268027924392146121101220882254606176608190913
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.8504035282032522570207795540511195384266142774826680167548969365210671260789
Short name T1237
Test name
Test status
Simulation time 150268849183 ps
CPU time 1926.82 seconds
Started Nov 22 01:51:49 PM PST 23
Finished Nov 22 02:23:58 PM PST 23
Peak memory 517564 kb
Host smart-467c1587-0ef3-42af-9833-c1bb7869f007
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8504035282032522570207
795540511195384266142774826680167548969365210671260789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_rese
t.8504035282032522570207795540511195384266142774826680167548969365210671260789
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.101689220309667622039900664566920495904735559148341694190933323048608521467771
Short name T32
Test name
Test status
Simulation time 156689183 ps
CPU time 4.03 seconds
Started Nov 22 01:51:14 PM PST 23
Finished Nov 22 01:51:20 PM PST 23
Peak memory 238656 kb
Host smart-3d53cb69-3ab6-4b40-85b0-bbebc88b7dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101689220309667622039900664566920495904735559148341694190933323048608521467771 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 74.otp_ctrl_init_fail.101689220309667622039900664566920495904735559148341694190933323048608521467771
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.10039997622270623880405894348380073632154133943980561960567910559900805852145
Short name T1274
Test name
Test status
Simulation time 176929183 ps
CPU time 4.44 seconds
Started Nov 22 01:51:33 PM PST 23
Finished Nov 22 01:51:41 PM PST 23
Peak memory 238632 kb
Host smart-4367515d-b434-4db6-93ab-f97e7b030df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10039997622270623880405894348380073632154133943980561960567910559900805852145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.10039997622270623880405894348380073632154133943980561960567910559900805852145
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.17230727936511205579814914797166362609280429500501631183069623373529749574802
Short name T987
Test name
Test status
Simulation time 150268849183 ps
CPU time 1952.87 seconds
Started Nov 22 01:51:39 PM PST 23
Finished Nov 22 02:24:17 PM PST 23
Peak memory 517564 kb
Host smart-5a49b201-6775-4094-9f1c-e2b5634ab953
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723072793651120557981
4914797166362609280429500501631183069623373529749574802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_res
et.17230727936511205579814914797166362609280429500501631183069623373529749574802
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.34448887859117629217604844574134763465308901261776596218658336917008364458037
Short name T887
Test name
Test status
Simulation time 156689183 ps
CPU time 3.9 seconds
Started Nov 22 01:51:18 PM PST 23
Finished Nov 22 01:51:25 PM PST 23
Peak memory 238648 kb
Host smart-456b6234-91c4-4dc6-956b-302ba45ad5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34448887859117629217604844574134763465308901261776596218658336917008364458037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 75.otp_ctrl_init_fail.34448887859117629217604844574134763465308901261776596218658336917008364458037
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.10607861360245922485067099943782532031600659339024891056677592383753296146489
Short name T65
Test name
Test status
Simulation time 176929183 ps
CPU time 4.43 seconds
Started Nov 22 01:51:34 PM PST 23
Finished Nov 22 01:51:42 PM PST 23
Peak memory 238632 kb
Host smart-c881cd92-2a6c-44dd-a6cc-7eca7f598664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10607861360245922485067099943782532031600659339024891056677592383753296146489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.10607861360245922485067099943782532031600659339024891056677592383753296146489
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.83652561000297339454023212325534429782453124281309885168777627976583200893556
Short name T1279
Test name
Test status
Simulation time 150268849183 ps
CPU time 1965.3 seconds
Started Nov 22 01:51:16 PM PST 23
Finished Nov 22 02:24:03 PM PST 23
Peak memory 517628 kb
Host smart-1dcb3c19-22d8-4793-9919-3d8b9ec637df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8365256100029733945402
3212325534429782453124281309885168777627976583200893556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_res
et.83652561000297339454023212325534429782453124281309885168777627976583200893556
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.63802415948533394673608027660002276613942106664324708309278712963927096689133
Short name T1079
Test name
Test status
Simulation time 156689183 ps
CPU time 4.02 seconds
Started Nov 22 01:51:51 PM PST 23
Finished Nov 22 01:51:56 PM PST 23
Peak memory 238576 kb
Host smart-27d898a6-6425-4b20-aac7-208ae2c4f91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63802415948533394673608027660002276613942106664324708309278712963927096689133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 76.otp_ctrl_init_fail.63802415948533394673608027660002276613942106664324708309278712963927096689133
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.24275486246088109411244423926112766249262334927082519700226088318025898583286
Short name T1298
Test name
Test status
Simulation time 176929183 ps
CPU time 4.37 seconds
Started Nov 22 01:51:48 PM PST 23
Finished Nov 22 01:51:55 PM PST 23
Peak memory 238708 kb
Host smart-35aa758b-e766-475e-a7f4-c3adb8cca74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24275486246088109411244423926112766249262334927082519700226088318025898583286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.24275486246088109411244423926112766249262334927082519700226088318025898583286
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.82903674946805400766882161356304232942748511078296118043186858870546030472359
Short name T459
Test name
Test status
Simulation time 150268849183 ps
CPU time 1941.03 seconds
Started Nov 22 01:51:55 PM PST 23
Finished Nov 22 02:24:18 PM PST 23
Peak memory 517352 kb
Host smart-cfc979c1-91cb-46c1-b640-cb82afdf2534
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8290367494680540076688
2161356304232942748511078296118043186858870546030472359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_res
et.82903674946805400766882161356304232942748511078296118043186858870546030472359
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.46546727160038615729115199709022520579243161184366824293049599249483546295716
Short name T298
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:51 PM PST 23
Peak memory 238620 kb
Host smart-8c05cf4f-feea-4364-b68b-6eb087bf7fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46546727160038615729115199709022520579243161184366824293049599249483546295716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 77.otp_ctrl_init_fail.46546727160038615729115199709022520579243161184366824293049599249483546295716
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.106284179827909442053964421825292677207318542590310127599819028908866873134512
Short name T581
Test name
Test status
Simulation time 176929183 ps
CPU time 4.25 seconds
Started Nov 22 01:51:37 PM PST 23
Finished Nov 22 01:51:45 PM PST 23
Peak memory 238668 kb
Host smart-600cd48f-91a0-42b7-86eb-9d478549f0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106284179827909442053964421825292677207318542590310127599819028908866873134512 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.106284179827909442053964421825292677207318542590310127599819028908866873134512
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.85522429271492596810959752515723574511874542164360496077483514061022254305946
Short name T637
Test name
Test status
Simulation time 150268849183 ps
CPU time 1932.07 seconds
Started Nov 22 01:51:51 PM PST 23
Finished Nov 22 02:24:05 PM PST 23
Peak memory 517472 kb
Host smart-4ff726cd-222a-4d56-a9e1-b8d6b263b021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8552242927149259681095
9752515723574511874542164360496077483514061022254305946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_res
et.85522429271492596810959752515723574511874542164360496077483514061022254305946
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.11505129459785057004330361931276590772536861676293964494088867429021103402542
Short name T381
Test name
Test status
Simulation time 156689183 ps
CPU time 3.89 seconds
Started Nov 22 01:51:55 PM PST 23
Finished Nov 22 01:52:01 PM PST 23
Peak memory 238404 kb
Host smart-a9a86794-94c2-48d9-9538-2700cdcd6491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11505129459785057004330361931276590772536861676293964494088867429021103402542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 78.otp_ctrl_init_fail.11505129459785057004330361931276590772536861676293964494088867429021103402542
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.79126958917084584267013789630728393398891787684989092244945615159540073528548
Short name T1245
Test name
Test status
Simulation time 176929183 ps
CPU time 4.27 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:52 PM PST 23
Peak memory 238708 kb
Host smart-08d5c76c-74f1-42b1-aaeb-fda71db2ab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79126958917084584267013789630728393398891787684989092244945615159540073528548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.79126958917084584267013789630728393398891787684989092244945615159540073528548
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.11277980315803648832669527863197410613385876810294620070269503064553451404995
Short name T929
Test name
Test status
Simulation time 150268849183 ps
CPU time 1958.77 seconds
Started Nov 22 01:51:52 PM PST 23
Finished Nov 22 02:24:34 PM PST 23
Peak memory 517412 kb
Host smart-eac93f13-0a86-4406-bdc1-2e7459721ed5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127798031580364883266
9527863197410613385876810294620070269503064553451404995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_res
et.11277980315803648832669527863197410613385876810294620070269503064553451404995
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.59375888813802808412344316723506876146530517903186738191115272852052356844380
Short name T998
Test name
Test status
Simulation time 156689183 ps
CPU time 4.27 seconds
Started Nov 22 01:51:24 PM PST 23
Finished Nov 22 01:51:31 PM PST 23
Peak memory 238628 kb
Host smart-5c736c33-cf4e-4188-b91e-cf3c3da98c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59375888813802808412344316723506876146530517903186738191115272852052356844380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 79.otp_ctrl_init_fail.59375888813802808412344316723506876146530517903186738191115272852052356844380
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.16980956655683041375776832044175657323118983357726293533461717959061191599529
Short name T411
Test name
Test status
Simulation time 176929183 ps
CPU time 4.41 seconds
Started Nov 22 01:51:20 PM PST 23
Finished Nov 22 01:51:27 PM PST 23
Peak memory 238660 kb
Host smart-74663356-e7b1-4c0b-818a-6fd026e645aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16980956655683041375776832044175657323118983357726293533461717959061191599529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.16980956655683041375776832044175657323118983357726293533461717959061191599529
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.91321920108414140642523923246994609216388970183814133385152704905249563863390
Short name T871
Test name
Test status
Simulation time 150268849183 ps
CPU time 1908.48 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 02:23:36 PM PST 23
Peak memory 517564 kb
Host smart-edaf72cc-a1e3-405a-8341-8f2480d9f711
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9132192010841414064252
3923246994609216388970183814133385152704905249563863390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_res
et.91321920108414140642523923246994609216388970183814133385152704905249563863390
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.8339495917622903877314655963657455585907396771785042867365012151816681066078
Short name T91
Test name
Test status
Simulation time 71069183 ps
CPU time 1.85 seconds
Started Nov 22 01:50:29 PM PST 23
Finished Nov 22 01:50:32 PM PST 23
Peak memory 238408 kb
Host smart-d9a4ab9c-08f9-43de-88d9-08317984e2e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8339495917622903877314655963657455585907396771785042867365012151816681066078 -assert nopostpro
c +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.8339495917622903877314655963657455585907396771785042867365012151816681066078
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.100983469383282636141934684934058791536286255430496097776786501748295175856151
Short name T510
Test name
Test status
Simulation time 190889183 ps
CPU time 4.74 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:09 PM PST 23
Peak memory 238784 kb
Host smart-255ba7d1-76bd-45cd-b472-6c5b2beb1cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100983469383282636141934684934058791536286255430496097776786501748295175856151 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.otp_ctrl_background_chks.100983469383282636141934684934058791536286255430496097776786501748295175856151
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.74937030240811985675659431792918843057001256561633417020947643673394757173562
Short name T97
Test name
Test status
Simulation time 111269183 ps
CPU time 2.72 seconds
Started Nov 22 01:50:16 PM PST 23
Finished Nov 22 01:50:24 PM PST 23
Peak memory 246788 kb
Host smart-5bacc497-ce4c-4f5b-9056-c761f8a950b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74937030240811985675659431792918843057001256561633417020947643673394757173562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.otp_ctrl_check_fail.74937030240811985675659431792918843057001256561633417020947643673394757173562
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.113290406055633977094415557901975236541435808784320356179125217445708785198399
Short name T236
Test name
Test status
Simulation time 390019183 ps
CPU time 10.62 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 01:50:19 PM PST 23
Peak memory 238704 kb
Host smart-9c656fde-bb89-4c6c-abb9-39cb915d2653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113290406055633977094415557901975236541435808784320356179125217445708785198399 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.otp_ctrl_dai_errs.113290406055633977094415557901975236541435808784320356179125217445708785198399
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.61342976064294195972203788695350042474349743933748433563507429888014259801376
Short name T841
Test name
Test status
Simulation time 614979183 ps
CPU time 10.6 seconds
Started Nov 22 01:50:24 PM PST 23
Finished Nov 22 01:50:36 PM PST 23
Peak memory 238784 kb
Host smart-58897aa8-2be3-4a73-84ff-c74be2765d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61342976064294195972203788695350042474349743933748433563507429888014259801376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.otp_ctrl_dai_lock.61342976064294195972203788695350042474349743933748433563507429888014259801376
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.56631758508116948076914588350891755362402442417512846757419567903566215938687
Short name T1164
Test name
Test status
Simulation time 156689183 ps
CPU time 3.97 seconds
Started Nov 22 01:50:51 PM PST 23
Finished Nov 22 01:50:55 PM PST 23
Peak memory 238608 kb
Host smart-e38c9acf-d70d-46fa-bbba-0feed2350958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56631758508116948076914588350891755362402442417512846757419567903566215938687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.otp_ctrl_init_fail.56631758508116948076914588350891755362402442417512846757419567903566215938687
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.107793590947767754990742056854305112383761548462122996529757712412008427416509
Short name T1025
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.66 seconds
Started Nov 22 01:50:14 PM PST 23
Finished Nov 22 01:50:38 PM PST 23
Peak memory 239028 kb
Host smart-5e97b20a-e3ed-4d80-8348-3a507e66e703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107793590947767754990742056854305112383761548462122996529757712412008427416509 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.otp_ctrl_macro_errs.107793590947767754990742056854305112383761548462122996529757712412008427416509
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.20291683363249046810197142579250847563895186753809067339581823204383135329376
Short name T693
Test name
Test status
Simulation time 346349183 ps
CPU time 7.51 seconds
Started Nov 22 01:50:14 PM PST 23
Finished Nov 22 01:50:26 PM PST 23
Peak memory 238744 kb
Host smart-288bfd4f-d5ed-4d24-a588-2d05364ca310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20291683363249046810197142579250847563895186753809067339581823204383135329376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.otp_ctrl_parallel_key_req.20291683363249046810197142579250847563895186753809067339581823204383135329376
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.96829822097752429581930057535096701201880580704681437270074836894088348006468
Short name T1046
Test name
Test status
Simulation time 176929183 ps
CPU time 4.3 seconds
Started Nov 22 01:50:32 PM PST 23
Finished Nov 22 01:50:37 PM PST 23
Peak memory 238704 kb
Host smart-d5a466cb-ecdf-4767-b763-6b59a826831d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96829822097752429581930057535096701201880580704681437270074836894088348006468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.96829822097752429581930057535096701201880580704681437270074836894088348006468
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.31702481716138029998021977355996371845097182952079181657923267337389738850851
Short name T893
Test name
Test status
Simulation time 486419183 ps
CPU time 11.82 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:26 PM PST 23
Peak memory 238772 kb
Host smart-17ee4bea-800b-4fef-9077-7dc566f78e32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31702481716138029998021977355996371845097182952079181657923267337389738850851 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.31702481716138029998021977355996371845097182952079181657923267337389738850851
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.31957374220803696946531917989768500456875154824853886074070022506792564491081
Short name T306
Test name
Test status
Simulation time 137469183 ps
CPU time 3.69 seconds
Started Nov 22 01:50:16 PM PST 23
Finished Nov 22 01:50:26 PM PST 23
Peak memory 238712 kb
Host smart-cef958cd-d2b7-4802-83b6-81b7a0685d16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31957374220803696946531917989768500456875154824853886074070022506792564491081 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_regwen.31957374220803696946531917989768500456875154824853886074070022506792564491081
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.65630691868852930468510801790315400564909854388481190744253675376270953184769
Short name T956
Test name
Test status
Simulation time 138839183 ps
CPU time 3.07 seconds
Started Nov 22 01:50:11 PM PST 23
Finished Nov 22 01:50:21 PM PST 23
Peak memory 238744 kb
Host smart-240d6692-2632-445e-abdb-b4abb5fd3a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65630691868852930468510801790315400564909854388481190744253675376270953184769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.otp_ctrl_smoke.65630691868852930468510801790315400564909854388481190744253675376270953184769
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.63793474693067934716531312931175642865808980082309212597259371454931125682311
Short name T748
Test name
Test status
Simulation time 13240088340 ps
CPU time 133.17 seconds
Started Nov 22 01:50:21 PM PST 23
Finished Nov 22 01:52:36 PM PST 23
Peak memory 241816 kb
Host smart-71886b3a-2cc4-417c-9b70-a50e5c33f80f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63793474693067934716531312931175642865808980082309212597259371454931125682311 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.63793474693067934716531312931175642865808980082309212597259371454931125682311
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.49291492339983829162709950914602071002012829004063684932610371400493102482032
Short name T1282
Test name
Test status
Simulation time 150268849183 ps
CPU time 1945.36 seconds
Started Nov 22 01:50:48 PM PST 23
Finished Nov 22 02:23:14 PM PST 23
Peak memory 517600 kb
Host smart-f9c76607-a584-4c21-960d-e123ebf33d8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4929149233998382916270
9950914602071002012829004063684932610371400493102482032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_rese
t.49291492339983829162709950914602071002012829004063684932610371400493102482032
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.64774686003722015064414495909921398787840287298832272512028586614068889648755
Short name T716
Test name
Test status
Simulation time 549639183 ps
CPU time 9.09 seconds
Started Nov 22 01:50:17 PM PST 23
Finished Nov 22 01:50:31 PM PST 23
Peak memory 246936 kb
Host smart-5467783e-7103-4f8d-8d5f-542517a993e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64774686003722015064414495909921398787840287298832272512028586614068889648755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.otp_ctrl_test_access.64774686003722015064414495909921398787840287298832272512028586614068889648755
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.6348321769625566357939847019415043166470571281717326491097569170222111955392
Short name T1128
Test name
Test status
Simulation time 156689183 ps
CPU time 3.99 seconds
Started Nov 22 01:51:23 PM PST 23
Finished Nov 22 01:51:29 PM PST 23
Peak memory 238648 kb
Host smart-acbd3a1e-9f02-4bdb-aa9c-860a90ed9dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6348321769625566357939847019415043166470571281717326491097569170222111955392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 80.otp_ctrl_init_fail.6348321769625566357939847019415043166470571281717326491097569170222111955392
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.7978966062597375634320989903491255453587421634477094054289852125637396498379
Short name T751
Test name
Test status
Simulation time 176929183 ps
CPU time 4.29 seconds
Started Nov 22 01:51:52 PM PST 23
Finished Nov 22 01:51:58 PM PST 23
Peak memory 238576 kb
Host smart-de20286f-6cc8-42cf-989a-fb2fc205c57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7978966062597375634320989903491255453587421634477094054289852125637396498379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.7978966062597375634320989903491255453587421634477094054289852125637396498379
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.34021484053105828552280112612841145852461394763190115269550369691694131741348
Short name T1278
Test name
Test status
Simulation time 150268849183 ps
CPU time 1922.44 seconds
Started Nov 22 01:51:56 PM PST 23
Finished Nov 22 02:24:00 PM PST 23
Peak memory 517352 kb
Host smart-1f3c74f7-2305-4e70-9cf1-c6225e802da8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402148405310582855228
0112612841145852461394763190115269550369691694131741348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_res
et.34021484053105828552280112612841145852461394763190115269550369691694131741348
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.32333913160717094399964363003693263098143472279280704535463958547342824701365
Short name T262
Test name
Test status
Simulation time 156689183 ps
CPU time 3.73 seconds
Started Nov 22 01:51:36 PM PST 23
Finished Nov 22 01:51:43 PM PST 23
Peak memory 238532 kb
Host smart-4408df9e-7b38-486b-85d7-7caf3b46a962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32333913160717094399964363003693263098143472279280704535463958547342824701365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 81.otp_ctrl_init_fail.32333913160717094399964363003693263098143472279280704535463958547342824701365
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.97583747953441446594252482815842258673215565367177691492429154226654811474200
Short name T707
Test name
Test status
Simulation time 176929183 ps
CPU time 4.19 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:52 PM PST 23
Peak memory 238648 kb
Host smart-97b2bda3-f6f3-4112-a6aa-be1c5e7245ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97583747953441446594252482815842258673215565367177691492429154226654811474200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.97583747953441446594252482815842258673215565367177691492429154226654811474200
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.38462582900905159876515558802435142461168696985082402187041313898048042407358
Short name T912
Test name
Test status
Simulation time 150268849183 ps
CPU time 1956.64 seconds
Started Nov 22 01:51:32 PM PST 23
Finished Nov 22 02:24:12 PM PST 23
Peak memory 517508 kb
Host smart-18310c73-be29-4a5b-b16a-e03451affc69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846258290090515987651
5558802435142461168696985082402187041313898048042407358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_res
et.38462582900905159876515558802435142461168696985082402187041313898048042407358
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.67585160321312628702378097436366463050172135505262374084020630554430484542172
Short name T271
Test name
Test status
Simulation time 156689183 ps
CPU time 4.19 seconds
Started Nov 22 01:51:28 PM PST 23
Finished Nov 22 01:51:34 PM PST 23
Peak memory 238600 kb
Host smart-2dd07ffb-a21e-4b08-bb01-1d649fbf99bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67585160321312628702378097436366463050172135505262374084020630554430484542172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 82.otp_ctrl_init_fail.67585160321312628702378097436366463050172135505262374084020630554430484542172
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.11486569403729754925222101556433557114995801489259232271043871818531296243420
Short name T762
Test name
Test status
Simulation time 176929183 ps
CPU time 4.26 seconds
Started Nov 22 01:51:18 PM PST 23
Finished Nov 22 01:51:25 PM PST 23
Peak memory 238788 kb
Host smart-ffad2594-2513-4292-8a52-43ab7cf62f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11486569403729754925222101556433557114995801489259232271043871818531296243420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.11486569403729754925222101556433557114995801489259232271043871818531296243420
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.112306329201564996341638777799642784329025713428376505708080795180174637822674
Short name T24
Test name
Test status
Simulation time 150268849183 ps
CPU time 1976.64 seconds
Started Nov 22 01:51:51 PM PST 23
Finished Nov 22 02:24:49 PM PST 23
Peak memory 517508 kb
Host smart-a4dab3ec-d842-4876-b90f-25b4eefea4f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123063292015649963416
38777799642784329025713428376505708080795180174637822674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_re
set.112306329201564996341638777799642784329025713428376505708080795180174637822674
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.41488349104875422264331518340673941894472097974295565630433874453695901434457
Short name T1182
Test name
Test status
Simulation time 156689183 ps
CPU time 3.92 seconds
Started Nov 22 01:51:48 PM PST 23
Finished Nov 22 01:51:55 PM PST 23
Peak memory 238652 kb
Host smart-bfed7f02-1333-41eb-91e6-50b757cfa0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41488349104875422264331518340673941894472097974295565630433874453695901434457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 83.otp_ctrl_init_fail.41488349104875422264331518340673941894472097974295565630433874453695901434457
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.35270524544748589420235597248634307724679749130715878863886495484225364643924
Short name T251
Test name
Test status
Simulation time 176929183 ps
CPU time 4.41 seconds
Started Nov 22 01:51:40 PM PST 23
Finished Nov 22 01:51:54 PM PST 23
Peak memory 238696 kb
Host smart-6da40918-f918-4a43-9e48-c1e3a154af1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35270524544748589420235597248634307724679749130715878863886495484225364643924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.35270524544748589420235597248634307724679749130715878863886495484225364643924
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.18193173681250257674426752946608802313570673620783633098594965300559285636913
Short name T229
Test name
Test status
Simulation time 150268849183 ps
CPU time 1926.1 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 02:23:54 PM PST 23
Peak memory 517596 kb
Host smart-1cac27c8-f69a-4bd7-8b07-1cd814228b74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819317368125025767442
6752946608802313570673620783633098594965300559285636913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_res
et.18193173681250257674426752946608802313570673620783633098594965300559285636913
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.44632648616108820958648337827169990926710302983959224982896438086888031372998
Short name T694
Test name
Test status
Simulation time 156689183 ps
CPU time 4.18 seconds
Started Nov 22 01:51:31 PM PST 23
Finished Nov 22 01:51:38 PM PST 23
Peak memory 238564 kb
Host smart-9912579b-7b8a-4334-af38-05d0cd1eb282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44632648616108820958648337827169990926710302983959224982896438086888031372998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 84.otp_ctrl_init_fail.44632648616108820958648337827169990926710302983959224982896438086888031372998
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.108808860364882588320965659399394507341694974054228339261434943052915300861390
Short name T1050
Test name
Test status
Simulation time 176929183 ps
CPU time 4.4 seconds
Started Nov 22 01:51:50 PM PST 23
Finished Nov 22 01:51:56 PM PST 23
Peak memory 238704 kb
Host smart-215d95bc-48fc-48ae-baab-62ebcbd281c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108808860364882588320965659399394507341694974054228339261434943052915300861390 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.108808860364882588320965659399394507341694974054228339261434943052915300861390
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.381526070182732577343199928167092723228156815624618201826516185970575874745
Short name T1124
Test name
Test status
Simulation time 150268849183 ps
CPU time 1895.96 seconds
Started Nov 22 01:51:51 PM PST 23
Finished Nov 22 02:23:29 PM PST 23
Peak memory 517444 kb
Host smart-7335b8a5-25ce-4d2b-bfc7-0c51e7d2c9fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815260701827325773431
99928167092723228156815624618201826516185970575874745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset
.381526070182732577343199928167092723228156815624618201826516185970575874745
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.81520489324610493285009165781577480086172688898238448791281357250621610014540
Short name T658
Test name
Test status
Simulation time 156689183 ps
CPU time 3.85 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:51 PM PST 23
Peak memory 238620 kb
Host smart-9bc42998-3d91-4ce0-b31c-553ceea6d215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81520489324610493285009165781577480086172688898238448791281357250621610014540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 85.otp_ctrl_init_fail.81520489324610493285009165781577480086172688898238448791281357250621610014540
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.111389410519592464824538654421366321399353274924930896703183947565047130315453
Short name T1101
Test name
Test status
Simulation time 176929183 ps
CPU time 4.31 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:52 PM PST 23
Peak memory 238588 kb
Host smart-81eacbb9-4258-4985-ac5f-55bdf6bfa35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111389410519592464824538654421366321399353274924930896703183947565047130315453 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.111389410519592464824538654421366321399353274924930896703183947565047130315453
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.97363547632939828105104041100250859028460606744421162420261645111576234923779
Short name T561
Test name
Test status
Simulation time 150268849183 ps
CPU time 1916.48 seconds
Started Nov 22 01:51:24 PM PST 23
Finished Nov 22 02:23:24 PM PST 23
Peak memory 517624 kb
Host smart-057f856b-ec40-4e8a-adb7-429533f68718
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9736354763293982810510
4041100250859028460606744421162420261645111576234923779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_res
et.97363547632939828105104041100250859028460606744421162420261645111576234923779
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.62022243161546071607776337033940310755619128298466047828460978973413783225884
Short name T253
Test name
Test status
Simulation time 156689183 ps
CPU time 3.95 seconds
Started Nov 22 01:51:51 PM PST 23
Finished Nov 22 01:51:57 PM PST 23
Peak memory 238492 kb
Host smart-41489be8-ab6e-413f-a821-f8ee1359bf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62022243161546071607776337033940310755619128298466047828460978973413783225884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 86.otp_ctrl_init_fail.62022243161546071607776337033940310755619128298466047828460978973413783225884
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.97958143085552795748372363626804129358281294113739459499819295681254787666908
Short name T1211
Test name
Test status
Simulation time 176929183 ps
CPU time 4.3 seconds
Started Nov 22 01:51:19 PM PST 23
Finished Nov 22 01:51:26 PM PST 23
Peak memory 238636 kb
Host smart-38852e00-86be-4b8d-b0a3-035b2b4ecf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97958143085552795748372363626804129358281294113739459499819295681254787666908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.97958143085552795748372363626804129358281294113739459499819295681254787666908
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.51944843666022780152799243028812979578195929497912869891626429283791290202589
Short name T867
Test name
Test status
Simulation time 150268849183 ps
CPU time 2006.13 seconds
Started Nov 22 01:51:51 PM PST 23
Finished Nov 22 02:25:18 PM PST 23
Peak memory 517588 kb
Host smart-571628ca-a137-4cc6-ab4e-32975bf07ea0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5194484366602278015279
9243028812979578195929497912869891626429283791290202589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_res
et.51944843666022780152799243028812979578195929497912869891626429283791290202589
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.95783671040549324000284213865292246078430704940213432670184480261542351922965
Short name T549
Test name
Test status
Simulation time 156689183 ps
CPU time 4.03 seconds
Started Nov 22 01:52:04 PM PST 23
Finished Nov 22 01:52:11 PM PST 23
Peak memory 238592 kb
Host smart-1ef947e6-2140-40db-83ab-b3a067c3ecb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95783671040549324000284213865292246078430704940213432670184480261542351922965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 87.otp_ctrl_init_fail.95783671040549324000284213865292246078430704940213432670184480261542351922965
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.9229439142950836172260643938422539642383896431796505058739504246127367038568
Short name T1284
Test name
Test status
Simulation time 176929183 ps
CPU time 4.24 seconds
Started Nov 22 01:51:38 PM PST 23
Finished Nov 22 01:51:47 PM PST 23
Peak memory 238588 kb
Host smart-d22d1ba2-afb5-4b14-9f9a-48b1c6cb6c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9229439142950836172260643938422539642383896431796505058739504246127367038568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.9229439142950836172260643938422539642383896431796505058739504246127367038568
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.46513085241349105985794678050257077679194208901698928837776780469144588085427
Short name T811
Test name
Test status
Simulation time 150268849183 ps
CPU time 1911.52 seconds
Started Nov 22 01:51:28 PM PST 23
Finished Nov 22 02:23:22 PM PST 23
Peak memory 517412 kb
Host smart-4fc9f9c4-f93c-4aaf-9283-e68a983093b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4651308524134910598579
4678050257077679194208901698928837776780469144588085427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_res
et.46513085241349105985794678050257077679194208901698928837776780469144588085427
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.39544852121169612221614343688985137336651515680103542111666562840106864755160
Short name T644
Test name
Test status
Simulation time 156689183 ps
CPU time 3.92 seconds
Started Nov 22 01:51:40 PM PST 23
Finished Nov 22 01:51:49 PM PST 23
Peak memory 238628 kb
Host smart-10856961-1f08-4609-97de-e66d5238a2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39544852121169612221614343688985137336651515680103542111666562840106864755160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 88.otp_ctrl_init_fail.39544852121169612221614343688985137336651515680103542111666562840106864755160
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.76896507571999006298623838842420795691251709898736372900910517064962383521109
Short name T862
Test name
Test status
Simulation time 176929183 ps
CPU time 4.34 seconds
Started Nov 22 01:51:46 PM PST 23
Finished Nov 22 01:51:54 PM PST 23
Peak memory 238648 kb
Host smart-f9fcca24-e188-4275-9f17-65fa4cea0052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76896507571999006298623838842420795691251709898736372900910517064962383521109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.76896507571999006298623838842420795691251709898736372900910517064962383521109
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.69060675994033818177446196694953481939484210390061763277370241471212797077682
Short name T1038
Test name
Test status
Simulation time 150268849183 ps
CPU time 1935.53 seconds
Started Nov 22 01:51:32 PM PST 23
Finished Nov 22 02:23:50 PM PST 23
Peak memory 517628 kb
Host smart-d5d4af62-0abe-429c-8a64-e74b9ee1120a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6906067599403381817744
6196694953481939484210390061763277370241471212797077682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_res
et.69060675994033818177446196694953481939484210390061763277370241471212797077682
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.30045938876644389276855291813653427158867223020039710094105321953842919658820
Short name T960
Test name
Test status
Simulation time 156689183 ps
CPU time 3.87 seconds
Started Nov 22 01:51:34 PM PST 23
Finished Nov 22 01:51:41 PM PST 23
Peak memory 238404 kb
Host smart-6b1d9e89-f14c-4d08-a86c-4acd26ec6fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30045938876644389276855291813653427158867223020039710094105321953842919658820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 89.otp_ctrl_init_fail.30045938876644389276855291813653427158867223020039710094105321953842919658820
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.88689281172112244938821200184488034899158784193489675429927068091008748073192
Short name T356
Test name
Test status
Simulation time 176929183 ps
CPU time 4.2 seconds
Started Nov 22 01:51:35 PM PST 23
Finished Nov 22 01:51:43 PM PST 23
Peak memory 238464 kb
Host smart-28cd4118-e8bc-4ccb-bd1c-bcec4bae8a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88689281172112244938821200184488034899158784193489675429927068091008748073192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.88689281172112244938821200184488034899158784193489675429927068091008748073192
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.331260414662326207253987291166458817349433659659444266399312816536317154509
Short name T945
Test name
Test status
Simulation time 150268849183 ps
CPU time 1919.7 seconds
Started Nov 22 01:51:34 PM PST 23
Finished Nov 22 02:23:38 PM PST 23
Peak memory 517408 kb
Host smart-c6211845-72bd-4b60-85e2-674024056579
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312604146623262072539
87291166458817349433659659444266399312816536317154509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset
.331260414662326207253987291166458817349433659659444266399312816536317154509
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.49575918611487235129756384161767640869513942062854131860898344845013427305184
Short name T563
Test name
Test status
Simulation time 71069183 ps
CPU time 1.92 seconds
Started Nov 22 01:50:24 PM PST 23
Finished Nov 22 01:50:28 PM PST 23
Peak memory 238428 kb
Host smart-433ea671-bb66-49d0-a98a-7ec8d92229fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49575918611487235129756384161767640869513942062854131860898344845013427305184 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.49575918611487235129756384161767640869513942062854131860898344845013427305184
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.97492136185419089321859921593353945860314504421915608424659048149725735546111
Short name T89
Test name
Test status
Simulation time 190889183 ps
CPU time 4.77 seconds
Started Nov 22 01:50:17 PM PST 23
Finished Nov 22 01:50:27 PM PST 23
Peak memory 238812 kb
Host smart-a8bad8a0-c8a8-42b7-8a9d-8256812925b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97492136185419089321859921593353945860314504421915608424659048149725735546111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 9.otp_ctrl_background_chks.97492136185419089321859921593353945860314504421915608424659048149725735546111
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.109817630567786767633376322385604473226046221615273118485531713750270495888769
Short name T1031
Test name
Test status
Simulation time 111269183 ps
CPU time 2.66 seconds
Started Nov 22 01:50:28 PM PST 23
Finished Nov 22 01:50:32 PM PST 23
Peak memory 246720 kb
Host smart-1af0c6df-4d8c-43e3-b7cc-3f5a6d5fa9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109817630567786767633376322385604473226046221615273118485531713750270495888769 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.otp_ctrl_check_fail.109817630567786767633376322385604473226046221615273118485531713750270495888769
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.42868691231890316854324586679390117097447535392293069669895166212496055875129
Short name T1158
Test name
Test status
Simulation time 390019183 ps
CPU time 11.11 seconds
Started Nov 22 01:50:10 PM PST 23
Finished Nov 22 01:50:29 PM PST 23
Peak memory 238536 kb
Host smart-2ce1f40b-37e2-4633-8301-05dccd618d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42868691231890316854324586679390117097447535392293069669895166212496055875129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.otp_ctrl_dai_errs.42868691231890316854324586679390117097447535392293069669895166212496055875129
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.35236257381637337717845969218275399812898805655357116682294286402753273143883
Short name T1119
Test name
Test status
Simulation time 614979183 ps
CPU time 10.58 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 01:50:19 PM PST 23
Peak memory 238844 kb
Host smart-f6d8eec9-9abf-425c-a90e-cd2103652b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35236257381637337717845969218275399812898805655357116682294286402753273143883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.otp_ctrl_dai_lock.35236257381637337717845969218275399812898805655357116682294286402753273143883
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.95943299883469312190601382381617222330307206962690288666912323290656362913255
Short name T552
Test name
Test status
Simulation time 156689183 ps
CPU time 3.84 seconds
Started Nov 22 01:50:10 PM PST 23
Finished Nov 22 01:50:22 PM PST 23
Peak memory 238624 kb
Host smart-9509c0f8-ba99-46b3-ac82-d3d2297b8d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95943299883469312190601382381617222330307206962690288666912323290656362913255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.otp_ctrl_init_fail.95943299883469312190601382381617222330307206962690288666912323290656362913255
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.58934819940357190134842358309560403509332295516196071448317145056565960502062
Short name T955
Test name
Test status
Simulation time 1137629183 ps
CPU time 19.73 seconds
Started Nov 22 01:50:17 PM PST 23
Finished Nov 22 01:50:42 PM PST 23
Peak memory 239032 kb
Host smart-c2194519-2c70-407c-bff7-b5e1c96ad1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58934819940357190134842358309560403509332295516196071448317145056565960502062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.otp_ctrl_macro_errs.58934819940357190134842358309560403509332295516196071448317145056565960502062
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.115310827458413792652397679498438637276120368316681891692424562823942704422827
Short name T36
Test name
Test status
Simulation time 346349183 ps
CPU time 8.11 seconds
Started Nov 22 01:50:19 PM PST 23
Finished Nov 22 01:50:31 PM PST 23
Peak memory 238736 kb
Host smart-e1ba7d6b-1d8e-4a03-ae5f-8966e89471b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115310827458413792652397679498438637276120368316681891692424562823942704422827 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.115310827458413792652397679498438637276120368316681891692424562823942704422827
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.53516790547845234980289937033648982293632577393052299181343042866225968867437
Short name T724
Test name
Test status
Simulation time 176929183 ps
CPU time 4.6 seconds
Started Nov 22 01:50:29 PM PST 23
Finished Nov 22 01:50:34 PM PST 23
Peak memory 238088 kb
Host smart-20ab8c35-c9f0-4732-8f00-f77d2d750978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53516790547845234980289937033648982293632577393052299181343042866225968867437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.53516790547845234980289937033648982293632577393052299181343042866225968867437
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.51024555181770696470253260491040649916568343008466311893880378028423206121489
Short name T813
Test name
Test status
Simulation time 486419183 ps
CPU time 12.09 seconds
Started Nov 22 01:50:14 PM PST 23
Finished Nov 22 01:50:30 PM PST 23
Peak memory 238708 kb
Host smart-e3fe19a6-c9be-4167-9b47-724025cdaa2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51024555181770696470253260491040649916568343008466311893880378028423206121489 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.51024555181770696470253260491040649916568343008466311893880378028423206121489
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.109158725637230104003036869617657341384560579422717926048420492531449266724827
Short name T31
Test name
Test status
Simulation time 137469183 ps
CPU time 3.73 seconds
Started Nov 22 01:50:49 PM PST 23
Finished Nov 22 01:50:54 PM PST 23
Peak memory 238804 kb
Host smart-7a1d1e62-01f5-4ef8-8f18-eb4a78494359
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=109158725637230104003036869617657341384560579422717926048420492531449266724827 -assert nopostproc +UVM_TE
STNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_regwen.109158725637230104003036869617657341384560579422717926048420492531449266724827
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.51294901313468804627782233641629739620597126930369757738946196607274871458264
Short name T870
Test name
Test status
Simulation time 138839183 ps
CPU time 3.12 seconds
Started Nov 22 01:50:25 PM PST 23
Finished Nov 22 01:50:29 PM PST 23
Peak memory 238816 kb
Host smart-2d643ec7-a450-4516-835a-936aacd92f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51294901313468804627782233641629739620597126930369757738946196607274871458264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.otp_ctrl_smoke.51294901313468804627782233641629739620597126930369757738946196607274871458264
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.40282194718133671574411894368949270751919980156093608862836103965213763784355
Short name T1068
Test name
Test status
Simulation time 13240088340 ps
CPU time 129.95 seconds
Started Nov 22 01:50:17 PM PST 23
Finished Nov 22 01:52:32 PM PST 23
Peak memory 241784 kb
Host smart-712cdc39-14fe-465a-9eb1-a0d2d0619376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40282194718133671574411894368949270751919980156093608862836103965213763784355 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.40282194718133671574411894368949270751919980156093608862836103965213763784355
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.95841496864556376461039779443202596446179134118628125968713779038557431088831
Short name T639
Test name
Test status
Simulation time 150268849183 ps
CPU time 1972.54 seconds
Started Nov 22 01:50:32 PM PST 23
Finished Nov 22 02:23:26 PM PST 23
Peak memory 517568 kb
Host smart-c06df0c9-10ca-4a10-96df-9066fb54355a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9584149686455637646103
9779443202596446179134118628125968713779038557431088831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_rese
t.95841496864556376461039779443202596446179134118628125968713779038557431088831
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.945921188548002122824349641263134923111216055045571379352091632132680774259
Short name T1117
Test name
Test status
Simulation time 549639183 ps
CPU time 9.27 seconds
Started Nov 22 01:50:11 PM PST 23
Finished Nov 22 01:50:27 PM PST 23
Peak memory 246872 kb
Host smart-27d4a759-c4b1-4d77-bfaf-1f3578d79ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945921188548002122824349641263134923111216055045571379352091632132680774259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_ba
se_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.otp_ctrl_test_access.945921188548002122824349641263134923111216055045571379352091632132680774259
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.54202837298352337669233579539939856197807473844270816767460850073561422303301
Short name T631
Test name
Test status
Simulation time 156689183 ps
CPU time 4.05 seconds
Started Nov 22 01:51:54 PM PST 23
Finished Nov 22 01:52:00 PM PST 23
Peak memory 238520 kb
Host smart-ba9a39c7-99d1-4f98-9c43-061f254f8b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54202837298352337669233579539939856197807473844270816767460850073561422303301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 90.otp_ctrl_init_fail.54202837298352337669233579539939856197807473844270816767460850073561422303301
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.56792630660990926514157865029674479644437375235779289087506604058859112272710
Short name T1288
Test name
Test status
Simulation time 176929183 ps
CPU time 4.19 seconds
Started Nov 22 01:51:36 PM PST 23
Finished Nov 22 01:51:44 PM PST 23
Peak memory 238464 kb
Host smart-306db30f-40c1-49d0-9409-f2c0760155fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56792630660990926514157865029674479644437375235779289087506604058859112272710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.56792630660990926514157865029674479644437375235779289087506604058859112272710
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.69430721678294390992233452284209229423806046077025515342453571431745423458396
Short name T1244
Test name
Test status
Simulation time 150268849183 ps
CPU time 1878.14 seconds
Started Nov 22 01:51:39 PM PST 23
Finished Nov 22 02:23:02 PM PST 23
Peak memory 517484 kb
Host smart-648169b0-1886-42c4-a2e0-964490d1e2a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6943072167829439099223
3452284209229423806046077025515342453571431745423458396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_res
et.69430721678294390992233452284209229423806046077025515342453571431745423458396
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.30725056572809538915540812132523271010327765484318983357431313251123333388394
Short name T1125
Test name
Test status
Simulation time 156689183 ps
CPU time 4.07 seconds
Started Nov 22 01:51:27 PM PST 23
Finished Nov 22 01:51:34 PM PST 23
Peak memory 238528 kb
Host smart-c8079b0d-4199-4f85-bf72-dae88f4cbb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30725056572809538915540812132523271010327765484318983357431313251123333388394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 91.otp_ctrl_init_fail.30725056572809538915540812132523271010327765484318983357431313251123333388394
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.19964208571676721960705392880956148023171514722823122321964870999698741118682
Short name T1027
Test name
Test status
Simulation time 176929183 ps
CPU time 4.42 seconds
Started Nov 22 01:51:46 PM PST 23
Finished Nov 22 01:51:54 PM PST 23
Peak memory 238716 kb
Host smart-3a3647c9-02a4-46a5-b965-2133f632294f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19964208571676721960705392880956148023171514722823122321964870999698741118682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.19964208571676721960705392880956148023171514722823122321964870999698741118682
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.36613904790321544444405615647494210948941682613064338839251814855465708060186
Short name T759
Test name
Test status
Simulation time 150268849183 ps
CPU time 1944.99 seconds
Started Nov 22 01:51:56 PM PST 23
Finished Nov 22 02:24:23 PM PST 23
Peak memory 517372 kb
Host smart-00e7d24d-dc7f-4e0b-a851-782585040f6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661390479032154444440
5615647494210948941682613064338839251814855465708060186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_res
et.36613904790321544444405615647494210948941682613064338839251814855465708060186
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.7533547361305451217138557419968374454608367928721511501559803617010691687804
Short name T288
Test name
Test status
Simulation time 156689183 ps
CPU time 4.21 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:51 PM PST 23
Peak memory 238620 kb
Host smart-bc679152-41e3-40e0-b20f-751a5d9a65d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7533547361305451217138557419968374454608367928721511501559803617010691687804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 92.otp_ctrl_init_fail.7533547361305451217138557419968374454608367928721511501559803617010691687804
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.13904434945846419271999277662840780945114357128082570778329951717289897978969
Short name T1272
Test name
Test status
Simulation time 176929183 ps
CPU time 4.36 seconds
Started Nov 22 01:51:32 PM PST 23
Finished Nov 22 01:51:40 PM PST 23
Peak memory 238604 kb
Host smart-1cd0aff9-5906-41a8-8ec9-a33d443a7a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13904434945846419271999277662840780945114357128082570778329951717289897978969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.13904434945846419271999277662840780945114357128082570778329951717289897978969
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.15633188307417613361240630728307977400607203725908111997292099984188340920010
Short name T620
Test name
Test status
Simulation time 150268849183 ps
CPU time 1880.97 seconds
Started Nov 22 01:51:39 PM PST 23
Finished Nov 22 02:23:05 PM PST 23
Peak memory 517372 kb
Host smart-8837f151-3c93-406f-8506-cdf24c8d9d45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563318830741761336124
0630728307977400607203725908111997292099984188340920010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_res
et.15633188307417613361240630728307977400607203725908111997292099984188340920010
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.67815909544265577733658240927940081104441156559554090593622967460262334542269
Short name T1197
Test name
Test status
Simulation time 156689183 ps
CPU time 3.86 seconds
Started Nov 22 01:51:39 PM PST 23
Finished Nov 22 01:51:48 PM PST 23
Peak memory 238548 kb
Host smart-1eb89f5c-7217-481a-855d-505de948b585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67815909544265577733658240927940081104441156559554090593622967460262334542269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 93.otp_ctrl_init_fail.67815909544265577733658240927940081104441156559554090593622967460262334542269
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.73639351182021749879253794963762909051874619259224329780028458727813407098122
Short name T293
Test name
Test status
Simulation time 176929183 ps
CPU time 4.26 seconds
Started Nov 22 01:51:40 PM PST 23
Finished Nov 22 01:51:49 PM PST 23
Peak memory 238640 kb
Host smart-9b2a1f3d-0c7f-45d7-8dc2-799f0e1db707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73639351182021749879253794963762909051874619259224329780028458727813407098122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.73639351182021749879253794963762909051874619259224329780028458727813407098122
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.37248159798025715502467236640972987531790488649715976184165941393344391316332
Short name T527
Test name
Test status
Simulation time 150268849183 ps
CPU time 1952.24 seconds
Started Nov 22 01:51:58 PM PST 23
Finished Nov 22 02:24:31 PM PST 23
Peak memory 517528 kb
Host smart-b67d1189-497c-4790-ba19-098059df90ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724815979802571550246
7236640972987531790488649715976184165941393344391316332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_res
et.37248159798025715502467236640972987531790488649715976184165941393344391316332
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.26936073445187418557961814647139904152424996090194712478311666856957464487108
Short name T899
Test name
Test status
Simulation time 156689183 ps
CPU time 3.92 seconds
Started Nov 22 01:51:36 PM PST 23
Finished Nov 22 01:51:43 PM PST 23
Peak memory 238580 kb
Host smart-d4c29293-f823-486e-8230-43c6dcedf990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26936073445187418557961814647139904152424996090194712478311666856957464487108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 94.otp_ctrl_init_fail.26936073445187418557961814647139904152424996090194712478311666856957464487108
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.115413595844285422071774750022308325273193434329024526168737287677018850572911
Short name T441
Test name
Test status
Simulation time 176929183 ps
CPU time 4.19 seconds
Started Nov 22 01:51:49 PM PST 23
Finished Nov 22 01:51:55 PM PST 23
Peak memory 238484 kb
Host smart-3c462281-54c1-4ac1-b20e-1b869bad1335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115413595844285422071774750022308325273193434329024526168737287677018850572911 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.115413595844285422071774750022308325273193434329024526168737287677018850572911
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.61478351649361658368108002390340778250675399477287873317429929136340409879272
Short name T414
Test name
Test status
Simulation time 150268849183 ps
CPU time 1942.91 seconds
Started Nov 22 01:51:54 PM PST 23
Finished Nov 22 02:24:19 PM PST 23
Peak memory 517500 kb
Host smart-5eed9cdf-152f-4704-aba3-f60e83466834
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6147835164936165836810
8002390340778250675399477287873317429929136340409879272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_res
et.61478351649361658368108002390340778250675399477287873317429929136340409879272
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.65681118815087434616416777006498785692594067553468825620740176183865925912433
Short name T1198
Test name
Test status
Simulation time 156689183 ps
CPU time 3.88 seconds
Started Nov 22 01:51:43 PM PST 23
Finished Nov 22 01:51:55 PM PST 23
Peak memory 238548 kb
Host smart-9097ae2a-7267-4526-90b4-df11bca24690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65681118815087434616416777006498785692594067553468825620740176183865925912433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 95.otp_ctrl_init_fail.65681118815087434616416777006498785692594067553468825620740176183865925912433
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.81351358556303206124423155607960554215756409980238882514356090364389468542381
Short name T1095
Test name
Test status
Simulation time 176929183 ps
CPU time 4.19 seconds
Started Nov 22 01:51:38 PM PST 23
Finished Nov 22 01:51:48 PM PST 23
Peak memory 238484 kb
Host smart-1bc80398-6300-4b0f-b082-2d7a4fd457ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81351358556303206124423155607960554215756409980238882514356090364389468542381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.81351358556303206124423155607960554215756409980238882514356090364389468542381
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.92507016175781658264847857049688517087366643461554943008556431218680388644309
Short name T25
Test name
Test status
Simulation time 150268849183 ps
CPU time 1960.16 seconds
Started Nov 22 01:51:28 PM PST 23
Finished Nov 22 02:24:10 PM PST 23
Peak memory 517568 kb
Host smart-6208f00d-1f99-41a7-99d1-d5a3365f28f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9250701617578165826484
7857049688517087366643461554943008556431218680388644309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_res
et.92507016175781658264847857049688517087366643461554943008556431218680388644309
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.109041803575538544584232298520395550604741434507617881500607085371054358992994
Short name T626
Test name
Test status
Simulation time 156689183 ps
CPU time 3.88 seconds
Started Nov 22 01:51:41 PM PST 23
Finished Nov 22 01:51:49 PM PST 23
Peak memory 238556 kb
Host smart-4bc9e9ad-9223-4a57-9fd7-6736d7a91b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109041803575538544584232298520395550604741434507617881500607085371054358992994 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 96.otp_ctrl_init_fail.109041803575538544584232298520395550604741434507617881500607085371054358992994
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.9320913223169483657759581395124720103269868112159101992595921746162846274002
Short name T302
Test name
Test status
Simulation time 176929183 ps
CPU time 4.4 seconds
Started Nov 22 01:51:47 PM PST 23
Finished Nov 22 01:51:55 PM PST 23
Peak memory 238720 kb
Host smart-78b4942a-6a77-42d3-9fb9-1e4f215d9351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9320913223169483657759581395124720103269868112159101992595921746162846274002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.9320913223169483657759581395124720103269868112159101992595921746162846274002
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.49654204714242585278036421758570651895400655015366641577230244315601952877781
Short name T328
Test name
Test status
Simulation time 150268849183 ps
CPU time 1962.36 seconds
Started Nov 22 01:51:54 PM PST 23
Finished Nov 22 02:24:38 PM PST 23
Peak memory 517500 kb
Host smart-a32b3780-4880-49a7-9a67-728865c93fb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4965420471424258527803
6421758570651895400655015366641577230244315601952877781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_res
et.49654204714242585278036421758570651895400655015366641577230244315601952877781
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.55260760530043221512532630646900460016282388545772344450648706510106048595295
Short name T845
Test name
Test status
Simulation time 156689183 ps
CPU time 4 seconds
Started Nov 22 01:51:54 PM PST 23
Finished Nov 22 01:52:04 PM PST 23
Peak memory 238548 kb
Host smart-67107420-5523-4558-8ce8-cecf0f3223c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55260760530043221512532630646900460016282388545772344450648706510106048595295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 97.otp_ctrl_init_fail.55260760530043221512532630646900460016282388545772344450648706510106048595295
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.69327172414427327991358927887402792417007712843504938600684474283302934427246
Short name T224
Test name
Test status
Simulation time 176929183 ps
CPU time 4.53 seconds
Started Nov 22 01:51:36 PM PST 23
Finished Nov 22 01:51:44 PM PST 23
Peak memory 238676 kb
Host smart-6d2d6469-b204-4435-91be-52127053011a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69327172414427327991358927887402792417007712843504938600684474283302934427246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.69327172414427327991358927887402792417007712843504938600684474283302934427246
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.83881579413143490637253830635322061007889081238225052953733378960019347983624
Short name T1093
Test name
Test status
Simulation time 150268849183 ps
CPU time 1937.62 seconds
Started Nov 22 01:51:49 PM PST 23
Finished Nov 22 02:24:09 PM PST 23
Peak memory 517572 kb
Host smart-e353f103-569c-4cfa-bced-7e775445f471
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8388157941314349063725
3830635322061007889081238225052953733378960019347983624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_res
et.83881579413143490637253830635322061007889081238225052953733378960019347983624
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.943637552151872709134590953548416774888782140270884331825756470173842004211
Short name T294
Test name
Test status
Simulation time 156689183 ps
CPU time 3.99 seconds
Started Nov 22 01:51:34 PM PST 23
Finished Nov 22 01:51:42 PM PST 23
Peak memory 238672 kb
Host smart-1350c0d5-ae65-424e-8e15-adeb45db7c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943637552151872709134590953548416774888782140270884331825756470173842004211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_ba
se_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 98.otp_ctrl_init_fail.943637552151872709134590953548416774888782140270884331825756470173842004211
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.23012996221271636714270094937221259231266319418082819611276094666016538407542
Short name T926
Test name
Test status
Simulation time 176929183 ps
CPU time 4.37 seconds
Started Nov 22 01:51:42 PM PST 23
Finished Nov 22 01:51:51 PM PST 23
Peak memory 238640 kb
Host smart-a8ea5c2c-7e6d-4e25-92a4-e62b4d84db9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23012996221271636714270094937221259231266319418082819611276094666016538407542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.23012996221271636714270094937221259231266319418082819611276094666016538407542
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.95346984723143744452532329291158897065539969754662683913997230039943265005418
Short name T79
Test name
Test status
Simulation time 150268849183 ps
CPU time 1869.51 seconds
Started Nov 22 01:51:39 PM PST 23
Finished Nov 22 02:22:54 PM PST 23
Peak memory 517372 kb
Host smart-3db1f572-f6f2-49b4-9e9a-bf6e5b44912a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9534698472314374445253
2329291158897065539969754662683913997230039943265005418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_res
et.95346984723143744452532329291158897065539969754662683913997230039943265005418
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.112049688788579322857725892178833486950585071501721217829737037624608603275003
Short name T842
Test name
Test status
Simulation time 156689183 ps
CPU time 3.98 seconds
Started Nov 22 01:51:58 PM PST 23
Finished Nov 22 01:52:04 PM PST 23
Peak memory 238580 kb
Host smart-ed17e8bc-aaa5-4eb0-acf3-c7a258ed4fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112049688788579322857725892178833486950585071501721217829737037624608603275003 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 99.otp_ctrl_init_fail.112049688788579322857725892178833486950585071501721217829737037624608603275003
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.60945731605254272171532253205121497266534502109045110096246545853335479834880
Short name T1045
Test name
Test status
Simulation time 176929183 ps
CPU time 4.31 seconds
Started Nov 22 01:51:42 PM PST 23
Finished Nov 22 01:51:50 PM PST 23
Peak memory 238640 kb
Host smart-29eb0700-6dff-4cc6-9a57-262c9c747f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60945731605254272171532253205121497266534502109045110096246545853335479834880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.60945731605254272171532253205121497266534502109045110096246545853335479834880
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.76171059668211639839935938856396726512657434359977415891961494163251188223268
Short name T342
Test name
Test status
Simulation time 150268849183 ps
CPU time 1990.12 seconds
Started Nov 22 01:51:48 PM PST 23
Finished Nov 22 02:25:01 PM PST 23
Peak memory 517632 kb
Host smart-edf7472b-b238-408a-95ac-5f620f9fc7df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7617105966821163983993
5938856396726512657434359977415891961494163251188223268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_res
et.76171059668211639839935938856396726512657434359977415891961494163251188223268
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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