Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
lc_esc_during_flash_addr_req	2	0	2	100.00	100	1	1	2
lc_esc_during_flash_data_req	2	0	2	100.00	100	1	1	2
lc_esc_during_lc_otp_prog_req	2	0	2	100.00	100	1	1	2
lc_esc_during_otbn_req	2	0	2	100.00	100	1	1	2
lc_esc_during_otp_idle	2	0	2	100.00	100	1	1	2
lc_esc_during_sram_0_req	2	0	2	100.00	100	1	1	2
lc_esc_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable lc_esc_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

335

1

T2

2

T8

2

T9

2

auto[1]

45

1

T179

1

T185

1

T84

2

---

Summary for Variable lc_esc_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

326

1

T2

1

T8

2

T99

2

auto[1]

54

1

T2

1

T9

2

T12

1

---

Summary for Variable lc_esc_during_lc_otp_prog_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_lc_otp_prog_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

342

1

T2

2

T8

1

T9

2

auto[1]

38

1

T8

1

T99

1

T103

2

---

Summary for Variable lc_esc_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

338

1

T2

2

T8

2

T9

2

auto[1]

42

1

T184

1

T13

1

T123

1

---

Summary for Variable lc_esc_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34

1

T99

1

T103

1

T179

1

auto[1]

346

1

T2

2

T8

2

T9

2

---

Summary for Variable lc_esc_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

343

1

T2

2

T8

2

T9

2

auto[1]

37

1

T309

1

T123

1

T310

1

---

Summary for Variable lc_esc_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

345

1

T2

2

T8

2

T9

2

auto[1]

35

1

T309

1

T123

1

T310

1