Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.88	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	1	14	93.33
Crosses	51	7	44	86.27

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	8	0	8	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	51	7	44	86.27	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	55227	1			T1	91		T2	105		T8	7
access_err	77131	1			T1	26		T2	2		T4	113
write_blank_err	503	1			T12	6		T84	1		T115	1
ecc_uncorr_err	70088	1			T12	783		T84	592		T115	478
ecc_corr_err	1256	1			T52	40		T116	11		T117	11
no_err	377574	1			T1	171		T2	125		T4	217

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lc_or_oob	43592	1			T1	14		T2	4		T4	48
secret2	60041	1			T1	8		T2	2		T4	40
secret1	88872	1			T1	10		T2	216		T4	60
secret0	111255	1			T1	10		T4	22		T9	4
hw_cfg	72271	1			T1	6		T4	26		T9	136
owner_sw_cfg	63588	1			T1	16		T2	2		T4	48
creator_sw_cfg	60493	1			T1	24		T2	8		T4	46
vendor_test	81667	1			T1	200		T4	40		T9	4

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	51	7	44	86.27	7
Automatically Generated Cross Bins	51	7	44	86.27	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	7

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	lc_or_oob	3675	1			T96	115		T12	399		T123	37
fsm_err	secret2	3641	1			T13	9		T121	142		T123	223
fsm_err	secret1	7481	1			T2	105		T84	135		T121	384
fsm_err	secret0	6083	1			T97	138		T184	176		T306	574
fsm_err	hw_cfg	7776	1			T9	68		T84	329		T13	276
fsm_err	owner_sw_cfg	4422	1			T307	60		T308	285		T134	2
fsm_err	creator_sw_cfg	3424	1			T8	7		T309	257		T310	204
fsm_err	vendor_test	18725	1			T1	91		T98	44		T52	351
access_err	lc_or_oob	18117	1			T1	7		T2	2		T4	24
access_err	secret2	13174	1			T1	4		T4	14		T35	4
access_err	secret1	6538	1			T1	2		T4	19		T35	4
access_err	secret0	5058	1			T1	2		T4	8		T52	7
access_err	hw_cfg	2994	1			T4	5		T10	2		T104	1
access_err	owner_sw_cfg	11601	1			T1	2		T4	19		T10	6
access_err	creator_sw_cfg	11873	1			T1	4		T4	19		T10	4
access_err	vendor_test	7776	1			T1	5		T4	5		T10	9
write_blank_err	secret2	14	1			T118	1		T257	1		T286	1
write_blank_err	secret1	42	1			T12	1		T123	1		T311	1
write_blank_err	secret0	88	1			T12	1		T84	1		T122	1
write_blank_err	hw_cfg	26	1			T120	1		T121	2		T124	1
write_blank_err	owner_sw_cfg	120	1			T12	2		T122	1		T118	1
write_blank_err	creator_sw_cfg	178	1			T12	1		T115	1		T120	1
write_blank_err	vendor_test	35	1			T12	1		T124	3		T118	2
ecc_uncorr_err	secret2	5736	1			T118	256		T157	39		T257	268
ecc_uncorr_err	secret1	18119	1			T12	163		T123	309		T117	48
ecc_uncorr_err	secret0	32652	1			T12	620		T84	592		T122	165
ecc_uncorr_err	hw_cfg	9369	1			T120	455		T121	879		T117	173
ecc_uncorr_err	owner_sw_cfg	2036	1			T215	115		T134	13		T312	512
ecc_uncorr_err	creator_sw_cfg	2176	1			T115	478		T117	113		T134	10
ecc_corr_err	secret2	88	1			T116	1		T117	6		T42	4
ecc_corr_err	secret1	170	1			T52	2		T116	1		T117	2
ecc_corr_err	secret0	203	1			T52	15		T42	12		T31	4
ecc_corr_err	hw_cfg	298	1			T52	11		T42	15		T31	3
ecc_corr_err	owner_sw_cfg	158	1			T52	10		T116	3		T42	8
ecc_corr_err	creator_sw_cfg	153	1			T52	2		T42	1		T31	1
ecc_corr_err	vendor_test	186	1			T116	6		T117	3		T42	1
no_err	lc_or_oob	21800	1			T1	7		T2	2		T4	24
no_err	secret2	37388	1			T1	4		T2	2		T4	26
no_err	secret1	56522	1			T1	8		T2	111		T4	41
no_err	secret0	67171	1			T1	8		T4	14		T9	4
no_err	hw_cfg	51808	1			T1	6		T4	21		T9	68
no_err	owner_sw_cfg	45251	1			T1	14		T2	2		T4	29
no_err	creator_sw_cfg	42689	1			T1	20		T2	8		T4	27
no_err	vendor_test	54945	1			T1	104		T4	35		T9	4

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
lc_or_oob_ignore	0	Excluded