Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 0 16 100.00


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
creator_sw_lock 2 0 2 100.00 100 1 1 2
hw_cfg_lock 2 0 2 100.00 100 1 1 2
lc_esc 2 0 2 100.00 100 1 1 2
owner_sw_lock 2 0 2 100.00 100 1 1 2
secret0_lock 2 0 2 100.00 100 1 1 2
secret1_lock 2 0 2 100.00 100 1 1 2
secret2_lock 2 0 2 100.00 100 1 1 2
vendor_sw_lock 2 0 2 100.00 100 1 1 2


Summary for Variable creator_sw_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for creator_sw_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7479 1 T19 2 T107 2 T108 2
auto[1] 5204 1 T1 3 T2 2 T4 7



Summary for Variable hw_cfg_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_cfg_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7665 1 T19 2 T107 2 T108 2
auto[1] 5018 1 T4 7 T7 1 T6 4



Summary for Variable lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12630 1 T19 2 T107 2 T108 2
auto[1] 53 1 T1 1 T98 1 T99 1



Summary for Variable owner_sw_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for owner_sw_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7855 1 T19 2 T107 2 T108 2
auto[1] 4828 1 T1 3 T2 2 T4 7



Summary for Variable secret0_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for secret0_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7717 1 T19 2 T107 2 T108 2
auto[1] 4966 1 T4 7 T7 1 T6 2



Summary for Variable secret1_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for secret1_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7696 1 T19 2 T107 2 T108 2
auto[1] 4987 1 T1 3 T4 7 T7 1



Summary for Variable secret2_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for secret2_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8999 1 T19 2 T107 2 T108 2
auto[1] 3684 1 T4 2 T7 1 T6 2



Summary for Variable vendor_sw_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for vendor_sw_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11074 1 T19 2 T107 2 T108 2
auto[1] 1609 1 T4 2 T104 8 T15 10

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