Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.88	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	1	14	93.33
Crosses	51	7	44	86.27

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	8	0	8	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	51	7	44	86.27	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	47868	1			T5	14		T98	51		T158	64
access_err	68091	1			T4	235		T5	18		T6	193
write_blank_err	363	1			T9	1		T97	1		T115	4
ecc_uncorr_err	51924	1			T5	31		T9	389		T97	765
ecc_corr_err	1103	1			T5	14		T115	1		T86	3
no_err	328634	1			T4	941		T5	165		T6	485

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lc_or_oob	37409	1			T4	162		T5	16		T6	98
secret2	66055	1			T4	132		T5	20		T6	76
secret1	78523	1			T4	108		T5	32		T6	80
secret0	71362	1			T4	100		T5	4		T6	56
hw_cfg	57860	1			T4	98		T5	110		T6	66
owner_sw_cfg	57961	1			T4	246		T5	10		T6	100
creator_sw_cfg	59539	1			T4	172		T5	20		T6	118
vendor_test	69274	1			T4	158		T5	30		T6	84

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	51	7	44	86.27	7
Automatically Generated Cross Bins	51	7	44	86.27	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	7

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	lc_or_oob	1525	1			T158	64		T186	44		T289	456
fsm_err	secret2	4237	1			T290	72		T213	403		T215	196
fsm_err	secret1	8375	1			T183	38		T229	328		T139	48
fsm_err	secret0	3898	1			T184	42		T96	10		T291	398
fsm_err	hw_cfg	6677	1			T5	14		T292	176		T190	16
fsm_err	owner_sw_cfg	3573	1			T98	51		T84	301		T293	35
fsm_err	creator_sw_cfg	4938	1			T294	32		T185	486		T122	23
fsm_err	vendor_test	14645	1			T103	161		T80	90		T96	100
access_err	lc_or_oob	17177	1			T4	81		T5	8		T6	49
access_err	secret2	11406	1			T4	43		T5	7		T6	12
access_err	secret1	5185	1			T6	18		T7	1		T10	22
access_err	secret0	4126	1			T4	2		T6	13		T7	3
access_err	hw_cfg	2527	1			T4	2		T5	2		T6	9
access_err	owner_sw_cfg	10223	1			T4	46		T6	31		T7	73
access_err	creator_sw_cfg	10156	1			T4	22		T5	1		T6	33
access_err	vendor_test	7291	1			T4	39		T6	28		T7	43
write_blank_err	secret2	22	1			T101	1		T116	1		T13	1
write_blank_err	secret1	33	1			T13	1		T280	1		T286	1
write_blank_err	secret0	50	1			T9	1		T15	1		T28	1
write_blank_err	hw_cfg	21	1			T115	2		T279	1		T295	1
write_blank_err	owner_sw_cfg	82	1			T11	3		T13	1		T280	2
write_blank_err	creator_sw_cfg	123	1			T97	1		T115	2		T11	1
write_blank_err	vendor_test	32	1			T11	2		T279	1		T296	1
ecc_uncorr_err	secret2	10504	1			T101	192		T116	700		T86	21
ecc_uncorr_err	secret1	13755	1			T5	10		T113	104		T13	628
ecc_uncorr_err	secret0	16808	1			T9	389		T15	111		T28	248
ecc_uncorr_err	hw_cfg	5155	1			T5	21		T115	343		T86	41
ecc_uncorr_err	owner_sw_cfg	2710	1			T113	65		T114	21		T122	64
ecc_uncorr_err	creator_sw_cfg	2992	1			T97	765		T113	155		T114	26
ecc_corr_err	secret2	107	1			T5	3		T93	2		T52	1
ecc_corr_err	secret1	127	1			T5	1		T86	1		T113	2
ecc_corr_err	secret0	182	1			T5	1		T93	13		T44	3
ecc_corr_err	hw_cfg	217	1			T5	4		T115	1		T86	1
ecc_corr_err	owner_sw_cfg	127	1			T86	1		T113	2		T93	5
ecc_corr_err	creator_sw_cfg	119	1			T5	2		T93	2		T44	1
ecc_corr_err	vendor_test	224	1			T5	3		T113	9		T93	1
no_err	lc_or_oob	18707	1			T4	81		T5	8		T6	49
no_err	secret2	39779	1			T4	89		T5	10		T6	64
no_err	secret1	51048	1			T4	108		T5	21		T6	62
no_err	secret0	46298	1			T4	98		T5	3		T6	43
no_err	hw_cfg	43263	1			T4	96		T5	69		T6	57
no_err	owner_sw_cfg	41246	1			T4	200		T5	10		T6	69
no_err	creator_sw_cfg	41211	1			T4	150		T5	17		T6	85
no_err	vendor_test	47082	1			T4	119		T5	27		T6	56

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
lc_or_oob_ignore	0	Excluded