Summary for Variable keymgr_rd_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for keymgr_rd_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3290 |
1 |
|
|
T111 |
1 |
|
T112 |
1 |
|
T175 |
1 |
auto[1] |
2199 |
1 |
|
|
T169 |
1 |
|
T110 |
1 |
|
T177 |
1 |
Summary for Variable secret2_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret2_lock
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3956 |
1 |
|
|
T169 |
1 |
|
T110 |
1 |
|
T111 |
1 |
auto[1] |
1533 |
1 |
|
|
T6 |
1 |
|
T8 |
1 |
|
T38 |
1 |
Summary for Cross keymgr_output_conditions
Samples crossed: keymgr_rd_en secret2_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for keymgr_output_conditions
Bins
keymgr_rd_en | secret2_lock | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
2360 |
1 |
|
|
T111 |
1 |
|
T112 |
1 |
|
T175 |
1 |
auto[0] |
auto[1] |
930 |
1 |
|
|
T6 |
1 |
|
T38 |
1 |
|
T29 |
3 |
auto[1] |
auto[0] |
1596 |
1 |
|
|
T169 |
1 |
|
T110 |
1 |
|
T177 |
1 |
auto[1] |
auto[1] |
603 |
1 |
|
|
T8 |
1 |
|
T29 |
2 |
|
T30 |
1 |