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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.28 92.55 91.03 92.21 92.11 93.28 96.53 95.27


Total test records in report: 1226
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T1037 /workspace/coverage/default/10.otp_ctrl_dai_errs.1931126806 Jan 03 12:53:56 PM PST 24 Jan 03 12:55:35 PM PST 24 160460721 ps
T1038 /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.1482725652 Jan 03 12:55:47 PM PST 24 Jan 03 12:57:09 PM PST 24 521928689 ps
T1039 /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.650823165 Jan 03 12:56:01 PM PST 24 Jan 03 12:57:15 PM PST 24 157776996 ps
T1040 /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.4198909381 Jan 03 12:54:07 PM PST 24 Jan 03 02:31:06 PM PST 24 435270629777 ps
T1041 /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.2839893673 Jan 03 12:56:12 PM PST 24 Jan 03 12:57:25 PM PST 24 227823333 ps
T1042 /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.293089664 Jan 03 12:54:33 PM PST 24 Jan 03 02:28:07 PM PST 24 728922235866 ps
T265 /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1654391020 Jan 03 12:54:57 PM PST 24 Jan 03 02:51:38 PM PST 24 784322860489 ps
T1043 /workspace/coverage/default/25.otp_ctrl_dai_lock.1337437873 Jan 03 12:53:56 PM PST 24 Jan 03 12:55:56 PM PST 24 17328896444 ps
T1044 /workspace/coverage/default/196.otp_ctrl_init_fail.2982897385 Jan 03 12:56:03 PM PST 24 Jan 03 12:57:23 PM PST 24 1966419259 ps
T135 /workspace/coverage/default/55.otp_ctrl_init_fail.3113869066 Jan 03 12:54:44 PM PST 24 Jan 03 12:56:25 PM PST 24 333412955 ps
T1045 /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.928493486 Jan 03 12:53:44 PM PST 24 Jan 03 12:55:11 PM PST 24 458382744 ps
T1046 /workspace/coverage/default/24.otp_ctrl_macro_errs.75130113 Jan 03 12:53:38 PM PST 24 Jan 03 12:54:57 PM PST 24 1340847599 ps
T1047 /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.1428753038 Jan 03 12:54:32 PM PST 24 Jan 03 01:42:53 PM PST 24 208083211969 ps
T1048 /workspace/coverage/default/22.otp_ctrl_alert_test.97128037 Jan 03 12:53:30 PM PST 24 Jan 03 12:54:40 PM PST 24 820998001 ps
T1049 /workspace/coverage/default/0.otp_ctrl_dai_errs.656055779 Jan 03 12:54:02 PM PST 24 Jan 03 12:55:49 PM PST 24 614437407 ps
T1050 /workspace/coverage/default/12.otp_ctrl_smoke.2080650392 Jan 03 12:53:47 PM PST 24 Jan 03 12:54:59 PM PST 24 200040080 ps
T1051 /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.3510560114 Jan 03 12:53:52 PM PST 24 Jan 03 01:03:41 PM PST 24 314501658935 ps
T1052 /workspace/coverage/default/71.otp_ctrl_init_fail.3442110918 Jan 03 12:54:51 PM PST 24 Jan 03 12:56:31 PM PST 24 235868559 ps
T1053 /workspace/coverage/default/238.otp_ctrl_init_fail.3244138858 Jan 03 12:56:17 PM PST 24 Jan 03 12:57:29 PM PST 24 150189209 ps
T1054 /workspace/coverage/default/2.otp_ctrl_background_chks.662890697 Jan 03 12:53:53 PM PST 24 Jan 03 12:55:21 PM PST 24 197885271 ps
T1055 /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.805072921 Jan 03 12:53:51 PM PST 24 Jan 03 12:55:14 PM PST 24 326611050 ps
T1056 /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.1187589815 Jan 03 12:56:02 PM PST 24 Jan 03 12:57:15 PM PST 24 278468493 ps
T1057 /workspace/coverage/default/20.otp_ctrl_dai_lock.3717416766 Jan 03 12:53:45 PM PST 24 Jan 03 12:55:00 PM PST 24 976924164 ps
T1058 /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.1850161386 Jan 03 12:53:51 PM PST 24 Jan 03 12:55:14 PM PST 24 163867030 ps
T1059 /workspace/coverage/default/9.otp_ctrl_background_chks.2545501926 Jan 03 12:53:38 PM PST 24 Jan 03 12:55:01 PM PST 24 2110170266 ps
T1060 /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.792367366 Jan 03 12:55:41 PM PST 24 Jan 03 02:50:56 PM PST 24 517374400858 ps
T1061 /workspace/coverage/default/9.otp_ctrl_init_fail.523183726 Jan 03 12:53:53 PM PST 24 Jan 03 12:55:20 PM PST 24 201512728 ps
T1062 /workspace/coverage/default/228.otp_ctrl_init_fail.3518551276 Jan 03 12:56:08 PM PST 24 Jan 03 12:57:28 PM PST 24 1762290038 ps
T1063 /workspace/coverage/default/166.otp_ctrl_init_fail.3337148149 Jan 03 12:56:01 PM PST 24 Jan 03 12:57:13 PM PST 24 99035510 ps
T1064 /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.826431900 Jan 03 12:53:49 PM PST 24 Jan 03 01:41:24 PM PST 24 137128120296 ps
T1065 /workspace/coverage/default/112.otp_ctrl_init_fail.1705285068 Jan 03 12:55:14 PM PST 24 Jan 03 12:56:59 PM PST 24 177883037 ps
T1066 /workspace/coverage/default/4.otp_ctrl_dai_lock.2308214118 Jan 03 12:53:40 PM PST 24 Jan 03 12:54:51 PM PST 24 364386930 ps
T1067 /workspace/coverage/default/17.otp_ctrl_dai_lock.768201884 Jan 03 12:53:56 PM PST 24 Jan 03 12:55:40 PM PST 24 473607782 ps
T1068 /workspace/coverage/default/82.otp_ctrl_init_fail.1617920045 Jan 03 12:54:56 PM PST 24 Jan 03 12:56:43 PM PST 24 152918721 ps
T1069 /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.1940518631 Jan 03 12:53:17 PM PST 24 Jan 03 12:54:12 PM PST 24 110467457 ps
T1070 /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.1457591536 Jan 03 12:54:14 PM PST 24 Jan 03 12:55:57 PM PST 24 580697303 ps
T1071 /workspace/coverage/default/47.otp_ctrl_test_access.800313214 Jan 03 12:54:28 PM PST 24 Jan 03 12:56:10 PM PST 24 706663586 ps
T1072 /workspace/coverage/default/2.otp_ctrl_parallel_key_req.1769485157 Jan 03 12:53:40 PM PST 24 Jan 03 12:55:01 PM PST 24 633860036 ps
T1073 /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.2485941975 Jan 03 12:54:32 PM PST 24 Jan 03 12:56:28 PM PST 24 9597177318 ps
T1074 /workspace/coverage/default/9.otp_ctrl_test_access.1912952952 Jan 03 12:53:57 PM PST 24 Jan 03 12:55:39 PM PST 24 565472416 ps
T1075 /workspace/coverage/default/0.otp_ctrl_low_freq_read.1729261639 Jan 03 12:53:46 PM PST 24 Jan 03 12:55:11 PM PST 24 7582418055 ps
T1076 /workspace/coverage/default/16.otp_ctrl_regwen.1808108368 Jan 03 12:53:44 PM PST 24 Jan 03 12:54:59 PM PST 24 157809991 ps
T1077 /workspace/coverage/default/13.otp_ctrl_stress_all.2879078258 Jan 03 12:53:39 PM PST 24 Jan 03 12:55:44 PM PST 24 4587459387 ps
T1078 /workspace/coverage/default/7.otp_ctrl_dai_lock.1681769855 Jan 03 12:53:45 PM PST 24 Jan 03 12:55:06 PM PST 24 355400060 ps
T1079 /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.3134805291 Jan 03 12:54:56 PM PST 24 Jan 03 02:19:14 PM PST 24 1038730318135 ps
T1080 /workspace/coverage/default/19.otp_ctrl_test_access.1861737274 Jan 03 12:53:44 PM PST 24 Jan 03 12:55:15 PM PST 24 2706578984 ps
T136 /workspace/coverage/default/48.otp_ctrl_init_fail.999287818 Jan 03 12:54:23 PM PST 24 Jan 03 12:56:02 PM PST 24 235700449 ps
T1081 /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.2491413413 Jan 03 12:54:57 PM PST 24 Jan 03 02:40:05 PM PST 24 424669257838 ps
T1082 /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.343965408 Jan 03 12:56:05 PM PST 24 Jan 03 12:57:17 PM PST 24 359659447 ps
T1083 /workspace/coverage/default/113.otp_ctrl_init_fail.862590947 Jan 03 12:55:13 PM PST 24 Jan 03 12:56:47 PM PST 24 265967121 ps
T1084 /workspace/coverage/default/38.otp_ctrl_alert_test.136830668 Jan 03 12:54:22 PM PST 24 Jan 03 12:56:05 PM PST 24 93059230 ps
T1085 /workspace/coverage/default/2.otp_ctrl_smoke.2094617436 Jan 03 12:53:51 PM PST 24 Jan 03 12:55:12 PM PST 24 145812246 ps
T1086 /workspace/coverage/default/26.otp_ctrl_parallel_key_req.2001110209 Jan 03 12:53:44 PM PST 24 Jan 03 12:55:14 PM PST 24 761802849 ps
T1087 /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.2737708478 Jan 03 12:53:58 PM PST 24 Jan 03 12:55:33 PM PST 24 556889048 ps
T1088 /workspace/coverage/default/20.otp_ctrl_macro_errs.1395958788 Jan 03 12:54:10 PM PST 24 Jan 03 12:56:05 PM PST 24 1594816758 ps
T1089 /workspace/coverage/default/27.otp_ctrl_dai_lock.2895307040 Jan 03 12:53:44 PM PST 24 Jan 03 12:55:27 PM PST 24 718451906 ps
T1090 /workspace/coverage/default/297.otp_ctrl_init_fail.2771666505 Jan 03 12:56:15 PM PST 24 Jan 03 12:57:28 PM PST 24 230293845 ps
T1091 /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.77663062 Jan 03 12:55:56 PM PST 24 Jan 03 12:57:22 PM PST 24 1935766196 ps
T1092 /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.2587306108 Jan 03 12:53:52 PM PST 24 Jan 03 12:55:22 PM PST 24 477424052 ps
T192 /workspace/coverage/default/1.otp_ctrl_sec_cm.3602508196 Jan 03 12:53:36 PM PST 24 Jan 03 12:57:02 PM PST 24 9237289942 ps
T1093 /workspace/coverage/default/44.otp_ctrl_parallel_key_req.2648900423 Jan 03 12:54:22 PM PST 24 Jan 03 12:56:19 PM PST 24 1124242052 ps
T1094 /workspace/coverage/default/5.otp_ctrl_test_access.591030719 Jan 03 12:53:38 PM PST 24 Jan 03 12:55:14 PM PST 24 12121562538 ps
T1095 /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.870679180 Jan 03 12:53:36 PM PST 24 Jan 03 02:09:06 PM PST 24 326221851867 ps
T1096 /workspace/coverage/default/119.otp_ctrl_init_fail.3312059207 Jan 03 12:55:42 PM PST 24 Jan 03 12:57:01 PM PST 24 116092084 ps
T1097 /workspace/coverage/default/27.otp_ctrl_test_access.2669163721 Jan 03 12:53:45 PM PST 24 Jan 03 12:54:56 PM PST 24 502907788 ps
T1098 /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.3641960059 Jan 03 12:56:36 PM PST 24 Jan 03 12:57:49 PM PST 24 117326257 ps
T1099 /workspace/coverage/default/45.otp_ctrl_macro_errs.1714586557 Jan 03 12:54:24 PM PST 24 Jan 03 12:56:15 PM PST 24 509407120 ps
T69 /workspace/coverage/default/18.otp_ctrl_check_fail.948353389 Jan 03 12:53:43 PM PST 24 Jan 03 12:55:04 PM PST 24 4025025229 ps
T1100 /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.833666445 Jan 03 12:54:05 PM PST 24 Jan 03 12:55:51 PM PST 24 459170197 ps
T1101 /workspace/coverage/default/16.otp_ctrl_macro_errs.2312502550 Jan 03 12:53:12 PM PST 24 Jan 03 12:54:38 PM PST 24 2560912989 ps
T1102 /workspace/coverage/default/15.otp_ctrl_regwen.39563224 Jan 03 12:53:52 PM PST 24 Jan 03 12:55:31 PM PST 24 246343196 ps
T1103 /workspace/coverage/default/24.otp_ctrl_parallel_key_req.3039614125 Jan 03 12:53:43 PM PST 24 Jan 03 12:54:55 PM PST 24 199045523 ps
T201 /workspace/coverage/default/269.otp_ctrl_init_fail.1317596916 Jan 03 12:56:21 PM PST 24 Jan 03 12:57:36 PM PST 24 402151891 ps
T1104 /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.3642620733 Jan 03 12:54:54 PM PST 24 Jan 03 01:56:10 PM PST 24 296838696283 ps
T1105 /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.2674750981 Jan 03 12:54:45 PM PST 24 Jan 03 12:56:28 PM PST 24 161377325 ps
T1106 /workspace/coverage/default/15.otp_ctrl_stress_all.2933812716 Jan 03 12:53:46 PM PST 24 Jan 03 12:55:08 PM PST 24 1076121135 ps
T1107 /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.851734258 Jan 03 12:53:49 PM PST 24 Jan 03 12:55:09 PM PST 24 3719537918 ps
T1108 /workspace/coverage/default/271.otp_ctrl_init_fail.4081868242 Jan 03 12:56:37 PM PST 24 Jan 03 12:57:51 PM PST 24 249261784 ps
T1109 /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.1323340885 Jan 03 12:53:37 PM PST 24 Jan 03 01:57:13 PM PST 24 3012596771873 ps
T1110 /workspace/coverage/default/40.otp_ctrl_check_fail.1675513333 Jan 03 12:54:03 PM PST 24 Jan 03 12:56:00 PM PST 24 3401116130 ps
T1111 /workspace/coverage/default/177.otp_ctrl_init_fail.989806312 Jan 03 12:56:01 PM PST 24 Jan 03 12:57:13 PM PST 24 365448109 ps
T1112 /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.544907904 Jan 03 12:53:54 PM PST 24 Jan 03 12:55:35 PM PST 24 373082103 ps
T1113 /workspace/coverage/default/272.otp_ctrl_init_fail.2705583359 Jan 03 12:56:06 PM PST 24 Jan 03 12:57:18 PM PST 24 1936232078 ps
T1114 /workspace/coverage/default/5.otp_ctrl_check_fail.434749619 Jan 03 12:53:13 PM PST 24 Jan 03 12:54:11 PM PST 24 1379448949 ps
T1115 /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.70608484 Jan 03 12:54:54 PM PST 24 Jan 03 01:41:54 PM PST 24 232989433100 ps
T1116 /workspace/coverage/default/7.otp_ctrl_stress_all.3238042160 Jan 03 12:53:30 PM PST 24 Jan 03 12:56:17 PM PST 24 7377535403 ps
T1117 /workspace/coverage/default/21.otp_ctrl_stress_all.1345063137 Jan 03 12:53:37 PM PST 24 Jan 03 12:56:18 PM PST 24 9186787450 ps
T1118 /workspace/coverage/default/233.otp_ctrl_init_fail.376869382 Jan 03 12:56:22 PM PST 24 Jan 03 12:57:36 PM PST 24 328284164 ps
T1119 /workspace/coverage/default/19.otp_ctrl_macro_errs.1957847365 Jan 03 12:54:09 PM PST 24 Jan 03 12:55:57 PM PST 24 486985305 ps
T1120 /workspace/coverage/default/2.otp_ctrl_alert_test.4098046356 Jan 03 12:53:51 PM PST 24 Jan 03 12:55:13 PM PST 24 77164189 ps
T1121 /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.2383879804 Jan 03 12:54:02 PM PST 24 Jan 03 12:55:45 PM PST 24 147902710 ps
T1122 /workspace/coverage/default/11.otp_ctrl_test_access.33600151 Jan 03 12:53:30 PM PST 24 Jan 03 12:54:37 PM PST 24 985771153 ps
T1123 /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.294274297 Jan 03 12:53:48 PM PST 24 Jan 03 12:55:14 PM PST 24 114726833 ps
T1124 /workspace/coverage/default/12.otp_ctrl_regwen.1991279879 Jan 03 12:53:27 PM PST 24 Jan 03 12:54:22 PM PST 24 251693925 ps
T1125 /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.2899198788 Jan 03 12:55:57 PM PST 24 Jan 03 12:57:15 PM PST 24 1326195472 ps
T1126 /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.863379032 Jan 03 12:53:47 PM PST 24 Jan 03 12:55:11 PM PST 24 640064267 ps
T1127 /workspace/coverage/default/2.otp_ctrl_test_access.1828112882 Jan 03 12:53:21 PM PST 24 Jan 03 12:54:11 PM PST 24 815647912 ps
T1128 /workspace/coverage/default/131.otp_ctrl_init_fail.664591930 Jan 03 12:56:01 PM PST 24 Jan 03 12:57:13 PM PST 24 521872324 ps
T1129 /workspace/coverage/default/18.otp_ctrl_regwen.1836310652 Jan 03 12:53:52 PM PST 24 Jan 03 12:55:25 PM PST 24 149851023 ps
T1130 /workspace/coverage/default/25.otp_ctrl_alert_test.272522874 Jan 03 12:53:44 PM PST 24 Jan 03 12:54:48 PM PST 24 152217517 ps
T1131 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1499650558 Jan 03 12:32:49 PM PST 24 Jan 03 12:34:49 PM PST 24 38544441 ps
T1132 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2835767418 Jan 03 12:32:42 PM PST 24 Jan 03 12:34:13 PM PST 24 37686344 ps
T206 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2005500840 Jan 03 12:32:40 PM PST 24 Jan 03 12:34:29 PM PST 24 2264054871 ps
T1133 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.4054858011 Jan 03 12:33:24 PM PST 24 Jan 03 12:34:46 PM PST 24 104827023 ps
T267 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1741998471 Jan 03 12:34:43 PM PST 24 Jan 03 12:35:59 PM PST 24 285712516 ps
T1134 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.976672619 Jan 03 12:32:56 PM PST 24 Jan 03 12:34:38 PM PST 24 320602813 ps
T268 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.883370257 Jan 03 12:32:58 PM PST 24 Jan 03 12:34:32 PM PST 24 144815488 ps
T1135 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3417746724 Jan 03 12:32:57 PM PST 24 Jan 03 12:34:28 PM PST 24 46856177 ps
T1136 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.3503422745 Jan 03 12:46:59 PM PST 24 Jan 03 12:48:03 PM PST 24 39054517 ps
T207 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.3463625272 Jan 03 12:33:03 PM PST 24 Jan 03 12:34:50 PM PST 24 1214121811 ps
T237 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.291243627 Jan 03 12:32:58 PM PST 24 Jan 03 12:34:47 PM PST 24 250602318 ps
T238 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.4294402249 Jan 03 12:32:48 PM PST 24 Jan 03 12:34:33 PM PST 24 275290982 ps
T239 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1536119465 Jan 03 12:32:54 PM PST 24 Jan 03 12:34:30 PM PST 24 1016142008 ps
T240 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.988936785 Jan 03 12:34:53 PM PST 24 Jan 03 12:36:28 PM PST 24 73666517 ps
T208 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3967924014 Jan 03 12:35:06 PM PST 24 Jan 03 12:36:58 PM PST 24 3006654916 ps
T241 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3990708400 Jan 03 12:33:19 PM PST 24 Jan 03 12:34:38 PM PST 24 157939871 ps
T242 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.569829191 Jan 03 12:33:48 PM PST 24 Jan 03 12:35:12 PM PST 24 79258304 ps
T243 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.423536577 Jan 03 12:37:09 PM PST 24 Jan 03 12:38:30 PM PST 24 60000877 ps
T244 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.1678838078 Jan 03 12:36:34 PM PST 24 Jan 03 12:38:07 PM PST 24 77405895 ps
T245 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.890572897 Jan 03 12:34:49 PM PST 24 Jan 03 12:36:00 PM PST 24 626028528 ps
T269 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1603092668 Jan 03 12:32:40 PM PST 24 Jan 03 12:34:38 PM PST 24 194528752 ps
T1137 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.683597570 Jan 03 12:35:00 PM PST 24 Jan 03 12:36:31 PM PST 24 181507827 ps
T303 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3763978354 Jan 03 12:32:56 PM PST 24 Jan 03 12:34:24 PM PST 24 1508247554 ps
T1138 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.2148050707 Jan 03 12:32:47 PM PST 24 Jan 03 12:34:10 PM PST 24 43784947 ps
T1139 /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3612858889 Jan 03 12:35:03 PM PST 24 Jan 03 12:36:20 PM PST 24 36256737 ps
T1140 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1320737148 Jan 03 12:33:31 PM PST 24 Jan 03 12:34:48 PM PST 24 151203261 ps
T1141 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.699241658 Jan 03 12:35:25 PM PST 24 Jan 03 12:36:58 PM PST 24 177891423 ps
T1142 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.4053427906 Jan 03 12:35:09 PM PST 24 Jan 03 12:36:42 PM PST 24 74743636 ps
T1143 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.4243328328 Jan 03 12:33:37 PM PST 24 Jan 03 12:35:00 PM PST 24 37852810 ps
T297 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3503246192 Jan 03 12:34:44 PM PST 24 Jan 03 12:36:31 PM PST 24 4637952373 ps
T1144 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.998837050 Jan 03 12:32:46 PM PST 24 Jan 03 12:34:49 PM PST 24 42205470 ps
T1145 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2378233963 Jan 03 12:33:11 PM PST 24 Jan 03 12:34:46 PM PST 24 525710553 ps
T1146 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1415151611 Jan 03 12:33:28 PM PST 24 Jan 03 12:35:02 PM PST 24 389167185 ps
T1147 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1097635736 Jan 03 12:33:50 PM PST 24 Jan 03 12:35:45 PM PST 24 145914982 ps
T1148 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.3121761250 Jan 03 12:33:12 PM PST 24 Jan 03 12:34:43 PM PST 24 142011405 ps
T1149 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1569691666 Jan 03 12:35:27 PM PST 24 Jan 03 12:37:01 PM PST 24 38778631 ps
T1150 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3167291643 Jan 03 12:33:15 PM PST 24 Jan 03 12:34:43 PM PST 24 129513190 ps
T1151 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.4030986618 Jan 03 12:32:59 PM PST 24 Jan 03 12:34:27 PM PST 24 146662942 ps
T1152 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.2126479245 Jan 03 12:32:46 PM PST 24 Jan 03 12:34:28 PM PST 24 38379408 ps
T1153 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2101724632 Jan 03 12:32:57 PM PST 24 Jan 03 12:34:59 PM PST 24 250620961 ps
T1154 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2723855173 Jan 03 12:32:35 PM PST 24 Jan 03 12:34:14 PM PST 24 130730622 ps
T1155 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1165390182 Jan 03 12:33:32 PM PST 24 Jan 03 12:34:44 PM PST 24 60259422 ps
T1156 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1501067393 Jan 03 12:32:34 PM PST 24 Jan 03 12:33:59 PM PST 24 1024264629 ps
T246 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2831623579 Jan 03 12:33:06 PM PST 24 Jan 03 12:34:34 PM PST 24 44625634 ps
T1157 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.2227862687 Jan 03 12:33:47 PM PST 24 Jan 03 12:35:25 PM PST 24 43862164 ps
T1158 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3731150517 Jan 03 12:33:33 PM PST 24 Jan 03 12:34:48 PM PST 24 39834033 ps
T1159 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3999741354 Jan 03 12:32:25 PM PST 24 Jan 03 12:34:08 PM PST 24 82828668 ps
T266 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.921814559 Jan 03 12:32:32 PM PST 24 Jan 03 12:34:01 PM PST 24 113534089 ps
T1160 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.1474801955 Jan 03 12:33:29 PM PST 24 Jan 03 12:35:07 PM PST 24 147067342 ps
T1161 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.1938050021 Jan 03 12:33:24 PM PST 24 Jan 03 12:34:58 PM PST 24 633289913 ps
T1162 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.3991344495 Jan 03 12:33:25 PM PST 24 Jan 03 12:35:01 PM PST 24 511562667 ps
T1163 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3407502729 Jan 03 12:33:11 PM PST 24 Jan 03 12:34:56 PM PST 24 167364582 ps
T1164 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.1969094210 Jan 03 12:33:01 PM PST 24 Jan 03 12:34:45 PM PST 24 76008109 ps
T1165 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.3668830760 Jan 03 12:33:44 PM PST 24 Jan 03 12:35:13 PM PST 24 588282854 ps
T1166 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.968944665 Jan 03 12:35:04 PM PST 24 Jan 03 12:36:29 PM PST 24 1894559899 ps
T1167 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2898646175 Jan 03 12:33:16 PM PST 24 Jan 03 12:34:38 PM PST 24 80434531 ps
T1168 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3881777903 Jan 03 12:32:58 PM PST 24 Jan 03 12:34:34 PM PST 24 329413998 ps
T1169 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3862849414 Jan 03 12:32:52 PM PST 24 Jan 03 12:34:28 PM PST 24 1274892117 ps
T1170 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.3499052159 Jan 03 12:32:33 PM PST 24 Jan 03 12:34:04 PM PST 24 41429569 ps
T1171 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.305566439 Jan 03 12:32:51 PM PST 24 Jan 03 12:34:16 PM PST 24 1463702961 ps
T1172 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.4077350551 Jan 03 12:33:44 PM PST 24 Jan 03 12:35:00 PM PST 24 71780043 ps
T300 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1533833182 Jan 03 12:32:42 PM PST 24 Jan 03 12:34:45 PM PST 24 1259133752 ps
T306 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3502446553 Jan 03 12:33:05 PM PST 24 Jan 03 12:34:59 PM PST 24 691108720 ps
T1173 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.425007003 Jan 03 12:33:35 PM PST 24 Jan 03 12:35:04 PM PST 24 102401671 ps
T301 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2662170665 Jan 03 12:32:26 PM PST 24 Jan 03 12:34:07 PM PST 24 2949146818 ps
T1174 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3322277816 Jan 03 12:33:27 PM PST 24 Jan 03 12:34:43 PM PST 24 104822520 ps
T1175 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.419060532 Jan 03 12:33:16 PM PST 24 Jan 03 12:34:28 PM PST 24 145009433 ps
T1176 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.1406708950 Jan 03 12:32:58 PM PST 24 Jan 03 12:34:45 PM PST 24 48372169 ps
T1177 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3231021795 Jan 03 12:35:18 PM PST 24 Jan 03 12:36:51 PM PST 24 369597520 ps
T1178 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3070543237 Jan 03 12:33:05 PM PST 24 Jan 03 12:34:25 PM PST 24 516752008 ps
T1179 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.424924452 Jan 03 12:33:34 PM PST 24 Jan 03 12:35:02 PM PST 24 74098915 ps
T1180 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2907128769 Jan 03 12:33:27 PM PST 24 Jan 03 12:34:54 PM PST 24 1486275480 ps
T1181 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.1060811717 Jan 03 12:33:05 PM PST 24 Jan 03 12:34:53 PM PST 24 60470854 ps
T304 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3127380975 Jan 03 12:34:42 PM PST 24 Jan 03 12:36:20 PM PST 24 4114397398 ps
T1182 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.579879185 Jan 03 12:33:13 PM PST 24 Jan 03 12:34:34 PM PST 24 79339203 ps
T302 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.630657926 Jan 03 12:33:21 PM PST 24 Jan 03 12:34:50 PM PST 24 2113680651 ps
T1183 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.901956963 Jan 03 12:33:19 PM PST 24 Jan 03 12:34:56 PM PST 24 196464902 ps
T305 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.521102796 Jan 03 12:33:30 PM PST 24 Jan 03 12:35:25 PM PST 24 2496913930 ps
T1184 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1359651013 Jan 03 12:33:02 PM PST 24 Jan 03 12:35:04 PM PST 24 86237390 ps
T1185 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2016467872 Jan 03 12:33:10 PM PST 24 Jan 03 12:34:38 PM PST 24 1057885253 ps
T1186 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2927009505 Jan 03 12:33:24 PM PST 24 Jan 03 12:35:01 PM PST 24 38722265 ps
T1187 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3710174388 Jan 03 12:33:32 PM PST 24 Jan 03 12:34:43 PM PST 24 129268340 ps
T1188 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.1956569696 Jan 03 12:34:43 PM PST 24 Jan 03 12:36:28 PM PST 24 75388944 ps
T1189 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.4046278664 Jan 03 12:32:28 PM PST 24 Jan 03 12:34:09 PM PST 24 493337905 ps
T1190 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.3927110581 Jan 03 12:37:05 PM PST 24 Jan 03 12:38:14 PM PST 24 542035773 ps
T1191 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.977440936 Jan 03 12:35:35 PM PST 24 Jan 03 12:37:09 PM PST 24 129689832 ps
T1192 /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1496915532 Jan 03 12:34:27 PM PST 24 Jan 03 12:35:48 PM PST 24 128762712 ps
T1193 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.672913743 Jan 03 12:32:40 PM PST 24 Jan 03 12:34:08 PM PST 24 38677659 ps
T1194 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2122196640 Jan 03 12:32:52 PM PST 24 Jan 03 12:34:13 PM PST 24 41925766 ps
T1195 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1189935046 Jan 03 12:33:10 PM PST 24 Jan 03 12:34:28 PM PST 24 88796960 ps
T1196 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2394719730 Jan 03 12:33:08 PM PST 24 Jan 03 12:34:46 PM PST 24 139629200 ps
T298 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.396180007 Jan 03 12:33:04 PM PST 24 Jan 03 12:34:40 PM PST 24 1675061707 ps
T1197 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.171211487 Jan 03 12:32:55 PM PST 24 Jan 03 12:34:48 PM PST 24 36045223 ps
T1198 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3151511521 Jan 03 12:33:27 PM PST 24 Jan 03 12:34:54 PM PST 24 1533676940 ps
T1199 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.393574554 Jan 03 12:32:48 PM PST 24 Jan 03 12:34:17 PM PST 24 146538465 ps
T1200 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.94000512 Jan 03 12:33:03 PM PST 24 Jan 03 12:34:52 PM PST 24 100380349 ps
T1201 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3429095898 Jan 03 12:36:31 PM PST 24 Jan 03 12:37:58 PM PST 24 65073203 ps
T1202 /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.429827247 Jan 03 12:32:35 PM PST 24 Jan 03 12:34:12 PM PST 24 120927895 ps
T1203 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1867122616 Jan 03 12:33:07 PM PST 24 Jan 03 12:34:32 PM PST 24 262741478 ps
T1204 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.772038977 Jan 03 12:34:20 PM PST 24 Jan 03 12:36:10 PM PST 24 142109504 ps
T1205 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1834852486 Jan 03 12:34:27 PM PST 24 Jan 03 12:36:13 PM PST 24 93452139 ps
T1206 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.800969001 Jan 03 12:33:21 PM PST 24 Jan 03 12:34:45 PM PST 24 65861803 ps
T247 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1488029455 Jan 03 12:33:17 PM PST 24 Jan 03 12:34:43 PM PST 24 195185066 ps
T248 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.533681575 Jan 03 12:32:42 PM PST 24 Jan 03 12:34:29 PM PST 24 105917213 ps
T1207 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.4142223213 Jan 03 12:33:12 PM PST 24 Jan 03 12:35:01 PM PST 24 1928832038 ps
T1208 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2583505367 Jan 03 12:32:46 PM PST 24 Jan 03 12:34:26 PM PST 24 216409237 ps
T1209 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.783560 Jan 03 12:32:58 PM PST 24 Jan 03 12:35:00 PM PST 24 4379165283 ps
T1210 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3033201994 Jan 03 12:33:24 PM PST 24 Jan 03 12:34:46 PM PST 24 1072341709 ps
T1211 /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3958598872 Jan 03 12:36:34 PM PST 24 Jan 03 12:38:03 PM PST 24 93452186 ps
T1212 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3036725343 Jan 03 12:33:54 PM PST 24 Jan 03 12:35:36 PM PST 24 1081911058 ps
T1213 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1440272525 Jan 03 12:33:24 PM PST 24 Jan 03 12:34:49 PM PST 24 134124587 ps
T1214 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3245383511 Jan 03 12:33:06 PM PST 24 Jan 03 12:34:26 PM PST 24 555224446 ps
T1215 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2162515044 Jan 03 12:33:00 PM PST 24 Jan 03 12:34:26 PM PST 24 40218362 ps
T1216 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1659056623 Jan 03 12:33:05 PM PST 24 Jan 03 12:34:21 PM PST 24 47654451 ps
T1217 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.901167169 Jan 03 12:33:44 PM PST 24 Jan 03 12:35:24 PM PST 24 869935812 ps
T1218 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3705767196 Jan 03 12:33:39 PM PST 24 Jan 03 12:35:09 PM PST 24 186187296 ps
T1219 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.645206694 Jan 03 12:32:34 PM PST 24 Jan 03 12:34:14 PM PST 24 165242946 ps
T1220 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.71883248 Jan 03 12:32:39 PM PST 24 Jan 03 12:34:14 PM PST 24 114359175 ps
T1221 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.733528363 Jan 03 12:32:50 PM PST 24 Jan 03 12:34:57 PM PST 24 169125715 ps
T299 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1964201469 Jan 03 12:32:39 PM PST 24 Jan 03 12:34:51 PM PST 24 9322952333 ps
T1222 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.3925323324 Jan 03 12:32:48 PM PST 24 Jan 03 12:34:43 PM PST 24 589859625 ps
T1223 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3376541168 Jan 03 12:33:42 PM PST 24 Jan 03 12:35:10 PM PST 24 35667008 ps
T249 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3817495435 Jan 03 12:35:06 PM PST 24 Jan 03 12:36:44 PM PST 24 90868758 ps
T1224 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2107781621 Jan 03 12:35:03 PM PST 24 Jan 03 12:36:46 PM PST 24 516713365 ps
T1225 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2893112487 Jan 03 12:32:34 PM PST 24 Jan 03 12:34:16 PM PST 24 1178986573 ps
T1226 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2877428643 Jan 03 12:35:04 PM PST 24 Jan 03 12:36:25 PM PST 24 154138379 ps

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.1148998561
Short name T7
Test name
Test status
Simulation time 111137573811 ps
CPU time 2101.79 seconds
Started Jan 03 12:54:10 PM PST 24
Finished Jan 03 01:30:48 PM PST 24
Peak memory 393216 kb
Host smart-7ac3136f-f5c0-4e44-83ac-6ef613e449c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148998561 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.1148998561
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.793686352
Short name T14
Test name
Test status
Simulation time 138550105 ps
CPU time 1.21 seconds
Started Jan 03 12:34:00 PM PST 24
Finished Jan 03 12:36:27 PM PST 24
Peak memory 229108 kb
Host smart-c8197570-c612-40a6-ae26-0a18caae8487
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793686352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl
_mem_partial_access.793686352
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3012535128
Short name T108
Test name
Test status
Simulation time 1260957633 ps
CPU time 15.68 seconds
Started Jan 03 12:32:46 PM PST 24
Finished Jan 03 12:34:29 PM PST 24
Peak memory 237716 kb
Host smart-ecc53ac0-73f5-4a65-96b5-4783177379af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012535128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.3012535128
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.735915326
Short name T29
Test name
Test status
Simulation time 1033533136 ps
CPU time 14.78 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:55:40 PM PST 24
Peak memory 238428 kb
Host smart-11e03750-335d-45f2-87b6-e653af39118f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=735915326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.735915326
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.1310309695
Short name T96
Test name
Test status
Simulation time 8764017683 ps
CPU time 70 seconds
Started Jan 03 12:54:03 PM PST 24
Finished Jan 03 12:56:52 PM PST 24
Peak memory 246808 kb
Host smart-2ebc6579-0938-4e98-8f3d-55a10c6644c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310309695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.1310309695
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.464221880
Short name T179
Test name
Test status
Simulation time 7986626828 ps
CPU time 115.07 seconds
Started Jan 03 12:53:59 PM PST 24
Finished Jan 03 12:57:31 PM PST 24
Peak memory 244252 kb
Host smart-f3de829e-f5ae-41ce-ab51-66dca3cd3e09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464221880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.
464221880
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.2072084681
Short name T5
Test name
Test status
Simulation time 2230807782 ps
CPU time 15.29 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:26 PM PST 24
Peak memory 238644 kb
Host smart-2b48e864-be24-4324-86f5-9972cca55ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072084681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.2072084681
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.3178682338
Short name T191
Test name
Test status
Simulation time 32801714312 ps
CPU time 147.95 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:57:20 PM PST 24
Peak memory 272396 kb
Host smart-ab9aa784-6886-414a-8342-6fc30b083e35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178682338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.3178682338
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.2457225908
Short name T326
Test name
Test status
Simulation time 77890347322 ps
CPU time 168.9 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:58:11 PM PST 24
Peak memory 246824 kb
Host smart-4f83631d-c6b6-410c-a619-b898ef36a9a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457225908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.2457225908
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.1007117366
Short name T110
Test name
Test status
Simulation time 140593810 ps
CPU time 1.33 seconds
Started Jan 03 12:33:43 PM PST 24
Finished Jan 03 12:35:13 PM PST 24
Peak memory 229268 kb
Host smart-1777c94c-0078-4c0b-ae4f-47226e463dfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007117366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.1007117366
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.2845762951
Short name T85
Test name
Test status
Simulation time 4085870828 ps
CPU time 55.2 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:55:27 PM PST 24
Peak memory 246868 kb
Host smart-67ca6cdc-ba19-492f-8775-c5c5d3b7e5df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845762951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
2845762951
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.1470936624
Short name T11
Test name
Test status
Simulation time 508342556103 ps
CPU time 10105.4 seconds
Started Jan 03 12:54:35 PM PST 24
Finished Jan 03 03:44:49 PM PST 24
Peak memory 1813144 kb
Host smart-c1923ab5-0b78-4677-b6d2-474d1cefa7ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470936624 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.1470936624
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.2625027677
Short name T93
Test name
Test status
Simulation time 759458317 ps
CPU time 12.43 seconds
Started Jan 03 12:53:50 PM PST 24
Finished Jan 03 12:55:17 PM PST 24
Peak memory 238504 kb
Host smart-6f30a6c3-5d0d-4596-aafc-fe3ceda48296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625027677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.2625027677
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.3916545393
Short name T26
Test name
Test status
Simulation time 422585500 ps
CPU time 12.93 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:12 PM PST 24
Peak memory 238508 kb
Host smart-ca8c2230-8dc3-43a0-a456-b3f99da74d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916545393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.3916545393
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.1670780818
Short name T321
Test name
Test status
Simulation time 67029119867 ps
CPU time 117.25 seconds
Started Jan 03 12:54:01 PM PST 24
Finished Jan 03 12:57:31 PM PST 24
Peak memory 239408 kb
Host smart-b01b57c5-d99a-4bf0-ba73-35813ebdb620
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670780818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.1670780818
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.135964209
Short name T214
Test name
Test status
Simulation time 1348928802479 ps
CPU time 6901.84 seconds
Started Jan 03 12:53:49 PM PST 24
Finished Jan 03 02:50:03 PM PST 24
Peak memory 1267696 kb
Host smart-1f74e286-6821-46f8-86f0-d11279f23c1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135964209 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.135964209
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.2564278203
Short name T134
Test name
Test status
Simulation time 125150983 ps
CPU time 4.23 seconds
Started Jan 03 12:55:46 PM PST 24
Finished Jan 03 12:57:04 PM PST 24
Peak memory 241156 kb
Host smart-ebd31f55-cd0f-4f83-b0ac-aca01b2ace4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564278203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.2564278203
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.3172504456
Short name T50
Test name
Test status
Simulation time 424241579 ps
CPU time 4.55 seconds
Started Jan 03 12:53:43 PM PST 24
Finished Jan 03 12:55:04 PM PST 24
Peak memory 238380 kb
Host smart-defb28ea-2a50-4127-ae3f-2a37ff1fa7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172504456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.3172504456
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.762860886
Short name T39
Test name
Test status
Simulation time 551436774 ps
CPU time 4.07 seconds
Started Jan 03 12:56:17 PM PST 24
Finished Jan 03 12:57:29 PM PST 24
Peak memory 241080 kb
Host smart-8814d5a7-1d41-4758-8175-5f7bb598c968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762860886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.762860886
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.439670055
Short name T344
Test name
Test status
Simulation time 83633690655 ps
CPU time 177.16 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:58:19 PM PST 24
Peak memory 241384 kb
Host smart-0044e7dd-c1d4-4386-ab8f-6c0b742f83be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439670055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.
439670055
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.692625941
Short name T28
Test name
Test status
Simulation time 383375737696 ps
CPU time 3285.43 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 01:49:53 PM PST 24
Peak memory 279412 kb
Host smart-9311ff1a-a1c6-405a-b864-c19c2216349a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692625941 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.692625941
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.3068095743
Short name T82
Test name
Test status
Simulation time 3588170032 ps
CPU time 7.98 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:54:53 PM PST 24
Peak memory 238580 kb
Host smart-9a631555-7eb1-4078-96cc-1d24d1cfdca4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3068095743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.3068095743
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.3684097529
Short name T114
Test name
Test status
Simulation time 987913650 ps
CPU time 15.84 seconds
Started Jan 03 12:52:59 PM PST 24
Finished Jan 03 12:54:27 PM PST 24
Peak memory 238516 kb
Host smart-673b1fa8-da77-4690-9b23-3965fcd41a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684097529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.3684097529
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3967924014
Short name T208
Test name
Test status
Simulation time 3006654916 ps
CPU time 18.69 seconds
Started Jan 03 12:35:06 PM PST 24
Finished Jan 03 12:36:58 PM PST 24
Peak memory 229612 kb
Host smart-e9195c30-ddc2-4bdd-b53e-74eaa7475bcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967924014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.3967924014
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.948486490
Short name T35
Test name
Test status
Simulation time 215295188 ps
CPU time 5.04 seconds
Started Jan 03 12:55:57 PM PST 24
Finished Jan 03 12:57:12 PM PST 24
Peak memory 241160 kb
Host smart-0f907a62-016d-4462-af24-4789d6d77bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948486490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.948486490
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.2329609172
Short name T336
Test name
Test status
Simulation time 9375327255 ps
CPU time 60.6 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:56:19 PM PST 24
Peak memory 238676 kb
Host smart-53875bad-0584-41c8-b06e-dce38d477114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329609172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.2329609172
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.575528092
Short name T3
Test name
Test status
Simulation time 277840046 ps
CPU time 3.79 seconds
Started Jan 03 12:56:11 PM PST 24
Finished Jan 03 12:57:23 PM PST 24
Peak memory 238392 kb
Host smart-82bbbd27-adaf-4993-bd51-f7d804e26048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575528092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.575528092
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.3962527702
Short name T47
Test name
Test status
Simulation time 1676185682 ps
CPU time 11.55 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:09 PM PST 24
Peak memory 238584 kb
Host smart-36a3e7d9-8189-4a11-9794-ce4ac35bb6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962527702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3962527702
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.2557546446
Short name T64
Test name
Test status
Simulation time 245571446 ps
CPU time 4.91 seconds
Started Jan 03 12:56:19 PM PST 24
Finished Jan 03 12:57:34 PM PST 24
Peak memory 240976 kb
Host smart-51e77db0-ca4b-49c0-a5bd-1544e295fe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557546446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.2557546446
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.1710516242
Short name T22
Test name
Test status
Simulation time 2533455111 ps
CPU time 7.02 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:54:52 PM PST 24
Peak memory 241788 kb
Host smart-71acb714-a666-4d39-84d7-cc0968409122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710516242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.1710516242
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.1604150482
Short name T45
Test name
Test status
Simulation time 396002286 ps
CPU time 7.9 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:08 PM PST 24
Peak memory 238492 kb
Host smart-eb0add1f-47a0-475b-baaa-66c6ed265a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604150482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.1604150482
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1245981538
Short name T109
Test name
Test status
Simulation time 155546946 ps
CPU time 2.38 seconds
Started Jan 03 12:32:40 PM PST 24
Finished Jan 03 12:34:43 PM PST 24
Peak memory 229516 kb
Host smart-0699d45b-03ef-4f97-a050-4e3cca8af3d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245981538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.1245981538
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.1374569478
Short name T55
Test name
Test status
Simulation time 594614286 ps
CPU time 4.39 seconds
Started Jan 03 12:56:37 PM PST 24
Finished Jan 03 12:57:52 PM PST 24
Peak memory 238364 kb
Host smart-bf7ce6e8-a6ef-48fb-aaab-1e1f389c6342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374569478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.1374569478
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.2300111740
Short name T365
Test name
Test status
Simulation time 677485951 ps
CPU time 1.82 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:54:49 PM PST 24
Peak memory 237840 kb
Host smart-8f71fcb5-21f2-42c9-b33b-2919cf3afc91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300111740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.2300111740
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.2761154993
Short name T148
Test name
Test status
Simulation time 15767331472 ps
CPU time 92.37 seconds
Started Jan 03 12:54:04 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 246840 kb
Host smart-053dd8ee-2022-4161-823e-5c5c0fa0bf6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761154993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.2761154993
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.759491658
Short name T315
Test name
Test status
Simulation time 280623030 ps
CPU time 7.52 seconds
Started Jan 03 12:54:26 PM PST 24
Finished Jan 03 12:56:13 PM PST 24
Peak memory 238516 kb
Host smart-c9111f65-6603-4f70-b6ef-d232b78dbeff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759491658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.759491658
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.2265540601
Short name T180
Test name
Test status
Simulation time 19291703494 ps
CPU time 285.85 seconds
Started Jan 03 12:54:40 PM PST 24
Finished Jan 03 01:00:59 PM PST 24
Peak memory 260240 kb
Host smart-11be8f18-55e3-4b28-a151-cc124b8e165f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265540601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.2265540601
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2662170665
Short name T301
Test name
Test status
Simulation time 2949146818 ps
CPU time 17.4 seconds
Started Jan 03 12:32:26 PM PST 24
Finished Jan 03 12:34:07 PM PST 24
Peak memory 229952 kb
Host smart-a79f5e9e-8b43-4d11-b2b1-fa0a60123767
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662170665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.2662170665
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.2619758413
Short name T71
Test name
Test status
Simulation time 173587269 ps
CPU time 3.72 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:54:52 PM PST 24
Peak memory 238352 kb
Host smart-01a291fc-3cee-4c12-aba8-152f226ad692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619758413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.2619758413
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.425035998
Short name T51
Test name
Test status
Simulation time 307768111 ps
CPU time 4.23 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:22 PM PST 24
Peak memory 243200 kb
Host smart-37ec490c-8d31-4ad5-b14c-3e9a68dc0493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425035998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.425035998
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.3750398732
Short name T117
Test name
Test status
Simulation time 600659301 ps
CPU time 4.2 seconds
Started Jan 03 12:56:07 PM PST 24
Finished Jan 03 12:57:20 PM PST 24
Peak memory 241208 kb
Host smart-2a687193-ae8f-4eef-976d-13679c43876a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750398732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.3750398732
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.3188140188
Short name T165
Test name
Test status
Simulation time 10396145562 ps
CPU time 22.1 seconds
Started Jan 03 12:54:03 PM PST 24
Finished Jan 03 12:56:04 PM PST 24
Peak memory 238604 kb
Host smart-2c7460ce-74d7-459e-a0ad-e2eb3ae036f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188140188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.3188140188
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.1933110949
Short name T203
Test name
Test status
Simulation time 281108261 ps
CPU time 4.59 seconds
Started Jan 03 12:55:45 PM PST 24
Finished Jan 03 12:57:01 PM PST 24
Peak memory 240900 kb
Host smart-7dd4b5ed-713e-4760-8908-fd09169275f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933110949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.1933110949
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.2403824086
Short name T359
Test name
Test status
Simulation time 8748491189 ps
CPU time 66.52 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:59 PM PST 24
Peak memory 242756 kb
Host smart-6f6bf7b7-6198-4141-ae9e-00f92df2ef05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403824086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.2403824086
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.1041463603
Short name T342
Test name
Test status
Simulation time 80508502107 ps
CPU time 599.84 seconds
Started Jan 03 12:54:02 PM PST 24
Finished Jan 03 01:05:41 PM PST 24
Peak memory 288896 kb
Host smart-19bdabe0-f7d1-4532-889e-459c9e058c4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041463603 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.1041463603
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.1048371649
Short name T57
Test name
Test status
Simulation time 2519047096 ps
CPU time 6.71 seconds
Started Jan 03 12:53:29 PM PST 24
Finished Jan 03 12:54:28 PM PST 24
Peak memory 238528 kb
Host smart-552fc189-8639-4a07-a73f-9860afc4c96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048371649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.1048371649
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.26475752
Short name T118
Test name
Test status
Simulation time 529560810 ps
CPU time 3.64 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:55:19 PM PST 24
Peak memory 238368 kb
Host smart-faf98256-7d00-4bc4-9c15-c07c482cfb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26475752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.26475752
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.3999665158
Short name T23
Test name
Test status
Simulation time 148708354 ps
CPU time 3.93 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:49 PM PST 24
Peak memory 238432 kb
Host smart-f0e57476-7987-4502-9c77-6506fda526f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999665158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.3999665158
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.2111418113
Short name T307
Test name
Test status
Simulation time 662069682 ps
CPU time 7.98 seconds
Started Jan 03 12:54:15 PM PST 24
Finished Jan 03 12:56:02 PM PST 24
Peak memory 238492 kb
Host smart-20dfac56-5718-4552-9895-603a34363fd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2111418113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.2111418113
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.2286968591
Short name T178
Test name
Test status
Simulation time 417630943 ps
CPU time 5.35 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:55:33 PM PST 24
Peak memory 238468 kb
Host smart-7addccdc-a8ec-4fe1-a42d-560f8ab48b56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286968591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.2286968591
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1964201469
Short name T299
Test name
Test status
Simulation time 9322952333 ps
CPU time 13.69 seconds
Started Jan 03 12:32:39 PM PST 24
Finished Jan 03 12:34:51 PM PST 24
Peak memory 229780 kb
Host smart-51e7070c-54a9-4c29-bc9c-cea656f41580
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964201469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.1964201469
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3127380975
Short name T304
Test name
Test status
Simulation time 4114397398 ps
CPU time 15.5 seconds
Started Jan 03 12:34:42 PM PST 24
Finished Jan 03 12:36:20 PM PST 24
Peak memory 237460 kb
Host smart-ddeb2d68-41c7-44a5-9c0e-f69a145407ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127380975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.3127380975
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.2970033133
Short name T599
Test name
Test status
Simulation time 180547876 ps
CPU time 4.18 seconds
Started Jan 03 12:55:14 PM PST 24
Finished Jan 03 12:57:04 PM PST 24
Peak memory 238272 kb
Host smart-810c04b1-d7f7-46e3-bf7c-1537116d4e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970033133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.2970033133
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2580123642
Short name T168
Test name
Test status
Simulation time 70063972 ps
CPU time 2.24 seconds
Started Jan 03 12:32:58 PM PST 24
Finished Jan 03 12:34:23 PM PST 24
Peak memory 237796 kb
Host smart-3c996133-6b74-48f4-9c26-d1bb0a299609
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580123642 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.2580123642
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.921814559
Short name T266
Test name
Test status
Simulation time 113534089 ps
CPU time 3.74 seconds
Started Jan 03 12:32:32 PM PST 24
Finished Jan 03 12:34:01 PM PST 24
Peak memory 229460 kb
Host smart-ce80c9c1-9a4d-4b08-854d-d71adda295fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921814559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alias
ing.921814559
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1488029455
Short name T247
Test name
Test status
Simulation time 195185066 ps
CPU time 2.09 seconds
Started Jan 03 12:33:17 PM PST 24
Finished Jan 03 12:34:43 PM PST 24
Peak memory 229532 kb
Host smart-56b4e286-7ccb-451f-992a-762fb4734a3d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488029455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.1488029455
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.533681575
Short name T248
Test name
Test status
Simulation time 105917213 ps
CPU time 1.42 seconds
Started Jan 03 12:32:42 PM PST 24
Finished Jan 03 12:34:29 PM PST 24
Peak memory 229396 kb
Host smart-2f0566fe-93de-411a-8fe6-fb0f70028cee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533681575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.533681575
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.1477872314
Short name T31
Test name
Test status
Simulation time 2076919884 ps
CPU time 15.13 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:54:49 PM PST 24
Peak memory 238436 kb
Host smart-8b8a4300-7dc3-4646-b54d-f726765090f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1477872314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.1477872314
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.3465137838
Short name T187
Test name
Test status
Simulation time 380272590514 ps
CPU time 2272.38 seconds
Started Jan 03 12:53:58 PM PST 24
Finished Jan 03 01:33:27 PM PST 24
Peak memory 915492 kb
Host smart-71c6e810-e176-4d60-b417-81b2ddcf6e80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465137838 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.3465137838
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.829353277
Short name T60
Test name
Test status
Simulation time 1871746962 ps
CPU time 13.93 seconds
Started Jan 03 12:54:02 PM PST 24
Finished Jan 03 12:55:55 PM PST 24
Peak memory 238616 kb
Host smart-2061b13c-3e6e-4eb9-a1a2-26548a1b6caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829353277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.829353277
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.2137517271
Short name T56
Test name
Test status
Simulation time 115126916 ps
CPU time 3.83 seconds
Started Jan 03 12:56:02 PM PST 24
Finished Jan 03 12:57:13 PM PST 24
Peak memory 240396 kb
Host smart-dc3f1a2e-a1e3-47bb-a78a-afe584898ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137517271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.2137517271
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.1317596916
Short name T201
Test name
Test status
Simulation time 402151891 ps
CPU time 3.74 seconds
Started Jan 03 12:56:21 PM PST 24
Finished Jan 03 12:57:36 PM PST 24
Peak memory 240916 kb
Host smart-2d82d75a-8db9-496c-8b15-4f6ae87359b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317596916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.1317596916
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.4165901470
Short name T162
Test name
Test status
Simulation time 5469565274 ps
CPU time 32.08 seconds
Started Jan 03 12:54:06 PM PST 24
Finished Jan 03 12:56:17 PM PST 24
Peak memory 246864 kb
Host smart-aaf5ef53-66ca-4b8a-8f3d-85ed3a2bc73d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165901470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.4165901470
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.3212327300
Short name T61
Test name
Test status
Simulation time 15886712736 ps
CPU time 41.42 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:55:57 PM PST 24
Peak memory 238652 kb
Host smart-e6a1fa76-6297-4670-b319-d618d64286ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212327300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.3212327300
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.2182935607
Short name T358
Test name
Test status
Simulation time 451559896 ps
CPU time 10.13 seconds
Started Jan 03 12:54:19 PM PST 24
Finished Jan 03 12:56:16 PM PST 24
Peak memory 246516 kb
Host smart-04762644-b59a-4d7f-9204-b5df0c0dd0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182935607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.2182935607
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.1550605742
Short name T79
Test name
Test status
Simulation time 540686781 ps
CPU time 3.58 seconds
Started Jan 03 12:56:10 PM PST 24
Finished Jan 03 12:57:23 PM PST 24
Peak memory 238352 kb
Host smart-b6dfc63e-c117-4551-b833-0336b7ab13a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550605742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.1550605742
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.2077516523
Short name T860
Test name
Test status
Simulation time 16754352349 ps
CPU time 115.37 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:57:06 PM PST 24
Peak memory 255048 kb
Host smart-e57374b0-0459-4ff5-9ec6-0d2c9461ccb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077516523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.2077516523
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.3301445783
Short name T943
Test name
Test status
Simulation time 921457672025 ps
CPU time 1290.61 seconds
Started Jan 03 12:53:54 PM PST 24
Finished Jan 03 01:16:55 PM PST 24
Peak memory 316692 kb
Host smart-777583db-be5e-4e40-96dd-4bdc7fb4bb2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301445783 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.3301445783
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.3085665552
Short name T1009
Test name
Test status
Simulation time 283337032 ps
CPU time 3.81 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 241092 kb
Host smart-d6c6dcf3-00ae-48d5-9dbe-3079b3130062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085665552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.3085665552
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.4090573084
Short name T76
Test name
Test status
Simulation time 599387275 ps
CPU time 4.02 seconds
Started Jan 03 12:56:19 PM PST 24
Finished Jan 03 12:57:33 PM PST 24
Peak memory 238496 kb
Host smart-c6e48540-a3c1-4811-ba62-8341d11cafa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090573084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.4090573084
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.3124087802
Short name T77
Test name
Test status
Simulation time 1673949713 ps
CPU time 3.97 seconds
Started Jan 03 12:56:38 PM PST 24
Finished Jan 03 12:57:52 PM PST 24
Peak memory 240364 kb
Host smart-e8d40695-9b69-4cd0-abf1-e220b1675fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124087802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.3124087802
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.3761562253
Short name T94
Test name
Test status
Simulation time 879301952 ps
CPU time 7.24 seconds
Started Jan 03 12:53:28 PM PST 24
Finished Jan 03 12:54:28 PM PST 24
Peak memory 238512 kb
Host smart-ab898d7d-4ccd-46de-a144-96c5969841bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761562253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
3761562253
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.960928920
Short name T369
Test name
Test status
Simulation time 276597230 ps
CPU time 5.79 seconds
Started Jan 03 12:53:17 PM PST 24
Finished Jan 03 12:54:27 PM PST 24
Peak memory 243640 kb
Host smart-00d7fcc5-250a-4033-87ef-263d6109d452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960928920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.960928920
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.3508670798
Short name T202
Test name
Test status
Simulation time 621253735 ps
CPU time 4.1 seconds
Started Jan 03 12:56:04 PM PST 24
Finished Jan 03 12:57:17 PM PST 24
Peak memory 242960 kb
Host smart-8af1802a-c0ac-4b96-9cf7-66617e247d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508670798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.3508670798
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.783560
Short name T1209
Test name
Test status
Simulation time 4379165283 ps
CPU time 9.93 seconds
Started Jan 03 12:32:58 PM PST 24
Finished Jan 03 12:35:00 PM PST 24
Peak memory 229572 kb
Host smart-3e9f6689-5c33-49cb-8fb0-bd8d32530110
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.783560
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.393574554
Short name T1199
Test name
Test status
Simulation time 146538465 ps
CPU time 1.54 seconds
Started Jan 03 12:32:48 PM PST 24
Finished Jan 03 12:34:17 PM PST 24
Peak memory 229396 kb
Host smart-c79d9c95-c764-4615-bca3-d4279588ca68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393574554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.393574554
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.4243328328
Short name T1143
Test name
Test status
Simulation time 37852810 ps
CPU time 1.27 seconds
Started Jan 03 12:33:37 PM PST 24
Finished Jan 03 12:35:00 PM PST 24
Peak memory 229456 kb
Host smart-defe5035-f5ce-4f73-a39a-9433fc4e64dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243328328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.4243328328
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.672913743
Short name T1193
Test name
Test status
Simulation time 38677659 ps
CPU time 1.3 seconds
Started Jan 03 12:32:40 PM PST 24
Finished Jan 03 12:34:08 PM PST 24
Peak memory 229180 kb
Host smart-d01d4873-2b30-48cc-b75a-63d08cdafbfc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672913743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.
672913743
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1603092668
Short name T269
Test name
Test status
Simulation time 194528752 ps
CPU time 3 seconds
Started Jan 03 12:32:40 PM PST 24
Finished Jan 03 12:34:38 PM PST 24
Peak memory 229448 kb
Host smart-b7e918b2-490b-4b85-8f8b-260a556d2f00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603092668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.1603092668
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1189935046
Short name T1195
Test name
Test status
Simulation time 88796960 ps
CPU time 3.11 seconds
Started Jan 03 12:33:10 PM PST 24
Finished Jan 03 12:34:28 PM PST 24
Peak memory 242052 kb
Host smart-b4fb7ef7-b2af-4e1f-b89d-e013cdb839b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189935046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.1189935046
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1533833182
Short name T300
Test name
Test status
Simulation time 1259133752 ps
CPU time 17.74 seconds
Started Jan 03 12:32:42 PM PST 24
Finished Jan 03 12:34:45 PM PST 24
Peak memory 229460 kb
Host smart-e9cab811-eae9-4925-96fe-f6b3a85ce15f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533833182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.1533833182
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2583505367
Short name T1208
Test name
Test status
Simulation time 216409237 ps
CPU time 3.86 seconds
Started Jan 03 12:32:46 PM PST 24
Finished Jan 03 12:34:26 PM PST 24
Peak memory 229456 kb
Host smart-11b2468a-6549-47de-b4bd-0632555ef579
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583505367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.2583505367
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.291243627
Short name T237
Test name
Test status
Simulation time 250602318 ps
CPU time 5.61 seconds
Started Jan 03 12:32:58 PM PST 24
Finished Jan 03 12:34:47 PM PST 24
Peak memory 229448 kb
Host smart-5fa5f531-dba0-4d12-a56f-7d03fa0c8313
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291243627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_b
ash.291243627
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.683597570
Short name T1137
Test name
Test status
Simulation time 181507827 ps
CPU time 2.07 seconds
Started Jan 03 12:35:00 PM PST 24
Finished Jan 03 12:36:31 PM PST 24
Peak memory 229212 kb
Host smart-f4514e1e-c72d-45d6-9339-df8b34b2a2df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683597570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_re
set.683597570
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.4195730886
Short name T170
Test name
Test status
Simulation time 101361551 ps
CPU time 2.74 seconds
Started Jan 03 12:32:56 PM PST 24
Finished Jan 03 12:34:25 PM PST 24
Peak memory 237772 kb
Host smart-2c1007cd-7f68-4002-962d-a77934a2704c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195730886 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.4195730886
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1391143996
Short name T209
Test name
Test status
Simulation time 149538361 ps
CPU time 1.5 seconds
Started Jan 03 12:35:20 PM PST 24
Finished Jan 03 12:36:58 PM PST 24
Peak memory 229088 kb
Host smart-9afb353f-a59f-4638-bc38-8f50bebe842d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391143996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1391143996
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.94000512
Short name T1200
Test name
Test status
Simulation time 100380349 ps
CPU time 1.26 seconds
Started Jan 03 12:33:03 PM PST 24
Finished Jan 03 12:34:52 PM PST 24
Peak memory 229140 kb
Host smart-b85944b3-466d-4e61-963a-2317bc42c897
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94000512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.94000512
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.1060811717
Short name T1181
Test name
Test status
Simulation time 60470854 ps
CPU time 1.34 seconds
Started Jan 03 12:33:05 PM PST 24
Finished Jan 03 12:34:53 PM PST 24
Peak memory 229088 kb
Host smart-72b9f530-6a20-404a-8aeb-2e928cd407c1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060811717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.1060811717
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3999741354
Short name T1159
Test name
Test status
Simulation time 82828668 ps
CPU time 2.65 seconds
Started Jan 03 12:32:25 PM PST 24
Finished Jan 03 12:34:08 PM PST 24
Peak memory 237668 kb
Host smart-91700f17-8c9a-4224-802d-a59f1e6a3b92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999741354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.3999741354
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2907128769
Short name T1180
Test name
Test status
Simulation time 1486275480 ps
CPU time 3.12 seconds
Started Jan 03 12:33:27 PM PST 24
Finished Jan 03 12:34:54 PM PST 24
Peak memory 237800 kb
Host smart-c3a73ad0-8e3e-47bf-b7e6-cbdc37a3424c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907128769 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.2907128769
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.890572897
Short name T245
Test name
Test status
Simulation time 626028528 ps
CPU time 1.93 seconds
Started Jan 03 12:34:49 PM PST 24
Finished Jan 03 12:36:00 PM PST 24
Peak memory 229388 kb
Host smart-37c3e333-be66-44f9-b934-e83fa4d40460
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890572897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.890572897
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.3503422745
Short name T1136
Test name
Test status
Simulation time 39054517 ps
CPU time 1.31 seconds
Started Jan 03 12:46:59 PM PST 24
Finished Jan 03 12:48:03 PM PST 24
Peak memory 229420 kb
Host smart-3fd24b1d-c9f2-4549-83c8-b39b5216826b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503422745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.3503422745
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3958598872
Short name T1211
Test name
Test status
Simulation time 93452186 ps
CPU time 2.39 seconds
Started Jan 03 12:36:34 PM PST 24
Finished Jan 03 12:38:03 PM PST 24
Peak memory 228652 kb
Host smart-f25bc777-d40c-4ceb-b0ef-fde088edccd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958598872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.3958598872
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3881777903
Short name T1168
Test name
Test status
Simulation time 329413998 ps
CPU time 6.22 seconds
Started Jan 03 12:32:58 PM PST 24
Finished Jan 03 12:34:34 PM PST 24
Peak memory 237680 kb
Host smart-3fd806eb-bfaf-4084-9423-ddb717328b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881777903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3881777903
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3705767196
Short name T1218
Test name
Test status
Simulation time 186187296 ps
CPU time 2.09 seconds
Started Jan 03 12:33:39 PM PST 24
Finished Jan 03 12:35:09 PM PST 24
Peak memory 237716 kb
Host smart-9a28c6d2-3af2-4a43-b7bb-6211d7287922
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705767196 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.3705767196
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.800969001
Short name T1206
Test name
Test status
Simulation time 65861803 ps
CPU time 1.36 seconds
Started Jan 03 12:33:21 PM PST 24
Finished Jan 03 12:34:45 PM PST 24
Peak memory 229448 kb
Host smart-83e540d8-b88c-4daa-9db5-bf84f826e8fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800969001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.800969001
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.3347816229
Short name T270
Test name
Test status
Simulation time 61459726 ps
CPU time 1.3 seconds
Started Jan 03 12:33:01 PM PST 24
Finished Jan 03 12:34:53 PM PST 24
Peak memory 229116 kb
Host smart-f3fefdf7-0e1b-41ba-8c47-e3281bce4f80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347816229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.3347816229
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1352698886
Short name T173
Test name
Test status
Simulation time 1030558925 ps
CPU time 4.37 seconds
Started Jan 03 12:34:43 PM PST 24
Finished Jan 03 12:36:14 PM PST 24
Peak memory 237488 kb
Host smart-434052b4-505f-495f-983a-fa8a5ba16c87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352698886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.1352698886
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3503246192
Short name T297
Test name
Test status
Simulation time 4637952373 ps
CPU time 16.38 seconds
Started Jan 03 12:34:44 PM PST 24
Finished Jan 03 12:36:31 PM PST 24
Peak memory 229740 kb
Host smart-961571ec-3532-4875-8808-c82447472caa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503246192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.3503246192
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2590156354
Short name T172
Test name
Test status
Simulation time 194631855 ps
CPU time 3.11 seconds
Started Jan 03 12:33:12 PM PST 24
Finished Jan 03 12:34:28 PM PST 24
Peak memory 245928 kb
Host smart-d2eef924-829d-4a80-91e9-e31afaa3f095
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590156354 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.2590156354
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2831623579
Short name T246
Test name
Test status
Simulation time 44625634 ps
CPU time 1.59 seconds
Started Jan 03 12:33:06 PM PST 24
Finished Jan 03 12:34:34 PM PST 24
Peak memory 229456 kb
Host smart-31445552-6a85-4260-ae01-73587507ed43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831623579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.2831623579
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.3668830760
Short name T1165
Test name
Test status
Simulation time 588282854 ps
CPU time 1.81 seconds
Started Jan 03 12:33:44 PM PST 24
Finished Jan 03 12:35:13 PM PST 24
Peak memory 229092 kb
Host smart-e0b62c8e-26da-44df-b350-161423fe2cb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668830760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.3668830760
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.429827247
Short name T1202
Test name
Test status
Simulation time 120927895 ps
CPU time 2.72 seconds
Started Jan 03 12:32:35 PM PST 24
Finished Jan 03 12:34:12 PM PST 24
Peak memory 229440 kb
Host smart-b9d82773-2ed5-4f8b-acea-41537d51f921
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429827247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_c
trl_same_csr_outstanding.429827247
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3231021795
Short name T1177
Test name
Test status
Simulation time 369597520 ps
CPU time 6.18 seconds
Started Jan 03 12:35:18 PM PST 24
Finished Jan 03 12:36:51 PM PST 24
Peak memory 237456 kb
Host smart-68e9e594-39a5-4e2d-8cc7-e3a6a115d460
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231021795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.3231021795
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3322277816
Short name T1174
Test name
Test status
Simulation time 104822520 ps
CPU time 2.59 seconds
Started Jan 03 12:33:27 PM PST 24
Finished Jan 03 12:34:43 PM PST 24
Peak memory 237692 kb
Host smart-cb0b27d7-7e90-4443-8690-3f8922aceb1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322277816 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.3322277816
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.424924452
Short name T1179
Test name
Test status
Simulation time 74098915 ps
CPU time 2.31 seconds
Started Jan 03 12:33:34 PM PST 24
Finished Jan 03 12:35:02 PM PST 24
Peak memory 229524 kb
Host smart-4299261d-9cf5-401f-ad87-f808cd870c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424924452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_c
trl_same_csr_outstanding.424924452
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.994866504
Short name T169
Test name
Test status
Simulation time 310225382 ps
CPU time 3.24 seconds
Started Jan 03 12:33:30 PM PST 24
Finished Jan 03 12:34:42 PM PST 24
Peak memory 237716 kb
Host smart-d6eba16f-d270-44ac-8e02-53b93b368336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994866504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.994866504
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.630657926
Short name T302
Test name
Test status
Simulation time 2113680651 ps
CPU time 9.7 seconds
Started Jan 03 12:33:21 PM PST 24
Finished Jan 03 12:34:50 PM PST 24
Peak memory 229820 kb
Host smart-12b829aa-c27c-4084-9dc6-a72400826e38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630657926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_in
tg_err.630657926
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2101724632
Short name T1153
Test name
Test status
Simulation time 250620961 ps
CPU time 3.04 seconds
Started Jan 03 12:32:57 PM PST 24
Finished Jan 03 12:34:59 PM PST 24
Peak memory 237772 kb
Host smart-ef0b5e23-89a4-4eda-ad71-d7a59a9089b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101724632 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.2101724632
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3710174388
Short name T1187
Test name
Test status
Simulation time 129268340 ps
CPU time 1.32 seconds
Started Jan 03 12:33:32 PM PST 24
Finished Jan 03 12:34:43 PM PST 24
Peak memory 229200 kb
Host smart-cd9b5cd0-fd44-4bc7-b2fd-1f5533109cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710174388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.3710174388
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.305566439
Short name T1171
Test name
Test status
Simulation time 1463702961 ps
CPU time 3.99 seconds
Started Jan 03 12:32:51 PM PST 24
Finished Jan 03 12:34:16 PM PST 24
Peak memory 237728 kb
Host smart-c0e9cf96-b93c-4046-a01b-0625acd59aa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305566439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.305566439
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3167291643
Short name T1150
Test name
Test status
Simulation time 129513190 ps
CPU time 2.03 seconds
Started Jan 03 12:33:15 PM PST 24
Finished Jan 03 12:34:43 PM PST 24
Peak memory 237724 kb
Host smart-30216669-a437-4814-b65c-e8f2a0f2fd4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167291643 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.3167291643
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.579879185
Short name T1182
Test name
Test status
Simulation time 79339203 ps
CPU time 2.05 seconds
Started Jan 03 12:33:13 PM PST 24
Finished Jan 03 12:34:34 PM PST 24
Peak memory 229424 kb
Host smart-656c271a-6501-4218-a5b9-f7de47bddbf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579879185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_c
trl_same_csr_outstanding.579879185
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1320737148
Short name T1140
Test name
Test status
Simulation time 151203261 ps
CPU time 4.87 seconds
Started Jan 03 12:33:31 PM PST 24
Finished Jan 03 12:34:48 PM PST 24
Peak memory 245900 kb
Host smart-ef669fe9-aeeb-491b-8756-8e4d6b902a52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320737148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1320737148
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3502446553
Short name T306
Test name
Test status
Simulation time 691108720 ps
CPU time 8.96 seconds
Started Jan 03 12:33:05 PM PST 24
Finished Jan 03 12:34:59 PM PST 24
Peak memory 229616 kb
Host smart-19a2d126-5278-487b-bdc3-cce216344ef0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502446553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.3502446553
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1440272525
Short name T1213
Test name
Test status
Simulation time 134124587 ps
CPU time 1.39 seconds
Started Jan 03 12:33:24 PM PST 24
Finished Jan 03 12:34:49 PM PST 24
Peak memory 229300 kb
Host smart-5635b01f-6253-4e59-b7c6-f11e4e4efdd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440272525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.1440272525
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.2227862687
Short name T1157
Test name
Test status
Simulation time 43862164 ps
CPU time 1.35 seconds
Started Jan 03 12:33:47 PM PST 24
Finished Jan 03 12:35:25 PM PST 24
Peak memory 229300 kb
Host smart-72265721-9beb-404d-b667-dafd2254e446
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227862687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.2227862687
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3151511521
Short name T1198
Test name
Test status
Simulation time 1533676940 ps
CPU time 3.98 seconds
Started Jan 03 12:33:27 PM PST 24
Finished Jan 03 12:34:54 PM PST 24
Peak memory 237596 kb
Host smart-f1ccede6-1af1-4da5-b57c-a2519b98ea6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151511521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.3151511521
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.425007003
Short name T1173
Test name
Test status
Simulation time 102401671 ps
CPU time 3.37 seconds
Started Jan 03 12:33:35 PM PST 24
Finished Jan 03 12:35:04 PM PST 24
Peak memory 246052 kb
Host smart-ac807107-b75c-4aec-adad-d5cf53f72f39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425007003 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.425007003
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2122196640
Short name T1194
Test name
Test status
Simulation time 41925766 ps
CPU time 1.43 seconds
Started Jan 03 12:32:52 PM PST 24
Finished Jan 03 12:34:13 PM PST 24
Peak memory 229448 kb
Host smart-593f6c59-3dd2-4e5c-a2fd-b5796b157352
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122196640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.2122196640
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2378233963
Short name T1145
Test name
Test status
Simulation time 525710553 ps
CPU time 1.59 seconds
Started Jan 03 12:33:11 PM PST 24
Finished Jan 03 12:34:46 PM PST 24
Peak memory 229076 kb
Host smart-64438388-5212-4727-98c7-b9669c25b902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378233963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.2378233963
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1359651013
Short name T1184
Test name
Test status
Simulation time 86237390 ps
CPU time 2.42 seconds
Started Jan 03 12:33:02 PM PST 24
Finished Jan 03 12:35:04 PM PST 24
Peak memory 229608 kb
Host smart-1b1abf85-e48c-4459-b17e-e2a9afca74ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359651013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.1359651013
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.976672619
Short name T1134
Test name
Test status
Simulation time 320602813 ps
CPU time 3.3 seconds
Started Jan 03 12:32:56 PM PST 24
Finished Jan 03 12:34:38 PM PST 24
Peak memory 237612 kb
Host smart-37bf9b19-b486-4147-b81f-7d760d6892c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976672619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.976672619
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3763978354
Short name T303
Test name
Test status
Simulation time 1508247554 ps
CPU time 10.54 seconds
Started Jan 03 12:32:56 PM PST 24
Finished Jan 03 12:34:24 PM PST 24
Peak memory 229488 kb
Host smart-e322e795-18b3-400d-8903-a683297e4820
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763978354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.3763978354
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1415151611
Short name T1146
Test name
Test status
Simulation time 389167185 ps
CPU time 2.71 seconds
Started Jan 03 12:33:28 PM PST 24
Finished Jan 03 12:35:02 PM PST 24
Peak memory 237752 kb
Host smart-18b1ab84-89e9-4fe9-a1bf-86b5d958ec61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415151611 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.1415151611
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.423536577
Short name T243
Test name
Test status
Simulation time 60000877 ps
CPU time 1.39 seconds
Started Jan 03 12:37:09 PM PST 24
Finished Jan 03 12:38:30 PM PST 24
Peak memory 229280 kb
Host smart-03a5b16c-592d-453f-8766-19c247fe1dc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423536577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.423536577
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2898646175
Short name T1167
Test name
Test status
Simulation time 80434531 ps
CPU time 1.33 seconds
Started Jan 03 12:33:16 PM PST 24
Finished Jan 03 12:34:38 PM PST 24
Peak memory 229088 kb
Host smart-0d6c265d-af73-49ff-8c16-63702d92b01b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898646175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.2898646175
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1741998471
Short name T267
Test name
Test status
Simulation time 285712516 ps
CPU time 2.39 seconds
Started Jan 03 12:34:43 PM PST 24
Finished Jan 03 12:35:59 PM PST 24
Peak memory 228756 kb
Host smart-3f220eac-824d-4cc1-8a23-975d79effdca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741998471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.1741998471
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.4142223213
Short name T1207
Test name
Test status
Simulation time 1928832038 ps
CPU time 5.64 seconds
Started Jan 03 12:33:12 PM PST 24
Finished Jan 03 12:35:01 PM PST 24
Peak memory 241752 kb
Host smart-a317abed-bca2-4a69-b295-000ba4372abc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142223213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.4142223213
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1867122616
Short name T1203
Test name
Test status
Simulation time 262741478 ps
CPU time 2.47 seconds
Started Jan 03 12:33:07 PM PST 24
Finished Jan 03 12:34:32 PM PST 24
Peak memory 237804 kb
Host smart-443774c4-b122-4962-a986-f9a23eda2896
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867122616 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.1867122616
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3376541168
Short name T1223
Test name
Test status
Simulation time 35667008 ps
CPU time 1.37 seconds
Started Jan 03 12:33:42 PM PST 24
Finished Jan 03 12:35:10 PM PST 24
Peak memory 229356 kb
Host smart-dcb28822-c454-47f0-a7a3-2d12f059ad53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376541168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.3376541168
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.2148050707
Short name T1138
Test name
Test status
Simulation time 43784947 ps
CPU time 1.35 seconds
Started Jan 03 12:32:47 PM PST 24
Finished Jan 03 12:34:10 PM PST 24
Peak memory 229124 kb
Host smart-72d46550-900d-462e-9eca-d1a431062e13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148050707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.2148050707
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.2219277492
Short name T212
Test name
Test status
Simulation time 217129562 ps
CPU time 1.93 seconds
Started Jan 03 12:33:24 PM PST 24
Finished Jan 03 12:34:58 PM PST 24
Peak memory 229684 kb
Host smart-92aaf450-9f6d-437f-85ca-a892fd8ce056
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219277492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.2219277492
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.732735349
Short name T211
Test name
Test status
Simulation time 61891514 ps
CPU time 3.25 seconds
Started Jan 03 12:32:23 PM PST 24
Finished Jan 03 12:33:53 PM PST 24
Peak memory 229428 kb
Host smart-ae016016-d7d9-48fa-90a7-09c7afe4af15
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732735349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alias
ing.732735349
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.968944665
Short name T1166
Test name
Test status
Simulation time 1894559899 ps
CPU time 9.63 seconds
Started Jan 03 12:35:04 PM PST 24
Finished Jan 03 12:36:29 PM PST 24
Peak memory 229160 kb
Host smart-663a25cb-2707-4405-91a1-5ee1eeefa422
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968944665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_b
ash.968944665
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1834852486
Short name T1205
Test name
Test status
Simulation time 93452139 ps
CPU time 1.98 seconds
Started Jan 03 12:34:27 PM PST 24
Finished Jan 03 12:36:13 PM PST 24
Peak memory 228332 kb
Host smart-ba83502e-f325-4730-9196-7ae0e8f7d741
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834852486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.1834852486
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.3499052159
Short name T1170
Test name
Test status
Simulation time 41429569 ps
CPU time 1.55 seconds
Started Jan 03 12:32:33 PM PST 24
Finished Jan 03 12:34:04 PM PST 24
Peak memory 229348 kb
Host smart-d0015490-47ff-4675-9ff4-4c32d59c8312
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499052159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.3499052159
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.171211487
Short name T1197
Test name
Test status
Simulation time 36045223 ps
CPU time 1.29 seconds
Started Jan 03 12:32:55 PM PST 24
Finished Jan 03 12:34:48 PM PST 24
Peak memory 229172 kb
Host smart-f980cdc2-703a-49e9-bbfa-49ba88c09d47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171211487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.171211487
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1499650558
Short name T1131
Test name
Test status
Simulation time 38544441 ps
CPU time 1.2 seconds
Started Jan 03 12:32:49 PM PST 24
Finished Jan 03 12:34:49 PM PST 24
Peak memory 229188 kb
Host smart-d3d68bef-fe3a-455e-8e26-1354d03aed6c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499650558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.1499650558
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.977440936
Short name T1191
Test name
Test status
Simulation time 129689832 ps
CPU time 1.28 seconds
Started Jan 03 12:35:35 PM PST 24
Finished Jan 03 12:37:09 PM PST 24
Peak memory 228916 kb
Host smart-a7d29972-e4fb-4761-b27f-8f8454dedd50
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977440936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.
977440936
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.733528363
Short name T1221
Test name
Test status
Simulation time 169125715 ps
CPU time 1.57 seconds
Started Jan 03 12:32:50 PM PST 24
Finished Jan 03 12:34:57 PM PST 24
Peak memory 229532 kb
Host smart-a8291cba-0b9c-4aeb-a6b8-33233f5dd14e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733528363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ct
rl_same_csr_outstanding.733528363
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3070543237
Short name T1178
Test name
Test status
Simulation time 516752008 ps
CPU time 4.89 seconds
Started Jan 03 12:33:05 PM PST 24
Finished Jan 03 12:34:25 PM PST 24
Peak memory 237800 kb
Host smart-b57153c1-69d6-4ea2-9aa4-57a6684a9a65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070543237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3070543237
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.1678838078
Short name T244
Test name
Test status
Simulation time 77405895 ps
CPU time 1.48 seconds
Started Jan 03 12:36:34 PM PST 24
Finished Jan 03 12:38:07 PM PST 24
Peak memory 228768 kb
Host smart-c223b50f-e2f0-46c9-85b5-fe2c9bd79721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678838078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.1678838078
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3429095898
Short name T1201
Test name
Test status
Simulation time 65073203 ps
CPU time 1.33 seconds
Started Jan 03 12:36:31 PM PST 24
Finished Jan 03 12:37:58 PM PST 24
Peak memory 228372 kb
Host smart-fee3d623-855d-440d-a90c-75a83b205ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429095898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.3429095898
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2119683492
Short name T360
Test name
Test status
Simulation time 549644658 ps
CPU time 1.51 seconds
Started Jan 03 12:34:43 PM PST 24
Finished Jan 03 12:36:20 PM PST 24
Peak memory 229096 kb
Host smart-587ed023-69d4-413a-b683-e8a8bc676da0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119683492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.2119683492
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3612858889
Short name T1139
Test name
Test status
Simulation time 36256737 ps
CPU time 1.24 seconds
Started Jan 03 12:35:03 PM PST 24
Finished Jan 03 12:36:20 PM PST 24
Peak memory 228912 kb
Host smart-6ecd61c1-d1e8-4dfa-b1c3-3e837a2c4dfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612858889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3612858889
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.1474801955
Short name T1160
Test name
Test status
Simulation time 147067342 ps
CPU time 1.35 seconds
Started Jan 03 12:33:29 PM PST 24
Finished Jan 03 12:35:07 PM PST 24
Peak memory 229288 kb
Host smart-23a471b9-b6f5-4d12-9368-25905457acdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474801955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.1474801955
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1659056623
Short name T1216
Test name
Test status
Simulation time 47654451 ps
CPU time 1.25 seconds
Started Jan 03 12:33:05 PM PST 24
Finished Jan 03 12:34:21 PM PST 24
Peak memory 229192 kb
Host smart-ba37e0fa-9a28-4708-8bc6-9b40dda5f953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659056623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.1659056623
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.3925323324
Short name T1222
Test name
Test status
Simulation time 589859625 ps
CPU time 2.24 seconds
Started Jan 03 12:32:48 PM PST 24
Finished Jan 03 12:34:43 PM PST 24
Peak memory 229272 kb
Host smart-604641a5-2ea3-41ab-b3d9-c23ba295eeb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925323324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.3925323324
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.4030986618
Short name T1151
Test name
Test status
Simulation time 146662942 ps
CPU time 1.41 seconds
Started Jan 03 12:32:59 PM PST 24
Finished Jan 03 12:34:27 PM PST 24
Peak memory 229208 kb
Host smart-91660c4f-dd32-4d55-93f7-70f99f9587b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030986618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.4030986618
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2723855173
Short name T1154
Test name
Test status
Simulation time 130730622 ps
CPU time 1.47 seconds
Started Jan 03 12:32:35 PM PST 24
Finished Jan 03 12:34:14 PM PST 24
Peak memory 229420 kb
Host smart-d20b0510-3833-4e1c-a9b2-26b8c4ab690f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723855173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.2723855173
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3817495435
Short name T249
Test name
Test status
Simulation time 90868758 ps
CPU time 2.22 seconds
Started Jan 03 12:35:06 PM PST 24
Finished Jan 03 12:36:44 PM PST 24
Peak memory 229224 kb
Host smart-57c9adea-1858-4bb4-be25-b374b913642a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817495435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.3817495435
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1536119465
Short name T239
Test name
Test status
Simulation time 1016142008 ps
CPU time 2.47 seconds
Started Jan 03 12:32:54 PM PST 24
Finished Jan 03 12:34:30 PM PST 24
Peak memory 229472 kb
Host smart-e01fee89-7a4b-431f-8859-bdd4482ee67e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536119465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.1536119465
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1088257440
Short name T167
Test name
Test status
Simulation time 64701438 ps
CPU time 1.73 seconds
Started Jan 03 12:33:42 PM PST 24
Finished Jan 03 12:35:11 PM PST 24
Peak memory 237800 kb
Host smart-f75a2cf0-def2-451f-b5b3-a906902e4d82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088257440 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.1088257440
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.645206694
Short name T1219
Test name
Test status
Simulation time 165242946 ps
CPU time 1.59 seconds
Started Jan 03 12:32:34 PM PST 24
Finished Jan 03 12:34:14 PM PST 24
Peak memory 229372 kb
Host smart-415dc802-2e38-4a69-8683-10392b32f3db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645206694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.645206694
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.2126479245
Short name T1152
Test name
Test status
Simulation time 38379408 ps
CPU time 1.33 seconds
Started Jan 03 12:32:46 PM PST 24
Finished Jan 03 12:34:28 PM PST 24
Peak memory 229368 kb
Host smart-8ea250c0-e68c-40a8-af8c-6d89eb7c328c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126479245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.2126479245
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2835767418
Short name T1132
Test name
Test status
Simulation time 37686344 ps
CPU time 1.23 seconds
Started Jan 03 12:32:42 PM PST 24
Finished Jan 03 12:34:13 PM PST 24
Peak memory 229108 kb
Host smart-3278598d-3a12-4d45-b86f-02ce3cb0a044
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835767418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.2835767418
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.4046278664
Short name T1189
Test name
Test status
Simulation time 493337905 ps
CPU time 1.37 seconds
Started Jan 03 12:32:28 PM PST 24
Finished Jan 03 12:34:09 PM PST 24
Peak memory 229140 kb
Host smart-c87ca3aa-16d9-4119-a572-274fef0065df
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046278664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.4046278664
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.901167169
Short name T1217
Test name
Test status
Simulation time 869935812 ps
CPU time 2.08 seconds
Started Jan 03 12:33:44 PM PST 24
Finished Jan 03 12:35:24 PM PST 24
Peak memory 229400 kb
Host smart-c8cdef03-a3a4-4c25-910b-720a78a1a095
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901167169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ct
rl_same_csr_outstanding.901167169
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2893112487
Short name T1225
Test name
Test status
Simulation time 1178986573 ps
CPU time 15.64 seconds
Started Jan 03 12:32:34 PM PST 24
Finished Jan 03 12:34:16 PM PST 24
Peak memory 229572 kb
Host smart-750889d0-343b-4e58-93d5-f6636a4a9c39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893112487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.2893112487
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.3991344495
Short name T1162
Test name
Test status
Simulation time 511562667 ps
CPU time 1.45 seconds
Started Jan 03 12:33:25 PM PST 24
Finished Jan 03 12:35:01 PM PST 24
Peak memory 229472 kb
Host smart-c62f37bc-f411-4478-a82d-c9da96208599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991344495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.3991344495
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3267921163
Short name T177
Test name
Test status
Simulation time 73350435 ps
CPU time 1.37 seconds
Started Jan 03 12:32:52 PM PST 24
Finished Jan 03 12:34:21 PM PST 24
Peak memory 229452 kb
Host smart-28a4341a-6d60-4bbd-9a77-e0e13bda3a27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267921163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.3267921163
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.1406708950
Short name T1176
Test name
Test status
Simulation time 48372169 ps
CPU time 1.32 seconds
Started Jan 03 12:32:58 PM PST 24
Finished Jan 03 12:34:45 PM PST 24
Peak memory 229104 kb
Host smart-205bfc32-7393-4358-a5e1-1bf938fe8089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406708950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.1406708950
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.988936785
Short name T240
Test name
Test status
Simulation time 73666517 ps
CPU time 1.35 seconds
Started Jan 03 12:34:53 PM PST 24
Finished Jan 03 12:36:28 PM PST 24
Peak memory 228892 kb
Host smart-501d68b2-f039-4a11-b9c6-a6d9704fea5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988936785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.988936785
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3731150517
Short name T1158
Test name
Test status
Simulation time 39834033 ps
CPU time 1.34 seconds
Started Jan 03 12:33:33 PM PST 24
Finished Jan 03 12:34:48 PM PST 24
Peak memory 229208 kb
Host smart-53853376-32a7-4bf9-ba68-e7ffa5011e7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731150517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.3731150517
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.772038977
Short name T1204
Test name
Test status
Simulation time 142109504 ps
CPU time 1.41 seconds
Started Jan 03 12:34:20 PM PST 24
Finished Jan 03 12:36:10 PM PST 24
Peak memory 228876 kb
Host smart-7f09c113-25bf-40cb-8730-c453359099ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772038977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.772038977
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.2343205814
Short name T276
Test name
Test status
Simulation time 123219566 ps
CPU time 1.39 seconds
Started Jan 03 12:34:35 PM PST 24
Finished Jan 03 12:35:49 PM PST 24
Peak memory 228332 kb
Host smart-f43a2a62-ab93-4c26-96ce-8fe7ecfa6926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343205814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.2343205814
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.419060532
Short name T1175
Test name
Test status
Simulation time 145009433 ps
CPU time 1.4 seconds
Started Jan 03 12:33:16 PM PST 24
Finished Jan 03 12:34:28 PM PST 24
Peak memory 229096 kb
Host smart-e9842aa3-2073-4de1-b5b3-17f40f96cf39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419060532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.419060532
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.4294402249
Short name T238
Test name
Test status
Simulation time 275290982 ps
CPU time 2.79 seconds
Started Jan 03 12:32:48 PM PST 24
Finished Jan 03 12:34:33 PM PST 24
Peak memory 229452 kb
Host smart-5d009ddc-61eb-44d0-8565-45b2a12aa733
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294402249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.4294402249
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3990708400
Short name T241
Test name
Test status
Simulation time 157939871 ps
CPU time 4 seconds
Started Jan 03 12:33:19 PM PST 24
Finished Jan 03 12:34:38 PM PST 24
Peak memory 229508 kb
Host smart-aca7263c-0ed9-4ce2-b827-67c61d6ce9a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990708400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.3990708400
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.901956963
Short name T1183
Test name
Test status
Simulation time 196464902 ps
CPU time 2.29 seconds
Started Jan 03 12:33:19 PM PST 24
Finished Jan 03 12:34:56 PM PST 24
Peak memory 229504 kb
Host smart-8206f9cb-8b91-4127-bdd8-da9ab97f058e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901956963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_re
set.901956963
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.1642204106
Short name T174
Test name
Test status
Simulation time 90082956 ps
CPU time 2.16 seconds
Started Jan 03 12:33:10 PM PST 24
Finished Jan 03 12:34:27 PM PST 24
Peak memory 237796 kb
Host smart-c45bf4a8-eee3-4c44-85e1-9b17725c45cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642204106 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.1642204106
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.4077350551
Short name T1172
Test name
Test status
Simulation time 71780043 ps
CPU time 1.54 seconds
Started Jan 03 12:33:44 PM PST 24
Finished Jan 03 12:35:00 PM PST 24
Peak memory 229476 kb
Host smart-4ad8c448-8816-4fdb-a741-d5452ce12846
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077350551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.4077350551
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1569691666
Short name T1149
Test name
Test status
Simulation time 38778631 ps
CPU time 1.26 seconds
Started Jan 03 12:35:27 PM PST 24
Finished Jan 03 12:37:01 PM PST 24
Peak memory 228932 kb
Host smart-fc0fe9be-4c28-4d22-8012-faa6242b92d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569691666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.1569691666
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2107781621
Short name T1224
Test name
Test status
Simulation time 516713365 ps
CPU time 2.08 seconds
Started Jan 03 12:35:03 PM PST 24
Finished Jan 03 12:36:46 PM PST 24
Peak memory 228968 kb
Host smart-bbc9dbeb-ee55-4983-811d-dc909b1b4e3e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107781621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.2107781621
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.71883248
Short name T1220
Test name
Test status
Simulation time 114359175 ps
CPU time 2.6 seconds
Started Jan 03 12:32:39 PM PST 24
Finished Jan 03 12:34:14 PM PST 24
Peak memory 229548 kb
Host smart-3547d724-650b-4e7a-8355-8f36bd4ff79c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71883248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_same_csr_outstanding.71883248
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.569829191
Short name T242
Test name
Test status
Simulation time 79258304 ps
CPU time 5.39 seconds
Started Jan 03 12:33:48 PM PST 24
Finished Jan 03 12:35:12 PM PST 24
Peak memory 237808 kb
Host smart-124898f8-ba52-4399-ae81-641916be5e14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569829191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.569829191
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2394719730
Short name T1196
Test name
Test status
Simulation time 139629200 ps
CPU time 1.42 seconds
Started Jan 03 12:33:08 PM PST 24
Finished Jan 03 12:34:46 PM PST 24
Peak memory 229092 kb
Host smart-ad723177-fce5-4d4c-9a07-65ec178d7c1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394719730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.2394719730
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.3096409789
Short name T274
Test name
Test status
Simulation time 41141729 ps
CPU time 1.32 seconds
Started Jan 03 12:33:15 PM PST 24
Finished Jan 03 12:34:43 PM PST 24
Peak memory 229096 kb
Host smart-36812835-e720-4a5a-83e2-8f0f55799830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096409789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.3096409789
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3417746724
Short name T1135
Test name
Test status
Simulation time 46856177 ps
CPU time 1.39 seconds
Started Jan 03 12:32:57 PM PST 24
Finished Jan 03 12:34:28 PM PST 24
Peak memory 229268 kb
Host smart-a571f071-3861-4be2-9e55-2f5b964a05db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417746724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.3417746724
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3245383511
Short name T1214
Test name
Test status
Simulation time 555224446 ps
CPU time 1.46 seconds
Started Jan 03 12:33:06 PM PST 24
Finished Jan 03 12:34:26 PM PST 24
Peak memory 229132 kb
Host smart-ba016894-da9e-44bf-9427-101b7ee3191e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245383511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.3245383511
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.3030824598
Short name T111
Test name
Test status
Simulation time 68958357 ps
CPU time 1.27 seconds
Started Jan 03 12:32:46 PM PST 24
Finished Jan 03 12:34:57 PM PST 24
Peak memory 229376 kb
Host smart-d3bc3d14-1bed-436c-a069-ab9dc2757d62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030824598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.3030824598
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.4053427906
Short name T1142
Test name
Test status
Simulation time 74743636 ps
CPU time 1.26 seconds
Started Jan 03 12:35:09 PM PST 24
Finished Jan 03 12:36:42 PM PST 24
Peak memory 228896 kb
Host smart-438393ca-285f-4cff-adcb-2cb8844f8df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053427906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.4053427906
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.3121761250
Short name T1148
Test name
Test status
Simulation time 142011405 ps
CPU time 1.35 seconds
Started Jan 03 12:33:12 PM PST 24
Finished Jan 03 12:34:43 PM PST 24
Peak memory 229156 kb
Host smart-627163ff-5d0e-4f34-bd27-88e96745b27d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121761250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.3121761250
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2699545192
Short name T175
Test name
Test status
Simulation time 35898652 ps
CPU time 1.24 seconds
Started Jan 03 12:33:10 PM PST 24
Finished Jan 03 12:34:30 PM PST 24
Peak memory 229216 kb
Host smart-4281620f-5894-4e39-ac8d-e92e395cf73c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699545192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.2699545192
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.1956569696
Short name T1188
Test name
Test status
Simulation time 75388944 ps
CPU time 1.38 seconds
Started Jan 03 12:34:43 PM PST 24
Finished Jan 03 12:36:28 PM PST 24
Peak memory 229052 kb
Host smart-c8ff76ac-dd9a-40b7-8f3d-e7429450f6f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956569696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.1956569696
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3033201994
Short name T1210
Test name
Test status
Simulation time 1072341709 ps
CPU time 2.57 seconds
Started Jan 03 12:33:24 PM PST 24
Finished Jan 03 12:34:46 PM PST 24
Peak memory 237728 kb
Host smart-bdfa626a-9152-47f8-a0a4-1c7fb43833bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033201994 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.3033201994
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1426856911
Short name T210
Test name
Test status
Simulation time 96869137 ps
CPU time 1.42 seconds
Started Jan 03 12:34:26 PM PST 24
Finished Jan 03 12:35:43 PM PST 24
Peak memory 228568 kb
Host smart-715022a5-94da-4565-9a7e-31eb44047d81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426856911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.1426856911
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.1969094210
Short name T1164
Test name
Test status
Simulation time 76008109 ps
CPU time 1.38 seconds
Started Jan 03 12:33:01 PM PST 24
Finished Jan 03 12:34:45 PM PST 24
Peak memory 229108 kb
Host smart-ca8ce66a-8e80-4536-b232-1ca04553becd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969094210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.1969094210
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1165390182
Short name T1155
Test name
Test status
Simulation time 60259422 ps
CPU time 1.86 seconds
Started Jan 03 12:33:32 PM PST 24
Finished Jan 03 12:34:44 PM PST 24
Peak memory 229488 kb
Host smart-5fb4792e-781b-4dac-b04d-a5691c6cac09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165390182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.1165390182
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2877428643
Short name T1226
Test name
Test status
Simulation time 154138379 ps
CPU time 4.86 seconds
Started Jan 03 12:35:04 PM PST 24
Finished Jan 03 12:36:25 PM PST 24
Peak memory 237396 kb
Host smart-d2d671c7-756a-46c5-aa28-ffe81ae65758
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877428643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.2877428643
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3862849414
Short name T1169
Test name
Test status
Simulation time 1274892117 ps
CPU time 15.94 seconds
Started Jan 03 12:32:52 PM PST 24
Finished Jan 03 12:34:28 PM PST 24
Peak memory 237816 kb
Host smart-5c07b073-a76f-4da6-8f61-3de51c7de622
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862849414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.3862849414
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.699241658
Short name T1141
Test name
Test status
Simulation time 177891423 ps
CPU time 2.3 seconds
Started Jan 03 12:35:25 PM PST 24
Finished Jan 03 12:36:58 PM PST 24
Peak memory 237532 kb
Host smart-27e6de60-aea9-40f3-a6dc-a0795197977b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699241658 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.699241658
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.1938050021
Short name T1161
Test name
Test status
Simulation time 633289913 ps
CPU time 2.22 seconds
Started Jan 03 12:33:24 PM PST 24
Finished Jan 03 12:34:58 PM PST 24
Peak memory 229520 kb
Host smart-f7deb118-faff-463b-b2ff-d42827bebd64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938050021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.1938050021
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2927009505
Short name T1186
Test name
Test status
Simulation time 38722265 ps
CPU time 1.3 seconds
Started Jan 03 12:33:24 PM PST 24
Finished Jan 03 12:35:01 PM PST 24
Peak memory 229140 kb
Host smart-2fc72590-1e67-4b90-ad0c-782b06fea75f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927009505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.2927009505
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1496915532
Short name T1192
Test name
Test status
Simulation time 128762712 ps
CPU time 2.33 seconds
Started Jan 03 12:34:27 PM PST 24
Finished Jan 03 12:35:48 PM PST 24
Peak memory 229076 kb
Host smart-89e679b2-88c7-4d9f-b02a-803bb2916ae1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496915532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.1496915532
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1097635736
Short name T1147
Test name
Test status
Simulation time 145914982 ps
CPU time 3.97 seconds
Started Jan 03 12:33:50 PM PST 24
Finished Jan 03 12:35:45 PM PST 24
Peak memory 237680 kb
Host smart-59b768df-edf0-43a6-8f94-3268a5052425
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097635736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.1097635736
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.3463625272
Short name T207
Test name
Test status
Simulation time 1214121811 ps
CPU time 15.45 seconds
Started Jan 03 12:33:03 PM PST 24
Finished Jan 03 12:34:50 PM PST 24
Peak memory 229756 kb
Host smart-c1b92a7b-2c05-4b95-ad7e-8485a854624c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463625272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.3463625272
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1501067393
Short name T1156
Test name
Test status
Simulation time 1024264629 ps
CPU time 2.84 seconds
Started Jan 03 12:32:34 PM PST 24
Finished Jan 03 12:33:59 PM PST 24
Peak memory 237668 kb
Host smart-94147292-593d-47b1-8fff-8f1289af4068
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501067393 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.1501067393
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.3927110581
Short name T1190
Test name
Test status
Simulation time 542035773 ps
CPU time 1.5 seconds
Started Jan 03 12:37:05 PM PST 24
Finished Jan 03 12:38:14 PM PST 24
Peak memory 229108 kb
Host smart-0979b6eb-1182-465c-9132-1f60ebaa927c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927110581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3927110581
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1745720475
Short name T171
Test name
Test status
Simulation time 266526334 ps
CPU time 3.29 seconds
Started Jan 03 12:33:02 PM PST 24
Finished Jan 03 12:34:33 PM PST 24
Peak memory 229460 kb
Host smart-229bbcf7-2619-41f0-8978-5c8ba93690e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745720475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.1745720475
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3407502729
Short name T1163
Test name
Test status
Simulation time 167364582 ps
CPU time 5.82 seconds
Started Jan 03 12:33:11 PM PST 24
Finished Jan 03 12:34:56 PM PST 24
Peak memory 237728 kb
Host smart-9c175047-e1ee-44f6-9d18-2eedf9873d96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407502729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3407502729
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.521102796
Short name T305
Test name
Test status
Simulation time 2496913930 ps
CPU time 16.36 seconds
Started Jan 03 12:33:30 PM PST 24
Finished Jan 03 12:35:25 PM PST 24
Peak memory 229708 kb
Host smart-856b322c-7f82-40d1-8537-122b9f185400
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521102796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_int
g_err.521102796
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2016467872
Short name T1185
Test name
Test status
Simulation time 1057885253 ps
CPU time 3.65 seconds
Started Jan 03 12:33:10 PM PST 24
Finished Jan 03 12:34:38 PM PST 24
Peak memory 237676 kb
Host smart-ae6d64d1-1f0f-48f5-801f-5f32c260c0fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016467872 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.2016467872
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.1276927092
Short name T107
Test name
Test status
Simulation time 133458637 ps
CPU time 1.58 seconds
Started Jan 03 12:33:03 PM PST 24
Finished Jan 03 12:34:43 PM PST 24
Peak memory 229420 kb
Host smart-0c44abf9-d6bf-4edb-87c0-30ecd2c56895
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276927092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.1276927092
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.998837050
Short name T1144
Test name
Test status
Simulation time 42205470 ps
CPU time 1.33 seconds
Started Jan 03 12:32:46 PM PST 24
Finished Jan 03 12:34:49 PM PST 24
Peak memory 229280 kb
Host smart-00721603-4c22-4906-83c2-bb67c439abed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998837050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.998837050
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.857854005
Short name T176
Test name
Test status
Simulation time 129170668 ps
CPU time 1.77 seconds
Started Jan 03 12:32:58 PM PST 24
Finished Jan 03 12:34:45 PM PST 24
Peak memory 229484 kb
Host smart-170451c4-4cbb-45d2-9377-5fb76ea227df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857854005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ct
rl_same_csr_outstanding.857854005
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.396180007
Short name T298
Test name
Test status
Simulation time 1675061707 ps
CPU time 19.32 seconds
Started Jan 03 12:33:04 PM PST 24
Finished Jan 03 12:34:40 PM PST 24
Peak memory 229708 kb
Host smart-c1396346-db96-4c3b-9104-9481406e82d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396180007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_int
g_err.396180007
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.4054858011
Short name T1133
Test name
Test status
Simulation time 104827023 ps
CPU time 2.94 seconds
Started Jan 03 12:33:24 PM PST 24
Finished Jan 03 12:34:46 PM PST 24
Peak memory 237800 kb
Host smart-5164275b-68a8-4519-af71-27f8e6991e52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054858011 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.4054858011
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2162515044
Short name T1215
Test name
Test status
Simulation time 40218362 ps
CPU time 1.44 seconds
Started Jan 03 12:33:00 PM PST 24
Finished Jan 03 12:34:26 PM PST 24
Peak memory 229420 kb
Host smart-895c1a53-3075-48e8-8966-0a5aa7a96cee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162515044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.2162515044
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.3270963200
Short name T112
Test name
Test status
Simulation time 75653994 ps
CPU time 1.33 seconds
Started Jan 03 12:32:40 PM PST 24
Finished Jan 03 12:34:13 PM PST 24
Peak memory 229356 kb
Host smart-3220d031-0426-4a39-8212-21d1c9d89f37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270963200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.3270963200
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.883370257
Short name T268
Test name
Test status
Simulation time 144815488 ps
CPU time 2.22 seconds
Started Jan 03 12:32:58 PM PST 24
Finished Jan 03 12:34:32 PM PST 24
Peak memory 229416 kb
Host smart-9658836f-dee9-4782-9e6b-2957f79e3311
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883370257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ct
rl_same_csr_outstanding.883370257
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3036725343
Short name T1212
Test name
Test status
Simulation time 1081911058 ps
CPU time 5.08 seconds
Started Jan 03 12:33:54 PM PST 24
Finished Jan 03 12:35:36 PM PST 24
Peak memory 237720 kb
Host smart-2aff60bf-6055-4133-a27f-21c8c150537b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036725343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.3036725343
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2005500840
Short name T206
Test name
Test status
Simulation time 2264054871 ps
CPU time 11.09 seconds
Started Jan 03 12:32:40 PM PST 24
Finished Jan 03 12:34:29 PM PST 24
Peak memory 229692 kb
Host smart-b6421166-2bb3-4cd1-8bc5-73f7f306a595
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005500840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.2005500840
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.4213423812
Short name T630
Test name
Test status
Simulation time 147944019 ps
CPU time 2.01 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:54:30 PM PST 24
Peak memory 238188 kb
Host smart-b61e0ac6-2bf2-4888-8505-98d50a9ab932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213423812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.4213423812
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.682828628
Short name T934
Test name
Test status
Simulation time 1173550655 ps
CPU time 6.69 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:54:41 PM PST 24
Peak memory 238460 kb
Host smart-3d8fcaa9-dbf5-4632-aec6-ec035fc6a62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682828628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.682828628
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.2294443569
Short name T282
Test name
Test status
Simulation time 2532374739 ps
CPU time 12.24 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:55:08 PM PST 24
Peak memory 243804 kb
Host smart-d0a02e60-3e09-488c-b435-43a6ddd42651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294443569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.2294443569
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.656055779
Short name T1049
Test name
Test status
Simulation time 614437407 ps
CPU time 7.09 seconds
Started Jan 03 12:54:02 PM PST 24
Finished Jan 03 12:55:49 PM PST 24
Peak memory 244560 kb
Host smart-a40bc6f0-4392-4097-ae4e-b832f88a5e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656055779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.656055779
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.96099320
Short name T962
Test name
Test status
Simulation time 2300019739 ps
CPU time 6.11 seconds
Started Jan 03 12:53:03 PM PST 24
Finished Jan 03 12:54:15 PM PST 24
Peak memory 238512 kb
Host smart-bff08cd2-9ca7-4199-b0b8-99958aa8ccf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96099320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.96099320
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.270565581
Short name T127
Test name
Test status
Simulation time 182141018 ps
CPU time 3.36 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:54:43 PM PST 24
Peak memory 241040 kb
Host smart-6cb10e5c-a6db-46d4-82ac-9e04269abaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270565581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.270565581
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.1729261639
Short name T1075
Test name
Test status
Simulation time 7582418055 ps
CPU time 19.68 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:11 PM PST 24
Peak memory 229776 kb
Host smart-f795b820-97f2-48a1-9dd8-cd3791493cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729261639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.1729261639
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.3979080155
Short name T113
Test name
Test status
Simulation time 17179050203 ps
CPU time 22.71 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:26 PM PST 24
Peak memory 240776 kb
Host smart-680a3a78-1ef5-4468-9d81-034ed1cd4510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979080155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.3979080155
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.1842093428
Short name T764
Test name
Test status
Simulation time 263118903 ps
CPU time 4.03 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:03 PM PST 24
Peak memory 243072 kb
Host smart-db6d66a6-666d-46f4-8d08-71ae4568bd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842093428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.1842093428
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.1330359446
Short name T254
Test name
Test status
Simulation time 116679526 ps
CPU time 2.61 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:54:36 PM PST 24
Peak memory 238472 kb
Host smart-7b1b8292-81a0-4791-91b2-2381487ec2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330359446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.1330359446
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.2383879804
Short name T1121
Test name
Test status
Simulation time 147902710 ps
CPU time 3.94 seconds
Started Jan 03 12:54:02 PM PST 24
Finished Jan 03 12:55:45 PM PST 24
Peak memory 238388 kb
Host smart-abf36668-45a6-41e2-9af8-947717aba266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2383879804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.2383879804
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.2666392692
Short name T361
Test name
Test status
Simulation time 3113545683 ps
CPU time 17.45 seconds
Started Jan 03 12:53:59 PM PST 24
Finished Jan 03 12:55:47 PM PST 24
Peak memory 229976 kb
Host smart-ac45e8bb-9e05-405e-8930-da004f620a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666392692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.2666392692
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.550576128
Short name T681
Test name
Test status
Simulation time 236044084 ps
CPU time 4.62 seconds
Started Jan 03 12:53:34 PM PST 24
Finished Jan 03 12:54:34 PM PST 24
Peak memory 242868 kb
Host smart-8665f430-e2fa-423c-a576-833f5799777d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=550576128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.550576128
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.4121528971
Short name T648
Test name
Test status
Simulation time 4423469888 ps
CPU time 8.2 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:55:04 PM PST 24
Peak memory 237588 kb
Host smart-15aa7bf6-c183-4c5a-b644-2f8d49fbb7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121528971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.4121528971
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.2660265093
Short name T845
Test name
Test status
Simulation time 8682471354 ps
CPU time 37.08 seconds
Started Jan 03 12:53:17 PM PST 24
Finished Jan 03 12:54:55 PM PST 24
Peak memory 239692 kb
Host smart-970f52b0-0d98-475c-b5aa-ef4e4133c093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660265093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
2660265093
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.3962081361
Short name T262
Test name
Test status
Simulation time 2246099363058 ps
CPU time 4117.88 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 02:03:38 PM PST 24
Peak memory 338216 kb
Host smart-7e7e8f34-e03a-4ce8-8369-db4d2b371f99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962081361 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.3962081361
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.3478566408
Short name T831
Test name
Test status
Simulation time 1082617155 ps
CPU time 8.8 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:55:09 PM PST 24
Peak memory 237604 kb
Host smart-44cf42e4-85a6-4a8a-b24a-3deecadc4ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478566408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.3478566408
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.3625615777
Short name T875
Test name
Test status
Simulation time 82163349 ps
CPU time 1.89 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:54:53 PM PST 24
Peak memory 229768 kb
Host smart-a84ae81c-d8d7-4d1e-a5b9-cb4b11178751
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3625615777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.3625615777
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.3492863908
Short name T256
Test name
Test status
Simulation time 1044950661 ps
CPU time 2.12 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:54:32 PM PST 24
Peak memory 238704 kb
Host smart-51e244f2-fcc2-4a4a-8f3e-54ec7aa423d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492863908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.3492863908
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.2934558140
Short name T335
Test name
Test status
Simulation time 6636055772 ps
CPU time 9.83 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:55:21 PM PST 24
Peak memory 238532 kb
Host smart-e60b4126-3543-4a3c-b45a-14b3bf8a8ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934558140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.2934558140
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.2246960503
Short name T1010
Test name
Test status
Simulation time 135164639 ps
CPU time 4.16 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:55:22 PM PST 24
Peak memory 242912 kb
Host smart-efa755ac-198a-4618-95d4-f89d6e5e8efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246960503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.2246960503
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.3269919947
Short name T458
Test name
Test status
Simulation time 240253986 ps
CPU time 7.52 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:55:23 PM PST 24
Peak memory 238480 kb
Host smart-76c26adf-f5c3-445e-8d5b-334b940cda04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269919947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.3269919947
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.88286195
Short name T446
Test name
Test status
Simulation time 515920265 ps
CPU time 5.22 seconds
Started Jan 03 12:53:55 PM PST 24
Finished Jan 03 12:55:30 PM PST 24
Peak memory 246704 kb
Host smart-da19f6cd-aa42-404f-b81e-73a1a3773863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88286195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.88286195
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.4114386417
Short name T104
Test name
Test status
Simulation time 6475066654 ps
CPU time 14.1 seconds
Started Jan 03 12:53:05 PM PST 24
Finished Jan 03 12:54:13 PM PST 24
Peak memory 238696 kb
Host smart-267057da-67b5-4c54-9b75-f367d306b804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114386417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.4114386417
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.1484432251
Short name T852
Test name
Test status
Simulation time 261806160 ps
CPU time 5.24 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:55:21 PM PST 24
Peak memory 238284 kb
Host smart-f15f5c0f-96d1-487f-b242-42126813e851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484432251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.1484432251
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.544907904
Short name T1112
Test name
Test status
Simulation time 373082103 ps
CPU time 11.99 seconds
Started Jan 03 12:53:54 PM PST 24
Finished Jan 03 12:55:35 PM PST 24
Peak memory 238476 kb
Host smart-9feea005-5d9b-45b6-985b-5e9ab307b4d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=544907904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.544907904
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.3132197259
Short name T309
Test name
Test status
Simulation time 505594748 ps
CPU time 4.79 seconds
Started Jan 03 12:53:14 PM PST 24
Finished Jan 03 12:54:23 PM PST 24
Peak memory 243516 kb
Host smart-29d2fe5b-0b71-48d8-a4af-5a63e8c67ba2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3132197259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.3132197259
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.3602508196
Short name T192
Test name
Test status
Simulation time 9237289942 ps
CPU time 147.8 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:57:02 PM PST 24
Peak memory 268468 kb
Host smart-edf082e2-aa3e-4aa3-afd1-7d593d2621ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602508196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.3602508196
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.779362487
Short name T1003
Test name
Test status
Simulation time 3843976453346 ps
CPU time 4998.73 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 02:17:59 PM PST 24
Peak memory 388756 kb
Host smart-eb6a9618-1fc9-495b-afa6-c9859b5bb118
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779362487 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.779362487
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.3060872901
Short name T436
Test name
Test status
Simulation time 2081895548 ps
CPU time 17.27 seconds
Started Jan 03 12:53:50 PM PST 24
Finished Jan 03 12:55:23 PM PST 24
Peak memory 237556 kb
Host smart-f458121a-b1e7-49de-a9f0-2f8df4fdf9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060872901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.3060872901
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.1578395142
Short name T709
Test name
Test status
Simulation time 878271480 ps
CPU time 2.46 seconds
Started Jan 03 12:53:12 PM PST 24
Finished Jan 03 12:54:11 PM PST 24
Peak memory 239264 kb
Host smart-3de60e1f-a609-4b8c-a537-dd3854b7e5cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578395142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.1578395142
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.555165238
Short name T80
Test name
Test status
Simulation time 370266718 ps
CPU time 4.46 seconds
Started Jan 03 12:53:25 PM PST 24
Finished Jan 03 12:54:16 PM PST 24
Peak memory 238164 kb
Host smart-71c14c8f-898f-40ef-b43e-98fff608a87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555165238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.555165238
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.1931126806
Short name T1037
Test name
Test status
Simulation time 160460721 ps
CPU time 7.46 seconds
Started Jan 03 12:53:56 PM PST 24
Finished Jan 03 12:55:35 PM PST 24
Peak memory 238308 kb
Host smart-6652e810-5a26-4440-ab0a-539e00ec874f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931126806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.1931126806
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.2897069039
Short name T827
Test name
Test status
Simulation time 583285702 ps
CPU time 4.4 seconds
Started Jan 03 12:53:43 PM PST 24
Finished Jan 03 12:54:53 PM PST 24
Peak memory 237584 kb
Host smart-250efd3a-6813-4b59-9a48-cc957af117de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897069039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.2897069039
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.4095676809
Short name T532
Test name
Test status
Simulation time 229745955 ps
CPU time 4.3 seconds
Started Jan 03 12:53:34 PM PST 24
Finished Jan 03 12:54:34 PM PST 24
Peak memory 240996 kb
Host smart-44b9b399-5db1-495a-8bea-79f8ff4a7c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095676809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.4095676809
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.1113460157
Short name T791
Test name
Test status
Simulation time 1082296356 ps
CPU time 9.47 seconds
Started Jan 03 12:53:20 PM PST 24
Finished Jan 03 12:54:33 PM PST 24
Peak memory 245540 kb
Host smart-0ee5fca1-e238-4ddd-bc64-3fb740d6e924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113460157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.1113460157
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.3907007964
Short name T896
Test name
Test status
Simulation time 3313690510 ps
CPU time 5.58 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:55:28 PM PST 24
Peak memory 246792 kb
Host smart-41d21b15-f875-4201-90f7-cf7be28649fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907007964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.3907007964
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.6128119
Short name T786
Test name
Test status
Simulation time 3458890859 ps
CPU time 6.36 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:02 PM PST 24
Peak memory 242880 kb
Host smart-2577384f-4114-46a0-91f3-6a481c7d9b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6128119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.6128119
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.1393954290
Short name T1004
Test name
Test status
Simulation time 5320162196 ps
CPU time 13.57 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:00 PM PST 24
Peak memory 238560 kb
Host smart-a119df72-f150-43de-9109-e2a0cf60a3ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393954290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.1393954290
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.1741439642
Short name T853
Test name
Test status
Simulation time 227525086 ps
CPU time 3.84 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:54:55 PM PST 24
Peak memory 238456 kb
Host smart-04405d25-fc66-4413-a5a9-c3c5d254984a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1741439642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.1741439642
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.325735013
Short name T396
Test name
Test status
Simulation time 640937311 ps
CPU time 4.71 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:54:48 PM PST 24
Peak memory 238508 kb
Host smart-711cbd7a-0e63-48f2-908d-fff86a358fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325735013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.325735013
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.3036420264
Short name T679
Test name
Test status
Simulation time 495862480 ps
CPU time 3.01 seconds
Started Jan 03 12:53:01 PM PST 24
Finished Jan 03 12:54:29 PM PST 24
Peak memory 240312 kb
Host smart-c106a04b-232d-4f1b-9ccf-0c2fe6e38568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036420264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.3036420264
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.2446588270
Short name T762
Test name
Test status
Simulation time 162114362 ps
CPU time 3.16 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:49 PM PST 24
Peak memory 241024 kb
Host smart-30d68041-4e32-4241-8a0a-c1c4ae408577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446588270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.2446588270
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.2980663475
Short name T687
Test name
Test status
Simulation time 1771173511 ps
CPU time 6.51 seconds
Started Jan 03 12:55:23 PM PST 24
Finished Jan 03 12:56:54 PM PST 24
Peak memory 238408 kb
Host smart-cd272ed0-53c4-412d-85e4-02cb412c3428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980663475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.2980663475
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.3038495136
Short name T655
Test name
Test status
Simulation time 156572252 ps
CPU time 3.81 seconds
Started Jan 03 12:55:14 PM PST 24
Finished Jan 03 12:56:49 PM PST 24
Peak memory 240972 kb
Host smart-d4cd5399-d1c9-48fb-8494-87020ef09e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038495136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3038495136
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.78468955
Short name T383
Test name
Test status
Simulation time 178786030 ps
CPU time 3.72 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:40 PM PST 24
Peak memory 240856 kb
Host smart-278c32ca-f302-47fd-a32f-57434c1fe518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78468955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.78468955
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.1182390389
Short name T968
Test name
Test status
Simulation time 583284013 ps
CPU time 4.33 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:44 PM PST 24
Peak memory 238416 kb
Host smart-3888ad31-fcf7-491e-9ef3-4e8c7a60e208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182390389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.1182390389
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.3921519700
Short name T726
Test name
Test status
Simulation time 207517873 ps
CPU time 3.4 seconds
Started Jan 03 12:55:44 PM PST 24
Finished Jan 03 12:57:00 PM PST 24
Peak memory 240624 kb
Host smart-ea06c352-e1c5-4777-b742-7614792a2193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921519700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.3921519700
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.2796004157
Short name T525
Test name
Test status
Simulation time 130168470 ps
CPU time 4.13 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:43 PM PST 24
Peak memory 238448 kb
Host smart-8c0b487b-53a7-424f-86b6-874ffacaa197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796004157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.2796004157
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.2550907057
Short name T294
Test name
Test status
Simulation time 342395927 ps
CPU time 3.56 seconds
Started Jan 03 12:55:14 PM PST 24
Finished Jan 03 12:57:06 PM PST 24
Peak memory 241032 kb
Host smart-7972a338-e53b-4d85-a0c9-b08705ed8404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550907057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.2550907057
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.3965771301
Short name T963
Test name
Test status
Simulation time 268361357 ps
CPU time 4.91 seconds
Started Jan 03 12:55:42 PM PST 24
Finished Jan 03 12:56:57 PM PST 24
Peak memory 241080 kb
Host smart-9b2f7e6d-ab93-4483-a2af-83d9dd883175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965771301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.3965771301
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.3675901417
Short name T602
Test name
Test status
Simulation time 117468227 ps
CPU time 4.78 seconds
Started Jan 03 12:55:44 PM PST 24
Finished Jan 03 12:57:09 PM PST 24
Peak memory 242976 kb
Host smart-466832f8-f3c7-4410-be29-6b21c333ef61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675901417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3675901417
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.308998062
Short name T593
Test name
Test status
Simulation time 166298752 ps
CPU time 3.49 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:43 PM PST 24
Peak memory 238368 kb
Host smart-d0c161f4-45df-43e1-a566-edc4831946fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308998062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.308998062
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.3512206249
Short name T540
Test name
Test status
Simulation time 129962209 ps
CPU time 5.25 seconds
Started Jan 03 12:55:23 PM PST 24
Finished Jan 03 12:56:50 PM PST 24
Peak memory 238364 kb
Host smart-8aaf5c30-ad6e-4118-a483-9758ebb93f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512206249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.3512206249
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.1067456095
Short name T954
Test name
Test status
Simulation time 2744189939 ps
CPU time 8.52 seconds
Started Jan 03 12:55:18 PM PST 24
Finished Jan 03 12:56:51 PM PST 24
Peak memory 243376 kb
Host smart-22ef26cd-2539-4ebc-a0b6-dbf9cac3ca67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067456095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.1067456095
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.3511623231
Short name T196
Test name
Test status
Simulation time 497106674 ps
CPU time 3.94 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:52 PM PST 24
Peak memory 243056 kb
Host smart-5a82d52d-ae37-4a86-9a7e-9ee464770b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511623231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.3511623231
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.3383636844
Short name T988
Test name
Test status
Simulation time 166319005 ps
CPU time 3.79 seconds
Started Jan 03 12:55:22 PM PST 24
Finished Jan 03 12:56:52 PM PST 24
Peak memory 238364 kb
Host smart-cd7f3890-54d3-4ef8-ae2a-4e8e0474f7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383636844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3383636844
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.982021551
Short name T670
Test name
Test status
Simulation time 94274827 ps
CPU time 3.16 seconds
Started Jan 03 12:55:46 PM PST 24
Finished Jan 03 12:56:59 PM PST 24
Peak memory 238572 kb
Host smart-14a765b7-7739-4c73-a448-4575340e0072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982021551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.982021551
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.227261643
Short name T508
Test name
Test status
Simulation time 332421572 ps
CPU time 3.93 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:43 PM PST 24
Peak memory 238308 kb
Host smart-ff6ff5aa-6c13-4d8e-bea5-0f139648ddb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227261643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.227261643
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.2840539446
Short name T638
Test name
Test status
Simulation time 273077256 ps
CPU time 5.39 seconds
Started Jan 03 12:55:23 PM PST 24
Finished Jan 03 12:56:50 PM PST 24
Peak memory 242920 kb
Host smart-12efe168-480e-42cf-b1b5-f05116b6605c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840539446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.2840539446
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.2549523237
Short name T722
Test name
Test status
Simulation time 136261161 ps
CPU time 1.95 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:54:41 PM PST 24
Peak memory 239176 kb
Host smart-33054a90-536a-4a59-80e4-b2235a2c71ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549523237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.2549523237
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.2164620953
Short name T62
Test name
Test status
Simulation time 413430790 ps
CPU time 11.69 seconds
Started Jan 03 12:54:11 PM PST 24
Finished Jan 03 12:55:57 PM PST 24
Peak memory 246584 kb
Host smart-14772977-37e8-4ee7-b80c-c8b5329db4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164620953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.2164620953
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.4230071162
Short name T842
Test name
Test status
Simulation time 411910044 ps
CPU time 6.84 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:07 PM PST 24
Peak memory 242516 kb
Host smart-5cdfc91f-d585-485e-a8b9-db05c1b4adc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230071162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.4230071162
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.2531773311
Short name T346
Test name
Test status
Simulation time 2022424116 ps
CPU time 9.83 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:15 PM PST 24
Peak memory 238508 kb
Host smart-757d4ffa-e92b-4d40-ae9d-f7e59a1ef278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531773311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.2531773311
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.3772798383
Short name T424
Test name
Test status
Simulation time 1592742415 ps
CPU time 3.25 seconds
Started Jan 03 12:53:17 PM PST 24
Finished Jan 03 12:54:21 PM PST 24
Peak memory 238320 kb
Host smart-26c96386-7e79-43df-bc8e-f5167ea4b6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772798383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.3772798383
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.174726430
Short name T1018
Test name
Test status
Simulation time 3608661860 ps
CPU time 20.18 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:31 PM PST 24
Peak memory 246500 kb
Host smart-8e5616e2-aa5a-416d-b3ef-d9d18c0a788c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174726430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.174726430
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.2980374501
Short name T663
Test name
Test status
Simulation time 7754999994 ps
CPU time 12.21 seconds
Started Jan 03 12:53:18 PM PST 24
Finished Jan 03 12:54:21 PM PST 24
Peak memory 238636 kb
Host smart-170782d6-db12-4911-a166-c27301e62904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980374501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.2980374501
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.818147230
Short name T816
Test name
Test status
Simulation time 336129501 ps
CPU time 3.56 seconds
Started Jan 03 12:53:23 PM PST 24
Finished Jan 03 12:54:33 PM PST 24
Peak memory 238380 kb
Host smart-50912338-e2c9-42f7-8a6c-9697ae4f2e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818147230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.818147230
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.4291078251
Short name T642
Test name
Test status
Simulation time 947567316 ps
CPU time 5.68 seconds
Started Jan 03 12:53:54 PM PST 24
Finished Jan 03 12:55:30 PM PST 24
Peak memory 243496 kb
Host smart-272c8f37-953b-456c-8d1e-f8cc38164b32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4291078251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.4291078251
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.2716231728
Short name T601
Test name
Test status
Simulation time 307116589 ps
CPU time 3.66 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:55:03 PM PST 24
Peak memory 246736 kb
Host smart-e23888d6-9d9c-4130-8de0-b38cb8e00fdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716231728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.2716231728
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.3050210486
Short name T1017
Test name
Test status
Simulation time 3606927602 ps
CPU time 6.31 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:58 PM PST 24
Peak memory 242968 kb
Host smart-118cb977-5470-4b89-805a-82eaf51da44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050210486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.3050210486
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.2029076803
Short name T935
Test name
Test status
Simulation time 678499505546 ps
CPU time 6808.14 seconds
Started Jan 03 12:53:29 PM PST 24
Finished Jan 03 02:47:50 PM PST 24
Peak memory 963732 kb
Host smart-e2ab8301-81e9-49d7-9bbc-c3f34cd854c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029076803 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.2029076803
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.33600151
Short name T1122
Test name
Test status
Simulation time 985771153 ps
CPU time 13.19 seconds
Started Jan 03 12:53:30 PM PST 24
Finished Jan 03 12:54:37 PM PST 24
Peak memory 238448 kb
Host smart-a3a06e56-14d1-4ac1-a0b5-830e4049ee17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33600151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.33600151
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.99098251
Short name T58
Test name
Test status
Simulation time 2772566588 ps
CPU time 6.16 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:50 PM PST 24
Peak memory 241556 kb
Host smart-a9163b92-b4ec-4c20-b6c2-2d2951ee28dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99098251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.99098251
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.1367516259
Short name T697
Test name
Test status
Simulation time 2770601970 ps
CPU time 5.86 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:50 PM PST 24
Peak memory 238532 kb
Host smart-6002f844-7dfd-43fe-b7e4-f3f3d149ca5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367516259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.1367516259
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.3746744876
Short name T63
Test name
Test status
Simulation time 294875214 ps
CPU time 3.76 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:50 PM PST 24
Peak memory 238372 kb
Host smart-38b2fe22-c231-4f96-9be0-c9391b8bc6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746744876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3746744876
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.981514675
Short name T355
Test name
Test status
Simulation time 515845098 ps
CPU time 6.53 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:43 PM PST 24
Peak memory 238524 kb
Host smart-c26a0990-37d2-41a9-b570-c6c3c21fc342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981514675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.981514675
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.1705285068
Short name T1065
Test name
Test status
Simulation time 177883037 ps
CPU time 3.69 seconds
Started Jan 03 12:55:14 PM PST 24
Finished Jan 03 12:56:59 PM PST 24
Peak memory 241072 kb
Host smart-e91085e3-6a02-4cb2-a50c-f8c60cc19944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705285068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.1705285068
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.3787446662
Short name T926
Test name
Test status
Simulation time 3856542156 ps
CPU time 6.66 seconds
Started Jan 03 12:55:41 PM PST 24
Finished Jan 03 12:57:08 PM PST 24
Peak memory 244200 kb
Host smart-55d2c6e6-718f-46ea-9780-bca6d4854624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787446662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.3787446662
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.862590947
Short name T1083
Test name
Test status
Simulation time 265967121 ps
CPU time 2.89 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:47 PM PST 24
Peak memory 240204 kb
Host smart-11049ea4-954c-4aad-822f-a88e785e758e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862590947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.862590947
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.1796203087
Short name T925
Test name
Test status
Simulation time 1946352921 ps
CPU time 6.29 seconds
Started Jan 03 12:55:17 PM PST 24
Finished Jan 03 12:57:13 PM PST 24
Peak memory 238624 kb
Host smart-0d18c621-afc1-472a-b46c-ebb8ce91c006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796203087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.1796203087
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.3045043513
Short name T374
Test name
Test status
Simulation time 2444051593 ps
CPU time 6.67 seconds
Started Jan 03 12:55:45 PM PST 24
Finished Jan 03 12:57:03 PM PST 24
Peak memory 241472 kb
Host smart-bcf545cd-3b57-457e-8deb-4184a30a38e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045043513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.3045043513
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.4003288689
Short name T352
Test name
Test status
Simulation time 208892577 ps
CPU time 3.3 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:51 PM PST 24
Peak memory 241088 kb
Host smart-96992d6d-1e97-4504-8256-70b09b21162c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003288689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.4003288689
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.2367151372
Short name T398
Test name
Test status
Simulation time 374838143 ps
CPU time 5.23 seconds
Started Jan 03 12:55:14 PM PST 24
Finished Jan 03 12:57:05 PM PST 24
Peak memory 238316 kb
Host smart-700695d6-f2c3-446e-b1e8-54bab3805af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367151372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.2367151372
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.2626004000
Short name T771
Test name
Test status
Simulation time 215944219 ps
CPU time 5.01 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:44 PM PST 24
Peak memory 246528 kb
Host smart-ec8dad16-0036-455d-8e96-f686eb56a202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626004000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.2626004000
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.2028106866
Short name T591
Test name
Test status
Simulation time 107093007 ps
CPU time 3.45 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:43 PM PST 24
Peak memory 238444 kb
Host smart-22dc15de-20cd-4a6c-955c-97510c97c201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028106866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.2028106866
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.2670065354
Short name T929
Test name
Test status
Simulation time 242589176 ps
CPU time 6.78 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:55 PM PST 24
Peak memory 246688 kb
Host smart-88508d9e-0788-42f7-9984-52978eafb036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670065354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.2670065354
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.3355979228
Short name T447
Test name
Test status
Simulation time 391914755 ps
CPU time 4.56 seconds
Started Jan 03 12:55:47 PM PST 24
Finished Jan 03 12:57:11 PM PST 24
Peak memory 241004 kb
Host smart-404359d8-19da-40f6-ba14-899707fbdc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355979228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.3355979228
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.3883020992
Short name T518
Test name
Test status
Simulation time 229716425 ps
CPU time 7.72 seconds
Started Jan 03 12:55:43 PM PST 24
Finished Jan 03 12:57:01 PM PST 24
Peak memory 242744 kb
Host smart-fb9d2303-7c7f-4577-9ea7-aa1499c8ac0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883020992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.3883020992
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.1004412352
Short name T607
Test name
Test status
Simulation time 438303898 ps
CPU time 4.01 seconds
Started Jan 03 12:55:27 PM PST 24
Finished Jan 03 12:57:10 PM PST 24
Peak memory 240816 kb
Host smart-091aff94-15f7-487d-9d56-64524b15f271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004412352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.1004412352
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.250299397
Short name T389
Test name
Test status
Simulation time 142923345 ps
CPU time 3.19 seconds
Started Jan 03 12:55:15 PM PST 24
Finished Jan 03 12:56:44 PM PST 24
Peak memory 238456 kb
Host smart-d005e5b4-8118-4107-99a7-63cdfe516deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250299397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.250299397
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.3312059207
Short name T1096
Test name
Test status
Simulation time 116092084 ps
CPU time 4.19 seconds
Started Jan 03 12:55:42 PM PST 24
Finished Jan 03 12:57:01 PM PST 24
Peak memory 238348 kb
Host smart-ca75822d-d519-4d8b-92f0-b5a537b4c8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312059207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.3312059207
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.2806145339
Short name T292
Test name
Test status
Simulation time 202937432 ps
CPU time 5.23 seconds
Started Jan 03 12:55:14 PM PST 24
Finished Jan 03 12:56:49 PM PST 24
Peak memory 242324 kb
Host smart-41f8c677-3947-4cb5-a1a9-b7ca41a55cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806145339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.2806145339
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.636454126
Short name T748
Test name
Test status
Simulation time 182328418 ps
CPU time 1.73 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:54:43 PM PST 24
Peak memory 238560 kb
Host smart-5f6fdf4c-7fe0-4553-87d5-3853b912e24d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636454126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.636454126
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.2325514602
Short name T426
Test name
Test status
Simulation time 6726344965 ps
CPU time 16.15 seconds
Started Jan 03 12:53:51 PM PST 24
Finished Jan 03 12:55:32 PM PST 24
Peak memory 243028 kb
Host smart-98407ed2-0b1d-46b2-b804-ba028c4f49f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325514602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.2325514602
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.3817136614
Short name T115
Test name
Test status
Simulation time 2385429784 ps
CPU time 7.55 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:54:59 PM PST 24
Peak memory 243964 kb
Host smart-90242844-fc40-4dfc-bab1-1861f5084159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817136614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.3817136614
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.4092427557
Short name T682
Test name
Test status
Simulation time 1084493646 ps
CPU time 5.55 seconds
Started Jan 03 12:54:06 PM PST 24
Finished Jan 03 12:55:50 PM PST 24
Peak memory 238520 kb
Host smart-cd0081ce-1c66-4642-94e6-0af215915381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092427557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.4092427557
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.2218988982
Short name T122
Test name
Test status
Simulation time 3339416808 ps
CPU time 17.95 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:10 PM PST 24
Peak memory 238956 kb
Host smart-aebb13ce-be9f-432a-be1a-afb89a84cdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218988982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.2218988982
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.3849280000
Short name T721
Test name
Test status
Simulation time 3411425824 ps
CPU time 6.57 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:54:58 PM PST 24
Peak memory 238676 kb
Host smart-2c593364-3799-4cfe-a693-881e16966369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849280000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.3849280000
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.1940518631
Short name T1069
Test name
Test status
Simulation time 110467457 ps
CPU time 2.84 seconds
Started Jan 03 12:53:17 PM PST 24
Finished Jan 03 12:54:12 PM PST 24
Peak memory 241472 kb
Host smart-812afbfb-a825-4143-88b1-4e772a4b25dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940518631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.1940518631
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.1166528315
Short name T1028
Test name
Test status
Simulation time 556873779 ps
CPU time 13.46 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:00 PM PST 24
Peak memory 243140 kb
Host smart-43b1f293-680b-478d-85dd-d89d5946e605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1166528315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.1166528315
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.1991279879
Short name T1124
Test name
Test status
Simulation time 251693925 ps
CPU time 3.95 seconds
Started Jan 03 12:53:27 PM PST 24
Finished Jan 03 12:54:22 PM PST 24
Peak memory 238348 kb
Host smart-3f91aa2e-7e77-4fa5-9d03-3fcf09aeb598
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991279879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1991279879
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.2080650392
Short name T1050
Test name
Test status
Simulation time 200040080 ps
CPU time 4.37 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:54:59 PM PST 24
Peak memory 243088 kb
Host smart-d353412e-1d5b-441f-839d-8f8421f9ad19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080650392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.2080650392
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.2586851705
Short name T324
Test name
Test status
Simulation time 1878978030 ps
CPU time 32.96 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:55:29 PM PST 24
Peak memory 238604 kb
Host smart-f767441b-f1cc-444b-90ee-74cf872031dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586851705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.2586851705
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.1323340885
Short name T1109
Test name
Test status
Simulation time 3012596771873 ps
CPU time 3745.05 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 01:57:13 PM PST 24
Peak memory 327492 kb
Host smart-ce74a030-cbdf-4a13-bd0b-e171edb60ebe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323340885 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.1323340885
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.1928240565
Short name T231
Test name
Test status
Simulation time 929972156 ps
CPU time 9.83 seconds
Started Jan 03 12:53:43 PM PST 24
Finished Jan 03 12:54:54 PM PST 24
Peak memory 243904 kb
Host smart-6b870ecb-849c-45de-8f2b-38346f10ae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928240565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1928240565
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.2757488269
Short name T125
Test name
Test status
Simulation time 268219452 ps
CPU time 3.99 seconds
Started Jan 03 12:55:14 PM PST 24
Finished Jan 03 12:56:47 PM PST 24
Peak memory 241352 kb
Host smart-8b5193e5-04a6-4acc-9772-390b3136cd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757488269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.2757488269
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.54665214
Short name T944
Test name
Test status
Simulation time 194628378 ps
CPU time 4 seconds
Started Jan 03 12:55:44 PM PST 24
Finished Jan 03 12:57:04 PM PST 24
Peak memory 246500 kb
Host smart-c2fa634a-3e7c-47ff-b570-25405b2800d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54665214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.54665214
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.4068063519
Short name T579
Test name
Test status
Simulation time 155946090 ps
CPU time 4.1 seconds
Started Jan 03 12:55:18 PM PST 24
Finished Jan 03 12:56:43 PM PST 24
Peak memory 238424 kb
Host smart-c3aef249-1933-4e75-b00e-fc5222db8bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068063519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.4068063519
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.3437489977
Short name T542
Test name
Test status
Simulation time 1216490649 ps
CPU time 8.12 seconds
Started Jan 03 12:55:15 PM PST 24
Finished Jan 03 12:56:49 PM PST 24
Peak memory 238412 kb
Host smart-9ce0104f-2668-4103-9866-3d65ddea551b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437489977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.3437489977
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.2471721743
Short name T75
Test name
Test status
Simulation time 167478060 ps
CPU time 4.08 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:43 PM PST 24
Peak memory 240988 kb
Host smart-c9310886-d6d4-4242-9ae5-0e6f7e83c2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471721743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.2471721743
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.3063792419
Short name T522
Test name
Test status
Simulation time 1667989669 ps
CPU time 10.54 seconds
Started Jan 03 12:55:18 PM PST 24
Finished Jan 03 12:56:52 PM PST 24
Peak memory 238468 kb
Host smart-9978328e-f1c5-4cc8-8ddd-56dd3eda972d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063792419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.3063792419
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.79720594
Short name T851
Test name
Test status
Simulation time 130062073 ps
CPU time 3.67 seconds
Started Jan 03 12:55:17 PM PST 24
Finished Jan 03 12:57:10 PM PST 24
Peak memory 246604 kb
Host smart-0c0aeb55-c6cc-46e1-b7e0-9522a44f742c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79720594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.79720594
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.1166445729
Short name T592
Test name
Test status
Simulation time 207333955 ps
CPU time 5.02 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:50 PM PST 24
Peak memory 242608 kb
Host smart-878e3b06-e166-4edc-a405-33b989ade9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166445729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.1166445729
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.3447746503
Short name T695
Test name
Test status
Simulation time 379530712 ps
CPU time 4.29 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:50 PM PST 24
Peak memory 238432 kb
Host smart-4ec905a3-dbd8-4c1f-bccf-671d55d4ff36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447746503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.3447746503
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.2856903982
Short name T987
Test name
Test status
Simulation time 348748286 ps
CPU time 3.62 seconds
Started Jan 03 12:55:19 PM PST 24
Finished Jan 03 12:56:42 PM PST 24
Peak memory 238300 kb
Host smart-a9344abb-cde1-4c40-b9a1-cdef7eb4d57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856903982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.2856903982
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.4154482458
Short name T99
Test name
Test status
Simulation time 189985352 ps
CPU time 3.94 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:49 PM PST 24
Peak memory 238344 kb
Host smart-42996e22-e151-46b2-ac2b-bf6e1eb9ac3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154482458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.4154482458
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.2656035049
Short name T103
Test name
Test status
Simulation time 441818961 ps
CPU time 6 seconds
Started Jan 03 12:55:18 PM PST 24
Finished Jan 03 12:56:49 PM PST 24
Peak memory 238496 kb
Host smart-f134ee5d-8faa-40d1-a643-13b2264aeaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656035049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.2656035049
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.3499810090
Short name T774
Test name
Test status
Simulation time 220282262 ps
CPU time 3.86 seconds
Started Jan 03 12:55:44 PM PST 24
Finished Jan 03 12:57:07 PM PST 24
Peak memory 240876 kb
Host smart-616614a0-3d85-4366-a3c7-978259f06bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499810090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3499810090
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.3710621937
Short name T480
Test name
Test status
Simulation time 475621863 ps
CPU time 9.57 seconds
Started Jan 03 12:55:12 PM PST 24
Finished Jan 03 12:57:02 PM PST 24
Peak memory 244380 kb
Host smart-c42985b2-fd66-4c85-b6ca-ba5f29288845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710621937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.3710621937
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.249586629
Short name T624
Test name
Test status
Simulation time 104229477 ps
CPU time 3.48 seconds
Started Jan 03 12:55:31 PM PST 24
Finished Jan 03 12:56:53 PM PST 24
Peak memory 246504 kb
Host smart-28d18d31-c655-478b-af93-6bace527d6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249586629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.249586629
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.2140834902
Short name T454
Test name
Test status
Simulation time 1122515986 ps
CPU time 7.92 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:47 PM PST 24
Peak memory 238460 kb
Host smart-bd3cfa95-701f-4b8f-a631-df0dce0bc181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140834902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.2140834902
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.3274131609
Short name T65
Test name
Test status
Simulation time 274218006 ps
CPU time 4.08 seconds
Started Jan 03 12:55:17 PM PST 24
Finished Jan 03 12:56:43 PM PST 24
Peak memory 240980 kb
Host smart-9dd6fc57-d59a-40e8-9a15-71fb6b3d1f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274131609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.3274131609
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.1514602120
Short name T158
Test name
Test status
Simulation time 248385059 ps
CPU time 3.54 seconds
Started Jan 03 12:55:20 PM PST 24
Finished Jan 03 12:56:49 PM PST 24
Peak memory 242236 kb
Host smart-14ccaf90-ec6b-4672-8e2a-f31f968286b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514602120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.1514602120
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.2756153022
Short name T666
Test name
Test status
Simulation time 475770258 ps
CPU time 3.52 seconds
Started Jan 03 12:55:21 PM PST 24
Finished Jan 03 12:56:45 PM PST 24
Peak memory 238300 kb
Host smart-e92075f3-6e02-4bee-b481-8cdffd53f485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756153022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.2756153022
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.2401383752
Short name T825
Test name
Test status
Simulation time 252211567 ps
CPU time 5.82 seconds
Started Jan 03 12:55:45 PM PST 24
Finished Jan 03 12:57:02 PM PST 24
Peak memory 238468 kb
Host smart-e800050e-75dc-44a7-a5ef-ed2d17450ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401383752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.2401383752
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.2221448634
Short name T52
Test name
Test status
Simulation time 1971238162 ps
CPU time 12.24 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:54:50 PM PST 24
Peak memory 238504 kb
Host smart-f954d9af-fb99-42b0-851e-e0ce3bf363c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221448634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.2221448634
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.3105025980
Short name T948
Test name
Test status
Simulation time 315839257 ps
CPU time 5.85 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:54:38 PM PST 24
Peak memory 242568 kb
Host smart-aa020a9b-b57f-4a47-847e-4f26a710211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105025980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.3105025980
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.3238766555
Short name T598
Test name
Test status
Simulation time 8863542051 ps
CPU time 15.21 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:22 PM PST 24
Peak memory 246272 kb
Host smart-bc08136b-5c71-42e3-99e3-bc44dad11281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238766555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.3238766555
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.185439349
Short name T809
Test name
Test status
Simulation time 680388158 ps
CPU time 4.67 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:54:46 PM PST 24
Peak memory 238424 kb
Host smart-60db1587-ddd2-4677-bcb6-1e0a5b5d6e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185439349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.185439349
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.1749271160
Short name T643
Test name
Test status
Simulation time 564367700 ps
CPU time 8.49 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:13 PM PST 24
Peak memory 243788 kb
Host smart-d2301b47-9b4a-49d4-a27a-9b16c81ba67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749271160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.1749271160
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.2811210209
Short name T672
Test name
Test status
Simulation time 11304486632 ps
CPU time 14.85 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:02 PM PST 24
Peak memory 246844 kb
Host smart-522b7d67-9e3e-463e-a332-e0ec56cd1be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811210209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.2811210209
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.1220354647
Short name T289
Test name
Test status
Simulation time 587306054 ps
CPU time 6.41 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:55:02 PM PST 24
Peak memory 241884 kb
Host smart-fb312a8a-90ce-4f26-83a0-fb39c60047f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220354647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.1220354647
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.1882076347
Short name T194
Test name
Test status
Simulation time 1369841169 ps
CPU time 10.43 seconds
Started Jan 03 12:54:02 PM PST 24
Finished Jan 03 12:55:47 PM PST 24
Peak memory 238436 kb
Host smart-7074e2d0-52fc-4cd9-9847-63602319ee5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1882076347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.1882076347
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.968442404
Short name T444
Test name
Test status
Simulation time 3747309382 ps
CPU time 12.04 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:32 PM PST 24
Peak memory 238704 kb
Host smart-44169064-acf8-4e57-8d30-e14b327f7e61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968442404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.968442404
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.479177234
Short name T384
Test name
Test status
Simulation time 851466572 ps
CPU time 6.03 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:54:50 PM PST 24
Peak memory 242640 kb
Host smart-c5af9cba-87a6-42bf-a62d-7fdbad7f83d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479177234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.479177234
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.2879078258
Short name T1077
Test name
Test status
Simulation time 4587459387 ps
CPU time 48.56 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:55:44 PM PST 24
Peak memory 239644 kb
Host smart-ba81c979-2e52-41ec-b84b-4dc3033cf785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879078258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.2879078258
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.3812162494
Short name T864
Test name
Test status
Simulation time 1234484922382 ps
CPU time 7782.29 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 03:04:41 PM PST 24
Peak memory 971100 kb
Host smart-556def10-3ce2-49af-bfa6-0f4ce00f7441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812162494 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.3812162494
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.1706454050
Short name T873
Test name
Test status
Simulation time 3630786383 ps
CPU time 15.83 seconds
Started Jan 03 12:53:15 PM PST 24
Finished Jan 03 12:54:24 PM PST 24
Peak memory 237748 kb
Host smart-7e6d591c-e678-4a10-8450-e4afddcdc2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706454050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.1706454050
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.2371982879
Short name T140
Test name
Test status
Simulation time 616472662 ps
CPU time 4.28 seconds
Started Jan 03 12:56:10 PM PST 24
Finished Jan 03 12:57:23 PM PST 24
Peak memory 238444 kb
Host smart-6faac744-3b0a-418f-a73a-ebbfb3209593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371982879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.2371982879
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.3892262005
Short name T724
Test name
Test status
Simulation time 146446009 ps
CPU time 4.65 seconds
Started Jan 03 12:55:46 PM PST 24
Finished Jan 03 12:57:01 PM PST 24
Peak memory 242212 kb
Host smart-ecd26394-f413-4057-b141-7fa422abee90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892262005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.3892262005
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.664591930
Short name T1128
Test name
Test status
Simulation time 521872324 ps
CPU time 4.28 seconds
Started Jan 03 12:56:01 PM PST 24
Finished Jan 03 12:57:13 PM PST 24
Peak memory 240628 kb
Host smart-66c5e9e7-d57b-4310-9bbb-304b514e138f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664591930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.664591930
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.689662803
Short name T692
Test name
Test status
Simulation time 1627333424 ps
CPU time 4.37 seconds
Started Jan 03 12:55:50 PM PST 24
Finished Jan 03 12:57:07 PM PST 24
Peak memory 242084 kb
Host smart-722d23c0-2b4c-4d09-a731-fe7f932f60f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689662803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.689662803
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.1596736954
Short name T916
Test name
Test status
Simulation time 254791785 ps
CPU time 3.46 seconds
Started Jan 03 12:55:50 PM PST 24
Finished Jan 03 12:57:04 PM PST 24
Peak memory 238360 kb
Host smart-39a713fa-4ca0-4501-a3cc-bc5c6f4ff60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596736954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.1596736954
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.2609953265
Short name T941
Test name
Test status
Simulation time 232654321 ps
CPU time 4.44 seconds
Started Jan 03 12:55:44 PM PST 24
Finished Jan 03 12:56:59 PM PST 24
Peak memory 238420 kb
Host smart-7b487b69-389a-426a-9eb7-1188f07b295d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609953265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.2609953265
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.4218315792
Short name T760
Test name
Test status
Simulation time 180464599 ps
CPU time 4.36 seconds
Started Jan 03 12:55:48 PM PST 24
Finished Jan 03 12:57:03 PM PST 24
Peak memory 241268 kb
Host smart-4961889d-fdba-4f71-adbf-84f94c4ac301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218315792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.4218315792
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.2839893673
Short name T1041
Test name
Test status
Simulation time 227823333 ps
CPU time 3.79 seconds
Started Jan 03 12:56:12 PM PST 24
Finished Jan 03 12:57:25 PM PST 24
Peak memory 242660 kb
Host smart-f40c8d38-59b8-41c9-8a85-71b37309ca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839893673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.2839893673
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.2689949811
Short name T529
Test name
Test status
Simulation time 220653473 ps
CPU time 4.25 seconds
Started Jan 03 12:55:45 PM PST 24
Finished Jan 03 12:57:08 PM PST 24
Peak memory 238368 kb
Host smart-705a9748-fa5b-467b-aa68-52427cd9df8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689949811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2689949811
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.1974209290
Short name T674
Test name
Test status
Simulation time 222221283 ps
CPU time 7.2 seconds
Started Jan 03 12:55:47 PM PST 24
Finished Jan 03 12:57:07 PM PST 24
Peak memory 238404 kb
Host smart-5ba31415-af96-4f22-9e40-0cf5475116bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974209290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.1974209290
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.782646023
Short name T719
Test name
Test status
Simulation time 302885636 ps
CPU time 3.42 seconds
Started Jan 03 12:56:04 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 238320 kb
Host smart-112ac3a4-4c12-4f24-bc85-8c6270c58557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782646023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.782646023
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.1712366434
Short name T1023
Test name
Test status
Simulation time 1844866717 ps
CPU time 4.96 seconds
Started Jan 03 12:56:16 PM PST 24
Finished Jan 03 12:57:30 PM PST 24
Peak memory 238520 kb
Host smart-c6aa830f-1d33-438a-b16a-bc95b95153c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712366434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1712366434
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.1230522787
Short name T1021
Test name
Test status
Simulation time 117518109 ps
CPU time 3.58 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:17 PM PST 24
Peak memory 240548 kb
Host smart-7b92c334-735f-4ba4-84c3-82d2f47925f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230522787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.1230522787
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.1523840873
Short name T777
Test name
Test status
Simulation time 120683392 ps
CPU time 4.14 seconds
Started Jan 03 12:56:13 PM PST 24
Finished Jan 03 12:57:25 PM PST 24
Peak memory 243020 kb
Host smart-46c9aca5-43f0-43fd-abc3-eb92cbc32ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523840873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.1523840873
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.2894297073
Short name T1022
Test name
Test status
Simulation time 144891804 ps
CPU time 3.53 seconds
Started Jan 03 12:55:57 PM PST 24
Finished Jan 03 12:57:09 PM PST 24
Peak memory 238392 kb
Host smart-6564f37d-90ba-4045-8784-2455fe1ee2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894297073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.2894297073
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.2899198788
Short name T1125
Test name
Test status
Simulation time 1326195472 ps
CPU time 9.93 seconds
Started Jan 03 12:55:57 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 238360 kb
Host smart-0e3b4aba-bc2a-497b-8424-1ca43965980f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899198788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.2899198788
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.620511789
Short name T749
Test name
Test status
Simulation time 169012513 ps
CPU time 4.39 seconds
Started Jan 03 12:56:01 PM PST 24
Finished Jan 03 12:57:13 PM PST 24
Peak memory 240996 kb
Host smart-3c8bfdbc-f415-4c4e-9d0b-b067f8e9e428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620511789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.620511789
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.1844506543
Short name T990
Test name
Test status
Simulation time 168953422 ps
CPU time 3.01 seconds
Started Jan 03 12:55:47 PM PST 24
Finished Jan 03 12:57:09 PM PST 24
Peak memory 238332 kb
Host smart-2b71ed6c-1a62-41f2-b45b-151c24924874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844506543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.1844506543
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.3704677577
Short name T489
Test name
Test status
Simulation time 77558516 ps
CPU time 1.71 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:54:31 PM PST 24
Peak memory 238144 kb
Host smart-e2334e6e-d31b-4a4e-bfa6-5ebf56d0053e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704677577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.3704677577
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.3023285665
Short name T1024
Test name
Test status
Simulation time 802298580 ps
CPU time 7.44 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:05 PM PST 24
Peak memory 238320 kb
Host smart-b7e7a445-de39-43f7-82d7-154c2ca162c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023285665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.3023285665
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.1866202911
Short name T957
Test name
Test status
Simulation time 758863276 ps
CPU time 14.88 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:54:53 PM PST 24
Peak memory 238480 kb
Host smart-1cf28003-4326-4ae3-acff-917419abc974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866202911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.1866202911
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.158388203
Short name T467
Test name
Test status
Simulation time 187853195 ps
CPU time 3.71 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:54:48 PM PST 24
Peak memory 240940 kb
Host smart-a2e8860a-fd76-4e8b-b0be-c5a6356a8678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158388203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.158388203
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.3972638268
Short name T645
Test name
Test status
Simulation time 738422312 ps
CPU time 6.78 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:52 PM PST 24
Peak memory 245652 kb
Host smart-19c4e738-8dbd-41e8-b36f-e61fe571e82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972638268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.3972638268
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.3624268082
Short name T668
Test name
Test status
Simulation time 312472800 ps
CPU time 3.77 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:55:29 PM PST 24
Peak memory 241208 kb
Host smart-d519f63f-3235-4935-a80a-d04bc1e5224f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624268082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.3624268082
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.259826982
Short name T327
Test name
Test status
Simulation time 1735115489 ps
CPU time 15.07 seconds
Started Jan 03 12:53:27 PM PST 24
Finished Jan 03 12:54:33 PM PST 24
Peak memory 238480 kb
Host smart-18cef304-2436-4b25-9b78-136fea14ba4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=259826982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.259826982
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.3896403824
Short name T976
Test name
Test status
Simulation time 2975625933 ps
CPU time 8.29 seconds
Started Jan 03 12:54:08 PM PST 24
Finished Jan 03 12:55:56 PM PST 24
Peak memory 238540 kb
Host smart-98a315cc-4a3a-4cdc-9274-03e74cd97ecb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3896403824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.3896403824
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.3232320226
Short name T704
Test name
Test status
Simulation time 803516975 ps
CPU time 6.76 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:52 PM PST 24
Peak memory 238456 kb
Host smart-c36136fb-b653-4baf-b4da-1dec062f668c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232320226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.3232320226
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.4281976572
Short name T1019
Test name
Test status
Simulation time 26449720527 ps
CPU time 156.2 seconds
Started Jan 03 12:53:26 PM PST 24
Finished Jan 03 12:56:48 PM PST 24
Peak memory 241292 kb
Host smart-ca6cf6ce-3d02-4ce9-8e30-df926842e4dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281976572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.4281976572
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.1183030873
Short name T649
Test name
Test status
Simulation time 444463962747 ps
CPU time 7800.39 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 03:04:57 PM PST 24
Peak memory 372028 kb
Host smart-4fb78de0-8cc5-4337-9956-ec7507d92d2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183030873 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.1183030873
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.3193275088
Short name T345
Test name
Test status
Simulation time 1018503353 ps
CPU time 15.71 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:55:04 PM PST 24
Peak memory 246668 kb
Host smart-f78d4325-ecfa-415f-9c70-8d64d7b132a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193275088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.3193275088
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.4272238709
Short name T861
Test name
Test status
Simulation time 2603788323 ps
CPU time 5.47 seconds
Started Jan 03 12:56:01 PM PST 24
Finished Jan 03 12:57:14 PM PST 24
Peak memory 238536 kb
Host smart-afc05152-213d-4d34-90ee-be5a71a31092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272238709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.4272238709
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.415206146
Short name T319
Test name
Test status
Simulation time 177125859 ps
CPU time 4.01 seconds
Started Jan 03 12:55:44 PM PST 24
Finished Jan 03 12:57:01 PM PST 24
Peak memory 246644 kb
Host smart-bf8b3892-c1c5-4074-8382-21fc23c1b7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415206146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.415206146
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.123862681
Short name T37
Test name
Test status
Simulation time 406470080 ps
CPU time 4.04 seconds
Started Jan 03 12:55:57 PM PST 24
Finished Jan 03 12:57:20 PM PST 24
Peak memory 241040 kb
Host smart-6a01bdfb-329c-4638-95fb-fcbcdd91cb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123862681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.123862681
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.2370701313
Short name T725
Test name
Test status
Simulation time 220918857 ps
CPU time 3.97 seconds
Started Jan 03 12:55:44 PM PST 24
Finished Jan 03 12:57:01 PM PST 24
Peak memory 238288 kb
Host smart-05d3a814-788b-4f02-86bd-926eaba87244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370701313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.2370701313
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.4047112259
Short name T492
Test name
Test status
Simulation time 529021703 ps
CPU time 3.99 seconds
Started Jan 03 12:55:47 PM PST 24
Finished Jan 03 12:57:02 PM PST 24
Peak memory 238404 kb
Host smart-803f9c55-301d-4b1f-857c-7f05b1b9a04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047112259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.4047112259
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.2030068786
Short name T558
Test name
Test status
Simulation time 341088982 ps
CPU time 8.55 seconds
Started Jan 03 12:55:45 PM PST 24
Finished Jan 03 12:57:05 PM PST 24
Peak memory 238364 kb
Host smart-e858e493-6f7a-4076-9879-96d564ae3abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030068786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.2030068786
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.2246920326
Short name T609
Test name
Test status
Simulation time 368563316 ps
CPU time 3.61 seconds
Started Jan 03 12:55:47 PM PST 24
Finished Jan 03 12:57:03 PM PST 24
Peak memory 242636 kb
Host smart-c0c292b4-57e3-4005-8f5e-b11dbe99ea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246920326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.2246920326
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.1187589815
Short name T1056
Test name
Test status
Simulation time 278468493 ps
CPU time 3.83 seconds
Started Jan 03 12:56:02 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 241264 kb
Host smart-9e7ab4ee-78d6-446a-a573-de726d568a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187589815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.1187589815
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.2262817771
Short name T535
Test name
Test status
Simulation time 327148324 ps
CPU time 4.06 seconds
Started Jan 03 12:55:44 PM PST 24
Finished Jan 03 12:57:04 PM PST 24
Peak memory 238432 kb
Host smart-400e2011-a4b1-4e4b-8ba3-5c824e0445d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262817771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.2262817771
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.3615684304
Short name T98
Test name
Test status
Simulation time 120913545 ps
CPU time 3.04 seconds
Started Jan 03 12:55:57 PM PST 24
Finished Jan 03 12:57:11 PM PST 24
Peak memory 240980 kb
Host smart-c1600f9a-6c4e-455b-88a5-a4365e8fca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615684304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.3615684304
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.4162732499
Short name T822
Test name
Test status
Simulation time 136400242 ps
CPU time 4.29 seconds
Started Jan 03 12:55:42 PM PST 24
Finished Jan 03 12:56:58 PM PST 24
Peak memory 240468 kb
Host smart-a3160480-9ce4-425f-8539-36642eb8f48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162732499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.4162732499
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.3093793473
Short name T83
Test name
Test status
Simulation time 2538675582 ps
CPU time 4.5 seconds
Started Jan 03 12:55:48 PM PST 24
Finished Jan 03 12:57:03 PM PST 24
Peak memory 238460 kb
Host smart-6093dcf8-172e-4b23-8b9a-141f979c7d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093793473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.3093793473
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.2589034588
Short name T994
Test name
Test status
Simulation time 1502347175 ps
CPU time 5.64 seconds
Started Jan 03 12:55:47 PM PST 24
Finished Jan 03 12:57:04 PM PST 24
Peak memory 246516 kb
Host smart-6669299a-740c-4bad-9bca-e94c900c0f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589034588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.2589034588
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.4246206104
Short name T983
Test name
Test status
Simulation time 155056074 ps
CPU time 3.23 seconds
Started Jan 03 12:55:44 PM PST 24
Finished Jan 03 12:57:00 PM PST 24
Peak memory 238264 kb
Host smart-8cb78f89-c46b-4d1a-9b18-93445ce80959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246206104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.4246206104
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.2458493809
Short name T510
Test name
Test status
Simulation time 543086107 ps
CPU time 3.77 seconds
Started Jan 03 12:55:48 PM PST 24
Finished Jan 03 12:57:02 PM PST 24
Peak memory 241236 kb
Host smart-e7969575-0296-4625-a3b6-5e9629cb7a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458493809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.2458493809
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.4185718131
Short name T806
Test name
Test status
Simulation time 936004666 ps
CPU time 6.23 seconds
Started Jan 03 12:55:47 PM PST 24
Finished Jan 03 12:57:04 PM PST 24
Peak memory 242836 kb
Host smart-5a81abb4-ef60-4535-ad56-a1f0fe586f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185718131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.4185718131
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.3723824165
Short name T157
Test name
Test status
Simulation time 188702407 ps
CPU time 3.97 seconds
Started Jan 03 12:55:59 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 240556 kb
Host smart-d1f4bf24-1c45-47e2-852e-9a5be99bcf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723824165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.3723824165
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.50210504
Short name T884
Test name
Test status
Simulation time 615704129 ps
CPU time 4.88 seconds
Started Jan 03 12:56:00 PM PST 24
Finished Jan 03 12:57:13 PM PST 24
Peak memory 246692 kb
Host smart-9f2ee086-7698-4c6a-a995-cb206af6eeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50210504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.50210504
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.4040320399
Short name T756
Test name
Test status
Simulation time 167972142 ps
CPU time 3.32 seconds
Started Jan 03 12:56:00 PM PST 24
Finished Jan 03 12:57:12 PM PST 24
Peak memory 238500 kb
Host smart-12d428d6-5198-4ebe-96b2-ff6744db2861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040320399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.4040320399
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.1488294742
Short name T501
Test name
Test status
Simulation time 320344047 ps
CPU time 4.8 seconds
Started Jan 03 12:55:44 PM PST 24
Finished Jan 03 12:57:09 PM PST 24
Peak memory 243064 kb
Host smart-945457d8-6997-4b0c-a50d-441ffe0219e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488294742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.1488294742
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.666982698
Short name T160
Test name
Test status
Simulation time 48900668 ps
CPU time 1.49 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:06 PM PST 24
Peak memory 238392 kb
Host smart-181ad50d-0819-4e1a-8552-8ae268cf3689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666982698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.666982698
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.1222036393
Short name T907
Test name
Test status
Simulation time 383557165 ps
CPU time 10.08 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:55:10 PM PST 24
Peak memory 238496 kb
Host smart-d90489fe-de69-48d6-8992-3ff1173fa81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222036393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.1222036393
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.2323540410
Short name T980
Test name
Test status
Simulation time 6993906351 ps
CPU time 11.11 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:54:57 PM PST 24
Peak memory 238616 kb
Host smart-c84700a1-b0a0-4685-9f64-0bb54d6e3222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323540410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.2323540410
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.1586633389
Short name T834
Test name
Test status
Simulation time 2244767251 ps
CPU time 5.73 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:45 PM PST 24
Peak memory 238444 kb
Host smart-411cad51-f45c-4686-ace5-62b4f2aee898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586633389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.1586633389
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.3991205967
Short name T887
Test name
Test status
Simulation time 953072277 ps
CPU time 10.98 seconds
Started Jan 03 12:53:49 PM PST 24
Finished Jan 03 12:55:27 PM PST 24
Peak memory 246004 kb
Host smart-11bdd19e-40df-4cab-93a7-dba0b98dfcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991205967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.3991205967
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.3114586195
Short name T146
Test name
Test status
Simulation time 3967213596 ps
CPU time 10.25 seconds
Started Jan 03 12:53:56 PM PST 24
Finished Jan 03 12:55:38 PM PST 24
Peak memory 238520 kb
Host smart-bc8fcaa7-9bee-41f0-ab92-bc49bfe315d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114586195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.3114586195
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.986745342
Short name T183
Test name
Test status
Simulation time 135290460 ps
CPU time 2.84 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:55:45 PM PST 24
Peak memory 238180 kb
Host smart-5ffe0e26-6eec-4792-aac5-cf17e255314b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986745342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.986745342
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.74476835
Short name T790
Test name
Test status
Simulation time 494711870 ps
CPU time 12.12 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:54:59 PM PST 24
Peak memory 243544 kb
Host smart-bb978714-d771-42f0-a6e5-9e253eefeda3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74476835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.74476835
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.39563224
Short name T1102
Test name
Test status
Simulation time 246343196 ps
CPU time 6.77 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:55:31 PM PST 24
Peak memory 238568 kb
Host smart-9f5b780e-a4a9-4dc6-95c1-99a13e8c1d79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39563224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.39563224
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.1952361843
Short name T257
Test name
Test status
Simulation time 1089536383 ps
CPU time 9.05 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:54:47 PM PST 24
Peak memory 243752 kb
Host smart-67e00795-ac24-4459-8fac-865a01ff8a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952361843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.1952361843
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.2933812716
Short name T1106
Test name
Test status
Simulation time 1076121135 ps
CPU time 11.9 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:08 PM PST 24
Peak memory 238396 kb
Host smart-3cc17186-57e4-4dff-8a51-da91080f9546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933812716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.2933812716
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.619602593
Short name T221
Test name
Test status
Simulation time 235394205977 ps
CPU time 2782.78 seconds
Started Jan 03 12:54:00 PM PST 24
Finished Jan 03 01:42:00 PM PST 24
Peak memory 942348 kb
Host smart-c0eb22c0-acc0-46bc-8512-c5c33ba7bbc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619602593 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.619602593
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.1875252636
Short name T496
Test name
Test status
Simulation time 1496870757 ps
CPU time 15.09 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:15 PM PST 24
Peak memory 237392 kb
Host smart-40e187f6-ff6e-4cd2-ae24-2beabf5abfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875252636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.1875252636
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.4131425367
Short name T914
Test name
Test status
Simulation time 621623022 ps
CPU time 4.05 seconds
Started Jan 03 12:55:48 PM PST 24
Finished Jan 03 12:57:03 PM PST 24
Peak memory 241008 kb
Host smart-dc21be04-c305-4368-89cc-95be90411475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131425367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.4131425367
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.3430646210
Short name T472
Test name
Test status
Simulation time 3865027353 ps
CPU time 8.52 seconds
Started Jan 03 12:55:57 PM PST 24
Finished Jan 03 12:57:14 PM PST 24
Peak memory 244008 kb
Host smart-69f8b538-4d84-4f67-ab09-e5de2ee54548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430646210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.3430646210
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.2680067741
Short name T683
Test name
Test status
Simulation time 288078585 ps
CPU time 3.66 seconds
Started Jan 03 12:55:49 PM PST 24
Finished Jan 03 12:57:02 PM PST 24
Peak memory 238320 kb
Host smart-0ec5566d-84f0-4d64-a051-e2e17e3c4950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680067741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.2680067741
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.1640954942
Short name T969
Test name
Test status
Simulation time 226364154 ps
CPU time 6.13 seconds
Started Jan 03 12:55:51 PM PST 24
Finished Jan 03 12:57:08 PM PST 24
Peak memory 238404 kb
Host smart-61fc261c-7dfd-4e7a-99a7-96eb31cf65fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640954942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.1640954942
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.3977767002
Short name T838
Test name
Test status
Simulation time 454147363 ps
CPU time 3.77 seconds
Started Jan 03 12:55:48 PM PST 24
Finished Jan 03 12:57:03 PM PST 24
Peak memory 240424 kb
Host smart-04450306-ec61-4e3b-9a53-315b395161f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977767002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.3977767002
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.116378082
Short name T354
Test name
Test status
Simulation time 150169211 ps
CPU time 6.66 seconds
Started Jan 03 12:55:47 PM PST 24
Finished Jan 03 12:57:06 PM PST 24
Peak memory 238464 kb
Host smart-95144abd-c592-4b49-a3f4-d23ab22b03b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116378082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.116378082
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.497039897
Short name T730
Test name
Test status
Simulation time 115764331 ps
CPU time 3.65 seconds
Started Jan 03 12:55:49 PM PST 24
Finished Jan 03 12:57:03 PM PST 24
Peak memory 238352 kb
Host smart-bf2387b9-ea77-4e92-869d-1eadb8ff3caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497039897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.497039897
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.2812377189
Short name T927
Test name
Test status
Simulation time 282176442 ps
CPU time 3.86 seconds
Started Jan 03 12:55:44 PM PST 24
Finished Jan 03 12:57:01 PM PST 24
Peak memory 242060 kb
Host smart-58098f4d-e31b-42a3-ac69-a05a27b92591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812377189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.2812377189
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.2125084113
Short name T708
Test name
Test status
Simulation time 640601162 ps
CPU time 7.11 seconds
Started Jan 03 12:56:12 PM PST 24
Finished Jan 03 12:57:28 PM PST 24
Peak memory 243512 kb
Host smart-35c5d4f0-cc9a-4b6d-8c53-ce9e8da4767d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125084113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.2125084113
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.2350358512
Short name T20
Test name
Test status
Simulation time 246708092 ps
CPU time 3.92 seconds
Started Jan 03 12:55:57 PM PST 24
Finished Jan 03 12:57:10 PM PST 24
Peak memory 246652 kb
Host smart-9556d1d3-43c1-4cdd-aebf-832e00e64804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350358512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.2350358512
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.3127765805
Short name T612
Test name
Test status
Simulation time 336882243 ps
CPU time 8.18 seconds
Started Jan 03 12:55:44 PM PST 24
Finished Jan 03 12:57:04 PM PST 24
Peak memory 244144 kb
Host smart-1f9a546b-118f-4035-b36d-d816e136381e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127765805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.3127765805
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.3218471554
Short name T72
Test name
Test status
Simulation time 296733090 ps
CPU time 3.85 seconds
Started Jan 03 12:56:00 PM PST 24
Finished Jan 03 12:57:19 PM PST 24
Peak memory 238392 kb
Host smart-b83ab09c-0e24-4e90-af2a-674cb2a7834b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218471554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.3218471554
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.1482725652
Short name T1038
Test name
Test status
Simulation time 521928689 ps
CPU time 6.85 seconds
Started Jan 03 12:55:47 PM PST 24
Finished Jan 03 12:57:09 PM PST 24
Peak memory 243052 kb
Host smart-4df7674a-e8b7-4776-b758-0808a76003a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482725652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.1482725652
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.2105026020
Short name T434
Test name
Test status
Simulation time 1693102382 ps
CPU time 4.78 seconds
Started Jan 03 12:55:44 PM PST 24
Finished Jan 03 12:57:08 PM PST 24
Peak memory 240324 kb
Host smart-97cdae54-62b3-4daa-b371-b2426e763802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105026020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.2105026020
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.1503084285
Short name T571
Test name
Test status
Simulation time 882364089 ps
CPU time 7.91 seconds
Started Jan 03 12:55:57 PM PST 24
Finished Jan 03 12:57:14 PM PST 24
Peak memory 238448 kb
Host smart-30791de9-5d5e-4f92-bc73-6d3b4340e95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503084285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.1503084285
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.630528493
Short name T419
Test name
Test status
Simulation time 298219563 ps
CPU time 3.76 seconds
Started Jan 03 12:55:47 PM PST 24
Finished Jan 03 12:57:02 PM PST 24
Peak memory 238416 kb
Host smart-17af0f06-2973-4f1d-bd5b-d0d5cebcfe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630528493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.630528493
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.1540449137
Short name T654
Test name
Test status
Simulation time 522988711 ps
CPU time 7.04 seconds
Started Jan 03 12:55:49 PM PST 24
Finished Jan 03 12:57:09 PM PST 24
Peak memory 244416 kb
Host smart-393fa62b-f68e-49e8-a943-592d418a759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540449137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.1540449137
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.107758553
Short name T547
Test name
Test status
Simulation time 446459192 ps
CPU time 4.79 seconds
Started Jan 03 12:55:56 PM PST 24
Finished Jan 03 12:57:20 PM PST 24
Peak memory 241140 kb
Host smart-ee9acb2e-fe01-4e3f-9a55-9d5d35413c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107758553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.107758553
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.3436291254
Short name T186
Test name
Test status
Simulation time 265511946 ps
CPU time 3.91 seconds
Started Jan 03 12:55:49 PM PST 24
Finished Jan 03 12:57:06 PM PST 24
Peak memory 241492 kb
Host smart-0e4a9e54-918a-43e0-983f-602cd0e08ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436291254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.3436291254
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.3294891759
Short name T622
Test name
Test status
Simulation time 143508659 ps
CPU time 1.96 seconds
Started Jan 03 12:54:00 PM PST 24
Finished Jan 03 12:55:39 PM PST 24
Peak memory 238500 kb
Host smart-2276fc63-cfb4-48b7-b0fd-8d6613294159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294891759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.3294891759
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.303838204
Short name T33
Test name
Test status
Simulation time 702398993 ps
CPU time 18.9 seconds
Started Jan 03 12:53:49 PM PST 24
Finished Jan 03 12:55:24 PM PST 24
Peak memory 246608 kb
Host smart-fb302a8c-7d48-4103-bf2b-67937b3e90f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303838204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.303838204
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.1003543938
Short name T9
Test name
Test status
Simulation time 1253919892 ps
CPU time 8.53 seconds
Started Jan 03 12:53:27 PM PST 24
Finished Jan 03 12:54:38 PM PST 24
Peak memory 238412 kb
Host smart-2e89953c-5aa4-417f-aa40-7103d9daedfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003543938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.1003543938
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.2025895818
Short name T913
Test name
Test status
Simulation time 352322019 ps
CPU time 9.65 seconds
Started Jan 03 12:54:00 PM PST 24
Finished Jan 03 12:55:43 PM PST 24
Peak memory 243184 kb
Host smart-6901cefe-b973-4181-829d-d1749be8ba92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025895818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.2025895818
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.1325826157
Short name T727
Test name
Test status
Simulation time 266713506 ps
CPU time 3.69 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:49 PM PST 24
Peak memory 238364 kb
Host smart-22ab488a-bd29-4f57-b02d-58ac46f8677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325826157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.1325826157
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.2312502550
Short name T1101
Test name
Test status
Simulation time 2560912989 ps
CPU time 15.5 seconds
Started Jan 03 12:53:12 PM PST 24
Finished Jan 03 12:54:38 PM PST 24
Peak memory 246728 kb
Host smart-41aabb27-c99c-45c9-a98f-5cbbb28e7483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312502550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.2312502550
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.2079741658
Short name T439
Test name
Test status
Simulation time 703564120 ps
CPU time 13.41 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:55:29 PM PST 24
Peak memory 238396 kb
Host smart-ca49b3ed-8e7c-4646-8afc-691bf7cc4fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079741658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.2079741658
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.4292059038
Short name T414
Test name
Test status
Simulation time 300597500 ps
CPU time 5.72 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:51 PM PST 24
Peak memory 246568 kb
Host smart-da53826d-d3de-462b-8c13-9329dc0b61e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292059038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.4292059038
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.20381154
Short name T946
Test name
Test status
Simulation time 1517323351 ps
CPU time 11.01 seconds
Started Jan 03 12:53:14 PM PST 24
Finished Jan 03 12:54:25 PM PST 24
Peak memory 238388 kb
Host smart-c5712f05-0b0e-4c7b-9a5c-bfd8235aba87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20381154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.20381154
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.1808108368
Short name T1076
Test name
Test status
Simulation time 157809991 ps
CPU time 3.2 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:54:59 PM PST 24
Peak memory 243344 kb
Host smart-174f9e30-51a7-4f6d-b710-7e7e6a59dc3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1808108368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.1808108368
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.2725227941
Short name T230
Test name
Test status
Simulation time 1674872277 ps
CPU time 4.81 seconds
Started Jan 03 12:53:59 PM PST 24
Finished Jan 03 12:55:40 PM PST 24
Peak memory 238432 kb
Host smart-4bc46f20-557c-40c5-8eb2-2d70b5d577af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725227941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2725227941
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.867474760
Short name T966
Test name
Test status
Simulation time 298242841 ps
CPU time 5.96 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:55:21 PM PST 24
Peak memory 243692 kb
Host smart-04c5dbde-d387-46cf-9614-c0d58eca1f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867474760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.867474760
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.654332449
Short name T728
Test name
Test status
Simulation time 95450526 ps
CPU time 2.95 seconds
Started Jan 03 12:55:47 PM PST 24
Finished Jan 03 12:57:01 PM PST 24
Peak memory 238412 kb
Host smart-fa451f97-538f-46f1-935e-04b61af4a059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654332449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.654332449
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.3387883283
Short name T483
Test name
Test status
Simulation time 154254199 ps
CPU time 4.72 seconds
Started Jan 03 12:55:43 PM PST 24
Finished Jan 03 12:57:02 PM PST 24
Peak memory 241200 kb
Host smart-7b8d2206-ebc3-4d10-b25f-9d6eb84c42bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387883283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3387883283
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.427195569
Short name T382
Test name
Test status
Simulation time 169015633 ps
CPU time 4.2 seconds
Started Jan 03 12:55:47 PM PST 24
Finished Jan 03 12:57:02 PM PST 24
Peak memory 238412 kb
Host smart-689dab41-6be8-4c58-a2fb-f43efdc55cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427195569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.427195569
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.186626932
Short name T1005
Test name
Test status
Simulation time 1579154604 ps
CPU time 5.17 seconds
Started Jan 03 12:56:04 PM PST 24
Finished Jan 03 12:57:17 PM PST 24
Peak memory 241076 kb
Host smart-3e4f28c4-5930-47a6-a01d-8c7080c1141d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186626932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.186626932
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.465481956
Short name T778
Test name
Test status
Simulation time 277457384 ps
CPU time 4.82 seconds
Started Jan 03 12:55:49 PM PST 24
Finished Jan 03 12:57:04 PM PST 24
Peak memory 246544 kb
Host smart-fc0e8333-58cd-4595-b9ef-4b8e52c0e2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465481956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.465481956
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.3458102937
Short name T481
Test name
Test status
Simulation time 138839290 ps
CPU time 2.38 seconds
Started Jan 03 12:56:05 PM PST 24
Finished Jan 03 12:57:14 PM PST 24
Peak memory 240848 kb
Host smart-41901ba1-9434-4df8-83d0-81daf975d71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458102937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.3458102937
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.1396963455
Short name T404
Test name
Test status
Simulation time 185908660 ps
CPU time 4.66 seconds
Started Jan 03 12:55:49 PM PST 24
Finished Jan 03 12:57:03 PM PST 24
Peak memory 241048 kb
Host smart-442d74ea-27f2-414b-9faf-10ef077db225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396963455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.1396963455
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.221411642
Short name T420
Test name
Test status
Simulation time 133126332 ps
CPU time 4.32 seconds
Started Jan 03 12:56:01 PM PST 24
Finished Jan 03 12:57:14 PM PST 24
Peak memory 238340 kb
Host smart-c8d4a5b9-e1be-4de6-bf22-88728e36425a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221411642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.221411642
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.2886461254
Short name T577
Test name
Test status
Simulation time 444073744 ps
CPU time 3.21 seconds
Started Jan 03 12:55:44 PM PST 24
Finished Jan 03 12:57:08 PM PST 24
Peak memory 238336 kb
Host smart-a8355153-bed0-41a0-b13d-af7fdcfef211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886461254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.2886461254
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.2983384920
Short name T805
Test name
Test status
Simulation time 2595755673 ps
CPU time 4.73 seconds
Started Jan 03 12:56:04 PM PST 24
Finished Jan 03 12:57:17 PM PST 24
Peak memory 241848 kb
Host smart-ba711c52-6c38-4770-81f9-77853165d16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983384920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.2983384920
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.2007475297
Short name T889
Test name
Test status
Simulation time 177500146 ps
CPU time 4.07 seconds
Started Jan 03 12:55:47 PM PST 24
Finished Jan 03 12:57:11 PM PST 24
Peak memory 240676 kb
Host smart-2688a8fb-9d92-4b34-9a7a-c6d9e76a0268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007475297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2007475297
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.1502035007
Short name T634
Test name
Test status
Simulation time 222558594 ps
CPU time 4.44 seconds
Started Jan 03 12:56:04 PM PST 24
Finished Jan 03 12:57:16 PM PST 24
Peak memory 242704 kb
Host smart-1627d3fe-8d4a-4245-84af-072b76ac62d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502035007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.1502035007
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.3337148149
Short name T1063
Test name
Test status
Simulation time 99035510 ps
CPU time 3.31 seconds
Started Jan 03 12:56:01 PM PST 24
Finished Jan 03 12:57:13 PM PST 24
Peak memory 238372 kb
Host smart-8eba623b-f82f-47a7-bfdf-5fd15df690c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337148149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.3337148149
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.295988089
Short name T775
Test name
Test status
Simulation time 263968174 ps
CPU time 6.75 seconds
Started Jan 03 12:56:01 PM PST 24
Finished Jan 03 12:57:16 PM PST 24
Peak memory 238452 kb
Host smart-24a6dbc6-7895-46d9-baab-14e824ef1040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295988089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.295988089
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.1844805074
Short name T1014
Test name
Test status
Simulation time 423638655 ps
CPU time 4.26 seconds
Started Jan 03 12:55:56 PM PST 24
Finished Jan 03 12:57:20 PM PST 24
Peak memory 241148 kb
Host smart-6aa7408a-1fc3-4029-94f8-7590025c5bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844805074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.1844805074
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.4117301491
Short name T469
Test name
Test status
Simulation time 224769259 ps
CPU time 3.12 seconds
Started Jan 03 12:56:00 PM PST 24
Finished Jan 03 12:57:20 PM PST 24
Peak memory 238348 kb
Host smart-dd233f90-f83c-49e6-9737-fec8619ed0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117301491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.4117301491
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.2098889669
Short name T124
Test name
Test status
Simulation time 156092744 ps
CPU time 3.38 seconds
Started Jan 03 12:55:56 PM PST 24
Finished Jan 03 12:57:19 PM PST 24
Peak memory 238400 kb
Host smart-2fd3e827-80ca-4cba-87a2-e4450d0bd4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098889669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.2098889669
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.1356725400
Short name T637
Test name
Test status
Simulation time 1532532293 ps
CPU time 3.52 seconds
Started Jan 03 12:55:59 PM PST 24
Finished Jan 03 12:57:13 PM PST 24
Peak memory 238372 kb
Host smart-fea2d7f6-fa4f-404d-a292-13a998d6a40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356725400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.1356725400
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.2412226997
Short name T812
Test name
Test status
Simulation time 174723536 ps
CPU time 4.01 seconds
Started Jan 03 12:55:56 PM PST 24
Finished Jan 03 12:57:19 PM PST 24
Peak memory 238492 kb
Host smart-ac53542e-5266-4a9c-83ab-ed92b9913c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412226997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.2412226997
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.3878015055
Short name T537
Test name
Test status
Simulation time 555629824 ps
CPU time 6.41 seconds
Started Jan 03 12:56:00 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 238508 kb
Host smart-6c6d8dd0-8d1d-4723-9a73-f2b364a777d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878015055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.3878015055
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.3307882911
Short name T364
Test name
Test status
Simulation time 93298521 ps
CPU time 1.97 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:54:52 PM PST 24
Peak memory 238720 kb
Host smart-82fc200f-bbc2-4c3b-a329-12e650d38968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307882911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.3307882911
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.2735570521
Short name T706
Test name
Test status
Simulation time 318128542 ps
CPU time 3.27 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:54:32 PM PST 24
Peak memory 241724 kb
Host smart-5e300e00-d6e2-4e40-a2fd-df84c79f168c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735570521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.2735570521
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.3117994879
Short name T587
Test name
Test status
Simulation time 121828935 ps
CPU time 4.21 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:15 PM PST 24
Peak memory 238244 kb
Host smart-e349795f-4aa0-47b6-ab29-0fb11146376f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117994879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.3117994879
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.768201884
Short name T1067
Test name
Test status
Simulation time 473607782 ps
CPU time 13.1 seconds
Started Jan 03 12:53:56 PM PST 24
Finished Jan 03 12:55:40 PM PST 24
Peak memory 238492 kb
Host smart-4a29072c-6ed3-4265-99cc-0be7c2b82a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768201884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.768201884
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.628220310
Short name T757
Test name
Test status
Simulation time 131055263 ps
CPU time 3.15 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:03 PM PST 24
Peak memory 238332 kb
Host smart-3424ea7a-3453-400b-8ba0-9701078b5bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628220310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.628220310
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.3332457132
Short name T895
Test name
Test status
Simulation time 806074925 ps
CPU time 19.79 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:12 PM PST 24
Peak memory 246760 kb
Host smart-500f3df6-0216-4579-b474-85e16afa5b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332457132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.3332457132
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.1589473162
Short name T715
Test name
Test status
Simulation time 438681092 ps
CPU time 4.52 seconds
Started Jan 03 12:53:33 PM PST 24
Finished Jan 03 12:54:31 PM PST 24
Peak memory 238400 kb
Host smart-8ef4709a-e050-4063-af66-3d8b2b7f11a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589473162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.1589473162
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.1850161386
Short name T1058
Test name
Test status
Simulation time 163867030 ps
CPU time 3.75 seconds
Started Jan 03 12:53:51 PM PST 24
Finished Jan 03 12:55:14 PM PST 24
Peak memory 238356 kb
Host smart-cb3275ca-6e23-4acb-98e2-5fc8c4c10e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850161386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.1850161386
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.3201115866
Short name T691
Test name
Test status
Simulation time 505130825 ps
CPU time 7.25 seconds
Started Jan 03 12:53:54 PM PST 24
Finished Jan 03 12:55:35 PM PST 24
Peak memory 238416 kb
Host smart-941ca420-349d-4f5f-8b1e-c971bcefa1a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3201115866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.3201115866
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.2721274493
Short name T431
Test name
Test status
Simulation time 444492563 ps
CPU time 3.18 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:54:48 PM PST 24
Peak memory 238260 kb
Host smart-5e35427d-da3b-46f5-b3ed-34750a9a21b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721274493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.2721274493
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.4198909381
Short name T1040
Test name
Test status
Simulation time 435270629777 ps
CPU time 5718.21 seconds
Started Jan 03 12:54:07 PM PST 24
Finished Jan 03 02:31:06 PM PST 24
Peak memory 1418744 kb
Host smart-f290fed6-8f3d-45da-9b63-1203744f0ed6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198909381 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.4198909381
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.459213355
Short name T105
Test name
Test status
Simulation time 489403207 ps
CPU time 6.14 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:55:02 PM PST 24
Peak memory 243248 kb
Host smart-539a5c86-8e65-4b1f-975a-8be7df1effc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459213355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.459213355
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.3418903911
Short name T421
Test name
Test status
Simulation time 96079759 ps
CPU time 2.88 seconds
Started Jan 03 12:55:58 PM PST 24
Finished Jan 03 12:57:09 PM PST 24
Peak memory 241320 kb
Host smart-b0b0695d-f2fa-4cd9-afce-d359a6cf93c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418903911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.3418903911
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.3630783317
Short name T456
Test name
Test status
Simulation time 279562076 ps
CPU time 3.9 seconds
Started Jan 03 12:55:59 PM PST 24
Finished Jan 03 12:57:14 PM PST 24
Peak memory 238384 kb
Host smart-7c337294-2afe-4b8d-9599-0b3e1b71d9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630783317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.3630783317
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.2749612366
Short name T351
Test name
Test status
Simulation time 175372040 ps
CPU time 4.89 seconds
Started Jan 03 12:56:00 PM PST 24
Finished Jan 03 12:57:24 PM PST 24
Peak memory 242872 kb
Host smart-b5d823ee-2e7c-4743-9749-4a8b7173cf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749612366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2749612366
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.2772937579
Short name T461
Test name
Test status
Simulation time 316052017 ps
CPU time 3.92 seconds
Started Jan 03 12:55:59 PM PST 24
Finished Jan 03 12:57:14 PM PST 24
Peak memory 241188 kb
Host smart-dd636ef5-bd58-4132-b94a-1d0fa24bb74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772937579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.2772937579
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.77663062
Short name T1091
Test name
Test status
Simulation time 1935766196 ps
CPU time 6.68 seconds
Started Jan 03 12:55:56 PM PST 24
Finished Jan 03 12:57:22 PM PST 24
Peak memory 243520 kb
Host smart-59c977d0-dffd-41d4-bbe7-c4e1d3edff68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77663062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.77663062
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.3681091049
Short name T580
Test name
Test status
Simulation time 161828632 ps
CPU time 3 seconds
Started Jan 03 12:55:57 PM PST 24
Finished Jan 03 12:57:10 PM PST 24
Peak memory 238200 kb
Host smart-af900ef5-4d22-4846-8f94-9ec1efc707e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681091049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.3681091049
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.3160962071
Short name T569
Test name
Test status
Simulation time 133279564 ps
CPU time 4.32 seconds
Started Jan 03 12:56:01 PM PST 24
Finished Jan 03 12:57:13 PM PST 24
Peak memory 238424 kb
Host smart-8586010d-bdac-47f8-9d14-0c430ecd9dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160962071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.3160962071
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.2958299525
Short name T620
Test name
Test status
Simulation time 581552870 ps
CPU time 4.45 seconds
Started Jan 03 12:55:57 PM PST 24
Finished Jan 03 12:57:12 PM PST 24
Peak memory 240612 kb
Host smart-47078b4f-ca52-4c54-ac73-195939382e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958299525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.2958299525
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.2749542778
Short name T997
Test name
Test status
Simulation time 87912853 ps
CPU time 2.98 seconds
Started Jan 03 12:55:59 PM PST 24
Finished Jan 03 12:57:13 PM PST 24
Peak memory 241296 kb
Host smart-7210a1bf-f15c-4632-976c-4b244340b8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749542778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.2749542778
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.4016453487
Short name T1015
Test name
Test status
Simulation time 177656732 ps
CPU time 4.64 seconds
Started Jan 03 12:56:01 PM PST 24
Finished Jan 03 12:57:13 PM PST 24
Peak memory 240512 kb
Host smart-86279021-487e-41c8-b5f0-e204856d9ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016453487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.4016453487
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.1011415875
Short name T338
Test name
Test status
Simulation time 190293919 ps
CPU time 5.88 seconds
Started Jan 03 12:56:00 PM PST 24
Finished Jan 03 12:57:20 PM PST 24
Peak memory 241224 kb
Host smart-d9b8eb58-0801-4d81-952f-15bb216a92fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011415875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.1011415875
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.2631380737
Short name T625
Test name
Test status
Simulation time 2046836918 ps
CPU time 4.42 seconds
Started Jan 03 12:56:02 PM PST 24
Finished Jan 03 12:57:13 PM PST 24
Peak memory 240536 kb
Host smart-7e6d4ed9-fc60-41d3-b06d-bb33fffae831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631380737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.2631380737
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.650823165
Short name T1039
Test name
Test status
Simulation time 157776996 ps
CPU time 6.46 seconds
Started Jan 03 12:56:01 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 242260 kb
Host smart-faf97b82-1265-4ec0-8d5b-d2c9b7e86abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650823165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.650823165
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.989806312
Short name T1111
Test name
Test status
Simulation time 365448109 ps
CPU time 3.53 seconds
Started Jan 03 12:56:01 PM PST 24
Finished Jan 03 12:57:13 PM PST 24
Peak memory 240480 kb
Host smart-c2958cb0-2add-4bc2-b12e-8107b5d7f3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989806312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.989806312
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.4133151854
Short name T744
Test name
Test status
Simulation time 256187114 ps
CPU time 4.74 seconds
Started Jan 03 12:56:36 PM PST 24
Finished Jan 03 12:57:50 PM PST 24
Peak memory 238504 kb
Host smart-85fd849a-4d85-40f1-919d-3d806dee8fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133151854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.4133151854
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.235438983
Short name T794
Test name
Test status
Simulation time 347523431 ps
CPU time 6.01 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:19 PM PST 24
Peak memory 238420 kb
Host smart-a6439faf-b732-4c81-8a6a-7d39c3687dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235438983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.235438983
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.946693255
Short name T128
Test name
Test status
Simulation time 469255895 ps
CPU time 3.97 seconds
Started Jan 03 12:56:04 PM PST 24
Finished Jan 03 12:57:16 PM PST 24
Peak memory 238380 kb
Host smart-c55be629-d292-4b09-be5a-b4472d9d29d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946693255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.946693255
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.96716420
Short name T1007
Test name
Test status
Simulation time 2837656541 ps
CPU time 4.87 seconds
Started Jan 03 12:56:05 PM PST 24
Finished Jan 03 12:57:17 PM PST 24
Peak memory 238604 kb
Host smart-99077bb8-c986-4020-ac05-f2fd0df16b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96716420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.96716420
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.4095690673
Short name T2
Test name
Test status
Simulation time 80807990 ps
CPU time 1.49 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:54:39 PM PST 24
Peak memory 238064 kb
Host smart-4cb8c850-fbdb-4b8b-a83b-e533b625a566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095690673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.4095690673
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.948353389
Short name T69
Test name
Test status
Simulation time 4025025229 ps
CPU time 19.48 seconds
Started Jan 03 12:53:43 PM PST 24
Finished Jan 03 12:55:04 PM PST 24
Peak memory 238728 kb
Host smart-6067852f-96d8-44d0-af99-20fc14ad7f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948353389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.948353389
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.1437141360
Short name T491
Test name
Test status
Simulation time 323601310 ps
CPU time 6.92 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:55:24 PM PST 24
Peak memory 238536 kb
Host smart-1d37ffeb-883f-48a8-9c79-4f72f1521347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437141360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.1437141360
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.1357664273
Short name T740
Test name
Test status
Simulation time 2565793006 ps
CPU time 9.67 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:15 PM PST 24
Peak memory 237704 kb
Host smart-f0d3ad9a-c2ff-44fd-a7e3-67e1fd2c1036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357664273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.1357664273
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.3657558750
Short name T36
Test name
Test status
Simulation time 187228944 ps
CPU time 4.04 seconds
Started Jan 03 12:54:08 PM PST 24
Finished Jan 03 12:55:52 PM PST 24
Peak memory 246524 kb
Host smart-4131d3c6-ac45-4a5c-975d-a229c829809a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657558750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.3657558750
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.2848242306
Short name T386
Test name
Test status
Simulation time 2990896740 ps
CPU time 3.92 seconds
Started Jan 03 12:53:31 PM PST 24
Finished Jan 03 12:54:28 PM PST 24
Peak memory 238680 kb
Host smart-0b0031a5-8bb4-466f-a75c-3fe25399c956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848242306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.2848242306
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.1835469237
Short name T452
Test name
Test status
Simulation time 5063826129 ps
CPU time 9.55 seconds
Started Jan 03 12:53:30 PM PST 24
Finished Jan 03 12:54:34 PM PST 24
Peak memory 243460 kb
Host smart-3ac61220-b660-45e1-b411-8817ad5e1d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835469237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.1835469237
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.294274297
Short name T1123
Test name
Test status
Simulation time 114726833 ps
CPU time 3.31 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:14 PM PST 24
Peak memory 238404 kb
Host smart-79c440ac-becc-443b-84db-50af25c4301d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294274297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.294274297
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.3974839214
Short name T603
Test name
Test status
Simulation time 10989022767 ps
CPU time 32.11 seconds
Started Jan 03 12:54:00 PM PST 24
Finished Jan 03 12:56:08 PM PST 24
Peak memory 244504 kb
Host smart-3555e364-35c0-4a1e-994b-24e3a2db05ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3974839214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.3974839214
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.1836310652
Short name T1129
Test name
Test status
Simulation time 149851023 ps
CPU time 3.86 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:55:25 PM PST 24
Peak memory 243844 kb
Host smart-24622107-05be-47c9-ac9f-59debacd8d4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1836310652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1836310652
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.3821638053
Short name T993
Test name
Test status
Simulation time 750246611 ps
CPU time 4.75 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:54:43 PM PST 24
Peak memory 242980 kb
Host smart-997e1a52-753d-403b-98ed-ff9429aecd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821638053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.3821638053
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.3479145462
Short name T653
Test name
Test status
Simulation time 8508840886 ps
CPU time 87.4 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:55:56 PM PST 24
Peak memory 240100 kb
Host smart-b0251e28-f342-4023-a483-e19fa5d2e0cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479145462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.3479145462
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.870679180
Short name T1095
Test name
Test status
Simulation time 326221851867 ps
CPU time 4467.18 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 02:09:06 PM PST 24
Peak memory 266068 kb
Host smart-dfcad167-164e-47d1-aab4-e1adbe045e70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870679180 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.870679180
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.498527364
Short name T166
Test name
Test status
Simulation time 1208028354 ps
CPU time 11.44 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:54:53 PM PST 24
Peak memory 243904 kb
Host smart-bb51930f-9bdb-478c-bffe-7b35cf11d1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498527364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.498527364
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.3688541512
Short name T546
Test name
Test status
Simulation time 106890802 ps
CPU time 3.43 seconds
Started Jan 03 12:56:09 PM PST 24
Finished Jan 03 12:57:20 PM PST 24
Peak memory 239984 kb
Host smart-71360a66-b9de-4bfc-be0e-746824dfcf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688541512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3688541512
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.3278651652
Short name T733
Test name
Test status
Simulation time 228367607 ps
CPU time 3.46 seconds
Started Jan 03 12:56:07 PM PST 24
Finished Jan 03 12:57:18 PM PST 24
Peak memory 241160 kb
Host smart-84e23d5a-1a16-4fe5-b68d-925eb2d4295e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278651652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3278651652
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.3423504299
Short name T430
Test name
Test status
Simulation time 450945939 ps
CPU time 4.52 seconds
Started Jan 03 12:56:00 PM PST 24
Finished Jan 03 12:57:13 PM PST 24
Peak memory 238424 kb
Host smart-d6b30cea-ade4-4b9a-a050-7a7db739c211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423504299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3423504299
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.733079217
Short name T356
Test name
Test status
Simulation time 411290666 ps
CPU time 5.46 seconds
Started Jan 03 12:56:05 PM PST 24
Finished Jan 03 12:57:18 PM PST 24
Peak memory 242684 kb
Host smart-0a25046d-b2aa-400b-aeef-70279f1c4c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733079217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.733079217
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.2580079256
Short name T133
Test name
Test status
Simulation time 505732776 ps
CPU time 3.14 seconds
Started Jan 03 12:56:04 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 238360 kb
Host smart-76fe615b-3fea-4ecb-a0f9-eaec8cd53e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580079256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.2580079256
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.1916336217
Short name T652
Test name
Test status
Simulation time 117827623 ps
CPU time 2.99 seconds
Started Jan 03 12:56:35 PM PST 24
Finished Jan 03 12:57:48 PM PST 24
Peak memory 242064 kb
Host smart-d729bd4f-bc2f-4f93-825d-6d9a06ca10ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916336217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.1916336217
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.3932970973
Short name T464
Test name
Test status
Simulation time 119615062 ps
CPU time 4.35 seconds
Started Jan 03 12:56:02 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 238436 kb
Host smart-a61dc32c-c18d-4476-ab52-e31ac2c08ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932970973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.3932970973
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.714609802
Short name T320
Test name
Test status
Simulation time 257624668 ps
CPU time 3.41 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:22 PM PST 24
Peak memory 242152 kb
Host smart-e387e767-2506-479a-b15a-4c12b26e940e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714609802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.714609802
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.866256555
Short name T468
Test name
Test status
Simulation time 140948074 ps
CPU time 4.24 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:22 PM PST 24
Peak memory 238408 kb
Host smart-d99ccf4a-e822-400f-9737-a546437f57b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866256555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.866256555
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.2872135468
Short name T470
Test name
Test status
Simulation time 543757755 ps
CPU time 4.26 seconds
Started Jan 03 12:56:02 PM PST 24
Finished Jan 03 12:57:14 PM PST 24
Peak memory 238352 kb
Host smart-87502283-1340-4219-ac25-fdb65bd27832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872135468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.2872135468
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.3676917599
Short name T758
Test name
Test status
Simulation time 251477756 ps
CPU time 3.32 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:14 PM PST 24
Peak memory 238412 kb
Host smart-13b5eee9-4001-4e8b-aba7-deba281bdc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676917599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.3676917599
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.3641960059
Short name T1098
Test name
Test status
Simulation time 117326257 ps
CPU time 3.18 seconds
Started Jan 03 12:56:36 PM PST 24
Finished Jan 03 12:57:49 PM PST 24
Peak memory 238356 kb
Host smart-fe3eb6e8-8144-47c0-a60b-f6458443386c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641960059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.3641960059
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.1336571642
Short name T415
Test name
Test status
Simulation time 1615675882 ps
CPU time 4.17 seconds
Started Jan 03 12:56:01 PM PST 24
Finished Jan 03 12:57:14 PM PST 24
Peak memory 240988 kb
Host smart-ce85bf6f-799b-47b4-bd10-0517ec9072c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336571642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.1336571642
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.1209393210
Short name T893
Test name
Test status
Simulation time 340663776 ps
CPU time 6.79 seconds
Started Jan 03 12:56:02 PM PST 24
Finished Jan 03 12:57:18 PM PST 24
Peak memory 238500 kb
Host smart-111e3672-eb79-4230-8699-5a41526137e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209393210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.1209393210
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.2966574054
Short name T605
Test name
Test status
Simulation time 172313812 ps
CPU time 3.44 seconds
Started Jan 03 12:56:01 PM PST 24
Finished Jan 03 12:57:13 PM PST 24
Peak memory 240440 kb
Host smart-b47d8ec2-915b-4b9c-908c-9d34b51b6902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966574054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.2966574054
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.3244665096
Short name T463
Test name
Test status
Simulation time 270183794 ps
CPU time 5.74 seconds
Started Jan 03 12:56:36 PM PST 24
Finished Jan 03 12:57:51 PM PST 24
Peak memory 238272 kb
Host smart-c77d2126-58ea-40f7-8604-43cd0fbb711d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244665096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.3244665096
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.987982576
Short name T48
Test name
Test status
Simulation time 2041030180 ps
CPU time 5.12 seconds
Started Jan 03 12:56:07 PM PST 24
Finished Jan 03 12:57:19 PM PST 24
Peak memory 240976 kb
Host smart-a83fb480-695f-4682-ae95-7bb7494c8dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987982576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.987982576
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.3606240109
Short name T185
Test name
Test status
Simulation time 1845541834 ps
CPU time 5.88 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:19 PM PST 24
Peak memory 242516 kb
Host smart-94bcc6d1-ea17-4b3c-a774-04915b108b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606240109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.3606240109
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.4165267478
Short name T917
Test name
Test status
Simulation time 198741337 ps
CPU time 3.75 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 240724 kb
Host smart-e43baa72-2405-4e22-ab67-12d047352960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165267478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.4165267478
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.2316047380
Short name T984
Test name
Test status
Simulation time 129824238 ps
CPU time 3.33 seconds
Started Jan 03 12:56:00 PM PST 24
Finished Jan 03 12:57:12 PM PST 24
Peak memory 240884 kb
Host smart-68802280-4541-44a0-be6b-46030e92b85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316047380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.2316047380
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.3447014523
Short name T779
Test name
Test status
Simulation time 60049274 ps
CPU time 1.78 seconds
Started Jan 03 12:54:06 PM PST 24
Finished Jan 03 12:55:46 PM PST 24
Peak memory 238304 kb
Host smart-f0ecfb84-a1e2-4595-97b9-00b9f853f748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447014523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.3447014523
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.66933229
Short name T97
Test name
Test status
Simulation time 3109405988 ps
CPU time 11.81 seconds
Started Jan 03 12:53:30 PM PST 24
Finished Jan 03 12:54:36 PM PST 24
Peak memory 245132 kb
Host smart-889e1930-6fdd-4fec-b162-87e1be7f0f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66933229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.66933229
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.620784975
Short name T765
Test name
Test status
Simulation time 13497777641 ps
CPU time 32.52 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:56:14 PM PST 24
Peak memory 244720 kb
Host smart-abd1a7ec-9c2a-4b49-865c-b2035c83d2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620784975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.620784975
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.1957847365
Short name T1119
Test name
Test status
Simulation time 486985305 ps
CPU time 9.38 seconds
Started Jan 03 12:54:09 PM PST 24
Finished Jan 03 12:55:57 PM PST 24
Peak memory 246664 kb
Host smart-f64f55d9-e8a7-44eb-baad-6447aa309a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957847365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.1957847365
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.1514547432
Short name T788
Test name
Test status
Simulation time 1991847296 ps
CPU time 14.87 seconds
Started Jan 03 12:53:55 PM PST 24
Finished Jan 03 12:55:36 PM PST 24
Peak memory 238588 kb
Host smart-56b88f93-a012-49c9-b2cf-8fccb9c9547c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514547432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.1514547432
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.18368391
Short name T849
Test name
Test status
Simulation time 3282065575 ps
CPU time 6.36 seconds
Started Jan 03 12:54:01 PM PST 24
Finished Jan 03 12:55:40 PM PST 24
Peak memory 238612 kb
Host smart-fcf05eca-85f4-440b-8d62-5d378937f14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18368391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.18368391
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.3126808961
Short name T505
Test name
Test status
Simulation time 134304722 ps
CPU time 2.87 seconds
Started Jan 03 12:53:43 PM PST 24
Finished Jan 03 12:54:48 PM PST 24
Peak memory 238244 kb
Host smart-8989f01d-17f2-4bac-a321-12d38ca14220
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3126808961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.3126808961
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.2652175638
Short name T840
Test name
Test status
Simulation time 917041564 ps
CPU time 7.15 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:54:53 PM PST 24
Peak memory 238440 kb
Host smart-1d5c33bd-cc98-421b-911c-24d8dce74ab4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2652175638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.2652175638
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.462981123
Short name T680
Test name
Test status
Simulation time 112301688 ps
CPU time 2.5 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:54:59 PM PST 24
Peak memory 243104 kb
Host smart-862ae39c-3982-4701-8a45-21f6bf4d2c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462981123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.462981123
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.2266971246
Short name T839
Test name
Test status
Simulation time 21603217559 ps
CPU time 79.37 seconds
Started Jan 03 12:53:49 PM PST 24
Finished Jan 03 12:56:55 PM PST 24
Peak memory 239572 kb
Host smart-7b3940f8-26bf-48f5-bdbd-4ae9d689b8c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266971246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.2266971246
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.1861737274
Short name T1080
Test name
Test status
Simulation time 2706578984 ps
CPU time 15.47 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:15 PM PST 24
Peak memory 238660 kb
Host smart-abb118a6-ea40-4f0f-ad4a-0d60176d4bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861737274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.1861737274
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.2251327685
Short name T453
Test name
Test status
Simulation time 384374036 ps
CPU time 4.07 seconds
Started Jan 03 12:56:01 PM PST 24
Finished Jan 03 12:57:14 PM PST 24
Peak memory 238364 kb
Host smart-7aca0209-501e-47ab-ba46-a490228d0a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251327685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.2251327685
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.225894666
Short name T843
Test name
Test status
Simulation time 311133877 ps
CPU time 4.15 seconds
Started Jan 03 12:56:01 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 241340 kb
Host smart-4a72f039-377e-4733-8ad0-660825eef2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225894666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.225894666
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.488418049
Short name T583
Test name
Test status
Simulation time 399343501 ps
CPU time 3.99 seconds
Started Jan 03 12:56:02 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 238340 kb
Host smart-4c3d31be-caa1-41e4-88c7-3d2c5fb30f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488418049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.488418049
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.1039672098
Short name T606
Test name
Test status
Simulation time 2572338780 ps
CPU time 7.6 seconds
Started Jan 03 12:56:08 PM PST 24
Finished Jan 03 12:57:24 PM PST 24
Peak memory 244040 kb
Host smart-56a97be5-899d-4214-8714-ae7941972cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039672098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.1039672098
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.81415602
Short name T1030
Test name
Test status
Simulation time 439201892 ps
CPU time 4.08 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:22 PM PST 24
Peak memory 238336 kb
Host smart-5187f643-0e94-46f8-a331-b6c5407633ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81415602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.81415602
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.4209057956
Short name T787
Test name
Test status
Simulation time 374167318 ps
CPU time 7.48 seconds
Started Jan 03 12:56:02 PM PST 24
Finished Jan 03 12:57:18 PM PST 24
Peak memory 246472 kb
Host smart-bcb6b186-ac57-4208-942b-78e3f87e3c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209057956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.4209057956
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.1465447286
Short name T883
Test name
Test status
Simulation time 217781716 ps
CPU time 3.61 seconds
Started Jan 03 12:56:04 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 238328 kb
Host smart-d363cbb6-0b01-4406-90b0-31685b354944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465447286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.1465447286
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.3971249931
Short name T595
Test name
Test status
Simulation time 186128362 ps
CPU time 4.97 seconds
Started Jan 03 12:56:17 PM PST 24
Finished Jan 03 12:57:30 PM PST 24
Peak memory 242656 kb
Host smart-e9b0b51d-1588-4eff-acdb-134c6ca07470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971249931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.3971249931
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.2480409336
Short name T574
Test name
Test status
Simulation time 2048692101 ps
CPU time 4.76 seconds
Started Jan 03 12:56:05 PM PST 24
Finished Jan 03 12:57:16 PM PST 24
Peak memory 238392 kb
Host smart-a7f20114-3d27-465e-aa6f-01e4da93779e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480409336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.2480409336
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.2073781195
Short name T1002
Test name
Test status
Simulation time 317137833 ps
CPU time 3.93 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:22 PM PST 24
Peak memory 246632 kb
Host smart-cab67874-bd90-4bfd-9794-29568eab9d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073781195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.2073781195
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.887515484
Short name T800
Test name
Test status
Simulation time 1801041241 ps
CPU time 5.18 seconds
Started Jan 03 12:56:05 PM PST 24
Finished Jan 03 12:57:17 PM PST 24
Peak memory 238388 kb
Host smart-2bfb4455-d297-43f4-bdf8-da0d2422d88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887515484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.887515484
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.3428125624
Short name T793
Test name
Test status
Simulation time 139269832 ps
CPU time 3.33 seconds
Started Jan 03 12:56:05 PM PST 24
Finished Jan 03 12:57:16 PM PST 24
Peak memory 238456 kb
Host smart-133c9f95-69da-4fc2-8ffd-a2e17859c845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428125624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.3428125624
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.2982897385
Short name T1044
Test name
Test status
Simulation time 1966419259 ps
CPU time 5.27 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:23 PM PST 24
Peak memory 238448 kb
Host smart-addd1310-109f-4813-96e1-f29d0db0144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982897385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.2982897385
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.606305262
Short name T975
Test name
Test status
Simulation time 350897286 ps
CPU time 5.57 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:19 PM PST 24
Peak memory 238364 kb
Host smart-ca9bdff7-388f-45e7-8fac-fa2a9f6d60c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606305262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.606305262
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.1810709784
Short name T930
Test name
Test status
Simulation time 293518727 ps
CPU time 3.76 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:17 PM PST 24
Peak memory 238436 kb
Host smart-d74f651e-263f-44e1-838b-efbd44ecc50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810709784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.1810709784
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.343965408
Short name T1082
Test name
Test status
Simulation time 359659447 ps
CPU time 4.34 seconds
Started Jan 03 12:56:05 PM PST 24
Finished Jan 03 12:57:17 PM PST 24
Peak memory 246576 kb
Host smart-617021d5-bf00-4d22-8440-b638f38f7b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343965408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.343965408
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.1540289756
Short name T877
Test name
Test status
Simulation time 1805799779 ps
CPU time 6.43 seconds
Started Jan 03 12:56:36 PM PST 24
Finished Jan 03 12:57:52 PM PST 24
Peak memory 238272 kb
Host smart-af5d463e-505c-4212-be03-ce4bbdde7300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540289756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1540289756
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.3513895036
Short name T397
Test name
Test status
Simulation time 142254166 ps
CPU time 2.65 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:14 PM PST 24
Peak memory 238512 kb
Host smart-56efcae6-b224-493b-bb62-50c18dd138b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513895036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.3513895036
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.3594283863
Short name T768
Test name
Test status
Simulation time 216366217 ps
CPU time 4.25 seconds
Started Jan 03 12:56:36 PM PST 24
Finished Jan 03 12:57:50 PM PST 24
Peak memory 240988 kb
Host smart-628274ab-6d0c-4895-9e39-ddd1de96ca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594283863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.3594283863
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.229279120
Short name T769
Test name
Test status
Simulation time 1328183213 ps
CPU time 6.96 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:26 PM PST 24
Peak memory 242288 kb
Host smart-8c550779-bc55-4094-b8b3-fec186674d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229279120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.229279120
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.4098046356
Short name T1120
Test name
Test status
Simulation time 77164189 ps
CPU time 1.97 seconds
Started Jan 03 12:53:51 PM PST 24
Finished Jan 03 12:55:13 PM PST 24
Peak memory 238636 kb
Host smart-e541bc29-6b1e-486a-b6db-35bec5bbecb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098046356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.4098046356
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.662890697
Short name T1054
Test name
Test status
Simulation time 197885271 ps
CPU time 3.79 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:55:21 PM PST 24
Peak memory 243516 kb
Host smart-523c01ac-e635-42a5-9466-4c8f983c6a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662890697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.662890697
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.2598374211
Short name T287
Test name
Test status
Simulation time 928372115 ps
CPU time 8.29 seconds
Started Jan 03 12:54:00 PM PST 24
Finished Jan 03 12:55:44 PM PST 24
Peak memory 238528 kb
Host smart-78ea42f3-ae13-4efc-ac57-92c30e8bf6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598374211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.2598374211
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.1290267435
Short name T101
Test name
Test status
Simulation time 227336382 ps
CPU time 5.94 seconds
Started Jan 03 12:54:05 PM PST 24
Finished Jan 03 12:55:51 PM PST 24
Peak memory 238508 kb
Host smart-e71a6aa8-b295-4a47-b5cb-6090c2ffc378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290267435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1290267435
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.599885005
Short name T613
Test name
Test status
Simulation time 1066910542 ps
CPU time 17.16 seconds
Started Jan 03 12:53:14 PM PST 24
Finished Jan 03 12:54:35 PM PST 24
Peak memory 245084 kb
Host smart-2fa8a092-b8ef-4196-9a4f-96737721bf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599885005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.599885005
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.2795761878
Short name T651
Test name
Test status
Simulation time 209286319 ps
CPU time 3.51 seconds
Started Jan 03 12:53:15 PM PST 24
Finished Jan 03 12:54:03 PM PST 24
Peak memory 238448 kb
Host smart-c34e3860-bc99-4cd6-a8f8-123e8eadc9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795761878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.2795761878
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.4147745440
Short name T129
Test name
Test status
Simulation time 2835465040 ps
CPU time 17.02 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:13 PM PST 24
Peak memory 238616 kb
Host smart-2311b1f3-69dc-4324-b49b-c5fa885a6afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147745440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.4147745440
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.1769485157
Short name T1072
Test name
Test status
Simulation time 633860036 ps
CPU time 15.23 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:55:01 PM PST 24
Peak memory 244784 kb
Host smart-6a487920-f53f-46c5-9f84-78784242cdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769485157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.1769485157
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.136104709
Short name T348
Test name
Test status
Simulation time 514379699 ps
CPU time 5.98 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:55:21 PM PST 24
Peak memory 238424 kb
Host smart-c549a6b5-99a2-490e-934e-64661398e312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136104709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.136104709
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.3699167849
Short name T936
Test name
Test status
Simulation time 677766060 ps
CPU time 15.63 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:54:50 PM PST 24
Peak memory 233452 kb
Host smart-c62a13e1-6f41-4ce9-9b10-94dfe7826c6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3699167849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.3699167849
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.2383560508
Short name T690
Test name
Test status
Simulation time 183841294 ps
CPU time 4.56 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:54:45 PM PST 24
Peak memory 238524 kb
Host smart-6d37bdaf-262f-48f5-bd13-867ca77ba4dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2383560508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.2383560508
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.3276874533
Short name T17
Test name
Test status
Simulation time 34481510412 ps
CPU time 190.24 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:57:46 PM PST 24
Peak memory 268356 kb
Host smart-c4eb83fb-754d-4444-b2c3-472e0350a11c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276874533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.3276874533
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.2094617436
Short name T1085
Test name
Test status
Simulation time 145812246 ps
CPU time 3.18 seconds
Started Jan 03 12:53:51 PM PST 24
Finished Jan 03 12:55:12 PM PST 24
Peak memory 246524 kb
Host smart-7457f802-93c0-4a03-9eb8-76bce5977981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094617436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.2094617436
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.11041871
Short name T891
Test name
Test status
Simulation time 377440483553 ps
CPU time 2861.43 seconds
Started Jan 03 12:53:15 PM PST 24
Finished Jan 03 01:41:45 PM PST 24
Peak memory 914540 kb
Host smart-8169772f-e0b2-4c88-958f-072cbd4f7462
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11041871 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.11041871
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.1828112882
Short name T1127
Test name
Test status
Simulation time 815647912 ps
CPU time 8.55 seconds
Started Jan 03 12:53:21 PM PST 24
Finished Jan 03 12:54:11 PM PST 24
Peak memory 242708 kb
Host smart-d744043d-d4a0-41f1-9669-5f0054aff42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828112882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.1828112882
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.1808813431
Short name T832
Test name
Test status
Simulation time 60150929 ps
CPU time 1.71 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:54:41 PM PST 24
Peak memory 239180 kb
Host smart-73f4fa8a-fec2-4795-aed6-a8e1542e37a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808813431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.1808813431
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.614239191
Short name T32
Test name
Test status
Simulation time 8287242408 ps
CPU time 20.7 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:55:13 PM PST 24
Peak memory 238700 kb
Host smart-da12da1b-0d35-4786-aacc-79f51780286e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614239191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.614239191
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.334120050
Short name T406
Test name
Test status
Simulation time 191681292 ps
CPU time 4.92 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:54:57 PM PST 24
Peak memory 246576 kb
Host smart-96e1dd0d-32d1-4916-8952-35163347d152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334120050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.334120050
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.3717416766
Short name T1057
Test name
Test status
Simulation time 976924164 ps
CPU time 9.76 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:55:00 PM PST 24
Peak memory 238480 kb
Host smart-9723bde1-5db6-4ee4-8dbf-a89264bb7de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717416766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3717416766
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.2973505546
Short name T153
Test name
Test status
Simulation time 349214443 ps
CPU time 4.27 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:54:51 PM PST 24
Peak memory 238356 kb
Host smart-fa3736f6-b016-4148-b1ac-6667b4711bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973505546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.2973505546
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.1395958788
Short name T1088
Test name
Test status
Simulation time 1594816758 ps
CPU time 17.36 seconds
Started Jan 03 12:54:10 PM PST 24
Finished Jan 03 12:56:05 PM PST 24
Peak memory 238416 kb
Host smart-6f58d601-c5b0-43dd-b2f4-0622562d4b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395958788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.1395958788
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.3333323612
Short name T517
Test name
Test status
Simulation time 411581815 ps
CPU time 10.72 seconds
Started Jan 03 12:53:51 PM PST 24
Finished Jan 03 12:55:18 PM PST 24
Peak memory 238496 kb
Host smart-03e70a28-e0a4-410c-a9fd-5a8a2a5400d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333323612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.3333323612
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.863379032
Short name T1126
Test name
Test status
Simulation time 640064267 ps
CPU time 5.51 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:11 PM PST 24
Peak memory 242808 kb
Host smart-fce90a71-cc5f-4379-8824-468bec547e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863379032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.863379032
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.2883807659
Short name T258
Test name
Test status
Simulation time 2862968728 ps
CPU time 16.76 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:55:45 PM PST 24
Peak memory 238636 kb
Host smart-4bd37f70-fb01-425a-acc7-76fa674bd1fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2883807659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.2883807659
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.496280348
Short name T657
Test name
Test status
Simulation time 360214174 ps
CPU time 3.1 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:54:57 PM PST 24
Peak memory 242888 kb
Host smart-853ee889-50c1-4cc2-b22a-cb64e9d700d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=496280348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.496280348
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.4090372577
Short name T869
Test name
Test status
Simulation time 141920837 ps
CPU time 3.31 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:47 PM PST 24
Peak memory 242620 kb
Host smart-78943e80-c418-440a-a598-1d5a24c23f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090372577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.4090372577
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.3873029723
Short name T803
Test name
Test status
Simulation time 69077267612 ps
CPU time 223.19 seconds
Started Jan 03 12:54:05 PM PST 24
Finished Jan 03 12:59:23 PM PST 24
Peak memory 246868 kb
Host smart-833eb044-a69c-456e-8375-86d8cb75fdfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873029723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.3873029723
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.2334152698
Short name T217
Test name
Test status
Simulation time 1048580085738 ps
CPU time 6817.62 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 02:48:10 PM PST 24
Peak memory 850336 kb
Host smart-2c3cca9f-af74-4b00-8719-195200f20558
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334152698 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.2334152698
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.4221286883
Short name T416
Test name
Test status
Simulation time 341569436 ps
CPU time 9 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:15 PM PST 24
Peak memory 245296 kb
Host smart-ae9cb821-05ed-48dc-907a-b246846c992f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221286883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.4221286883
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.1556793776
Short name T1011
Test name
Test status
Simulation time 289775421 ps
CPU time 3.9 seconds
Started Jan 03 12:56:04 PM PST 24
Finished Jan 03 12:57:16 PM PST 24
Peak memory 238492 kb
Host smart-98faff7b-ad18-428b-a626-a71ea553f1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556793776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.1556793776
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.826997681
Short name T1033
Test name
Test status
Simulation time 428839743 ps
CPU time 4.04 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:17 PM PST 24
Peak memory 238400 kb
Host smart-38e042e3-f2ac-431e-9799-92a912489292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826997681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.826997681
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.914160388
Short name T818
Test name
Test status
Simulation time 132815960 ps
CPU time 4.74 seconds
Started Jan 03 12:56:06 PM PST 24
Finished Jan 03 12:57:18 PM PST 24
Peak memory 238420 kb
Host smart-ea1d64ad-580e-41c6-9c88-c8c70bf2d9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914160388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.914160388
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.758246567
Short name T59
Test name
Test status
Simulation time 192096727 ps
CPU time 3.02 seconds
Started Jan 03 12:56:34 PM PST 24
Finished Jan 03 12:57:47 PM PST 24
Peak memory 238396 kb
Host smart-e0ceb38c-fba3-4638-b488-9b475f49df16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758246567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.758246567
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.2687377279
Short name T78
Test name
Test status
Simulation time 576797852 ps
CPU time 3.9 seconds
Started Jan 03 12:56:07 PM PST 24
Finished Jan 03 12:57:18 PM PST 24
Peak memory 238344 kb
Host smart-b8504fe5-4494-4715-b845-2d0417663666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687377279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.2687377279
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.3461189768
Short name T673
Test name
Test status
Simulation time 128749105 ps
CPU time 4.65 seconds
Started Jan 03 12:56:05 PM PST 24
Finished Jan 03 12:57:16 PM PST 24
Peak memory 240844 kb
Host smart-d5b2ef3a-d765-4389-a78c-d0b602914af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461189768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.3461189768
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.2826784702
Short name T998
Test name
Test status
Simulation time 177503999 ps
CPU time 3.78 seconds
Started Jan 03 12:56:11 PM PST 24
Finished Jan 03 12:57:23 PM PST 24
Peak memory 238284 kb
Host smart-d2546942-1984-4dc6-a4fa-490794f5b4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826784702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.2826784702
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.3417181257
Short name T528
Test name
Test status
Simulation time 1755868840 ps
CPU time 5.06 seconds
Started Jan 03 12:56:06 PM PST 24
Finished Jan 03 12:57:21 PM PST 24
Peak memory 240936 kb
Host smart-a66a2831-be6c-4227-8c04-bf2e898b8ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417181257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3417181257
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.3692160495
Short name T413
Test name
Test status
Simulation time 67674731 ps
CPU time 1.78 seconds
Started Jan 03 12:53:31 PM PST 24
Finished Jan 03 12:54:47 PM PST 24
Peak memory 238624 kb
Host smart-4f51168a-1ee6-4c42-9bf7-a3b1d45202c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692160495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.3692160495
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.292523621
Short name T776
Test name
Test status
Simulation time 1224696593 ps
CPU time 6.81 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:52 PM PST 24
Peak memory 243452 kb
Host smart-61a7ad07-e0f9-4ba0-99b6-86fdf1315b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292523621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.292523621
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.3432345168
Short name T1027
Test name
Test status
Simulation time 4737794275 ps
CPU time 9.15 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:54:53 PM PST 24
Peak memory 246448 kb
Host smart-d5743cc4-42a3-4341-a07f-2c35df22ed09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432345168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3432345168
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.1635903773
Short name T536
Test name
Test status
Simulation time 1435012889 ps
CPU time 12.75 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:58 PM PST 24
Peak memory 238556 kb
Host smart-35f87768-763b-43f7-9cda-677ac2caafcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635903773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1635903773
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.436195060
Short name T801
Test name
Test status
Simulation time 970131327 ps
CPU time 5.85 seconds
Started Jan 03 12:54:03 PM PST 24
Finished Jan 03 12:55:47 PM PST 24
Peak memory 238580 kb
Host smart-a24519be-58b3-4694-b9db-7e4d7c43b9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436195060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.436195060
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.3548088206
Short name T6
Test name
Test status
Simulation time 1643621351 ps
CPU time 14.63 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:55:30 PM PST 24
Peak memory 238472 kb
Host smart-cacb76ad-e6ae-45c4-984b-0b96424dc015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548088206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.3548088206
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.3184652319
Short name T986
Test name
Test status
Simulation time 1507175269 ps
CPU time 3.89 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:04 PM PST 24
Peak memory 246456 kb
Host smart-b81fe974-a62d-4f0d-8857-1b088978796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184652319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.3184652319
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.2339378913
Short name T835
Test name
Test status
Simulation time 378974177 ps
CPU time 5.9 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:55:21 PM PST 24
Peak memory 241128 kb
Host smart-dc059719-897f-4343-b183-857d8d633d6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2339378913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.2339378913
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.1977035138
Short name T804
Test name
Test status
Simulation time 181430688 ps
CPU time 3.26 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:55:19 PM PST 24
Peak memory 238508 kb
Host smart-6928bc47-aa35-4ffb-a7ef-5fb7ff22d028
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1977035138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.1977035138
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.4065534387
Short name T372
Test name
Test status
Simulation time 752098172 ps
CPU time 5.47 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:55:23 PM PST 24
Peak memory 242840 kb
Host smart-ce6bfda0-75f9-43c6-a811-15e13b5bc1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065534387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.4065534387
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.1345063137
Short name T1117
Test name
Test status
Simulation time 9186787450 ps
CPU time 101.01 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:56:18 PM PST 24
Peak memory 255080 kb
Host smart-d16d33d6-84a3-469d-bb08-53eb0fa3e9f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345063137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.1345063137
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.1257134232
Short name T13
Test name
Test status
Simulation time 852051797793 ps
CPU time 2175.14 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 01:31:08 PM PST 24
Peak memory 250248 kb
Host smart-ef8c7193-a896-4bbf-ad17-343eaf347ac6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257134232 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.1257134232
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.4158029327
Short name T87
Test name
Test status
Simulation time 2271230331 ps
CPU time 22.11 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:55:04 PM PST 24
Peak memory 245924 kb
Host smart-fa5585a0-b081-441a-a814-88f004e5edbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158029327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.4158029327
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.2324960478
Short name T437
Test name
Test status
Simulation time 858679108 ps
CPU time 5.96 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:17 PM PST 24
Peak memory 240736 kb
Host smart-d118f6eb-84f5-4d56-98b9-0d6e8b07f940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324960478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.2324960478
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.1699343328
Short name T614
Test name
Test status
Simulation time 417921796 ps
CPU time 3.36 seconds
Started Jan 03 12:56:35 PM PST 24
Finished Jan 03 12:57:49 PM PST 24
Peak memory 238444 kb
Host smart-5a778d92-954f-49ae-b1a6-bd3ae3f5a479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699343328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.1699343328
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.4036711605
Short name T939
Test name
Test status
Simulation time 227363771 ps
CPU time 3.78 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:23 PM PST 24
Peak memory 240640 kb
Host smart-da4c64d0-7b7a-482f-810c-a22687744dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036711605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.4036711605
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.4022774292
Short name T120
Test name
Test status
Simulation time 242170848 ps
CPU time 3.96 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 240936 kb
Host smart-bdf9bfed-08f9-498c-b3cb-fa06a919be51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022774292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.4022774292
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.1609177432
Short name T865
Test name
Test status
Simulation time 1985383767 ps
CPU time 4.65 seconds
Started Jan 03 12:56:04 PM PST 24
Finished Jan 03 12:57:16 PM PST 24
Peak memory 240896 kb
Host smart-c484b814-596d-4392-b34f-352ceac3551e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609177432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.1609177432
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.97753289
Short name T417
Test name
Test status
Simulation time 193012397 ps
CPU time 3.66 seconds
Started Jan 03 12:56:07 PM PST 24
Finished Jan 03 12:57:19 PM PST 24
Peak memory 241112 kb
Host smart-fcc25807-d31b-4a15-9c93-913012fd0b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97753289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.97753289
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.373363701
Short name T548
Test name
Test status
Simulation time 598660615 ps
CPU time 4.08 seconds
Started Jan 03 12:56:37 PM PST 24
Finished Jan 03 12:57:51 PM PST 24
Peak memory 238492 kb
Host smart-fb978731-7cca-484f-9f0d-1f002a1128e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373363701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.373363701
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.2633379016
Short name T449
Test name
Test status
Simulation time 209458751 ps
CPU time 2.95 seconds
Started Jan 03 12:56:07 PM PST 24
Finished Jan 03 12:57:17 PM PST 24
Peak memory 241100 kb
Host smart-5ff6a074-4690-4572-97cf-970fb9d4fc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633379016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2633379016
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.2729585776
Short name T195
Test name
Test status
Simulation time 248016305 ps
CPU time 4.35 seconds
Started Jan 03 12:56:07 PM PST 24
Finished Jan 03 12:57:20 PM PST 24
Peak memory 238396 kb
Host smart-3239a603-57c9-4446-9f7a-772e98cd9de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729585776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.2729585776
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.21849725
Short name T796
Test name
Test status
Simulation time 248903881 ps
CPU time 4.2 seconds
Started Jan 03 12:56:07 PM PST 24
Finished Jan 03 12:57:19 PM PST 24
Peak memory 241020 kb
Host smart-bdb6692d-c006-4cef-8ed6-1676c3531ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21849725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.21849725
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.97128037
Short name T1048
Test name
Test status
Simulation time 820998001 ps
CPU time 1.89 seconds
Started Jan 03 12:53:30 PM PST 24
Finished Jan 03 12:54:40 PM PST 24
Peak memory 238852 kb
Host smart-606768ae-f9a3-4227-8a96-2588350ffc38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97128037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.97128037
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.3364214467
Short name T617
Test name
Test status
Simulation time 1659762200 ps
CPU time 4.98 seconds
Started Jan 03 12:54:06 PM PST 24
Finished Jan 03 12:55:50 PM PST 24
Peak memory 240840 kb
Host smart-33ebe88b-7cf0-4e7c-896d-3ee819a4961c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364214467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.3364214467
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.4249134150
Short name T116
Test name
Test status
Simulation time 2942243321 ps
CPU time 9.21 seconds
Started Jan 03 12:53:43 PM PST 24
Finished Jan 03 12:54:58 PM PST 24
Peak memory 246700 kb
Host smart-160b0534-9a9e-4a47-8480-df53dba80b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249134150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.4249134150
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.2993845168
Short name T819
Test name
Test status
Simulation time 9040724829 ps
CPU time 19.3 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:55:05 PM PST 24
Peak memory 238704 kb
Host smart-e15115ef-4024-46be-9e39-6850fd0725bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993845168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2993845168
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.3536264339
Short name T156
Test name
Test status
Simulation time 129378916 ps
CPU time 3.44 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:54:58 PM PST 24
Peak memory 240844 kb
Host smart-f9ce89e7-4038-4c2b-bbfc-fbd26f71dbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536264339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.3536264339
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.2733059431
Short name T283
Test name
Test status
Simulation time 1831582296 ps
CPU time 26.84 seconds
Started Jan 03 12:53:43 PM PST 24
Finished Jan 03 12:55:12 PM PST 24
Peak memory 241992 kb
Host smart-7af4a01c-5e61-45e4-9811-56127774cde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733059431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.2733059431
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.4179464727
Short name T560
Test name
Test status
Simulation time 145194177 ps
CPU time 3.76 seconds
Started Jan 03 12:53:43 PM PST 24
Finished Jan 03 12:54:48 PM PST 24
Peak memory 238540 kb
Host smart-97547b18-a365-42c4-9439-bf70285121ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179464727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.4179464727
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.436625585
Short name T487
Test name
Test status
Simulation time 499501317 ps
CPU time 3.92 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:54:48 PM PST 24
Peak memory 238488 kb
Host smart-3d99974c-734e-49f1-9ee2-c966cbfdd9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436625585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.436625585
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.3602562785
Short name T881
Test name
Test status
Simulation time 507922964 ps
CPU time 9.31 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:55:09 PM PST 24
Peak memory 243520 kb
Host smart-0f308b7a-ed5a-44ed-b131-a1303c40add7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3602562785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.3602562785
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.3567233459
Short name T311
Test name
Test status
Simulation time 252353743 ps
CPU time 4.33 seconds
Started Jan 03 12:53:51 PM PST 24
Finished Jan 03 12:55:24 PM PST 24
Peak memory 246712 kb
Host smart-eb10f06a-262d-4e7c-9dc6-4260d5cd9baa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3567233459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.3567233459
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.883482186
Short name T495
Test name
Test status
Simulation time 360953712 ps
CPU time 3.1 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:55:45 PM PST 24
Peak memory 238400 kb
Host smart-a208faba-2b72-4353-ba66-3dfb0393b667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883482186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.883482186
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.47762814
Short name T616
Test name
Test status
Simulation time 12708903961 ps
CPU time 77.77 seconds
Started Jan 03 12:53:08 PM PST 24
Finished Jan 03 12:55:26 PM PST 24
Peak memory 246908 kb
Host smart-1a838db8-9518-47f3-b630-dc4b4b5dae6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47762814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.47762814
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.101729580
Short name T953
Test name
Test status
Simulation time 147425827851 ps
CPU time 1595.12 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 01:21:12 PM PST 24
Peak memory 543536 kb
Host smart-42963516-5f50-4fbb-aa00-4c9ba983a3ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101729580 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.101729580
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.578065238
Short name T252
Test name
Test status
Simulation time 12281853094 ps
CPU time 29.4 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:55:07 PM PST 24
Peak memory 238680 kb
Host smart-0a12927a-6b05-4dc7-b338-11119883c830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578065238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.578065238
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.2695347548
Short name T581
Test name
Test status
Simulation time 310597705 ps
CPU time 3.6 seconds
Started Jan 03 12:56:07 PM PST 24
Finished Jan 03 12:57:18 PM PST 24
Peak memory 240720 kb
Host smart-d0caee24-ca73-4076-bf32-2e96464c5c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695347548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.2695347548
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.3239927478
Short name T119
Test name
Test status
Simulation time 217223536 ps
CPU time 3.79 seconds
Started Jan 03 12:56:07 PM PST 24
Finished Jan 03 12:57:19 PM PST 24
Peak memory 240852 kb
Host smart-e8ef3195-f4bd-413b-a216-098b3a60a56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239927478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3239927478
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.2022707741
Short name T450
Test name
Test status
Simulation time 283272581 ps
CPU time 3.77 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 238304 kb
Host smart-54e3d0f1-418a-4b46-8ce6-c6a352510355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022707741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.2022707741
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.1887567375
Short name T520
Test name
Test status
Simulation time 151339458 ps
CPU time 4.67 seconds
Started Jan 03 12:56:07 PM PST 24
Finished Jan 03 12:57:20 PM PST 24
Peak memory 238144 kb
Host smart-7e73cd77-9f71-4fb8-8e55-8fca641d6028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887567375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.1887567375
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.3663634166
Short name T698
Test name
Test status
Simulation time 1503569286 ps
CPU time 3.91 seconds
Started Jan 03 12:56:10 PM PST 24
Finished Jan 03 12:57:21 PM PST 24
Peak memory 238444 kb
Host smart-5c9637df-f9e9-4aba-b11c-e16b133a7223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663634166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.3663634166
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.1003605531
Short name T440
Test name
Test status
Simulation time 472117463 ps
CPU time 4.45 seconds
Started Jan 03 12:56:18 PM PST 24
Finished Jan 03 12:57:33 PM PST 24
Peak memory 240908 kb
Host smart-4c895bda-72c7-47b9-a777-7e56b1f62460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003605531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.1003605531
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.2231158565
Short name T928
Test name
Test status
Simulation time 146166319 ps
CPU time 3.83 seconds
Started Jan 03 12:56:19 PM PST 24
Finished Jan 03 12:57:33 PM PST 24
Peak memory 238336 kb
Host smart-c704765d-435b-4108-8122-fd93989fca71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231158565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.2231158565
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.2248736189
Short name T874
Test name
Test status
Simulation time 159879923 ps
CPU time 4.09 seconds
Started Jan 03 12:56:17 PM PST 24
Finished Jan 03 12:57:29 PM PST 24
Peak memory 238324 kb
Host smart-12d8756b-5707-4b6b-9e4c-0d8ad9e796b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248736189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.2248736189
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.3518551276
Short name T1062
Test name
Test status
Simulation time 1762290038 ps
CPU time 5.04 seconds
Started Jan 03 12:56:08 PM PST 24
Finished Jan 03 12:57:28 PM PST 24
Peak memory 238344 kb
Host smart-3e2c2003-390f-4fbe-a7fb-cd88b0476386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518551276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.3518551276
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.1135021345
Short name T908
Test name
Test status
Simulation time 175091513 ps
CPU time 4.07 seconds
Started Jan 03 12:56:17 PM PST 24
Finished Jan 03 12:57:29 PM PST 24
Peak memory 240760 kb
Host smart-d98c3f24-4f3e-4616-8822-e06fe7028779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135021345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.1135021345
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.2275114427
Short name T366
Test name
Test status
Simulation time 86624327 ps
CPU time 1.59 seconds
Started Jan 03 12:54:05 PM PST 24
Finished Jan 03 12:55:46 PM PST 24
Peak memory 238440 kb
Host smart-74995318-dc75-4b2b-8bb2-0374c800d2b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275114427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.2275114427
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.2081606322
Short name T647
Test name
Test status
Simulation time 238757434 ps
CPU time 4.81 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:20 PM PST 24
Peak memory 244252 kb
Host smart-3acfa8b6-cc92-48cd-9fc2-4390a00cbb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081606322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.2081606322
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.1160778010
Short name T280
Test name
Test status
Simulation time 8087419306 ps
CPU time 20.64 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:55:06 PM PST 24
Peak memory 242460 kb
Host smart-6ec1e48b-4118-46c6-a494-c1a7c2285869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160778010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.1160778010
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.1720527353
Short name T91
Test name
Test status
Simulation time 2614479009 ps
CPU time 12.37 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:54:56 PM PST 24
Peak memory 238660 kb
Host smart-24b34f49-bf45-4b7a-b093-eb5b2cac6791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720527353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.1720527353
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.2254616233
Short name T40
Test name
Test status
Simulation time 238620839 ps
CPU time 4.17 seconds
Started Jan 03 12:53:50 PM PST 24
Finished Jan 03 12:55:15 PM PST 24
Peak memory 238332 kb
Host smart-19ba2269-2930-47f1-95a2-f6778167b141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254616233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.2254616233
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.2997756693
Short name T507
Test name
Test status
Simulation time 2116626918 ps
CPU time 7.57 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:08 PM PST 24
Peak memory 245784 kb
Host smart-1b40421a-cfb6-43ef-8afb-0bfd90977fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997756693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.2997756693
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.3830250743
Short name T465
Test name
Test status
Simulation time 2650955534 ps
CPU time 13.65 seconds
Started Jan 03 12:54:06 PM PST 24
Finished Jan 03 12:55:59 PM PST 24
Peak memory 238556 kb
Host smart-ffffe1c2-737d-4f8f-a312-4336005d00a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830250743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.3830250743
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.523413325
Short name T293
Test name
Test status
Simulation time 244577065 ps
CPU time 2.06 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:02 PM PST 24
Peak memory 238428 kb
Host smart-cef463ad-b65e-4468-ac94-91f2454ca8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523413325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.523413325
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.2628738317
Short name T837
Test name
Test status
Simulation time 1307427384 ps
CPU time 14.42 seconds
Started Jan 03 12:53:43 PM PST 24
Finished Jan 03 12:54:59 PM PST 24
Peak memory 238492 kb
Host smart-a9051705-4abd-4e18-b4fc-2da561fd6ddf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2628738317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.2628738317
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.3111094654
Short name T205
Test name
Test status
Simulation time 408770418 ps
CPU time 5.3 seconds
Started Jan 03 12:53:30 PM PST 24
Finished Jan 03 12:54:29 PM PST 24
Peak memory 238420 kb
Host smart-3d960451-45c4-4005-838b-cc72b7277633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3111094654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.3111094654
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.136703179
Short name T394
Test name
Test status
Simulation time 134855042 ps
CPU time 4.68 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:15 PM PST 24
Peak memory 238584 kb
Host smart-e4e91039-84ee-48da-a2a3-aa9dfb0bb1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136703179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.136703179
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.567489009
Short name T656
Test name
Test status
Simulation time 43534234605 ps
CPU time 113.11 seconds
Started Jan 03 12:53:50 PM PST 24
Finished Jan 03 12:57:11 PM PST 24
Peak memory 246744 kb
Host smart-9c45afdf-bd2f-43d0-b78e-0ed15ece0d49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567489009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.
567489009
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.607564936
Short name T224
Test name
Test status
Simulation time 305154060640 ps
CPU time 2636.56 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 01:38:49 PM PST 24
Peak memory 263164 kb
Host smart-bfec8d77-955b-4110-a3b2-e72f5ee45703
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607564936 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.607564936
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.3591516395
Short name T1035
Test name
Test status
Simulation time 698098591 ps
CPU time 4.64 seconds
Started Jan 03 12:53:33 PM PST 24
Finished Jan 03 12:54:50 PM PST 24
Peak memory 243872 kb
Host smart-7d7903e4-d599-4fe2-a4ac-003471b5f653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591516395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.3591516395
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.2072164802
Short name T597
Test name
Test status
Simulation time 244867661 ps
CPU time 4.32 seconds
Started Jan 03 12:56:19 PM PST 24
Finished Jan 03 12:57:33 PM PST 24
Peak memory 241312 kb
Host smart-7f163233-2112-46dc-93bc-74e0091012f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072164802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.2072164802
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.1709771936
Short name T701
Test name
Test status
Simulation time 336110273 ps
CPU time 3.8 seconds
Started Jan 03 12:56:38 PM PST 24
Finished Jan 03 12:57:52 PM PST 24
Peak memory 240472 kb
Host smart-e34b845e-b1b2-4d5a-afe1-37b8a5dd8824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709771936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.1709771936
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.376869382
Short name T1118
Test name
Test status
Simulation time 328284164 ps
CPU time 4.29 seconds
Started Jan 03 12:56:22 PM PST 24
Finished Jan 03 12:57:36 PM PST 24
Peak memory 238372 kb
Host smart-8f31d932-d4cd-43b8-94ab-3f9ed98e1acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376869382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.376869382
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.1588225746
Short name T21
Test name
Test status
Simulation time 183520259 ps
CPU time 3.46 seconds
Started Jan 03 12:56:17 PM PST 24
Finished Jan 03 12:57:28 PM PST 24
Peak memory 240664 kb
Host smart-d9eb84a4-ab69-4d7b-8d5c-2550931eb766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588225746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.1588225746
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.1761344579
Short name T999
Test name
Test status
Simulation time 630502655 ps
CPU time 3.88 seconds
Started Jan 03 12:56:20 PM PST 24
Finished Jan 03 12:57:34 PM PST 24
Peak memory 238460 kb
Host smart-ff32d193-015a-4e92-b8cd-7d71d24bef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761344579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.1761344579
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.1214454912
Short name T81
Test name
Test status
Simulation time 363817297 ps
CPU time 3.8 seconds
Started Jan 03 12:56:50 PM PST 24
Finished Jan 03 12:57:59 PM PST 24
Peak memory 238456 kb
Host smart-eca4c468-327c-4d81-a5e9-2acf55984543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214454912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.1214454912
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.3244138858
Short name T1053
Test name
Test status
Simulation time 150189209 ps
CPU time 3.56 seconds
Started Jan 03 12:56:17 PM PST 24
Finished Jan 03 12:57:29 PM PST 24
Peak memory 238340 kb
Host smart-166cc6d9-5070-43f6-b316-2dcbad1a2ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244138858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.3244138858
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.815105073
Short name T828
Test name
Test status
Simulation time 437012359 ps
CPU time 4.06 seconds
Started Jan 03 12:56:16 PM PST 24
Finished Jan 03 12:57:29 PM PST 24
Peak memory 238332 kb
Host smart-2fbb9db3-bf45-4229-a5ae-01a28d905c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815105073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.815105073
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.9368077
Short name T770
Test name
Test status
Simulation time 245755196 ps
CPU time 2.24 seconds
Started Jan 03 12:54:15 PM PST 24
Finished Jan 03 12:55:56 PM PST 24
Peak memory 239260 kb
Host smart-05154057-82c6-430e-9ce8-8c8e11d4e85e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9368077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.9368077
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.1445811706
Short name T919
Test name
Test status
Simulation time 5127847142 ps
CPU time 10.65 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:54:59 PM PST 24
Peak memory 238636 kb
Host smart-e3a9c8f8-799e-42eb-8770-b582c02e0d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445811706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.1445811706
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.2449295217
Short name T380
Test name
Test status
Simulation time 1121744406 ps
CPU time 13.96 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:32 PM PST 24
Peak memory 246664 kb
Host smart-f8c08825-ac10-4b9e-a94c-5bcf04d3d428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449295217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.2449295217
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.1189988760
Short name T644
Test name
Test status
Simulation time 3056496892 ps
CPU time 11.96 seconds
Started Jan 03 12:53:50 PM PST 24
Finished Jan 03 12:55:23 PM PST 24
Peak memory 237540 kb
Host smart-ecce5ba0-cdcd-4db2-8da7-965521373572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189988760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.1189988760
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.75130113
Short name T1046
Test name
Test status
Simulation time 1340847599 ps
CPU time 21.16 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:54:57 PM PST 24
Peak memory 246744 kb
Host smart-40198c94-033f-4b67-9569-f5b9568ca5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75130113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.75130113
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.3039614125
Short name T1103
Test name
Test status
Simulation time 199045523 ps
CPU time 6.42 seconds
Started Jan 03 12:53:43 PM PST 24
Finished Jan 03 12:54:55 PM PST 24
Peak memory 238520 kb
Host smart-e946ff5b-4605-43c2-b58d-b1be5af24e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039614125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.3039614125
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.1037378652
Short name T830
Test name
Test status
Simulation time 275189764 ps
CPU time 4.43 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:54:58 PM PST 24
Peak memory 238276 kb
Host smart-d44f803c-1d61-4ea4-9554-2f43436848b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037378652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1037378652
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.1839566114
Short name T964
Test name
Test status
Simulation time 468412543 ps
CPU time 6.8 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:54:48 PM PST 24
Peak memory 243232 kb
Host smart-15918147-2b75-409b-a527-8ceb8147edb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839566114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.1839566114
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.655219373
Short name T627
Test name
Test status
Simulation time 248553345 ps
CPU time 6.06 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:51 PM PST 24
Peak memory 238460 kb
Host smart-cf49827d-51ad-4cc8-9810-06494dd6fb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655219373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.655219373
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.3110467955
Short name T813
Test name
Test status
Simulation time 2516391697485 ps
CPU time 3694.77 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 01:56:31 PM PST 24
Peak memory 839500 kb
Host smart-bdf05beb-f63c-4518-bd71-a83d61f70777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110467955 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.3110467955
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.2970286945
Short name T589
Test name
Test status
Simulation time 1058040963 ps
CPU time 8.4 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:54:51 PM PST 24
Peak memory 244692 kb
Host smart-1bc8b805-07b6-4fb2-ba71-2e2e7bb01881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970286945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.2970286945
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.876186336
Short name T121
Test name
Test status
Simulation time 135213603 ps
CPU time 4.12 seconds
Started Jan 03 12:56:09 PM PST 24
Finished Jan 03 12:57:23 PM PST 24
Peak memory 240528 kb
Host smart-5dcf2135-16bf-47b5-8efe-62e05844e2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876186336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.876186336
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.3215867585
Short name T123
Test name
Test status
Simulation time 1639875306 ps
CPU time 3.76 seconds
Started Jan 03 12:56:27 PM PST 24
Finished Jan 03 12:57:42 PM PST 24
Peak memory 238256 kb
Host smart-5383e209-043d-4616-99c8-7d614dac4799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215867585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.3215867585
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.2302224317
Short name T938
Test name
Test status
Simulation time 235680489 ps
CPU time 4.4 seconds
Started Jan 03 12:56:17 PM PST 24
Finished Jan 03 12:57:30 PM PST 24
Peak memory 240424 kb
Host smart-f35e5b92-3ac2-4574-ad16-82abfea987da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302224317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.2302224317
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.3877918608
Short name T870
Test name
Test status
Simulation time 2707523035 ps
CPU time 5.72 seconds
Started Jan 03 12:56:22 PM PST 24
Finished Jan 03 12:57:37 PM PST 24
Peak memory 238500 kb
Host smart-4bb6f6ec-9334-4e5a-a196-54590e444b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877918608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.3877918608
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.2691629313
Short name T49
Test name
Test status
Simulation time 1598047543 ps
CPU time 4.61 seconds
Started Jan 03 12:56:21 PM PST 24
Finished Jan 03 12:57:35 PM PST 24
Peak memory 238412 kb
Host smart-c31821b3-3b63-412e-b818-2b1aa69e536d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691629313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.2691629313
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.572188528
Short name T693
Test name
Test status
Simulation time 2323018007 ps
CPU time 4.58 seconds
Started Jan 03 12:56:21 PM PST 24
Finished Jan 03 12:57:35 PM PST 24
Peak memory 238432 kb
Host smart-850d594b-cc15-4d3e-810d-8e8e0cd1121c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572188528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.572188528
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.2097505461
Short name T24
Test name
Test status
Simulation time 469678717 ps
CPU time 3.6 seconds
Started Jan 03 12:56:18 PM PST 24
Finished Jan 03 12:57:33 PM PST 24
Peak memory 238384 kb
Host smart-e35f35a3-212b-4ef8-a49b-294ef442ceed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097505461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.2097505461
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.3007558838
Short name T942
Test name
Test status
Simulation time 150436255 ps
CPU time 4.53 seconds
Started Jan 03 12:56:21 PM PST 24
Finished Jan 03 12:57:37 PM PST 24
Peak memory 238376 kb
Host smart-04adc23f-b193-4176-b5ad-b9e7439795cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007558838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.3007558838
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.4276161185
Short name T504
Test name
Test status
Simulation time 1955965314 ps
CPU time 4.73 seconds
Started Jan 03 12:56:18 PM PST 24
Finished Jan 03 12:57:34 PM PST 24
Peak memory 241252 kb
Host smart-a8b9e0a8-9a90-4588-9df3-7aef71e572e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276161185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.4276161185
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.2182025760
Short name T387
Test name
Test status
Simulation time 126902103 ps
CPU time 3.72 seconds
Started Jan 03 12:56:18 PM PST 24
Finished Jan 03 12:57:33 PM PST 24
Peak memory 240696 kb
Host smart-f0601cae-2027-489d-89ac-1d1059ae4558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182025760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.2182025760
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.272522874
Short name T1130
Test name
Test status
Simulation time 152217517 ps
CPU time 1.65 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:54:48 PM PST 24
Peak memory 238504 kb
Host smart-079ca95c-56df-4ee1-b3cc-d505512477e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272522874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.272522874
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.732670152
Short name T995
Test name
Test status
Simulation time 1043921596 ps
CPU time 11.08 seconds
Started Jan 03 12:53:59 PM PST 24
Finished Jan 03 12:55:39 PM PST 24
Peak memory 246644 kb
Host smart-620116a6-1a85-4f51-9651-b7e89afef0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732670152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.732670152
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.1337437873
Short name T1043
Test name
Test status
Simulation time 17328896444 ps
CPU time 29.61 seconds
Started Jan 03 12:53:56 PM PST 24
Finished Jan 03 12:55:56 PM PST 24
Peak memory 244908 kb
Host smart-3cdbd12b-248c-47d1-9281-2c66215363f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337437873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.1337437873
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.1872829855
Short name T514
Test name
Test status
Simulation time 1899903785 ps
CPU time 4.34 seconds
Started Jan 03 12:53:55 PM PST 24
Finished Jan 03 12:55:27 PM PST 24
Peak memory 238436 kb
Host smart-62d534dd-4c00-4e6a-bac2-5782102dafeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872829855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.1872829855
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.2925713177
Short name T799
Test name
Test status
Simulation time 440456929 ps
CPU time 9.73 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:55:55 PM PST 24
Peak memory 238536 kb
Host smart-f621fa52-21b8-4afc-bc03-d1f479862063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925713177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.2925713177
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.3898519377
Short name T610
Test name
Test status
Simulation time 1945944083 ps
CPU time 12.13 seconds
Started Jan 03 12:53:49 PM PST 24
Finished Jan 03 12:55:18 PM PST 24
Peak memory 241952 kb
Host smart-9d4fb9a5-2299-48bf-9321-f47ea0599371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898519377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.3898519377
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.584013761
Short name T353
Test name
Test status
Simulation time 255705539 ps
CPU time 5.1 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:54:50 PM PST 24
Peak memory 241608 kb
Host smart-3b3272b6-1386-4181-94b8-c66465a29894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584013761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.584013761
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.2587306108
Short name T1092
Test name
Test status
Simulation time 477424052 ps
CPU time 6.63 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:55:22 PM PST 24
Peak memory 242860 kb
Host smart-0caf016e-c315-4257-8c0a-ff5063fad0b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2587306108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.2587306108
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.745555776
Short name T628
Test name
Test status
Simulation time 569683627 ps
CPU time 8.43 seconds
Started Jan 03 12:53:55 PM PST 24
Finished Jan 03 12:55:31 PM PST 24
Peak memory 245624 kb
Host smart-f141aae7-0f1f-4bbf-8c6b-2bb3219ae975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=745555776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.745555776
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.1637713031
Short name T38
Test name
Test status
Simulation time 984620222 ps
CPU time 5.71 seconds
Started Jan 03 12:53:50 PM PST 24
Finished Jan 03 12:55:11 PM PST 24
Peak memory 238432 kb
Host smart-64af8b3a-4ee0-46b2-9c38-31409ec08cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637713031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.1637713031
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.3201640763
Short name T182
Test name
Test status
Simulation time 86251171873 ps
CPU time 188.01 seconds
Started Jan 03 12:53:43 PM PST 24
Finished Jan 03 12:57:52 PM PST 24
Peak memory 243420 kb
Host smart-66745d23-7d43-4e04-ac81-19c8d20f56ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201640763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.3201640763
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.2512157427
Short name T632
Test name
Test status
Simulation time 383127264 ps
CPU time 8.24 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:12 PM PST 24
Peak memory 244876 kb
Host smart-acfe3ef8-3311-44f4-97bc-1d9d47921711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512157427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.2512157427
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.349798246
Short name T703
Test name
Test status
Simulation time 123272989 ps
CPU time 3.76 seconds
Started Jan 03 12:56:19 PM PST 24
Finished Jan 03 12:57:32 PM PST 24
Peak memory 238364 kb
Host smart-a87a5825-ec75-4107-b554-4303119df263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349798246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.349798246
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.3858373650
Short name T73
Test name
Test status
Simulation time 338876212 ps
CPU time 4.71 seconds
Started Jan 03 12:56:21 PM PST 24
Finished Jan 03 12:57:35 PM PST 24
Peak memory 243176 kb
Host smart-600e9f86-0fe5-40e1-99fa-d628c5a69c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858373650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.3858373650
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.1394857522
Short name T66
Test name
Test status
Simulation time 331713958 ps
CPU time 4.22 seconds
Started Jan 03 12:56:19 PM PST 24
Finished Jan 03 12:57:32 PM PST 24
Peak memory 238468 kb
Host smart-9cc08a11-6795-4005-bf1c-c13eaf496a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394857522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.1394857522
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.697565433
Short name T567
Test name
Test status
Simulation time 353521379 ps
CPU time 4.02 seconds
Started Jan 03 12:56:20 PM PST 24
Finished Jan 03 12:57:34 PM PST 24
Peak memory 238432 kb
Host smart-ddb2c78b-0108-44ed-af07-175d4da3f84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697565433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.697565433
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.1123878467
Short name T488
Test name
Test status
Simulation time 3089140822 ps
CPU time 4.54 seconds
Started Jan 03 12:56:37 PM PST 24
Finished Jan 03 12:57:52 PM PST 24
Peak memory 238476 kb
Host smart-92ba121a-3fff-4fa3-be71-128c99723c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123878467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.1123878467
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.2044018412
Short name T856
Test name
Test status
Simulation time 1696210886 ps
CPU time 6.23 seconds
Started Jan 03 12:56:05 PM PST 24
Finished Jan 03 12:57:19 PM PST 24
Peak memory 240800 kb
Host smart-e38bc34c-9976-4c2e-87c6-cafe4cd46200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044018412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.2044018412
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.2083043989
Short name T973
Test name
Test status
Simulation time 433697709 ps
CPU time 3.98 seconds
Started Jan 03 12:56:35 PM PST 24
Finished Jan 03 12:57:48 PM PST 24
Peak memory 238384 kb
Host smart-dc6c8222-d84d-4a08-b3df-a5dba9554f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083043989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2083043989
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.1190805263
Short name T198
Test name
Test status
Simulation time 243846429 ps
CPU time 3.45 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:22 PM PST 24
Peak memory 240388 kb
Host smart-2c4fc8ae-08cd-4dbc-949f-1342027a0583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190805263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.1190805263
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.452028478
Short name T432
Test name
Test status
Simulation time 43057262 ps
CPU time 1.49 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:54:54 PM PST 24
Peak memory 229892 kb
Host smart-2440820c-c980-43a3-b832-f11a89fd24c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452028478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.452028478
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.719943484
Short name T296
Test name
Test status
Simulation time 349298018 ps
CPU time 8.76 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:14 PM PST 24
Peak memory 236832 kb
Host smart-797809c5-2998-4e61-8eb0-114a3ad7778d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719943484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.719943484
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.1395934900
Short name T334
Test name
Test status
Simulation time 1294085952 ps
CPU time 13.54 seconds
Started Jan 03 12:53:56 PM PST 24
Finished Jan 03 12:55:50 PM PST 24
Peak memory 243888 kb
Host smart-a9f34d5a-afcc-403c-8d6e-67786fbdd3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395934900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.1395934900
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.1037552251
Short name T594
Test name
Test status
Simulation time 383987772 ps
CPU time 5.28 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:54:53 PM PST 24
Peak memory 242484 kb
Host smart-5cc5776d-dc39-4d59-9acb-aa380684802f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037552251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.1037552251
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.2233500800
Short name T512
Test name
Test status
Simulation time 2805488030 ps
CPU time 16.61 seconds
Started Jan 03 12:53:56 PM PST 24
Finished Jan 03 12:55:44 PM PST 24
Peak memory 241824 kb
Host smart-b5242cc7-b291-4479-aebf-32aacf5eef99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233500800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.2233500800
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.2001110209
Short name T1086
Test name
Test status
Simulation time 761802849 ps
CPU time 8.65 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:14 PM PST 24
Peak memory 238412 kb
Host smart-601725e2-59c5-42bb-b8ec-293fee61f4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001110209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.2001110209
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.833666445
Short name T1100
Test name
Test status
Simulation time 459170197 ps
CPU time 5.8 seconds
Started Jan 03 12:54:05 PM PST 24
Finished Jan 03 12:55:51 PM PST 24
Peak memory 238452 kb
Host smart-a462e5bb-4c4a-4f85-b79f-22dd3e77403a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833666445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.833666445
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.3906508902
Short name T368
Test name
Test status
Simulation time 501894569 ps
CPU time 3.41 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:54:58 PM PST 24
Peak memory 234772 kb
Host smart-49d598fd-5e8e-4de2-9272-201727153fdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906508902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.3906508902
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.3247092979
Short name T1026
Test name
Test status
Simulation time 460537783 ps
CPU time 6.51 seconds
Started Jan 03 12:54:15 PM PST 24
Finished Jan 03 12:56:00 PM PST 24
Peak memory 238468 kb
Host smart-87d88356-666a-4014-a275-f108ffc5ed08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247092979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.3247092979
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.424318682
Short name T549
Test name
Test status
Simulation time 3449313023 ps
CPU time 7.61 seconds
Started Jan 03 12:53:54 PM PST 24
Finished Jan 03 12:55:27 PM PST 24
Peak memory 244000 kb
Host smart-ef3f8e43-06aa-4353-89d5-5a3a6e15fb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424318682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.424318682
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.2749411302
Short name T4
Test name
Test status
Simulation time 4997189615605 ps
CPU time 5289.89 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 02:23:38 PM PST 24
Peak memory 273272 kb
Host smart-f4d35e6f-251e-4f2f-9775-79fa598ce6be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749411302 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.2749411302
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.2635338644
Short name T961
Test name
Test status
Simulation time 1010525782 ps
CPU time 13.1 seconds
Started Jan 03 12:54:07 PM PST 24
Finished Jan 03 12:56:01 PM PST 24
Peak memory 238384 kb
Host smart-4b9312a5-9411-4a5c-b220-a8811e46204e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635338644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.2635338644
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.3315129203
Short name T568
Test name
Test status
Simulation time 208008427 ps
CPU time 4.41 seconds
Started Jan 03 12:56:03 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 240544 kb
Host smart-1af7fc12-cc84-4622-947b-79e4b01cbb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315129203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.3315129203
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.4166798695
Short name T700
Test name
Test status
Simulation time 1844922331 ps
CPU time 3.04 seconds
Started Jan 03 12:56:07 PM PST 24
Finished Jan 03 12:57:19 PM PST 24
Peak memory 240712 kb
Host smart-e683e290-263b-403d-8a57-1bed2d7eca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166798695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.4166798695
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.3271775913
Short name T902
Test name
Test status
Simulation time 607068158 ps
CPU time 4.73 seconds
Started Jan 03 12:56:11 PM PST 24
Finished Jan 03 12:57:24 PM PST 24
Peak memory 240336 kb
Host smart-942de5eb-b1b1-4bcc-a549-c63c4891156a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271775913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.3271775913
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.3542485965
Short name T473
Test name
Test status
Simulation time 223982098 ps
CPU time 3.89 seconds
Started Jan 03 12:56:04 PM PST 24
Finished Jan 03 12:57:15 PM PST 24
Peak memory 241012 kb
Host smart-17924c0f-5036-4f29-a4ca-f1d47511e426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542485965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.3542485965
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.4272413635
Short name T823
Test name
Test status
Simulation time 527353165 ps
CPU time 4.07 seconds
Started Jan 03 12:56:06 PM PST 24
Finished Jan 03 12:57:17 PM PST 24
Peak memory 238332 kb
Host smart-7ed2065e-be88-4f3d-abad-a374bb5bcb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272413635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.4272413635
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.326804848
Short name T623
Test name
Test status
Simulation time 275737279 ps
CPU time 4.03 seconds
Started Jan 03 12:56:06 PM PST 24
Finished Jan 03 12:57:17 PM PST 24
Peak memory 243072 kb
Host smart-a2f2d5cd-062f-4fe6-bc6b-2a4ffd70ab7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326804848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.326804848
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.3298370287
Short name T555
Test name
Test status
Simulation time 172411050 ps
CPU time 3.95 seconds
Started Jan 03 12:56:04 PM PST 24
Finished Jan 03 12:57:16 PM PST 24
Peak memory 242752 kb
Host smart-d45ef592-9de6-4eea-8cdf-af381b35c0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298370287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.3298370287
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.651581585
Short name T400
Test name
Test status
Simulation time 196534347 ps
CPU time 3.18 seconds
Started Jan 03 12:56:18 PM PST 24
Finished Jan 03 12:57:33 PM PST 24
Peak memory 238376 kb
Host smart-a180b6ba-d983-4557-b0c5-2ff735349dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651581585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.651581585
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.1595489094
Short name T524
Test name
Test status
Simulation time 206546659 ps
CPU time 2.91 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:54:51 PM PST 24
Peak memory 238804 kb
Host smart-4c47a62f-9520-4776-b713-7900249fb751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595489094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.1595489094
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.1862300045
Short name T281
Test name
Test status
Simulation time 4413813108 ps
CPU time 17.11 seconds
Started Jan 03 12:53:55 PM PST 24
Finished Jan 03 12:55:42 PM PST 24
Peak memory 244792 kb
Host smart-9e212068-0e94-484f-b6a9-ff93e831c24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862300045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.1862300045
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.2895307040
Short name T1089
Test name
Test status
Simulation time 718451906 ps
CPU time 7.7 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:27 PM PST 24
Peak memory 242676 kb
Host smart-40fca15e-0de0-4197-86b7-ad76cd5d0afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895307040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.2895307040
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.416812582
Short name T979
Test name
Test status
Simulation time 129116383 ps
CPU time 4.67 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:55:26 PM PST 24
Peak memory 241112 kb
Host smart-b0f6dcee-3d27-4892-b877-3cec6aa37e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416812582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.416812582
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.3801214801
Short name T857
Test name
Test status
Simulation time 1017240592 ps
CPU time 11.59 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:03 PM PST 24
Peak memory 246396 kb
Host smart-86132792-857d-47e0-bda7-f6c560e6bacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801214801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.3801214801
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.1662027975
Short name T379
Test name
Test status
Simulation time 1882328259 ps
CPU time 4.42 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:55:32 PM PST 24
Peak memory 238448 kb
Host smart-0269d1cc-f768-4e06-a514-ed9c69d36656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662027975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.1662027975
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.928493486
Short name T1045
Test name
Test status
Simulation time 458382744 ps
CPU time 2.95 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:11 PM PST 24
Peak memory 240992 kb
Host smart-67822369-5d1d-4e54-a458-a110804dd722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928493486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.928493486
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.851734258
Short name T1107
Test name
Test status
Simulation time 3719537918 ps
CPU time 8.5 seconds
Started Jan 03 12:53:49 PM PST 24
Finished Jan 03 12:55:09 PM PST 24
Peak memory 238604 kb
Host smart-55c11be9-2c00-49cb-9f7b-415f06ce3048
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=851734258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.851734258
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.3718774181
Short name T850
Test name
Test status
Simulation time 121945350 ps
CPU time 4.18 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:15 PM PST 24
Peak memory 242936 kb
Host smart-d7059399-223b-4244-ba53-f2bad2c1de56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3718774181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.3718774181
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.3296912309
Short name T685
Test name
Test status
Simulation time 119111957 ps
CPU time 3.05 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:55:23 PM PST 24
Peak memory 242300 kb
Host smart-e5beef43-061e-4597-81c0-99be4bc36405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296912309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.3296912309
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.3551545287
Short name T526
Test name
Test status
Simulation time 3888125199 ps
CPU time 18.24 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:29 PM PST 24
Peak memory 246844 kb
Host smart-9b645b72-e83b-41f8-ab2d-0fbeb502f609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551545287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.3551545287
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.4165514521
Short name T12
Test name
Test status
Simulation time 235627187223 ps
CPU time 2014.47 seconds
Started Jan 03 12:54:22 PM PST 24
Finished Jan 03 01:29:38 PM PST 24
Peak memory 260712 kb
Host smart-71c45415-38ba-43e3-939e-de60836df3b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165514521 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.4165514521
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.2669163721
Short name T1097
Test name
Test status
Simulation time 502907788 ps
CPU time 3.7 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:54:56 PM PST 24
Peak memory 238344 kb
Host smart-e03be693-8f1c-492e-98ae-92b7cb896be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669163721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.2669163721
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.1987446763
Short name T42
Test name
Test status
Simulation time 245749505 ps
CPU time 4.13 seconds
Started Jan 03 12:56:35 PM PST 24
Finished Jan 03 12:57:50 PM PST 24
Peak memory 238520 kb
Host smart-3c8f331e-1d24-408d-badd-e276d210d368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987446763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.1987446763
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.4081868242
Short name T1108
Test name
Test status
Simulation time 249261784 ps
CPU time 3.2 seconds
Started Jan 03 12:56:37 PM PST 24
Finished Jan 03 12:57:51 PM PST 24
Peak memory 240620 kb
Host smart-971a3972-389b-4a91-8d23-71ec4e82dc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081868242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.4081868242
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.2705583359
Short name T1113
Test name
Test status
Simulation time 1936232078 ps
CPU time 4.62 seconds
Started Jan 03 12:56:06 PM PST 24
Finished Jan 03 12:57:18 PM PST 24
Peak memory 240324 kb
Host smart-71ece241-d3ef-40f5-b102-733cb5f0049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705583359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.2705583359
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.2960673952
Short name T422
Test name
Test status
Simulation time 223836472 ps
CPU time 3.76 seconds
Started Jan 03 12:56:02 PM PST 24
Finished Jan 03 12:57:14 PM PST 24
Peak memory 246608 kb
Host smart-43aa8c50-d25d-43be-8dec-a1bf41331439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960673952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.2960673952
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.1292075816
Short name T586
Test name
Test status
Simulation time 184710181 ps
CPU time 4.31 seconds
Started Jan 03 12:56:07 PM PST 24
Finished Jan 03 12:57:20 PM PST 24
Peak memory 238380 kb
Host smart-9a60392b-28bc-4462-9cdb-d64dceb6902b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292075816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.1292075816
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.3207056369
Short name T459
Test name
Test status
Simulation time 179361842 ps
CPU time 4.5 seconds
Started Jan 03 12:56:10 PM PST 24
Finished Jan 03 12:57:22 PM PST 24
Peak memory 246640 kb
Host smart-760a9362-e812-4cfe-9a91-e94bdb3ad809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207056369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.3207056369
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.3286725007
Short name T154
Test name
Test status
Simulation time 582131442 ps
CPU time 4.08 seconds
Started Jan 03 12:56:10 PM PST 24
Finished Jan 03 12:57:22 PM PST 24
Peak memory 238432 kb
Host smart-a17aa318-3b9f-460f-94b6-07c88cf90ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286725007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.3286725007
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.267885716
Short name T807
Test name
Test status
Simulation time 474937095 ps
CPU time 2.8 seconds
Started Jan 03 12:56:21 PM PST 24
Finished Jan 03 12:57:36 PM PST 24
Peak memory 238400 kb
Host smart-b9fa7bc3-c376-437f-af4d-05b3022ff242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267885716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.267885716
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.1774907057
Short name T646
Test name
Test status
Simulation time 196585969 ps
CPU time 3.99 seconds
Started Jan 03 12:56:06 PM PST 24
Finished Jan 03 12:57:20 PM PST 24
Peak memory 241516 kb
Host smart-5d17cd2f-58d6-4d8c-8647-dbfb86a2baab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774907057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.1774907057
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.922945962
Short name T145
Test name
Test status
Simulation time 453993276 ps
CPU time 4.53 seconds
Started Jan 03 12:56:16 PM PST 24
Finished Jan 03 12:57:29 PM PST 24
Peak memory 238316 kb
Host smart-a81c8d43-20fd-4702-833f-79213bf6de18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922945962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.922945962
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.111121171
Short name T100
Test name
Test status
Simulation time 85063489 ps
CPU time 1.52 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:54:39 PM PST 24
Peak memory 238300 kb
Host smart-2026e3e2-9449-48eb-854c-62f56929ef36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111121171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.111121171
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.209966367
Short name T46
Test name
Test status
Simulation time 464452895 ps
CPU time 10.34 seconds
Started Jan 03 12:53:54 PM PST 24
Finished Jan 03 12:55:35 PM PST 24
Peak memory 246712 kb
Host smart-2487b1e5-9473-49b3-9c41-b68ee57cb6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209966367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.209966367
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.2151247638
Short name T393
Test name
Test status
Simulation time 1225482286 ps
CPU time 8.39 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:01 PM PST 24
Peak memory 245216 kb
Host smart-cb53a535-d2c4-4305-82bf-e1107206ebc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151247638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.2151247638
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.1483552581
Short name T331
Test name
Test status
Simulation time 5245236239 ps
CPU time 23.44 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:55:05 PM PST 24
Peak memory 244548 kb
Host smart-cce3d98a-1649-42e5-a6f3-91997d656b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483552581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.1483552581
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.1351086548
Short name T707
Test name
Test status
Simulation time 286023502 ps
CPU time 4.38 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:10 PM PST 24
Peak memory 239384 kb
Host smart-af0de7d8-a835-4fd3-ae4f-c7c122ecb7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351086548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.1351086548
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.1205975110
Short name T747
Test name
Test status
Simulation time 1326321451 ps
CPU time 19.25 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:11 PM PST 24
Peak memory 246752 kb
Host smart-2427e74f-53c0-47ee-ba2a-fe24f8908203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205975110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.1205975110
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.2157102933
Short name T357
Test name
Test status
Simulation time 271988706 ps
CPU time 6.26 seconds
Started Jan 03 12:54:01 PM PST 24
Finished Jan 03 12:55:45 PM PST 24
Peak memory 238448 kb
Host smart-9d065617-0a36-4b20-b256-3241b9ea123b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157102933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.2157102933
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.1993434845
Short name T742
Test name
Test status
Simulation time 101637262 ps
CPU time 3.26 seconds
Started Jan 03 12:53:56 PM PST 24
Finished Jan 03 12:55:30 PM PST 24
Peak memory 238416 kb
Host smart-b43c1d3a-6941-4121-9320-11992e6a5774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993434845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.1993434845
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.935051693
Short name T138
Test name
Test status
Simulation time 1218569933 ps
CPU time 7.54 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:05 PM PST 24
Peak memory 238296 kb
Host smart-ea964bc8-6285-474d-81b4-f6c75d0d9779
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=935051693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.935051693
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.4193797336
Short name T509
Test name
Test status
Simulation time 1072371054 ps
CPU time 7.97 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:54:50 PM PST 24
Peak memory 238568 kb
Host smart-8d772101-29f3-4f74-8051-498fc416bd25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193797336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.4193797336
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.4172001982
Short name T604
Test name
Test status
Simulation time 287506257 ps
CPU time 4.29 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:55:46 PM PST 24
Peak memory 238444 kb
Host smart-2426038c-b10b-41b2-8864-6010902b6bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172001982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.4172001982
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.1951561610
Short name T333
Test name
Test status
Simulation time 2836792964 ps
CPU time 54.43 seconds
Started Jan 03 12:54:01 PM PST 24
Finished Jan 03 12:56:33 PM PST 24
Peak memory 238676 kb
Host smart-7eaddd6d-6ba5-458a-b07a-b533f6546112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951561610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.1951561610
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.893873937
Short name T947
Test name
Test status
Simulation time 16748438428 ps
CPU time 16.87 seconds
Started Jan 03 12:54:02 PM PST 24
Finished Jan 03 12:55:58 PM PST 24
Peak memory 237780 kb
Host smart-1ff6c049-b371-4e49-8180-b90a270bb340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893873937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.893873937
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.1595052675
Short name T428
Test name
Test status
Simulation time 285567188 ps
CPU time 4.71 seconds
Started Jan 03 12:56:18 PM PST 24
Finished Jan 03 12:57:34 PM PST 24
Peak memory 241056 kb
Host smart-b9286091-72fd-4401-bb0c-ff4df08efda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595052675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.1595052675
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.3241761455
Short name T821
Test name
Test status
Simulation time 2392932087 ps
CPU time 5.04 seconds
Started Jan 03 12:56:18 PM PST 24
Finished Jan 03 12:57:31 PM PST 24
Peak memory 238548 kb
Host smart-22c748c5-057a-4e47-8902-39533ea29309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241761455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.3241761455
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.1328637782
Short name T482
Test name
Test status
Simulation time 1895107725 ps
CPU time 4.29 seconds
Started Jan 03 12:56:38 PM PST 24
Finished Jan 03 12:57:53 PM PST 24
Peak memory 238332 kb
Host smart-79b3b874-2afc-4ac7-942c-de25066d962f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328637782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.1328637782
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.1944462333
Short name T705
Test name
Test status
Simulation time 378107836 ps
CPU time 3.89 seconds
Started Jan 03 12:56:35 PM PST 24
Finished Jan 03 12:57:49 PM PST 24
Peak memory 238388 kb
Host smart-421c4d23-a790-4cbc-9212-b6886873f1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944462333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.1944462333
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.394355026
Short name T659
Test name
Test status
Simulation time 2057632224 ps
CPU time 4.87 seconds
Started Jan 03 12:56:39 PM PST 24
Finished Jan 03 12:57:54 PM PST 24
Peak memory 238376 kb
Host smart-60537395-82cf-4850-9b65-f6c877284304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394355026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.394355026
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.3335662579
Short name T761
Test name
Test status
Simulation time 2304846156 ps
CPU time 6.01 seconds
Started Jan 03 12:56:06 PM PST 24
Finished Jan 03 12:57:21 PM PST 24
Peak memory 238460 kb
Host smart-b466dec0-cf4c-49d1-bf6e-976212ec49f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335662579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.3335662579
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.2206849208
Short name T68
Test name
Test status
Simulation time 557752224 ps
CPU time 3.95 seconds
Started Jan 03 12:56:09 PM PST 24
Finished Jan 03 12:57:21 PM PST 24
Peak memory 241136 kb
Host smart-73bb3b91-5d18-4fec-a487-85ac74031e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206849208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.2206849208
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.2747308526
Short name T391
Test name
Test status
Simulation time 580895590 ps
CPU time 3.56 seconds
Started Jan 03 12:56:19 PM PST 24
Finished Jan 03 12:57:32 PM PST 24
Peak memory 238404 kb
Host smart-efea2f83-a84d-4a21-9ab6-6fefb9396511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747308526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.2747308526
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.4089367721
Short name T1025
Test name
Test status
Simulation time 114670955 ps
CPU time 1.7 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:54:58 PM PST 24
Peak memory 239240 kb
Host smart-6962c8f1-5119-4b72-92a3-71c0e168a27d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089367721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.4089367721
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.3073328410
Short name T829
Test name
Test status
Simulation time 7258768426 ps
CPU time 32.01 seconds
Started Jan 03 12:54:12 PM PST 24
Finished Jan 03 12:56:23 PM PST 24
Peak memory 238696 kb
Host smart-300439f3-e664-46fa-bb0b-0034e5a5001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073328410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.3073328410
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.929189115
Short name T544
Test name
Test status
Simulation time 198119379 ps
CPU time 6.83 seconds
Started Jan 03 12:53:56 PM PST 24
Finished Jan 03 12:55:34 PM PST 24
Peak memory 238424 kb
Host smart-7bbcbcd0-9566-4a5d-af50-1bdcc5a16eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929189115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.929189115
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.2741668929
Short name T959
Test name
Test status
Simulation time 1720588332 ps
CPU time 4.49 seconds
Started Jan 03 12:53:56 PM PST 24
Finished Jan 03 12:55:29 PM PST 24
Peak memory 238448 kb
Host smart-08af1293-35c6-49bf-9170-38984d4026fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741668929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.2741668929
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.4004144012
Short name T713
Test name
Test status
Simulation time 205155031 ps
CPU time 3.64 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:14 PM PST 24
Peak memory 240840 kb
Host smart-63d20c36-8af9-47cd-a6f8-f49d19ad09ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004144012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.4004144012
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.920209379
Short name T412
Test name
Test status
Simulation time 951400555 ps
CPU time 16.6 seconds
Started Jan 03 12:53:51 PM PST 24
Finished Jan 03 12:55:27 PM PST 24
Peak memory 238600 kb
Host smart-0f36af53-b53a-4e47-87a3-341ac4f6cdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920209379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.920209379
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.1778350825
Short name T552
Test name
Test status
Simulation time 652708465 ps
CPU time 12.72 seconds
Started Jan 03 12:54:05 PM PST 24
Finished Jan 03 12:55:58 PM PST 24
Peak memory 243840 kb
Host smart-c63c8c9d-88ba-49c5-b000-9940ceca06d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778350825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.1778350825
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.4161740323
Short name T815
Test name
Test status
Simulation time 826949760 ps
CPU time 4.82 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:54:57 PM PST 24
Peak memory 243264 kb
Host smart-74ac8a28-d200-4bf0-afbd-c03eedbb8aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161740323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.4161740323
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.70815923
Short name T541
Test name
Test status
Simulation time 312375632 ps
CPU time 8.42 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:55:34 PM PST 24
Peak memory 242528 kb
Host smart-8acacf57-9bf7-44d0-b55b-eec1beb77931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70815923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.70815923
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.1169755419
Short name T317
Test name
Test status
Simulation time 1581781051 ps
CPU time 4.56 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:15 PM PST 24
Peak memory 238424 kb
Host smart-ff530e06-0ce6-4f24-9df5-7018dff24817
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1169755419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.1169755419
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.3615785520
Short name T731
Test name
Test status
Simulation time 235012375 ps
CPU time 3.79 seconds
Started Jan 03 12:53:51 PM PST 24
Finished Jan 03 12:55:12 PM PST 24
Peak memory 241568 kb
Host smart-37f4ed08-c6c0-4aa4-88a9-86ef20b9e869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615785520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.3615785520
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.605003167
Short name T538
Test name
Test status
Simulation time 13190210038 ps
CPU time 110.45 seconds
Started Jan 03 12:54:02 PM PST 24
Finished Jan 03 12:57:32 PM PST 24
Peak memory 255192 kb
Host smart-1d339747-d66c-418b-a4bc-582dd9b25297
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605003167 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.605003167
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.983336826
Short name T402
Test name
Test status
Simulation time 255213841 ps
CPU time 3.66 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:54:56 PM PST 24
Peak memory 243212 kb
Host smart-017a2013-d588-4651-b961-6a44d37693de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983336826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.983336826
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.2225207693
Short name T152
Test name
Test status
Simulation time 151395721 ps
CPU time 3.24 seconds
Started Jan 03 12:56:19 PM PST 24
Finished Jan 03 12:57:31 PM PST 24
Peak memory 238280 kb
Host smart-55c7146d-b319-421e-a6bb-3efe2a003ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225207693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.2225207693
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.3961358387
Short name T228
Test name
Test status
Simulation time 125331654 ps
CPU time 3.35 seconds
Started Jan 03 12:56:18 PM PST 24
Finished Jan 03 12:57:29 PM PST 24
Peak memory 238312 kb
Host smart-234ed300-c69e-43a1-9696-18e076cc7c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961358387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.3961358387
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.4017789110
Short name T872
Test name
Test status
Simulation time 261880037 ps
CPU time 3.31 seconds
Started Jan 03 12:56:08 PM PST 24
Finished Jan 03 12:57:27 PM PST 24
Peak memory 240716 kb
Host smart-3d17ab0c-7036-44e1-bad2-95e0194645eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017789110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.4017789110
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.1230369012
Short name T909
Test name
Test status
Simulation time 276755414 ps
CPU time 4.71 seconds
Started Jan 03 12:56:17 PM PST 24
Finished Jan 03 12:57:30 PM PST 24
Peak memory 238340 kb
Host smart-0c0b90f4-0804-4c8c-9b20-ad522d7b39af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230369012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.1230369012
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.3865603326
Short name T906
Test name
Test status
Simulation time 177988637 ps
CPU time 4.13 seconds
Started Jan 03 12:56:17 PM PST 24
Finished Jan 03 12:57:29 PM PST 24
Peak memory 238468 kb
Host smart-0b6dafdf-71a9-48c9-9598-4bb7e0139edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865603326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.3865603326
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.2825776228
Short name T390
Test name
Test status
Simulation time 314999866 ps
CPU time 4.65 seconds
Started Jan 03 12:56:27 PM PST 24
Finished Jan 03 12:57:43 PM PST 24
Peak memory 240388 kb
Host smart-beb1fc68-53a6-4c38-9547-2b3080ad1176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825776228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.2825776228
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.3149025467
Short name T1031
Test name
Test status
Simulation time 690778762 ps
CPU time 4.54 seconds
Started Jan 03 12:56:21 PM PST 24
Finished Jan 03 12:57:37 PM PST 24
Peak memory 238536 kb
Host smart-bb48ab0e-6a36-4f91-acf9-02da303a3ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149025467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.3149025467
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.2771666505
Short name T1090
Test name
Test status
Simulation time 230293845 ps
CPU time 4.19 seconds
Started Jan 03 12:56:15 PM PST 24
Finished Jan 03 12:57:28 PM PST 24
Peak memory 240620 kb
Host smart-21c8624b-1448-4f10-81db-1b49a6c35b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771666505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.2771666505
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.808558481
Short name T506
Test name
Test status
Simulation time 3085937818 ps
CPU time 5.97 seconds
Started Jan 03 12:56:49 PM PST 24
Finished Jan 03 12:58:01 PM PST 24
Peak memory 241112 kb
Host smart-88eab0da-7cac-4748-a82f-3094fc552602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808558481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.808558481
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.1764763053
Short name T766
Test name
Test status
Simulation time 172328917 ps
CPU time 4.08 seconds
Started Jan 03 12:56:16 PM PST 24
Finished Jan 03 12:57:29 PM PST 24
Peak memory 238264 kb
Host smart-4ac72214-a697-4d54-bfb2-5c8e4d00596d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764763053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.1764763053
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.2844467551
Short name T696
Test name
Test status
Simulation time 664739652 ps
CPU time 1.46 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:54:30 PM PST 24
Peak memory 239384 kb
Host smart-8078ba33-448e-41dc-87d2-0693e1eb9b7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844467551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.2844467551
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.1432461584
Short name T44
Test name
Test status
Simulation time 663678514 ps
CPU time 10.8 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:11 PM PST 24
Peak memory 238424 kb
Host smart-ed703930-0d37-475b-b356-cf62a509a4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432461584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1432461584
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.4072887446
Short name T466
Test name
Test status
Simulation time 260634136 ps
CPU time 4.86 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:13 PM PST 24
Peak memory 238300 kb
Host smart-2fef8f54-b452-42ac-a71e-b7a541284f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072887446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.4072887446
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.4168242027
Short name T539
Test name
Test status
Simulation time 1708760646 ps
CPU time 14.8 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:54:56 PM PST 24
Peak memory 237588 kb
Host smart-7c6c9053-643b-4474-83bc-44bbe778d5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168242027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.4168242027
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.422335094
Short name T972
Test name
Test status
Simulation time 177620563 ps
CPU time 3.78 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:54:38 PM PST 24
Peak memory 238296 kb
Host smart-b067007b-4ce9-42c0-8121-cb483fc1793d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422335094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.422335094
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.205512962
Short name T750
Test name
Test status
Simulation time 10820080826 ps
CPU time 17.01 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:24 PM PST 24
Peak memory 238644 kb
Host smart-d678ee1b-0986-4026-a1cd-5e9ceb095922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205512962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.205512962
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.3817499353
Short name T330
Test name
Test status
Simulation time 7900032328 ps
CPU time 16.06 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:07 PM PST 24
Peak memory 238572 kb
Host smart-4c8e03e6-c8fb-4d73-950f-346a5dfa9b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817499353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.3817499353
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.1194613703
Short name T142
Test name
Test status
Simulation time 508703445 ps
CPU time 5.25 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:16 PM PST 24
Peak memory 243160 kb
Host smart-fb2e1bbe-d314-4d11-b57f-e47a4c05aa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194613703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.1194613703
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.1815893977
Short name T403
Test name
Test status
Simulation time 295829014 ps
CPU time 4.21 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:54:56 PM PST 24
Peak memory 238328 kb
Host smart-711bec24-8ede-488e-978d-b52c01d84c4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815893977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.1815893977
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.3999733251
Short name T314
Test name
Test status
Simulation time 459929073 ps
CPU time 6.66 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:18 PM PST 24
Peak memory 245028 kb
Host smart-0a955895-1044-474f-94b1-ae4484ed7033
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999733251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3999733251
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.3691956371
Short name T18
Test name
Test status
Simulation time 9056367121 ps
CPU time 148.89 seconds
Started Jan 03 12:52:57 PM PST 24
Finished Jan 03 12:56:34 PM PST 24
Peak memory 268476 kb
Host smart-e02010d8-dcf1-48e9-8237-4b57125bd1e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691956371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.3691956371
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.254482042
Short name T499
Test name
Test status
Simulation time 4875573693 ps
CPU time 7.86 seconds
Started Jan 03 12:53:50 PM PST 24
Finished Jan 03 12:55:13 PM PST 24
Peak memory 238532 kb
Host smart-248b5099-b0ee-467c-b0ad-623cf0e2b57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254482042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.254482042
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.2230113644
Short name T88
Test name
Test status
Simulation time 607236386 ps
CPU time 15.09 seconds
Started Jan 03 12:53:22 PM PST 24
Finished Jan 03 12:54:38 PM PST 24
Peak memory 238444 kb
Host smart-e0836467-4f4f-49aa-b0bf-05209593ba59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230113644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.
2230113644
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.1915065163
Short name T741
Test name
Test status
Simulation time 442249720859 ps
CPU time 1034.76 seconds
Started Jan 03 12:53:02 PM PST 24
Finished Jan 03 01:11:18 PM PST 24
Peak memory 255032 kb
Host smart-346dd80a-93f4-42fb-b3d4-9d0bdf1bb6ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915065163 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.1915065163
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.1477772823
Short name T746
Test name
Test status
Simulation time 1501213188 ps
CPU time 12.83 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:55:05 PM PST 24
Peak memory 244756 kb
Host smart-b1214fad-bbd1-40e2-b822-d8f483aab3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477772823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.1477772823
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.3049868217
Short name T1034
Test name
Test status
Simulation time 73270410 ps
CPU time 1.36 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:54:57 PM PST 24
Peak memory 238252 kb
Host smart-fe93fa29-e7d6-4410-a9fe-d00856b6b544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049868217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.3049868217
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.3946314587
Short name T855
Test name
Test status
Simulation time 7781940723 ps
CPU time 17.41 seconds
Started Jan 03 12:54:00 PM PST 24
Finished Jan 03 12:55:55 PM PST 24
Peak memory 238676 kb
Host smart-c8f1dbdd-ed0e-4b4c-beed-992c1e3ea485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946314587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.3946314587
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.3835739054
Short name T511
Test name
Test status
Simulation time 327711458 ps
CPU time 4.19 seconds
Started Jan 03 12:54:02 PM PST 24
Finished Jan 03 12:55:46 PM PST 24
Peak memory 242128 kb
Host smart-89596f6f-9e64-4a10-9d87-876a9a80ba25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835739054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.3835739054
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.1137840016
Short name T90
Test name
Test status
Simulation time 1380243119 ps
CPU time 7.73 seconds
Started Jan 03 12:54:18 PM PST 24
Finished Jan 03 12:56:12 PM PST 24
Peak memory 238540 kb
Host smart-0850debe-353a-46fb-8c2c-97ac5c880e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137840016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.1137840016
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.3721604838
Short name T783
Test name
Test status
Simulation time 1626836172 ps
CPU time 5.08 seconds
Started Jan 03 12:53:54 PM PST 24
Finished Jan 03 12:55:33 PM PST 24
Peak memory 238284 kb
Host smart-6165c3c2-e88c-45b8-9f03-df5dc88ebec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721604838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.3721604838
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.4237041060
Short name T86
Test name
Test status
Simulation time 283677375 ps
CPU time 5.45 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:54:58 PM PST 24
Peak memory 245124 kb
Host smart-734a4784-1c1c-4222-b51a-242922c314d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237041060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.4237041060
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.602431201
Short name T773
Test name
Test status
Simulation time 239529592 ps
CPU time 4.93 seconds
Started Jan 03 12:54:00 PM PST 24
Finished Jan 03 12:55:40 PM PST 24
Peak memory 242228 kb
Host smart-7512c0ee-f651-497f-b9b3-26f2f3648a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602431201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.602431201
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.4199593484
Short name T611
Test name
Test status
Simulation time 426275504 ps
CPU time 6.55 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:55:01 PM PST 24
Peak memory 238236 kb
Host smart-2c92d028-b196-408c-8607-938184fcd714
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199593484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.4199593484
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.2532180799
Short name T494
Test name
Test status
Simulation time 454530950 ps
CPU time 6 seconds
Started Jan 03 12:54:21 PM PST 24
Finished Jan 03 12:56:05 PM PST 24
Peak memory 238536 kb
Host smart-4eca2b6a-4f4d-4e50-b4b5-f01f6d10e011
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2532180799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.2532180799
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.2836021825
Short name T8
Test name
Test status
Simulation time 3167213102 ps
CPU time 7.52 seconds
Started Jan 03 12:54:06 PM PST 24
Finished Jan 03 12:55:52 PM PST 24
Peak memory 238564 kb
Host smart-b7d7c43f-b57e-482b-9845-7f80585b3390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836021825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.2836021825
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.781721132
Short name T991
Test name
Test status
Simulation time 35604385331 ps
CPU time 232.87 seconds
Started Jan 03 12:54:10 PM PST 24
Finished Jan 03 12:59:41 PM PST 24
Peak memory 240136 kb
Host smart-58f8912f-33ee-4276-b93a-04343de78242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781721132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.
781721132
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.2647979585
Short name T763
Test name
Test status
Simulation time 311450529506 ps
CPU time 2341.51 seconds
Started Jan 03 12:54:03 PM PST 24
Finished Jan 03 01:34:43 PM PST 24
Peak memory 304260 kb
Host smart-1734b476-e1d2-49b8-befd-1fbe06a34a7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647979585 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.2647979585
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.1139870381
Short name T545
Test name
Test status
Simulation time 1200564597 ps
CPU time 13.99 seconds
Started Jan 03 12:54:04 PM PST 24
Finished Jan 03 12:56:00 PM PST 24
Peak memory 246552 kb
Host smart-c078af0f-0f37-454f-b9df-db69f29e7a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139870381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.1139870381
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.999066134
Short name T159
Test name
Test status
Simulation time 1043599440 ps
CPU time 3.16 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:54:37 PM PST 24
Peak memory 238888 kb
Host smart-dffa0acf-8e30-4394-a53a-7ae279a63894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999066134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.999066134
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.1219956709
Short name T523
Test name
Test status
Simulation time 174018996 ps
CPU time 4.54 seconds
Started Jan 03 12:54:06 PM PST 24
Finished Jan 03 12:55:49 PM PST 24
Peak memory 238352 kb
Host smart-6648f30b-ee58-4c76-b711-e8de7f38f70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219956709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.1219956709
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.2834384907
Short name T892
Test name
Test status
Simulation time 387163686 ps
CPU time 4.59 seconds
Started Jan 03 12:54:00 PM PST 24
Finished Jan 03 12:55:42 PM PST 24
Peak memory 245500 kb
Host smart-8643fbca-ccdd-4889-9618-e69ef3625284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834384907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.2834384907
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.378487250
Short name T671
Test name
Test status
Simulation time 1764357523 ps
CPU time 4.63 seconds
Started Jan 03 12:53:54 PM PST 24
Finished Jan 03 12:55:29 PM PST 24
Peak memory 241212 kb
Host smart-20898cea-f722-43cb-900f-002edaf65bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378487250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.378487250
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.393547964
Short name T863
Test name
Test status
Simulation time 1699004360 ps
CPU time 24.45 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:55:47 PM PST 24
Peak memory 246772 kb
Host smart-746c1c2b-4dc0-4616-8efc-2dc0dfb081ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393547964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.393547964
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.3750374405
Short name T661
Test name
Test status
Simulation time 185094130 ps
CPU time 6.64 seconds
Started Jan 03 12:53:59 PM PST 24
Finished Jan 03 12:55:35 PM PST 24
Peak memory 246260 kb
Host smart-049c4725-3bb1-41d8-98ae-547ae386a73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750374405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.3750374405
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.2737708478
Short name T1087
Test name
Test status
Simulation time 556889048 ps
CPU time 3.26 seconds
Started Jan 03 12:53:58 PM PST 24
Finished Jan 03 12:55:33 PM PST 24
Peak memory 238388 kb
Host smart-0cb2c8eb-3c36-465a-96ea-6f500b947892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737708478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.2737708478
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.1651312739
Short name T734
Test name
Test status
Simulation time 891966076 ps
CPU time 10.88 seconds
Started Jan 03 12:54:02 PM PST 24
Finished Jan 03 12:55:49 PM PST 24
Peak memory 238464 kb
Host smart-705fbc97-1539-42bd-8814-11887fe58cfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651312739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.1651312739
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.2807621760
Short name T584
Test name
Test status
Simulation time 211097026 ps
CPU time 5.85 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:54:58 PM PST 24
Peak memory 243572 kb
Host smart-cb230e3f-f1cc-4015-8a73-64f6a2363172
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2807621760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2807621760
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.2537496593
Short name T503
Test name
Test status
Simulation time 187471745 ps
CPU time 3.64 seconds
Started Jan 03 12:54:06 PM PST 24
Finished Jan 03 12:55:48 PM PST 24
Peak memory 238508 kb
Host smart-c5cb7fd5-721b-425d-a688-46311c46bfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537496593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.2537496593
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.2862138179
Short name T817
Test name
Test status
Simulation time 2037168056 ps
CPU time 27.74 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 12:55:26 PM PST 24
Peak memory 239632 kb
Host smart-cd0d7497-c5bf-4154-9783-494c266068f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862138179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.2862138179
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.826431900
Short name T1064
Test name
Test status
Simulation time 137128120296 ps
CPU time 2768.14 seconds
Started Jan 03 12:53:49 PM PST 24
Finished Jan 03 01:41:24 PM PST 24
Peak memory 262644 kb
Host smart-3fa1f863-97ba-40a6-b5e6-67e2947a86d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826431900 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.826431900
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.41070633
Short name T841
Test name
Test status
Simulation time 842260479 ps
CPU time 10.23 seconds
Started Jan 03 12:54:11 PM PST 24
Finished Jan 03 12:55:56 PM PST 24
Peak memory 243284 kb
Host smart-2f78f60c-d564-4f29-accb-4700e4a46bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41070633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.41070633
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.3596130530
Short name T367
Test name
Test status
Simulation time 113198814 ps
CPU time 1.64 seconds
Started Jan 03 12:54:01 PM PST 24
Finished Jan 03 12:55:39 PM PST 24
Peak memory 238404 kb
Host smart-28f723d6-3afd-4b0f-89ad-f22606bc1c3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596130530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.3596130530
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.2985660816
Short name T664
Test name
Test status
Simulation time 333813754 ps
CPU time 7.2 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:54:46 PM PST 24
Peak memory 244124 kb
Host smart-71c2740c-28df-4d85-bcfe-8cfcb49667e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985660816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.2985660816
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.2087288097
Short name T253
Test name
Test status
Simulation time 2488597166 ps
CPU time 19.94 seconds
Started Jan 03 12:53:33 PM PST 24
Finished Jan 03 12:54:50 PM PST 24
Peak memory 238620 kb
Host smart-3e5d3222-d4ad-40da-9662-0e046038f1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087288097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.2087288097
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.965347601
Short name T519
Test name
Test status
Simulation time 146625030 ps
CPU time 3.87 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:55:29 PM PST 24
Peak memory 238284 kb
Host smart-3186acf5-9a69-4c03-809d-468c96428f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965347601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.965347601
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.1697729124
Short name T441
Test name
Test status
Simulation time 595981789 ps
CPU time 7.5 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:04 PM PST 24
Peak memory 238392 kb
Host smart-61caf0e1-bacf-4941-bb49-028ff81d8155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697729124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.1697729124
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.2230598711
Short name T781
Test name
Test status
Simulation time 2618687803 ps
CPU time 5.35 seconds
Started Jan 03 12:53:56 PM PST 24
Finished Jan 03 12:55:33 PM PST 24
Peak memory 243040 kb
Host smart-6644fa4b-0ef7-4f7a-8461-d3797d5088c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230598711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.2230598711
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.1362758935
Short name T181
Test name
Test status
Simulation time 1419483187 ps
CPU time 16.27 seconds
Started Jan 03 12:53:55 PM PST 24
Finished Jan 03 12:55:41 PM PST 24
Peak memory 242796 kb
Host smart-648d3f41-5a3e-43a0-b1d0-cd5832ea23bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1362758935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.1362758935
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.1634900523
Short name T313
Test name
Test status
Simulation time 251807732 ps
CPU time 6.74 seconds
Started Jan 03 12:54:06 PM PST 24
Finished Jan 03 12:55:52 PM PST 24
Peak memory 245404 kb
Host smart-ee64f767-efd2-46e8-b14b-871e3316fad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634900523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1634900523
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.4010394068
Short name T675
Test name
Test status
Simulation time 523773340 ps
CPU time 5.83 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:54:38 PM PST 24
Peak memory 238408 kb
Host smart-285280df-069a-43be-a8d3-e747a07ceaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010394068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.4010394068
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.4291192737
Short name T275
Test name
Test status
Simulation time 9646357301 ps
CPU time 23.23 seconds
Started Jan 03 12:54:03 PM PST 24
Finished Jan 03 12:56:05 PM PST 24
Peak memory 238604 kb
Host smart-dcfe81d1-547c-4368-81a3-a36feddc2837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291192737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.4291192737
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.3369584281
Short name T95
Test name
Test status
Simulation time 1561606034 ps
CPU time 9.8 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:10 PM PST 24
Peak memory 237536 kb
Host smart-1e63ac22-df2c-44a1-a0f2-fe15ea1dc512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369584281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.3369584281
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.2605718226
Short name T197
Test name
Test status
Simulation time 333011494 ps
CPU time 3.64 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:55:31 PM PST 24
Peak memory 239220 kb
Host smart-553f6e68-40b5-4e01-a0db-af38b23c98e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605718226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.2605718226
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.2410800415
Short name T27
Test name
Test status
Simulation time 369536421 ps
CPU time 6.31 seconds
Started Jan 03 12:53:59 PM PST 24
Finished Jan 03 12:55:42 PM PST 24
Peak memory 238532 kb
Host smart-1a1b1c4a-7bb0-4768-ade7-65656b2f30f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410800415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.2410800415
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.1328378853
Short name T497
Test name
Test status
Simulation time 430608557 ps
CPU time 5.32 seconds
Started Jan 03 12:53:55 PM PST 24
Finished Jan 03 12:55:28 PM PST 24
Peak memory 238444 kb
Host smart-90e0011b-e444-4041-aa16-5eb0f35a177e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328378853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.1328378853
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.4001045956
Short name T92
Test name
Test status
Simulation time 2285212565 ps
CPU time 18.77 seconds
Started Jan 03 12:53:55 PM PST 24
Finished Jan 03 12:55:39 PM PST 24
Peak memory 238688 kb
Host smart-fc3cd18e-2737-4beb-8364-f84c09b64a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001045956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.4001045956
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.305866790
Short name T375
Test name
Test status
Simulation time 148665279 ps
CPU time 3.49 seconds
Started Jan 03 12:54:04 PM PST 24
Finished Jan 03 12:55:46 PM PST 24
Peak memory 240880 kb
Host smart-371b3a4f-3ac6-4575-9860-38c0d3ed152b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305866790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.305866790
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.1835775609
Short name T717
Test name
Test status
Simulation time 3824381062 ps
CPU time 23.19 seconds
Started Jan 03 12:54:00 PM PST 24
Finished Jan 03 12:55:57 PM PST 24
Peak memory 238752 kb
Host smart-3504c8ce-7a2a-47bd-94c9-c6a7f968e359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835775609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.1835775609
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.2533350749
Short name T401
Test name
Test status
Simulation time 1484915633 ps
CPU time 3.02 seconds
Started Jan 03 12:54:06 PM PST 24
Finished Jan 03 12:55:48 PM PST 24
Peak memory 240636 kb
Host smart-7bd9ad1e-8a65-411c-8511-7092796731bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533350749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.2533350749
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.3679548245
Short name T409
Test name
Test status
Simulation time 236082754 ps
CPU time 3.75 seconds
Started Jan 03 12:53:58 PM PST 24
Finished Jan 03 12:55:32 PM PST 24
Peak memory 243716 kb
Host smart-10b59d91-5df0-45e2-87a3-e89c865565a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679548245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.3679548245
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.3857169937
Short name T676
Test name
Test status
Simulation time 1731614254 ps
CPU time 5.26 seconds
Started Jan 03 12:54:00 PM PST 24
Finished Jan 03 12:55:43 PM PST 24
Peak memory 241132 kb
Host smart-39a016f9-4a59-4743-a81f-a077c76dd539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3857169937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.3857169937
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.2987345762
Short name T660
Test name
Test status
Simulation time 204472602 ps
CPU time 2.91 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:54:47 PM PST 24
Peak memory 240904 kb
Host smart-d5f2ed64-2c98-4a12-9806-6449b4d484ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987345762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.2987345762
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.3510560114
Short name T1051
Test name
Test status
Simulation time 314501658935 ps
CPU time 505.36 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 01:03:41 PM PST 24
Peak memory 255156 kb
Host smart-e18b7cd7-63ef-4823-9d70-a358887224f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510560114 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.3510560114
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.668370774
Short name T490
Test name
Test status
Simulation time 551730827 ps
CPU time 9.01 seconds
Started Jan 03 12:53:58 PM PST 24
Finished Jan 03 12:55:45 PM PST 24
Peak memory 246076 kb
Host smart-2cf751f0-454d-4adb-a14a-1c08e5e74b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668370774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.668370774
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.3161809624
Short name T423
Test name
Test status
Simulation time 98097545 ps
CPU time 1.77 seconds
Started Jan 03 12:54:06 PM PST 24
Finished Jan 03 12:55:47 PM PST 24
Peak memory 239220 kb
Host smart-a7f83040-a406-4e00-be92-6899d500d1d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161809624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.3161809624
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.2877179154
Short name T559
Test name
Test status
Simulation time 168373165 ps
CPU time 6.84 seconds
Started Jan 03 12:54:02 PM PST 24
Finished Jan 03 12:55:49 PM PST 24
Peak memory 242616 kb
Host smart-7c4b235a-1444-4bf7-84a0-dc9ea6e67a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877179154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.2877179154
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.3965495180
Short name T745
Test name
Test status
Simulation time 435200462 ps
CPU time 6.76 seconds
Started Jan 03 12:54:15 PM PST 24
Finished Jan 03 12:56:01 PM PST 24
Peak memory 238516 kb
Host smart-8fe9be0e-c5ff-42a1-be3e-1cebb4b816ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965495180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.3965495180
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.3764104622
Short name T564
Test name
Test status
Simulation time 299765543 ps
CPU time 3.61 seconds
Started Jan 03 12:54:00 PM PST 24
Finished Jan 03 12:55:39 PM PST 24
Peak memory 238428 kb
Host smart-8513cab6-1ad4-4f02-b69c-5c1c3fd46ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764104622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.3764104622
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.3031087486
Short name T714
Test name
Test status
Simulation time 1903016232 ps
CPU time 10.09 seconds
Started Jan 03 12:54:15 PM PST 24
Finished Jan 03 12:56:04 PM PST 24
Peak memory 238616 kb
Host smart-74a019d4-556a-4373-84a4-d3be767fd96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031087486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.3031087486
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.2073413932
Short name T621
Test name
Test status
Simulation time 1311071194 ps
CPU time 14.31 seconds
Started Jan 03 12:54:15 PM PST 24
Finished Jan 03 12:56:14 PM PST 24
Peak memory 238464 kb
Host smart-f216cd3b-716f-421f-947e-d627200a6bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073413932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.2073413932
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.570170842
Short name T759
Test name
Test status
Simulation time 402465583 ps
CPU time 4.18 seconds
Started Jan 03 12:54:14 PM PST 24
Finished Jan 03 12:55:53 PM PST 24
Peak memory 241188 kb
Host smart-7e74a64d-0bfe-4d40-acf4-6f12f0537a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570170842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.570170842
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.3686979999
Short name T395
Test name
Test status
Simulation time 147981115 ps
CPU time 3.99 seconds
Started Jan 03 12:53:56 PM PST 24
Finished Jan 03 12:55:29 PM PST 24
Peak memory 242644 kb
Host smart-54d88011-8851-4755-9b89-ca2e18c4213f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3686979999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.3686979999
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.2837728090
Short name T316
Test name
Test status
Simulation time 3949247019 ps
CPU time 7.63 seconds
Started Jan 03 12:53:59 PM PST 24
Finished Jan 03 12:55:43 PM PST 24
Peak memory 243868 kb
Host smart-a0c5f3b9-6115-4120-9054-a6caf573510a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2837728090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2837728090
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.1301495851
Short name T189
Test name
Test status
Simulation time 256507754820 ps
CPU time 3061.45 seconds
Started Jan 03 12:54:09 PM PST 24
Finished Jan 03 01:46:50 PM PST 24
Peak memory 345204 kb
Host smart-043a57c6-98b5-40b5-804a-5476bee13e78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301495851 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.1301495851
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.3984808451
Short name T493
Test name
Test status
Simulation time 1728212511 ps
CPU time 10.45 seconds
Started Jan 03 12:53:58 PM PST 24
Finished Jan 03 12:55:46 PM PST 24
Peak memory 238556 kb
Host smart-d68f1972-9eff-41b9-8028-80dad02c850c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984808451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.3984808451
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.4189210475
Short name T710
Test name
Test status
Simulation time 189677762 ps
CPU time 1.56 seconds
Started Jan 03 12:54:13 PM PST 24
Finished Jan 03 12:55:52 PM PST 24
Peak memory 238252 kb
Host smart-3b2821ef-4907-40db-8766-014a1a7342d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189210475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.4189210475
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.1954065084
Short name T782
Test name
Test status
Simulation time 120116404 ps
CPU time 4.19 seconds
Started Jan 03 12:53:51 PM PST 24
Finished Jan 03 12:55:12 PM PST 24
Peak memory 242976 kb
Host smart-95e40b93-9e4f-4445-a3e2-f4c9073b84e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954065084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.1954065084
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.2047910648
Short name T970
Test name
Test status
Simulation time 615438565 ps
CPU time 4.76 seconds
Started Jan 03 12:54:02 PM PST 24
Finished Jan 03 12:55:47 PM PST 24
Peak memory 238420 kb
Host smart-12efb121-e4fa-4fd9-a326-f86312458f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047910648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.2047910648
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.378368123
Short name T399
Test name
Test status
Simulation time 630711530 ps
CPU time 14.03 seconds
Started Jan 03 12:53:59 PM PST 24
Finished Jan 03 12:55:43 PM PST 24
Peak memory 238576 kb
Host smart-09e4b8f2-8198-4e7c-ad16-d1029e539979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378368123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.378368123
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.962886424
Short name T702
Test name
Test status
Simulation time 1095323649 ps
CPU time 15.46 seconds
Started Jan 03 12:53:50 PM PST 24
Finished Jan 03 12:55:21 PM PST 24
Peak memory 246680 kb
Host smart-910a3fd0-cef6-46fa-94f4-9b7cca46fa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962886424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.962886424
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.2198270251
Short name T457
Test name
Test status
Simulation time 328236250 ps
CPU time 5.7 seconds
Started Jan 03 12:53:54 PM PST 24
Finished Jan 03 12:55:30 PM PST 24
Peak memory 244760 kb
Host smart-74735f8b-27e1-4c81-b08a-7f48f5e23875
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198270251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.2198270251
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.3728108831
Short name T735
Test name
Test status
Simulation time 3387950211 ps
CPU time 6.87 seconds
Started Jan 03 12:53:56 PM PST 24
Finished Jan 03 12:55:34 PM PST 24
Peak memory 243352 kb
Host smart-50ebcf3f-1607-4d9c-b7d4-6527c9aac0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728108831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.3728108831
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.403665155
Short name T1020
Test name
Test status
Simulation time 1047823735717 ps
CPU time 9630.62 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 03:35:59 PM PST 24
Peak memory 680744 kb
Host smart-a86a3c9e-92d6-417c-8963-b52f479de192
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403665155 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.403665155
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.3827144861
Short name T460
Test name
Test status
Simulation time 816983577 ps
CPU time 11.85 seconds
Started Jan 03 12:53:59 PM PST 24
Finished Jan 03 12:55:47 PM PST 24
Peak memory 237684 kb
Host smart-9d94eb14-8016-44b7-9b6c-f99dafffce7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827144861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.3827144861
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.461028212
Short name T1012
Test name
Test status
Simulation time 234872398 ps
CPU time 1.83 seconds
Started Jan 03 12:54:04 PM PST 24
Finished Jan 03 12:55:48 PM PST 24
Peak memory 238412 kb
Host smart-36871b96-d27b-4b8b-b8f9-5d477f6ee41c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461028212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.461028212
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.701732787
Short name T163
Test name
Test status
Simulation time 3697966457 ps
CPU time 10.36 seconds
Started Jan 03 12:53:58 PM PST 24
Finished Jan 03 12:55:38 PM PST 24
Peak memory 238672 kb
Host smart-c0c7f4a9-8e69-4142-b5ca-3bdf8d7b39ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701732787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.701732787
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.253734311
Short name T618
Test name
Test status
Simulation time 1737239929 ps
CPU time 9.99 seconds
Started Jan 03 12:54:00 PM PST 24
Finished Jan 03 12:55:48 PM PST 24
Peak memory 238584 kb
Host smart-f99615f8-1f56-46cb-98b5-f3f312c21ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253734311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.253734311
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.2417964925
Short name T737
Test name
Test status
Simulation time 1260003571 ps
CPU time 12.37 seconds
Started Jan 03 12:53:59 PM PST 24
Finished Jan 03 12:55:48 PM PST 24
Peak memory 238560 kb
Host smart-4cbb9f2c-9549-45c3-a418-b993e8d78d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417964925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.2417964925
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.3357520294
Short name T349
Test name
Test status
Simulation time 296410601 ps
CPU time 5.47 seconds
Started Jan 03 12:54:17 PM PST 24
Finished Jan 03 12:55:57 PM PST 24
Peak memory 243696 kb
Host smart-39ac9199-6a45-4f7d-aac2-0231c2b11e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357520294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.3357520294
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.1463955392
Short name T565
Test name
Test status
Simulation time 544230525 ps
CPU time 5.74 seconds
Started Jan 03 12:54:02 PM PST 24
Finished Jan 03 12:55:42 PM PST 24
Peak memory 238316 kb
Host smart-12ee5e5a-bcbe-4520-b531-96d6661dd297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463955392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.1463955392
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.1294903465
Short name T921
Test name
Test status
Simulation time 167987629 ps
CPU time 3.25 seconds
Started Jan 03 12:54:01 PM PST 24
Finished Jan 03 12:55:37 PM PST 24
Peak memory 238344 kb
Host smart-91958b27-1321-4432-948e-f2e2f2b168d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1294903465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.1294903465
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.2154736317
Short name T1008
Test name
Test status
Simulation time 5717082781 ps
CPU time 7.8 seconds
Started Jan 03 12:54:01 PM PST 24
Finished Jan 03 12:55:45 PM PST 24
Peak memory 238620 kb
Host smart-0dbffe33-a04e-4999-a35a-3cd24680758e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154736317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.2154736317
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.2176369793
Short name T325
Test name
Test status
Simulation time 19081290382 ps
CPU time 82.86 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:56:49 PM PST 24
Peak memory 246888 kb
Host smart-48c26aee-d6f1-4114-9e0c-61a9c28e7639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176369793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.2176369793
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.2289171856
Short name T876
Test name
Test status
Simulation time 873857841626 ps
CPU time 5294.19 seconds
Started Jan 03 12:54:00 PM PST 24
Finished Jan 03 02:23:50 PM PST 24
Peak memory 1030428 kb
Host smart-50cd4aed-1340-4588-87d5-125ba80b1033
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289171856 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.2289171856
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.3849228844
Short name T322
Test name
Test status
Simulation time 4234728784 ps
CPU time 7.75 seconds
Started Jan 03 12:53:59 PM PST 24
Finished Jan 03 12:55:38 PM PST 24
Peak memory 238572 kb
Host smart-553ca527-c275-4610-a47a-7c6519f918e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849228844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.3849228844
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.186188184
Short name T137
Test name
Test status
Simulation time 5238851516 ps
CPU time 9.68 seconds
Started Jan 03 12:54:24 PM PST 24
Finished Jan 03 12:56:17 PM PST 24
Peak memory 238712 kb
Host smart-b81666b0-146f-4780-a1bd-14ecc3ddb41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186188184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.186188184
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.4227404497
Short name T286
Test name
Test status
Simulation time 2518940594 ps
CPU time 9.76 seconds
Started Jan 03 12:53:58 PM PST 24
Finished Jan 03 12:55:45 PM PST 24
Peak memory 238568 kb
Host smart-c24865ca-1c14-4595-a510-9f3d547fb399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227404497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.4227404497
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.2979022646
Short name T378
Test name
Test status
Simulation time 239265324 ps
CPU time 2.88 seconds
Started Jan 03 12:54:18 PM PST 24
Finished Jan 03 12:56:07 PM PST 24
Peak memory 243268 kb
Host smart-6c904aff-e3f6-4d79-8567-43b71e41dc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979022646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.2979022646
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.3155454062
Short name T904
Test name
Test status
Simulation time 2663448653 ps
CPU time 7.77 seconds
Started Jan 03 12:54:09 PM PST 24
Finished Jan 03 12:55:55 PM PST 24
Peak memory 241280 kb
Host smart-c0e7ae6f-3d13-4c06-8e6d-baaaf1d37ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155454062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.3155454062
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.784329741
Short name T886
Test name
Test status
Simulation time 445865097 ps
CPU time 7.8 seconds
Started Jan 03 12:53:52 PM PST 24
Finished Jan 03 12:55:30 PM PST 24
Peak memory 238448 kb
Host smart-4fe4aabe-fe35-4f7b-89a0-9d68a7bd2e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784329741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.784329741
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.2901203
Short name T515
Test name
Test status
Simulation time 646632035 ps
CPU time 4.99 seconds
Started Jan 03 12:54:08 PM PST 24
Finished Jan 03 12:55:52 PM PST 24
Peak memory 242156 kb
Host smart-4674c6bc-9d42-4258-8d26-5cabbf252cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.2901203
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.15404580
Short name T720
Test name
Test status
Simulation time 711333642 ps
CPU time 21.15 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:56:03 PM PST 24
Peak memory 238452 kb
Host smart-f8572959-14bf-4459-815c-885ac8166c25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15404580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.15404580
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.2036958509
Short name T920
Test name
Test status
Simulation time 131024440 ps
CPU time 3.02 seconds
Started Jan 03 12:53:54 PM PST 24
Finished Jan 03 12:55:26 PM PST 24
Peak memory 238520 kb
Host smart-34120e7e-be83-49dd-b802-c1f01ef73ea9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2036958509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.2036958509
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.1174792615
Short name T337
Test name
Test status
Simulation time 731093308 ps
CPU time 26.61 seconds
Started Jan 03 12:53:58 PM PST 24
Finished Jan 03 12:55:56 PM PST 24
Peak memory 238512 kb
Host smart-1afe5afe-d4f3-4ecc-b110-626d3f339755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174792615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.1174792615
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.3828428311
Short name T343
Test name
Test status
Simulation time 1044380258 ps
CPU time 13.35 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:55:40 PM PST 24
Peak memory 238372 kb
Host smart-eb8423f4-96cc-4449-bf4d-c26e3a75aee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828428311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.3828428311
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.136830668
Short name T1084
Test name
Test status
Simulation time 93059230 ps
CPU time 1.58 seconds
Started Jan 03 12:54:22 PM PST 24
Finished Jan 03 12:56:05 PM PST 24
Peak memory 239264 kb
Host smart-afed2725-5e64-4f5c-9235-2c23278f8ec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136830668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.136830668
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.3823430580
Short name T278
Test name
Test status
Simulation time 509189068 ps
CPU time 5.93 seconds
Started Jan 03 12:53:59 PM PST 24
Finished Jan 03 12:55:41 PM PST 24
Peak memory 238488 kb
Host smart-c88a4e78-dfa3-400f-a844-a3d1a60c0983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823430580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3823430580
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.237368608
Short name T955
Test name
Test status
Simulation time 6953332283 ps
CPU time 15.95 seconds
Started Jan 03 12:54:14 PM PST 24
Finished Jan 03 12:56:04 PM PST 24
Peak memory 244604 kb
Host smart-b480554a-f10c-4a2a-8361-a2843a138f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237368608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.237368608
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.4273951285
Short name T43
Test name
Test status
Simulation time 2186414538 ps
CPU time 6.14 seconds
Started Jan 03 12:54:12 PM PST 24
Finished Jan 03 12:55:57 PM PST 24
Peak memory 242532 kb
Host smart-fd1ed5c5-25dc-4cad-b375-8baa965c1420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273951285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.4273951285
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.2497246393
Short name T130
Test name
Test status
Simulation time 2070585164 ps
CPU time 26.19 seconds
Started Jan 03 12:54:24 PM PST 24
Finished Jan 03 12:56:34 PM PST 24
Peak memory 238684 kb
Host smart-9b84c186-89d7-4569-b576-e215e752ec14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497246393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.2497246393
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.606443606
Short name T438
Test name
Test status
Simulation time 511628098 ps
CPU time 3.32 seconds
Started Jan 03 12:54:10 PM PST 24
Finished Jan 03 12:55:49 PM PST 24
Peak memory 241704 kb
Host smart-343fd8d8-e7c0-444d-b095-e3fabe296c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606443606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.606443606
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.1891653175
Short name T151
Test name
Test status
Simulation time 795544639 ps
CPU time 14.18 seconds
Started Jan 03 12:53:58 PM PST 24
Finished Jan 03 12:55:44 PM PST 24
Peak memory 238360 kb
Host smart-785451c8-e01e-4caf-8692-a37afad9322b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1891653175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.1891653175
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.1037649144
Short name T486
Test name
Test status
Simulation time 87837552 ps
CPU time 2.41 seconds
Started Jan 03 12:54:14 PM PST 24
Finished Jan 03 12:56:05 PM PST 24
Peak memory 238448 kb
Host smart-70d736be-0347-4637-99f5-04b217887fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037649144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.1037649144
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.3088184104
Short name T932
Test name
Test status
Simulation time 394824747 ps
CPU time 9.82 seconds
Started Jan 03 12:54:10 PM PST 24
Finished Jan 03 12:55:58 PM PST 24
Peak memory 238500 kb
Host smart-1cb61204-f957-4ace-8b6a-ee643ca2eb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088184104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.3088184104
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.25450426
Short name T665
Test name
Test status
Simulation time 51057649 ps
CPU time 1.49 seconds
Started Jan 03 12:54:17 PM PST 24
Finished Jan 03 12:55:53 PM PST 24
Peak memory 238268 kb
Host smart-af446267-5b03-4654-b2da-f1ed3eec8fc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25450426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.25450426
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.3584967371
Short name T478
Test name
Test status
Simulation time 235102312 ps
CPU time 6.55 seconds
Started Jan 03 12:54:16 PM PST 24
Finished Jan 03 12:56:09 PM PST 24
Peak memory 243856 kb
Host smart-11348c2a-5297-4ea8-bbd4-d93296584083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584967371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.3584967371
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.1278488248
Short name T329
Test name
Test status
Simulation time 2411651176 ps
CPU time 11.35 seconds
Started Jan 03 12:54:09 PM PST 24
Finished Jan 03 12:55:59 PM PST 24
Peak memory 237584 kb
Host smart-d0833e94-a007-44ed-b27b-0d4c836b9b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278488248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.1278488248
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.2748281536
Short name T41
Test name
Test status
Simulation time 662807563 ps
CPU time 4.48 seconds
Started Jan 03 12:54:11 PM PST 24
Finished Jan 03 12:55:50 PM PST 24
Peak memory 238308 kb
Host smart-2df4c95e-159b-410e-8bb7-52918a5453e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748281536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.2748281536
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.3800519932
Short name T965
Test name
Test status
Simulation time 313260149 ps
CPU time 4.19 seconds
Started Jan 03 12:53:58 PM PST 24
Finished Jan 03 12:55:51 PM PST 24
Peak memory 246460 kb
Host smart-b8b4244b-dbc2-40e0-be9a-ce6844c2fce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800519932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.3800519932
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.1457591536
Short name T1070
Test name
Test status
Simulation time 580697303 ps
CPU time 8.45 seconds
Started Jan 03 12:54:14 PM PST 24
Finished Jan 03 12:55:57 PM PST 24
Peak memory 246616 kb
Host smart-9a4a07fd-ccee-4c93-9ba9-f9a23bc5e386
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1457591536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.1457591536
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.3816262338
Short name T738
Test name
Test status
Simulation time 217544828 ps
CPU time 6.12 seconds
Started Jan 03 12:54:15 PM PST 24
Finished Jan 03 12:56:00 PM PST 24
Peak memory 238476 kb
Host smart-fde09d87-8e74-459f-acae-b45b079160f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3816262338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.3816262338
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.448694540
Short name T811
Test name
Test status
Simulation time 135507565 ps
CPU time 3.86 seconds
Started Jan 03 12:54:19 PM PST 24
Finished Jan 03 12:55:58 PM PST 24
Peak memory 238488 kb
Host smart-15c00efa-a1b5-4b60-8eba-a10464044b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448694540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.448694540
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.1903177060
Short name T585
Test name
Test status
Simulation time 8942420339 ps
CPU time 61.55 seconds
Started Jan 03 12:54:19 PM PST 24
Finished Jan 03 12:57:07 PM PST 24
Peak memory 240600 kb
Host smart-f79db1f5-0583-479e-8dbc-b584a184d456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903177060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.1903177060
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.4049279930
Short name T16
Test name
Test status
Simulation time 52485357480 ps
CPU time 879.44 seconds
Started Jan 03 12:54:06 PM PST 24
Finished Jan 03 01:10:24 PM PST 24
Peak memory 246908 kb
Host smart-5ace1d93-cc5e-4495-9e63-72ef24c51d5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049279930 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.4049279930
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.2700201999
Short name T729
Test name
Test status
Simulation time 8212896733 ps
CPU time 12.28 seconds
Started Jan 03 12:54:01 PM PST 24
Finished Jan 03 12:55:51 PM PST 24
Peak memory 245544 kb
Host smart-ba5c55d2-2c1a-4625-b313-f1234fe7f004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700201999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.2700201999
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.1025638403
Short name T732
Test name
Test status
Simulation time 82083721 ps
CPU time 1.5 seconds
Started Jan 03 12:53:34 PM PST 24
Finished Jan 03 12:54:31 PM PST 24
Peak memory 239264 kb
Host smart-e11e7a2e-1e59-4d01-9855-657732d477ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025638403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.1025638403
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.3291772137
Short name T30
Test name
Test status
Simulation time 2302100077 ps
CPU time 21.23 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:17 PM PST 24
Peak memory 246816 kb
Host smart-50a7adae-808b-46c4-837d-af2c54f43147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291772137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.3291772137
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.3698225606
Short name T833
Test name
Test status
Simulation time 184913583 ps
CPU time 5.03 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:54:50 PM PST 24
Peak memory 242288 kb
Host smart-2b6ad4f7-cfaf-425c-b69c-1cd6eb029668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698225606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.3698225606
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.1468727645
Short name T905
Test name
Test status
Simulation time 463482540 ps
CPU time 5.46 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:54:47 PM PST 24
Peak memory 241868 kb
Host smart-1af53396-c0b0-4f54-b505-9bccd25369d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468727645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.1468727645
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.2308214118
Short name T1066
Test name
Test status
Simulation time 364386930 ps
CPU time 5.53 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:54:51 PM PST 24
Peak memory 238500 kb
Host smart-a7b0fc6b-fd1b-47fb-aa9a-501c7c69a5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308214118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.2308214118
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.1260540534
Short name T126
Test name
Test status
Simulation time 1933628992 ps
CPU time 19.92 seconds
Started Jan 03 12:53:00 PM PST 24
Finished Jan 03 12:54:28 PM PST 24
Peak memory 238584 kb
Host smart-66982042-fefc-4bcc-bfd7-6198c91f3d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260540534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.1260540534
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.3595119344
Short name T985
Test name
Test status
Simulation time 694485762 ps
CPU time 11.76 seconds
Started Jan 03 12:53:32 PM PST 24
Finished Jan 03 12:54:38 PM PST 24
Peak memory 243736 kb
Host smart-b9d8d4a8-bc09-4525-a89c-4c36ef676ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595119344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3595119344
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.3321633802
Short name T291
Test name
Test status
Simulation time 402920460 ps
CPU time 8.65 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:55:36 PM PST 24
Peak memory 238300 kb
Host smart-ce303794-b569-4314-82b7-19d0028f5df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321633802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.3321633802
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.1969996049
Short name T161
Test name
Test status
Simulation time 651516326 ps
CPU time 8.45 seconds
Started Jan 03 12:53:10 PM PST 24
Finished Jan 03 12:54:28 PM PST 24
Peak memory 238456 kb
Host smart-91a9b1f5-cb05-4879-9da4-23612e2f50f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1969996049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.1969996049
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.4112953195
Short name T626
Test name
Test status
Simulation time 328801900 ps
CPU time 6.41 seconds
Started Jan 03 12:53:08 PM PST 24
Finished Jan 03 12:54:05 PM PST 24
Peak memory 238512 kb
Host smart-175f6a5c-a509-4417-bcb8-8a209a229f2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4112953195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.4112953195
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.804129002
Short name T19
Test name
Test status
Simulation time 8873454623 ps
CPU time 150.18 seconds
Started Jan 03 12:54:07 PM PST 24
Finished Jan 03 12:58:15 PM PST 24
Peak memory 260240 kb
Host smart-0e0fb16b-0887-42c5-a810-f7ab73da9687
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804129002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.804129002
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.3195046205
Short name T411
Test name
Test status
Simulation time 1873090740 ps
CPU time 3.99 seconds
Started Jan 03 12:53:24 PM PST 24
Finished Jan 03 12:54:13 PM PST 24
Peak memory 241564 kb
Host smart-d21beb42-f0bd-4590-a51d-20a82693cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195046205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.3195046205
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.2178362050
Short name T323
Test name
Test status
Simulation time 13706249828 ps
CPU time 48.2 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:55:30 PM PST 24
Peak memory 239280 kb
Host smart-6c264ffb-d778-45b2-a41f-f84ca42dbd95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178362050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
2178362050
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.843434950
Short name T295
Test name
Test status
Simulation time 530137963570 ps
CPU time 6464.36 seconds
Started Jan 03 12:53:54 PM PST 24
Finished Jan 03 02:43:05 PM PST 24
Peak memory 286208 kb
Host smart-4e4ba3b7-ea68-47a7-8dd0-427fb63933ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843434950 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.843434950
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.1219087281
Short name T900
Test name
Test status
Simulation time 327699722 ps
CPU time 6.7 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:55:05 PM PST 24
Peak memory 237480 kb
Host smart-25487b67-5f5b-4a37-b4be-104c916908b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219087281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.1219087281
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.1786325693
Short name T435
Test name
Test status
Simulation time 127421154 ps
CPU time 2.1 seconds
Started Jan 03 12:54:14 PM PST 24
Finished Jan 03 12:56:05 PM PST 24
Peak memory 238424 kb
Host smart-94a3b4e9-bbbe-4676-a58c-c6b4d6f6caf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786325693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.1786325693
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.1675513333
Short name T1110
Test name
Test status
Simulation time 3401116130 ps
CPU time 18.82 seconds
Started Jan 03 12:54:03 PM PST 24
Finished Jan 03 12:56:00 PM PST 24
Peak memory 238692 kb
Host smart-44563049-a16b-46c9-9339-eede5d03bfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675513333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1675513333
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.3945814478
Short name T992
Test name
Test status
Simulation time 601150467 ps
CPU time 7.79 seconds
Started Jan 03 12:54:16 PM PST 24
Finished Jan 03 12:56:02 PM PST 24
Peak memory 238532 kb
Host smart-c0078fb4-ba41-4b0b-9da8-fe40dc5730c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945814478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.3945814478
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.1913229415
Short name T141
Test name
Test status
Simulation time 536175867 ps
CPU time 4.07 seconds
Started Jan 03 12:54:14 PM PST 24
Finished Jan 03 12:55:52 PM PST 24
Peak memory 238444 kb
Host smart-960b4242-e1dd-4602-a6cf-7d77a084828a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913229415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.1913229415
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.3244231594
Short name T521
Test name
Test status
Simulation time 2701942567 ps
CPU time 21.88 seconds
Started Jan 03 12:54:12 PM PST 24
Finished Jan 03 12:56:12 PM PST 24
Peak memory 239172 kb
Host smart-cd9cf585-026e-48bf-a43a-cb3e229b7c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244231594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.3244231594
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.864072427
Short name T967
Test name
Test status
Simulation time 372645975 ps
CPU time 5.59 seconds
Started Jan 03 12:54:03 PM PST 24
Finished Jan 03 12:55:47 PM PST 24
Peak memory 242756 kb
Host smart-fc718d4a-18a7-4fc7-84e6-f09b8d7f7437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864072427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.864072427
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.1971589025
Short name T641
Test name
Test status
Simulation time 1434514412 ps
CPU time 13.6 seconds
Started Jan 03 12:54:15 PM PST 24
Finished Jan 03 12:56:16 PM PST 24
Peak memory 238448 kb
Host smart-718e66f3-7f26-43b4-ab06-b6d6ec990b9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971589025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.1971589025
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.3565956498
Short name T485
Test name
Test status
Simulation time 108028838 ps
CPU time 3.08 seconds
Started Jan 03 12:54:05 PM PST 24
Finished Jan 03 12:55:48 PM PST 24
Peak memory 241232 kb
Host smart-e9deda5d-50ef-4291-9d95-43eab9773e99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3565956498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.3565956498
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.132390958
Short name T576
Test name
Test status
Simulation time 29001303622 ps
CPU time 121.42 seconds
Started Jan 03 12:54:24 PM PST 24
Finished Jan 03 12:58:13 PM PST 24
Peak memory 255064 kb
Host smart-9cfb8f9e-d6c6-41fa-ae51-798f161b4b44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132390958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.
132390958
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.3479864325
Short name T216
Test name
Test status
Simulation time 905401405666 ps
CPU time 3707.36 seconds
Started Jan 03 12:54:08 PM PST 24
Finished Jan 03 01:57:35 PM PST 24
Peak memory 274988 kb
Host smart-1b846773-05b6-49e8-b964-c9e1887a0a8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479864325 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.3479864325
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.3632836998
Short name T1036
Test name
Test status
Simulation time 503471526 ps
CPU time 9.67 seconds
Started Jan 03 12:54:25 PM PST 24
Finished Jan 03 12:56:11 PM PST 24
Peak memory 244956 kb
Host smart-79070c6d-6bc8-41c9-b422-e4e944cd8aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632836998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.3632836998
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.1745524611
Short name T371
Test name
Test status
Simulation time 244740449 ps
CPU time 2.16 seconds
Started Jan 03 12:54:28 PM PST 24
Finished Jan 03 12:56:07 PM PST 24
Peak memory 238156 kb
Host smart-d4464bed-9d5f-4c07-b8af-316b3c730f54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745524611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.1745524611
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.3136943116
Short name T982
Test name
Test status
Simulation time 700999258 ps
CPU time 7.3 seconds
Started Jan 03 12:54:02 PM PST 24
Finished Jan 03 12:55:49 PM PST 24
Peak memory 243088 kb
Host smart-db59412b-1052-4850-a1ed-f57a909a960e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136943116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.3136943116
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.4004017076
Short name T798
Test name
Test status
Simulation time 483990868 ps
CPU time 3.59 seconds
Started Jan 03 12:54:09 PM PST 24
Finished Jan 03 12:55:51 PM PST 24
Peak memory 240852 kb
Host smart-63bd5ba2-819d-4cd0-a535-28882f6abe5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004017076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.4004017076
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.261179168
Short name T723
Test name
Test status
Simulation time 583584431 ps
CPU time 10.63 seconds
Started Jan 03 12:54:11 PM PST 24
Finished Jan 03 12:55:57 PM PST 24
Peak memory 238492 kb
Host smart-a5087328-48aa-493a-9aa8-9cef09082c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261179168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.261179168
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.59772723
Short name T859
Test name
Test status
Simulation time 106459869 ps
CPU time 4.37 seconds
Started Jan 03 12:54:06 PM PST 24
Finished Jan 03 12:55:49 PM PST 24
Peak memory 244592 kb
Host smart-1bbc1167-1970-4573-a1b4-b4ad6b3a1af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59772723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.59772723
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.4205909844
Short name T854
Test name
Test status
Simulation time 611292830 ps
CPU time 13.95 seconds
Started Jan 03 12:54:26 PM PST 24
Finished Jan 03 12:56:24 PM PST 24
Peak memory 238300 kb
Host smart-3a195e9b-e651-4bd0-a185-05da87d62198
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4205909844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.4205909844
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.1525612751
Short name T736
Test name
Test status
Simulation time 512719730 ps
CPU time 5.62 seconds
Started Jan 03 12:54:08 PM PST 24
Finished Jan 03 12:55:53 PM PST 24
Peak memory 246696 kb
Host smart-e83c2536-aad7-4ccc-b5df-8fded5682e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525612751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.1525612751
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.1991393976
Short name T951
Test name
Test status
Simulation time 7091026804 ps
CPU time 15.38 seconds
Started Jan 03 12:54:08 PM PST 24
Finished Jan 03 12:56:03 PM PST 24
Peak memory 230124 kb
Host smart-2a33e599-270b-46aa-9254-6dca066222d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991393976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.1991393976
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.3809063287
Short name T743
Test name
Test status
Simulation time 946558128 ps
CPU time 9.71 seconds
Started Jan 03 12:54:14 PM PST 24
Finished Jan 03 12:55:58 PM PST 24
Peak memory 238412 kb
Host smart-10cc3dba-3bed-4b37-a34d-a5af525220e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809063287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.3809063287
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.3960186982
Short name T53
Test name
Test status
Simulation time 3161000432 ps
CPU time 21.08 seconds
Started Jan 03 12:54:31 PM PST 24
Finished Jan 03 12:56:32 PM PST 24
Peak memory 238652 kb
Host smart-6080e9dc-438f-467d-80bb-ea2ec9a6ba78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960186982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.3960186982
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.631583202
Short name T590
Test name
Test status
Simulation time 4698325541 ps
CPU time 7.88 seconds
Started Jan 03 12:54:20 PM PST 24
Finished Jan 03 12:56:02 PM PST 24
Peak memory 245540 kb
Host smart-9da2c1c5-20ef-4199-83e0-c4c3bbcba8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631583202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.631583202
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.1992531583
Short name T149
Test name
Test status
Simulation time 1630586996 ps
CPU time 4.28 seconds
Started Jan 03 12:54:17 PM PST 24
Finished Jan 03 12:55:55 PM PST 24
Peak memory 238356 kb
Host smart-1b371abb-c893-4b95-a2c2-33238af298ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992531583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.1992531583
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.2412270776
Short name T716
Test name
Test status
Simulation time 171110970 ps
CPU time 4.25 seconds
Started Jan 03 12:54:18 PM PST 24
Finished Jan 03 12:56:08 PM PST 24
Peak memory 238536 kb
Host smart-97ca9ec0-e67c-47b2-8442-08c34558cd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412270776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.2412270776
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.2783935162
Short name T139
Test name
Test status
Simulation time 1342604172 ps
CPU time 2.7 seconds
Started Jan 03 12:54:16 PM PST 24
Finished Jan 03 12:55:57 PM PST 24
Peak memory 238440 kb
Host smart-9015abbc-df88-450f-b09d-ea1a4094f8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783935162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.2783935162
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.3903426890
Short name T328
Test name
Test status
Simulation time 11193553573 ps
CPU time 32.17 seconds
Started Jan 03 12:54:16 PM PST 24
Finished Jan 03 12:56:27 PM PST 24
Peak memory 238596 kb
Host smart-0c77d018-3fa3-43c9-9fa1-ce9cdd48e639
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3903426890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.3903426890
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.752730315
Short name T279
Test name
Test status
Simulation time 207155198468 ps
CPU time 998.45 seconds
Started Jan 03 12:54:12 PM PST 24
Finished Jan 03 01:12:29 PM PST 24
Peak memory 246924 kb
Host smart-2043ebb0-d464-4fac-8bb1-d260a6e71b5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752730315 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.752730315
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.457716033
Short name T443
Test name
Test status
Simulation time 863739821 ps
CPU time 11.3 seconds
Started Jan 03 12:54:12 PM PST 24
Finished Jan 03 12:56:02 PM PST 24
Peak memory 242384 kb
Host smart-1faafc97-1002-4504-a59a-76ec3a15c995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457716033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.457716033
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.1786678176
Short name T882
Test name
Test status
Simulation time 931280973 ps
CPU time 2.77 seconds
Started Jan 03 12:54:23 PM PST 24
Finished Jan 03 12:56:10 PM PST 24
Peak memory 238240 kb
Host smart-f961a4b6-dd71-46b3-90ba-a0eaba6c9e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786678176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.1786678176
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.872276336
Short name T557
Test name
Test status
Simulation time 365436722 ps
CPU time 7.11 seconds
Started Jan 03 12:54:14 PM PST 24
Finished Jan 03 12:55:56 PM PST 24
Peak memory 242744 kb
Host smart-66d57ba8-a7ba-432e-a2ef-04e0284003a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872276336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.872276336
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.461081999
Short name T826
Test name
Test status
Simulation time 126571393 ps
CPU time 4.46 seconds
Started Jan 03 12:54:04 PM PST 24
Finished Jan 03 12:55:51 PM PST 24
Peak memory 241076 kb
Host smart-ff2a596a-ab8d-4c53-97cc-798ce07daee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461081999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.461081999
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.2599062217
Short name T792
Test name
Test status
Simulation time 1332640949 ps
CPU time 6.84 seconds
Started Jan 03 12:54:24 PM PST 24
Finished Jan 03 12:56:18 PM PST 24
Peak memory 238512 kb
Host smart-b58be249-3b53-47e9-95e4-5bf0a4f5d5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599062217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.2599062217
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.571321198
Short name T290
Test name
Test status
Simulation time 178200996 ps
CPU time 2.87 seconds
Started Jan 03 12:54:28 PM PST 24
Finished Jan 03 12:56:08 PM PST 24
Peak memory 238284 kb
Host smart-5ff2e602-301b-403b-b846-f9b5110441f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571321198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.571321198
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.2369217361
Short name T866
Test name
Test status
Simulation time 10845715907 ps
CPU time 22.26 seconds
Started Jan 03 12:54:17 PM PST 24
Finished Jan 03 12:56:14 PM PST 24
Peak memory 238480 kb
Host smart-bf9e49ae-699c-4402-b100-daecccb5e25c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369217361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.2369217361
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.2059165104
Short name T689
Test name
Test status
Simulation time 224094802 ps
CPU time 3.61 seconds
Started Jan 03 12:54:17 PM PST 24
Finished Jan 03 12:55:55 PM PST 24
Peak memory 241048 kb
Host smart-a1f9b8b0-4aa7-4033-b3d3-0973a2b7e19c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059165104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.2059165104
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.3677383988
Short name T867
Test name
Test status
Simulation time 209868321169 ps
CPU time 1897.06 seconds
Started Jan 03 12:54:31 PM PST 24
Finished Jan 03 01:27:51 PM PST 24
Peak memory 411772 kb
Host smart-b22118ab-352b-409c-8744-e0ddeaf5edf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677383988 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.3677383988
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.733801746
Short name T694
Test name
Test status
Simulation time 1086681828 ps
CPU time 18.5 seconds
Started Jan 03 12:54:22 PM PST 24
Finished Jan 03 12:56:28 PM PST 24
Peak memory 238600 kb
Host smart-da3ca660-5540-4587-b3fb-5c5948b723c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733801746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.733801746
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.58894730
Short name T385
Test name
Test status
Simulation time 224398580 ps
CPU time 4.01 seconds
Started Jan 03 12:54:25 PM PST 24
Finished Jan 03 12:56:08 PM PST 24
Peak memory 240396 kb
Host smart-e04b6a52-553d-4386-a334-fdba1710edc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58894730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.58894730
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.2648900423
Short name T1093
Test name
Test status
Simulation time 1124242052 ps
CPU time 21.06 seconds
Started Jan 03 12:54:22 PM PST 24
Finished Jan 03 12:56:19 PM PST 24
Peak memory 243324 kb
Host smart-faaf59df-2fa5-4a96-90ee-26a6280b9834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648900423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.2648900423
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.3706642760
Short name T635
Test name
Test status
Simulation time 1460180283 ps
CPU time 11.25 seconds
Started Jan 03 12:54:28 PM PST 24
Finished Jan 03 12:56:27 PM PST 24
Peak memory 238368 kb
Host smart-84bba9f9-24e6-430b-9313-df86db84fb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706642760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.3706642760
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.1761423293
Short name T814
Test name
Test status
Simulation time 851159907 ps
CPU time 12.11 seconds
Started Jan 03 12:54:31 PM PST 24
Finished Jan 03 12:56:23 PM PST 24
Peak memory 238380 kb
Host smart-9e8544a0-91bb-4b0b-ac51-7205f1aa0b51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1761423293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.1761423293
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.619001618
Short name T554
Test name
Test status
Simulation time 315932396 ps
CPU time 3.75 seconds
Started Jan 03 12:54:28 PM PST 24
Finished Jan 03 12:56:19 PM PST 24
Peak memory 238400 kb
Host smart-6761dade-5e43-41d0-9191-50dde882bff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619001618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.619001618
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.2402005231
Short name T285
Test name
Test status
Simulation time 16521115266 ps
CPU time 30.55 seconds
Started Jan 03 12:54:24 PM PST 24
Finished Jan 03 12:56:33 PM PST 24
Peak memory 246916 kb
Host smart-6c783239-60d4-4d7d-8318-74d8ae9e5b8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402005231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.2402005231
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.4275324853
Short name T1000
Test name
Test status
Simulation time 954818030316 ps
CPU time 4358.95 seconds
Started Jan 03 12:54:24 PM PST 24
Finished Jan 03 02:08:48 PM PST 24
Peak memory 952424 kb
Host smart-f1a9a31d-863b-44dc-abf5-1010087a5d99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275324853 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.4275324853
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.1744171866
Short name T405
Test name
Test status
Simulation time 1158577340 ps
CPU time 9.12 seconds
Started Jan 03 12:54:32 PM PST 24
Finished Jan 03 12:56:20 PM PST 24
Peak memory 238424 kb
Host smart-d87fae28-b53a-4f62-a1f1-121d0e209a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744171866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.1744171866
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.1200689955
Short name T636
Test name
Test status
Simulation time 50555432 ps
CPU time 1.54 seconds
Started Jan 03 12:54:26 PM PST 24
Finished Jan 03 12:56:07 PM PST 24
Peak memory 238364 kb
Host smart-7c539ccd-7101-4b8c-8595-3191872f8226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200689955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.1200689955
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.686537979
Short name T718
Test name
Test status
Simulation time 308750838 ps
CPU time 6.35 seconds
Started Jan 03 12:54:18 PM PST 24
Finished Jan 03 12:56:10 PM PST 24
Peak memory 238412 kb
Host smart-14226ccd-b38c-4f66-aa8d-d4251be9be33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686537979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.686537979
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.2177224028
Short name T686
Test name
Test status
Simulation time 957142147 ps
CPU time 13.81 seconds
Started Jan 03 12:54:17 PM PST 24
Finished Jan 03 12:56:05 PM PST 24
Peak memory 237464 kb
Host smart-fbaee51e-5df4-4407-a07e-ec2f16269e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177224028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.2177224028
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.1714586557
Short name T1099
Test name
Test status
Simulation time 509407120 ps
CPU time 4.09 seconds
Started Jan 03 12:54:24 PM PST 24
Finished Jan 03 12:56:15 PM PST 24
Peak memory 238624 kb
Host smart-335d6f31-c5b5-48ff-a15f-15267e38e5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714586557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.1714586557
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.2485941975
Short name T1073
Test name
Test status
Simulation time 9597177318 ps
CPU time 21.37 seconds
Started Jan 03 12:54:32 PM PST 24
Finished Jan 03 12:56:28 PM PST 24
Peak memory 243568 kb
Host smart-45f0d8f2-f3f0-434e-8af2-3e56663a8cab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2485941975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.2485941975
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.1965523537
Short name T858
Test name
Test status
Simulation time 234953739 ps
CPU time 4.71 seconds
Started Jan 03 12:54:25 PM PST 24
Finished Jan 03 12:56:17 PM PST 24
Peak memory 238392 kb
Host smart-1425b01b-dee7-43b9-81e8-b8f5d83afa31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965523537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.1965523537
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.3355561529
Short name T868
Test name
Test status
Simulation time 30647050176 ps
CPU time 130.89 seconds
Started Jan 03 12:54:25 PM PST 24
Finished Jan 03 12:58:12 PM PST 24
Peak memory 246828 kb
Host smart-4d3d15e3-79b8-4165-ba80-bd81b5d77f7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355561529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.3355561529
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.1428753038
Short name T1047
Test name
Test status
Simulation time 208083211969 ps
CPU time 2796.15 seconds
Started Jan 03 12:54:32 PM PST 24
Finished Jan 03 01:42:53 PM PST 24
Peak memory 286720 kb
Host smart-1369361e-a610-497d-adfc-700f300c32ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428753038 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.1428753038
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.1760690250
Short name T789
Test name
Test status
Simulation time 191712239 ps
CPU time 4.59 seconds
Started Jan 03 12:54:17 PM PST 24
Finished Jan 03 12:55:56 PM PST 24
Peak memory 246664 kb
Host smart-441125b2-72a7-4406-8bbf-148a41b67695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760690250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.1760690250
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.2679999474
Short name T25
Test name
Test status
Simulation time 2354236780 ps
CPU time 21.13 seconds
Started Jan 03 12:54:40 PM PST 24
Finished Jan 03 12:56:38 PM PST 24
Peak memory 238676 kb
Host smart-fa62982e-8bfc-4d65-a4da-02b4f4ca4708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679999474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.2679999474
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.3105673643
Short name T824
Test name
Test status
Simulation time 132132447 ps
CPU time 5.03 seconds
Started Jan 03 12:54:25 PM PST 24
Finished Jan 03 12:56:07 PM PST 24
Peak memory 238284 kb
Host smart-366153ab-67c7-4989-ae25-b435b772b47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105673643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.3105673643
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.2599778296
Short name T10
Test name
Test status
Simulation time 597194537 ps
CPU time 12.32 seconds
Started Jan 03 12:54:25 PM PST 24
Finished Jan 03 12:56:25 PM PST 24
Peak memory 246680 kb
Host smart-71ca2ec8-a204-4ddd-b0b7-23e46401d094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599778296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.2599778296
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.3922552376
Short name T376
Test name
Test status
Simulation time 1824671599 ps
CPU time 14.18 seconds
Started Jan 03 12:54:35 PM PST 24
Finished Jan 03 12:56:28 PM PST 24
Peak memory 241304 kb
Host smart-87e4eeb6-5524-40ed-b49a-e392c292ad70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922552376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.3922552376
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.2894737209
Short name T1016
Test name
Test status
Simulation time 259052243 ps
CPU time 2.91 seconds
Started Jan 03 12:54:30 PM PST 24
Finished Jan 03 12:56:21 PM PST 24
Peak memory 241076 kb
Host smart-ef9ae8a7-f1a1-4464-bde3-a5bd42c22ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894737209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.2894737209
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.3216790991
Short name T563
Test name
Test status
Simulation time 604390558 ps
CPU time 4.17 seconds
Started Jan 03 12:54:36 PM PST 24
Finished Jan 03 12:56:21 PM PST 24
Peak memory 238316 kb
Host smart-3ae08b50-8e8a-4aea-aeaf-e44f629ea170
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216790991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.3216790991
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.2595539236
Short name T200
Test name
Test status
Simulation time 420412332 ps
CPU time 3.95 seconds
Started Jan 03 12:54:39 PM PST 24
Finished Jan 03 12:56:21 PM PST 24
Peak memory 238432 kb
Host smart-15e14a80-15f2-45b8-963e-65b600beecc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2595539236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.2595539236
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.966212767
Short name T543
Test name
Test status
Simulation time 285640982 ps
CPU time 5.58 seconds
Started Jan 03 12:54:28 PM PST 24
Finished Jan 03 12:56:10 PM PST 24
Peak memory 242452 kb
Host smart-ed911a95-e69c-4b68-80a5-360586dc5530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966212767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.966212767
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.2494587317
Short name T271
Test name
Test status
Simulation time 1995042128364 ps
CPU time 5138.14 seconds
Started Jan 03 12:54:24 PM PST 24
Finished Jan 03 02:21:47 PM PST 24
Peak memory 373344 kb
Host smart-a83b5c7d-1e9a-4ebd-8ec1-e3e635e99257
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494587317 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.2494587317
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.833516255
Short name T650
Test name
Test status
Simulation time 172567238 ps
CPU time 3.3 seconds
Started Jan 03 12:54:33 PM PST 24
Finished Jan 03 12:56:21 PM PST 24
Peak memory 242472 kb
Host smart-05e9ea3e-100b-4753-8372-4feda56f967e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833516255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.833516255
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.3239672902
Short name T445
Test name
Test status
Simulation time 64647678 ps
CPU time 1.94 seconds
Started Jan 03 12:54:32 PM PST 24
Finished Jan 03 12:56:13 PM PST 24
Peak memory 239344 kb
Host smart-9be08c3a-6249-4d55-a736-8a544a3ffe25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239672902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.3239672902
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.3976074386
Short name T531
Test name
Test status
Simulation time 374765176 ps
CPU time 4.44 seconds
Started Jan 03 12:54:34 PM PST 24
Finished Jan 03 12:56:26 PM PST 24
Peak memory 238476 kb
Host smart-05cb6f81-ab85-4930-a103-d2d46d7255c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976074386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.3976074386
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.4238176432
Short name T899
Test name
Test status
Simulation time 511804962 ps
CPU time 6.73 seconds
Started Jan 03 12:54:38 PM PST 24
Finished Jan 03 12:56:20 PM PST 24
Peak memory 238428 kb
Host smart-6e8cfd39-1b14-4b71-a3e6-ae3e4bab538f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238176432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.4238176432
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.3579031416
Short name T477
Test name
Test status
Simulation time 10298427046 ps
CPU time 22.8 seconds
Started Jan 03 12:54:28 PM PST 24
Finished Jan 03 12:56:27 PM PST 24
Peak memory 238516 kb
Host smart-67a80e81-4116-4379-9bec-3bf7f3dde5c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3579031416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.3579031416
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.800313214
Short name T1071
Test name
Test status
Simulation time 706663586 ps
CPU time 5.15 seconds
Started Jan 03 12:54:28 PM PST 24
Finished Jan 03 12:56:10 PM PST 24
Peak memory 237568 kb
Host smart-948940c3-ab47-4e0e-8de5-ffb012cd71bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800313214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.800313214
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.2385964197
Short name T573
Test name
Test status
Simulation time 97151629 ps
CPU time 1.62 seconds
Started Jan 03 12:54:44 PM PST 24
Finished Jan 03 12:56:22 PM PST 24
Peak memory 239336 kb
Host smart-1a881ba7-92c4-47b5-b478-8aee5d2e85f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385964197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.2385964197
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.884732199
Short name T795
Test name
Test status
Simulation time 632600662 ps
CPU time 13.24 seconds
Started Jan 03 12:54:24 PM PST 24
Finished Jan 03 12:56:21 PM PST 24
Peak memory 246620 kb
Host smart-953684fd-b8fc-4139-be36-aa66c2b5c8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884732199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.884732199
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.1396130803
Short name T259
Test name
Test status
Simulation time 476658410 ps
CPU time 5.83 seconds
Started Jan 03 12:54:33 PM PST 24
Finished Jan 03 12:56:23 PM PST 24
Peak memory 238508 kb
Host smart-a11ab587-4c91-4e54-bfda-c03a2e9875d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396130803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.1396130803
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.999287818
Short name T136
Test name
Test status
Simulation time 235700449 ps
CPU time 4.32 seconds
Started Jan 03 12:54:23 PM PST 24
Finished Jan 03 12:56:02 PM PST 24
Peak memory 241248 kb
Host smart-15a55bdd-667e-4011-9c3c-f2e84fc0701f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999287818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.999287818
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.2957233449
Short name T451
Test name
Test status
Simulation time 155470241 ps
CPU time 4.47 seconds
Started Jan 03 12:54:22 PM PST 24
Finished Jan 03 12:56:05 PM PST 24
Peak memory 245968 kb
Host smart-521baffe-13e4-4726-bfd0-1906f27531dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957233449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.2957233449
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.3047289080
Short name T341
Test name
Test status
Simulation time 500496018 ps
CPU time 7.15 seconds
Started Jan 03 12:54:35 PM PST 24
Finished Jan 03 12:56:18 PM PST 24
Peak memory 243636 kb
Host smart-92d804bb-306e-4002-bbcf-0d58ca6ff22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047289080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.3047289080
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.3299954860
Short name T204
Test name
Test status
Simulation time 157203118 ps
CPU time 4.25 seconds
Started Jan 03 12:54:25 PM PST 24
Finished Jan 03 12:56:06 PM PST 24
Peak memory 241456 kb
Host smart-e190b163-b4e9-445a-be82-a55f0e8214d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299954860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.3299954860
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.1278362112
Short name T1013
Test name
Test status
Simulation time 10636992341 ps
CPU time 28.57 seconds
Started Jan 03 12:54:23 PM PST 24
Finished Jan 03 12:56:27 PM PST 24
Peak memory 243936 kb
Host smart-f4338a51-f912-4d31-a179-9e917ad151b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1278362112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.1278362112
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.1087851874
Short name T312
Test name
Test status
Simulation time 346302406 ps
CPU time 3.86 seconds
Started Jan 03 12:54:22 PM PST 24
Finished Jan 03 12:56:07 PM PST 24
Peak memory 238472 kb
Host smart-987e50ac-cf08-42f1-bbf7-49ac7b0567c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1087851874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.1087851874
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.825722476
Short name T188
Test name
Test status
Simulation time 34199462421 ps
CPU time 95.85 seconds
Started Jan 03 12:54:30 PM PST 24
Finished Jan 03 12:57:45 PM PST 24
Peak memory 242468 kb
Host smart-78e354fc-5c71-4076-8e42-b2e74a895f7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825722476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.
825722476
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.293089664
Short name T1042
Test name
Test status
Simulation time 728922235866 ps
CPU time 5508.67 seconds
Started Jan 03 12:54:33 PM PST 24
Finished Jan 03 02:28:07 PM PST 24
Peak memory 1032776 kb
Host smart-c0acce97-b516-40e2-b66a-eb713eacbcb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293089664 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.293089664
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.2503218488
Short name T362
Test name
Test status
Simulation time 123704459 ps
CPU time 2.05 seconds
Started Jan 03 12:54:37 PM PST 24
Finished Jan 03 12:56:18 PM PST 24
Peak memory 238480 kb
Host smart-d5103f76-87f5-4c01-910d-361d0c43a136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503218488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.2503218488
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.2618960983
Short name T34
Test name
Test status
Simulation time 363412508 ps
CPU time 10.42 seconds
Started Jan 03 12:54:28 PM PST 24
Finished Jan 03 12:56:26 PM PST 24
Peak memory 238468 kb
Host smart-694ed3ea-890b-4ec2-932a-3e12799cd698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618960983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.2618960983
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.622837963
Short name T381
Test name
Test status
Simulation time 376364685 ps
CPU time 4.29 seconds
Started Jan 03 12:54:26 PM PST 24
Finished Jan 03 12:56:10 PM PST 24
Peak memory 237480 kb
Host smart-6afa5c5d-7faf-450d-9335-ab25d43ae69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622837963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.622837963
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.2328822657
Short name T918
Test name
Test status
Simulation time 232119533 ps
CPU time 4.37 seconds
Started Jan 03 12:54:21 PM PST 24
Finished Jan 03 12:56:04 PM PST 24
Peak memory 240872 kb
Host smart-06d9e1f6-a460-4758-8cc7-6c6331b054c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328822657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.2328822657
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.1691493491
Short name T981
Test name
Test status
Simulation time 1597084506 ps
CPU time 14.05 seconds
Started Jan 03 12:54:28 PM PST 24
Finished Jan 03 12:56:19 PM PST 24
Peak memory 238428 kb
Host smart-c0ef86fb-c59f-4890-ad85-3ede717f46c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691493491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.1691493491
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.4144813167
Short name T533
Test name
Test status
Simulation time 3134760340 ps
CPU time 9.8 seconds
Started Jan 03 12:54:31 PM PST 24
Finished Jan 03 12:56:21 PM PST 24
Peak memory 246680 kb
Host smart-45f44f89-c606-4d6a-8c3d-ffc2b627f04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144813167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.4144813167
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.1795410471
Short name T530
Test name
Test status
Simulation time 439078557 ps
CPU time 3.74 seconds
Started Jan 03 12:54:28 PM PST 24
Finished Jan 03 12:56:08 PM PST 24
Peak memory 243676 kb
Host smart-8c1e8c2a-a519-4559-ae57-e316322c962d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1795410471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.1795410471
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.1462705623
Short name T410
Test name
Test status
Simulation time 197053319 ps
CPU time 5.3 seconds
Started Jan 03 12:54:40 PM PST 24
Finished Jan 03 12:56:22 PM PST 24
Peak memory 238596 kb
Host smart-391c5d14-65a0-491f-8663-8facf6b54242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462705623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.1462705623
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.3151565319
Short name T755
Test name
Test status
Simulation time 1097817664 ps
CPU time 16.89 seconds
Started Jan 03 12:54:38 PM PST 24
Finished Jan 03 12:56:40 PM PST 24
Peak memory 238512 kb
Host smart-cb656053-8837-47a3-936b-58350bb1b2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151565319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.3151565319
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.2263733544
Short name T363
Test name
Test status
Simulation time 166453099 ps
CPU time 1.82 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:54:44 PM PST 24
Peak memory 238524 kb
Host smart-c2c8b575-271a-48be-bd18-2c3c86ebe01d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263733544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.2263733544
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.2119584473
Short name T572
Test name
Test status
Simulation time 1111104762 ps
CPU time 6.65 seconds
Started Jan 03 12:53:33 PM PST 24
Finished Jan 03 12:54:32 PM PST 24
Peak memory 238560 kb
Host smart-761fdb56-d0f9-46d0-bbe4-386594d12df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119584473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.2119584473
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.434749619
Short name T1114
Test name
Test status
Simulation time 1379448949 ps
CPU time 10.05 seconds
Started Jan 03 12:53:13 PM PST 24
Finished Jan 03 12:54:11 PM PST 24
Peak memory 238432 kb
Host smart-8d8e633f-c3ef-4e40-8013-a079d04de7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434749619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.434749619
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.3282172177
Short name T1029
Test name
Test status
Simulation time 278715194 ps
CPU time 6.05 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:54:48 PM PST 24
Peak memory 243060 kb
Host smart-4a4aa657-927c-4afd-8b9e-3805a3334ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282172177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.3282172177
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.43181141
Short name T527
Test name
Test status
Simulation time 1320147820 ps
CPU time 15.16 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:54:47 PM PST 24
Peak memory 242956 kb
Host smart-31edfc41-9397-4465-b07f-95947236583b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43181141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.43181141
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.3155247739
Short name T74
Test name
Test status
Simulation time 744026870 ps
CPU time 5.02 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:54:47 PM PST 24
Peak memory 243312 kb
Host smart-4ee8078e-c195-45ee-940c-caae4b77cd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155247739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.3155247739
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.1105268126
Short name T288
Test name
Test status
Simulation time 888656231 ps
CPU time 9.03 seconds
Started Jan 03 12:53:44 PM PST 24
Finished Jan 03 12:54:56 PM PST 24
Peak memory 246636 kb
Host smart-342635b3-a7cd-4168-9614-67e63274104e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105268126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.1105268126
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.125301241
Short name T164
Test name
Test status
Simulation time 2474647199 ps
CPU time 24.05 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:55:42 PM PST 24
Peak memory 246732 kb
Host smart-fdf2c8b6-5c8b-4444-bb5b-e7619a088802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125301241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.125301241
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.1890535402
Short name T600
Test name
Test status
Simulation time 1042888060 ps
CPU time 7.51 seconds
Started Jan 03 12:52:59 PM PST 24
Finished Jan 03 12:54:13 PM PST 24
Peak memory 238424 kb
Host smart-12458f56-f239-42f2-b0bf-d360e5c38ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890535402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.1890535402
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.979443267
Short name T996
Test name
Test status
Simulation time 2730008474 ps
CPU time 5.88 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:54:46 PM PST 24
Peak memory 241576 kb
Host smart-b61636d4-96f3-4174-82c3-5a54053a93fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=979443267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.979443267
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.1446230399
Short name T534
Test name
Test status
Simulation time 466122100 ps
CPU time 7.79 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:54:42 PM PST 24
Peak memory 238452 kb
Host smart-e1e69f69-cea6-4004-9b7d-190b0676edb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446230399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.1446230399
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.2747632862
Short name T455
Test name
Test status
Simulation time 1420917676 ps
CPU time 4.26 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:54:50 PM PST 24
Peak memory 238344 kb
Host smart-8e5422bd-0fe3-464a-aa6b-0f531dbcee44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747632862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.2747632862
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.1956719343
Short name T940
Test name
Test status
Simulation time 55453854610 ps
CPU time 109.89 seconds
Started Jan 03 12:54:05 PM PST 24
Finished Jan 03 12:57:35 PM PST 24
Peak memory 242300 kb
Host smart-32281183-d2be-4bcd-83e5-d9954e7a0b24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956719343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
1956719343
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.1842735558
Short name T261
Test name
Test status
Simulation time 927085331779 ps
CPU time 6699.53 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 02:46:29 PM PST 24
Peak memory 911376 kb
Host smart-efba67d7-f951-4941-b53d-6c992dac3e41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842735558 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.1842735558
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.591030719
Short name T1094
Test name
Test status
Simulation time 12121562538 ps
CPU time 32.08 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:55:14 PM PST 24
Peak memory 239652 kb
Host smart-ca5f52fe-4634-4d86-b8c5-53f598fb1a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591030719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.591030719
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.583571593
Short name T767
Test name
Test status
Simulation time 194270535 ps
CPU time 2.91 seconds
Started Jan 03 12:54:21 PM PST 24
Finished Jan 03 12:56:08 PM PST 24
Peak memory 238360 kb
Host smart-b2c0e18a-9f2f-477a-8cca-d9e5de4156e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583571593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.583571593
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.3418792136
Short name T562
Test name
Test status
Simulation time 265930888969 ps
CPU time 4115.93 seconds
Started Jan 03 12:54:25 PM PST 24
Finished Jan 03 02:04:38 PM PST 24
Peak memory 884640 kb
Host smart-ba768a7c-9b59-4c2f-a366-dc3389130dc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418792136 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.3418792136
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.4249979170
Short name T475
Test name
Test status
Simulation time 140240135 ps
CPU time 3.79 seconds
Started Jan 03 12:54:43 PM PST 24
Finished Jan 03 12:56:37 PM PST 24
Peak memory 238396 kb
Host smart-cd4ca619-7e73-413a-b49a-d01cabe04376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249979170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.4249979170
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.3673460510
Short name T408
Test name
Test status
Simulation time 236517201 ps
CPU time 4.15 seconds
Started Jan 03 12:54:36 PM PST 24
Finished Jan 03 12:56:18 PM PST 24
Peak memory 241260 kb
Host smart-5bdc78e3-09a3-46cc-ba7e-3389ea651de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673460510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.3673460510
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.1944370437
Short name T332
Test name
Test status
Simulation time 200903038036 ps
CPU time 595.01 seconds
Started Jan 03 12:54:41 PM PST 24
Finished Jan 03 01:06:13 PM PST 24
Peak memory 263308 kb
Host smart-64ee8a57-b3e6-4eca-bc5f-299e87ccdee1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944370437 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.1944370437
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.4160500850
Short name T862
Test name
Test status
Simulation time 323471400 ps
CPU time 3.22 seconds
Started Jan 03 12:54:39 PM PST 24
Finished Jan 03 12:56:16 PM PST 24
Peak memory 238344 kb
Host smart-80cd3b74-b8ab-43fc-8a9f-7c0ab4198452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160500850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.4160500850
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.3793830242
Short name T250
Test name
Test status
Simulation time 3359231262953 ps
CPU time 6955.8 seconds
Started Jan 03 12:54:59 PM PST 24
Finished Jan 03 02:52:34 PM PST 24
Peak memory 274364 kb
Host smart-74e0924b-1ccd-460a-a9ac-06d8d64612ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793830242 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.3793830242
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.3807942867
Short name T377
Test name
Test status
Simulation time 120666977 ps
CPU time 3.99 seconds
Started Jan 03 12:54:36 PM PST 24
Finished Jan 03 12:56:18 PM PST 24
Peak memory 238332 kb
Host smart-d29fa795-521b-4d39-b249-826a52ffb01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807942867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.3807942867
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.2650788688
Short name T890
Test name
Test status
Simulation time 461691644092 ps
CPU time 1842.95 seconds
Started Jan 03 12:54:42 PM PST 24
Finished Jan 03 01:26:59 PM PST 24
Peak memory 312040 kb
Host smart-856ee611-7643-4277-9097-aa0bd288dce5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650788688 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.2650788688
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.3113869066
Short name T135
Test name
Test status
Simulation time 333412955 ps
CPU time 4.18 seconds
Started Jan 03 12:54:44 PM PST 24
Finished Jan 03 12:56:25 PM PST 24
Peak memory 240648 kb
Host smart-65f13c2b-1719-4e8e-b3be-c818a223fb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113869066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.3113869066
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.1231405839
Short name T699
Test name
Test status
Simulation time 885639181 ps
CPU time 6.08 seconds
Started Jan 03 12:54:32 PM PST 24
Finished Jan 03 12:56:14 PM PST 24
Peak memory 242424 kb
Host smart-bd6fed05-22ba-4c35-bb10-6ea354d896f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231405839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.1231405839
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.18352065
Short name T885
Test name
Test status
Simulation time 2178856708804 ps
CPU time 7566.4 seconds
Started Jan 03 12:54:52 PM PST 24
Finished Jan 03 03:02:34 PM PST 24
Peak memory 1746748 kb
Host smart-69e31b1d-3afa-40f7-affc-09b94eda4150
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18352065 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.18352065
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.2287767083
Short name T933
Test name
Test status
Simulation time 155666999 ps
CPU time 3.7 seconds
Started Jan 03 12:54:35 PM PST 24
Finished Jan 03 12:56:17 PM PST 24
Peak memory 241068 kb
Host smart-cef57f34-45ae-4547-893f-e58c03cd3e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287767083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.2287767083
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.2804172575
Short name T235
Test name
Test status
Simulation time 425476025060 ps
CPU time 2181.05 seconds
Started Jan 03 12:54:45 PM PST 24
Finished Jan 03 01:32:42 PM PST 24
Peak memory 365656 kb
Host smart-b596ef53-432a-4b85-ab4c-d695321053ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804172575 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.2804172575
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.1908099734
Short name T688
Test name
Test status
Simulation time 365054557 ps
CPU time 4.45 seconds
Started Jan 03 12:54:44 PM PST 24
Finished Jan 03 12:56:25 PM PST 24
Peak memory 241444 kb
Host smart-d022d9ad-4ba6-452f-ae0f-550c1bba7fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908099734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.1908099734
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.3875483119
Short name T263
Test name
Test status
Simulation time 226332436686 ps
CPU time 3171.67 seconds
Started Jan 03 12:54:40 PM PST 24
Finished Jan 03 01:49:09 PM PST 24
Peak memory 263332 kb
Host smart-06ed5b4d-3c0b-43b5-8247-77cc6c117298
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875483119 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.3875483119
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.1065190308
Short name T802
Test name
Test status
Simulation time 188558795 ps
CPU time 4.86 seconds
Started Jan 03 12:54:34 PM PST 24
Finished Jan 03 12:56:26 PM PST 24
Peak memory 240888 kb
Host smart-76c4e18d-ad09-40d9-abf6-dd9716074187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065190308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.1065190308
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.1936305893
Short name T553
Test name
Test status
Simulation time 1887372783 ps
CPU time 4.83 seconds
Started Jan 03 12:54:40 PM PST 24
Finished Jan 03 12:56:18 PM PST 24
Peak memory 243708 kb
Host smart-51016256-6c40-41ed-81a6-97df45159abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936305893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.1936305893
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.2703370975
Short name T878
Test name
Test status
Simulation time 518825213384 ps
CPU time 4081.33 seconds
Started Jan 03 12:54:37 PM PST 24
Finished Jan 03 02:04:17 PM PST 24
Peak memory 493860 kb
Host smart-9727e834-e2ee-411a-ba4f-b7184e40ca10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703370975 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.2703370975
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.2464058254
Short name T956
Test name
Test status
Simulation time 652247154 ps
CPU time 4.14 seconds
Started Jan 03 12:54:38 PM PST 24
Finished Jan 03 12:56:28 PM PST 24
Peak memory 238384 kb
Host smart-a845a01d-0b24-435d-9d04-3a59a0f5c003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464058254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.2464058254
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.1918361656
Short name T350
Test name
Test status
Simulation time 490782671 ps
CPU time 5.59 seconds
Started Jan 03 12:54:34 PM PST 24
Finished Jan 03 12:56:21 PM PST 24
Peak memory 238384 kb
Host smart-b1f37734-80b7-4906-97a4-41c7a00d1552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918361656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.1918361656
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.3588688256
Short name T234
Test name
Test status
Simulation time 216451967243 ps
CPU time 3051.2 seconds
Started Jan 03 12:54:47 PM PST 24
Finished Jan 03 01:47:15 PM PST 24
Peak memory 297976 kb
Host smart-42f9a6dc-a41d-4c0e-9d37-7208ce1e9dd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588688256 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.3588688256
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.600963055
Short name T952
Test name
Test status
Simulation time 168072069 ps
CPU time 1.53 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:47 PM PST 24
Peak memory 238104 kb
Host smart-e23cf5bd-d9e9-42b0-88b6-d1ec1f444c80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600963055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.600963055
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.417529000
Short name T640
Test name
Test status
Simulation time 206667629 ps
CPU time 3.81 seconds
Started Jan 03 12:53:21 PM PST 24
Finished Jan 03 12:54:28 PM PST 24
Peak memory 243692 kb
Host smart-42838910-fdc8-4738-986c-cd5aaa749950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417529000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.417529000
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.155075832
Short name T912
Test name
Test status
Simulation time 1709274222 ps
CPU time 8.93 seconds
Started Jan 03 12:53:58 PM PST 24
Finished Jan 03 12:55:44 PM PST 24
Peak memory 238628 kb
Host smart-8707ed27-8e31-4f5a-91b3-8f1f008ed065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155075832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.155075832
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.1365410839
Short name T502
Test name
Test status
Simulation time 2127909208 ps
CPU time 6.85 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:54:49 PM PST 24
Peak memory 243392 kb
Host smart-2863f59c-2592-44ce-8875-e30cca907995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365410839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.1365410839
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.2468862881
Short name T193
Test name
Test status
Simulation time 998771589 ps
CPU time 16.84 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:55:02 PM PST 24
Peak memory 243520 kb
Host smart-6fddc8c7-684e-4151-b57f-7a87314b7f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468862881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.2468862881
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.2581486465
Short name T392
Test name
Test status
Simulation time 316717956 ps
CPU time 4.84 seconds
Started Jan 03 12:53:31 PM PST 24
Finished Jan 03 12:54:29 PM PST 24
Peak memory 238384 kb
Host smart-2b6bd1b8-2e03-4ca2-a0fa-5ab0e5a1ad22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581486465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.2581486465
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.1463276045
Short name T910
Test name
Test status
Simulation time 9153334560 ps
CPU time 17.86 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:54:58 PM PST 24
Peak memory 238484 kb
Host smart-8c1d5413-3589-42a2-a7f5-699fde8bde45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463276045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.1463276045
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.1430541748
Short name T923
Test name
Test status
Simulation time 1193004702 ps
CPU time 9.52 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:55:51 PM PST 24
Peak memory 243904 kb
Host smart-7179e78e-0667-4239-9966-ec09002912e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430541748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.1430541748
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.2685089670
Short name T960
Test name
Test status
Simulation time 2580507564 ps
CPU time 20.05 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:55:36 PM PST 24
Peak memory 238416 kb
Host smart-7958fba2-544a-43a3-a898-3a5d868f2390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685089670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.2685089670
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.1934181312
Short name T388
Test name
Test status
Simulation time 216376918 ps
CPU time 3.1 seconds
Started Jan 03 12:53:56 PM PST 24
Finished Jan 03 12:55:28 PM PST 24
Peak memory 237556 kb
Host smart-14e4d1fd-cbdb-4ea8-bb07-3c63b1b2c2a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1934181312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.1934181312
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.2837918274
Short name T471
Test name
Test status
Simulation time 476984032 ps
CPU time 5.24 seconds
Started Jan 03 12:53:28 PM PST 24
Finished Jan 03 12:54:26 PM PST 24
Peak memory 238328 kb
Host smart-05080b61-319f-42a8-a540-4af2cb0ff024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837918274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.2837918274
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.168707256
Short name T639
Test name
Test status
Simulation time 62932728621 ps
CPU time 144.73 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:57:45 PM PST 24
Peak memory 245956 kb
Host smart-7d9290ed-ee98-429f-acf0-2c69317ef33a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168707256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.168707256
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.2429190155
Short name T273
Test name
Test status
Simulation time 599505617674 ps
CPU time 4154.54 seconds
Started Jan 03 12:53:51 PM PST 24
Finished Jan 03 02:04:26 PM PST 24
Peak memory 647512 kb
Host smart-6f6d0f5d-fad8-4824-b0df-f59b2ef04ad9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429190155 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.2429190155
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.1481894369
Short name T150
Test name
Test status
Simulation time 393872377 ps
CPU time 5.79 seconds
Started Jan 03 12:53:42 PM PST 24
Finished Jan 03 12:54:51 PM PST 24
Peak memory 243464 kb
Host smart-38b246de-5ca7-48fe-97f4-50083a1e11e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481894369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.1481894369
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.4220290075
Short name T808
Test name
Test status
Simulation time 128794853 ps
CPU time 3.79 seconds
Started Jan 03 12:54:39 PM PST 24
Finished Jan 03 12:56:29 PM PST 24
Peak memory 241784 kb
Host smart-cc5f84b0-77c8-43e2-a643-ae09bdf651c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220290075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.4220290075
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.163557493
Short name T977
Test name
Test status
Simulation time 2129628501 ps
CPU time 3.66 seconds
Started Jan 03 12:54:43 PM PST 24
Finished Jan 03 12:56:37 PM PST 24
Peak memory 240664 kb
Host smart-55d926d4-3bea-49e0-9a67-c5239f71836a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163557493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.163557493
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.139694737
Short name T911
Test name
Test status
Simulation time 3482140814111 ps
CPU time 4684.84 seconds
Started Jan 03 12:54:43 PM PST 24
Finished Jan 03 02:14:39 PM PST 24
Peak memory 896308 kb
Host smart-ab0ce39f-7456-4e01-b030-1547ef1c50db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139694737 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.139694737
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.1633446638
Short name T669
Test name
Test status
Simulation time 792515324 ps
CPU time 5.17 seconds
Started Jan 03 12:54:41 PM PST 24
Finished Jan 03 12:56:26 PM PST 24
Peak memory 238384 kb
Host smart-e1801040-6015-40d8-b4a4-c38ddec3b099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633446638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.1633446638
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.564054839
Short name T556
Test name
Test status
Simulation time 1560737624 ps
CPU time 5.09 seconds
Started Jan 03 12:54:40 PM PST 24
Finished Jan 03 12:56:24 PM PST 24
Peak memory 238464 kb
Host smart-23e13212-a750-4f94-99e4-b54769ae07df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564054839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.564054839
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.2774485544
Short name T226
Test name
Test status
Simulation time 259077705072 ps
CPU time 4559.34 seconds
Started Jan 03 12:54:37 PM PST 24
Finished Jan 03 02:12:15 PM PST 24
Peak memory 946992 kb
Host smart-7468382a-deb9-426c-bd2c-2cf746b0d80b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774485544 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.2774485544
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.1745841157
Short name T232
Test name
Test status
Simulation time 269270609 ps
CPU time 4.53 seconds
Started Jan 03 12:54:34 PM PST 24
Finished Jan 03 12:56:14 PM PST 24
Peak memory 238392 kb
Host smart-233c722d-8fa8-481b-9602-743022c5ee71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745841157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.1745841157
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.3209714295
Short name T251
Test name
Test status
Simulation time 7130357492842 ps
CPU time 9111.19 seconds
Started Jan 03 12:54:38 PM PST 24
Finished Jan 03 03:28:16 PM PST 24
Peak memory 946692 kb
Host smart-b9c6e45c-0802-4047-acb1-28ac6756ee3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209714295 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.3209714295
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.1248627198
Short name T484
Test name
Test status
Simulation time 115268798 ps
CPU time 4 seconds
Started Jan 03 12:54:42 PM PST 24
Finished Jan 03 12:56:41 PM PST 24
Peak memory 241280 kb
Host smart-ac89d998-07f2-453a-bbc7-9e8f93c1539d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248627198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.1248627198
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.3932545514
Short name T513
Test name
Test status
Simulation time 196447841 ps
CPU time 3.76 seconds
Started Jan 03 12:54:34 PM PST 24
Finished Jan 03 12:56:19 PM PST 24
Peak memory 238336 kb
Host smart-23a1e736-e3b1-4a9f-bbfc-50566690762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932545514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3932545514
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.3435708304
Short name T619
Test name
Test status
Simulation time 2088497886115 ps
CPU time 6768.97 seconds
Started Jan 03 12:54:44 PM PST 24
Finished Jan 03 02:49:11 PM PST 24
Peak memory 762472 kb
Host smart-bda26fac-326d-4887-9d42-6ffdb0b69804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435708304 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.3435708304
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.4094293350
Short name T631
Test name
Test status
Simulation time 2663407192 ps
CPU time 6.4 seconds
Started Jan 03 12:54:47 PM PST 24
Finished Jan 03 12:56:37 PM PST 24
Peak memory 241276 kb
Host smart-44af63a4-bdad-4582-8b79-cd124f769404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094293350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.4094293350
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.2674750981
Short name T1105
Test name
Test status
Simulation time 161377325 ps
CPU time 4.24 seconds
Started Jan 03 12:54:45 PM PST 24
Finished Jan 03 12:56:28 PM PST 24
Peak memory 242484 kb
Host smart-6c06415f-0139-4991-ba23-0da03f83e098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674750981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.2674750981
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.2835685693
Short name T425
Test name
Test status
Simulation time 1942940516187 ps
CPU time 4403.54 seconds
Started Jan 03 12:54:43 PM PST 24
Finished Jan 03 02:09:52 PM PST 24
Peak memory 268288 kb
Host smart-dd6e0a84-1450-4bc0-8f53-5d222054c543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835685693 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.2835685693
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.4189158359
Short name T678
Test name
Test status
Simulation time 165580440 ps
CPU time 3.49 seconds
Started Jan 03 12:54:41 PM PST 24
Finished Jan 03 12:56:30 PM PST 24
Peak memory 240520 kb
Host smart-9b68b47d-7787-469e-ad58-e9ac649933ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189158359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.4189158359
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.2203978465
Short name T596
Test name
Test status
Simulation time 134153238 ps
CPU time 2.75 seconds
Started Jan 03 12:54:41 PM PST 24
Finished Jan 03 12:56:26 PM PST 24
Peak memory 238428 kb
Host smart-413c3578-efba-49be-b6ca-717fb68a24dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203978465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2203978465
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.1314217798
Short name T219
Test name
Test status
Simulation time 552663095658 ps
CPU time 6988.51 seconds
Started Jan 03 12:54:43 PM PST 24
Finished Jan 03 02:52:45 PM PST 24
Peak memory 395468 kb
Host smart-d0a4571e-7aea-4e5f-8465-849983fe2f2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314217798 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.1314217798
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.589851360
Short name T427
Test name
Test status
Simulation time 159294466 ps
CPU time 4.76 seconds
Started Jan 03 12:54:47 PM PST 24
Finished Jan 03 12:56:36 PM PST 24
Peak memory 238356 kb
Host smart-e3655df0-3374-4c76-976b-af43d77c1876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589851360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.589851360
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.1416214663
Short name T131
Test name
Test status
Simulation time 1877874880 ps
CPU time 4.21 seconds
Started Jan 03 12:54:45 PM PST 24
Finished Jan 03 12:56:28 PM PST 24
Peak memory 238332 kb
Host smart-aac93aa0-f4e4-4740-8261-bb9a31d37cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416214663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.1416214663
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.2049358857
Short name T931
Test name
Test status
Simulation time 193880866 ps
CPU time 2.69 seconds
Started Jan 03 12:54:44 PM PST 24
Finished Jan 03 12:56:31 PM PST 24
Peak memory 240984 kb
Host smart-fbd51433-903b-431c-a455-6cf0a5698281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049358857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.2049358857
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.983330110
Short name T922
Test name
Test status
Simulation time 77308323 ps
CPU time 1.74 seconds
Started Jan 03 12:53:08 PM PST 24
Finished Jan 03 12:54:35 PM PST 24
Peak memory 238532 kb
Host smart-c027746d-2dad-48f0-9834-8e1f3d9438c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983330110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.983330110
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.2345762234
Short name T500
Test name
Test status
Simulation time 3063354632 ps
CPU time 12.72 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:18 PM PST 24
Peak memory 244744 kb
Host smart-20a58612-beb2-4255-a9f2-a7859e32f28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345762234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.2345762234
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.2441789027
Short name T958
Test name
Test status
Simulation time 1382658659 ps
CPU time 15.32 seconds
Started Jan 03 12:53:47 PM PST 24
Finished Jan 03 12:55:11 PM PST 24
Peak memory 238484 kb
Host smart-9c91dba7-baa2-4748-8a12-d84c47426573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441789027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.2441789027
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.3061073725
Short name T575
Test name
Test status
Simulation time 362795874 ps
CPU time 5.42 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:54:34 PM PST 24
Peak memory 238480 kb
Host smart-bcffd9bb-3e8a-4025-a968-45ab990f7682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061073725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.3061073725
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.1681769855
Short name T1078
Test name
Test status
Simulation time 355400060 ps
CPU time 5.93 seconds
Started Jan 03 12:53:45 PM PST 24
Finished Jan 03 12:55:06 PM PST 24
Peak memory 238556 kb
Host smart-7b4ec285-0208-445e-a20c-9db2bca53c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681769855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.1681769855
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.4140209661
Short name T752
Test name
Test status
Simulation time 458470558 ps
CPU time 3.83 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:54:54 PM PST 24
Peak memory 238364 kb
Host smart-a65b51aa-a6b8-470c-a963-65f7b1da162c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140209661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.4140209661
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.4172549807
Short name T582
Test name
Test status
Simulation time 3048538636 ps
CPU time 20.4 seconds
Started Jan 03 12:53:30 PM PST 24
Finished Jan 03 12:54:45 PM PST 24
Peak memory 244600 kb
Host smart-a821d009-4d5d-4a3c-b901-b02d5e22df51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172549807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.4172549807
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.3324891163
Short name T190
Test name
Test status
Simulation time 1572705646 ps
CPU time 4.8 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:54:57 PM PST 24
Peak memory 240848 kb
Host smart-d8122a4a-6c25-4011-9234-c741ce84e291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324891163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.3324891163
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.199060462
Short name T233
Test name
Test status
Simulation time 170927474 ps
CPU time 3.67 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:54:38 PM PST 24
Peak memory 238508 kb
Host smart-2dfcb1cb-197a-4c91-a009-91d614a01523
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=199060462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.199060462
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.2626274511
Short name T971
Test name
Test status
Simulation time 144733881 ps
CPU time 4.02 seconds
Started Jan 03 12:53:50 PM PST 24
Finished Jan 03 12:55:10 PM PST 24
Peak memory 241124 kb
Host smart-1e74d907-5fa3-4831-b44b-ac9007032a16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2626274511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.2626274511
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.2291176054
Short name T784
Test name
Test status
Simulation time 2071069644 ps
CPU time 6.51 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:54:52 PM PST 24
Peak memory 238388 kb
Host smart-44349ce1-0dde-4ffb-bb9b-ad336bf5f0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291176054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.2291176054
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.3238042160
Short name T1116
Test name
Test status
Simulation time 7377535403 ps
CPU time 117.01 seconds
Started Jan 03 12:53:30 PM PST 24
Finished Jan 03 12:56:17 PM PST 24
Peak memory 241768 kb
Host smart-08ea535b-aca2-4de6-bfb6-b1b297642ca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238042160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
3238042160
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.90809134
Short name T846
Test name
Test status
Simulation time 5148625582831 ps
CPU time 6656.01 seconds
Started Jan 03 12:53:48 PM PST 24
Finished Jan 03 02:46:08 PM PST 24
Peak memory 291068 kb
Host smart-1d0e99d9-7ce4-4f9d-99ee-47b4a100de5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90809134 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.90809134
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.2376895928
Short name T677
Test name
Test status
Simulation time 1659399020 ps
CPU time 24.01 seconds
Started Jan 03 12:53:33 PM PST 24
Finished Jan 03 12:54:54 PM PST 24
Peak memory 237608 kb
Host smart-005bdfe3-da52-4bb4-8443-65046d44f39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376895928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2376895928
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.558208420
Short name T662
Test name
Test status
Simulation time 402832585 ps
CPU time 5 seconds
Started Jan 03 12:54:48 PM PST 24
Finished Jan 03 12:56:32 PM PST 24
Peak memory 242488 kb
Host smart-7360dd3a-74e7-4e05-b338-106a1aa93705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558208420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.558208420
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.2885706158
Short name T225
Test name
Test status
Simulation time 2076594078644 ps
CPU time 6213.96 seconds
Started Jan 03 12:54:39 PM PST 24
Finished Jan 03 02:39:47 PM PST 24
Peak memory 967160 kb
Host smart-0d3033ec-5604-450c-9faa-60f1465b556d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885706158 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.2885706158
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.3442110918
Short name T1052
Test name
Test status
Simulation time 235868559 ps
CPU time 4.1 seconds
Started Jan 03 12:54:51 PM PST 24
Finished Jan 03 12:56:31 PM PST 24
Peak memory 238488 kb
Host smart-04d63afc-4b5c-4c8a-8670-de3327517772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442110918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.3442110918
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.786089101
Short name T780
Test name
Test status
Simulation time 173273398 ps
CPU time 4.28 seconds
Started Jan 03 12:54:59 PM PST 24
Finished Jan 03 12:56:41 PM PST 24
Peak memory 241964 kb
Host smart-eb1fdc0a-efd5-429c-8a8a-b752de35190b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786089101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.786089101
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.2454575326
Short name T264
Test name
Test status
Simulation time 219984893570 ps
CPU time 3434.09 seconds
Started Jan 03 12:54:58 PM PST 24
Finished Jan 03 01:53:50 PM PST 24
Peak memory 714792 kb
Host smart-a2dafc2a-1dd0-44ae-91d6-a0dcca3c313b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454575326 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.2454575326
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.3335885846
Short name T888
Test name
Test status
Simulation time 376288628 ps
CPU time 3.83 seconds
Started Jan 03 12:54:55 PM PST 24
Finished Jan 03 12:56:40 PM PST 24
Peak memory 238324 kb
Host smart-ede62fd7-d5a1-4b9d-83ce-1dce547fb922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335885846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.3335885846
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.3484945504
Short name T785
Test name
Test status
Simulation time 6392869293 ps
CPU time 9.73 seconds
Started Jan 03 12:54:57 PM PST 24
Finished Jan 03 12:56:37 PM PST 24
Peak memory 246316 kb
Host smart-1299f7d0-1455-4c13-8ec0-e50d5937c2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484945504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.3484945504
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.2559133897
Short name T1032
Test name
Test status
Simulation time 294865178304 ps
CPU time 761.56 seconds
Started Jan 03 12:54:51 PM PST 24
Finished Jan 03 01:09:08 PM PST 24
Peak memory 307596 kb
Host smart-15cabb79-2196-4f10-8549-7853781b4e55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559133897 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.2559133897
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.1475496956
Short name T608
Test name
Test status
Simulation time 164458520 ps
CPU time 4.27 seconds
Started Jan 03 12:55:02 PM PST 24
Finished Jan 03 12:56:55 PM PST 24
Peak memory 238320 kb
Host smart-3bb00772-1af3-4aef-a463-72c536db1a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475496956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.1475496956
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.4229932888
Short name T442
Test name
Test status
Simulation time 588970299 ps
CPU time 6.44 seconds
Started Jan 03 12:54:55 PM PST 24
Finished Jan 03 12:56:54 PM PST 24
Peak memory 243228 kb
Host smart-375bfb65-eb79-4738-b3ce-e16b29c3a53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229932888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.4229932888
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.1427381505
Short name T989
Test name
Test status
Simulation time 5180778329934 ps
CPU time 9280.76 seconds
Started Jan 03 12:54:59 PM PST 24
Finished Jan 03 03:31:25 PM PST 24
Peak memory 271808 kb
Host smart-85daa3be-8670-4d7b-a97f-d68228adb64b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427381505 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.1427381505
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.2859696915
Short name T898
Test name
Test status
Simulation time 2529644152 ps
CPU time 4.86 seconds
Started Jan 03 12:54:58 PM PST 24
Finished Jan 03 12:56:40 PM PST 24
Peak memory 238448 kb
Host smart-ee2c3393-488e-4b96-b94a-55a534504834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859696915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.2859696915
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.3035620428
Short name T978
Test name
Test status
Simulation time 4037443825 ps
CPU time 7.07 seconds
Started Jan 03 12:54:55 PM PST 24
Finished Jan 03 12:56:55 PM PST 24
Peak memory 243804 kb
Host smart-0683ee93-7ded-40b6-8a21-d3bccd0dd3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035620428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.3035620428
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.3728883595
Short name T339
Test name
Test status
Simulation time 3420827850934 ps
CPU time 8553.96 seconds
Started Jan 03 12:55:04 PM PST 24
Finished Jan 03 03:19:41 PM PST 24
Peak memory 1569200 kb
Host smart-b09f71e1-a426-4f38-849c-53919b4a1eae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728883595 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.3728883595
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.912446472
Short name T945
Test name
Test status
Simulation time 132479724 ps
CPU time 4.54 seconds
Started Jan 03 12:54:50 PM PST 24
Finished Jan 03 12:56:31 PM PST 24
Peak memory 238436 kb
Host smart-5750534e-14da-4670-a36f-02ab9ff4162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912446472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.912446472
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.3226851818
Short name T772
Test name
Test status
Simulation time 489406754 ps
CPU time 7.36 seconds
Started Jan 03 12:54:54 PM PST 24
Finished Jan 03 12:56:43 PM PST 24
Peak memory 238408 kb
Host smart-af8ff9d1-b5aa-48c5-9fe7-1012c2c90b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226851818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.3226851818
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.3642620733
Short name T1104
Test name
Test status
Simulation time 296838696283 ps
CPU time 3584.51 seconds
Started Jan 03 12:54:54 PM PST 24
Finished Jan 03 01:56:10 PM PST 24
Peak memory 263200 kb
Host smart-ac72f211-2909-49a2-a1e3-b29bb7aa0ad8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642620733 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.3642620733
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.1211395267
Short name T70
Test name
Test status
Simulation time 730449533 ps
CPU time 4.63 seconds
Started Jan 03 12:55:00 PM PST 24
Finished Jan 03 12:57:11 PM PST 24
Peak memory 238320 kb
Host smart-0c8aaa04-bce0-4830-a86d-5ff9796cda6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211395267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.1211395267
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.2741243938
Short name T658
Test name
Test status
Simulation time 438640570 ps
CPU time 5.9 seconds
Started Jan 03 12:54:57 PM PST 24
Finished Jan 03 12:56:33 PM PST 24
Peak memory 242144 kb
Host smart-fe5d8be0-d7ab-4638-8266-e8dd251c9401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741243938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.2741243938
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.3134805291
Short name T1079
Test name
Test status
Simulation time 1038730318135 ps
CPU time 4927.6 seconds
Started Jan 03 12:54:56 PM PST 24
Finished Jan 03 02:19:14 PM PST 24
Peak memory 314092 kb
Host smart-a2bb784b-e4b9-4697-bdcd-1599c56f6565
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134805291 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.3134805291
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.732738790
Short name T516
Test name
Test status
Simulation time 295010284 ps
CPU time 5.06 seconds
Started Jan 03 12:54:58 PM PST 24
Finished Jan 03 12:56:51 PM PST 24
Peak memory 240516 kb
Host smart-9f8b8140-96a9-46d6-94f3-adb20d8e00ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732738790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.732738790
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.3642418635
Short name T901
Test name
Test status
Simulation time 298716237 ps
CPU time 3.7 seconds
Started Jan 03 12:55:05 PM PST 24
Finished Jan 03 12:56:49 PM PST 24
Peak memory 243212 kb
Host smart-1582a20f-8131-4559-a809-9c11f163ac95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642418635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.3642418635
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.2724007789
Short name T1001
Test name
Test status
Simulation time 312985476683 ps
CPU time 2866.43 seconds
Started Jan 03 12:54:51 PM PST 24
Finished Jan 03 01:44:13 PM PST 24
Peak memory 651676 kb
Host smart-26ae26f7-7e93-49be-ad94-44b63e4707a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724007789 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.2724007789
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.471157655
Short name T754
Test name
Test status
Simulation time 583798282 ps
CPU time 4.59 seconds
Started Jan 03 12:55:08 PM PST 24
Finished Jan 03 12:56:40 PM PST 24
Peak memory 238388 kb
Host smart-bc8074fc-28ca-466d-b94b-c4a8d2ffc09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471157655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.471157655
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.1743856678
Short name T373
Test name
Test status
Simulation time 348892389 ps
CPU time 4.37 seconds
Started Jan 03 12:54:55 PM PST 24
Finished Jan 03 12:56:45 PM PST 24
Peak memory 241672 kb
Host smart-81a7ed53-464e-4dbe-9928-3e982e45907e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743856678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.1743856678
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.1537353678
Short name T897
Test name
Test status
Simulation time 115213875807 ps
CPU time 1563.38 seconds
Started Jan 03 12:54:58 PM PST 24
Finished Jan 03 01:22:49 PM PST 24
Peak memory 246836 kb
Host smart-ae98954f-8ac0-4429-82bb-d324d6d42aca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537353678 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.1537353678
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.2088191904
Short name T915
Test name
Test status
Simulation time 2874192137 ps
CPU time 4.94 seconds
Started Jan 03 12:54:50 PM PST 24
Finished Jan 03 12:56:31 PM PST 24
Peak memory 238492 kb
Host smart-f1b89d6b-a993-4204-ad1c-835eb566bd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088191904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2088191904
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.4163732958
Short name T474
Test name
Test status
Simulation time 223870633 ps
CPU time 2.97 seconds
Started Jan 03 12:54:57 PM PST 24
Finished Jan 03 12:56:42 PM PST 24
Peak memory 240816 kb
Host smart-45b19dec-9d03-4563-bbf6-53829223b538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163732958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.4163732958
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.726879644
Short name T260
Test name
Test status
Simulation time 340876062114 ps
CPU time 4369.41 seconds
Started Jan 03 12:54:57 PM PST 24
Finished Jan 03 02:09:35 PM PST 24
Peak memory 316460 kb
Host smart-e9804bda-a2f3-4b53-ad09-f5bef80d62a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726879644 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.726879644
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.4202498856
Short name T462
Test name
Test status
Simulation time 918686986 ps
CPU time 1.76 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:54:43 PM PST 24
Peak memory 238600 kb
Host smart-c14c061b-9fa3-46d3-ac95-e5cd63c60672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202498856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.4202498856
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.941619448
Short name T847
Test name
Test status
Simulation time 1328942975 ps
CPU time 9.55 seconds
Started Jan 03 12:53:09 PM PST 24
Finished Jan 03 12:54:12 PM PST 24
Peak memory 244144 kb
Host smart-55e0fb91-dfda-4e25-82d0-8c421027038d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941619448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.941619448
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.813765289
Short name T566
Test name
Test status
Simulation time 592550745 ps
CPU time 10.24 seconds
Started Jan 03 12:53:04 PM PST 24
Finished Jan 03 12:54:19 PM PST 24
Peak memory 238568 kb
Host smart-2792eddb-ab5c-4b67-aa31-24a919174e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813765289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.813765289
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.932234670
Short name T844
Test name
Test status
Simulation time 352447047 ps
CPU time 4.85 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:54:46 PM PST 24
Peak memory 238488 kb
Host smart-a1e65800-b494-4c47-bf15-7a15937e018a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932234670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.932234670
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.2429853617
Short name T106
Test name
Test status
Simulation time 1935861230 ps
CPU time 13.69 seconds
Started Jan 03 12:53:34 PM PST 24
Finished Jan 03 12:54:43 PM PST 24
Peak memory 243784 kb
Host smart-f86e9c6c-314d-49f7-adde-e7a113c10994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429853617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.2429853617
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.2111149919
Short name T102
Test name
Test status
Simulation time 2596137494 ps
CPU time 4.53 seconds
Started Jan 03 12:53:43 PM PST 24
Finished Jan 03 12:54:53 PM PST 24
Peak memory 240920 kb
Host smart-cd73485d-5034-44c3-8ae2-25d492bab3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111149919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.2111149919
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.482613306
Short name T284
Test name
Test status
Simulation time 430241571 ps
CPU time 7.24 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:54:49 PM PST 24
Peak memory 238620 kb
Host smart-1faa525f-8359-4721-a588-3d9c2db024a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482613306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.482613306
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.2667477687
Short name T448
Test name
Test status
Simulation time 2162835986 ps
CPU time 5.72 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:54:47 PM PST 24
Peak memory 231384 kb
Host smart-2e5d67c1-5211-4f6a-b67f-3c0de9a75e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667477687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.2667477687
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.4061524028
Short name T84
Test name
Test status
Simulation time 321405069 ps
CPU time 6.04 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:51 PM PST 24
Peak memory 242492 kb
Host smart-fde80d89-35c8-4e0e-9bf4-eef7fb70026e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061524028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.4061524028
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.787281052
Short name T89
Test name
Test status
Simulation time 2474234375 ps
CPU time 17.23 seconds
Started Jan 03 12:53:35 PM PST 24
Finished Jan 03 12:54:46 PM PST 24
Peak memory 243484 kb
Host smart-f71854ab-1f77-4ba5-85d7-3443f2694c0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=787281052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.787281052
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.2161554602
Short name T308
Test name
Test status
Simulation time 3017823716 ps
CPU time 5.8 seconds
Started Jan 03 12:54:06 PM PST 24
Finished Jan 03 12:55:51 PM PST 24
Peak memory 238608 kb
Host smart-3d1b2895-8e2d-489a-a99f-f2c4a6bb7205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2161554602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.2161554602
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.20217567
Short name T629
Test name
Test status
Simulation time 101509156 ps
CPU time 2.94 seconds
Started Jan 03 12:53:19 PM PST 24
Finished Jan 03 12:54:29 PM PST 24
Peak memory 240740 kb
Host smart-4ee2274e-1a9b-46cd-95fa-8002d1289a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20217567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.20217567
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.259943657
Short name T370
Test name
Test status
Simulation time 3471916313 ps
CPU time 21.6 seconds
Started Jan 03 12:53:49 PM PST 24
Finished Jan 03 12:55:27 PM PST 24
Peak memory 238452 kb
Host smart-517142af-4c13-4227-975d-c8e64f67123e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259943657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.259943657
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.3786194026
Short name T143
Test name
Test status
Simulation time 332906859 ps
CPU time 5.51 seconds
Started Jan 03 12:53:49 PM PST 24
Finished Jan 03 12:55:18 PM PST 24
Peak memory 238472 kb
Host smart-51a09bda-c841-4a97-86d8-739668186822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786194026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.3786194026
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.569206
Short name T924
Test name
Test status
Simulation time 462764990 ps
CPU time 3.93 seconds
Started Jan 03 12:54:56 PM PST 24
Finished Jan 03 12:56:43 PM PST 24
Peak memory 240768 kb
Host smart-0943cd53-2cf2-401a-b87c-885ec36d8058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.569206
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.837288457
Short name T147
Test name
Test status
Simulation time 172547840 ps
CPU time 4.03 seconds
Started Jan 03 12:55:14 PM PST 24
Finished Jan 03 12:56:47 PM PST 24
Peak memory 238488 kb
Host smart-615fc514-dff2-4537-bab4-9ef337f1bd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837288457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.837288457
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.2123876986
Short name T751
Test name
Test status
Simulation time 251915537593 ps
CPU time 2844.47 seconds
Started Jan 03 12:54:55 PM PST 24
Finished Jan 03 01:44:06 PM PST 24
Peak memory 295020 kb
Host smart-bce6d2e7-db46-41ec-8bcc-889a6967f0a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123876986 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.2123876986
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.464513877
Short name T418
Test name
Test status
Simulation time 434169170 ps
CPU time 4.15 seconds
Started Jan 03 12:54:50 PM PST 24
Finished Jan 03 12:56:26 PM PST 24
Peak memory 238408 kb
Host smart-7f311e0f-2aed-4280-973e-d5fa62a6190c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464513877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.464513877
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.872635117
Short name T879
Test name
Test status
Simulation time 167425959 ps
CPU time 6.87 seconds
Started Jan 03 12:55:01 PM PST 24
Finished Jan 03 12:56:55 PM PST 24
Peak memory 238408 kb
Host smart-9fe20ff7-e74a-4698-beb1-bd46da2828db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872635117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.872635117
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.859607850
Short name T213
Test name
Test status
Simulation time 1406083545014 ps
CPU time 10214.2 seconds
Started Jan 03 12:54:56 PM PST 24
Finished Jan 03 03:46:52 PM PST 24
Peak memory 1139768 kb
Host smart-6ae8200f-3e87-4fe8-9a9a-4efff2f99886
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859607850 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.859607850
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.1617920045
Short name T1068
Test name
Test status
Simulation time 152918721 ps
CPU time 3.7 seconds
Started Jan 03 12:54:56 PM PST 24
Finished Jan 03 12:56:43 PM PST 24
Peak memory 238344 kb
Host smart-5eb3689f-0f04-47b2-bd2a-bfa5b0d6ddf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617920045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.1617920045
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.1054644643
Short name T476
Test name
Test status
Simulation time 224359114 ps
CPU time 4.92 seconds
Started Jan 03 12:55:01 PM PST 24
Finished Jan 03 12:56:53 PM PST 24
Peak memory 238444 kb
Host smart-aa91a58d-a028-4ecc-adcf-f3ebe236e3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054644643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.1054644643
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.1085237310
Short name T950
Test name
Test status
Simulation time 1303732174076 ps
CPU time 6089.02 seconds
Started Jan 03 12:54:55 PM PST 24
Finished Jan 03 02:38:09 PM PST 24
Peak memory 299888 kb
Host smart-56e8af89-7a8d-4dfe-ac73-3ad49cfe58ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085237310 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.1085237310
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.3858809272
Short name T848
Test name
Test status
Simulation time 345516527 ps
CPU time 4.38 seconds
Started Jan 03 12:55:01 PM PST 24
Finished Jan 03 12:56:42 PM PST 24
Peak memory 238384 kb
Host smart-70009a71-f32d-4e6f-8768-84d8d6f7105d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858809272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.3858809272
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.1546311587
Short name T229
Test name
Test status
Simulation time 352376987 ps
CPU time 7.51 seconds
Started Jan 03 12:54:56 PM PST 24
Finished Jan 03 12:56:46 PM PST 24
Peak memory 241592 kb
Host smart-8faa2032-f087-422e-83ad-37938257e88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546311587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.1546311587
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.70608484
Short name T1115
Test name
Test status
Simulation time 232989433100 ps
CPU time 2718.59 seconds
Started Jan 03 12:54:54 PM PST 24
Finished Jan 03 01:41:54 PM PST 24
Peak memory 295204 kb
Host smart-a64d3a35-ca41-424f-8224-0af146b9281a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70608484 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.70608484
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.2462863063
Short name T433
Test name
Test status
Simulation time 304898321 ps
CPU time 4.11 seconds
Started Jan 03 12:54:57 PM PST 24
Finished Jan 03 12:56:43 PM PST 24
Peak memory 238472 kb
Host smart-4604af97-0180-473e-afe2-93dc0f010c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462863063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.2462863063
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.3084113698
Short name T429
Test name
Test status
Simulation time 2050415137 ps
CPU time 6.82 seconds
Started Jan 03 12:54:57 PM PST 24
Finished Jan 03 12:56:34 PM PST 24
Peak memory 238444 kb
Host smart-a92ea5ad-f917-4ab3-a4c7-087bbaaa569b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084113698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.3084113698
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.3395010235
Short name T222
Test name
Test status
Simulation time 3977760733052 ps
CPU time 7369.96 seconds
Started Jan 03 12:55:00 PM PST 24
Finished Jan 03 02:59:57 PM PST 24
Peak memory 312916 kb
Host smart-af8ab58e-e835-4af8-b75f-eddc6ac43c9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395010235 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.3395010235
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.4083831406
Short name T711
Test name
Test status
Simulation time 155302785 ps
CPU time 4.26 seconds
Started Jan 03 12:55:00 PM PST 24
Finished Jan 03 12:56:37 PM PST 24
Peak memory 238312 kb
Host smart-864ebb1b-4b7f-4899-8ada-67221e193db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083831406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.4083831406
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.1886928638
Short name T797
Test name
Test status
Simulation time 169025645 ps
CPU time 4.38 seconds
Started Jan 03 12:54:56 PM PST 24
Finished Jan 03 12:56:37 PM PST 24
Peak memory 238304 kb
Host smart-4b408ee7-11ec-440e-9aec-6299cae92b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886928638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.1886928638
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.3438629810
Short name T347
Test name
Test status
Simulation time 226173368055 ps
CPU time 335.19 seconds
Started Jan 03 12:55:01 PM PST 24
Finished Jan 03 01:02:13 PM PST 24
Peak memory 255108 kb
Host smart-c887bae8-c322-47f0-bf31-8011b17daff2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438629810 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.3438629810
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.1787079687
Short name T937
Test name
Test status
Simulation time 1524405594 ps
CPU time 4.1 seconds
Started Jan 03 12:54:58 PM PST 24
Finished Jan 03 12:56:45 PM PST 24
Peak memory 241004 kb
Host smart-d7f04818-5537-4043-b570-3953eef0bb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787079687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.1787079687
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.4199525757
Short name T836
Test name
Test status
Simulation time 175162662 ps
CPU time 3.57 seconds
Started Jan 03 12:54:59 PM PST 24
Finished Jan 03 12:56:50 PM PST 24
Peak memory 241072 kb
Host smart-a6ed072f-a6ba-4aa3-97e5-f08386a04ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199525757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.4199525757
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.2599184625
Short name T223
Test name
Test status
Simulation time 519314013877 ps
CPU time 6447.66 seconds
Started Jan 03 12:55:04 PM PST 24
Finished Jan 03 02:44:34 PM PST 24
Peak memory 885932 kb
Host smart-9084df05-9bb0-44c9-ac07-c98736e798d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599184625 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.2599184625
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.2756780866
Short name T144
Test name
Test status
Simulation time 540473878 ps
CPU time 3.58 seconds
Started Jan 03 12:54:58 PM PST 24
Finished Jan 03 12:56:45 PM PST 24
Peak memory 240152 kb
Host smart-f58596f7-7ade-464e-a0ca-24ace6490cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756780866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.2756780866
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.4147470993
Short name T667
Test name
Test status
Simulation time 182133619 ps
CPU time 4.44 seconds
Started Jan 03 12:55:04 PM PST 24
Finished Jan 03 12:56:37 PM PST 24
Peak memory 242000 kb
Host smart-7372b060-eb16-4875-8e3c-eebd0d7e45b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147470993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.4147470993
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.668217608
Short name T272
Test name
Test status
Simulation time 4117487384465 ps
CPU time 7497.09 seconds
Started Jan 03 12:55:02 PM PST 24
Finished Jan 03 03:01:44 PM PST 24
Peak memory 855616 kb
Host smart-39f329e5-bbe8-4831-8101-6df1ca1977e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668217608 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.668217608
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.1307982804
Short name T1
Test name
Test status
Simulation time 115791356 ps
CPU time 2.99 seconds
Started Jan 03 12:54:57 PM PST 24
Finished Jan 03 12:56:42 PM PST 24
Peak memory 240768 kb
Host smart-d7382216-3816-4d69-86c7-be2c330f5ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307982804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.1307982804
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.411123969
Short name T498
Test name
Test status
Simulation time 192496309 ps
CPU time 5.37 seconds
Started Jan 03 12:55:02 PM PST 24
Finished Jan 03 12:56:53 PM PST 24
Peak memory 242088 kb
Host smart-1d6f2d6b-124c-4733-a89c-281733f93622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411123969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.411123969
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.1370625951
Short name T949
Test name
Test status
Simulation time 884349982270 ps
CPU time 7749.03 seconds
Started Jan 03 12:54:54 PM PST 24
Finished Jan 03 03:05:36 PM PST 24
Peak memory 1579180 kb
Host smart-d543a41a-8b6c-4bb8-adac-bafb5bc97153
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370625951 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.1370625951
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.3634599379
Short name T739
Test name
Test status
Simulation time 2486824044 ps
CPU time 4.51 seconds
Started Jan 03 12:55:05 PM PST 24
Finished Jan 03 12:56:45 PM PST 24
Peak memory 238532 kb
Host smart-acb0c29b-5a49-43c0-a448-03ea46b23ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634599379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.3634599379
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.1209620640
Short name T255
Test name
Test status
Simulation time 101618741 ps
CPU time 3.73 seconds
Started Jan 03 12:55:02 PM PST 24
Finished Jan 03 12:56:54 PM PST 24
Peak memory 241296 kb
Host smart-051526b6-1694-4244-b4c5-de339c69a50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209620640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.1209620640
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.274014350
Short name T218
Test name
Test status
Simulation time 2573374754724 ps
CPU time 5246.54 seconds
Started Jan 03 12:54:59 PM PST 24
Finished Jan 03 02:24:08 PM PST 24
Peak memory 272020 kb
Host smart-11c139bb-397e-4daf-97a6-e7ca971541a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274014350 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.274014350
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.1255560404
Short name T588
Test name
Test status
Simulation time 294907608 ps
CPU time 2.3 seconds
Started Jan 03 12:53:39 PM PST 24
Finished Jan 03 12:54:46 PM PST 24
Peak memory 238156 kb
Host smart-766acb30-8e7b-49ca-8e24-1241a6349271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255560404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.1255560404
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.2545501926
Short name T1059
Test name
Test status
Simulation time 2110170266 ps
CPU time 15.46 seconds
Started Jan 03 12:53:38 PM PST 24
Finished Jan 03 12:55:01 PM PST 24
Peak memory 246824 kb
Host smart-acb3937f-a860-4a87-9559-effb3a95e214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545501926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.2545501926
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.2188607116
Short name T810
Test name
Test status
Simulation time 1114832592 ps
CPU time 16.57 seconds
Started Jan 03 12:53:41 PM PST 24
Finished Jan 03 12:54:57 PM PST 24
Peak memory 238508 kb
Host smart-7af3a8de-cd4c-498f-8278-8835f0a7c93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188607116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2188607116
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.1059758777
Short name T277
Test name
Test status
Simulation time 3080046272 ps
CPU time 13.51 seconds
Started Jan 03 12:53:46 PM PST 24
Finished Jan 03 12:55:06 PM PST 24
Peak memory 245212 kb
Host smart-31d0a1d5-cb8c-46d5-9495-5140fb286c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059758777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.1059758777
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.2690565898
Short name T684
Test name
Test status
Simulation time 673633731 ps
CPU time 8.82 seconds
Started Jan 03 12:53:37 PM PST 24
Finished Jan 03 12:54:46 PM PST 24
Peak memory 243552 kb
Host smart-7f49f2c1-9a3b-4171-9645-5c9343d0e544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690565898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.2690565898
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.523183726
Short name T1061
Test name
Test status
Simulation time 201512728 ps
CPU time 2.99 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:55:20 PM PST 24
Peak memory 240984 kb
Host smart-22053298-d667-460e-8506-c0970da95ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523183726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.523183726
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.4234560222
Short name T903
Test name
Test status
Simulation time 508701996 ps
CPU time 7.28 seconds
Started Jan 03 12:53:40 PM PST 24
Finished Jan 03 12:54:53 PM PST 24
Peak memory 245056 kb
Host smart-471e9831-a138-40db-95b7-1870ae581d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234560222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.4234560222
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.1089430772
Short name T712
Test name
Test status
Simulation time 248674833 ps
CPU time 6.77 seconds
Started Jan 03 12:54:00 PM PST 24
Finished Jan 03 12:55:42 PM PST 24
Peak memory 245224 kb
Host smart-d82beb97-b305-447a-82bc-d40f44062282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089430772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.1089430772
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.805072921
Short name T1055
Test name
Test status
Simulation time 326611050 ps
CPU time 3.13 seconds
Started Jan 03 12:53:51 PM PST 24
Finished Jan 03 12:55:14 PM PST 24
Peak memory 238292 kb
Host smart-3177c40b-d205-4376-bc7a-43dfd28c0c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805072921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.805072921
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.1831760400
Short name T561
Test name
Test status
Simulation time 172041191 ps
CPU time 4.67 seconds
Started Jan 03 12:53:49 PM PST 24
Finished Jan 03 12:55:10 PM PST 24
Peak memory 238300 kb
Host smart-fb65b5dd-7ca0-410e-b856-10877896b12d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1831760400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.1831760400
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.4018918133
Short name T310
Test name
Test status
Simulation time 460331526 ps
CPU time 4.6 seconds
Started Jan 03 12:53:53 PM PST 24
Finished Jan 03 12:55:21 PM PST 24
Peak memory 238452 kb
Host smart-6f9a3de5-fdb8-4ab2-a328-415072e10109
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4018918133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.4018918133
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.3459224501
Short name T974
Test name
Test status
Simulation time 319877022 ps
CPU time 3.81 seconds
Started Jan 03 12:53:36 PM PST 24
Finished Jan 03 12:54:38 PM PST 24
Peak memory 238316 kb
Host smart-ed1bb24d-610e-462c-9ff8-7893049d4dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459224501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.3459224501
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.4146898529
Short name T220
Test name
Test status
Simulation time 243572023658 ps
CPU time 2708.47 seconds
Started Jan 03 12:54:31 PM PST 24
Finished Jan 03 01:41:27 PM PST 24
Peak memory 260696 kb
Host smart-1811c500-3820-4808-a311-d9d651142405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146898529 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.4146898529
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.1912952952
Short name T1074
Test name
Test status
Simulation time 565472416 ps
CPU time 11.44 seconds
Started Jan 03 12:53:57 PM PST 24
Finished Jan 03 12:55:39 PM PST 24
Peak memory 246700 kb
Host smart-1b56565f-754d-48ce-9020-19d4fc3ff2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912952952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.1912952952
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.3912383658
Short name T880
Test name
Test status
Simulation time 368904685 ps
CPU time 4.38 seconds
Started Jan 03 12:54:58 PM PST 24
Finished Jan 03 12:56:48 PM PST 24
Peak memory 238452 kb
Host smart-2617cec4-197e-439b-88d8-c12ca2f703e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912383658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.3912383658
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.1966355604
Short name T894
Test name
Test status
Simulation time 251032274 ps
CPU time 4.95 seconds
Started Jan 03 12:55:00 PM PST 24
Finished Jan 03 12:57:11 PM PST 24
Peak memory 242840 kb
Host smart-c38c1b71-92fd-4c87-b4ea-b99c34d4a7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966355604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.1966355604
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.102532277
Short name T227
Test name
Test status
Simulation time 2570827983781 ps
CPU time 3179.31 seconds
Started Jan 03 12:54:59 PM PST 24
Finished Jan 03 01:49:43 PM PST 24
Peak memory 350236 kb
Host smart-c340d42f-493d-4d5a-ae3a-990bab878db7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102532277 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.102532277
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.4279817116
Short name T820
Test name
Test status
Simulation time 130448988 ps
CPU time 3.12 seconds
Started Jan 03 12:54:59 PM PST 24
Finished Jan 03 12:56:54 PM PST 24
Peak memory 238344 kb
Host smart-6e01a820-abc0-4a83-a5b3-09c8c2e936af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279817116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.4279817116
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.1383961963
Short name T199
Test name
Test status
Simulation time 3295485153 ps
CPU time 9.25 seconds
Started Jan 03 12:54:56 PM PST 24
Finished Jan 03 12:56:46 PM PST 24
Peak memory 238468 kb
Host smart-3d20b214-7686-4ab1-aa3d-462199cf37b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383961963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1383961963
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.1630975658
Short name T15
Test name
Test status
Simulation time 168268040420 ps
CPU time 1184.02 seconds
Started Jan 03 12:55:01 PM PST 24
Finished Jan 03 01:16:19 PM PST 24
Peak memory 443088 kb
Host smart-1f2ac4b1-4973-47f4-a0c3-59de8d613a4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630975658 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.1630975658
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.2124685081
Short name T578
Test name
Test status
Simulation time 206584601 ps
CPU time 3.05 seconds
Started Jan 03 12:55:00 PM PST 24
Finished Jan 03 12:57:05 PM PST 24
Peak memory 240676 kb
Host smart-474d9f32-8560-4142-9779-e4c0a0f02822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124685081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.2124685081
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.4214343143
Short name T184
Test name
Test status
Simulation time 148952646 ps
CPU time 3.61 seconds
Started Jan 03 12:55:02 PM PST 24
Finished Jan 03 12:56:50 PM PST 24
Peak memory 242400 kb
Host smart-e8ef0f4b-0920-4568-b662-c3794201dfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214343143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.4214343143
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.2919212438
Short name T236
Test name
Test status
Simulation time 1859045528170 ps
CPU time 6465.87 seconds
Started Jan 03 12:55:05 PM PST 24
Finished Jan 03 02:44:24 PM PST 24
Peak memory 820332 kb
Host smart-5f342c3d-0501-4c22-bfad-6668961de631
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919212438 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.2919212438
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.2146700693
Short name T479
Test name
Test status
Simulation time 2123192124 ps
CPU time 4.03 seconds
Started Jan 03 12:55:00 PM PST 24
Finished Jan 03 12:57:06 PM PST 24
Peak memory 238496 kb
Host smart-6190d6e5-ce09-4774-adc9-e31adde0f4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146700693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.2146700693
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.139176318
Short name T407
Test name
Test status
Simulation time 269522096 ps
CPU time 7.01 seconds
Started Jan 03 12:55:01 PM PST 24
Finished Jan 03 12:56:55 PM PST 24
Peak memory 238332 kb
Host smart-134d9889-9720-4a67-8bef-12e4e6a4dbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139176318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.139176318
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1654391020
Short name T265
Test name
Test status
Simulation time 784322860489 ps
CPU time 6909.51 seconds
Started Jan 03 12:54:57 PM PST 24
Finished Jan 03 02:51:38 PM PST 24
Peak memory 1628352 kb
Host smart-0b95ba1f-50f3-4b66-adb3-260a1daaa240
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654391020 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.1654391020
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.711092922
Short name T615
Test name
Test status
Simulation time 132325730 ps
CPU time 3.04 seconds
Started Jan 03 12:54:58 PM PST 24
Finished Jan 03 12:56:49 PM PST 24
Peak memory 246536 kb
Host smart-0f8962a4-2fa0-419a-bff0-beb970cbbcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711092922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.711092922
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.1970165734
Short name T318
Test name
Test status
Simulation time 340782359 ps
CPU time 3.78 seconds
Started Jan 03 12:54:59 PM PST 24
Finished Jan 03 12:56:45 PM PST 24
Peak memory 238248 kb
Host smart-9de19eab-89ce-4020-8c65-19ac35dcab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970165734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.1970165734
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.2491413413
Short name T1081
Test name
Test status
Simulation time 424669257838 ps
CPU time 6205.33 seconds
Started Jan 03 12:54:57 PM PST 24
Finished Jan 03 02:40:05 PM PST 24
Peak memory 281024 kb
Host smart-131f1155-5100-49a9-897d-e4f8182305d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491413413 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.2491413413
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.1139175878
Short name T132
Test name
Test status
Simulation time 220544153 ps
CPU time 3.75 seconds
Started Jan 03 12:54:58 PM PST 24
Finished Jan 03 12:56:49 PM PST 24
Peak memory 241232 kb
Host smart-442856b2-a598-477d-a98c-c0e7c6569783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139175878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.1139175878
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.2735387695
Short name T871
Test name
Test status
Simulation time 199994642 ps
CPU time 4.97 seconds
Started Jan 03 12:55:01 PM PST 24
Finished Jan 03 12:56:40 PM PST 24
Peak memory 243536 kb
Host smart-6a0fafb3-c1fc-4622-989e-04d4fc0c2b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735387695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.2735387695
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.3890415608
Short name T340
Test name
Test status
Simulation time 117571374702 ps
CPU time 2139.16 seconds
Started Jan 03 12:54:57 PM PST 24
Finished Jan 03 01:32:18 PM PST 24
Peak memory 281024 kb
Host smart-b1d6f542-a3ae-43a7-89dc-2faf2469db72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890415608 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.3890415608
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.669574914
Short name T67
Test name
Test status
Simulation time 146309577 ps
CPU time 4.15 seconds
Started Jan 03 12:55:02 PM PST 24
Finished Jan 03 12:56:55 PM PST 24
Peak memory 238484 kb
Host smart-6358db76-46fa-4ec9-8c22-a6bf27d11d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669574914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.669574914
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.1864098633
Short name T633
Test name
Test status
Simulation time 167517756 ps
CPU time 3.29 seconds
Started Jan 03 12:55:01 PM PST 24
Finished Jan 03 12:56:54 PM PST 24
Peak memory 241012 kb
Host smart-48617f92-778e-4940-8c5e-ef0d2cd1e356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864098633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.1864098633
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.2472541076
Short name T551
Test name
Test status
Simulation time 125471234865 ps
CPU time 1013.41 seconds
Started Jan 03 12:55:14 PM PST 24
Finished Jan 03 01:13:39 PM PST 24
Peak memory 338764 kb
Host smart-1342e8e0-d9d1-4d1a-bd73-c29d8cf323a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472541076 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.2472541076
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.3235411376
Short name T155
Test name
Test status
Simulation time 393478042 ps
CPU time 4.41 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:41 PM PST 24
Peak memory 238352 kb
Host smart-c6f465c3-f519-4836-a181-526aa5c15a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235411376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.3235411376
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.3179086909
Short name T1006
Test name
Test status
Simulation time 1452375350 ps
CPU time 9.33 seconds
Started Jan 03 12:55:14 PM PST 24
Finished Jan 03 12:56:53 PM PST 24
Peak memory 238356 kb
Host smart-6d74d3e9-7c5c-4b1b-99ac-5dfd9871f6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179086909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.3179086909
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.2485048183
Short name T570
Test name
Test status
Simulation time 246717222 ps
CPU time 4.01 seconds
Started Jan 03 12:55:44 PM PST 24
Finished Jan 03 12:57:09 PM PST 24
Peak memory 240684 kb
Host smart-abaae7d9-693f-49ee-b37e-c172f364293b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485048183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.2485048183
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.2944710284
Short name T550
Test name
Test status
Simulation time 109902581 ps
CPU time 2.75 seconds
Started Jan 03 12:55:13 PM PST 24
Finished Jan 03 12:56:49 PM PST 24
Peak memory 238344 kb
Host smart-4c58f369-b2ad-44ac-b44b-9ddec538ae41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944710284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.2944710284
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.832134060
Short name T215
Test name
Test status
Simulation time 426464700281 ps
CPU time 7488.58 seconds
Started Jan 03 12:55:42 PM PST 24
Finished Jan 03 03:01:43 PM PST 24
Peak memory 922744 kb
Host smart-053f6092-74f8-4c38-a027-4055215ae52d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832134060 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.832134060
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.3213769940
Short name T54
Test name
Test status
Simulation time 304879691 ps
CPU time 4.11 seconds
Started Jan 03 12:55:45 PM PST 24
Finished Jan 03 12:57:00 PM PST 24
Peak memory 241024 kb
Host smart-23629197-6de1-4101-bd0d-a36de10dfe5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213769940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.3213769940
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.2240832187
Short name T753
Test name
Test status
Simulation time 1902560194 ps
CPU time 7.79 seconds
Started Jan 03 12:55:45 PM PST 24
Finished Jan 03 12:57:03 PM PST 24
Peak memory 238444 kb
Host smart-a58b0075-e7d6-4955-9df4-f73a9f44a1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240832187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.2240832187
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.792367366
Short name T1060
Test name
Test status
Simulation time 517374400858 ps
CPU time 6833.9 seconds
Started Jan 03 12:55:41 PM PST 24
Finished Jan 03 02:50:56 PM PST 24
Peak memory 353724 kb
Host smart-734d6a67-04cd-4504-bf0a-436b6cb55036
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792367366 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.792367366
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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