Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
39.39	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

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Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	5	10	66.67
Crosses	51	35	16	31.37

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	5	2	28.57	100	1	1	0
partition	8	0	8	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	51	35	16	31.37	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	5	2	28.57

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
access_err	0	1	1
write_blank_err	0	1	1
ecc_uncorr_err	0	1	1
ecc_corr_err	0	1	1
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fsm_err

108512

1

T1

740

T9

1410

T8

2030

no_err

219988

1

T1

740

T9

1430

T4

2700

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lc_or_oob	19676	1			T21	8180		T22	2436		T23	1640
secret2	35246	1			T9	2820		T4	340		T5	220
secret1	54000	1			T4	560		T5	220		T7	40
secret0	27086	1			T1	1480		T4	480		T5	260
hw_cfg0	44540	1			T4	160		T5	280		T7	240
owner_sw_cfg	47314	1			T4	480		T5	280		T7	20
creator_sw_cfg	42768	1			T4	220		T5	660		T7	280
vendor_test	57870	1			T9	20		T4	460		T5	160

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	51	35	16	31.37	35
Automatically Generated Cross Bins	51	35	16	31.37	35
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Element holes

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[access_err]	*	--	--	8

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[write_blank_err]	[secret2 , secret1 , secret0 , hw_cfg0 , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	7
[ecc_uncorr_err]	[secret2 , secret1 , secret0 , hw_cfg0 , owner_sw_cfg , creator_sw_cfg]	--	--	6
[ecc_corr_err , macro_err]	[secret2 , secret1 , secret0 , hw_cfg0 , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	14

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	lc_or_oob	9830	1			T21	4090		T22	1210		T23	820
fsm_err	secret2	10030	1			T9	1410		T156	3380		T310	1460
fsm_err	secret1	19124	1			T8	2030		T204	1290		T64	140
fsm_err	secret0	6000	1			T1	740		T196	110		T147	940
fsm_err	hw_cfg0	13750	1			T311	2310		T101	6310		T160	1950
fsm_err	owner_sw_cfg	15998	1			T194	950		T265	890		T197	290
fsm_err	creator_sw_cfg	13040	1			T146	1440		T203	550		T195	960
fsm_err	vendor_test	20740	1			T48	300		T192	3800		T193	4850
no_err	lc_or_oob	9846	1			T21	4090		T22	1226		T23	820
no_err	secret2	25216	1			T9	1410		T4	340		T5	220
no_err	secret1	34876	1			T4	560		T5	220		T7	40
no_err	secret0	21086	1			T1	740		T4	480		T5	260
no_err	hw_cfg0	30790	1			T4	160		T5	280		T7	240
no_err	owner_sw_cfg	31316	1			T4	480		T5	280		T7	20
no_err	creator_sw_cfg	29728	1			T4	220		T5	660		T7	280
no_err	vendor_test	37130	1			T9	20		T4	460		T5	160

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
lc_or_oob_ignore	0	Excluded