Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.57	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33
Crosses	8	2	6	75.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
secret1_lock	2	0	2	100.00	100	1	1	2
sram_index	4	1	3	75.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sram_req_lock_cross	8	2	6	75.00	100	1	1	0

Summary for Variable secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret1_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39

1

T10

2

T312

3

T227

5

auto[1]

4

1

T227

2

T313

2

-

-

---

Summary for Variable sram_index

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	1	3	75.00

User Defined Bins for sram_index

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sram_key[0x0]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_key[0x1]	12	1			T312	1		T227	2		T313	3
sram_key[0x2]	15	1			T10	1		T312	1		T227	3
sram_key[0x3]	16	1			T10	1		T312	1		T227	2

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Summary for Cross sram_req_lock_cross

Samples crossed: sram_index secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	2	6	75.00	2

Automatically Generated Cross Bins for sram_req_lock_cross

Element holes

sram_index	secret1_lock	COUNT	AT LEAST	NUMBER	STATUS
[sram_key[0x0]]	*	--	--	2

Covered bins

sram_index	secret1_lock	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_key[0x1]	auto[0]	11	1			T312	1		T227	2		T313	2
sram_key[0x1]	auto[1]	1	1			T313	1		-	-		-	-
sram_key[0x2]	auto[0]	14	1			T10	1		T312	1		T227	2
sram_key[0x2]	auto[1]	1	1			T227	1		-	-		-	-
sram_key[0x3]	auto[0]	14	1			T10	1		T312	1		T227	1
sram_key[0x3]	auto[1]	2	1			T227	1		T313	1		-	-